diff --git a/CHANGELOG.md b/CHANGELOG.md index 01e60611e..6c80eafcc 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,5 +1,9 @@ # CHANGELOG +## [3.8.6] -- 2013-12-24 +- Fixed check ISA fields to include 32/64 in Zca and CMO tests. Note that the riscv-ctg CGFs have not been updated. +- Fixed check ISA fields in rv32e_m/B/src/ror-01 and rori-01 that listed I instead of E. Again, CGF has not been updated. + ## [3.8.5] -- 2013-12-23 - Renamed rv32e_unratified to rv32e_m because the E extension has been ratified January 2023 - Copied missing ebreak.S and ecall.S tests from rv32i_m/privilege to rv32e_m/privilege and update ISA for E diff --git a/riscv-test-suite/rv32e_m/B/src/ror-01.S b/riscv-test-suite/rv32e_m/B/src/ror-01.S index 3ae4e2dd8..d4591fa1c 100644 --- a/riscv-test-suite/rv32e_m/B/src/ror-01.S +++ b/riscv-test-suite/rv32e_m/B/src/ror-01.S @@ -32,13 +32,13 @@ RVTEST_CODE_BEGIN RVTEST_CASE(0,"//check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",ror) -RVTEST_CASE(1,"//check ISA:=regex(.*I.*Zbkb.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",ror) +RVTEST_CASE(1,"//check ISA:=regex(.*E.*Zbkb.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",ror) -RVTEST_CASE(2,"//check ISA:=regex(.*I.*Zk.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",ror) +RVTEST_CASE(2,"//check ISA:=regex(.*E.*Zk.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",ror) -RVTEST_CASE(3,"//check ISA:=regex(.*I.*Zkn.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",ror) +RVTEST_CASE(3,"//check ISA:=regex(.*E.*Zkn.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",ror) -RVTEST_CASE(4,"//check ISA:=regex(.*I.*Zks.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",ror) +RVTEST_CASE(4,"//check ISA:=regex(.*E.*Zks.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",ror) RVTEST_SIGBASE(x2,signature_x2_1) diff --git a/riscv-test-suite/rv32e_m/B/src/rori-01.S b/riscv-test-suite/rv32e_m/B/src/rori-01.S index 35f5c90fa..2976e5bdd 100644 --- a/riscv-test-suite/rv32e_m/B/src/rori-01.S +++ b/riscv-test-suite/rv32e_m/B/src/rori-01.S @@ -34,11 +34,11 @@ RVTEST_CASE(0,"//check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True;def TEST_CASE RVTEST_CASE(1,"//check ISA:=regex(.*E.*Zbkb.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",rori) -RVTEST_CASE(2,"//check ISA:=regex(.*.*Zk.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",rori) +RVTEST_CASE(2,"//check ISA:=regex(.*E.*Zk.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",rori) -RVTEST_CASE(3,"//check ISA:=regex(.*I.*Zkn.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",rori) +RVTEST_CASE(3,"//check ISA:=regex(.*E.*Zkn.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",rori) -RVTEST_CASE(4,"//check ISA:=regex(.*I.*Zks.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",rori) +RVTEST_CASE(4,"//check ISA:=regex(.*E.*Zks.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",rori) RVTEST_SIGBASE(x5,signature_x5_1) diff --git a/riscv-test-suite/rv32i_m/C/src/clbu-01.S b/riscv-test-suite/rv32i_m/C/src/clbu-01.S index afaac9684..0f248faa4 100644 --- a/riscv-test-suite/rv32i_m/C/src/clbu-01.S +++ b/riscv-test-suite/rv32i_m/C/src/clbu-01.S @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",clbu) +RVTEST_CASE(0,"//check ISA:=regex(.*32.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",clbu) RVTEST_SIGBASE(x1,signature_x1_1) diff --git a/riscv-test-suite/rv32i_m/C/src/clhu-01.S b/riscv-test-suite/rv32i_m/C/src/clhu-01.S index 2f86a9032..ad422a16b 100644 --- a/riscv-test-suite/rv32i_m/C/src/clhu-01.S +++ b/riscv-test-suite/rv32i_m/C/src/clhu-01.S @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",clhu) +RVTEST_CASE(0,"//check ISA:=regex(.*32.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",clhu) RVTEST_SIGBASE(x1,signature_x1_1) diff --git a/riscv-test-suite/rv32i_m/C/src/cmul-01.S b/riscv-test-suite/rv32i_m/C/src/cmul-01.S index 766a928b2..9d2089d98 100644 --- a/riscv-test-suite/rv32i_m/C/src/cmul-01.S +++ b/riscv-test-suite/rv32i_m/C/src/cmul-01.S @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*M.*Zca.*Zcb.*);def TEST_CASE_1=True;",cmul) +RVTEST_CASE(0,"//check ISA:=regex(.*32.*I.*M.*Zca.*Zcb.*);def TEST_CASE_1=True;",cmul) RVTEST_SIGBASE(x1,signature_x1_1) diff --git a/riscv-test-suite/rv32i_m/C/src/cnot-01.S b/riscv-test-suite/rv32i_m/C/src/cnot-01.S index f185b87b8..7e2771da2 100644 --- a/riscv-test-suite/rv32i_m/C/src/cnot-01.S +++ b/riscv-test-suite/rv32i_m/C/src/cnot-01.S @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",cnot) +RVTEST_CASE(0,"//check ISA:=regex(.*32.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",cnot) RVTEST_SIGBASE(x1,signature_x1_1) diff --git a/riscv-test-suite/rv32i_m/C/src/csb-01.S b/riscv-test-suite/rv32i_m/C/src/csb-01.S index 55fe9c3a5..f3d2b1b2f 100644 --- a/riscv-test-suite/rv32i_m/C/src/csb-01.S +++ b/riscv-test-suite/rv32i_m/C/src/csb-01.S @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",csb) +RVTEST_CASE(0,"//check ISA:=regex(.*32.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",csb) RVTEST_SIGBASE(x1,signature_x1_1) diff --git a/riscv-test-suite/rv32i_m/C/src/csext.b-01.S b/riscv-test-suite/rv32i_m/C/src/csext.b-01.S index 3289b2507..92047d0e7 100644 --- a/riscv-test-suite/rv32i_m/C/src/csext.b-01.S +++ b/riscv-test-suite/rv32i_m/C/src/csext.b-01.S @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*.Zbb.*);def TEST_CASE_1=True;",csext.b) +RVTEST_CASE(0,"//check ISA:=regex(.*32.*I.*Zca.*Zcb.*.Zbb.*);def TEST_CASE_1=True;",csext.b) RVTEST_SIGBASE(x1,signature_x1_1) diff --git a/riscv-test-suite/rv32i_m/C/src/csext.h-01.S b/riscv-test-suite/rv32i_m/C/src/csext.h-01.S index 778001bdf..af62913d9 100644 --- a/riscv-test-suite/rv32i_m/C/src/csext.h-01.S +++ b/riscv-test-suite/rv32i_m/C/src/csext.h-01.S @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*.Zbb.*);def TEST_CASE_1=True;",csext.h) +RVTEST_CASE(0,"//check ISA:=regex(.*32.*I.*Zca.*Zcb.*.Zbb.*);def TEST_CASE_1=True;",csext.h) RVTEST_SIGBASE(x1,signature_x1_1) diff --git a/riscv-test-suite/rv32i_m/C/src/csh-01.S b/riscv-test-suite/rv32i_m/C/src/csh-01.S index 92827c6de..4e2ae8cff 100644 --- a/riscv-test-suite/rv32i_m/C/src/csh-01.S +++ b/riscv-test-suite/rv32i_m/C/src/csh-01.S @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",csh) +RVTEST_CASE(0,"//check ISA:=regex(.*32.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",csh) RVTEST_SIGBASE(x1,signature_x1_1) diff --git a/riscv-test-suite/rv32i_m/C/src/czext.b-01.S b/riscv-test-suite/rv32i_m/C/src/czext.b-01.S index cf6275897..ce122151d 100644 --- a/riscv-test-suite/rv32i_m/C/src/czext.b-01.S +++ b/riscv-test-suite/rv32i_m/C/src/czext.b-01.S @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",czext.b) +RVTEST_CASE(0,"//check ISA:=regex(.*32.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",czext.b) RVTEST_SIGBASE(x1,signature_x1_1) diff --git a/riscv-test-suite/rv32i_m/C/src/czext.h-01.S b/riscv-test-suite/rv32i_m/C/src/czext.h-01.S index a250968a5..77b3b3c85 100644 --- a/riscv-test-suite/rv32i_m/C/src/czext.h-01.S +++ b/riscv-test-suite/rv32i_m/C/src/czext.h-01.S @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*.Zbb.*);def TEST_CASE_1=True;",czext.h) +RVTEST_CASE(0,"//check ISA:=regex(.*32.*I.*Zca.*Zcb.*.Zbb.*);def TEST_CASE_1=True;",czext.h) RVTEST_SIGBASE(x1,signature_x1_1) diff --git a/riscv-test-suite/rv32i_m/CMO/src/cbo.zero-01.S b/riscv-test-suite/rv32i_m/CMO/src/cbo.zero-01.S index 460ea1e81..4fbfdf2e7 100644 --- a/riscv-test-suite/rv32i_m/CMO/src/cbo.zero-01.S +++ b/riscv-test-suite/rv32i_m/CMO/src/cbo.zero-01.S @@ -16,11 +16,11 @@ // SPDX-License-Identifier: BSD-3-Clause // ----------- // -// This assembly file tests the cbo.zero instruction of the RISC-V RV32ZicbozZicsr extension for the cbozero covergroup. +// This assembly file tests the cbo.zero instruction of the RISC-V RV32Zicboz extension for the cbozero covergroup. // #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV32IZicbozZicsr") +RVTEST_ISA("RV32IZicsr_Zicboz") .section .text.init .globl rvtest_entry_point @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zicboz.*Zicsr.*);def TEST_CASE_1=True;",cbozero) +RVTEST_CASE(0,"//check ISA:=regex(.*32.*I.*Zicsr.*Zicboz.*);def TEST_CASE_1=True;",cbozero) RVTEST_SIGBASE(x2,signature_x2_1) diff --git a/riscv-test-suite/rv64i_m/C/src/clbu-01.S b/riscv-test-suite/rv64i_m/C/src/clbu-01.S index fbd3c4300..9009cbed7 100644 --- a/riscv-test-suite/rv64i_m/C/src/clbu-01.S +++ b/riscv-test-suite/rv64i_m/C/src/clbu-01.S @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",clbu) +RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",clbu) RVTEST_SIGBASE(x1,signature_x1_1) diff --git a/riscv-test-suite/rv64i_m/C/src/clh-01.S b/riscv-test-suite/rv64i_m/C/src/clh-01.S index 398e7eb53..724f1f905 100644 --- a/riscv-test-suite/rv64i_m/C/src/clh-01.S +++ b/riscv-test-suite/rv64i_m/C/src/clh-01.S @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",clh) +RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",clh) RVTEST_SIGBASE(x1,signature_x1_1) diff --git a/riscv-test-suite/rv64i_m/C/src/clhu-01.S b/riscv-test-suite/rv64i_m/C/src/clhu-01.S index 048009253..1a3c57f6e 100644 --- a/riscv-test-suite/rv64i_m/C/src/clhu-01.S +++ b/riscv-test-suite/rv64i_m/C/src/clhu-01.S @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",clhu) +RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",clhu) RVTEST_SIGBASE(x1,signature_x1_1) diff --git a/riscv-test-suite/rv64i_m/C/src/cmul-01.S b/riscv-test-suite/rv64i_m/C/src/cmul-01.S index 291790454..a11cb8b4c 100644 --- a/riscv-test-suite/rv64i_m/C/src/cmul-01.S +++ b/riscv-test-suite/rv64i_m/C/src/cmul-01.S @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*M.*Zca.*Zcb.*);def TEST_CASE_1=True;",cmul) +RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*M.*Zca.*Zcb.*);def TEST_CASE_1=True;",cmul) RVTEST_SIGBASE(x1,signature_x1_1) diff --git a/riscv-test-suite/rv64i_m/C/src/cnot-01.S b/riscv-test-suite/rv64i_m/C/src/cnot-01.S index 80a464616..e6a81b823 100644 --- a/riscv-test-suite/rv64i_m/C/src/cnot-01.S +++ b/riscv-test-suite/rv64i_m/C/src/cnot-01.S @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",cnot) +RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",cnot) RVTEST_SIGBASE(x1,signature_x1_1) diff --git a/riscv-test-suite/rv64i_m/C/src/csb-01.S b/riscv-test-suite/rv64i_m/C/src/csb-01.S index a6d0b7a10..f2e0b9ed3 100644 --- a/riscv-test-suite/rv64i_m/C/src/csb-01.S +++ b/riscv-test-suite/rv64i_m/C/src/csb-01.S @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",csb) +RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",csb) RVTEST_SIGBASE(x1,signature_x1_1) diff --git a/riscv-test-suite/rv64i_m/C/src/csext.b-01.S b/riscv-test-suite/rv64i_m/C/src/csext.b-01.S index ddad7072a..388067bcb 100644 --- a/riscv-test-suite/rv64i_m/C/src/csext.b-01.S +++ b/riscv-test-suite/rv64i_m/C/src/csext.b-01.S @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*.Zbb.*);def TEST_CASE_1=True;",csext.b) +RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*Zca.*Zcb.*.Zbb.*);def TEST_CASE_1=True;",csext.b) RVTEST_SIGBASE(x1,signature_x1_1) diff --git a/riscv-test-suite/rv64i_m/C/src/csext.h-01.S b/riscv-test-suite/rv64i_m/C/src/csext.h-01.S index 9d5cb95ff..c9db2e8d2 100644 --- a/riscv-test-suite/rv64i_m/C/src/csext.h-01.S +++ b/riscv-test-suite/rv64i_m/C/src/csext.h-01.S @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*.Zbb.*);def TEST_CASE_1=True;",csext.h) +RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*Zca.*Zcb.*.Zbb.*);def TEST_CASE_1=True;",csext.h) RVTEST_SIGBASE(x1,signature_x1_1) diff --git a/riscv-test-suite/rv64i_m/C/src/csh-01.S b/riscv-test-suite/rv64i_m/C/src/csh-01.S index 00a6f756c..e512cb809 100644 --- a/riscv-test-suite/rv64i_m/C/src/csh-01.S +++ b/riscv-test-suite/rv64i_m/C/src/csh-01.S @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",csh) +RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",csh) RVTEST_SIGBASE(x1,signature_x1_1) diff --git a/riscv-test-suite/rv64i_m/C/src/czext.b-01.S b/riscv-test-suite/rv64i_m/C/src/czext.b-01.S index 4755d29b8..98da2d4e4 100644 --- a/riscv-test-suite/rv64i_m/C/src/czext.b-01.S +++ b/riscv-test-suite/rv64i_m/C/src/czext.b-01.S @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",czext.b) +RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",czext.b) RVTEST_SIGBASE(x1,signature_x1_1) diff --git a/riscv-test-suite/rv64i_m/C/src/czext.h-01.S b/riscv-test-suite/rv64i_m/C/src/czext.h-01.S index 689cc31e9..bb5336422 100644 --- a/riscv-test-suite/rv64i_m/C/src/czext.h-01.S +++ b/riscv-test-suite/rv64i_m/C/src/czext.h-01.S @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*.Zbb.*);def TEST_CASE_1=True;",czext.h) +RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*Zca.*Zcb.*.Zbb.*);def TEST_CASE_1=True;",czext.h) RVTEST_SIGBASE(x1,signature_x1_1) diff --git a/riscv-test-suite/rv64i_m/C/src/czext.w-01.S b/riscv-test-suite/rv64i_m/C/src/czext.w-01.S index a4a710048..fd17ec784 100644 --- a/riscv-test-suite/rv64i_m/C/src/czext.w-01.S +++ b/riscv-test-suite/rv64i_m/C/src/czext.w-01.S @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*.Zba.*);def TEST_CASE_1=True;",czext.w) +RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*Zca.*Zcb.*.Zba.*);def TEST_CASE_1=True;",czext.w) RVTEST_SIGBASE(x1,signature_x1_1) diff --git a/riscv-test-suite/rv64i_m/CMO/src/cbo.zero-01.S b/riscv-test-suite/rv64i_m/CMO/src/cbo.zero-01.S index 841789229..cc66623c1 100644 --- a/riscv-test-suite/rv64i_m/CMO/src/cbo.zero-01.S +++ b/riscv-test-suite/rv64i_m/CMO/src/cbo.zero-01.S @@ -16,11 +16,11 @@ // SPDX-License-Identifier: BSD-3-Clause // ----------- // -// This assembly file tests the cbo.zero instruction of the RISC-V RV64ZicbozZicsr extension for the cbozero covergroup. +// This assembly file tests the cbo.zero instruction of the RISC-V RV64ZicsrZicboz extension for the cbozero covergroup. // #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV64IZicbozZicsr") +RVTEST_ISA("RV64IZicboz") .section .text.init .globl rvtest_entry_point @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zicboz.*Zicsr.*);def TEST_CASE_1=True;",cbozero) +RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*Zicsr.*Zicboz.*);def TEST_CASE_1=True;",cbozero) RVTEST_SIGBASE(x3,signature_x3_1)