diff --git a/CHANGELOG.md b/CHANGELOG.md
index 6c80eafcc..6846c0469 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,5 +1,8 @@
 # CHANGELOG
 
+## [3.8.7] -- 2024-01-02
+- Update satp initialization macro
+
 ## [3.8.6] -- 2013-12-24
 - Fixed check ISA fields to include 32/64 in Zca and CMO tests.  Note that the riscv-ctg CGFs have not been updated.
 - Fixed check ISA fields in rv32e_m/B/src/ror-01 and rori-01 that listed I instead of E. Again, CGF has not been updated.
diff --git a/riscv-test-suite/env/arch_test.h b/riscv-test-suite/env/arch_test.h
index 2eb0ab436..bfb74b4b7 100644
--- a/riscv-test-suite/env/arch_test.h
+++ b/riscv-test-suite/env/arch_test.h
@@ -996,6 +996,13 @@ init_\__MODE__\()edeleg:
 init_\__MODE__\()satp:
 .ifnc \__MODE__ , M                      // if S or VS mode **FIXME: fixed offset frm trapreg_sv?
         LA(     T4, rvtest_\__MODE__\()root_pg_tbl)     // rplc xsatp w/ identity-mapped pg table 
+        srli T4, T4, 12
+      #if (XLEN==32)
+        LI(T3, SATP32_MODE)
+      #else
+        LI(T3, (SATP64_MODE) & (SATP_MODE_SV39 << 60))
+      #endif
+        or      T4, T4, T3
         csrrw   T4, CSR_XSATP, T4
         SREG    T4, xsatp_sv_off(T1)
 .endif