From 8e62b757fd500cb8cd3a2557f46dea4dda647a14 Mon Sep 17 00:00:00 2001 From: Alexander Richardson Date: Fri, 30 Aug 2024 07:15:47 +0100 Subject: [PATCH] Update charter based on latest discussions Signed-off-by: Alexander Richardson --- charter.adoc | 39 +++++++++++++++++---------------------- 1 file changed, 17 insertions(+), 22 deletions(-) diff --git a/charter.adoc b/charter.adoc index 47842ae..bfe38fc 100644 --- a/charter.adoc +++ b/charter.adoc @@ -10,32 +10,27 @@ Given the commercial demonstration of the effectiveness of CHERI, multiple vendo == Objectives -To create a standardization task group to specify three specifications: +To create a standardization task group to create the following specifications: -* Usermode CHERI RV64 and RV32 extensions - -* Privileged CHERI RV64 and RV32 extensions - -* CHERI RV64 and RV32 ABIs +- Usermode CHERI RV64 and RV32 extensions +- Privileged CHERI RV64 and RV32 extensions +- CHERI RVA23[US]64 compatibility +- CHERI RV64 and RV32 ABIs in conjunction with the psABI TG This will include specifying requirements for: -* Encoding 128-bit capabilities over a 64-bit baseline ISA; encoding 64-bit capabilities over a 32-bit baseline ISA - -* Tagged memory to support capability validity tags - -* CHERI extensions to the RV64 and RV32 ISA to support efficient temporal memory safety, initially for C/C++ memory protection - -* ABI details including register conventions, calling conventions, and C/C++ types - -* CHERI features to support safe, capability-aware exception handling - -* CHERI features to support compartmentalization models +- Encoding 128-bit capabilities over a 64-bit baseline ISA; encoding 64-bit capabilities over a 32-bit baseline ISA +- Tagged memory to support capability validity tags +- CHERI extensions to the RV64 and RV32 ISA to support efficient temporal memory safety, initially for C/C++ memory protection +- ABI details including register conventions, calling conventions, and C/C++ types +- CHERI features to support safe, capability-aware exception handling +- CHERI features to support compartmentalization models +- Ensure RV32 can support the CHERIoT software model The task group will coordinate efforts to: -* Update the CHERI-RISC-V Sail model to the most recent baseline RISC-V model - -* Develop a CHERI-RISC-V test suite - -* Add support for at least one compiler to target CHERI-RISC-V as specified (LLVM support exists already for the current academic prototype) +- Update the CHERI-RISC-V Sail model to the most recent baseline RISC-V model +- Develop a CHERI-RISC-V test suite +- Add support for at least one compiler to target CHERI-RISC-V as specified (LLVM support exists already for the current academic prototype) +- Demonstrate addition of CHERI support to POSIX and embedded operating systems +- Engage with upstream OS and compiler vendors to contribute these changes