From d957d65f5089f2f1c930259b155c3e2654c1be13 Mon Sep 17 00:00:00 2001
From: Taichi Ishitani <taichi730@gmail.com>
Date: Sun, 29 Dec 2024 00:09:19 +0900
Subject: [PATCH] update supported ruby version

(refs: rggen/rggen#226)
---
 .github/workflows/ci.yml                      |  2 +-
 lib/rggen/systemverilog/common/feature.rb     | 10 +++----
 lib/rggen/systemverilog/common/utility.rb     |  4 +--
 .../common/utility/structure_definition.rb    |  4 +--
 lib/rggen/systemverilog/ral/bit_field/type.rb | 10 +++----
 lib/rggen/systemverilog/ral/feature.rb        | 10 +++----
 .../rtl/bit_field/type/custom.rb              | 26 +++++++++----------
 .../rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb   | 12 ++++-----
 .../rtl/bit_field/type/ro_rotrg.rb            |  6 ++---
 .../systemverilog/rtl/bit_field/type/rohw.rb  | 10 +++----
 .../rtl/bit_field/type/row0trg_row1trg.rb     |  8 +++---
 .../rtl/bit_field/type/rowo_rowotrg.rb        | 12 ++++-----
 .../rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb   |  8 +++---
 .../rtl/bit_field/type/rw_rwtrg_w1.rb         |  8 +++---
 .../systemverilog/rtl/bit_field/type/rwc.rb   |  6 ++---
 .../rtl/bit_field/type/rwe_rwl.rb             |  6 ++---
 .../systemverilog/rtl/bit_field/type/rwhw.rb  | 10 +++----
 .../systemverilog/rtl/bit_field/type/rws.rb   |  6 ++---
 .../type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb |  4 +--
 .../rtl/bit_field/type/w0t_w1t.rb             |  4 +--
 .../rtl/bit_field/type/w0trg_w1trg.rb         |  4 +--
 .../rtl/bit_field/type/wo_wo1_wotrg.rb        |  6 ++---
 .../rtl/bit_field/type/wrc_wrs.rb             |  4 +--
 lib/rggen/systemverilog/rtl/feature.rb        | 26 ++++++++-----------
 .../systemverilog/rtl_package/feature.rb      |  6 ++---
 .../rtl_package/register/sv_rtl_package.rb    |  4 +--
 rggen-systemverilog.gemspec                   |  2 +-
 27 files changed, 106 insertions(+), 112 deletions(-)

diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index fdc01ea..ef1daed 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -8,7 +8,7 @@ jobs:
 
     strategy:
       matrix:
-        ruby: ['3.3', '3.2', '3.1', '3.0']
+        ruby: ['3.4', '3.3', '3.2', '3.1']
         frozen_string_literal: ['yes', 'no']
 
     env:
diff --git a/lib/rggen/systemverilog/common/feature.rb b/lib/rggen/systemverilog/common/feature.rb
index 9f306b6..b219662 100644
--- a/lib/rggen/systemverilog/common/feature.rb
+++ b/lib/rggen/systemverilog/common/feature.rb
@@ -38,9 +38,9 @@ def post_initialize
           @package_imports = Hash.new { |h, k| h[k] = [] }
         end
 
-        def define_entity(context, name, args, &block)
+        def define_entity(context, name, args, &)
           layer, attributes = parse_entity_arguments(args)
-          entity = create_entity(context, name, attributes, &block)
+          entity = create_entity(context, name, attributes, &)
           add_entity(context, entity, name, layer)
         end
 
@@ -56,9 +56,9 @@ def parse_entity_arguments(args)
           end
         end
 
-        def create_entity(context, name, attributes, &block)
-          merged_attributes = { name: name }.merge(Hash(attributes))
-          __send__(context.method_name, context.entity_type, merged_attributes, &block)
+        def create_entity(context, name, attributes, &)
+          merged_attributes = { name: }.merge(Hash(attributes))
+          __send__(context.method_name, context.entity_type, merged_attributes, &)
         end
 
         def add_entity(context, entity, name, layer)
diff --git a/lib/rggen/systemverilog/common/utility.rb b/lib/rggen/systemverilog/common/utility.rb
index 1c96ca5..9223884 100644
--- a/lib/rggen/systemverilog/common/utility.rb
+++ b/lib/rggen/systemverilog/common/utility.rb
@@ -92,7 +92,7 @@ def width_cast(expression, width)
         end
 
         def argument(name, attribute = {})
-          DataObject.new(:argument, attribute.merge(name: name)).declaration
+          DataObject.new(:argument, attribute.merge(name:)).declaration
         end
 
         {
@@ -103,7 +103,7 @@ def argument(name, attribute = {})
           package_definition: PackageDefinition
         }.each do |method_name, definition|
           define_method(method_name) do |name, attributes = {}, &block|
-            definition.new(attributes.merge(name: name), &block).to_code
+            definition.new(attributes.merge(name:), &block).to_code
           end
         end
       end
diff --git a/lib/rggen/systemverilog/common/utility/structure_definition.rb b/lib/rggen/systemverilog/common/utility/structure_definition.rb
index c393a22..848b9fb 100644
--- a/lib/rggen/systemverilog/common/utility/structure_definition.rb
+++ b/lib/rggen/systemverilog/common/utility/structure_definition.rb
@@ -7,9 +7,9 @@ module Utility
         class StructureDefinition < Core::Utility::CodeUtility::StructureDefinition
           include Core::Utility::AttributeSetter
 
-          def initialize(default_attributes = {}, &block)
+          def initialize(default_attributes = {}, &)
             apply_attributes(**default_attributes)
-            super(&block)
+            super(&)
           end
 
           private
diff --git a/lib/rggen/systemverilog/ral/bit_field/type.rb b/lib/rggen/systemverilog/ral/bit_field/type.rb
index 37c7057..55fcd15 100644
--- a/lib/rggen/systemverilog/ral/bit_field/type.rb
+++ b/lib/rggen/systemverilog/ral/bit_field/type.rb
@@ -4,12 +4,12 @@
   sv_ral do
     base_feature do
       define_helpers do
-        def access(access_type = nil, &block)
-          attribute_accessor('@access', access_type, &block)
+        def access(access_type = nil, &)
+          attribute_accessor('@access', access_type, &)
         end
 
-        def model_name(name = nil, &block)
-          attribute_accessor('@model_name', name, &block)
+        def model_name(name = nil, &)
+          attribute_accessor('@model_name', name, &)
         end
 
         private
@@ -28,7 +28,7 @@ def attribute_accessor(variable_name, value, &block)
       build do
         variable :ral_model, {
           name: bit_field.name, data_type: model_name,
-          array_size: array_size, random: true
+          array_size:, random: true
         }
       end
 
diff --git a/lib/rggen/systemverilog/ral/feature.rb b/lib/rggen/systemverilog/ral/feature.rb
index 6777a5c..dd57347 100644
--- a/lib/rggen/systemverilog/ral/feature.rb
+++ b/lib/rggen/systemverilog/ral/feature.rb
@@ -6,14 +6,12 @@ module RAL
       class Feature < Common::Feature
         private
 
-        def create_variable(_, attributes, &block)
-          DataObject.new(
-            :variable, attributes.merge(array_format: :unpacked), &block
-          )
+        def create_variable(_, attributes, &)
+          DataObject.new(:variable, attributes.merge(array_format: :unpacked), &)
         end
 
-        def create_parameter(_, attributes, &block)
-          DataObject.new(:parameter, attributes, &block)
+        def create_parameter(_, attributes, &)
+          DataObject.new(:parameter, attributes, &)
         end
 
         define_entity :variable, :create_variable, :variable, -> { component.parent }
diff --git a/lib/rggen/systemverilog/rtl/bit_field/type/custom.rb b/lib/rggen/systemverilog/rtl/bit_field/type/custom.rb
index 7a494f2..a223743 100644
--- a/lib/rggen/systemverilog/rtl/bit_field/type/custom.rb
+++ b/lib/rggen/systemverilog/rtl/bit_field/type/custom.rb
@@ -5,47 +5,47 @@
     build do
       if external_read_data?
         input :value_in, {
-          name: "i_#{full_name}", width: width,
-          array_size: array_size, array_format: array_port_format
+          name: "i_#{full_name}", width:,
+          array_size:, array_format: array_port_format
         }
       else
         output :value_out, {
-          name: "o_#{full_name}", width: width,
-          array_size: array_size, array_format: array_port_format
+          name: "o_#{full_name}", width:,
+          array_size:, array_format: array_port_format
         }
       end
       if bit_field.hw_write?
         input :hw_write_enable, {
           name: "i_#{full_name}_hw_write_enable", width: 1,
-          array_size: array_size, array_format: array_port_format
+          array_size:, array_format: array_port_format
         }
         input :hw_write_data, {
-          name: "i_#{full_name}_hw_write_data", width: width,
-          array_size: array_size, array_format: array_port_format
+          name: "i_#{full_name}_hw_write_data", width:,
+          array_size:, array_format: array_port_format
         }
       end
       if bit_field.hw_set?
         input :hw_set, {
-          name: "i_#{full_name}_hw_set", width: width,
-          array_size: array_size, array_format: array_port_format
+          name: "i_#{full_name}_hw_set", width:,
+          array_size:, array_format: array_port_format
         }
       end
       if bit_field.hw_clear?
         input :hw_clear, {
-          name: "i_#{full_name}_hw_clear", width: width,
-          array_size: array_size, array_format: array_port_format
+          name: "i_#{full_name}_hw_clear", width:,
+          array_size:, array_format: array_port_format
         }
       end
       if bit_field.write_trigger?
         output :write_trigger, {
           name: "o_#{full_name}_write_trigger", width: 1,
-          array_size: array_size, array_format: array_port_format
+          array_size:, array_format: array_port_format
         }
       end
       if bit_field.read_trigger?
         output :read_trigger, {
           name: "o_#{full_name}_read_trigger", width: 1,
-          array_size: array_size, array_format: array_port_format
+          array_size:, array_format: array_port_format
         }
       end
     end
diff --git a/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb b/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb
index c72b0a4..c51f8f4 100644
--- a/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb
+++ b/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb
@@ -4,17 +4,17 @@
   sv_rtl do
     build do
       input :set, {
-        name: "i_#{full_name}_set", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "i_#{full_name}_set", width:,
+        array_size:, array_format: array_port_format
       }
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:,
+        array_size:, array_format: array_port_format
       }
       if bit_field.reference?
         output :value_unmasked, {
-          name: "o_#{full_name}_unmasked", width: width,
-          array_size: array_size, array_format: array_port_format
+          name: "o_#{full_name}_unmasked", width:,
+          array_size:, array_format: array_port_format
         }
       end
     end
diff --git a/lib/rggen/systemverilog/rtl/bit_field/type/ro_rotrg.rb b/lib/rggen/systemverilog/rtl/bit_field/type/ro_rotrg.rb
index 5446bde..45378d3 100644
--- a/lib/rggen/systemverilog/rtl/bit_field/type/ro_rotrg.rb
+++ b/lib/rggen/systemverilog/rtl/bit_field/type/ro_rotrg.rb
@@ -5,14 +5,14 @@
     build do
       unless bit_field.reference?
         input :value_in, {
-          name: "i_#{full_name}", width: width,
-          array_size: array_size, array_format: array_port_format
+          name: "i_#{full_name}", width:,
+          array_size:, array_format: array_port_format
         }
       end
       if rotrg?
         output :read_trigger, {
           name: "o_#{full_name}_read_trigger", width: 1,
-          array_size: array_size, array_format: array_port_format
+          array_size:, array_format: array_port_format
         }
       end
     end
diff --git a/lib/rggen/systemverilog/rtl/bit_field/type/rohw.rb b/lib/rggen/systemverilog/rtl/bit_field/type/rohw.rb
index 6c92f8e..8323bdf 100644
--- a/lib/rggen/systemverilog/rtl/bit_field/type/rohw.rb
+++ b/lib/rggen/systemverilog/rtl/bit_field/type/rohw.rb
@@ -6,16 +6,16 @@
       unless bit_field.reference?
         input :valid, {
           name: "i_#{full_name}_valid", width: 1,
-          array_size: array_size, array_format: array_port_format
+          array_size:, array_format: array_port_format
         }
       end
       input :value_in, {
-        name: "i_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "i_#{full_name}", width:,
+        array_size:, array_format: array_port_format
       }
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:,
+        array_size:, array_format: array_port_format
       }
     end
 
diff --git a/lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.rb b/lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.rb
index 2a694d6..267bddf 100644
--- a/lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.rb
+++ b/lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.rb
@@ -5,13 +5,13 @@
     build do
       unless bit_field.reference?
         input :value_in, {
-          name: "i_#{full_name}", width: width,
-          array_size: array_size, array_format: array_port_format
+          name: "i_#{full_name}", width:,
+          array_size:, array_format: array_port_format
         }
       end
       output :trigger, {
-        name: "o_#{full_name}_trigger", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}_trigger", width:,
+        array_size:, array_format: array_port_format
       }
     end
 
diff --git a/lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.rb b/lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.rb
index 710a937..fbfdcf2 100644
--- a/lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.rb
+++ b/lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.rb
@@ -4,23 +4,23 @@
   sv_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:,
+        array_size:, array_format: array_port_format
       }
       unless bit_field.reference?
         input :value_in, {
-          name: "i_#{full_name}", width: width,
-          array_size: array_size, array_format: array_port_format
+          name: "i_#{full_name}", width:,
+          array_size:, array_format: array_port_format
         }
       end
       if rowotrg?
         output :write_trigger, {
           name: "o_#{full_name}_write_trigger", width: 1,
-          array_size: array_size, array_format: array_port_format
+          array_size:, array_format: array_port_format
         }
         output :read_trigger, {
           name: "o_#{full_name}_read_trigger", width: 1,
-          array_size: array_size, array_format: array_port_format
+          array_size:, array_format: array_port_format
         }
       end
     end
diff --git a/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb b/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb
index 08b35b2..31cea94 100644
--- a/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb
+++ b/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb
@@ -4,12 +4,12 @@
   sv_rtl do
     build do
       input :clear, {
-        name: "i_#{full_name}_clear", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "i_#{full_name}_clear", width:,
+        array_size:, array_format: array_port_format
       }
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:,
+        array_size:, array_format: array_port_format
       }
     end
 
diff --git a/lib/rggen/systemverilog/rtl/bit_field/type/rw_rwtrg_w1.rb b/lib/rggen/systemverilog/rtl/bit_field/type/rw_rwtrg_w1.rb
index df63f7c..a0178a3 100644
--- a/lib/rggen/systemverilog/rtl/bit_field/type/rw_rwtrg_w1.rb
+++ b/lib/rggen/systemverilog/rtl/bit_field/type/rw_rwtrg_w1.rb
@@ -4,17 +4,17 @@
   sv_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:,
+        array_size:, array_format: array_port_format
       }
       if rwtrg?
         output :write_trigger, {
           name: "o_#{full_name}_write_trigger", width: 1,
-          array_size: array_size, array_format: array_port_format
+          array_size:, array_format: array_port_format
         }
         output :read_trigger, {
           name: "o_#{full_name}_read_trigger", width: 1,
-          array_size: array_size, array_format: array_port_format
+          array_size:, array_format: array_port_format
         }
       end
     end
diff --git a/lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb b/lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb
index 5fb3516..3130bdd 100644
--- a/lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb
+++ b/lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb
@@ -6,12 +6,12 @@
       unless bit_field.reference?
         input :clear, {
           name: "i_#{full_name}_clear", width: 1,
-          array_size: array_size, array_format: array_port_format
+          array_size:, array_format: array_port_format
         }
       end
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:,
+        array_size:, array_format: array_port_format
       }
     end
 
diff --git a/lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.rb b/lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.rb
index 16d7319..fe6a353 100644
--- a/lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.rb
+++ b/lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.rb
@@ -6,12 +6,12 @@
       unless bit_field.reference?
         input :control, {
           name: "i_#{full_name}_#{enable_or_lock}", width: 1,
-          array_size: array_size, array_format: array_port_format
+          array_size:, array_format: array_port_format
         }
       end
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:,
+        array_size:, array_format: array_port_format
       }
     end
 
diff --git a/lib/rggen/systemverilog/rtl/bit_field/type/rwhw.rb b/lib/rggen/systemverilog/rtl/bit_field/type/rwhw.rb
index 3721342..b310d35 100644
--- a/lib/rggen/systemverilog/rtl/bit_field/type/rwhw.rb
+++ b/lib/rggen/systemverilog/rtl/bit_field/type/rwhw.rb
@@ -6,16 +6,16 @@
       unless bit_field.reference?
         input :valid, {
           name: "i_#{full_name}_valid", width: 1,
-          array_size: array_size, array_format: array_port_format
+          array_size:, array_format: array_port_format
         }
       end
       input :value_in, {
-        name: "i_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "i_#{full_name}", width:,
+        array_size:, array_format: array_port_format
       }
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:,
+        array_size:, array_format: array_port_format
       }
     end
 
diff --git a/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb b/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb
index c2ea8aa..a6d3d6d 100644
--- a/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb
+++ b/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb
@@ -6,12 +6,12 @@
       unless bit_field.reference?
         input :set, {
           name: "i_#{full_name}_set", width: 1,
-          array_size: array_size, array_format: array_port_format
+          array_size:, array_format: array_port_format
         }
       end
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:,
+        array_size:, array_format: array_port_format
       }
     end
 
diff --git a/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb b/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb
index d4451e9..0dd37fc 100644
--- a/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb
+++ b/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb
@@ -6,8 +6,8 @@
   sv_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:,
+        array_size:, array_format: array_port_format
       }
     end
 
diff --git a/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb b/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb
index fceb7ed..d43ba0d 100644
--- a/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb
+++ b/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb
@@ -4,8 +4,8 @@
   sv_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:,
+        array_size:, array_format: array_port_format
       }
     end
 
diff --git a/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb b/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb
index 5b313c9..9aca036 100644
--- a/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb
+++ b/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb
@@ -4,8 +4,8 @@
   sv_rtl do
     build do
       output :trigger, {
-        name: "o_#{full_name}_trigger", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}_trigger", width:,
+        array_size:, array_format: array_port_format
       }
     end
 
diff --git a/lib/rggen/systemverilog/rtl/bit_field/type/wo_wo1_wotrg.rb b/lib/rggen/systemverilog/rtl/bit_field/type/wo_wo1_wotrg.rb
index 6039d4e..a4264df 100644
--- a/lib/rggen/systemverilog/rtl/bit_field/type/wo_wo1_wotrg.rb
+++ b/lib/rggen/systemverilog/rtl/bit_field/type/wo_wo1_wotrg.rb
@@ -4,13 +4,13 @@
   sv_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:,
+        array_size:, array_format: array_port_format
       }
       if wotrg?
         output :write_trigger, {
           name: "o_#{full_name}_write_trigger", width: 1,
-          array_size: array_size, array_format: array_port_format
+          array_size:, array_format: array_port_format
         }
       end
     end
diff --git a/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.rb b/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.rb
index f651102..69525b9 100644
--- a/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.rb
+++ b/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.rb
@@ -4,8 +4,8 @@
   sv_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:,
+        array_size:, array_format: array_port_format
       }
     end
 
diff --git a/lib/rggen/systemverilog/rtl/feature.rb b/lib/rggen/systemverilog/rtl/feature.rb
index c88281a..fe2cd67 100644
--- a/lib/rggen/systemverilog/rtl/feature.rb
+++ b/lib/rggen/systemverilog/rtl/feature.rb
@@ -6,32 +6,28 @@ module RTL
       class Feature < Common::Feature
         private
 
-        def create_variable(data_type, attributes, &block)
-          DataObject.new(
-            :variable, attributes.merge(data_type: data_type), &block
-          )
+        def create_variable(data_type, attributes, &)
+          DataObject.new(:variable, attributes.merge(data_type:), &)
         end
 
-        def create_if_instance(_, attributes, &block)
-          InterfaceInstance.new(attributes, &block)
+        def create_if_instance(_, attributes, &)
+          InterfaceInstance.new(attributes, &)
         end
 
-        def create_port(direction, attributes, &block)
+        def create_port(direction, attributes, &)
           attributes =
             { data_type: 'logic' }
               .merge(attributes)
-              .merge(direction: direction)
-          DataObject.new(:argument, attributes, &block)
+              .merge(direction:)
+          DataObject.new(:argument, attributes, &)
         end
 
-        def create_if_port(_, attributes, &block)
-          InterfacePort.new(attributes, &block)
+        def create_if_port(_, attributes, &)
+          InterfacePort.new(attributes, &)
         end
 
-        def create_parameter(parameter_type, attributes, &block)
-          DataObject.new(
-            :parameter, attributes.merge(parameter_type: parameter_type), &block
-          )
+        def create_parameter(parameter_type, attributes, &)
+          DataObject.new(:parameter, attributes.merge(parameter_type:), &)
         end
 
         define_entity :logic, :create_variable, :variable, -> { component }
diff --git a/lib/rggen/systemverilog/rtl_package/feature.rb b/lib/rggen/systemverilog/rtl_package/feature.rb
index a5f4c26..5b3c648 100644
--- a/lib/rggen/systemverilog/rtl_package/feature.rb
+++ b/lib/rggen/systemverilog/rtl_package/feature.rb
@@ -10,14 +10,14 @@ def full_name(separator = '_')
           component.full_name(separator)
         end
 
-        def create_parameter(parameter_type, attributes, &block)
+        def create_parameter(parameter_type, attributes, &)
           attributes =
             attributes.merge(
-              parameter_type: parameter_type, array_format: :unpacked,
+              parameter_type:, array_format: :unpacked,
               name: attributes[:name].upcase
             )
           DataObject.new(
-            :parameter, attributes, &block
+            :parameter, attributes, &
           )
         end
 
diff --git a/lib/rggen/systemverilog/rtl_package/register/sv_rtl_package.rb b/lib/rggen/systemverilog/rtl_package/register/sv_rtl_package.rb
index 87447e4..1c4c831 100644
--- a/lib/rggen/systemverilog/rtl_package/register/sv_rtl_package.rb
+++ b/lib/rggen/systemverilog/rtl_package/register/sv_rtl_package.rb
@@ -41,7 +41,7 @@ def define_array_offset_localparams
       value_list = group_address_list(address_list, size_list).first
       localparam :__offset, {
         name: "#{full_name}_byte_offset",
-        data_type: :bit, width: width, array_size: size_list, default: value_list
+        data_type: :bit, width:, array_size: size_list, default: value_list
       }
     end
 
@@ -68,7 +68,7 @@ def define_single_offset_localparam
       value = address_list.first
       localparam :__offset, {
         name: "#{full_name}_byte_offset",
-        data_type: :bit, width: width, default: value
+        data_type: :bit, width:, default: value
       }
     end
 
diff --git a/rggen-systemverilog.gemspec b/rggen-systemverilog.gemspec
index 8504226..4d268fa 100644
--- a/rggen-systemverilog.gemspec
+++ b/rggen-systemverilog.gemspec
@@ -26,5 +26,5 @@ Gem::Specification.new do |spec|
   spec.files = `git ls-files lib LICENSE CODE_OF_CONDUCT.md README.md`.split($RS)
   spec.require_paths = ['lib']
 
-  spec.required_ruby_version = Gem::Requirement.new('>= 3.0')
+  spec.required_ruby_version = Gem::Requirement.new('>= 3.1')
 end