diff --git a/verible-test-0.sv b/verible-test-0.sv
index 152347f9..d2502340 100644
--- a/verible-test-0.sv
+++ b/verible-test-0.sv
@@ -1,13 +1,13 @@
-module debounce(
-  input wire logic clk, output logic debounced
-   );
-stateType ns;
+module debounce (
+    input wire logic clk,
+    output logic debounced
+);
+  stateType ns;
 
-  always_comb
-            begin
-             ns = ERR;
-       end
+  always_comb begin
+    ns = ERR;
+  end
 
   logic timerDone;
-     logic clrTimer;
-   endmodule
+  logic clrTimer;
+endmodule