Floating-point wrappers in the STL

[VonTum]

With wrappers for builtin floating-point modules (On Intel & Xilinx FPGAs), we have a far more competent language to be used at PC2.

Full parametrizability will likely be blocked by #25, but basic 32-bit floats shouldn't be an issue

• Investigate such floating point libraries for Xilinx FPGAs (Vivado)
• Investigate for Intel FPGAs (Intel Quartus)
• Make shared library, with interface that is compatible with both

[VonTum]

http://www.flopoco.org/ is a good resource for this

[VonTum]

As is https://www.sollya.org/

[VonTum]

Of course, DSP-based floating point units will be provided by Intel and Xilinx specifically. Look through documentation to see what's possible. Maybe look at HLS generated hardware?

[VonTum]

More https://github.com/freecores/fpu_double