From 02a2f7ea26d1dff80e9f13019ae6500052f0d349 Mon Sep 17 00:00:00 2001 From: Steve Klabnik Date: Mon, 18 Jul 2022 14:26:10 -0500 Subject: [PATCH] Update toolchain to last night's nightly --- Cargo.lock | 23 +++++++--- app/demo-stm32f4-discovery/app-f3.toml | 3 +- app/demo-stm32f4-discovery/app.toml | 2 +- app/demo-stm32h7-nucleo/app-h753.toml | 2 +- app/gemini-bu/app.toml | 2 +- app/gimlet/rev-b.toml | 4 +- app/gimletlet/app.toml | 4 +- app/sidecar/app.toml | 2 +- build/xtask/src/dist.rs | 2 +- drv/lpc55-romapi/src/lib.rs | 1 - drv/sidecar-seq-server/src/main.rs | 1 - drv/stm32g0-usart/Cargo.toml | 2 +- drv/stm32xx-sys/src/main.rs | 1 + rust-toolchain.toml | 2 +- stage0/src/main.rs | 7 +-- sys/kern/src/arch/arm_m.rs | 47 ++++++++++---------- sys/kern/src/lib.rs | 3 +- sys/userlib/src/lib.rs | 60 +++++++++++++------------- sys/userlib/src/macros.rs | 4 +- task/jefe/Cargo.toml | 2 +- task/ping/src/main.rs | 3 +- task/uartecho/src/main.rs | 1 - test/test-assist/Cargo.toml | 2 +- test/test-runner/Cargo.toml | 2 +- 24 files changed, 96 insertions(+), 86 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 146d153de..aba6dbe61 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -363,9 +363,9 @@ checksum = "6245d59a3e82a7fc217c5828a6692dbc6dfb63a0c8c90495621f7b9d79704a0e" [[package]] name = "cortex-m" -version = "0.7.3" +version = "0.7.5" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "2ac919ef424449ec8c08d515590ce15d9262c0ca5f0da5b0c901e971a3b783b3" +checksum = "cd20d4ac4aa86f4f75f239d59e542ef67de87cce2c282818dc6e84155d3ea126" dependencies = [ "bare-metal 0.2.5", "bitfield", @@ -403,6 +403,15 @@ dependencies = [ "cortex-m", ] +[[package]] +name = "cortex-m-semihosting" +version = "0.5.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c23234600452033cc77e4b761e740e02d2c4168e11dbf36ab14a0f58973592b0" +dependencies = [ + "cortex-m", +] + [[package]] name = "cpufeatures" version = "0.2.1" @@ -1167,7 +1176,7 @@ name = "drv-stm32g0-usart" version = "0.1.0" dependencies = [ "cortex-m", - "cortex-m-semihosting", + "cortex-m-semihosting 0.5.0", "drv-stm32xx-sys-api", "num-traits", "stm32g0", @@ -2212,7 +2221,7 @@ source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "c3d55dedd501dfd02514646e0af4d7016ce36bc12ae177ef52056989966a1eec" dependencies = [ "cortex-m", - "cortex-m-semihosting", + "cortex-m-semihosting 0.3.7", ] [[package]] @@ -3041,7 +3050,7 @@ dependencies = [ "armv6m-atomic-hack", "build-util", "cortex-m", - "cortex-m-semihosting", + "cortex-m-semihosting 0.5.0", "hubris-num-tasks", "idol", "idol-runtime", @@ -3366,7 +3375,7 @@ version = "0.1.0" dependencies = [ "build-util", "cortex-m", - "cortex-m-semihosting", + "cortex-m-semihosting 0.5.0", "hubris-num-tasks", "num-traits", "test-api", @@ -3409,7 +3418,7 @@ dependencies = [ "build-util", "cfg-if", "cortex-m", - "cortex-m-semihosting", + "cortex-m-semihosting 0.5.0", "hubris-num-tasks", "num-traits", "test-api", diff --git a/app/demo-stm32f4-discovery/app-f3.toml b/app/demo-stm32f4-discovery/app-f3.toml index bba927374..7e76d2603 100644 --- a/app/demo-stm32f4-discovery/app-f3.toml +++ b/app/demo-stm32f4-discovery/app-f3.toml @@ -44,7 +44,7 @@ stacksize = 1536 name = "drv-stm32fx-rcc" features = ["f3"] priority = 1 -max-sizes = {flash = 4096, ram = 1024} +max-sizes = {flash = 8192, ram = 1024} uses = ["rcc"] start = true @@ -96,4 +96,3 @@ priority = 5 max-sizes = {flash = 128, ram = 256} stacksize = 256 start = true - diff --git a/app/demo-stm32f4-discovery/app.toml b/app/demo-stm32f4-discovery/app.toml index 6cd074a92..9a6f23473 100644 --- a/app/demo-stm32f4-discovery/app.toml +++ b/app/demo-stm32f4-discovery/app.toml @@ -44,7 +44,7 @@ stacksize = 1536 name = "drv-stm32fx-rcc" features = ["f4"] priority = 1 -max-sizes = {flash = 4096, ram = 1024} +max-sizes = {flash = 8192, ram = 1024} uses = ["rcc"] start = true diff --git a/app/demo-stm32h7-nucleo/app-h753.toml b/app/demo-stm32h7-nucleo/app-h753.toml index 2854dbff8..9eb598152 100644 --- a/app/demo-stm32h7-nucleo/app-h753.toml +++ b/app/demo-stm32h7-nucleo/app-h753.toml @@ -153,7 +153,7 @@ task-slots = ["sys", "hash_driver"] name = "drv-stm32h7-hash-server" features = ["h753"] priority = 3 -max-sizes = {flash = 8192, ram=4096 } +max-sizes = {flash = 16384, ram=4096 } stacksize = 2048 start = true uses = ["hash"] diff --git a/app/gemini-bu/app.toml b/app/gemini-bu/app.toml index 2288ec3ac..7d0347e9d 100644 --- a/app/gemini-bu/app.toml +++ b/app/gemini-bu/app.toml @@ -138,7 +138,7 @@ task-slots = ["sys", "hash_driver"] name = "drv-stm32h7-hash-server" features = ["h753"] priority = 3 -max-sizes = {flash = 8192, ram=4096 } +max-sizes = {flash = 16384, ram=4096 } stacksize = 2048 start = true uses = ["hash"] diff --git a/app/gimlet/rev-b.toml b/app/gimlet/rev-b.toml index 6bee7bccc..18a96b39e 100644 --- a/app/gimlet/rev-b.toml +++ b/app/gimlet/rev-b.toml @@ -177,7 +177,7 @@ register_defs = "gimlet-regs-b.json" name = "drv-stm32h7-hash-server" features = ["h753"] priority = 2 -max-sizes = {flash = 8192, ram=4096 } +max-sizes = {flash = 16384, ram=4096 } stacksize = 2048 start = true uses = ["hash"] @@ -224,7 +224,7 @@ features = ["vlan"] [tasks.validate] name = "task-validate" priority = 5 -max-sizes = {flash = 8192, ram = 4096 } +max-sizes = {flash = 16384, ram = 4096 } stacksize = 1000 start = true task-slots = ["i2c_driver"] diff --git a/app/gimletlet/app.toml b/app/gimletlet/app.toml index a416b66ff..422bb5be5 100644 --- a/app/gimletlet/app.toml +++ b/app/gimletlet/app.toml @@ -111,7 +111,7 @@ features = ["stm32h753", "usart2"] uses = ["usart2"] interrupts = {"usart2.irq" = 1} priority = 3 -max-sizes = {flash = 8192, ram = 4096} +max-sizes = {flash = 16384, ram = 4096} stacksize = 2048 start = true task-slots = ["sys"] @@ -185,7 +185,7 @@ task-slots = ["sys", "user_leds"] [tasks.update_server] name = "stm32h7-update-server" priority = 3 -max-sizes = {flash = 8192, ram = 4096} +max-sizes = {flash = 16384, ram = 4096} stacksize = 2048 start = true uses = ["flash_controller", "bank2"] diff --git a/app/sidecar/app.toml b/app/sidecar/app.toml index b7aef611a..cc098574c 100644 --- a/app/sidecar/app.toml +++ b/app/sidecar/app.toml @@ -244,7 +244,7 @@ task-slots = ["i2c_driver", "sensor", "sequencer"] [tasks.validate] name = "task-validate" priority = 5 -max-sizes = {flash = 8192, ram = 4096 } +max-sizes = {flash = 16384, ram = 4096 } stacksize = 1000 start = true task-slots = ["i2c_driver"] diff --git a/build/xtask/src/dist.rs b/build/xtask/src/dist.rs index 3ed345d95..7b779a285 100644 --- a/build/xtask/src/dist.rs +++ b/build/xtask/src/dist.rs @@ -708,7 +708,6 @@ fn link_task( name: &str, allocs: &Allocations, ) -> Result<()> { - println!("linking task '{}'", name); let task_toml = &cfg.toml.tasks[name]; generate_task_linker_script( "memory.x", @@ -1287,6 +1286,7 @@ fn link( cmd.arg("-m").arg(m); cmd.arg("-z").arg("common-page-size=0x20"); cmd.arg("-z").arg("max-page-size=0x20"); + cmd.arg("-rustc-lld-flavor=ld"); cmd.current_dir(working_dir); diff --git a/drv/lpc55-romapi/src/lib.rs b/drv/lpc55-romapi/src/lib.rs index 34573e108..623525d9f 100644 --- a/drv/lpc55-romapi/src/lib.rs +++ b/drv/lpc55-romapi/src/lib.rs @@ -2,7 +2,6 @@ // License, v. 2.0. If a copy of the MPL was not distributed with this // file, You can obtain one at https://mozilla.org/MPL/2.0/. -#![feature(asm)] #![feature(naked_functions)] #![no_std] diff --git a/drv/sidecar-seq-server/src/main.rs b/drv/sidecar-seq-server/src/main.rs index 596f6cacd..73c213682 100644 --- a/drv/sidecar-seq-server/src/main.rs +++ b/drv/sidecar-seq-server/src/main.rs @@ -6,7 +6,6 @@ #![no_std] #![no_main] -#![feature(destructuring_assignment)] use crate::clock_generator::ClockGenerator; use crate::front_io::FrontIOBoard; diff --git a/drv/stm32g0-usart/Cargo.toml b/drv/stm32g0-usart/Cargo.toml index 366e297d9..6f419c338 100644 --- a/drv/stm32g0-usart/Cargo.toml +++ b/drv/stm32g0-usart/Cargo.toml @@ -10,7 +10,7 @@ num-traits = { version = "0.2.12", default-features = false } drv-stm32xx-sys-api = {path = "../stm32xx-sys-api", default-features = false} stm32g0 = { git = "https://github.com/oxidecomputer/stm32-rs-nightlies", branch = "stm32g0b1-initial-support", default-features = false } cortex-m = { version = "0.7", features = ["inline-asm"] } -cortex-m-semihosting = { version = "0.3.7", features = ["inline-asm"] } +cortex-m-semihosting = { version = "0.5.0" } [features] g031 = ["stm32g0/stm32g031", "drv-stm32xx-sys-api/g031"] diff --git a/drv/stm32xx-sys/src/main.rs b/drv/stm32xx-sys/src/main.rs index 62899df45..aa8d082f9 100644 --- a/drv/stm32xx-sys/src/main.rs +++ b/drv/stm32xx-sys/src/main.rs @@ -6,6 +6,7 @@ #![no_std] #![no_main] +#![deny(unsafe_op_in_unsafe_fn)] cfg_if::cfg_if! { if #[cfg(feature = "family-stm32g0")] { diff --git a/rust-toolchain.toml b/rust-toolchain.toml index c65647663..7bef575c0 100644 --- a/rust-toolchain.toml +++ b/rust-toolchain.toml @@ -1,5 +1,5 @@ [toolchain] -channel = "nightly-2021-09-22" +channel = "nightly-2022-07-17" targets = [ "thumbv6m-none-eabi", "thumbv7em-none-eabihf", "thumbv8m.main-none-eabihf" ] profile = "minimal" components = [ "rustfmt" ] diff --git a/stage0/src/main.rs b/stage0/src/main.rs index 7a3f446f5..73a213cdb 100644 --- a/stage0/src/main.rs +++ b/stage0/src/main.rs @@ -3,12 +3,13 @@ // file, You can obtain one at https://mozilla.org/MPL/2.0/. #![feature(cmse_nonsecure_entry)] -#![feature(asm)] #![feature(naked_functions)] #![feature(array_methods)] #![no_main] #![no_std] +use core::arch; + extern crate lpc55_pac; extern crate panic_halt; use cortex_m::peripheral::Peripherals; @@ -98,7 +99,7 @@ unsafe fn branch_to_image(image: Image) -> ! { let stack = image.get_sp(); // and branch - asm!(" + arch::asm!(" msr MSP_NS, {stack} bxns {entry}", stack = in(reg) stack, @@ -125,7 +126,7 @@ unsafe fn branch_to_image(image: Image) -> ! { let stack = image.get_sp(); // and branch - asm!(" + arch::asm!(" msr MSP, {stack} bx {entry}", stack = in(reg) stack, diff --git a/sys/kern/src/arch/arm_m.rs b/sys/kern/src/arch/arm_m.rs index e0279329a..1d6aace27 100644 --- a/sys/kern/src/arch/arm_m.rs +++ b/sys/kern/src/arch/arm_m.rs @@ -70,6 +70,7 @@ //! context switches, and just always do full save/restore, eliminating PendSV. //! We'll see. +use core::arch; use core::sync::atomic::{AtomicBool, AtomicPtr, AtomicU32, Ordering}; use zerocopy::FromBytes; @@ -335,7 +336,7 @@ pub fn apply_memory_protection(task: &task::Task) { let mpu = unsafe { // At least by not taking a &mut we're confident we're not violating // aliasing.... - &*cortex_m::peripheral::MPU::ptr() + &*cortex_m::peripheral::MPU::PTR }; for (i, region) in task.region_table().iter().enumerate() { @@ -426,7 +427,7 @@ pub fn apply_memory_protection(task: &task::Task) { let mpu = unsafe { // At least by not taking a &mut we're confident we're not violating // aliasing.... - &*cortex_m::peripheral::MPU::ptr() + &*cortex_m::peripheral::MPU::PTR }; unsafe { const DISABLE: u32 = 0b000; @@ -533,7 +534,7 @@ pub fn start_first_task(tick_divisor: u32, task: &mut task::Task) -> ! { // from their defaults, so it can't cause any surprise preemption or // anything. But these operations are `unsafe` in the `cortex_m` crate. unsafe { - let scb = &*cortex_m::peripheral::SCB::ptr(); + let scb = &*cortex_m::peripheral::SCB::PTR; // Faults on, on the processors that distinguish faults. This // distinguishes the following faults from HardFault: // @@ -588,7 +589,7 @@ pub fn start_first_task(tick_divisor: u32, task: &mut task::Task) -> ! { // Configure the priority of all external interrupts so that they can't // preempt the kernel. - let nvic = &*cortex_m::peripheral::NVIC::ptr(); + let nvic = &*cortex_m::peripheral::NVIC::PTR; cfg_if::cfg_if! { if #[cfg(armv6m)] { @@ -632,7 +633,7 @@ pub fn start_first_task(tick_divisor: u32, task: &mut task::Task) -> ! { // Safety: this, too, is safe in practice but unsafe in API. unsafe { // Configure the timer. - let syst = &*cortex_m::peripheral::SYST::ptr(); + let syst = &*cortex_m::peripheral::SYST::PTR; // Program reload value. syst.rvr.write(tick_divisor - 1); // Clear current value. @@ -646,7 +647,7 @@ pub fn start_first_task(tick_divisor: u32, task: &mut task::Task) -> ! { let mpu = unsafe { // At least by not taking a &mut we're confident we're not violating // aliasing.... - &*cortex_m::peripheral::MPU::ptr() + &*cortex_m::peripheral::MPU::PTR }; const ENABLE: u32 = 0b001; @@ -697,7 +698,7 @@ pub fn start_first_task(tick_divisor: u32, task: &mut task::Task) -> ! { cfg_if::cfg_if! { if #[cfg(armv6m)] { unsafe { - asm!(" + arch::asm!(" @ restore the callee-save registers ldm r0!, {{r4-r7}} ldm r0, {{r0-r3}} @@ -715,7 +716,7 @@ pub fn start_first_task(tick_divisor: u32, task: &mut task::Task) -> ! { } } else if #[cfg(any(armv7m, armv8m))] { unsafe { - asm!(" + arch::asm!(" @ Restore callee-save registers. ldm {task}, {{r4-r11}} @ Trap into the kernel. @@ -760,7 +761,7 @@ pub unsafe extern "C" fn SVCall() { unsafe { cfg_if::cfg_if! { if #[cfg(armv6m)] { - asm!(" + arch::asm!(" @ Inspect LR to figure out the caller's mode. mov r0, lr ldr r1, =0xFFFFFFF3 @@ -834,7 +835,7 @@ pub unsafe extern "C" fn SVCall() { options(noreturn), ) } else if #[cfg(any(armv7m, armv8m))] { - asm!(" + arch::asm!(" @ Inspect LR to figure out the caller's mode. mov r0, lr mov r1, #0xFFFFFFF3 @@ -987,7 +988,7 @@ pub unsafe extern "C" fn PendSV() { unsafe { cfg_if::cfg_if! { if #[cfg(armv6m)] { - asm!( + arch::asm!( " @ store volatile state. @ first, get a pointer to the current task. @@ -1033,7 +1034,7 @@ pub unsafe extern "C" fn PendSV() { options(noreturn), ); } else if #[cfg(any(armv7m, armv8m))] { - asm!( + arch::asm!( " @ store volatile state. @ first, get a pointer to the current task. @@ -1106,7 +1107,7 @@ pub unsafe extern "C" fn DefaultHandler() { // Safety: we're just reading the PSR. let exception_num = unsafe { let mut ipsr: u32; - asm!( + arch::asm!( "mrs {}, IPSR", out(reg) ipsr, options(pure, nomem, preserves_flags, nostack), @@ -1156,7 +1157,7 @@ pub unsafe extern "C" fn DefaultHandler() { pub fn disable_irq(n: u32) { // Disable the interrupt by poking the Interrupt Clear Enable Register. - let nvic = unsafe { &*cortex_m::peripheral::NVIC::ptr() }; + let nvic = unsafe { &*cortex_m::peripheral::NVIC::PTR }; let reg_num = (n / 32) as usize; let bit_mask = 1 << (n % 32); unsafe { @@ -1166,7 +1167,7 @@ pub fn disable_irq(n: u32) { pub fn enable_irq(n: u32) { // Enable the interrupt by poking the Interrupt Set Enable Register. - let nvic = unsafe { &*cortex_m::peripheral::NVIC::ptr() }; + let nvic = unsafe { &*cortex_m::peripheral::NVIC::PTR }; let reg_num = (n / 32) as usize; let bit_mask = 1 << (n % 32); unsafe { @@ -1187,7 +1188,7 @@ enum FaultType { #[cfg(any(armv7m, armv8m))] unsafe extern "C" fn configurable_fault() { unsafe { - asm!( + arch::asm!( " @ Read the current task pointer. movw r0, #:lower16:CURRENT_TASK_PTR @@ -1251,7 +1252,7 @@ pub unsafe extern "C" fn MemoryManagement() { // Safety: this is merely a call (a tailcall, really) to a different handler // -- we're doing it this way simply because the other handler does context // save, so we can't go up into Rust here. - unsafe { asm!("b {0}", sym configurable_fault, options(noreturn)) } + unsafe { arch::asm!("b {0}", sym configurable_fault, options(noreturn)) } } /// Initial entry point for handling a bus fault. @@ -1263,7 +1264,7 @@ pub unsafe extern "C" fn BusFault() { // Safety: this is merely a call (a tailcall, really) to a different handler // -- we're doing it this way simply because the other handler does context // save, so we can't go up into Rust here. - unsafe { asm!("b {0}", sym configurable_fault, options(noreturn)) } + unsafe { arch::asm!("b {0}", sym configurable_fault, options(noreturn)) } } /// Initial entry point for handling a usage fault. @@ -1275,7 +1276,7 @@ pub unsafe extern "C" fn UsageFault() { // Safety: this is merely a call (a tailcall, really) to a different handler // -- we're doing it this way simply because the other handler does context // save, so we can't go up into Rust here. - unsafe { asm!("b {0}", sym configurable_fault, options(noreturn)) } + unsafe { arch::asm!("b {0}", sym configurable_fault, options(noreturn)) } } /// Initial entry point for handling a hard fault (ARMv6). @@ -1285,7 +1286,7 @@ pub unsafe extern "C" fn UsageFault() { #[cfg(armv6m)] pub unsafe extern "C" fn HardFault() { unsafe { - asm!( + arch::asm!( " @ Read the current task pointer. ldr r0, =CURRENT_TASK_PTR @@ -1461,7 +1462,7 @@ unsafe extern "C" fn handle_fault( // reference, so we shouldn't be breaking any rules by doing this. Arguably // this should be available as a safe operation in the cortex_m crate, but // that crate comes with _ideas_ about peripheral ownership management. - let scb = unsafe { &*cortex_m::peripheral::SCB::ptr() }; + let scb = unsafe { &*cortex_m::peripheral::SCB::PTR }; let cfsr = Cfsr::from_bits_truncate(scb.cfsr.read()); // Who faulted? Collect some parameters from the task. @@ -1565,7 +1566,7 @@ unsafe extern "C" fn handle_fault( // Context Control register. const LSPACT: u32 = 1 << 0; unsafe { - let fpu = &*cortex_m::peripheral::FPU::ptr(); + let fpu = &*cortex_m::peripheral::FPU::PTR; fpu.fpccr.modify(|x| x & !LSPACT); } } @@ -1577,7 +1578,7 @@ unsafe extern "C" fn handle_fault( // points to a correctly aligned area large enough to store 16 floats -- a // property our caller is required to ensure -- this is ok. unsafe { - asm!("vstm {0}, {{s16-s31}}", in(reg) fpsave); + arch::asm!("vstm {0}, {{s16-s31}}", in(reg) fpsave); } // We are now going to force a fault on our current task and directly diff --git a/sys/kern/src/lib.rs b/sys/kern/src/lib.rs index 977a88152..b4c3bd547 100644 --- a/sys/kern/src/lib.rs +++ b/sys/kern/src/lib.rs @@ -27,8 +27,9 @@ //! most clever algorithms used in kernels wind up requiring `unsafe`.) #![cfg_attr(target_os = "none", no_std)] -#![feature(asm)] #![feature(naked_functions)] +#![feature(asm_sym)] +#![feature(asm_const)] // Require an unsafe block even in an unsafe fn, because unsafe fns are about // contract, not implementation. #![forbid(unsafe_op_in_unsafe_fn)] diff --git a/sys/userlib/src/lib.rs b/sys/userlib/src/lib.rs index de4ff9f76..3e9d63267 100644 --- a/sys/userlib/src/lib.rs +++ b/sys/userlib/src/lib.rs @@ -25,7 +25,8 @@ //! See: https://github.com/rust-lang/rust/issues/73450#issuecomment-650463347 #![no_std] -#![feature(asm)] +#![feature(asm_const)] +#![feature(asm_sym)] #![feature(naked_functions)] #[macro_use] @@ -36,6 +37,7 @@ pub use num_derive::{FromPrimitive, ToPrimitive}; pub use num_traits::{FromPrimitive, ToPrimitive}; pub use unwrap_lite::UnwrapLite; +use core::arch; use core::marker::PhantomData; pub mod hl; @@ -154,7 +156,7 @@ struct SendArgs<'a> { unsafe extern "C" fn sys_send_stub(_args: &mut SendArgs<'_>) -> RcLen { cfg_if::cfg_if! { if #[cfg(armv6m)] { - asm!(" + arch::asm!(" @ Spill the registers we're about to use to pass stuff. push {{r4-r7, lr}} mov r4, r8 @@ -191,7 +193,7 @@ unsafe extern "C" fn sys_send_stub(_args: &mut SendArgs<'_>) -> RcLen { options(noreturn), ) } else if #[cfg(any(armv7m, armv8m))] { - asm!(" + arch::asm!(" @ Spill the registers we're about to use to pass stuff. push {{r4-r11}} @ Load in args from the struct. @@ -338,7 +340,7 @@ unsafe extern "C" fn sys_recv_stub( ) -> u32 { cfg_if::cfg_if! { if #[cfg(armv6m)] { - asm!(" + arch::asm!(" @ Spill the registers we're about to use to pass stuff. push {{r4-r7, lr}} mov r4, r8 @@ -384,7 +386,7 @@ unsafe extern "C" fn sys_recv_stub( options(noreturn), ) } else if #[cfg(any(armv7m, armv8m))] { - asm!(" + arch::asm!(" @ Spill the registers we're about to use to pass stuff. push {{r4-r11}} @ Move register arguments into their proper positions. @@ -453,7 +455,7 @@ unsafe extern "C" fn sys_reply_stub( ) { cfg_if::cfg_if! { if #[cfg(armv6m)] { - asm!(" + arch::asm!(" @ Spill the registers we're about to use to pass stuff. Note @ that we're being clever and pushing only the registers we @ need; this means the pop sequence at the end needs to match! @@ -485,7 +487,7 @@ unsafe extern "C" fn sys_reply_stub( options(noreturn), ) } else if #[cfg(any(armv7m, armv8m))] { - asm!(" + arch::asm!(" @ Spill the registers we're about to use to pass stuff. Note @ that we're being clever and pushing only the registers we @ need; this means the pop sequence at the end needs to match! @@ -552,7 +554,7 @@ unsafe extern "C" fn sys_set_timer_stub( ) { cfg_if::cfg_if! { if #[cfg(armv6m)] { - asm!(" + arch::asm!(" @ Spill the registers we're about to use to pass stuff. push {{r4-r7, lr}} mov r4, r11 @@ -582,7 +584,7 @@ unsafe extern "C" fn sys_set_timer_stub( options(noreturn), ) } else if #[cfg(any(armv7m, armv8m))] { - asm!(" + arch::asm!(" @ Spill the registers we're about to use to pass stuff. push {{r4-r7, r11, lr}} @@ -635,7 +637,7 @@ pub fn sys_borrow_read( unsafe extern "C" fn sys_borrow_read_stub(_args: *mut BorrowReadArgs) -> RcLen { cfg_if::cfg_if! { if #[cfg(armv6m)] { - asm!(" + arch::asm!(" @ Spill the registers we're about to use to pass stuff. push {{r4-r7, lr}} mov r4, r8 @@ -668,7 +670,7 @@ unsafe extern "C" fn sys_borrow_read_stub(_args: *mut BorrowReadArgs) -> RcLen { options(noreturn), ) } else if #[cfg(any(armv7m, armv8m))] { - asm!(" + arch::asm!(" @ Spill the registers we're about to use to pass stuff. push {{r4-r8, r11}} @@ -732,7 +734,7 @@ unsafe extern "C" fn sys_borrow_write_stub( ) -> RcLen { cfg_if::cfg_if! { if #[cfg(armv6m)] { - asm!(" + arch::asm!(" @ Spill the registers we're about to use to pass stuff. push {{r4-r7, lr}} mov r4, r8 @@ -766,7 +768,7 @@ unsafe extern "C" fn sys_borrow_write_stub( options(noreturn), ) } else if #[cfg(any(armv7m, armv8m))] { - asm!(" + arch::asm!(" @ Spill the registers we're about to use to pass stuff. push {{r4-r8, r11}} @@ -851,7 +853,7 @@ unsafe extern "C" fn sys_borrow_info_stub( ) { cfg_if::cfg_if! { if #[cfg(armv6m)] { - asm!(" + arch::asm!(" @ Spill the registers we're about to use to pass stuff. push {{r4-r6, lr}} mov r4, r11 @@ -880,7 +882,7 @@ unsafe extern "C" fn sys_borrow_info_stub( options(noreturn), ) } else if #[cfg(any(armv7m, armv8m))] { - asm!(" + arch::asm!(" @ Spill the registers we're about to use to pass stuff. push {{r4-r6, r11}} @@ -923,7 +925,7 @@ pub fn sys_irq_control(mask: u32, enable: bool) { unsafe extern "C" fn sys_irq_control_stub(_mask: u32, _enable: u32) { cfg_if::cfg_if! { if #[cfg(armv6m)] { - asm!(" + arch::asm!(" @ Spill the registers we're about to use to pass stuff. push {{r4, r5, lr}} mov r4, r11 @@ -951,7 +953,7 @@ unsafe extern "C" fn sys_irq_control_stub(_mask: u32, _enable: u32) { options(noreturn), ) } else if #[cfg(any(armv7m, armv8m))] { - asm!(" + arch::asm!(" @ Spill the registers we're about to use to pass stuff. push {{r4, r5, r11, lr}} @@ -990,7 +992,7 @@ pub fn sys_panic(msg: &[u8]) -> ! { unsafe extern "C" fn sys_panic_stub(_msg: *const u8, _len: usize) -> ! { cfg_if::cfg_if! { if #[cfg(armv6m)] { - asm!(" + arch::asm!(" @ We're not going to return, so technically speaking we don't @ need to save registers. However, we save them anyway, so that @ we can reconstruct the state that led to the panic. @@ -1014,7 +1016,7 @@ unsafe extern "C" fn sys_panic_stub(_msg: *const u8, _len: usize) -> ! { options(noreturn), ) } else if #[cfg(any(armv7m, armv8m))] { - asm!(" + arch::asm!(" @ We're not going to return, so technically speaking we don't @ need to save registers. However, we save them anyway, so that @ we can reconstruct the state that led to the panic. @@ -1100,7 +1102,7 @@ struct RawTimerState { unsafe extern "C" fn sys_get_timer_stub(_out: *mut RawTimerState) { cfg_if::cfg_if! { if #[cfg(armv6m)] { - asm!(" + arch::asm!(" @ Spill the registers we're about to use to pass stuff. push {{r4-r7, lr}} mov r4, r8 @@ -1133,7 +1135,7 @@ unsafe extern "C" fn sys_get_timer_stub(_out: *mut RawTimerState) { options(noreturn), ) } else if #[cfg(any(armv7m, armv8m))] { - asm!(" + arch::asm!(" @ Spill the registers we're about to use to pass stuff. push {{r4-r11}} @ Load the constant syscall number. @@ -1172,7 +1174,7 @@ pub unsafe extern "C" fn _start() -> ! { cfg_if::cfg_if! { if #[cfg(armv6m)] { - asm!(" + arch::asm!(" @ Copy data initialization image into data section. @ Note: this assumes that both source and destination are 32-bit @ aligned and padded to 4-byte boundary. @@ -1222,7 +1224,7 @@ pub unsafe extern "C" fn _start() -> ! { options(noreturn), ) } else if #[cfg(any(armv7m, armv8m))] { - asm!(" + arch::asm!(" @ Copy data initialization image into data section. @ Note: this assumes that both source and destination are 32-bit @ aligned and padded to 4-byte boundary. @@ -1459,7 +1461,7 @@ pub fn sys_refresh_task_id(task_id: TaskId) -> TaskId { unsafe extern "C" fn sys_refresh_task_id_stub(_tid: u32) -> u32 { cfg_if::cfg_if! { if #[cfg(armv6m)] { - asm!(" + arch::asm!(" @ Spill the registers we're about to use to pass stuff. @ match! push {{r4, r5, lr}} @@ -1489,7 +1491,7 @@ unsafe extern "C" fn sys_refresh_task_id_stub(_tid: u32) -> u32 { options(noreturn), ) } else if #[cfg(any(armv7m, armv8m))] { - asm!(" + arch::asm!(" @ Spill the registers we're about to use to pass stuff. push {{r4, r5, r11, lr}} @@ -1528,7 +1530,7 @@ pub fn sys_post(task_id: TaskId, bits: u32) -> u32 { unsafe extern "C" fn sys_post_stub(_tid: u32, _mask: u32) -> u32 { cfg_if::cfg_if! { if #[cfg(armv6m)] { - asm!(" + arch::asm!(" @ Spill the registers we're about to use to pass stuff. push {{r4, r5, lr}} mov r4, r11 @@ -1558,7 +1560,7 @@ unsafe extern "C" fn sys_post_stub(_tid: u32, _mask: u32) -> u32 { options(noreturn), ) } else if #[cfg(any(armv7m, armv8m))] { - asm!(" + arch::asm!(" @ Spill the registers we're about to use to pass stuff. push {{r4, r5, r11, lr}} @@ -1598,7 +1600,7 @@ pub fn sys_reply_fault(task_id: TaskId, reason: ReplyFaultReason) { unsafe extern "C" fn sys_reply_fault_stub(_tid: u32, _reason: u32) { cfg_if::cfg_if! { if #[cfg(armv6m)] { - asm!(" + arch::asm!(" @ Spill the registers we're about to use to pass stuff. push {{r4, r5, lr}} mov r4, r11 @@ -1626,7 +1628,7 @@ unsafe extern "C" fn sys_reply_fault_stub(_tid: u32, _reason: u32) { options(noreturn), ) } else if #[cfg(any(armv7m, armv8m))] { - asm!(" + arch::asm!(" @ Spill the registers we're about to use to pass stuff. push {{r4, r5, r11, lr}} diff --git a/sys/userlib/src/macros.rs b/sys/userlib/src/macros.rs index 76d4049a0..66f34a9de 100644 --- a/sys/userlib/src/macros.rs +++ b/sys/userlib/src/macros.rs @@ -11,13 +11,13 @@ cfg_if::cfg_if! { macro_rules! sys_log { ($s:expr) => { unsafe { - let stim = &mut (*cortex_m::peripheral::ITM::ptr()).stim[1]; + let stim = &mut (*cortex_m::peripheral::ITM::PTR).stim[1]; cortex_m::iprintln!(stim, $s); } }; ($s:expr, $($tt:tt)*) => { unsafe { - let stim = &mut (*cortex_m::peripheral::ITM::ptr()).stim[1]; + let stim = &mut (*cortex_m::peripheral::ITM::PTR).stim[1]; cortex_m::iprintln!(stim, $s, $($tt)*); } }; diff --git a/task/jefe/Cargo.toml b/task/jefe/Cargo.toml index ce0885c6b..a6c1a5c20 100644 --- a/task/jefe/Cargo.toml +++ b/task/jefe/Cargo.toml @@ -11,7 +11,7 @@ ringbuf = {path = "../../lib/ringbuf" } num-traits = { version = "0.2.12", default-features = false } zerocopy = "0.6.1" cortex-m = { version = "0.7", features = ["inline-asm"] } -cortex-m-semihosting = { version = "0.3.7", features = ["inline-asm"], optional = true } +cortex-m-semihosting = { version = "0.5.0", optional = true } armv6m-atomic-hack = {path = "../../lib/armv6m-atomic-hack"} idol-runtime = {git = "https://github.com/oxidecomputer/idolatry.git"} task-jefe-api = {path = "../jefe-api"} diff --git a/task/ping/src/main.rs b/task/ping/src/main.rs index 3792d0318..f3117e1da 100644 --- a/task/ping/src/main.rs +++ b/task/ping/src/main.rs @@ -4,7 +4,6 @@ #![no_std] #![no_main] -#![feature(asm)] use userlib::*; @@ -29,7 +28,7 @@ fn divzero() { let p: u32 = 123; let q: u32 = 0; let _res: u32; - asm!("udiv r2, r1, r0", in("r1") p, in("r0") q, out("r2") _res); + core::arch::asm!("udiv r2, r1, r0", in("r1") p, in("r0") q, out("r2") _res); } } diff --git a/task/uartecho/src/main.rs b/task/uartecho/src/main.rs index 6ceb97416..f6fc167ec 100644 --- a/task/uartecho/src/main.rs +++ b/task/uartecho/src/main.rs @@ -4,7 +4,6 @@ #![no_std] #![no_main] -#![feature(asm)] #[cfg(any(feature = "stm32h743", feature = "stm32h753"))] use drv_stm32h7_usart as drv_usart; diff --git a/test/test-assist/Cargo.toml b/test/test-assist/Cargo.toml index fc4a89a3e..67a1b1afd 100644 --- a/test/test-assist/Cargo.toml +++ b/test/test-assist/Cargo.toml @@ -10,7 +10,7 @@ hubris-num-tasks = {path = "../../sys/num-tasks"} zerocopy = "0.6.1" num-traits = { version = "0.2.12", default-features = false } test-api = {path = "../test-api"} -cortex-m-semihosting = { version = "0.3.7", features = ["inline-asm"], optional = true } +cortex-m-semihosting = { version = "0.5.0", optional = true } [build-dependencies] build-util = {path = "../../build/util"} diff --git a/test/test-runner/Cargo.toml b/test/test-runner/Cargo.toml index 853664c1b..db8e87382 100644 --- a/test/test-runner/Cargo.toml +++ b/test/test-runner/Cargo.toml @@ -10,7 +10,7 @@ test-api = {path = "../test-api"} cortex-m = {version = "0.7", features = ["inline-asm"]} zerocopy = "0.6.1" num-traits = { version = "0.2.12", default-features = false } -cortex-m-semihosting = { version = "0.3.7", features = ["inline-asm"], optional = true } +cortex-m-semihosting = { version = "0.5.0", optional = true } armv6m-atomic-hack = {path = "../../lib/armv6m-atomic-hack"} cfg-if = "1"