-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathMakefile
160 lines (128 loc) · 5.73 KB
/
Makefile
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
MODULE = riscv_top
TECH=osu018
COMMON_SRC = ./source/mem_bus_arbiter.v ./source/dp_ram.v ./source/dp_rom.v ./source/riscv_top.v ./source/uart.v ./source/uart_wrap.v ./source/gpio.v
VERILOG_SRC = ./source/alu.v \
./source/reg_file.v \
./source/riscv_core.v \
./source/riscv_core_axi.v \
./source/decoder.v \
./source/decompressor.v \
./source/controller.v \
./source/lsu.v \
./source/csr.v \
./source/fetch_stage.v \
./source/realign_buffer.v \
./source/mont_mul.v \
./source/axilite_master.v
POST_SYNTH_SRC = ./riscv_core.rtlnopwr.v \
/usr/local/share/qflow/tech/osu018/osu018_stdcells.v
SIM_SRC = $(VERILOG_SRC)
TESTNAMES = $(wildcard ./tests/*.S)
ECC_WORD_COUNT = 8
HARD_GF = 1
DUMP_TRACE = 1
BOOT_ADDRESS = 0
MEM_SIZE = 524288
#MEM_SIZE = 262144
DEFINE_FLAGS = -DECC_WORD_COUNT=$(ECC_WORD_COUNT) -DBOOT_ADDRESS=$(BOOT_ADDRESS) -DMEM_SIZE=$(MEM_SIZE) -DDUMP_TRACE=$(DUMP_TRACE) -DMEM_ORIGIN=$(MEM_ORIGIN) -DMEM_LENGTH=$(MEM_LENGTH) -DSTACK_LENGTH=$(STACK_LENGTH) -DSTACK_ORIGIN=$(STACK_ORIGIN) -DHARD_GF=$(HARD_GF)
all: firmware sim_iverilog
test: compile_test sim_iverilog
clean:
rm -rf $(shell (cat .gitignore))
lint:
verilator $(DEFINE_FLAGS) -I./source --lint-only $(SIM_SRC) $(COMMON_SRC) --top-module $(MODULE)
MEM_ORIGIN=0
MEM_LENGTH=\(MEM_SIZE-STACK_LENGTH\)
STACK_LENGTH=98304
STACK_ORIGIN=\(MEM_SIZE-STACK_LENGTH\)
CFLAGS = -O3 -falign-functions=4 -falign-jumps=4 -falign-labels=4 -funroll-all-loops -fdata-sections -ffunction-sections -Wl,--gc-sections
COMMON_C_SRC = software/start.S software/handlers.c software/print.c
compile_test: CFLAGS += -nostdlib
compile_test: COMMON_C_SRC =
bootrom: CFLAGS=-Os -fdata-sections -ffunction-sections -Wl,--gc-sections
bootrom: MEM_SIZE=2048
bootrom: MEM_ORIGIN=0x100000
bootrom: MEM_LENGTH=MEM_SIZE
bootrom: STACK_ORIGIN=0
bootrom: STACK_LENGTH=MEM_SIZE
bootrom: SRC=software/bootrom.c
compile_test bootrom firmware: prepare_ld
riscv32-unknown-elf-gcc -I./software $(CFLAGS) $(DEFINE_FLAGS) -march=rv32ec -mabi=ilp32e -nostartfiles -T software/out.ld $(COMMON_C_SRC) $(SRC) -o firmware.elf
riscv32-unknown-elf-objdump --disassembler-options=no-aliases,numeric -D firmware.elf > firmware.dump
riscv32-unknown-elf-objcopy -O binary firmware.elf firmware.bin
riscv32-unknown-elf-objcopy -O ihex firmware.elf firmware.ihex
cat firmware.bin | od -t x4 -w4 -v -A n > firmware.txt
test_all:
$(foreach var,$(TESTNAMES), echo "Test Name:$(var)"; make DUMP_TRACE=0 SRC=$(var) compile_test sim_iverilog;)
COREMARK_SRC = coremark/core_list_join.c \
coremark/core_main.c \
coremark/core_matrix.c \
coremark/core_portme.c \
coremark/core_state.c \
coremark/core_util.c \
coremark/cvt.c \
coremark/ee_printf.c
FOURQ_SRC = FourQ_RV32/random/random.c \
FourQ_RV32/sha512/sha512.c \
FourQ_RV32/tests/$(FOURQ_TEST).c \
FourQ_RV32/tests/test_extras.c \
FourQ_RV32/crypto_util.c \
FourQ_RV32/eccp2.c \
FourQ_RV32/eccp2_no_endo.c \
FourQ_RV32/kex.c \
FourQ_RV32/schnorrq.c \
FourQ_RV32/tests/blake2/*.c
C25519_SRC = CycloneCrypto/ecc/curve25519.c \
CycloneCrypto/ecc/ed25519.c \
CycloneCrypto/hash/sha512.c \
CycloneCrypto/common/os_port_none.c \
CycloneCrypto/common/cpu_endian.c \
CycloneCrypto/main.c
P256_SRC = tinycrypt/tests/test_ecc_$(P256_TEST).c \
tinycrypt/tests/test_ecc_utils.c \
tinycrypt/source/*.c
# g++ -I./ -I./common ./ecc/curve25519.c ./ecc/ed25519.c ./hash/sha512.c ./common/os_port_none.c ./common/cpu_endian.c main.c
p256: CFLAGS += --std=gnu99 -I./tinycrypt/include -I./tinycrypt/tests/include
p256: SRC=$(P256_SRC)
c25519: CFLAGS += -ICycloneCrypto/ -ICycloneCrypto/common
c25519: SRC=$(C25519_SRC)
fourq: CFLAGS += -fwrapv -fomit-frame-pointer -D_RV32_ -D__OSNONE__ -DUSE_ENDO -D_NO_CACHE_MEM_ -I./FourQ_RV32 -I./FourQ_RV32/tests/blake2
fourq: SRC=$(FOURQ_SRC)
fourq: ECC_WORD_COUNT = 4
coremark: SRC=$(COREMARK_SRC)
dhrystone: SRC=dhrystone/dhrystone.c dhrystone/dhrystone_main.c
p256 c25519 fourq coremark dhrystone: DUMP_TRACE=0
p256 c25519 fourq coremark dhrystone: firmware sim_verilator
sim_verilator: compile_verilator
-./obj_dir/V$(MODULE)
compile_verilator:
verilator -O3 $(DEFINE_FLAGS) --cc --trace --x-assign unique $(SIM_SRC) $(COMMON_SRC) -I./source --exe $(MODULE)_tb.cpp --top-module $(MODULE)
make CXXFLAGS="$(DEFINE_FLAGS)" -j -C obj_dir/ -f V$(MODULE).mk V$(MODULE)
sim_iverilog: compile_iverilog
vvp iv_exec
compile_iverilog:
iverilog $(DEFINE_FLAGS) -g2012 -I./source $(SIM_SRC) $(COMMON_SRC) riscv_top_tb.v -o iv_exec
synth_vivado:
vivado -mode batch -nojournal -nolog -source vivado_synth.tcl
synth:
qflow synthesize --tech $(TECH) riscv_core > /dev/null
sta:
qflow sta --tech $(TECH) riscv_core > /dev/null
prepare_ld:
gcc -E -x c $(DEFINE_FLAGS) software/link.ld | grep -v '^#' > software/out.ld
synth_fpga:
yosys -ql synth_fpga.log -p 'synth_ice40 -top riscv_top; write_verilog synth.v' $(SIM_SRC) $(COMMON_SRC)
gcc_fourq:
gcc -O3 -fwrapv -fomit-frame-pointer -funroll-loops -D_RV32_ -D__OSNONE__ -DUSE_ENDO=1 -D_NO_CACHE_MEM_ -I./FourQ_RV32 $(CFLAGS) $(DEFINE_FLAGS) $(FOURQ_SRC)
sim_mmul:
iverilog -g2012 -I./source ./source/mont_mul.v ./source/dp_ram.v mont_mul_tb.v -o iv_exec
vvp iv_exec
bench_all:
mkdir -p bench_res
make fourq FOURQ_TEST=ecc_tests HARD_GF=$(HARD_GF) > ./bench_res/ecc_tests.out
make fourq FOURQ_TEST=crypto_tests HARD_GF=$(HARD_GF) > ./bench_res/crypto_tests.out
make fourq FOURQ_TEST=fp_tests HARD_GF=$(HARD_GF) > ./bench_res/fp_tests.out
make fourq FOURQ_TEST=ARIS HARD_GF=$(HARD_GF) > ./bench_res/ARIS.out
make p256 P256_TEST=dh HARD_GF=$(HARD_GF) > ./bench_res/p256_dh.out
make p256 P256_TEST=dsa HARD_GF=$(HARD_GF) > ./bench_res/p256_dsa.out
make c25519 HARD_GF=$(HARD_GF) > ./bench_res/c25519.out