From b7a81f720ab5c55e2428a254add675ed4bdd4bc6 Mon Sep 17 00:00:00 2001 From: Nate Catelli Date: Wed, 23 Aug 2023 15:14:39 +0000 Subject: [PATCH] fix: address clippy lints --- src/cpu/chip8/memory.rs | 2 +- src/cpu/chip8/operations/mod.rs | 2 -- src/cpu/chip8/operations/tests/mod.rs | 1 - 3 files changed, 1 insertion(+), 4 deletions(-) diff --git a/src/cpu/chip8/memory.rs b/src/cpu/chip8/memory.rs index f12dce4..3c7edc8 100644 --- a/src/cpu/chip8/memory.rs +++ b/src/cpu/chip8/memory.rs @@ -11,7 +11,7 @@ where T: Default, { pub fn new(capacity: usize) -> Self { - let inner = (0..capacity).into_iter().map(|_| ::default()).collect(); + let inner = (0..capacity).map(|_| ::default()).collect(); Self { capacity, inner } } } diff --git a/src/cpu/chip8/operations/mod.rs b/src/cpu/chip8/operations/mod.rs index f66726e..7ead1b8 100644 --- a/src/cpu/chip8/operations/mod.rs +++ b/src/cpu/chip8/operations/mod.rs @@ -648,7 +648,6 @@ impl Generate> for ReadRegistersFromMemory { fn generate(&self, cpu: &Chip8) -> Vec { let reg_inclusive_end_idx = u8::from(self.addressing_mode.src); (0..=reg_inclusive_end_idx) - .into_iter() .filter(|idx| *idx <= 0x0f) // safe to unwrap due to filter constraint .map(|idx| GpRegisters::try_from(idx).unwrap()) @@ -685,7 +684,6 @@ impl Generate> for StoreRegistersToMemory { fn generate(&self, cpu: &Chip8) -> Vec { let reg_inclusive_end_idx = u8::from(self.addressing_mode.src); (0..=reg_inclusive_end_idx) - .into_iter() .filter(|idx| *idx <= 0x0f) // safe to unwrap due to filter constraint .map(|idx| GpRegisters::try_from(idx).unwrap()) diff --git a/src/cpu/chip8/operations/tests/mod.rs b/src/cpu/chip8/operations/tests/mod.rs index 6c3e5bd..d006a14 100644 --- a/src/cpu/chip8/operations/tests/mod.rs +++ b/src/cpu/chip8/operations/tests/mod.rs @@ -113,7 +113,6 @@ fn should_generate_drw_instruction() { cpu.address_space.write(0x00, 0xf0).unwrap(); let mut expected = (0..8) - .into_iter() // 0xf0 .map(|x| { let bit_is_set = (0xf0u8 >> (7 - x)) & 1;