From 550f656b155b1dc21788810697967d6d11777a25 Mon Sep 17 00:00:00 2001 From: Matt Jenkins Date: Wed, 18 Apr 2018 10:06:42 +0100 Subject: [PATCH] Added XLP printing routines --- src/Makefile.am | 2 +- src/Makefile.in | 12 +- src/families/family-xlp.c | 412 ++++++++++++++++++++++++++++++++++++++ src/include/pic32.h | 163 +++++++++++++++ src/target.c | 3 +- 5 files changed, 588 insertions(+), 4 deletions(-) create mode 100644 src/families/family-xlp.c diff --git a/src/Makefile.am b/src/Makefile.am index 3fe3c34..d8dabc2 100644 --- a/src/Makefile.am +++ b/src/Makefile.am @@ -1,7 +1,7 @@ bin_PROGRAMS=pic32prog pic32prog_LDADD=$(ADAPTER_OBJ) $(HID_OBJ) $(SER_OBJ) pic32prog_DEPENDENCIES=$(ADAPTER_OBJ) $(HID_OBJ) $(SER_OBJ) -pic32prog_SOURCES=pic32prog.c configure.c executive.c target.c families/family-mz.c families/family-mx1.c families/family-mx3.c +pic32prog_SOURCES=pic32prog.c configure.c executive.c target.c families/family-mz.c families/family-mx1.c families/family-mx3.c families/family-xlp.c pic32prog_CFLAGS=-DGITCOUNT='"$(GITCOUNT)"' EXTRA_pic32prog_SOURCES=hid/linux/hid.c hid/mac/hid.c hid/windows/hid.c hid/bsd/hid.c adapters/adapter-an1388.c adapters/adapter-an1388-uart.c adapters/adapter-bitbang.c adapters/adapter-hidboot.c adapters/adapter-mpsse.c adapters/adapter-pickit2.c adapters/adapter-stk500v2.c adapters/adapter-uhb.c serial.c diff --git a/src/Makefile.in b/src/Makefile.in index d96f0c0..25f62e4 100644 --- a/src/Makefile.in +++ b/src/Makefile.in @@ -112,7 +112,8 @@ am_pic32prog_OBJECTS = pic32prog-pic32prog.$(OBJEXT) \ pic32prog-target.$(OBJEXT) \ families/pic32prog-family-mz.$(OBJEXT) \ families/pic32prog-family-mx1.$(OBJEXT) \ - families/pic32prog-family-mx3.$(OBJEXT) + families/pic32prog-family-mx3.$(OBJEXT) \ + families/pic32prog-family-xlp.$(OBJEXT) pic32prog_OBJECTS = $(am_pic32prog_OBJECTS) am__DEPENDENCIES_1 = @BSD_TRUE@am__DEPENDENCIES_2 = $(am__DEPENDENCIES_1) \ @@ -301,7 +302,7 @@ top_srcdir = @top_srcdir@ pic32prog_LDADD = $(ADAPTER_OBJ) $(HID_OBJ) $(SER_OBJ) $(am__append_1) \ $(am__append_2) $(am__append_4) pic32prog_DEPENDENCIES = $(ADAPTER_OBJ) $(HID_OBJ) $(SER_OBJ) -pic32prog_SOURCES = pic32prog.c configure.c executive.c target.c families/family-mz.c families/family-mx1.c families/family-mx3.c +pic32prog_SOURCES = pic32prog.c configure.c executive.c target.c families/family-mz.c families/family-mx1.c families/family-mx3.c families/family-xlp.c pic32prog_CFLAGS = -DGITCOUNT='"$(GITCOUNT)"' $(am__append_3) EXTRA_pic32prog_SOURCES = hid/linux/hid.c hid/mac/hid.c hid/windows/hid.c hid/bsd/hid.c adapters/adapter-an1388.c adapters/adapter-an1388-uart.c adapters/adapter-bitbang.c adapters/adapter-hidboot.c adapters/adapter-mpsse.c adapters/adapter-pickit2.c adapters/adapter-stk500v2.c adapters/adapter-uhb.c serial.c @LINUX_TRUE@pic32prog_LDFLAGS = -Wl,-start-group $(LIBUSB_STATIC) @@ -387,6 +388,7 @@ families/$(am__dirstamp): families/pic32prog-family-mz.$(OBJEXT): families/$(am__dirstamp) families/pic32prog-family-mx1.$(OBJEXT): families/$(am__dirstamp) families/pic32prog-family-mx3.$(OBJEXT): families/$(am__dirstamp) +families/pic32prog-family-xlp.$(OBJEXT): families/$(am__dirstamp) hid/linux/$(am__dirstamp): @$(MKDIR_P) hid/linux @: > hid/linux/$(am__dirstamp) @@ -484,6 +486,12 @@ families/pic32prog-family-mx3.o: families/family-mx3.c families/pic32prog-family-mx3.obj: families/family-mx3.c $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(pic32prog_CFLAGS) $(CFLAGS) -c -o families/pic32prog-family-mx3.obj `if test -f 'families/family-mx3.c'; then $(CYGPATH_W) 'families/family-mx3.c'; else $(CYGPATH_W) '$(srcdir)/families/family-mx3.c'; fi` +families/pic32prog-family-xlp.o: families/family-xlp.c + $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(pic32prog_CFLAGS) $(CFLAGS) -c -o families/pic32prog-family-xlp.o `test -f 'families/family-xlp.c' || echo '$(srcdir)/'`families/family-xlp.c + +families/pic32prog-family-xlp.obj: families/family-xlp.c + $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(pic32prog_CFLAGS) $(CFLAGS) -c -o families/pic32prog-family-xlp.obj `if test -f 'families/family-xlp.c'; then $(CYGPATH_W) 'families/family-xlp.c'; else $(CYGPATH_W) '$(srcdir)/families/family-xlp.c'; fi` + hid/linux/pic32prog-hid.o: hid/linux/hid.c $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(pic32prog_CFLAGS) $(CFLAGS) -c -o hid/linux/pic32prog-hid.o `test -f 'hid/linux/hid.c' || echo '$(srcdir)/'`hid/linux/hid.c diff --git a/src/families/family-xlp.c b/src/families/family-xlp.c new file mode 100644 index 0000000..cac0691 --- /dev/null +++ b/src/families/family-xlp.c @@ -0,0 +1,412 @@ +/* + * Routines specific for PIC32 MXx7x XLP family. + * + * Copyright (C) 2013 Serge Vakulenko + * Copyright (C) 2015-2017 Majenko Technologies + * + * This file is part of PIC32PROG project, which is distributed + * under the terms of the GNU General Public License (GPL). + * See the accompanying file "COPYING" for more details. + */ +#include +#include "pic32.h" + +/* + * Print configuration for XLP/2 XLP family. + */ +void print_xlp(unsigned cfg0, unsigned cfg1, unsigned cfg2, unsigned cfg3) +{ + /*-------------------------------------- + * Configuration register 0 + */ + printf(" DEVCFG0 = %08x\n", cfg0); + if ((~cfg0 & XLP_CFG0_DEBUG_MASK) == XLP_CFG0_DEBUG_ENABLED) + printf(" %u Debugger enabled\n", + cfg0 & XLP_CFG0_DEBUG_MASK); + else + printf(" %u Debugger disabled\n", + cfg0 & XLP_CFG0_DEBUG_MASK); + + if (~cfg0 & XLP_CFG0_JTAG_DISABLE) + printf(" %u JTAG disabled\n", + cfg0 & XLP_CFG0_JTAG_DISABLE); + + switch (~cfg0 & XLP_CFG0_ICESEL_MASK) { + case XLP_CFG0_ICESEL_PAIR1: + printf(" %02x Use PGC1/PGD1\n", cfg0 & XLP_CFG0_ICESEL_MASK); + break; + case XLP_CFG0_ICESEL_PAIR2: + printf(" %02x Use PGC2/PGD2\n", cfg0 & XLP_CFG0_ICESEL_MASK); + break; + case XLP_CFG0_ICESEL_PAIR3: + printf(" %02x Use PGC3/PGD3\n", cfg0 & XLP_CFG0_ICESEL_MASK); + break; + case XLP_CFG0_ICESEL_PAIR4: + printf(" %02x Use PGC4/PGD4\n", cfg0 & XLP_CFG0_ICESEL_MASK); + break; + } + + if (~cfg0 & XLP_CFG0_PWP_MASK) + printf(" %05x Program flash write protect\n", + cfg0 & XLP_CFG0_PWP_MASK); + + if (~cfg0 & XLP_CFG0_SMCLR) + printf(" MCLR generates POR\n"); + if (~cfg0 & XLP_CFG0_BWP) + printf(" Boot flash write protect\n"); + if (~cfg0 & XLP_CFG0_CP) + printf(" Code protect\n"); + + + /*-------------------------------------- + * Configuration register 1 + */ + printf(" DEVCFG1 = %08x\n", cfg1); + switch (cfg1 & XLP_CFG1_FNOSC_MASK) { + case XLP_CFG1_FNOSC_FRC: + printf(" %u Fast RC Oscillator\n", XLP_CFG1_FNOSC_FRC); + break; + + case XLP_CFG1_FNOSC_FRCPLL: + printf(" %u Fast RC Oscillator with divide-by-N with PLL\n", XLP_CFG1_FNOSC_FRCPLL); + break; + + case XLP_CFG1_FNOSC_PRI: + printf(" %u Primary Oscillator\n", XLP_CFG1_FNOSC_PRI); + break; + + case XLP_CFG1_FNOSC_PRIPLL: + printf(" %u Primary Oscillator with PLL\n", XLP_CFG1_FNOSC_PRIPLL); + break; + + case XLP_CFG1_FNOSC_SOSC: + printf(" %u Secondary Oscillator\n", XLP_CFG1_FNOSC_SOSC); + break; + + case XLP_CFG1_FNOSC_LPRC: + printf(" %u Low-Power RC Oscillator\n", XLP_CFG1_FNOSC_LPRC); + break; + + case XLP_CFG1_FNOSC_FRCDIV16: + printf(" %u Fast RC Oscillator with fixed divide-by-16 postscaler\n", XLP_CFG1_FNOSC_FRCDIV16); + break; + + case XLP_CFG1_FNOSC_FRCDIV: + printf(" %u Fast RC Oscillator with divide-by-N\n", XLP_CFG1_FNOSC_FRCDIV); + break; + } + + if (cfg1 & XLP_CFG1_FSOSCEN) + printf(" %u Secondary oscillator enabled\n", + XLP_CFG1_FSOSCEN >> 4); + if (cfg1 & XLP_CFG1_IESO) + printf(" %u Internal-external switch over enabled\n", + XLP_CFG1_IESO >> 4); + + switch (cfg1 & XLP_CFG1_POSCMOD_MASK) { + case XLP_CFG1_POSCMOD_EXT: + printf(" %u Primary oscillator: External\n", XLP_CFG1_POSCMOD_EXT >> 8); + break; + case XLP_CFG1_POSCMOD_XT: + printf(" %u Primary oscillator: XT\n", XLP_CFG1_POSCMOD_XT >> 8); + break; + case XLP_CFG1_POSCMOD_HS: + printf(" %u Primary oscillator: HS\n", XLP_CFG1_POSCMOD_HS >> 8); + break; + case XLP_CFG1_POSCMOD_DISABLE: + printf(" %u Primary oscillator: disabled\n", XLP_CFG1_POSCMOD_DISABLE >> 8); + break; + } + if (cfg1 & XLP_CFG1_CLKO_DISABLE) + printf(" %u CLKO output disabled\n", + XLP_CFG1_CLKO_DISABLE >> 8); + + switch (cfg1 & XLP_CFG1_FPBDIV_MASK) { + case XLP_CFG1_FPBDIV_1: + printf(" %u Peripheral bus clock: SYSCLK / 1\n", XLP_CFG1_FPBDIV_1 >> 12); + break; + case XLP_CFG1_FPBDIV_2: + printf(" %u Peripheral bus clock: SYSCLK / 2\n", XLP_CFG1_FPBDIV_2 >> 12); + break; + case XLP_CFG1_FPBDIV_4: + printf(" %u Peripheral bus clock: SYSCLK / 4\n", XLP_CFG1_FPBDIV_4 >> 12); + break; + case XLP_CFG1_FPBDIV_8: + printf(" %u Peripheral bus clock: SYSCLK / 8\n", XLP_CFG1_FPBDIV_8 >> 12); + break; + } + if (cfg1 & XLP_CFG1_FCKM_ENABLE) + printf(" %u Fail-safe clock monitor enabled\n", XLP_CFG1_FCKM_ENABLE >> 12); + if (cfg1 & XLP_CFG1_FCKS_ENABLE) + printf(" %u Clock switching enabled\n", XLP_CFG1_FCKS_ENABLE >> 12); + + switch (cfg1 & XLP_CFG1_WDTPS_MASK) { + case XLP_CFG1_WDTPS_1: + printf(" %2x Watchdog postscale: 1/1\n", XLP_CFG1_WDTPS_1 >> 16); + break; + case XLP_CFG1_WDTPS_2: + printf(" %2x Watchdog postscale: 1/2\n", XLP_CFG1_WDTPS_2 >> 16); + break; + case XLP_CFG1_WDTPS_4: + printf(" %2x Watchdog postscale: 1/4\n", XLP_CFG1_WDTPS_4 >> 16); + break; + case XLP_CFG1_WDTPS_8: + printf(" %2x Watchdog postscale: 1/8\n", XLP_CFG1_WDTPS_8 >> 16); + break; + case XLP_CFG1_WDTPS_16: + printf(" %2x Watchdog postscale: 1/16\n", XLP_CFG1_WDTPS_16 >> 16); + break; + case XLP_CFG1_WDTPS_32: + printf(" %2x Watchdog postscale: 1/32\n", XLP_CFG1_WDTPS_32 >> 16); + break; + case XLP_CFG1_WDTPS_64: + printf(" %2x Watchdog postscale: 1/64\n", XLP_CFG1_WDTPS_64 >> 16); + break; + case XLP_CFG1_WDTPS_128: + printf(" %2x Watchdog postscale: 1/128\n", XLP_CFG1_WDTPS_128 >> 16); + break; + case XLP_CFG1_WDTPS_256: + printf(" %2x Watchdog postscale: 1/256\n", XLP_CFG1_WDTPS_256 >> 16); + break; + case XLP_CFG1_WDTPS_512: + printf(" %2x Watchdog postscale: 1/512\n", XLP_CFG1_WDTPS_512 >> 16); + break; + case XLP_CFG1_WDTPS_1024: + printf(" %2x Watchdog postscale: 1/1024\n", XLP_CFG1_WDTPS_1024 >> 16); + break; + case XLP_CFG1_WDTPS_2048: + printf(" %2x Watchdog postscale: 1/2048\n", XLP_CFG1_WDTPS_2048 >> 16); + break; + case XLP_CFG1_WDTPS_4096: + printf(" %2x Watchdog postscale: 1/4096\n", XLP_CFG1_WDTPS_4096 >> 16); + break; + case XLP_CFG1_WDTPS_8192: + printf(" %2x Watchdog postscale: 1/8192\n", XLP_CFG1_WDTPS_8192 >> 16); + break; + case XLP_CFG1_WDTPS_16384: + printf(" %2x Watchdog postscale: 1/16384\n", XLP_CFG1_WDTPS_16384 >> 16); + break; + case XLP_CFG1_WDTPS_32768: + printf(" %2x Watchdog postscale: 1/32768\n", XLP_CFG1_WDTPS_32768 >> 16); + break; + case XLP_CFG1_WDTPS_65536: + printf(" %2x Watchdog postscale: 1/65536\n", XLP_CFG1_WDTPS_65536 >> 16); + break; + case XLP_CFG1_WDTPS_131072: + printf(" %2x Watchdog postscale: 1/131072\n", XLP_CFG1_WDTPS_131072 >> 16); + break; + case XLP_CFG1_WDTPS_262144: + printf(" %2x Watchdog postscale: 1/262144\n", XLP_CFG1_WDTPS_262144 >> 16); + break; + case XLP_CFG1_WDTPS_524288: + printf(" %2x Watchdog postscale: 1/524288\n", XLP_CFG1_WDTPS_524288 >> 16); + break; + case XLP_CFG1_WDTPS_1048576: + printf(" %2x Watchdog postscale: 1/1048576\n", XLP_CFG1_WDTPS_1048576 >> 16); + break; + } + + if (cfg1 & XLP_CFG1_WDTSPGM) + printf(" %u Watchdog timer stops during flash programming\n", XLP_CFG1_WDTSPGM >> 20); + + if (cfg1 & XLP_CFG1_WINDIS) + printf(" %u Watchdog in non-Window mode\n", XLP_CFG1_WINDIS >> 20); + else { + printf(" %u Watchdog in Window mode\n", XLP_CFG1_WINDIS >> 20); + switch(cfg1 & XLP_CFG1_FWDTWINSZ_MASK) { + case XLP_CFG1_FWDTWINSZ_75: + printf(" %u Window size is 75%%\n", XLP_CFG1_FWDTWINSZ_75 >> 24); + break; + case XLP_CFG1_FWDTWINSZ_50: + printf(" %u Window size is 50%%\n", XLP_CFG1_FWDTWINSZ_50 >> 24); + break; + case XLP_CFG1_FWDTWINSZ_37: + printf(" %u Window size is 37.5%%\n", XLP_CFG1_FWDTWINSZ_37 >> 24); + break; + case XLP_CFG1_FWDTWINSZ_25: + printf(" %u Window size is 25%%\n", XLP_CFG1_FWDTWINSZ_25 >> 24); + break; + } + } + + if (cfg1 & XLP_CFG1_FWDTEN) + printf(" %u Watchdog enable\n", XLP_CFG1_FWDTEN >> 20); + + + /*-------------------------------------- + * Configuration register 2 + */ + printf(" DEVCFG2 = %08x\n", cfg2); + switch (cfg2 & XLP_CFG2_FPLLIDIV_MASK) { + case XLP_CFG2_FPLLIDIV_1: + printf(" %u PLL divider: 1/1\n", XLP_CFG2_FPLLIDIV_1); + break; + case XLP_CFG2_FPLLIDIV_2: + printf(" %u PLL divider: 1/2\n", XLP_CFG2_FPLLIDIV_2); + break; + case XLP_CFG2_FPLLIDIV_3: + printf(" %u PLL divider: 1/3\n", XLP_CFG2_FPLLIDIV_3); + break; + case XLP_CFG2_FPLLIDIV_4: + printf(" %u PLL divider: 1/4\n", XLP_CFG2_FPLLIDIV_4); + break; + case XLP_CFG2_FPLLIDIV_5: + printf(" %u PLL divider: 1/5\n", XLP_CFG2_FPLLIDIV_5); + break; + case XLP_CFG2_FPLLIDIV_6: + printf(" %u PLL divider: 1/6\n", XLP_CFG2_FPLLIDIV_6); + break; + case XLP_CFG2_FPLLIDIV_10: + printf(" %u PLL divider: 1/10\n", XLP_CFG2_FPLLIDIV_10); + break; + case XLP_CFG2_FPLLIDIV_12: + printf(" %u PLL divider: 1/12\n", XLP_CFG2_FPLLIDIV_12); + break; + } + switch (cfg2 & XLP_CFG2_FPLLMUL_MASK) { + case XLP_CFG2_FPLLMUL_15: + printf(" %u PLL multiplier: 15x\n", XLP_CFG2_FPLLMUL_15 >> 4); + break; + case XLP_CFG2_FPLLMUL_16: + printf(" %u PLL multiplier: 16x\n", XLP_CFG2_FPLLMUL_16 >> 4); + break; + case XLP_CFG2_FPLLMUL_17: + printf(" %u PLL multiplier: 17x\n", XLP_CFG2_FPLLMUL_17 >> 4); + break; + case XLP_CFG2_FPLLMUL_18: + printf(" %u PLL multiplier: 18x\n", XLP_CFG2_FPLLMUL_18 >> 4); + break; + case XLP_CFG2_FPLLMUL_19: + printf(" %u PLL multiplier: 19x\n", XLP_CFG2_FPLLMUL_19 >> 4); + break; + case XLP_CFG2_FPLLMUL_20: + printf(" %u PLL multiplier: 20x\n", XLP_CFG2_FPLLMUL_20 >> 4); + break; + case XLP_CFG2_FPLLMUL_21: + printf(" %u PLL multiplier: 21x\n", XLP_CFG2_FPLLMUL_21 >> 4); + break; + case XLP_CFG2_FPLLMUL_24: + printf(" %u PLL multiplier: 24x\n", XLP_CFG2_FPLLMUL_24 >> 4); + break; + } + if (cfg2 & XLP_CFG2_FPLLICLK) { + printf(" %x FRC is selected as input to the System PLL\n", XLP_CFG2_FPLLICLK >> 4); + } else { + printf(" %x POSC is selected as input to the System PLL\n", 0); + } + + switch (cfg2 & XLP_CFG2_UPLLIDIV_MASK) { + case XLP_CFG2_UPLLIDIV_1: + printf(" %u USB PLL divider: 1/1\n", XLP_CFG2_UPLLIDIV_1 >> 8); + break; + case XLP_CFG2_UPLLIDIV_2: + printf(" %u USB PLL divider: 1/2\n", XLP_CFG2_UPLLIDIV_2 >> 8); + break; + case XLP_CFG2_UPLLIDIV_3: + printf(" %u USB PLL divider: 1/3\n", XLP_CFG2_UPLLIDIV_3 >> 8); + break; + case XLP_CFG2_UPLLIDIV_4: + printf(" %u USB PLL divider: 1/4\n", XLP_CFG2_UPLLIDIV_4 >> 8); + break; + case XLP_CFG2_UPLLIDIV_5: + printf(" %u USB PLL divider: 1/5\n", XLP_CFG2_UPLLIDIV_5 >> 8); + break; + case XLP_CFG2_UPLLIDIV_6: + printf(" %u USB PLL divider: 1/6\n", XLP_CFG2_UPLLIDIV_6 >> 8); + break; + case XLP_CFG2_UPLLIDIV_10: + printf(" %u USB PLL divider: 1/10\n", XLP_CFG2_UPLLIDIV_10 >> 8); + break; + case XLP_CFG2_UPLLIDIV_12: + printf(" %u USB PLL divider: 1/12\n", XLP_CFG2_UPLLIDIV_12 >> 8); + break; + } + if (cfg2 & XLP_CFG2_UPLL_DISABLE) + printf(" %u Disable USB PLL\n", + XLP_CFG2_UPLL_DISABLE >> 12); + else + printf(" Enable USB PLL\n"); + + switch (cfg2 & XLP_CFG2_FPLLODIV_MASK) { + case XLP_CFG2_FPLLODIV_1: + printf(" %u PLL postscaler: 1/1\n", XLP_CFG2_FPLLODIV_1 >> 16); + break; + case XLP_CFG2_FPLLODIV_2: + printf(" %u PLL postscaler: 1/2\n", XLP_CFG2_FPLLODIV_2 >> 16); + break; + case XLP_CFG2_FPLLODIV_4: + printf(" %u PLL postscaler: 1/4\n", XLP_CFG2_FPLLODIV_4 >> 16); + break; + case XLP_CFG2_FPLLODIV_8: + printf(" %u PLL postscaler: 1/8\n", XLP_CFG2_FPLLODIV_8 >> 16); + break; + case XLP_CFG2_FPLLODIV_16: + printf(" %u PLL postscaler: 1/16\n", XLP_CFG2_FPLLODIV_16 >> 16); + break; + case XLP_CFG2_FPLLODIV_32: + printf(" %u PLL postscaler: 1/32\n", XLP_CFG2_FPLLODIV_32 >> 16); + break; + case XLP_CFG2_FPLLODIV_64: + printf(" %u PLL postscaler: 1/64\n", XLP_CFG2_FPLLODIV_64 >> 16); + break; + case XLP_CFG2_FPLLODIV_256: + printf(" %u PLL postscaler: 1/128\n", XLP_CFG2_FPLLODIV_256 >> 16); + break; + } + + if (cfg2 & XLP_CFG2_BOREN) + printf(" %x Brown-Out Reset Enabled\n", XLP_CFG2_BOREN >> 20); + + if (cfg2 & XLP_CFG2_VBATBOREN) + printf(" %x VBAT BOR Enabled\n", XLP_CFG2_VBATBOREN >> 20); + + if (cfg2 & XLP_CFG2_DSBOREN) + printf(" %x Deep Sleep BOR Enabled\n", XLP_CFG2_DSBOREN >> 20); + + if (cfg2 & XLP_CFG2_DSWDTEN) { + printf(" %2x Deep Sleep Watchdog Postscale 1:2^%d\n", (cfg2 & XLP_CFG2_DSWDTPS_MASK) >> 24, 5 + ((cfg2 & XLP_CFG2_DSWDTPS_MASK) >> 24)); + if (cfg2 & XLP_CFG2_DSWDTOSC) { + printf(" %x Deep Sleep Watchdog Clock is LPRC\n", XLP_CFG2_DSWDTOSC >> 28); + } else { + printf(" %x Deep Sleep Watchdog Clock is SOSC\n", 0); + } + printf(" %x Deep Sleep Watchdog Enabled\n", XLP_CFG2_DSWDTEN >> 28); + } + if (cfg2 & XLP_CFG2_FDSEN) { + printf(" %x Deep Sleep Enabled\n", XLP_CFG2_FDSEN >> 28); + } + + + + /*-------------------------------------- + * Configuration register 3 + */ + printf(" DEVCFG3 = %08x\n", cfg3); + if (~cfg3 & XLP_CFG3_USERID_MASK) + printf(" %04x User-defined ID\n", + cfg3 & XLP_CFG3_USERID_MASK); + + if (cfg3 & XLP_CFG3_PMDL1WAY) + printf(" %u Peripheral Module Disable - only 1 reconfig\n", + XLP_CFG3_PMDL1WAY >> 28); + else + printf(" USBID pin: controlled by port\n"); + + if (cfg3 & XLP_CFG3_IOL1WAY) + printf(" %u Peripheral Pin Select - only 1 reconfig\n", + XLP_CFG3_IOL1WAY >> 28); + else + printf(" USBID pin: controlled by port\n"); + + if (cfg3 & XLP_CFG3_FUSBIDIO) + printf(" %u USBID pin: controlled by USB\n", + XLP_CFG3_FUSBIDIO >> 28); + else + printf(" USBID pin: controlled by port\n"); + + if (cfg3 & XLP_CFG3_FVBUSONIO) + printf(" %u VBuson pin: controlled by USB\n", + XLP_CFG3_FVBUSONIO >> 28); + else + printf(" VBuson pin: controlled by port\n"); +} diff --git a/src/include/pic32.h b/src/include/pic32.h index e9f6c86..d3c0adb 100644 --- a/src/include/pic32.h +++ b/src/include/pic32.h @@ -486,4 +486,167 @@ extern const unsigned pic32_pemz[]; #define MX1_CFG3_FUSBIDIO 0x40000000 /* USBID pin: controlled by USB */ #define MX1_CFG3_FVBUSONIO 0x80000000 /* VBuson pin: controlled by USB */ + +/*------------------------------------------------------------------- + * MX[1/2]7x XLP family. + * + * Config0 register, inverted. + */ +#define XLP_CFG0_DEBUG_MASK 0x00000003 /* Debugger enable bits */ +#define XLP_CFG0_DEBUG_DISABLED 0x00000000 /* Debugger disabled */ +#define XLP_CFG0_DEBUG_ENABLED 0x00000002 /* Debugger enabled */ + +#define XLP_CFG0_JTAG_DISABLE 0x00000004 /* Disable JTAG port */ + +#define XLP_CFG0_ICESEL_MASK 0x00000018 /* Debugger channel select */ +#define XLP_CFG0_ICESEL_PAIR1 0x00000000 /* Use PGC1/PGD1 */ +#define XLP_CFG0_ICESEL_PAIR2 0x00000008 /* Use PGC2/PGD2 */ +#define XLP_CFG0_ICESEL_PAIR3 0x00000010 /* Use PGC3/PGD3 */ +#define XLP_CFG0_ICESEL_PAIR4 0x00000018 /* Use PGC4/PGD4 */ + +#define XLP_CFG0_PWP_MASK 0x000ff000 /* Program flash write protect */ +#define XLP_CFG0_SMCLR 0x00800000 /* Soft Master Clear Enable */ +#define XLP_CFG0_BWP 0x01000000 /* Boot flash write protect */ +#define XLP_CFG0_CP 0x10000000 /* Code protect */ + +/* + * Config1 register. + */ + +#define XLP_CFG1_FNOSC_MASK 0x00000007 /* Oscillator selection */ +#define XLP_CFG1_FNOSC_FRC 0x00000000 /* Fast RC Oscillator */ +#define XLP_CFG1_FNOSC_FRCPLL 0x00000001 /* Fast RC Oscillator with divide-by-N with PLL module */ +#define XLP_CFG1_FNOSC_PRI 0x00000002 /* Primary Oscillator */ +#define XLP_CFG1_FNOSC_PRIPLL 0x00000003 /* Primary Oscillator with PLL module */ +#define XLP_CFG1_FNOSC_SOSC 0x00000004 /* Secondary Oscillator */ +#define XLP_CFG1_FNOSC_LPRC 0x00000005 /* Low-Power RC Oscillator */ +#define XLP_CFG1_FNOSC_FRCDIV16 0x00000006 /* Fast RC Oscillator with fixed divide-by-16 postscaler */ +#define XLP_CFG1_FNOSC_FRCDIV 0x00000007 /* Fast RC Oscillator with divide-by-N */ + +#define XLP_CFG1_FSOSCEN 0x00000020 /* Secondary oscillator enable */ + +#define XLP_CFG1_IESO 0x00000080 /* Internal-external switch over */ + +#define XLP_CFG1_POSCMOD_MASK 0x00000300 /* Primary oscillator config */ +#define XLP_CFG1_POSCMOD_EXT 0x00000000 /* External mode */ +#define XLP_CFG1_POSCMOD_XT 0x00000100 /* XT oscillator */ +#define XLP_CFG1_POSCMOD_HS 0x00000200 /* HS oscillator */ +#define XLP_CFG1_POSCMOD_DISABLE 0x00000300 /* Disabled */ + +#define XLP_CFG1_CLKO_DISABLE 0x00000400 /* Disable CLKO output */ + +#define XLP_CFG1_FPBDIV_MASK 0x00003000 /* Peripheral bus clock divisor */ +#define XLP_CFG1_FPBDIV_1 0x00000000 /* SYSCLK / 1 */ +#define XLP_CFG1_FPBDIV_2 0x00001000 /* SYSCLK / 2 */ +#define XLP_CFG1_FPBDIV_4 0x00002000 /* SYSCLK / 4 */ +#define XLP_CFG1_FPBDIV_8 0x00003000 /* SYSCLK / 8 */ + +#define XLP_CFG1_FCKS_ENABLE 0x00004000 /* Clock switching enable */ + +#define XLP_CFG1_FCKM_ENABLE 0x00008000 /* Fail-safe clock monitor enable */ + +#define XLP_CFG1_WDTPS_MASK 0x001f0000 /* Watchdog postscale */ +#define XLP_CFG1_WDTPS_1 0x00000000 /* 1:1 */ +#define XLP_CFG1_WDTPS_2 0x00010000 /* 1:2 */ +#define XLP_CFG1_WDTPS_4 0x00020000 /* 1:4 */ +#define XLP_CFG1_WDTPS_8 0x00030000 /* 1:8 */ +#define XLP_CFG1_WDTPS_16 0x00040000 /* 1:16 */ +#define XLP_CFG1_WDTPS_32 0x00050000 /* 1:32 */ +#define XLP_CFG1_WDTPS_64 0x00060000 /* 1:64 */ +#define XLP_CFG1_WDTPS_128 0x00070000 /* 1:128 */ +#define XLP_CFG1_WDTPS_256 0x00080000 /* 1:256 */ +#define XLP_CFG1_WDTPS_512 0x00090000 /* 1:512 */ +#define XLP_CFG1_WDTPS_1024 0x000a0000 /* 1:1024 */ +#define XLP_CFG1_WDTPS_2048 0x000b0000 /* 1:2048 */ +#define XLP_CFG1_WDTPS_4096 0x000c0000 /* 1:4096 */ +#define XLP_CFG1_WDTPS_8192 0x000d0000 /* 1:8192 */ +#define XLP_CFG1_WDTPS_16384 0x000e0000 /* 1:16384 */ +#define XLP_CFG1_WDTPS_32768 0x000f0000 /* 1:32768 */ +#define XLP_CFG1_WDTPS_65536 0x00100000 /* 1:65536 */ +#define XLP_CFG1_WDTPS_131072 0x00110000 /* 1:131072 */ +#define XLP_CFG1_WDTPS_262144 0x00120000 /* 1:262144 */ +#define XLP_CFG1_WDTPS_524288 0x00130000 /* 1:524288 */ +#define XLP_CFG1_WDTPS_1048576 0x00140000 /* 1:1048576 */ + +#define XLP_CFG1_WDTSPGM 0x00200000 /* Watchdog Timer Stop During Flash Programming */ + +#define XLP_CFG1_WINDIS 0x00400000 /* Watchdog is in non-Window mode */ + +#define XLP_CFG1_FWDTEN 0x00800000 /* Watchdog enable */ +#define XLP_CFG1_FWDTWINSZ_MASK 0x03000000 /* Watchdog Timer Window Size */ +#define XLP_CFG1_FWDTWINSZ_75 0x00000000 /* 75% */ +#define XLP_CFG1_FWDTWINSZ_50 0x01000000 /* 50% */ +#define XLP_CFG1_FWDTWINSZ_37 0x02000000 /* 37.5% */ +#define XLP_CFG1_FWDTWINSZ_25 0x03000000 /* 25% */ + +/* + * Config2 register. + */ +#define XLP_CFG2_FPLLIDIV_MASK 0x00000007 /* PLL input divider */ +#define XLP_CFG2_FPLLIDIV_1 0x00000000 /* 1x */ +#define XLP_CFG2_FPLLIDIV_2 0x00000001 /* 2x */ +#define XLP_CFG2_FPLLIDIV_3 0x00000002 /* 3x */ +#define XLP_CFG2_FPLLIDIV_4 0x00000003 /* 4x */ +#define XLP_CFG2_FPLLIDIV_5 0x00000004 /* 5x */ +#define XLP_CFG2_FPLLIDIV_6 0x00000005 /* 6x */ +#define XLP_CFG2_FPLLIDIV_10 0x00000006 /* 10x */ +#define XLP_CFG2_FPLLIDIV_12 0x00000007 /* 12x */ + +#define XLP_CFG2_FPLLMUL_MASK 0x00000070 /* PLL multiplier */ +#define XLP_CFG2_FPLLMUL_15 0x00000000 /* 15x */ +#define XLP_CFG2_FPLLMUL_16 0x00000010 /* 16x */ +#define XLP_CFG2_FPLLMUL_17 0x00000020 /* 17x */ +#define XLP_CFG2_FPLLMUL_18 0x00000030 /* 18x */ +#define XLP_CFG2_FPLLMUL_19 0x00000040 /* 19x */ +#define XLP_CFG2_FPLLMUL_20 0x00000050 /* 20x */ +#define XLP_CFG2_FPLLMUL_21 0x00000060 /* 21x */ +#define XLP_CFG2_FPLLMUL_24 0x00000070 /* 24x */ + +#define XLP_CFG2_FPLLICLK 0x00000080 /* System PLL Input Clock Select */ + +#define XLP_CFG2_UPLLIDIV_MASK 0x00000700 /* USB PLL input divider */ +#define XLP_CFG2_UPLLIDIV_1 0x00000000 /* 1x */ +#define XLP_CFG2_UPLLIDIV_2 0x00000100 /* 2x */ +#define XLP_CFG2_UPLLIDIV_3 0x00000200 /* 3x */ +#define XLP_CFG2_UPLLIDIV_4 0x00000300 /* 4x */ +#define XLP_CFG2_UPLLIDIV_5 0x00000400 /* 5x */ +#define XLP_CFG2_UPLLIDIV_6 0x00000500 /* 6x */ +#define XLP_CFG2_UPLLIDIV_10 0x00000600 /* 10x */ +#define XLP_CFG2_UPLLIDIV_12 0x00000700 /* 12x */ + +#define XLP_CFG2_UPLL_DISABLE 0x00008000 /* Disable and bypass USB PLL */ + +#define XLP_CFG2_FPLLODIV_MASK 0x00070000 /* Default postscaler for PLL */ +#define XLP_CFG2_FPLLODIV_1 0x00000000 /* 1x */ +#define XLP_CFG2_FPLLODIV_2 0x00010000 /* 2x */ +#define XLP_CFG2_FPLLODIV_4 0x00020000 /* 4x */ +#define XLP_CFG2_FPLLODIV_8 0x00030000 /* 8x */ +#define XLP_CFG2_FPLLODIV_16 0x00040000 /* 16x */ +#define XLP_CFG2_FPLLODIV_32 0x00050000 /* 32x */ +#define XLP_CFG2_FPLLODIV_64 0x00060000 /* 64x */ +#define XLP_CFG2_FPLLODIV_256 0x00070000 /* 256x */ + +#define XLP_CFG2_BOREN 0x00100000 /* Brown-Out Reset (BOR) Enable */ +#define XLP_CFG2_VBATBOREN 0x00200000 /* VBAT BOR Enable */ +#define XLP_CFG2_DSBOREN 0x00800000 /* Deep Sleep BOR Enable */ + +#define XLP_CFG2_DSWDTPS_MASK 0x1F000000 /* Deep sleep watchdog timer postscale */ + /* 1:2^(5+N) */ + +#define XLP_CFG2_DSWDTOSC 0x20000000 /* Deep Sleep Watchdog Timer Reference Clock Select */ +#define XLP_CFG2_DSWDTEN 0x40000000 /* Deep Sleep Watchdog Timer Enable */ +#define XLP_CFG2_FDSEN 0x80000000 /* Deep Sleep Enable */ + +/* + * Config3 register. + */ + +#define XLP_CFG3_USERID_MASK 0x0000ffff /* User-defined ID */ +#define XLP_CFG3_AI2C1 0x00400000 /* Alternate I/O Select for I2C1 */ +#define XLP_CFG3_AI2C2 0x00800000 /* Alternate I/O Select for I2C2 */ +#define XLP_CFG3_PMDL1WAY 0x10000000 /* Peripheral Module Disable - only 1 reconfig */ +#define XLP_CFG3_IOL1WAY 0x20000000 /* Peripheral Pin Select - only 1 reconfig */ +#define XLP_CFG3_FUSBIDIO 0x40000000 /* USBID pin: controlled by USB */ +#define XLP_CFG3_FVBUSONIO 0x80000000 /* VBuson pin: controlled by USB */ + #endif diff --git a/src/target.c b/src/target.c index 56da512..a07fed5 100644 --- a/src/target.c +++ b/src/target.c @@ -27,6 +27,7 @@ extern print_func_t print_mx1; extern print_func_t print_mx3; extern print_func_t print_mz; +extern print_func_t print_xlp; extern unsigned long open_retries; @@ -39,7 +40,7 @@ family_t family_mx1 = { "mx1", 3, 0x0bf0, 128, print_mx1, pic32_pemx1, 422, 0x0301 }; static const family_t family_xlp = { "xlp", - 12, 0x2ff0, 512, print_mx1, pic32_pemx3, 1044, 0x0201 }; + 12, 0x2ff0, 512, print_xlp, pic32_pemx3, 1044, 0x0201 }; static const family_t family_mx3 = { "mx3", 12, 0x2ff0, 512, print_mx3, pic32_pemx3, 1044, 0x0201 };