From fe23a9a2fee515f94b0f996c2c12bc63703a2078 Mon Sep 17 00:00:00 2001 From: Drew Risinger Date: Tue, 22 Jun 2021 11:23:25 -0400 Subject: [PATCH] spi2: allow optional CS pin in SPIInterface Matches capability in differential versions --- misoc/cores/spi2.py | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/misoc/cores/spi2.py b/misoc/cores/spi2.py index 8ee0b2ae7..ee74a395b 100644 --- a/misoc/cores/spi2.py +++ b/misoc/cores/spi2.py @@ -222,7 +222,7 @@ def __init__(self, data_width=32, div_width=8): class SPIInterface(Module): """Drive one or more SPI buses with a single interface.""" def __init__(self, *pads): - self.cs = Signal(sum(len(p.cs_n) for p in pads)) + self.cs = Signal(sum(len(getattr(p, "cs_n", [0])) for p in pads)) self.cs_polarity = Signal.like(self.cs) self.clk_next = Signal() self.clk_polarity = Signal() @@ -236,7 +236,7 @@ def __init__(self, *pads): i = 0 for p in pads: - n = len(p.cs_n) + n = len(getattr(p, "cs_n", [0])) cs = TSTriple(n) cs.o.reset = C((1 << n) - 1) clk = TSTriple() @@ -244,10 +244,9 @@ def __init__(self, *pads): miso = TSTriple() miso_reg = Signal(reset_less=True) mosi_reg = Signal(reset_less=True) - self.specials += [ - cs.get_tristate(p.cs_n), - clk.get_tristate(p.clk), - ] + self.specials += clk.get_tristate(p.clk) + if hasattr(p, "cs_n"): + self.specials += cs.get_tristate(p.cs_n) if hasattr(p, "mosi"): self.specials += mosi.get_tristate(p.mosi) if hasattr(p, "miso"):