From cf5664f7c4ab567ac66377819a0477cca44a4534 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 16 Jun 2023 14:34:24 +0300 Subject: [PATCH] debugcc: Rework clock muxes into a chain structure Enforcing a primary+leaf configuration does not walk for all the cases. Some clocks (msm8996 CPU) have more muxes to be powered on. Other (MCCC) do not require GCC at all. Make clock measurement more versatile by reworking GCC + optional leaf into a chain of muxes. Signed-off-by: Dmitry Baryshkov --- debugcc.c | 127 ++++------ debugcc.h | 45 +++- msm8936.c | 242 +++++++++---------- msm8994.c | 368 ++++++++++++++-------------- msm8996.c | 527 ++++++++++++++++++++-------------------- msm8998.c | 405 ++++++++++++++++--------------- qcs404.c | 288 ++++++++++++---------- sc8280xp.c | 688 +++++++++++++++++++++++++++-------------------------- sdm845.c | 536 +++++++++++++++++++++-------------------- sm6115.c | 301 ++++++++++++----------- sm6125.c | 450 ++++++++++++++++++----------------- sm6350.c | 329 +++++++++++++------------ sm6375.c | 357 +++++++++++++-------------- sm8150.c | 569 +++++++++++++++++++++++--------------------- sm8250.c | 679 +++++++++++++++++++++++++++------------------------- sm8350.c | 566 ++++++++++++++++++++++--------------------- sm8450.c | 626 ++++++++++++++++++++++++------------------------ sm8550.c | 629 ++++++++++++++++++++++++------------------------ 18 files changed, 3983 insertions(+), 3749 deletions(-) diff --git a/debugcc.c b/debugcc.c index c8e23f3..047cd6c 100644 --- a/debugcc.c +++ b/debugcc.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include #include @@ -42,33 +43,23 @@ #include "debugcc.h" -static uint32_t readl(void *ptr) -{ - return *((volatile uint32_t*)ptr); -} - -static void writel(uint32_t val, void *ptr) -{ - *((volatile uint32_t*)ptr) = val; -} - -static unsigned int measure_ticks(struct debug_mux *gcc, unsigned int ticks) +static unsigned int measure_ticks(struct gcc_mux *gcc, unsigned int ticks) { uint32_t val; - writel(ticks, gcc->base + gcc->debug_ctl_reg); + writel(ticks, gcc->mux.base + gcc->debug_ctl_reg); do { - val = readl(gcc->base + gcc->debug_status_reg); + val = readl(gcc->mux.base + gcc->debug_status_reg); } while (val & BIT(25)); - writel(ticks | BIT(20), gcc->base + gcc->debug_ctl_reg); + writel(ticks | BIT(20), gcc->mux.base + gcc->debug_ctl_reg); do { - val = readl(gcc->base + gcc->debug_status_reg); + val = readl(gcc->mux.base + gcc->debug_status_reg); } while (!(val & BIT(25))); val &= 0x1ffffff; - writel(ticks, gcc->base + gcc->debug_ctl_reg); + writel(ticks, gcc->mux.base + gcc->debug_ctl_reg); return val; } @@ -92,6 +83,9 @@ static void mux_prepare_enable(struct debug_mux *mux, int selector) } mux_enable(mux); + + if (mux->parent) + mux_prepare_enable(mux->parent, mux->parent_mux_val); } void mux_enable(struct debug_mux *mux) @@ -103,17 +97,14 @@ void mux_enable(struct debug_mux *mux) val |= mux->enable_mask; writel(val, mux->base + mux->enable_reg); } - - if (mux->premeasure) - mux->premeasure(mux); } void mux_disable(struct debug_mux *mux) { uint32_t val; - if (mux->postmeasure) - mux->postmeasure(mux); + if (mux->parent) + mux_disable(mux->parent); if (mux->enable_mask) { val = readl(mux->base + mux->enable_reg); @@ -122,35 +113,21 @@ void mux_disable(struct debug_mux *mux) } } -static bool leaf_enabled(struct debug_mux *mux, struct debug_mux *leaf) -{ - uint32_t val; - - /* If no AHB clock is specified, we assume it's clocked */ - if (!leaf || !leaf->ahb_mask) - return true; - - val = readl(mux->base + leaf->ahb_reg); - val &= leaf->ahb_mask; - - /* CLK_OFF will be set if block is not clocked, so inverse */ - return !val; -} - -static unsigned long measure_default(const struct measure_clk *clk) +unsigned long measure_gcc(const struct measure_clk *clk, + const struct debug_mux *mux) { unsigned long raw_count_short; unsigned long raw_count_full; - struct debug_mux *gcc = clk->primary; + struct gcc_mux *gcc = container_of(mux, struct gcc_mux, mux); unsigned long xo_div4; - xo_div4 = readl(gcc->base + gcc->xo_div4_reg); - writel(xo_div4 | 1, gcc->base + gcc->xo_div4_reg); + xo_div4 = readl(mux->base + gcc->xo_div4_reg); + writel(xo_div4 | 1, mux->base + gcc->xo_div4_reg); raw_count_short = measure_ticks(gcc, 0x1000); raw_count_full = measure_ticks(gcc, 0x10000); - writel(xo_div4, gcc->base + gcc->xo_div4_reg); + writel(xo_div4, mux->base + gcc->xo_div4_reg); if (raw_count_full == raw_count_short) { return 0; @@ -159,49 +136,49 @@ static unsigned long measure_default(const struct measure_clk *clk) raw_count_full = ((raw_count_full * 10) + 15) * 4800000; raw_count_full = raw_count_full / ((0x10000 * 10) + 35); - if (clk->leaf && clk->leaf->div_val) - raw_count_full *= clk->leaf->div_val; + if (mux->div_val) + raw_count_full *= mux->div_val; - if (clk->primary->div_val) - raw_count_full *= clk->primary->div_val; + return raw_count_full; +} - if (clk->fixed_div) - raw_count_full *= clk->fixed_div; +unsigned long measure_leaf(const struct measure_clk *clk, + const struct debug_mux *mux) +{ + unsigned long count; + + if (!mux->parent) { + printf("No parent in measure_leaf, mux '%s'\n", mux->block_name ? : "gcc"); + return 0; + } + count = mux->parent->measure(clk, mux->parent); - return raw_count_full; + if (mux->div_val) + count *= mux->div_val; + + return count; } -unsigned long measure_mccc(const struct measure_clk *clk) +unsigned long measure_mccc(const struct measure_clk *clk, + const struct debug_mux *mux) { /* MCCC is always on, just read the rate and return. */ - return 1000000000000ULL / readl(clk->leaf->base + clk->leaf_mux); + return 1000000000000ULL / readl(clk->clk_mux->base + clk->mux); } static void measure(const struct measure_clk *clk) { unsigned long clk_rate; - struct debug_mux *gcc = clk->primary; - - if (!leaf_enabled(gcc, clk->leaf)) { - printf("%50s: skipping\n", clk->name); - return; - } - if (clk->leaf) - mux_prepare_enable(clk->leaf, clk->leaf_mux); + mux_prepare_enable(clk->clk_mux, clk->mux); - mux_prepare_enable(clk->primary, clk->mux); + clk_rate = clk->clk_mux->measure(clk, clk->clk_mux); - if (clk->leaf && clk->leaf->measure) - clk_rate = clk->leaf->measure(clk); - else - clk_rate = measure_default(clk); - - mux_disable(clk->primary); + if (clk->fixed_div) + clk_rate *= clk->fixed_div; - if (clk->leaf) - mux_disable(clk->leaf); + mux_disable(clk->clk_mux); if (clk_rate == 0) { printf("%50s: off\n", clk->name); @@ -265,8 +242,8 @@ static const struct measure_clk *find_clock(const struct debugcc_platform *platf static bool clock_from_block(const struct measure_clk *clk, const char *block_name) { return !block_name || - (!clk->leaf && !strcmp(block_name, CORE_CC_BLOCK)) || - (clk->leaf && clk->leaf->block_name && !strcmp(block_name, clk->leaf->block_name)); + (!clk->clk_mux && !strcmp(block_name, CORE_CC_BLOCK)) || + (clk->clk_mux && clk->clk_mux->block_name && !strcmp(block_name, clk->clk_mux->block_name)); } static void list_clocks_block(const struct debugcc_platform *platform, const char *block_name) @@ -277,8 +254,8 @@ static void list_clocks_block(const struct debugcc_platform *platform, const cha if (!clock_from_block(clk, block_name)) continue; - if (clk->leaf && clk->leaf->block_name) - printf("%-40s %s\n", clk->name, clk->leaf->block_name); + if (clk->clk_mux && clk->clk_mux->block_name) + printf("%-40s %s\n", clk->name, clk->clk_mux->block_name); else printf("%s\n", clk->name); } @@ -296,7 +273,7 @@ int mmap_mux(int devmem, struct debug_mux *mux) return -1; } - return 0; + return mmap_mux(devmem, mux->parent); } /** @@ -312,11 +289,7 @@ static int mmap_hardware(int devmem, const struct debugcc_platform *platform) int ret; for (clk = platform->clocks; clk->name; clk++) { - ret = mmap_mux(devmem, clk->primary); - if (ret < 0) - return ret; - - ret = mmap_mux(devmem, clk->leaf); + ret = mmap_mux(devmem, clk->clk_mux); if (ret < 0) return ret; } diff --git a/debugcc.h b/debugcc.h index 68eda04..8cb220e 100644 --- a/debugcc.h +++ b/debugcc.h @@ -43,6 +43,9 @@ struct debug_mux { const char *block_name; size_t size; + struct debug_mux *parent; + unsigned long parent_mux_val; + unsigned int enable_reg; unsigned int enable_mask; @@ -55,25 +58,22 @@ struct debug_mux { unsigned int div_mask; unsigned int div_val; + unsigned long (*measure)(const struct measure_clk *clk, + const struct debug_mux *mux); +}; + +struct gcc_mux { + struct debug_mux mux; + unsigned int xo_div4_reg; unsigned int debug_ctl_reg; unsigned int debug_status_reg; - - unsigned int ahb_reg; - unsigned int ahb_mask; - - void (*premeasure)(struct debug_mux *mux); - unsigned long (*measure)(const struct measure_clk *clk); - void (*postmeasure)(struct debug_mux *mux); }; struct measure_clk { char *name; - struct debug_mux *primary; - int mux; - - struct debug_mux *leaf; - int leaf_mux; + struct debug_mux *clk_mux; + unsigned long mux; unsigned int fixed_div; }; @@ -84,10 +84,29 @@ struct debugcc_platform { int (*premap)(int devmem); }; +#define container_of(ptr, type, member) \ + ((type *) ((char *)(ptr) - offsetof(type, member))) + +static inline uint32_t readl(void *ptr) +{ + return *((volatile uint32_t*)ptr); +} + +static inline void writel(uint32_t val, void *ptr) +{ + *((volatile uint32_t*)ptr) = val; +} + int mmap_mux(int devmem, struct debug_mux *mux); void mux_enable(struct debug_mux *mux); void mux_disable(struct debug_mux *mux); -unsigned long measure_mccc(const struct measure_clk *clk); + +unsigned long measure_gcc(const struct measure_clk *clk, + const struct debug_mux *mux); +unsigned long measure_leaf(const struct measure_clk *clk, + const struct debug_mux *mux); +unsigned long measure_mccc(const struct measure_clk *clk, + const struct debug_mux *mux); extern const struct debugcc_platform *platforms[]; diff --git a/msm8936.c b/msm8936.c index ff8ac5d..cd364c0 100644 --- a/msm8936.c +++ b/msm8936.c @@ -49,22 +49,24 @@ #define GCC_CLOCK_FREQ_MEASURE_STATUS 0x74008 #define GCC_XO_DIV4_CBCR 0x30034 -static struct debug_mux gcc; +static struct gcc_mux gcc = { + .mux = { + .phys = GCC_BASE, + .size = GCC_SIZE, -static struct debug_mux gcc = { - .phys = GCC_BASE, - .size = GCC_SIZE, + .measure = measure_gcc, - .enable_reg = GCC_DEBUG_CLK_CTL, - .enable_mask = BIT(16), + .enable_reg = GCC_DEBUG_CLK_CTL, + .enable_mask = BIT(16), - .mux_reg = GCC_DEBUG_CLK_CTL, - .mux_mask = 0x1ff, + .mux_reg = GCC_DEBUG_CLK_CTL, + .mux_mask = 0x1ff, - .div_reg = GCC_DEBUG_CLK_CTL, - .div_shift = 12, - .div_mask = 0xf << 12, - .div_val = 4, + .div_reg = GCC_DEBUG_CLK_CTL, + .div_shift = 12, + .div_mask = 0xf << 12, + .div_val = 4, + }, .xo_div4_reg = GCC_XO_DIV4_CBCR, .debug_ctl_reg = GCC_CLOCK_FREQ_MEASURE_CTL, @@ -72,114 +74,114 @@ static struct debug_mux gcc = { }; static struct measure_clk msm8936_clocks[] = { - { "gcc_gp1_clk", &gcc, 16 }, - { "gcc_gp2_clk", &gcc, 17 }, - { "gcc_gp3_clk", &gcc, 18 }, - { "gcc_bimc_gfx_clk", &gcc, 45 }, - { "gcc_mss_cfg_ahb_clk", &gcc, 48 }, - { "gcc_mss_q6_bimc_axi_clk", &gcc, 49 }, - { "gcc_apss_tcu_clk", &gcc, 80 }, - { "gcc_mdp_tbu_clk", &gcc, 81 }, - { "gcc_gfx_tbu_clk", &gcc, 82 }, - { "gcc_gfx_tcu_clk", &gcc, 83 }, - { "gcc_venus_tbu_clk", &gcc, 84 }, - { "gcc_gtcu_ahb_clk", &gcc, 88 }, - { "gcc_vfe_tbu_clk", &gcc, 90 }, - { "gcc_smmu_cfg_clk", &gcc, 91 }, - { "gcc_jpeg_tbu_clk", &gcc, 92 }, - { "gcc_usb_hs_system_clk", &gcc, 96 }, - { "gcc_usb_hs_ahb_clk", &gcc, 97 }, - { "gcc_usb_fs_ahb_clk", &gcc, 241 }, - { "gcc_usb_fs_ic_clk", &gcc, 244 }, - { "gcc_usb2a_phy_sleep_clk", &gcc, 99 }, - { "gcc_sdcc1_apps_clk", &gcc, 104 }, - { "gcc_sdcc1_ahb_clk", &gcc, 105 }, - { "gcc_sdcc2_apps_clk", &gcc, 112 }, - { "gcc_sdcc2_ahb_clk", &gcc, 113 }, - { "gcc_blsp1_ahb_clk", &gcc, 136 }, - { "gcc_blsp1_qup1_spi_apps_clk", &gcc, 138 }, - { "gcc_blsp1_qup1_i2c_apps_clk", &gcc, 139 }, - { "gcc_blsp1_uart1_apps_clk", &gcc, 140 }, - { "gcc_blsp1_qup2_spi_apps_clk", &gcc, 142 }, - { "gcc_blsp1_qup2_i2c_apps_clk", &gcc, 144 }, - { "gcc_blsp1_uart2_apps_clk", &gcc, 145 }, - { "gcc_blsp1_qup3_spi_apps_clk", &gcc, 147 }, - { "gcc_blsp1_qup3_i2c_apps_clk", &gcc, 148 }, - { "gcc_blsp1_qup4_spi_apps_clk", &gcc, 152 }, - { "gcc_blsp1_qup4_i2c_apps_clk", &gcc, 153 }, - { "gcc_blsp1_qup5_spi_apps_clk", &gcc, 156 }, - { "gcc_blsp1_qup5_i2c_apps_clk", &gcc, 157 }, - { "gcc_blsp1_qup6_spi_apps_clk", &gcc, 161 }, - { "gcc_blsp1_qup6_i2c_apps_clk", &gcc, 162 }, - { "gcc_camss_ahb_clk", &gcc, 168 }, - { "gcc_camss_top_ahb_clk", &gcc, 169 }, - { "gcc_camss_micro_ahb_clk", &gcc, 170 }, - { "gcc_camss_gp0_clk", &gcc, 171 }, - { "gcc_camss_gp1_clk", &gcc, 172 }, - { "gcc_camss_mclk0_clk", &gcc, 173 }, - { "gcc_camss_mclk1_clk", &gcc, 174 }, - { "gcc_camss_mclk2_clk", &gcc, 445 }, - { "gcc_camss_cci_clk", &gcc, 175 }, - { "gcc_camss_cci_ahb_clk", &gcc, 176 }, - { "gcc_camss_csi0phytimer_clk", &gcc, 177 }, - { "gcc_camss_csi1phytimer_clk", &gcc, 178 }, - { "gcc_camss_jpeg0_clk", &gcc, 179 }, - { "gcc_camss_jpeg_ahb_clk", &gcc, 180 }, - { "gcc_camss_jpeg_axi_clk", &gcc, 181 }, - { "gcc_camss_vfe0_clk", &gcc, 184 }, - { "gcc_camss_cpp_clk", &gcc, 185 }, - { "gcc_camss_cpp_ahb_clk", &gcc, 186 }, - { "gcc_camss_vfe_ahb_clk", &gcc, 187 }, - { "gcc_camss_vfe_axi_clk", &gcc, 188 }, - { "gcc_camss_csi_vfe0_clk", &gcc, 191 }, - { "gcc_camss_csi0_clk", &gcc, 192 }, - { "gcc_camss_csi0_ahb_clk", &gcc, 193 }, - { "gcc_camss_csi0phy_clk", &gcc, 194 }, - { "gcc_camss_csi0rdi_clk", &gcc, 195 }, - { "gcc_camss_csi0pix_clk", &gcc, 196 }, - { "gcc_camss_csi1_clk", &gcc, 197 }, - { "gcc_camss_csi1_ahb_clk", &gcc, 198 }, - { "gcc_camss_csi1phy_clk", &gcc, 199 }, - { "gcc_camss_csi2_clk", &gcc, 227 }, - { "gcc_camss_csi2_ahb_clk", &gcc, 228 }, - { "gcc_camss_csi2phy_clk", &gcc, 229 }, - { "gcc_camss_csi2rdi_clk", &gcc, 230 }, - { "gcc_camss_csi2pix_clk", &gcc, 231 }, - { "gcc_pdm_ahb_clk", &gcc, 208 }, - { "gcc_pdm2_clk", &gcc, 210 }, - { "gcc_prng_ahb_clk", &gcc, 216 }, - { "gcc_camss_csi1rdi_clk", &gcc, 224 }, - { "gcc_camss_csi1pix_clk", &gcc, 225 }, - { "gcc_camss_ispif_ahb_clk", &gcc, 226 }, - { "gcc_boot_rom_ahb_clk", &gcc, 248 }, - { "gcc_crypto_clk", &gcc, 312 }, - { "gcc_crypto_axi_clk", &gcc, 313 }, - { "gcc_crypto_ahb_clk", &gcc, 314 }, - { "gcc_oxili_timer_clk", &gcc, 489 }, - { "gcc_oxili_gfx3d_clk", &gcc, 490 }, - { "gcc_oxili_ahb_clk", &gcc, 491 }, - { "gcc_oxili_gmem_clk", &gcc, 496 }, - { "gcc_venus0_vcodec0_clk", &gcc, 497 }, - { "gcc_venus0_core0_vcodec0_clk", &gcc, 440 }, - { "gcc_venus0_core1_vcodec0_clk", &gcc, 441 }, - { "gcc_venus0_axi_clk", &gcc, 498 }, - { "gcc_venus0_ahb_clk", &gcc, 499 }, - { "gcc_mdss_ahb_clk", &gcc, 502 }, - { "gcc_mdss_axi_clk", &gcc, 503 }, - { "gcc_mdss_pclk0_clk", &gcc, 504 }, - { "gcc_mdss_pclk1_clk", &gcc, 442 }, - { "gcc_mdss_mdp_clk", &gcc, 505 }, - { "gcc_mdss_vsync_clk", &gcc, 507 }, - { "gcc_mdss_byte0_clk", &gcc, 508 }, - { "gcc_mdss_byte1_clk", &gcc, 443 }, - { "gcc_mdss_esc0_clk", &gcc, 509 }, - { "gcc_mdss_esc1_clk", &gcc, 444 }, - { "gcc_bimc_clk", &gcc, 340 }, - { "gcc_bimc_gpu_clk", &gcc, 343 }, - { "gcc_bimc_ddr_ch0_clk", &gcc, 346 }, - { "gcc_cpp_tbu_clk", &gcc, 233 }, - { "gcc_mdp_rt_tbu_clk", &gcc, 238 }, - { "wcnss_m_clk", &gcc, 408 }, + { "gcc_gp1_clk", &gcc.mux, 16 }, + { "gcc_gp2_clk", &gcc.mux, 17 }, + { "gcc_gp3_clk", &gcc.mux, 18 }, + { "gcc_bimc_gfx_clk", &gcc.mux, 45 }, + { "gcc_mss_cfg_ahb_clk", &gcc.mux, 48 }, + { "gcc_mss_q6_bimc_axi_clk", &gcc.mux, 49 }, + { "gcc_apss_tcu_clk", &gcc.mux, 80 }, + { "gcc_mdp_tbu_clk", &gcc.mux, 81 }, + { "gcc_gfx_tbu_clk", &gcc.mux, 82 }, + { "gcc_gfx_tcu_clk", &gcc.mux, 83 }, + { "gcc_venus_tbu_clk", &gcc.mux, 84 }, + { "gcc_gtcu_ahb_clk", &gcc.mux, 88 }, + { "gcc_vfe_tbu_clk", &gcc.mux, 90 }, + { "gcc_smmu_cfg_clk", &gcc.mux, 91 }, + { "gcc_jpeg_tbu_clk", &gcc.mux, 92 }, + { "gcc_usb_hs_system_clk", &gcc.mux, 96 }, + { "gcc_usb_hs_ahb_clk", &gcc.mux, 97 }, + { "gcc_usb_fs_ahb_clk", &gcc.mux, 241 }, + { "gcc_usb_fs_ic_clk", &gcc.mux, 244 }, + { "gcc_usb2a_phy_sleep_clk", &gcc.mux, 99 }, + { "gcc_sdcc1_apps_clk", &gcc.mux, 104 }, + { "gcc_sdcc1_ahb_clk", &gcc.mux, 105 }, + { "gcc_sdcc2_apps_clk", &gcc.mux, 112 }, + { "gcc_sdcc2_ahb_clk", &gcc.mux, 113 }, + { "gcc_blsp1_ahb_clk", &gcc.mux, 136 }, + { "gcc_blsp1_qup1_spi_apps_clk", &gcc.mux, 138 }, + { "gcc_blsp1_qup1_i2c_apps_clk", &gcc.mux, 139 }, + { "gcc_blsp1_uart1_apps_clk", &gcc.mux, 140 }, + { "gcc_blsp1_qup2_spi_apps_clk", &gcc.mux, 142 }, + { "gcc_blsp1_qup2_i2c_apps_clk", &gcc.mux, 144 }, + { "gcc_blsp1_uart2_apps_clk", &gcc.mux, 145 }, + { "gcc_blsp1_qup3_spi_apps_clk", &gcc.mux, 147 }, + { "gcc_blsp1_qup3_i2c_apps_clk", &gcc.mux, 148 }, + { "gcc_blsp1_qup4_spi_apps_clk", &gcc.mux, 152 }, + { "gcc_blsp1_qup4_i2c_apps_clk", &gcc.mux, 153 }, + { "gcc_blsp1_qup5_spi_apps_clk", &gcc.mux, 156 }, + { "gcc_blsp1_qup5_i2c_apps_clk", &gcc.mux, 157 }, + { "gcc_blsp1_qup6_spi_apps_clk", &gcc.mux, 161 }, + { "gcc_blsp1_qup6_i2c_apps_clk", &gcc.mux, 162 }, + { "gcc_camss_ahb_clk", &gcc.mux, 168 }, + { "gcc_camss_top_ahb_clk", &gcc.mux, 169 }, + { "gcc_camss_micro_ahb_clk", &gcc.mux, 170 }, + { "gcc_camss_gp0_clk", &gcc.mux, 171 }, + { "gcc_camss_gp1_clk", &gcc.mux, 172 }, + { "gcc_camss_mclk0_clk", &gcc.mux, 173 }, + { "gcc_camss_mclk1_clk", &gcc.mux, 174 }, + { "gcc_camss_mclk2_clk", &gcc.mux, 445 }, + { "gcc_camss_cci_clk", &gcc.mux, 175 }, + { "gcc_camss_cci_ahb_clk", &gcc.mux, 176 }, + { "gcc_camss_csi0phytimer_clk", &gcc.mux, 177 }, + { "gcc_camss_csi1phytimer_clk", &gcc.mux, 178 }, + { "gcc_camss_jpeg0_clk", &gcc.mux, 179 }, + { "gcc_camss_jpeg_ahb_clk", &gcc.mux, 180 }, + { "gcc_camss_jpeg_axi_clk", &gcc.mux, 181 }, + { "gcc_camss_vfe0_clk", &gcc.mux, 184 }, + { "gcc_camss_cpp_clk", &gcc.mux, 185 }, + { "gcc_camss_cpp_ahb_clk", &gcc.mux, 186 }, + { "gcc_camss_vfe_ahb_clk", &gcc.mux, 187 }, + { "gcc_camss_vfe_axi_clk", &gcc.mux, 188 }, + { "gcc_camss_csi_vfe0_clk", &gcc.mux, 191 }, + { "gcc_camss_csi0_clk", &gcc.mux, 192 }, + { "gcc_camss_csi0_ahb_clk", &gcc.mux, 193 }, + { "gcc_camss_csi0phy_clk", &gcc.mux, 194 }, + { "gcc_camss_csi0rdi_clk", &gcc.mux, 195 }, + { "gcc_camss_csi0pix_clk", &gcc.mux, 196 }, + { "gcc_camss_csi1_clk", &gcc.mux, 197 }, + { "gcc_camss_csi1_ahb_clk", &gcc.mux, 198 }, + { "gcc_camss_csi1phy_clk", &gcc.mux, 199 }, + { "gcc_camss_csi2_clk", &gcc.mux, 227 }, + { "gcc_camss_csi2_ahb_clk", &gcc.mux, 228 }, + { "gcc_camss_csi2phy_clk", &gcc.mux, 229 }, + { "gcc_camss_csi2rdi_clk", &gcc.mux, 230 }, + { "gcc_camss_csi2pix_clk", &gcc.mux, 231 }, + { "gcc_pdm_ahb_clk", &gcc.mux, 208 }, + { "gcc_pdm2_clk", &gcc.mux, 210 }, + { "gcc_prng_ahb_clk", &gcc.mux, 216 }, + { "gcc_camss_csi1rdi_clk", &gcc.mux, 224 }, + { "gcc_camss_csi1pix_clk", &gcc.mux, 225 }, + { "gcc_camss_ispif_ahb_clk", &gcc.mux, 226 }, + { "gcc_boot_rom_ahb_clk", &gcc.mux, 248 }, + { "gcc_crypto_clk", &gcc.mux, 312 }, + { "gcc_crypto_axi_clk", &gcc.mux, 313 }, + { "gcc_crypto_ahb_clk", &gcc.mux, 314 }, + { "gcc_oxili_timer_clk", &gcc.mux, 489 }, + { "gcc_oxili_gfx3d_clk", &gcc.mux, 490 }, + { "gcc_oxili_ahb_clk", &gcc.mux, 491 }, + { "gcc_oxili_gmem_clk", &gcc.mux, 496 }, + { "gcc_venus0_vcodec0_clk", &gcc.mux, 497 }, + { "gcc_venus0_core0_vcodec0_clk", &gcc.mux, 440 }, + { "gcc_venus0_core1_vcodec0_clk", &gcc.mux, 441 }, + { "gcc_venus0_axi_clk", &gcc.mux, 498 }, + { "gcc_venus0_ahb_clk", &gcc.mux, 499 }, + { "gcc_mdss_ahb_clk", &gcc.mux, 502 }, + { "gcc_mdss_axi_clk", &gcc.mux, 503 }, + { "gcc_mdss_pclk0_clk", &gcc.mux, 504 }, + { "gcc_mdss_pclk1_clk", &gcc.mux, 442 }, + { "gcc_mdss_mdp_clk", &gcc.mux, 505 }, + { "gcc_mdss_vsync_clk", &gcc.mux, 507 }, + { "gcc_mdss_byte0_clk", &gcc.mux, 508 }, + { "gcc_mdss_byte1_clk", &gcc.mux, 443 }, + { "gcc_mdss_esc0_clk", &gcc.mux, 509 }, + { "gcc_mdss_esc1_clk", &gcc.mux, 444 }, + { "gcc_bimc_clk", &gcc.mux, 340 }, + { "gcc_bimc_gpu_clk", &gcc.mux, 343 }, + { "gcc_bimc_ddr_ch0_clk", &gcc.mux, 346 }, + { "gcc_cpp_tbu_clk", &gcc.mux, 233 }, + { "gcc_mdp_rt_tbu_clk", &gcc.mux, 238 }, + { "wcnss_m_clk", &gcc.mux, 408 }, {}, }; diff --git a/msm8994.c b/msm8994.c index 76112ab..7d9e42d 100644 --- a/msm8994.c +++ b/msm8994.c @@ -12,20 +12,24 @@ #include "debugcc.h" -static struct debug_mux gcc = { - .phys = 0xfc400000, - .size = 0x2000, +static struct gcc_mux gcc = { + .mux = { + .phys = 0xfc400000, + .size = 0x2000, - .enable_reg = 0x1880, - .enable_mask = BIT(16), + .measure = measure_gcc, - .mux_reg = 0x1880, - .mux_mask = 0x3ff, + .enable_reg = 0x1880, + .enable_mask = BIT(16), + + .mux_reg = 0x1880, + .mux_mask = 0x3ff, - .div_reg = 0x1880, - .div_shift = 12, - .div_mask = 0xf << 12, - .div_val = 4, + .div_reg = 0x1880, + .div_shift = 12, + .div_mask = 0xf << 12, + .div_val = 4, + }, .xo_div4_reg = 0x10c8, .debug_ctl_reg = 0x1884, @@ -37,6 +41,10 @@ static struct debug_mux mmcc = { .size = 0x5200, .block_name = "mm", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x2b, + .enable_reg = 0x900, .enable_mask = BIT(16), @@ -45,175 +53,175 @@ static struct debug_mux mmcc = { }; static struct measure_clk msm8994_clocks[] = { - // { "debug_cpu_clk", &gcc, 0x16a }, - // { "debug_mmss_clk", &gcc, 0x2b }, - // { "debug_rpm_clk", &gcc, 0xffff }, - { "gcc_sys_noc_usb3_axi_clk", &gcc, 0x6 }, - { "gcc_mss_q6_bimc_axi_clk", &gcc, 0x31 }, - { "gcc_usb30_master_clk", &gcc, 0x50 }, - { "gcc_usb30_sleep_clk", &gcc, 0x51 }, - { "gcc_usb30_mock_utmi_clk", &gcc, 0x52 }, - { "gcc_usb3_phy_aux_clk", &gcc, 0x53 }, - { "gcc_usb3_phy_pipe_clk", &gcc, 0x54 }, - { "gcc_sys_noc_ufs_axi_clk", &gcc, 0x58 }, - { "gcc_usb_hs_system_clk", &gcc, 0x60 }, - { "gcc_usb_hs_ahb_clk", &gcc, 0x61 }, - { "gcc_usb2_hs_phy_sleep_clk", &gcc, 0x63 }, - { "gcc_usb_phy_cfg_ahb2phy_clk", &gcc, 0x64 }, - { "gcc_sdcc1_apps_clk", &gcc, 0x68 }, - { "gcc_sdcc1_ahb_clk", &gcc, 0x69 }, - { "gcc_sdcc2_apps_clk", &gcc, 0x70 }, - { "gcc_sdcc2_ahb_clk", &gcc, 0x71 }, - { "gcc_sdcc3_apps_clk", &gcc, 0x78 }, - { "gcc_sdcc3_ahb_clk", &gcc, 0x79 }, - { "gcc_sdcc4_apps_clk", &gcc, 0x80 }, - { "gcc_sdcc4_ahb_clk", &gcc, 0x81 }, - { "gcc_blsp1_ahb_clk", &gcc, 0x88 }, - { "gcc_blsp1_qup1_spi_apps_clk", &gcc, 0x8a }, - { "gcc_blsp1_qup1_i2c_apps_clk", &gcc, 0x8b }, - { "gcc_blsp1_uart1_apps_clk", &gcc, 0x8c }, - { "gcc_blsp1_qup2_spi_apps_clk", &gcc, 0x8e }, - { "gcc_blsp1_qup2_i2c_apps_clk", &gcc, 0x90 }, - { "gcc_blsp1_uart2_apps_clk", &gcc, 0x91 }, - { "gcc_blsp1_qup3_spi_apps_clk", &gcc, 0x93 }, - { "gcc_blsp1_qup3_i2c_apps_clk", &gcc, 0x94 }, - { "gcc_blsp1_uart3_apps_clk", &gcc, 0x95 }, - { "gcc_blsp1_qup4_spi_apps_clk", &gcc, 0x98 }, - { "gcc_blsp1_qup4_i2c_apps_clk", &gcc, 0x99 }, - { "gcc_blsp1_uart4_apps_clk", &gcc, 0x9a }, - { "gcc_blsp1_qup5_spi_apps_clk", &gcc, 0x9c }, - { "gcc_blsp1_qup5_i2c_apps_clk", &gcc, 0x9d }, - { "gcc_blsp1_uart5_apps_clk", &gcc, 0x9e }, - { "gcc_blsp1_qup6_spi_apps_clk", &gcc, 0xa1 }, - { "gcc_blsp1_qup6_i2c_apps_clk", &gcc, 0xa2 }, - { "gcc_blsp1_uart6_apps_clk", &gcc, 0xa3 }, - { "gcc_blsp2_ahb_clk", &gcc, 0xa8 }, - { "gcc_blsp2_qup1_spi_apps_clk", &gcc, 0xaa }, - { "gcc_blsp2_qup1_i2c_apps_clk", &gcc, 0xab }, - { "gcc_blsp2_uart1_apps_clk", &gcc, 0xac }, - { "gcc_blsp2_qup2_spi_apps_clk", &gcc, 0xae }, - { "gcc_blsp2_qup2_i2c_apps_clk", &gcc, 0xb0 }, - { "gcc_blsp2_uart2_apps_clk", &gcc, 0xb1 }, - { "gcc_blsp2_qup3_spi_apps_clk", &gcc, 0xb3 }, - { "gcc_blsp2_qup3_i2c_apps_clk", &gcc, 0xb4 }, - { "gcc_blsp2_uart3_apps_clk", &gcc, 0xb5 }, - { "gcc_blsp2_qup4_spi_apps_clk", &gcc, 0xb8 }, - { "gcc_blsp2_qup4_i2c_apps_clk", &gcc, 0xb9 }, - { "gcc_blsp2_uart4_apps_clk", &gcc, 0xba }, - { "gcc_blsp2_qup5_spi_apps_clk", &gcc, 0xbc }, - { "gcc_blsp2_qup5_i2c_apps_clk", &gcc, 0xbd }, - { "gcc_blsp2_uart5_apps_clk", &gcc, 0xbe }, - { "gcc_blsp2_qup6_spi_apps_clk", &gcc, 0xc1 }, - { "gcc_blsp2_qup6_i2c_apps_clk", &gcc, 0xc2 }, - { "gcc_blsp2_uart6_apps_clk", &gcc, 0xc3 }, - { "gcc_pdm_ahb_clk", &gcc, 0xd0 }, - { "gcc_pdm2_clk", &gcc, 0xd2 }, - { "gcc_prng_ahb_clk", &gcc, 0xd8 }, - { "gcc_bam_dma_ahb_clk", &gcc, 0xe0 }, - { "gcc_tsif_ahb_clk", &gcc, 0xe8 }, - { "gcc_tsif_ref_clk", &gcc, 0xe9 }, - { "gcc_boot_rom_ahb_clk", &gcc, 0xf8 }, - { "gcc_lpass_q6_axi_clk", &gcc, 0x160 }, - { "gcc_pcie_0_slv_axi_clk", &gcc, 0x1e8 }, - { "gcc_pcie_0_mstr_axi_clk", &gcc, 0x1e9 }, - { "gcc_pcie_0_cfg_ahb_clk", &gcc, 0x1ea }, - { "gcc_pcie_0_aux_clk", &gcc, 0x1eb }, - { "gcc_pcie_0_pipe_clk", &gcc, 0x1ec }, - { "gcc_pcie_1_slv_axi_clk", &gcc, 0x1f0 }, - { "gcc_pcie_1_mstr_axi_clk", &gcc, 0x1f1 }, - { "gcc_pcie_1_cfg_ahb_clk", &gcc, 0x1f2 }, - { "gcc_pcie_1_aux_clk", &gcc, 0x1f3 }, - { "gcc_pcie_1_pipe_clk", &gcc, 0x1f4 }, - { "gcc_ufs_axi_clk", &gcc, 0x230 }, - { "gcc_ufs_ahb_clk", &gcc, 0x231 }, - { "gcc_ufs_tx_cfg_clk", &gcc, 0x232 }, - { "gcc_ufs_rx_cfg_clk", &gcc, 0x233 }, - { "gcc_ufs_tx_symbol_0_clk", &gcc, 0x234 }, - { "gcc_ufs_tx_symbol_1_clk", &gcc, 0x235 }, - { "gcc_ufs_rx_symbol_0_clk", &gcc, 0x236 }, - { "gcc_ufs_rx_symbol_1_clk", &gcc, 0x237 }, - { "mmsscc_mmssnoc_ahb", &gcc, 0x2b, &mmcc, 0x1 }, - { "oxili_gfx3d_clk", &gcc, 0x2b, &mmcc, 0xd }, - { "mmss_misc_ahb_clk", &gcc, 0x2b, &mmcc, 0x3 }, - { "mmss_mmssnoc_axi_clk", &gcc, 0x2b, &mmcc, 0x4 }, - { "mmss_s0_axi_clk", &gcc, 0x2b, &mmcc, 0x5 }, - { "ocmemcx_ocmemnoc_clk", &gcc, 0x2b, &mmcc, 0x9 }, - { "oxilicx_ahb_clk", &gcc, 0x2b, &mmcc, 0xc }, - { "venus0_vcodec0_clk", &gcc, 0x2b, &mmcc, 0xe }, - { "venus0_axi_clk", &gcc, 0x2b, &mmcc, 0xf }, - { "venus0_ocmemnoc_clk", &gcc, 0x2b, &mmcc, 0x10 }, - { "venus0_ahb_clk", &gcc, 0x2b, &mmcc, 0x11 }, - { "mdss_mdp_clk", &gcc, 0x2b, &mmcc, 0x14 }, - { "mdss_pclk0_clk", &gcc, 0x2b, &mmcc, 0x16 }, - { "mdss_pclk1_clk", &gcc, 0x2b, &mmcc, 0x17 }, - { "mdss_extpclk_clk", &gcc, 0x2b, &mmcc, 0x18 }, - { "venus0_core0_vcodec_clk", &gcc, 0x2b, &mmcc, 0x1a }, - { "venus0_core1_vcodec_clk", &gcc, 0x2b, &mmcc, 0x1b }, - { "mdss_vsync_clk", &gcc, 0x2b, &mmcc, 0x1c }, - { "mdss_hdmi_clk", &gcc, 0x2b, &mmcc, 0x1d }, - { "mdss_byte0_clk", &gcc, 0x2b, &mmcc, 0x1e }, - { "mdss_byte1_clk", &gcc, 0x2b, &mmcc, 0x1f }, - { "mdss_esc0_clk", &gcc, 0x2b, &mmcc, 0x20 }, - { "mdss_esc1_clk", &gcc, 0x2b, &mmcc, 0x21 }, - { "mdss_ahb_clk", &gcc, 0x2b, &mmcc, 0x22 }, - { "mdss_hdmi_ahb_clk", &gcc, 0x2b, &mmcc, 0x23 }, - { "mdss_axi_clk", &gcc, 0x2b, &mmcc, 0x24 }, - { "camss_top_ahb_clk", &gcc, 0x2b, &mmcc, 0x25 }, - { "camss_micro_ahb_clk", &gcc, 0x2b, &mmcc, 0x26 }, - { "camss_gp0_clk", &gcc, 0x2b, &mmcc, 0x27 }, - { "camss_gp1_clk", &gcc, 0x2b, &mmcc, 0x28 }, - { "camss_mclk0_clk", &gcc, 0x2b, &mmcc, 0x29 }, - { "camss_mclk1_clk", &gcc, 0x2b, &mmcc, 0x2a }, - { "camss_mclk2_clk", &gcc, 0x2b, &mmcc, 0x2b }, - { "camss_mclk3_clk", &gcc, 0x2b, &mmcc, 0x2c }, - { "camss_cci_cci_clk", &gcc, 0x2b, &mmcc, 0x2d }, - { "camss_cci_cci_ahb_clk", &gcc, 0x2b, &mmcc, 0x2e }, - { "camss_phy0_csi0phytimer_clk", &gcc, 0x2b, &mmcc, 0x2f }, - { "camss_phy1_csi1phytimer_clk", &gcc, 0x2b, &mmcc, 0x30 }, - { "camss_phy2_csi2phytimer_clk", &gcc, 0x2b, &mmcc, 0x31 }, - { "camss_jpeg_jpeg0_clk", &gcc, 0x2b, &mmcc, 0x32 }, - { "camss_jpeg_jpeg1_clk", &gcc, 0x2b, &mmcc, 0x33 }, - { "camss_jpeg_jpeg2_clk", &gcc, 0x2b, &mmcc, 0x34 }, - { "camss_jpeg_jpeg_ahb_clk", &gcc, 0x2b, &mmcc, 0x35 }, - { "camss_jpeg_jpeg_axi_clk", &gcc, 0x2b, &mmcc, 0x36 }, - { "camss_ahb_clk", &gcc, 0x2b, &mmcc, 0x37 }, - { "camss_vfe_vfe0_clk", &gcc, 0x2b, &mmcc, 0x38 }, - { "camss_vfe_vfe1_clk", &gcc, 0x2b, &mmcc, 0x39 }, - { "camss_vfe_cpp_clk", &gcc, 0x2b, &mmcc, 0x3a }, - { "camss_vfe_cpp_ahb_clk", &gcc, 0x2b, &mmcc, 0x3b }, - { "camss_vfe_vfe_ahb_clk", &gcc, 0x2b, &mmcc, 0x3c }, - { "camss_vfe_vfe_axi_clk", &gcc, 0x2b, &mmcc, 0x3d }, - { "oxili_rbbmtimer_clk", &gcc, 0x2b, &mmcc, 0x3e }, - { "camss_csi_vfe0_clk", &gcc, 0x2b, &mmcc, 0x3f }, - { "camss_csi_vfe1_clk", &gcc, 0x2b, &mmcc, 0x40 }, - { "camss_csi0_clk", &gcc, 0x2b, &mmcc, 0x41 }, - { "camss_csi0_ahb_clk", &gcc, 0x2b, &mmcc, 0x42 }, - { "camss_csi0phy_clk", &gcc, 0x2b, &mmcc, 0x43 }, - { "camss_csi0rdi_clk", &gcc, 0x2b, &mmcc, 0x44 }, - { "camss_csi0pix_clk", &gcc, 0x2b, &mmcc, 0x45 }, - { "camss_csi1_clk", &gcc, 0x2b, &mmcc, 0x46 }, - { "camss_csi1_ahb_clk", &gcc, 0x2b, &mmcc, 0x47 }, - { "camss_csi1phy_clk", &gcc, 0x2b, &mmcc, 0x48 }, - { "camss_csi1rdi_clk", &gcc, 0x2b, &mmcc, 0x49 }, - { "camss_csi1pix_clk", &gcc, 0x2b, &mmcc, 0x4a }, - { "camss_csi2_clk", &gcc, 0x2b, &mmcc, 0x4b }, - { "camss_csi2_ahb_clk", &gcc, 0x2b, &mmcc, 0x4c }, - { "camss_csi2phy_clk", &gcc, 0x2b, &mmcc, 0x4d }, - { "camss_csi2rdi_clk", &gcc, 0x2b, &mmcc, 0x4e }, - { "camss_csi2pix_clk", &gcc, 0x2b, &mmcc, 0x4f }, - { "camss_csi3_clk", &gcc, 0x2b, &mmcc, 0x50 }, - { "camss_csi3_ahb_clk", &gcc, 0x2b, &mmcc, 0x51 }, - { "camss_csi3phy_clk", &gcc, 0x2b, &mmcc, 0x52 }, - { "camss_csi3rdi_clk", &gcc, 0x2b, &mmcc, 0x53 }, - { "camss_csi3pix_clk", &gcc, 0x2b, &mmcc, 0x54 }, - { "camss_ispif_ahb_clk", &gcc, 0x2b, &mmcc, 0x55 }, - { "venus0_core2_vcodec_clk", &gcc, 0x2b, &mmcc, 0x79 }, - { "camss_vfe_cpp_axi_clk", &gcc, 0x2b, &mmcc, 0x7a }, - { "camss_jpeg_dma_clk", &gcc, 0x2b, &mmcc, 0x7b }, - { "fd_core_clk", &gcc, 0x2b, &mmcc, 0x89 }, - { "fd_core_uar_clk", &gcc, 0x2b, &mmcc, 0x8a }, - { "fd_axi_clk", &gcc, 0x2b, &mmcc, 0x8b }, - { "fd_ahb_clk", &gcc, 0x2b, &mmcc, 0x8c }, + // { "debug_cpu_clk", &gcc.mux, 0x16a }, + + { "gcc_sys_noc_usb3_axi_clk", &gcc.mux, 0x6 }, + { "gcc_mss_q6_bimc_axi_clk", &gcc.mux, 0x31 }, + { "gcc_usb30_master_clk", &gcc.mux, 0x50 }, + { "gcc_usb30_sleep_clk", &gcc.mux, 0x51 }, + { "gcc_usb30_mock_utmi_clk", &gcc.mux, 0x52 }, + { "gcc_usb3_phy_aux_clk", &gcc.mux, 0x53 }, + { "gcc_usb3_phy_pipe_clk", &gcc.mux, 0x54 }, + { "gcc_sys_noc_ufs_axi_clk", &gcc.mux, 0x58 }, + { "gcc_usb_hs_system_clk", &gcc.mux, 0x60 }, + { "gcc_usb_hs_ahb_clk", &gcc.mux, 0x61 }, + { "gcc_usb2_hs_phy_sleep_clk", &gcc.mux, 0x63 }, + { "gcc_usb_phy_cfg_ahb2phy_clk", &gcc.mux, 0x64 }, + { "gcc_sdcc1_apps_clk", &gcc.mux, 0x68 }, + { "gcc_sdcc1_ahb_clk", &gcc.mux, 0x69 }, + { "gcc_sdcc2_apps_clk", &gcc.mux, 0x70 }, + { "gcc_sdcc2_ahb_clk", &gcc.mux, 0x71 }, + { "gcc_sdcc3_apps_clk", &gcc.mux, 0x78 }, + { "gcc_sdcc3_ahb_clk", &gcc.mux, 0x79 }, + { "gcc_sdcc4_apps_clk", &gcc.mux, 0x80 }, + { "gcc_sdcc4_ahb_clk", &gcc.mux, 0x81 }, + { "gcc_blsp1_ahb_clk", &gcc.mux, 0x88 }, + { "gcc_blsp1_qup1_spi_apps_clk", &gcc.mux, 0x8a }, + { "gcc_blsp1_qup1_i2c_apps_clk", &gcc.mux, 0x8b }, + { "gcc_blsp1_uart1_apps_clk", &gcc.mux, 0x8c }, + { "gcc_blsp1_qup2_spi_apps_clk", &gcc.mux, 0x8e }, + { "gcc_blsp1_qup2_i2c_apps_clk", &gcc.mux, 0x90 }, + { "gcc_blsp1_uart2_apps_clk", &gcc.mux, 0x91 }, + { "gcc_blsp1_qup3_spi_apps_clk", &gcc.mux, 0x93 }, + { "gcc_blsp1_qup3_i2c_apps_clk", &gcc.mux, 0x94 }, + { "gcc_blsp1_uart3_apps_clk", &gcc.mux, 0x95 }, + { "gcc_blsp1_qup4_spi_apps_clk", &gcc.mux, 0x98 }, + { "gcc_blsp1_qup4_i2c_apps_clk", &gcc.mux, 0x99 }, + { "gcc_blsp1_uart4_apps_clk", &gcc.mux, 0x9a }, + { "gcc_blsp1_qup5_spi_apps_clk", &gcc.mux, 0x9c }, + { "gcc_blsp1_qup5_i2c_apps_clk", &gcc.mux, 0x9d }, + { "gcc_blsp1_uart5_apps_clk", &gcc.mux, 0x9e }, + { "gcc_blsp1_qup6_spi_apps_clk", &gcc.mux, 0xa1 }, + { "gcc_blsp1_qup6_i2c_apps_clk", &gcc.mux, 0xa2 }, + { "gcc_blsp1_uart6_apps_clk", &gcc.mux, 0xa3 }, + { "gcc_blsp2_ahb_clk", &gcc.mux, 0xa8 }, + { "gcc_blsp2_qup1_spi_apps_clk", &gcc.mux, 0xaa }, + { "gcc_blsp2_qup1_i2c_apps_clk", &gcc.mux, 0xab }, + { "gcc_blsp2_uart1_apps_clk", &gcc.mux, 0xac }, + { "gcc_blsp2_qup2_spi_apps_clk", &gcc.mux, 0xae }, + { "gcc_blsp2_qup2_i2c_apps_clk", &gcc.mux, 0xb0 }, + { "gcc_blsp2_uart2_apps_clk", &gcc.mux, 0xb1 }, + { "gcc_blsp2_qup3_spi_apps_clk", &gcc.mux, 0xb3 }, + { "gcc_blsp2_qup3_i2c_apps_clk", &gcc.mux, 0xb4 }, + { "gcc_blsp2_uart3_apps_clk", &gcc.mux, 0xb5 }, + { "gcc_blsp2_qup4_spi_apps_clk", &gcc.mux, 0xb8 }, + { "gcc_blsp2_qup4_i2c_apps_clk", &gcc.mux, 0xb9 }, + { "gcc_blsp2_uart4_apps_clk", &gcc.mux, 0xba }, + { "gcc_blsp2_qup5_spi_apps_clk", &gcc.mux, 0xbc }, + { "gcc_blsp2_qup5_i2c_apps_clk", &gcc.mux, 0xbd }, + { "gcc_blsp2_uart5_apps_clk", &gcc.mux, 0xbe }, + { "gcc_blsp2_qup6_spi_apps_clk", &gcc.mux, 0xc1 }, + { "gcc_blsp2_qup6_i2c_apps_clk", &gcc.mux, 0xc2 }, + { "gcc_blsp2_uart6_apps_clk", &gcc.mux, 0xc3 }, + { "gcc_pdm_ahb_clk", &gcc.mux, 0xd0 }, + { "gcc_pdm2_clk", &gcc.mux, 0xd2 }, + { "gcc_prng_ahb_clk", &gcc.mux, 0xd8 }, + { "gcc_bam_dma_ahb_clk", &gcc.mux, 0xe0 }, + { "gcc_tsif_ahb_clk", &gcc.mux, 0xe8 }, + { "gcc_tsif_ref_clk", &gcc.mux, 0xe9 }, + { "gcc_boot_rom_ahb_clk", &gcc.mux, 0xf8 }, + { "gcc_lpass_q6_axi_clk", &gcc.mux, 0x160 }, + { "gcc_pcie_0_slv_axi_clk", &gcc.mux, 0x1e8 }, + { "gcc_pcie_0_mstr_axi_clk", &gcc.mux, 0x1e9 }, + { "gcc_pcie_0_cfg_ahb_clk", &gcc.mux, 0x1ea }, + { "gcc_pcie_0_aux_clk", &gcc.mux, 0x1eb }, + { "gcc_pcie_0_pipe_clk", &gcc.mux, 0x1ec }, + { "gcc_pcie_1_slv_axi_clk", &gcc.mux, 0x1f0 }, + { "gcc_pcie_1_mstr_axi_clk", &gcc.mux, 0x1f1 }, + { "gcc_pcie_1_cfg_ahb_clk", &gcc.mux, 0x1f2 }, + { "gcc_pcie_1_aux_clk", &gcc.mux, 0x1f3 }, + { "gcc_pcie_1_pipe_clk", &gcc.mux, 0x1f4 }, + { "gcc_ufs_axi_clk", &gcc.mux, 0x230 }, + { "gcc_ufs_ahb_clk", &gcc.mux, 0x231 }, + { "gcc_ufs_tx_cfg_clk", &gcc.mux, 0x232 }, + { "gcc_ufs_rx_cfg_clk", &gcc.mux, 0x233 }, + { "gcc_ufs_tx_symbol_0_clk", &gcc.mux, 0x234 }, + { "gcc_ufs_tx_symbol_1_clk", &gcc.mux, 0x235 }, + { "gcc_ufs_rx_symbol_0_clk", &gcc.mux, 0x236 }, + { "gcc_ufs_rx_symbol_1_clk", &gcc.mux, 0x237 }, + + { "mmsscc_mmssnoc_ahb", &mmcc, 0x1 }, + { "oxili_gfx3d_clk", &mmcc, 0xd }, + { "mmss_misc_ahb_clk", &mmcc, 0x3 }, + { "mmss_mmssnoc_axi_clk", &mmcc, 0x4 }, + { "mmss_s0_axi_clk", &mmcc, 0x5 }, + { "ocmemcx_ocmemnoc_clk", &mmcc, 0x9 }, + { "oxilicx_ahb_clk", &mmcc, 0xc }, + { "venus0_vcodec0_clk", &mmcc, 0xe }, + { "venus0_axi_clk", &mmcc, 0xf }, + { "venus0_ocmemnoc_clk", &mmcc, 0x10 }, + { "venus0_ahb_clk", &mmcc, 0x11 }, + { "mdss_mdp_clk", &mmcc, 0x14 }, + { "mdss_pclk0_clk", &mmcc, 0x16 }, + { "mdss_pclk1_clk", &mmcc, 0x17 }, + { "mdss_extpclk_clk", &mmcc, 0x18 }, + { "venus0_core0_vcodec_clk", &mmcc, 0x1a }, + { "venus0_core1_vcodec_clk", &mmcc, 0x1b }, + { "mdss_vsync_clk", &mmcc, 0x1c }, + { "mdss_hdmi_clk", &mmcc, 0x1d }, + { "mdss_byte0_clk", &mmcc, 0x1e }, + { "mdss_byte1_clk", &mmcc, 0x1f }, + { "mdss_esc0_clk", &mmcc, 0x20 }, + { "mdss_esc1_clk", &mmcc, 0x21 }, + { "mdss_ahb_clk", &mmcc, 0x22 }, + { "mdss_hdmi_ahb_clk", &mmcc, 0x23 }, + { "mdss_axi_clk", &mmcc, 0x24 }, + { "camss_top_ahb_clk", &mmcc, 0x25 }, + { "camss_micro_ahb_clk", &mmcc, 0x26 }, + { "camss_gp0_clk", &mmcc, 0x27 }, + { "camss_gp1_clk", &mmcc, 0x28 }, + { "camss_mclk0_clk", &mmcc, 0x29 }, + { "camss_mclk1_clk", &mmcc, 0x2a }, + { "camss_mclk2_clk", &mmcc, 0x2b }, + { "camss_mclk3_clk", &mmcc, 0x2c }, + { "camss_cci_cci_clk", &mmcc, 0x2d }, + { "camss_cci_cci_ahb_clk", &mmcc, 0x2e }, + { "camss_phy0_csi0phytimer_clk", &mmcc, 0x2f }, + { "camss_phy1_csi1phytimer_clk", &mmcc, 0x30 }, + { "camss_phy2_csi2phytimer_clk", &mmcc, 0x31 }, + { "camss_jpeg_jpeg0_clk", &mmcc, 0x32 }, + { "camss_jpeg_jpeg1_clk", &mmcc, 0x33 }, + { "camss_jpeg_jpeg2_clk", &mmcc, 0x34 }, + { "camss_jpeg_jpeg_ahb_clk", &mmcc, 0x35 }, + { "camss_jpeg_jpeg_axi_clk", &mmcc, 0x36 }, + { "camss_ahb_clk", &mmcc, 0x37 }, + { "camss_vfe_vfe0_clk", &mmcc, 0x38 }, + { "camss_vfe_vfe1_clk", &mmcc, 0x39 }, + { "camss_vfe_cpp_clk", &mmcc, 0x3a }, + { "camss_vfe_cpp_ahb_clk", &mmcc, 0x3b }, + { "camss_vfe_vfe_ahb_clk", &mmcc, 0x3c }, + { "camss_vfe_vfe_axi_clk", &mmcc, 0x3d }, + { "oxili_rbbmtimer_clk", &mmcc, 0x3e }, + { "camss_csi_vfe0_clk", &mmcc, 0x3f }, + { "camss_csi_vfe1_clk", &mmcc, 0x40 }, + { "camss_csi0_clk", &mmcc, 0x41 }, + { "camss_csi0_ahb_clk", &mmcc, 0x42 }, + { "camss_csi0phy_clk", &mmcc, 0x43 }, + { "camss_csi0rdi_clk", &mmcc, 0x44 }, + { "camss_csi0pix_clk", &mmcc, 0x45 }, + { "camss_csi1_clk", &mmcc, 0x46 }, + { "camss_csi1_ahb_clk", &mmcc, 0x47 }, + { "camss_csi1phy_clk", &mmcc, 0x48 }, + { "camss_csi1rdi_clk", &mmcc, 0x49 }, + { "camss_csi1pix_clk", &mmcc, 0x4a }, + { "camss_csi2_clk", &mmcc, 0x4b }, + { "camss_csi2_ahb_clk", &mmcc, 0x4c }, + { "camss_csi2phy_clk", &mmcc, 0x4d }, + { "camss_csi2rdi_clk", &mmcc, 0x4e }, + { "camss_csi2pix_clk", &mmcc, 0x4f }, + { "camss_csi3_clk", &mmcc, 0x50 }, + { "camss_csi3_ahb_clk", &mmcc, 0x51 }, + { "camss_csi3phy_clk", &mmcc, 0x52 }, + { "camss_csi3rdi_clk", &mmcc, 0x53 }, + { "camss_csi3pix_clk", &mmcc, 0x54 }, + { "camss_ispif_ahb_clk", &mmcc, 0x55 }, + { "venus0_core2_vcodec_clk", &mmcc, 0x79 }, + { "camss_vfe_cpp_axi_clk", &mmcc, 0x7a }, + { "camss_jpeg_dma_clk", &mmcc, 0x7b }, + { "fd_core_clk", &mmcc, 0x89 }, + { "fd_core_uar_clk", &mmcc, 0x8a }, + { "fd_axi_clk", &mmcc, 0x8b }, + { "fd_ahb_clk", &mmcc, 0x8c }, {} }; diff --git a/msm8996.c b/msm8996.c index cbe8608..727c79d 100644 --- a/msm8996.c +++ b/msm8996.c @@ -49,20 +49,24 @@ #define GCC_DEBUG_STATUS 0x62008 #define GCC_XO_DIV4_CBCR 0x43008 -static struct debug_mux gcc = { - .phys = GCC_BASE, - .size = GCC_SIZE, +static struct gcc_mux gcc = { + .mux = { + .phys = GCC_BASE, + .size = GCC_SIZE, - .enable_reg = GCC_DEBUG_CLK_CTL, - .enable_mask = BIT(16), + .measure = measure_gcc, - .mux_reg = GCC_DEBUG_CLK_CTL, - .mux_mask = 0x3ff, + .enable_reg = GCC_DEBUG_CLK_CTL, + .enable_mask = BIT(16), - .div_reg = GCC_DEBUG_CLK_CTL, - .div_shift = 12, - .div_mask = 0xf << 12, - .div_val = 4, + .mux_reg = GCC_DEBUG_CLK_CTL, + .mux_mask = 0x3ff, + + .div_reg = GCC_DEBUG_CLK_CTL, + .div_shift = 12, + .div_mask = 0xf << 12, + .div_val = 4, + }, .xo_div4_reg = GCC_XO_DIV4_CBCR, .debug_ctl_reg = GCC_DEBUG_CTL, @@ -74,6 +78,10 @@ static struct debug_mux mmss_cc = { .size = 0xb00c, .block_name = "mmss", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x1b, + .enable_reg = 0x900, .enable_mask = BIT(16), @@ -86,6 +94,10 @@ static struct debug_mux apc0_mux = { .phys = 0x06400000, .size = 0x1000, + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0xbb, + .enable_reg = 0x48, .enable_mask = 0xf00, }; @@ -94,273 +106,262 @@ static struct debug_mux apc1_mux = { .phys = 0x06480000, .size = 0x1000, + .measure = measure_leaf, + .parent = &apc0_mux, + .enable_reg = 0x48, .enable_mask = 0xf00, }; -static void cpu_premeasure(struct debug_mux *mux) -{ - mux_enable(&apc0_mux); - mux_enable(&apc1_mux); -}; - -static void cpu_postmeasure(struct debug_mux *mux) -{ - mux_disable(&apc0_mux); - mux_disable(&apc1_mux); -}; - static struct debug_mux cpu_cc = { .phys = 0x09820000, .size = 0x1000, .block_name = "cpu", + .measure = measure_leaf, + .parent = &apc1_mux, + .mux_reg = 0x78, .mux_mask = 0xff << 8, .mux_shift = 8, - - .premeasure = cpu_premeasure, - .postmeasure = cpu_postmeasure, }; static struct measure_clk msm8996_clocks[] = { - { "snoc_clk", &gcc, 0x0000 }, - { "gcc_sys_noc_usb3_axi_clk", &gcc, 0x0006 }, - { "gcc_sys_noc_ufs_axi_clk", &gcc, 0x0007 }, - { "cnoc_clk", &gcc, 0x000e }, - { "pnoc_clk", &gcc, 0x0011 }, - { "gcc_periph_noc_usb20_ahb_clk", &gcc, 0x0014 }, - { "gcc_mmss_noc_cfg_ahb_clk", &gcc, 0x0019 }, - //{ "mmss_gcc_dbg_clk", &gcc, 0x001b }, - { "mmss_mmagic_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x0001 }, - { "mmss_misc_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x0003 }, - { "vmem_maxi_clk", &gcc, 0x1b, &mmss_cc, 0x0009 }, - { "vmem_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x000a }, - { "gpu_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x000c }, - { "gpu_gx_gfx3d_clk", &gcc, 0x1b, &mmss_cc, 0x000d }, - { "video_core_clk", &gcc, 0x1b, &mmss_cc, 0x000e }, - { "video_axi_clk", &gcc, 0x1b, &mmss_cc, 0x000f }, - { "video_maxi_clk", &gcc, 0x1b, &mmss_cc, 0x0010 }, - { "video_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x0011 }, - { "mmss_rbcpr_clk", &gcc, 0x1b, &mmss_cc, 0x0012 }, - { "mmss_rbcpr_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x0013 }, - { "mdss_mdp_clk", &gcc, 0x1b, &mmss_cc, 0x0014 }, - { "mdss_pclk0_clk", &gcc, 0x1b, &mmss_cc, 0x0016 }, - { "mdss_pclk1_clk", &gcc, 0x1b, &mmss_cc, 0x0017 }, - { "mdss_extpclk_clk", &gcc, 0x1b, &mmss_cc, 0x0018 }, - { "video_subcore0_clk", &gcc, 0x1b, &mmss_cc, 0x001a }, - { "video_subcore1_clk", &gcc, 0x1b, &mmss_cc, 0x001b }, - { "mdss_vsync_clk", &gcc, 0x1b, &mmss_cc, 0x001c }, - { "mdss_hdmi_clk", &gcc, 0x1b, &mmss_cc, 0x001d }, - { "mdss_byte0_clk", &gcc, 0x1b, &mmss_cc, 0x001e }, - { "mdss_byte1_clk", &gcc, 0x1b, &mmss_cc, 0x001f }, - { "mdss_esc0_clk", &gcc, 0x1b, &mmss_cc, 0x0020 }, - { "mdss_esc1_clk", &gcc, 0x1b, &mmss_cc, 0x0021 }, - { "mdss_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x0022 }, - { "mdss_hdmi_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x0023 }, - { "mdss_axi_clk", &gcc, 0x1b, &mmss_cc, 0x0024 }, - { "camss_top_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x0025 }, - { "camss_micro_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x0026 }, - { "camss_gp0_clk", &gcc, 0x1b, &mmss_cc, 0x0027 }, - { "camss_gp1_clk", &gcc, 0x1b, &mmss_cc, 0x0028 }, - { "camss_mclk0_clk", &gcc, 0x1b, &mmss_cc, 0x0029 }, - { "camss_mclk1_clk", &gcc, 0x1b, &mmss_cc, 0x002a }, - { "camss_mclk2_clk", &gcc, 0x1b, &mmss_cc, 0x002b }, - { "camss_mclk3_clk", &gcc, 0x1b, &mmss_cc, 0x002c }, - { "camss_cci_clk", &gcc, 0x1b, &mmss_cc, 0x002d }, - { "camss_cci_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x002e }, - { "camss_csi0phytimer_clk", &gcc, 0x1b, &mmss_cc, 0x002f }, - { "camss_csi1phytimer_clk", &gcc, 0x1b, &mmss_cc, 0x0030 }, - { "camss_csi2phytimer_clk", &gcc, 0x1b, &mmss_cc, 0x0031 }, - { "camss_jpeg0_clk", &gcc, 0x1b, &mmss_cc, 0x0032 }, - { "camss_ispif_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x0033 }, - { "camss_jpeg2_clk", &gcc, 0x1b, &mmss_cc, 0x0034 }, - { "camss_jpeg_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x0035 }, - { "camss_jpeg_axi_clk", &gcc, 0x1b, &mmss_cc, 0x0036 }, - { "camss_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x0037 }, - { "camss_vfe0_clk", &gcc, 0x1b, &mmss_cc, 0x0038 }, - { "camss_vfe1_clk", &gcc, 0x1b, &mmss_cc, 0x0039 }, - { "camss_cpp_clk", &gcc, 0x1b, &mmss_cc, 0x003a }, - { "camss_cpp_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x003b }, - { "camss_vfe_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x003c }, - { "camss_vfe_axi_clk", &gcc, 0x1b, &mmss_cc, 0x003d }, - { "gpu_gx_rbbmtimer_clk", &gcc, 0x1b, &mmss_cc, 0x003e }, - { "camss_csi_vfe0_clk", &gcc, 0x1b, &mmss_cc, 0x003f }, - { "camss_csi_vfe1_clk", &gcc, 0x1b, &mmss_cc, 0x0040 }, - { "camss_csi0_clk", &gcc, 0x1b, &mmss_cc, 0x0041 }, - { "camss_csi0_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x0042 }, - { "camss_csi0phy_clk", &gcc, 0x1b, &mmss_cc, 0x0043 }, - { "camss_csi0rdi_clk", &gcc, 0x1b, &mmss_cc, 0x0044 }, - { "camss_csi0pix_clk", &gcc, 0x1b, &mmss_cc, 0x0045 }, - { "camss_csi1_clk", &gcc, 0x1b, &mmss_cc, 0x0046 }, - { "camss_csi1_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x0047 }, - { "camss_csi1phy_clk", &gcc, 0x1b, &mmss_cc, 0x0048 }, - { "camss_csi1rdi_clk", &gcc, 0x1b, &mmss_cc, 0x0049 }, - { "camss_csi1pix_clk", &gcc, 0x1b, &mmss_cc, 0x004a }, - { "camss_csi2_clk", &gcc, 0x1b, &mmss_cc, 0x004b }, - { "camss_csi2_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x004c }, - { "camss_csi2phy_clk", &gcc, 0x1b, &mmss_cc, 0x004d }, - { "camss_csi2rdi_clk", &gcc, 0x1b, &mmss_cc, 0x004e }, - { "camss_csi2pix_clk", &gcc, 0x1b, &mmss_cc, 0x004f }, - { "camss_csi3_clk", &gcc, 0x1b, &mmss_cc, 0x0050 }, - { "camss_csi3_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x0051 }, - { "camss_csi3phy_clk", &gcc, 0x1b, &mmss_cc, 0x0052 }, - { "camss_csi3rdi_clk", &gcc, 0x1b, &mmss_cc, 0x0053 }, - { "camss_csi3pix_clk", &gcc, 0x1b, &mmss_cc, 0x0054 }, - { "mmss_mmagic_maxi_clk", &gcc, 0x1b, &mmss_cc, 0x0070 }, - { "camss_vfe0_stream_clk", &gcc, 0x1b, &mmss_cc, 0x0071 }, - { "camss_vfe1_stream_clk", &gcc, 0x1b, &mmss_cc, 0x0072 }, - { "camss_cpp_vbif_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x0073 }, - { "mmss_mmagic_cfg_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x0074 }, - { "mmss_misc_cxo_clk", &gcc, 0x1b, &mmss_cc, 0x0077 }, - { "camss_cpp_axi_clk", &gcc, 0x1b, &mmss_cc, 0x007a }, - { "camss_jpeg_dma_clk", &gcc, 0x1b, &mmss_cc, 0x007b }, - { "camss_vfe0_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x0086 }, - { "camss_vfe1_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x0087 }, - { "gpu_aon_isense_clk", &gcc, 0x1b, &mmss_cc, 0x0088 }, - { "fd_core_clk", &gcc, 0x1b, &mmss_cc, 0x0089 }, - { "fd_core_uar_clk", &gcc, 0x1b, &mmss_cc, 0x008a }, - { "fd_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x008c }, - { "camss_csiphy0_3p_clk", &gcc, 0x1b, &mmss_cc, 0x0091 }, - { "camss_csiphy1_3p_clk", &gcc, 0x1b, &mmss_cc, 0x0092 }, - { "camss_csiphy2_3p_clk", &gcc, 0x1b, &mmss_cc, 0x0093 }, - { "smmu_vfe_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x0094 }, - { "smmu_vfe_axi_clk", &gcc, 0x1b, &mmss_cc, 0x0095 }, - { "smmu_cpp_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x0096 }, - { "smmu_cpp_axi_clk", &gcc, 0x1b, &mmss_cc, 0x0097 }, - { "smmu_jpeg_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x0098 }, - { "smmu_jpeg_axi_clk", &gcc, 0x1b, &mmss_cc, 0x0099 }, - { "mmagic_camss_axi_clk", &gcc, 0x1b, &mmss_cc, 0x009a }, - { "smmu_rot_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x009b }, - { "smmu_rot_axi_clk", &gcc, 0x1b, &mmss_cc, 0x009c }, - { "smmu_mdp_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x009d }, - { "smmu_mdp_axi_clk", &gcc, 0x1b, &mmss_cc, 0x009e }, - { "mmagic_mdss_axi_clk", &gcc, 0x1b, &mmss_cc, 0x009f }, - { "smmu_video_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x00a0 }, - { "smmu_video_axi_clk", &gcc, 0x1b, &mmss_cc, 0x00a1 }, - { "mmagic_video_axi_clk", &gcc, 0x1b, &mmss_cc, 0x00a2 }, - { "mmagic_camss_noc_cfg_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x00ad }, - { "mmagic_mdss_noc_cfg_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x00ae }, - { "mmagic_video_noc_cfg_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x00af }, - { "mmagic_bimc_noc_cfg_ahb_clk", &gcc, 0x1b, &mmss_cc, 0x00b0 }, - { "gcc_mmss_bimc_gfx_clk", &gcc, 0x001c}, - { "gcc_usb30_master_clk", &gcc, 0x002d }, - { "gcc_usb30_sleep_clk", &gcc, 0x002e }, - { "gcc_usb30_mock_utmi_clk", &gcc, 0x002f }, - { "gcc_usb3_phy_aux_clk", &gcc, 0x0030 }, - { "gcc_usb3_phy_pipe_clk", &gcc, 0x0031 }, - { "gcc_usb20_master_clk", &gcc, 0x0035 }, - { "gcc_usb20_sleep_clk", &gcc, 0x0036 }, - { "gcc_usb20_mock_utmi_clk", &gcc, 0x0037 }, - { "gcc_usb_phy_cfg_ahb2phy_clk", &gcc, 0x0038 }, - { "gcc_sdcc1_apps_clk", &gcc, 0x0039 }, - { "gcc_sdcc1_ahb_clk", &gcc, 0x003a }, - { "gcc_sdcc2_apps_clk", &gcc, 0x003b }, - { "gcc_sdcc2_ahb_clk", &gcc, 0x003c }, - { "gcc_sdcc3_apps_clk", &gcc, 0x003d }, - { "gcc_sdcc3_ahb_clk", &gcc, 0x003e }, - { "gcc_sdcc4_apps_clk", &gcc, 0x003f }, - { "gcc_sdcc4_ahb_clk", &gcc, 0x0040 }, - { "gcc_blsp1_ahb_clk", &gcc, 0x0041 }, - { "gcc_blsp1_qup1_spi_apps_clk", &gcc, 0x0043 }, - { "gcc_blsp1_qup1_i2c_apps_clk", &gcc, 0x0044 }, - { "gcc_blsp1_uart1_apps_clk", &gcc, 0x0045 }, - { "gcc_blsp1_qup2_spi_apps_clk", &gcc, 0x0047 }, - { "gcc_blsp1_qup2_i2c_apps_clk", &gcc, 0x0048 }, - { "gcc_blsp1_uart2_apps_clk", &gcc, 0x0049 }, - { "gcc_blsp1_qup3_spi_apps_clk", &gcc, 0x004b }, - { "gcc_blsp1_qup3_i2c_apps_clk", &gcc, 0x004c }, - { "gcc_blsp1_uart3_apps_clk", &gcc, 0x004d }, - { "gcc_blsp1_qup4_spi_apps_clk", &gcc, 0x004f }, - { "gcc_blsp1_qup4_i2c_apps_clk", &gcc, 0x0050 }, - { "gcc_blsp1_uart4_apps_clk", &gcc, 0x0051 }, - { "gcc_blsp1_qup5_spi_apps_clk", &gcc, 0x0053 }, - { "gcc_blsp1_qup5_i2c_apps_clk", &gcc, 0x0054 }, - { "gcc_blsp1_uart5_apps_clk", &gcc, 0x0055 }, - { "gcc_blsp1_qup6_spi_apps_clk", &gcc, 0x0057 }, - { "gcc_blsp1_qup6_i2c_apps_clk", &gcc, 0x0058 }, - { "gcc_blsp1_uart6_apps_clk", &gcc, 0x0059 }, - { "gcc_blsp2_ahb_clk", &gcc, 0x005b }, - { "gcc_blsp2_qup1_spi_apps_clk", &gcc, 0x005d }, - { "gcc_blsp2_qup1_i2c_apps_clk", &gcc, 0x005e }, - { "gcc_blsp2_uart1_apps_clk", &gcc, 0x005f }, - { "gcc_blsp2_qup2_spi_apps_clk", &gcc, 0x0061 }, - { "gcc_blsp2_qup2_i2c_apps_clk", &gcc, 0x0062 }, - { "gcc_blsp2_uart2_apps_clk", &gcc, 0x0063 }, - { "gcc_blsp2_qup3_spi_apps_clk", &gcc, 0x0065 }, - { "gcc_blsp2_qup3_i2c_apps_clk", &gcc, 0x0066 }, - { "gcc_blsp2_uart3_apps_clk", &gcc, 0x0067 }, - { "gcc_blsp2_qup4_spi_apps_clk", &gcc, 0x0069 }, - { "gcc_blsp2_qup4_i2c_apps_clk", &gcc, 0x006a }, - { "gcc_blsp2_uart4_apps_clk", &gcc, 0x006b }, - { "gcc_blsp2_qup5_spi_apps_clk", &gcc, 0x006d }, - { "gcc_blsp2_qup5_i2c_apps_clk", &gcc, 0x006e }, - { "gcc_blsp2_uart5_apps_clk", &gcc, 0x006f }, - { "gcc_blsp2_qup6_spi_apps_clk", &gcc, 0x0071 }, - { "gcc_blsp2_qup6_i2c_apps_clk", &gcc, 0x0072 }, - { "gcc_blsp2_uart6_apps_clk", &gcc, 0x0073 }, - { "gcc_pdm_ahb_clk", &gcc, 0x0076 }, - { "gcc_pdm2_clk", &gcc, 0x0078 }, - { "gcc_prng_ahb_clk", &gcc, 0x0079 }, - { "gcc_tsif_ahb_clk", &gcc, 0x007a }, - { "gcc_tsif_ref_clk", &gcc, 0x007b }, - { "gcc_boot_rom_ahb_clk", &gcc, 0x007e }, - { "ce1_clk", &gcc, 0x0099 }, - { "gcc_ce1_axi_m_clk", &gcc, 0x009a }, - { "gcc_ce1_ahb_m_clk", &gcc, 0x009b }, - { "measure_only_bimc_hmss_axi_clk", &gcc, 0x00a5 }, - { "bimc_clk", &gcc, 0x00ad }, - { "gcc_bimc_gfx_clk", &gcc, 0x00af}, - { "gcc_hmss_rbcpr_clk", &gcc, 0x00ba }, - //{ "cpu_dbg_clk", &gcc, 0x00bb }, - { "cpu_cbf_clk", &gcc, 0x00bb, &cpu_cc, 0x01 }, - { "cpu_pwr_clk", &gcc, 0x00bb, &cpu_cc, 0x11, 16 }, - { "cpu_perf_clk", &gcc, 0x00bb, &cpu_cc, 0x21, 16 }, - { "gcc_gp1_clk", &gcc, 0x00e3 }, - { "gcc_gp2_clk", &gcc, 0x00e4 }, - { "gcc_gp3_clk", &gcc, 0x00e5 }, - { "gcc_pcie_0_slv_axi_clk", &gcc, 0x00e6 }, - { "gcc_pcie_0_mstr_axi_clk", &gcc, 0x00e7 }, - { "gcc_pcie_0_cfg_ahb_clk", &gcc, 0x00e8 }, - { "gcc_pcie_0_aux_clk", &gcc, 0x00e9 }, - { "gcc_pcie_0_pipe_clk", &gcc, 0x00ea }, - { "gcc_pcie_1_slv_axi_clk", &gcc, 0x00ec }, - { "gcc_pcie_1_mstr_axi_clk", &gcc, 0x00ed }, - { "gcc_pcie_1_cfg_ahb_clk", &gcc, 0x00ee }, - { "gcc_pcie_1_aux_clk", &gcc, 0x00ef }, - { "gcc_pcie_1_pipe_clk", &gcc, 0x00f0 }, - { "gcc_pcie_2_slv_axi_clk", &gcc, 0x00f2 }, - { "gcc_pcie_2_mstr_axi_clk", &gcc, 0x00f3 }, - { "gcc_pcie_2_cfg_ahb_clk", &gcc, 0x00f4 }, - { "gcc_pcie_2_aux_clk", &gcc, 0x00f5 }, - { "gcc_pcie_2_pipe_clk", &gcc, 0x00f6 }, - { "gcc_pcie_phy_cfg_ahb_clk", &gcc, 0x00f8 }, - { "gcc_pcie_phy_aux_clk", &gcc, 0x00f9 }, - { "gcc_ufs_axi_clk", &gcc, 0x00fc }, - { "gcc_ufs_ahb_clk", &gcc, 0x00fd }, - { "gcc_ufs_tx_cfg_clk", &gcc, 0x00fe }, - { "gcc_ufs_rx_cfg_clk", &gcc, 0x00ff }, - { "gcc_ufs_tx_symbol_0_clk", &gcc, 0x0100 }, - { "gcc_ufs_rx_symbol_0_clk", &gcc, 0x0101 }, - { "gcc_ufs_rx_symbol_1_clk", &gcc, 0x0102 }, - { "gcc_ufs_unipro_core_clk", &gcc, 0x0106 }, - { "gcc_ufs_ice_core_clk", &gcc, 0x0107 }, - { "gcc_ufs_sys_clk_core_clk", &gcc, 0x108}, - { "gcc_ufs_tx_symbol_clk_core_clk", &gcc, 0x0109 }, - { "gcc_aggre0_snoc_axi_clk", &gcc, 0x0116 }, - { "gcc_aggre0_cnoc_ahb_clk", &gcc, 0x0117 }, - { "gcc_smmu_aggre0_axi_clk", &gcc, 0x0119 }, - { "gcc_smmu_aggre0_ahb_clk", &gcc, 0x011a }, - { "gcc_aggre0_noc_qosgen_extref_clk", &gcc, 0x011b }, - { "gcc_aggre2_ufs_axi_clk", &gcc, 0x0126 }, - { "gcc_aggre2_usb3_axi_clk", &gcc, 0x0127 }, - { "gcc_dcc_ahb_clk", &gcc, 0x012b }, - { "gcc_aggre0_noc_mpu_cfg_ahb_clk", &gcc, 0x012c}, - { "ipa_clk", &gcc, 0x12f }, - { "gcc_mss_cfg_ahb_clk", &gcc, 0x0133 }, - { "gcc_mss_mnoc_bimc_axi_clk", &gcc, 0x0134 }, - { "gcc_mss_snoc_axi_clk", &gcc, 0x0135 }, - { "gcc_mss_q6_bimc_axi_clk", &gcc, 0x0136 }, + { "snoc_clk", &gcc.mux, 0x0000 }, + { "gcc_sys_noc_usb3_axi_clk", &gcc.mux, 0x0006 }, + { "gcc_sys_noc_ufs_axi_clk", &gcc.mux, 0x0007 }, + { "cnoc_clk", &gcc.mux, 0x000e }, + { "pnoc_clk", &gcc.mux, 0x0011 }, + { "gcc_periph_noc_usb20_ahb_clk", &gcc.mux, 0x0014 }, + { "gcc_mmss_noc_cfg_ahb_clk", &gcc.mux, 0x0019 }, + { "mmss_mmagic_ahb_clk", &mmss_cc, 0x0001 }, + { "mmss_misc_ahb_clk", &mmss_cc, 0x0003 }, + { "vmem_maxi_clk", &mmss_cc, 0x0009 }, + { "vmem_ahb_clk", &mmss_cc, 0x000a }, + { "gpu_ahb_clk", &mmss_cc, 0x000c }, + { "gpu_gx_gfx3d_clk", &mmss_cc, 0x000d }, + { "video_core_clk", &mmss_cc, 0x000e }, + { "video_axi_clk", &mmss_cc, 0x000f }, + { "video_maxi_clk", &mmss_cc, 0x0010 }, + { "video_ahb_clk", &mmss_cc, 0x0011 }, + { "mmss_rbcpr_clk", &mmss_cc, 0x0012 }, + { "mmss_rbcpr_ahb_clk", &mmss_cc, 0x0013 }, + { "mdss_mdp_clk", &mmss_cc, 0x0014 }, + { "mdss_pclk0_clk", &mmss_cc, 0x0016 }, + { "mdss_pclk1_clk", &mmss_cc, 0x0017 }, + { "mdss_extpclk_clk", &mmss_cc, 0x0018 }, + { "video_subcore0_clk", &mmss_cc, 0x001a }, + { "video_subcore1_clk", &mmss_cc, 0x001b }, + { "mdss_vsync_clk", &mmss_cc, 0x001c }, + { "mdss_hdmi_clk", &mmss_cc, 0x001d }, + { "mdss_byte0_clk", &mmss_cc, 0x001e }, + { "mdss_byte1_clk", &mmss_cc, 0x001f }, + { "mdss_esc0_clk", &mmss_cc, 0x0020 }, + { "mdss_esc1_clk", &mmss_cc, 0x0021 }, + { "mdss_ahb_clk", &mmss_cc, 0x0022 }, + { "mdss_hdmi_ahb_clk", &mmss_cc, 0x0023 }, + { "mdss_axi_clk", &mmss_cc, 0x0024 }, + { "camss_top_ahb_clk", &mmss_cc, 0x0025 }, + { "camss_micro_ahb_clk", &mmss_cc, 0x0026 }, + { "camss_gp0_clk", &mmss_cc, 0x0027 }, + { "camss_gp1_clk", &mmss_cc, 0x0028 }, + { "camss_mclk0_clk", &mmss_cc, 0x0029 }, + { "camss_mclk1_clk", &mmss_cc, 0x002a }, + { "camss_mclk2_clk", &mmss_cc, 0x002b }, + { "camss_mclk3_clk", &mmss_cc, 0x002c }, + { "camss_cci_clk", &mmss_cc, 0x002d }, + { "camss_cci_ahb_clk", &mmss_cc, 0x002e }, + { "camss_csi0phytimer_clk", &mmss_cc, 0x002f }, + { "camss_csi1phytimer_clk", &mmss_cc, 0x0030 }, + { "camss_csi2phytimer_clk", &mmss_cc, 0x0031 }, + { "camss_jpeg0_clk", &mmss_cc, 0x0032 }, + { "camss_ispif_ahb_clk", &mmss_cc, 0x0033 }, + { "camss_jpeg2_clk", &mmss_cc, 0x0034 }, + { "camss_jpeg_ahb_clk", &mmss_cc, 0x0035 }, + { "camss_jpeg_axi_clk", &mmss_cc, 0x0036 }, + { "camss_ahb_clk", &mmss_cc, 0x0037 }, + { "camss_vfe0_clk", &mmss_cc, 0x0038 }, + { "camss_vfe1_clk", &mmss_cc, 0x0039 }, + { "camss_cpp_clk", &mmss_cc, 0x003a }, + { "camss_cpp_ahb_clk", &mmss_cc, 0x003b }, + { "camss_vfe_ahb_clk", &mmss_cc, 0x003c }, + { "camss_vfe_axi_clk", &mmss_cc, 0x003d }, + { "gpu_gx_rbbmtimer_clk", &mmss_cc, 0x003e }, + { "camss_csi_vfe0_clk", &mmss_cc, 0x003f }, + { "camss_csi_vfe1_clk", &mmss_cc, 0x0040 }, + { "camss_csi0_clk", &mmss_cc, 0x0041 }, + { "camss_csi0_ahb_clk", &mmss_cc, 0x0042 }, + { "camss_csi0phy_clk", &mmss_cc, 0x0043 }, + { "camss_csi0rdi_clk", &mmss_cc, 0x0044 }, + { "camss_csi0pix_clk", &mmss_cc, 0x0045 }, + { "camss_csi1_clk", &mmss_cc, 0x0046 }, + { "camss_csi1_ahb_clk", &mmss_cc, 0x0047 }, + { "camss_csi1phy_clk", &mmss_cc, 0x0048 }, + { "camss_csi1rdi_clk", &mmss_cc, 0x0049 }, + { "camss_csi1pix_clk", &mmss_cc, 0x004a }, + { "camss_csi2_clk", &mmss_cc, 0x004b }, + { "camss_csi2_ahb_clk", &mmss_cc, 0x004c }, + { "camss_csi2phy_clk", &mmss_cc, 0x004d }, + { "camss_csi2rdi_clk", &mmss_cc, 0x004e }, + { "camss_csi2pix_clk", &mmss_cc, 0x004f }, + { "camss_csi3_clk", &mmss_cc, 0x0050 }, + { "camss_csi3_ahb_clk", &mmss_cc, 0x0051 }, + { "camss_csi3phy_clk", &mmss_cc, 0x0052 }, + { "camss_csi3rdi_clk", &mmss_cc, 0x0053 }, + { "camss_csi3pix_clk", &mmss_cc, 0x0054 }, + { "mmss_mmagic_maxi_clk", &mmss_cc, 0x0070 }, + { "camss_vfe0_stream_clk", &mmss_cc, 0x0071 }, + { "camss_vfe1_stream_clk", &mmss_cc, 0x0072 }, + { "camss_cpp_vbif_ahb_clk", &mmss_cc, 0x0073 }, + { "mmss_mmagic_cfg_ahb_clk", &mmss_cc, 0x0074 }, + { "mmss_misc_cxo_clk", &mmss_cc, 0x0077 }, + { "camss_cpp_axi_clk", &mmss_cc, 0x007a }, + { "camss_jpeg_dma_clk", &mmss_cc, 0x007b }, + { "camss_vfe0_ahb_clk", &mmss_cc, 0x0086 }, + { "camss_vfe1_ahb_clk", &mmss_cc, 0x0087 }, + { "gpu_aon_isense_clk", &mmss_cc, 0x0088 }, + { "fd_core_clk", &mmss_cc, 0x0089 }, + { "fd_core_uar_clk", &mmss_cc, 0x008a }, + { "fd_ahb_clk", &mmss_cc, 0x008c }, + { "camss_csiphy0_3p_clk", &mmss_cc, 0x0091 }, + { "camss_csiphy1_3p_clk", &mmss_cc, 0x0092 }, + { "camss_csiphy2_3p_clk", &mmss_cc, 0x0093 }, + { "smmu_vfe_ahb_clk", &mmss_cc, 0x0094 }, + { "smmu_vfe_axi_clk", &mmss_cc, 0x0095 }, + { "smmu_cpp_ahb_clk", &mmss_cc, 0x0096 }, + { "smmu_cpp_axi_clk", &mmss_cc, 0x0097 }, + { "smmu_jpeg_ahb_clk", &mmss_cc, 0x0098 }, + { "smmu_jpeg_axi_clk", &mmss_cc, 0x0099 }, + { "mmagic_camss_axi_clk", &mmss_cc, 0x009a }, + { "smmu_rot_ahb_clk", &mmss_cc, 0x009b }, + { "smmu_rot_axi_clk", &mmss_cc, 0x009c }, + { "smmu_mdp_ahb_clk", &mmss_cc, 0x009d }, + { "smmu_mdp_axi_clk", &mmss_cc, 0x009e }, + { "mmagic_mdss_axi_clk", &mmss_cc, 0x009f }, + { "smmu_video_ahb_clk", &mmss_cc, 0x00a0 }, + { "smmu_video_axi_clk", &mmss_cc, 0x00a1 }, + { "mmagic_video_axi_clk", &mmss_cc, 0x00a2 }, + { "mmagic_camss_noc_cfg_ahb_clk", &mmss_cc, 0x00ad }, + { "mmagic_mdss_noc_cfg_ahb_clk", &mmss_cc, 0x00ae }, + { "mmagic_video_noc_cfg_ahb_clk", &mmss_cc, 0x00af }, + { "mmagic_bimc_noc_cfg_ahb_clk", &mmss_cc, 0x00b0 }, + { "gcc_mmss_bimc_gfx_clk", &gcc.mux, 0x001c}, + { "gcc_usb30_master_clk", &gcc.mux, 0x002d }, + { "gcc_usb30_sleep_clk", &gcc.mux, 0x002e }, + { "gcc_usb30_mock_utmi_clk", &gcc.mux, 0x002f }, + { "gcc_usb3_phy_aux_clk", &gcc.mux, 0x0030 }, + { "gcc_usb3_phy_pipe_clk", &gcc.mux, 0x0031 }, + { "gcc_usb20_master_clk", &gcc.mux, 0x0035 }, + { "gcc_usb20_sleep_clk", &gcc.mux, 0x0036 }, + { "gcc_usb20_mock_utmi_clk", &gcc.mux, 0x0037 }, + { "gcc_usb_phy_cfg_ahb2phy_clk", &gcc.mux, 0x0038 }, + { "gcc_sdcc1_apps_clk", &gcc.mux, 0x0039 }, + { "gcc_sdcc1_ahb_clk", &gcc.mux, 0x003a }, + { "gcc_sdcc2_apps_clk", &gcc.mux, 0x003b }, + { "gcc_sdcc2_ahb_clk", &gcc.mux, 0x003c }, + { "gcc_sdcc3_apps_clk", &gcc.mux, 0x003d }, + { "gcc_sdcc3_ahb_clk", &gcc.mux, 0x003e }, + { "gcc_sdcc4_apps_clk", &gcc.mux, 0x003f }, + { "gcc_sdcc4_ahb_clk", &gcc.mux, 0x0040 }, + { "gcc_blsp1_ahb_clk", &gcc.mux, 0x0041 }, + { "gcc_blsp1_qup1_spi_apps_clk", &gcc.mux, 0x0043 }, + { "gcc_blsp1_qup1_i2c_apps_clk", &gcc.mux, 0x0044 }, + { "gcc_blsp1_uart1_apps_clk", &gcc.mux, 0x0045 }, + { "gcc_blsp1_qup2_spi_apps_clk", &gcc.mux, 0x0047 }, + { "gcc_blsp1_qup2_i2c_apps_clk", &gcc.mux, 0x0048 }, + { "gcc_blsp1_uart2_apps_clk", &gcc.mux, 0x0049 }, + { "gcc_blsp1_qup3_spi_apps_clk", &gcc.mux, 0x004b }, + { "gcc_blsp1_qup3_i2c_apps_clk", &gcc.mux, 0x004c }, + { "gcc_blsp1_uart3_apps_clk", &gcc.mux, 0x004d }, + { "gcc_blsp1_qup4_spi_apps_clk", &gcc.mux, 0x004f }, + { "gcc_blsp1_qup4_i2c_apps_clk", &gcc.mux, 0x0050 }, + { "gcc_blsp1_uart4_apps_clk", &gcc.mux, 0x0051 }, + { "gcc_blsp1_qup5_spi_apps_clk", &gcc.mux, 0x0053 }, + { "gcc_blsp1_qup5_i2c_apps_clk", &gcc.mux, 0x0054 }, + { "gcc_blsp1_uart5_apps_clk", &gcc.mux, 0x0055 }, + { "gcc_blsp1_qup6_spi_apps_clk", &gcc.mux, 0x0057 }, + { "gcc_blsp1_qup6_i2c_apps_clk", &gcc.mux, 0x0058 }, + { "gcc_blsp1_uart6_apps_clk", &gcc.mux, 0x0059 }, + { "gcc_blsp2_ahb_clk", &gcc.mux, 0x005b }, + { "gcc_blsp2_qup1_spi_apps_clk", &gcc.mux, 0x005d }, + { "gcc_blsp2_qup1_i2c_apps_clk", &gcc.mux, 0x005e }, + { "gcc_blsp2_uart1_apps_clk", &gcc.mux, 0x005f }, + { "gcc_blsp2_qup2_spi_apps_clk", &gcc.mux, 0x0061 }, + { "gcc_blsp2_qup2_i2c_apps_clk", &gcc.mux, 0x0062 }, + { "gcc_blsp2_uart2_apps_clk", &gcc.mux, 0x0063 }, + { "gcc_blsp2_qup3_spi_apps_clk", &gcc.mux, 0x0065 }, + { "gcc_blsp2_qup3_i2c_apps_clk", &gcc.mux, 0x0066 }, + { "gcc_blsp2_uart3_apps_clk", &gcc.mux, 0x0067 }, + { "gcc_blsp2_qup4_spi_apps_clk", &gcc.mux, 0x0069 }, + { "gcc_blsp2_qup4_i2c_apps_clk", &gcc.mux, 0x006a }, + { "gcc_blsp2_uart4_apps_clk", &gcc.mux, 0x006b }, + { "gcc_blsp2_qup5_spi_apps_clk", &gcc.mux, 0x006d }, + { "gcc_blsp2_qup5_i2c_apps_clk", &gcc.mux, 0x006e }, + { "gcc_blsp2_uart5_apps_clk", &gcc.mux, 0x006f }, + { "gcc_blsp2_qup6_spi_apps_clk", &gcc.mux, 0x0071 }, + { "gcc_blsp2_qup6_i2c_apps_clk", &gcc.mux, 0x0072 }, + { "gcc_blsp2_uart6_apps_clk", &gcc.mux, 0x0073 }, + { "gcc_pdm_ahb_clk", &gcc.mux, 0x0076 }, + { "gcc_pdm2_clk", &gcc.mux, 0x0078 }, + { "gcc_prng_ahb_clk", &gcc.mux, 0x0079 }, + { "gcc_tsif_ahb_clk", &gcc.mux, 0x007a }, + { "gcc_tsif_ref_clk", &gcc.mux, 0x007b }, + { "gcc_boot_rom_ahb_clk", &gcc.mux, 0x007e }, + { "ce1_clk", &gcc.mux, 0x0099 }, + { "gcc_ce1_axi_m_clk", &gcc.mux, 0x009a }, + { "gcc_ce1_ahb_m_clk", &gcc.mux, 0x009b }, + { "measure_only_bimc_hmss_axi_clk", &gcc.mux, 0x00a5 }, + { "bimc_clk", &gcc.mux, 0x00ad }, + { "gcc_bimc_gfx_clk", &gcc.mux, 0x00af}, + { "gcc_hmss_rbcpr_clk", &gcc.mux, 0x00ba }, + { "cpu_cbf_clk", &cpu_cc, 0x01 }, + { "cpu_pwr_clk", &cpu_cc, 0x11, 16 }, + { "cpu_perf_clk", &cpu_cc, 0x21, 16 }, + { "gcc_gp1_clk", &gcc.mux, 0x00e3 }, + { "gcc_gp2_clk", &gcc.mux, 0x00e4 }, + { "gcc_gp3_clk", &gcc.mux, 0x00e5 }, + { "gcc_pcie_0_slv_axi_clk", &gcc.mux, 0x00e6 }, + { "gcc_pcie_0_mstr_axi_clk", &gcc.mux, 0x00e7 }, + { "gcc_pcie_0_cfg_ahb_clk", &gcc.mux, 0x00e8 }, + { "gcc_pcie_0_aux_clk", &gcc.mux, 0x00e9 }, + { "gcc_pcie_0_pipe_clk", &gcc.mux, 0x00ea }, + { "gcc_pcie_1_slv_axi_clk", &gcc.mux, 0x00ec }, + { "gcc_pcie_1_mstr_axi_clk", &gcc.mux, 0x00ed }, + { "gcc_pcie_1_cfg_ahb_clk", &gcc.mux, 0x00ee }, + { "gcc_pcie_1_aux_clk", &gcc.mux, 0x00ef }, + { "gcc_pcie_1_pipe_clk", &gcc.mux, 0x00f0 }, + { "gcc_pcie_2_slv_axi_clk", &gcc.mux, 0x00f2 }, + { "gcc_pcie_2_mstr_axi_clk", &gcc.mux, 0x00f3 }, + { "gcc_pcie_2_cfg_ahb_clk", &gcc.mux, 0x00f4 }, + { "gcc_pcie_2_aux_clk", &gcc.mux, 0x00f5 }, + { "gcc_pcie_2_pipe_clk", &gcc.mux, 0x00f6 }, + { "gcc_pcie_phy_cfg_ahb_clk", &gcc.mux, 0x00f8 }, + { "gcc_pcie_phy_aux_clk", &gcc.mux, 0x00f9 }, + { "gcc_ufs_axi_clk", &gcc.mux, 0x00fc }, + { "gcc_ufs_ahb_clk", &gcc.mux, 0x00fd }, + { "gcc_ufs_tx_cfg_clk", &gcc.mux, 0x00fe }, + { "gcc_ufs_rx_cfg_clk", &gcc.mux, 0x00ff }, + { "gcc_ufs_tx_symbol_0_clk", &gcc.mux, 0x0100 }, + { "gcc_ufs_rx_symbol_0_clk", &gcc.mux, 0x0101 }, + { "gcc_ufs_rx_symbol_1_clk", &gcc.mux, 0x0102 }, + { "gcc_ufs_unipro_core_clk", &gcc.mux, 0x0106 }, + { "gcc_ufs_ice_core_clk", &gcc.mux, 0x0107 }, + { "gcc_ufs_sys_clk_core_clk", &gcc.mux, 0x108}, + { "gcc_ufs_tx_symbol_clk_core_clk", &gcc.mux, 0x0109 }, + { "gcc_aggre0_snoc_axi_clk", &gcc.mux, 0x0116 }, + { "gcc_aggre0_cnoc_ahb_clk", &gcc.mux, 0x0117 }, + { "gcc_smmu_aggre0_axi_clk", &gcc.mux, 0x0119 }, + { "gcc_smmu_aggre0_ahb_clk", &gcc.mux, 0x011a }, + { "gcc_aggre0_noc_qosgen_extref_clk", &gcc.mux, 0x011b }, + { "gcc_aggre2_ufs_axi_clk", &gcc.mux, 0x0126 }, + { "gcc_aggre2_usb3_axi_clk", &gcc.mux, 0x0127 }, + { "gcc_dcc_ahb_clk", &gcc.mux, 0x012b }, + { "gcc_aggre0_noc_mpu_cfg_ahb_clk", &gcc.mux, 0x012c}, + { "ipa_clk", &gcc.mux, 0x12f }, + { "gcc_mss_cfg_ahb_clk", &gcc.mux, 0x0133 }, + { "gcc_mss_mnoc_bimc_axi_clk", &gcc.mux, 0x0134 }, + { "gcc_mss_snoc_axi_clk", &gcc.mux, 0x0135 }, + { "gcc_mss_q6_bimc_axi_clk", &gcc.mux, 0x0136 }, {} }; diff --git a/msm8998.c b/msm8998.c index acbd443..fbcdb07 100644 --- a/msm8998.c +++ b/msm8998.c @@ -12,19 +12,23 @@ #include "debugcc.h" -static struct debug_mux gcc = { - .phys = 0x100000, - .size = 0xb0000, +static struct gcc_mux gcc = { + .mux = { + .phys = 0x100000, + .size = 0xb0000, - .enable_reg = 0x62000, - .enable_mask = BIT(16), + .measure = measure_gcc, - .mux_reg = 0x62000, - .mux_mask = 0x3ff, + .enable_reg = 0x62000, + .enable_mask = BIT(16), - .div_reg = 0x62000, - .div_mask = 0xf, - .div_val = 4, + .mux_reg = 0x62000, + .mux_mask = 0x3ff, + + .div_reg = 0x62000, + .div_mask = 0xf, + .div_val = 4, + }, .xo_div4_reg = 0x43008, .debug_ctl_reg = 0x62004, @@ -36,6 +40,10 @@ static struct debug_mux mm_cc = { .size = 0x40000, .block_name = "mm", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x22, + .enable_reg = 0x900, .enable_mask = BIT(16), @@ -48,6 +56,10 @@ static struct debug_mux gpu_cc = { .size = 0x9000, .block_name = "gpu", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x13d, + .enable_reg = 0x120, .enable_mask = BIT(16), @@ -56,194 +68,191 @@ static struct debug_mux gpu_cc = { }; static struct measure_clk msm8998_clocks[] = { - // { "gpu_gcc_debug_clk", &gcc, 0x13d }, - // { "gfx_gcc_debug_clk", &gcc, 0x13d }, - // { "debug_mmss_clk", &gcc, 0x22 }, - // { "debug_cpu_clk", &gcc, 0xc0 }, - - { "snoc_clk", &gcc, 0x0 }, - { "cnoc_clk", &gcc, 0xe }, - { "bimc_clk", &gcc, 0x14e }, - { "gcc_mmss_sys_noc_axi_clk", &gcc, 0x1f }, - { "gcc_mmss_noc_cfg_ahb_clk", &gcc, 0x20 }, - { "gcc_usb30_master_clk", &gcc, 0x3e }, - { "gcc_usb30_sleep_clk", &gcc, 0x3f }, - { "gcc_usb30_mock_utmi_clk", &gcc, 0x40 }, - { "gcc_usb3_phy_aux_clk", &gcc, 0x41 }, - { "gcc_usb3_phy_pipe_clk", &gcc, 0x42 }, - { "gcc_sdcc2_apps_clk", &gcc, 0x46 }, - { "gcc_sdcc2_ahb_clk", &gcc, 0x47 }, - { "gcc_sdcc4_apps_clk", &gcc, 0x48 }, - { "gcc_sdcc4_ahb_clk", &gcc, 0x49 }, - { "gcc_blsp1_ahb_clk", &gcc, 0x4a }, - { "gcc_blsp1_qup1_spi_apps_clk", &gcc, 0x4c }, - { "gcc_blsp1_qup1_i2c_apps_clk", &gcc, 0x4d }, - { "gcc_blsp1_uart1_apps_clk", &gcc, 0x4e }, - { "gcc_blsp1_qup2_spi_apps_clk", &gcc, 0x50 }, - { "gcc_blsp1_qup2_i2c_apps_clk", &gcc, 0x51 }, - { "gcc_blsp1_uart2_apps_clk", &gcc, 0x52 }, - { "gcc_blsp1_qup3_spi_apps_clk", &gcc, 0x54 }, - { "gcc_blsp1_qup3_i2c_apps_clk", &gcc, 0x55 }, - { "gcc_blsp1_uart3_apps_clk", &gcc, 0x56 }, - { "gcc_blsp1_qup4_spi_apps_clk", &gcc, 0x58 }, - { "gcc_blsp1_qup4_i2c_apps_clk", &gcc, 0x59 }, - { "gcc_blsp1_qup5_spi_apps_clk", &gcc, 0x5a }, - { "gcc_blsp1_qup5_i2c_apps_clk", &gcc, 0x5b }, - { "gcc_blsp1_qup6_spi_apps_clk", &gcc, 0x5c }, - { "gcc_blsp1_qup6_i2c_apps_clk", &gcc, 0x5d }, - { "gcc_blsp2_ahb_clk", &gcc, 0x5e }, - { "gcc_blsp2_qup1_spi_apps_clk", &gcc, 0x60 }, - { "gcc_blsp2_qup1_i2c_apps_clk", &gcc, 0x61 }, - { "gcc_blsp2_uart1_apps_clk", &gcc, 0x62 }, - { "gcc_blsp2_qup2_spi_apps_clk", &gcc, 0x64 }, - { "gcc_blsp2_qup2_i2c_apps_clk", &gcc, 0x65 }, - { "gcc_blsp2_uart2_apps_clk", &gcc, 0x66 }, - { "gcc_blsp2_qup3_spi_apps_clk", &gcc, 0x68 }, - { "gcc_blsp2_qup3_i2c_apps_clk", &gcc, 0x69 }, - { "gcc_blsp2_uart3_apps_clk", &gcc, 0x6a }, - { "gcc_blsp2_qup4_spi_apps_clk", &gcc, 0x6c }, - { "gcc_blsp2_qup4_i2c_apps_clk", &gcc, 0x6d }, - { "gcc_blsp2_qup5_spi_apps_clk", &gcc, 0x6e }, - { "gcc_blsp2_qup5_i2c_apps_clk", &gcc, 0x6f }, - { "gcc_blsp2_qup6_spi_apps_clk", &gcc, 0x70 }, - { "gcc_blsp2_qup6_i2c_apps_clk", &gcc, 0x71 }, - { "gcc_pdm_ahb_clk", &gcc, 0x72 }, - { "gcc_pdm2_clk", &gcc, 0x74}, - { "gcc_prng_ahb_clk", &gcc, 0x75 }, - { "gcc_tsif_ahb_clk", &gcc, 0x76 }, - { "gcc_tsif_ref_clk", &gcc, 0x77 }, - { "gcc_boot_rom_ahb_clk", &gcc, 0x7a }, - { "ce1_clk", &gcc, 0x97 }, - { "gcc_ce1_axi_m_clk", &gcc, 0x98 }, - { "gcc_ce1_ahb_m_clk", &gcc, 0x99 }, - { "measure_only_bimc_hmss_axi_clk", &gcc, 0xbb }, - { "gcc_bimc_gfx_clk", &gcc, 0xac }, - { "gcc_hmss_rbcpr_clk", &gcc, 0xbc }, - { "gcc_gp1_clk", &gcc, 0xdf }, - { "gcc_gp2_clk", &gcc, 0xe0 }, - { "gcc_gp3_clk", &gcc, 0xe1 }, - { "gcc_pcie_0_slv_axi_clk", &gcc, 0xe2 }, - { "gcc_pcie_0_mstr_axi_clk", &gcc, 0xe3 }, - { "gcc_pcie_0_cfg_ahb_clk", &gcc, 0xe4 }, - { "gcc_pcie_0_aux_clk", &gcc, 0xe5 }, - { "gcc_pcie_0_pipe_clk", &gcc, 0xe6 }, - { "gcc_pcie_phy_aux_clk", &gcc, 0xe8 }, - { "gcc_ufs_axi_clk", &gcc, 0xea }, - { "gcc_ufs_ahb_clk", &gcc, 0xeb }, - { "gcc_ufs_tx_symbol_0_clk", &gcc, 0xec }, - { "gcc_ufs_rx_symbol_0_clk", &gcc, 0xed }, - { "gcc_ufs_rx_symbol_1_clk", &gcc, 0x162 }, - { "gcc_ufs_unipro_core_clk", &gcc, 0xf0 }, - { "gcc_ufs_ice_core_clk", &gcc, 0xf1 }, - { "gcc_dcc_ahb_clk", &gcc, 0x119 }, - { "ipa_clk", &gcc, 0x11b }, - { "gcc_mss_cfg_ahb_clk", &gcc, 0x11f }, - { "gcc_mss_q6_bimc_axi_clk", &gcc, 0x124 }, - { "gcc_mss_mnoc_bimc_axi_clk", &gcc, 0x120 }, - { "gcc_mss_snoc_axi_clk", &gcc, 0x123 }, - { "gcc_gpu_cfg_ahb_clk", &gcc, 0x13b }, - { "gcc_gpu_bimc_gfx_clk", &gcc, 0x13f }, - { "gcc_qspi_ahb_clk", &gcc, 0x156 }, - { "gcc_qspi_ref_clk", &gcc, 0x157 }, - - { "mmss_mnoc_ahb_clk", &gcc, 0x22, &mm_cc, 0x1 }, - { "mmss_misc_ahb_clk", &gcc, 0x22, &mm_cc, 0x3 }, - { "mmss_vmem_maxi_clk", &gcc, 0x22, &mm_cc, 0x9 }, - { "mmss_vmem_ahb_clk", &gcc, 0x22, &mm_cc, 0xa }, - { "mmss_bimc_smmu_ahb_clk", &gcc, 0x22, &mm_cc, 0xc }, - { "mmss_bimc_smmu_axi_clk", &gcc, 0x22, &mm_cc, 0xd }, - { "mmss_video_core_clk", &gcc, 0x22, &mm_cc, 0xe }, - { "mmss_video_axi_clk", &gcc, 0x22, &mm_cc, 0xf }, - { "mmss_video_maxi_clk", &gcc, 0x22, &mm_cc, 0x10 }, - { "mmss_video_ahb_clk", &gcc, 0x22, &mm_cc, 0x11 }, - { "mmss_mdss_rot_clk", &gcc, 0x22, &mm_cc, 0x12 }, - { "mmss_snoc_dvm_axi_clk", &gcc, 0x22, &mm_cc, 0x13 }, - { "mmss_mdss_mdp_clk", &gcc, 0x22, &mm_cc, 0x14 }, - { "mmss_mdss_mdp_lut_clk", &gcc, 0x22, &mm_cc, 0x15 }, - { "mmss_mdss_pclk0_clk", &gcc, 0x22, &mm_cc, 0x16 }, - { "mmss_mdss_pclk1_clk", &gcc, 0x22, &mm_cc, 0x17 }, - { "mmss_mdss_extpclk_clk", &gcc, 0x22, &mm_cc, 0x18 }, - { "mmss_video_subcore0_clk", &gcc, 0x22, &mm_cc, 0x1a }, - { "mmss_video_subcore1_clk", &gcc, 0x22, &mm_cc, 0x1b }, - { "mmss_mdss_vsync_clk", &gcc, 0x22, &mm_cc, 0x1c }, - { "mmss_mdss_hdmi_clk", &gcc, 0x22, &mm_cc, 0x1d }, - { "mmss_mdss_byte0_clk", &gcc, 0x22, &mm_cc, 0x1e }, - { "mmss_mdss_byte1_clk", &gcc, 0x22, &mm_cc, 0x1f }, - { "mmss_mdss_esc0_clk", &gcc, 0x22, &mm_cc, 0x20 }, - { "mmss_mdss_esc1_clk", &gcc, 0x22, &mm_cc, 0x21 }, - { "mmss_mdss_ahb_clk", &gcc, 0x22, &mm_cc, 0x22 }, - { "mmss_mdss_hdmi_dp_ahb_clk", &gcc, 0x22, &mm_cc, 0x23 }, - { "mmss_mdss_axi_clk", &gcc, 0x22, &mm_cc, 0x24 }, - { "mmss_camss_top_ahb_clk", &gcc, 0x22, &mm_cc, 0x25 }, - { "mmss_camss_micro_ahb_clk", &gcc, 0x22, &mm_cc, 0x26 }, - { "mmss_camss_gp0_clk", &gcc, 0x22, &mm_cc, 0x27 }, - { "mmss_camss_gp1_clk", &gcc, 0x22, &mm_cc, 0x28 }, - { "mmss_camss_mclk0_clk", &gcc, 0x22, &mm_cc, 0x29 }, - { "mmss_camss_mclk1_clk", &gcc, 0x22, &mm_cc, 0x2a }, - { "mmss_camss_mclk2_clk", &gcc, 0x22, &mm_cc, 0x2b }, - { "mmss_camss_mclk3_clk", &gcc, 0x22, &mm_cc, 0x2c }, - { "mmss_camss_cci_clk", &gcc, 0x22, &mm_cc, 0x2d }, - { "mmss_camss_cci_ahb_clk", &gcc, 0x22, &mm_cc, 0x2e }, - { "mmss_camss_csi0phytimer_clk", &gcc, 0x22, &mm_cc, 0x2f }, - { "mmss_camss_csi1phytimer_clk", &gcc, 0x22, &mm_cc, 0x30 }, - { "mmss_camss_csi2phytimer_clk", &gcc, 0x22, &mm_cc, 0x31 }, - { "mmss_camss_jpeg0_clk", &gcc, 0x22, &mm_cc, 0x32 }, - { "mmss_camss_ispif_ahb_clk", &gcc, 0x22, &mm_cc, 0x33 }, - { "mmss_camss_jpeg_ahb_clk", &gcc, 0x22, &mm_cc, 0x35 }, - { "mmss_camss_jpeg_axi_clk", &gcc, 0x22, &mm_cc, 0x36 }, - { "mmss_camss_ahb_clk", &gcc, 0x22, &mm_cc, 0x37 }, - { "mmss_camss_vfe0_clk", &gcc, 0x22, &mm_cc, 0x38 }, - { "mmss_camss_vfe1_clk", &gcc, 0x22, &mm_cc, 0x39 }, - { "mmss_camss_cpp_clk", &gcc, 0x22, &mm_cc, 0x3a }, - { "mmss_camss_cpp_ahb_clk", &gcc, 0x22, &mm_cc, 0x3b }, - { "mmss_camss_csi_vfe0_clk", &gcc, 0x22, &mm_cc, 0x3f }, - { "mmss_camss_csi_vfe1_clk", &gcc, 0x22, &mm_cc, 0x40 }, - { "mmss_camss_csi0_clk", &gcc, 0x22, &mm_cc, 0x41 }, - { "mmss_camss_csi0_ahb_clk", &gcc, 0x22, &mm_cc, 0x42 }, - { "mmss_camss_csiphy0_clk", &gcc, 0x22, &mm_cc, 0x43 }, - { "mmss_camss_csi0rdi_clk", &gcc, 0x22, &mm_cc, 0x44 }, - { "mmss_camss_csi0pix_clk", &gcc, 0x22, &mm_cc, 0x45 }, - { "mmss_camss_csi1_clk", &gcc, 0x22, &mm_cc, 0x46 }, - { "mmss_camss_csi1_ahb_clk", &gcc, 0x22, &mm_cc, 0x47 }, - { "mmss_camss_csi1rdi_clk", &gcc, 0x22, &mm_cc, 0x49 }, - { "mmss_camss_csi1pix_clk", &gcc, 0x22, &mm_cc, 0x4a }, - { "mmss_camss_csi2_clk", &gcc, 0x22, &mm_cc, 0x4b }, - { "mmss_camss_csi2_ahb_clk", &gcc, 0x22, &mm_cc, 0x4c }, - { "mmss_camss_csi2rdi_clk", &gcc, 0x22, &mm_cc, 0x4e }, - { "mmss_camss_csi2pix_clk", &gcc, 0x22, &mm_cc, 0x4f }, - { "mmss_camss_csi3_clk", &gcc, 0x22, &mm_cc, 0x50 }, - { "mmss_camss_csi3_ahb_clk", &gcc, 0x22, &mm_cc, 0x51 }, - { "mmss_camss_csi3rdi_clk", &gcc, 0x22, &mm_cc, 0x53 }, - { "mmss_camss_csi3pix_clk", &gcc, 0x22, &mm_cc, 0x54 }, - { "mmss_mnoc_maxi_clk", &gcc, 0x22, &mm_cc, 0x70 }, - { "mmss_camss_vfe0_stream_clk", &gcc, 0x22, &mm_cc, 0x71 }, - { "mmss_camss_vfe1_stream_clk", &gcc, 0x22, &mm_cc, 0x72 }, - { "mmss_camss_cpp_vbif_ahb_clk", &gcc, 0x22, &mm_cc, 0x73 }, - { "mmss_misc_cxo_clk", &gcc, 0x22, &mm_cc, 0x77 }, - { "mmss_camss_cpp_axi_clk", &gcc, 0x22, &mm_cc, 0x7a }, - { "mmss_camss_csiphy1_clk", &gcc, 0x22, &mm_cc, 0x85 }, - { "mmss_camss_vfe0_ahb_clk", &gcc, 0x22, &mm_cc, 0x86 }, - { "mmss_camss_vfe1_ahb_clk", &gcc, 0x22, &mm_cc, 0x87 }, - { "mmss_camss_csiphy2_clk", &gcc, 0x22, &mm_cc, 0x88 }, - { "mmss_fd_core_clk", &gcc, 0x22, &mm_cc, 0x89 }, - { "mmss_fd_core_uar_clk", &gcc, 0x22, &mm_cc, 0x8a }, - { "mmss_fd_ahb_clk", &gcc, 0x22, &mm_cc, 0x8c }, - { "mmss_camss_cphy_csid0_clk", &gcc, 0x22, &mm_cc, 0x8d }, - { "mmss_camss_cphy_csid1_clk", &gcc, 0x22, &mm_cc, 0x8e }, - { "mmss_camss_cphy_csid2_clk", &gcc, 0x22, &mm_cc, 0x8f }, - { "mmss_camss_cphy_csid3_clk", &gcc, 0x22, &mm_cc, 0x90 }, - { "mmss_mdss_dp_link_clk", &gcc, 0x22, &mm_cc, 0x98 }, - { "mmss_mdss_dp_link_intf_clk", &gcc, 0x22, &mm_cc, 0x99 }, - { "mmss_mdss_dp_crypto_clk", &gcc, 0x22, &mm_cc, 0x9a }, - { "mmss_mdss_dp_pixel_clk", &gcc, 0x22, &mm_cc, 0x9b }, - { "mmss_mdss_dp_aux_clk", &gcc, 0x22, &mm_cc, 0x9c }, - { "mmss_mdss_dp_gtc_clk", &gcc, 0x22, &mm_cc, 0x9d }, - { "mmss_mdss_byte0_intf_clk", &gcc, 0x22, &mm_cc, 0xad }, - { "mmss_mdss_byte1_intf_clk", &gcc, 0x22, &mm_cc, 0xae }, - - { "gpucc_rbcpr_clk", &gcc, 0x13d, &gpu_cc, 0x3 }, - { "gpucc_rbbmtimer_clk", &gcc, 0x13d, &gpu_cc, 0x5 }, - { "gpucc_gfx3d_isense_clk", &gcc, 0x13d, &gpu_cc, 0xa }, + // { "debug_cpu_clk", &gcc.mux, 0xc0 }, + + { "snoc_clk", &gcc.mux, 0x0 }, + { "cnoc_clk", &gcc.mux, 0xe }, + { "bimc_clk", &gcc.mux, 0x14e }, + { "gcc_mmss_sys_noc_axi_clk", &gcc.mux, 0x1f }, + { "gcc_mmss_noc_cfg_ahb_clk", &gcc.mux, 0x20 }, + { "gcc_usb30_master_clk", &gcc.mux, 0x3e }, + { "gcc_usb30_sleep_clk", &gcc.mux, 0x3f }, + { "gcc_usb30_mock_utmi_clk", &gcc.mux, 0x40 }, + { "gcc_usb3_phy_aux_clk", &gcc.mux, 0x41 }, + { "gcc_usb3_phy_pipe_clk", &gcc.mux, 0x42 }, + { "gcc_sdcc2_apps_clk", &gcc.mux, 0x46 }, + { "gcc_sdcc2_ahb_clk", &gcc.mux, 0x47 }, + { "gcc_sdcc4_apps_clk", &gcc.mux, 0x48 }, + { "gcc_sdcc4_ahb_clk", &gcc.mux, 0x49 }, + { "gcc_blsp1_ahb_clk", &gcc.mux, 0x4a }, + { "gcc_blsp1_qup1_spi_apps_clk", &gcc.mux, 0x4c }, + { "gcc_blsp1_qup1_i2c_apps_clk", &gcc.mux, 0x4d }, + { "gcc_blsp1_uart1_apps_clk", &gcc.mux, 0x4e }, + { "gcc_blsp1_qup2_spi_apps_clk", &gcc.mux, 0x50 }, + { "gcc_blsp1_qup2_i2c_apps_clk", &gcc.mux, 0x51 }, + { "gcc_blsp1_uart2_apps_clk", &gcc.mux, 0x52 }, + { "gcc_blsp1_qup3_spi_apps_clk", &gcc.mux, 0x54 }, + { "gcc_blsp1_qup3_i2c_apps_clk", &gcc.mux, 0x55 }, + { "gcc_blsp1_uart3_apps_clk", &gcc.mux, 0x56 }, + { "gcc_blsp1_qup4_spi_apps_clk", &gcc.mux, 0x58 }, + { "gcc_blsp1_qup4_i2c_apps_clk", &gcc.mux, 0x59 }, + { "gcc_blsp1_qup5_spi_apps_clk", &gcc.mux, 0x5a }, + { "gcc_blsp1_qup5_i2c_apps_clk", &gcc.mux, 0x5b }, + { "gcc_blsp1_qup6_spi_apps_clk", &gcc.mux, 0x5c }, + { "gcc_blsp1_qup6_i2c_apps_clk", &gcc.mux, 0x5d }, + { "gcc_blsp2_ahb_clk", &gcc.mux, 0x5e }, + { "gcc_blsp2_qup1_spi_apps_clk", &gcc.mux, 0x60 }, + { "gcc_blsp2_qup1_i2c_apps_clk", &gcc.mux, 0x61 }, + { "gcc_blsp2_uart1_apps_clk", &gcc.mux, 0x62 }, + { "gcc_blsp2_qup2_spi_apps_clk", &gcc.mux, 0x64 }, + { "gcc_blsp2_qup2_i2c_apps_clk", &gcc.mux, 0x65 }, + { "gcc_blsp2_uart2_apps_clk", &gcc.mux, 0x66 }, + { "gcc_blsp2_qup3_spi_apps_clk", &gcc.mux, 0x68 }, + { "gcc_blsp2_qup3_i2c_apps_clk", &gcc.mux, 0x69 }, + { "gcc_blsp2_uart3_apps_clk", &gcc.mux, 0x6a }, + { "gcc_blsp2_qup4_spi_apps_clk", &gcc.mux, 0x6c }, + { "gcc_blsp2_qup4_i2c_apps_clk", &gcc.mux, 0x6d }, + { "gcc_blsp2_qup5_spi_apps_clk", &gcc.mux, 0x6e }, + { "gcc_blsp2_qup5_i2c_apps_clk", &gcc.mux, 0x6f }, + { "gcc_blsp2_qup6_spi_apps_clk", &gcc.mux, 0x70 }, + { "gcc_blsp2_qup6_i2c_apps_clk", &gcc.mux, 0x71 }, + { "gcc_pdm_ahb_clk", &gcc.mux, 0x72 }, + { "gcc_pdm2_clk", &gcc.mux, 0x74}, + { "gcc_prng_ahb_clk", &gcc.mux, 0x75 }, + { "gcc_tsif_ahb_clk", &gcc.mux, 0x76 }, + { "gcc_tsif_ref_clk", &gcc.mux, 0x77 }, + { "gcc_boot_rom_ahb_clk", &gcc.mux, 0x7a }, + { "ce1_clk", &gcc.mux, 0x97 }, + { "gcc_ce1_axi_m_clk", &gcc.mux, 0x98 }, + { "gcc_ce1_ahb_m_clk", &gcc.mux, 0x99 }, + { "measure_only_bimc_hmss_axi_clk", &gcc.mux, 0xbb }, + { "gcc_bimc_gfx_clk", &gcc.mux, 0xac }, + { "gcc_hmss_rbcpr_clk", &gcc.mux, 0xbc }, + { "gcc_gp1_clk", &gcc.mux, 0xdf }, + { "gcc_gp2_clk", &gcc.mux, 0xe0 }, + { "gcc_gp3_clk", &gcc.mux, 0xe1 }, + { "gcc_pcie_0_slv_axi_clk", &gcc.mux, 0xe2 }, + { "gcc_pcie_0_mstr_axi_clk", &gcc.mux, 0xe3 }, + { "gcc_pcie_0_cfg_ahb_clk", &gcc.mux, 0xe4 }, + { "gcc_pcie_0_aux_clk", &gcc.mux, 0xe5 }, + { "gcc_pcie_0_pipe_clk", &gcc.mux, 0xe6 }, + { "gcc_pcie_phy_aux_clk", &gcc.mux, 0xe8 }, + { "gcc_ufs_axi_clk", &gcc.mux, 0xea }, + { "gcc_ufs_ahb_clk", &gcc.mux, 0xeb }, + { "gcc_ufs_tx_symbol_0_clk", &gcc.mux, 0xec }, + { "gcc_ufs_rx_symbol_0_clk", &gcc.mux, 0xed }, + { "gcc_ufs_rx_symbol_1_clk", &gcc.mux, 0x162 }, + { "gcc_ufs_unipro_core_clk", &gcc.mux, 0xf0 }, + { "gcc_ufs_ice_core_clk", &gcc.mux, 0xf1 }, + { "gcc_dcc_ahb_clk", &gcc.mux, 0x119 }, + { "ipa_clk", &gcc.mux, 0x11b }, + { "gcc_mss_cfg_ahb_clk", &gcc.mux, 0x11f }, + { "gcc_mss_q6_bimc_axi_clk", &gcc.mux, 0x124 }, + { "gcc_mss_mnoc_bimc_axi_clk", &gcc.mux, 0x120 }, + { "gcc_mss_snoc_axi_clk", &gcc.mux, 0x123 }, + { "gcc_gpu_cfg_ahb_clk", &gcc.mux, 0x13b }, + { "gcc_gpu_bimc_gfx_clk", &gcc.mux, 0x13f }, + { "gcc_qspi_ahb_clk", &gcc.mux, 0x156 }, + { "gcc_qspi_ref_clk", &gcc.mux, 0x157 }, + + { "mmss_mnoc_ahb_clk", &mm_cc, 0x1 }, + { "mmss_misc_ahb_clk", &mm_cc, 0x3 }, + { "mmss_vmem_maxi_clk", &mm_cc, 0x9 }, + { "mmss_vmem_ahb_clk", &mm_cc, 0xa }, + { "mmss_bimc_smmu_ahb_clk", &mm_cc, 0xc }, + { "mmss_bimc_smmu_axi_clk", &mm_cc, 0xd }, + { "mmss_video_core_clk", &mm_cc, 0xe }, + { "mmss_video_axi_clk", &mm_cc, 0xf }, + { "mmss_video_maxi_clk", &mm_cc, 0x10 }, + { "mmss_video_ahb_clk", &mm_cc, 0x11 }, + { "mmss_mdss_rot_clk", &mm_cc, 0x12 }, + { "mmss_snoc_dvm_axi_clk", &mm_cc, 0x13 }, + { "mmss_mdss_mdp_clk", &mm_cc, 0x14 }, + { "mmss_mdss_mdp_lut_clk", &mm_cc, 0x15 }, + { "mmss_mdss_pclk0_clk", &mm_cc, 0x16 }, + { "mmss_mdss_pclk1_clk", &mm_cc, 0x17 }, + { "mmss_mdss_extpclk_clk", &mm_cc, 0x18 }, + { "mmss_video_subcore0_clk", &mm_cc, 0x1a }, + { "mmss_video_subcore1_clk", &mm_cc, 0x1b }, + { "mmss_mdss_vsync_clk", &mm_cc, 0x1c }, + { "mmss_mdss_hdmi_clk", &mm_cc, 0x1d }, + { "mmss_mdss_byte0_clk", &mm_cc, 0x1e }, + { "mmss_mdss_byte1_clk", &mm_cc, 0x1f }, + { "mmss_mdss_esc0_clk", &mm_cc, 0x20 }, + { "mmss_mdss_esc1_clk", &mm_cc, 0x21 }, + { "mmss_mdss_ahb_clk", &mm_cc, 0x22 }, + { "mmss_mdss_hdmi_dp_ahb_clk", &mm_cc, 0x23 }, + { "mmss_mdss_axi_clk", &mm_cc, 0x24 }, + { "mmss_camss_top_ahb_clk", &mm_cc, 0x25 }, + { "mmss_camss_micro_ahb_clk", &mm_cc, 0x26 }, + { "mmss_camss_gp0_clk", &mm_cc, 0x27 }, + { "mmss_camss_gp1_clk", &mm_cc, 0x28 }, + { "mmss_camss_mclk0_clk", &mm_cc, 0x29 }, + { "mmss_camss_mclk1_clk", &mm_cc, 0x2a }, + { "mmss_camss_mclk2_clk", &mm_cc, 0x2b }, + { "mmss_camss_mclk3_clk", &mm_cc, 0x2c }, + { "mmss_camss_cci_clk", &mm_cc, 0x2d }, + { "mmss_camss_cci_ahb_clk", &mm_cc, 0x2e }, + { "mmss_camss_csi0phytimer_clk", &mm_cc, 0x2f }, + { "mmss_camss_csi1phytimer_clk", &mm_cc, 0x30 }, + { "mmss_camss_csi2phytimer_clk", &mm_cc, 0x31 }, + { "mmss_camss_jpeg0_clk", &mm_cc, 0x32 }, + { "mmss_camss_ispif_ahb_clk", &mm_cc, 0x33 }, + { "mmss_camss_jpeg_ahb_clk", &mm_cc, 0x35 }, + { "mmss_camss_jpeg_axi_clk", &mm_cc, 0x36 }, + { "mmss_camss_ahb_clk", &mm_cc, 0x37 }, + { "mmss_camss_vfe0_clk", &mm_cc, 0x38 }, + { "mmss_camss_vfe1_clk", &mm_cc, 0x39 }, + { "mmss_camss_cpp_clk", &mm_cc, 0x3a }, + { "mmss_camss_cpp_ahb_clk", &mm_cc, 0x3b }, + { "mmss_camss_csi_vfe0_clk", &mm_cc, 0x3f }, + { "mmss_camss_csi_vfe1_clk", &mm_cc, 0x40 }, + { "mmss_camss_csi0_clk", &mm_cc, 0x41 }, + { "mmss_camss_csi0_ahb_clk", &mm_cc, 0x42 }, + { "mmss_camss_csiphy0_clk", &mm_cc, 0x43 }, + { "mmss_camss_csi0rdi_clk", &mm_cc, 0x44 }, + { "mmss_camss_csi0pix_clk", &mm_cc, 0x45 }, + { "mmss_camss_csi1_clk", &mm_cc, 0x46 }, + { "mmss_camss_csi1_ahb_clk", &mm_cc, 0x47 }, + { "mmss_camss_csi1rdi_clk", &mm_cc, 0x49 }, + { "mmss_camss_csi1pix_clk", &mm_cc, 0x4a }, + { "mmss_camss_csi2_clk", &mm_cc, 0x4b }, + { "mmss_camss_csi2_ahb_clk", &mm_cc, 0x4c }, + { "mmss_camss_csi2rdi_clk", &mm_cc, 0x4e }, + { "mmss_camss_csi2pix_clk", &mm_cc, 0x4f }, + { "mmss_camss_csi3_clk", &mm_cc, 0x50 }, + { "mmss_camss_csi3_ahb_clk", &mm_cc, 0x51 }, + { "mmss_camss_csi3rdi_clk", &mm_cc, 0x53 }, + { "mmss_camss_csi3pix_clk", &mm_cc, 0x54 }, + { "mmss_mnoc_maxi_clk", &mm_cc, 0x70 }, + { "mmss_camss_vfe0_stream_clk", &mm_cc, 0x71 }, + { "mmss_camss_vfe1_stream_clk", &mm_cc, 0x72 }, + { "mmss_camss_cpp_vbif_ahb_clk", &mm_cc, 0x73 }, + { "mmss_misc_cxo_clk", &mm_cc, 0x77 }, + { "mmss_camss_cpp_axi_clk", &mm_cc, 0x7a }, + { "mmss_camss_csiphy1_clk", &mm_cc, 0x85 }, + { "mmss_camss_vfe0_ahb_clk", &mm_cc, 0x86 }, + { "mmss_camss_vfe1_ahb_clk", &mm_cc, 0x87 }, + { "mmss_camss_csiphy2_clk", &mm_cc, 0x88 }, + { "mmss_fd_core_clk", &mm_cc, 0x89 }, + { "mmss_fd_core_uar_clk", &mm_cc, 0x8a }, + { "mmss_fd_ahb_clk", &mm_cc, 0x8c }, + { "mmss_camss_cphy_csid0_clk", &mm_cc, 0x8d }, + { "mmss_camss_cphy_csid1_clk", &mm_cc, 0x8e }, + { "mmss_camss_cphy_csid2_clk", &mm_cc, 0x8f }, + { "mmss_camss_cphy_csid3_clk", &mm_cc, 0x90 }, + { "mmss_mdss_dp_link_clk", &mm_cc, 0x98 }, + { "mmss_mdss_dp_link_intf_clk", &mm_cc, 0x99 }, + { "mmss_mdss_dp_crypto_clk", &mm_cc, 0x9a }, + { "mmss_mdss_dp_pixel_clk", &mm_cc, 0x9b }, + { "mmss_mdss_dp_aux_clk", &mm_cc, 0x9c }, + { "mmss_mdss_dp_gtc_clk", &mm_cc, 0x9d }, + { "mmss_mdss_byte0_intf_clk", &mm_cc, 0xad }, + { "mmss_mdss_byte1_intf_clk", &mm_cc, 0xae }, + + { "gpucc_rbcpr_clk", &gpu_cc, 0x3 }, + { "gpucc_rbbmtimer_clk", &gpu_cc, 0x5 }, + { "gpucc_gfx3d_isense_clk", &gpu_cc, 0xa }, {} }; diff --git a/qcs404.c b/qcs404.c index 553ee05..6845d98 100644 --- a/qcs404.c +++ b/qcs404.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include @@ -49,147 +50,190 @@ #define GCC_CLOCK_FREQ_MEASURE_STATUS 0x74008 #define GCC_XO_DIV4_CBCR 0x30034 -static struct debug_mux gcc; +struct turing_mux { + struct debug_mux mux; -static struct debug_mux gcc = { - .phys = GCC_BASE, - .size = GCC_SIZE, + unsigned int ahb_reg; + unsigned int ahb_mask; +}; + +unsigned long measure_turing(const struct measure_clk *clk, + const struct debug_mux *mux); + +static struct gcc_mux gcc = { + .mux = { + .phys = GCC_BASE, + .size = GCC_SIZE, - .enable_reg = GCC_DEBUG_CLK_CTL, - .enable_mask = BIT(16), + .measure = measure_gcc, - .mux_reg = GCC_DEBUG_CLK_CTL, - .mux_mask = 0x1ff, + .enable_reg = GCC_DEBUG_CLK_CTL, + .enable_mask = BIT(16), - .div_reg = GCC_DEBUG_CLK_CTL, - .div_shift = 12, - .div_mask = 0xf << 12, - .div_val = 4, + .mux_reg = GCC_DEBUG_CLK_CTL, + .mux_mask = 0x1ff, + + .div_reg = GCC_DEBUG_CLK_CTL, + .div_shift = 12, + .div_mask = 0xf << 12, + .div_val = 4, + }, .xo_div4_reg = GCC_XO_DIV4_CBCR, .debug_ctl_reg = GCC_CLOCK_FREQ_MEASURE_CTL, .debug_status_reg = GCC_CLOCK_FREQ_MEASURE_STATUS, }; -static struct debug_mux turing = { - .phys = 0x800000, - .size = 0x30000, +static struct turing_mux turing = { + .mux = { + .phys = 0x800000, + .size = 0x30000, - .enable_reg = 0x22008, - .enable_mask = BIT(0), + .measure = measure_turing, + .parent = &gcc.mux, + .parent_mux_val = 50, - .mux_reg = 0x22000, - .mux_mask = 0xffff, + .enable_reg = 0x22008, + .enable_mask = BIT(0), - .div_mask = 0, + .mux_reg = 0x22000, + .mux_mask = 0xffff, + }, .ahb_reg = 0x5e004, .ahb_mask = BIT(31), }; +static bool leaf_enabled(struct turing_mux *leaf) +{ + uint32_t val; + + /* If no AHB clock is specified, we assume it's clocked */ + if (!leaf || !leaf->ahb_mask) + return true; + + /* we know that the parent is GCC, we read AHB reg from GCC */ + val = readl(leaf->mux.parent->base + leaf->ahb_reg); + val &= leaf->ahb_mask; + + /* CLK_OFF will be set if block is not clocked, so inverse */ + return !val; +} + +unsigned long measure_turing(const struct measure_clk *clk, + const struct debug_mux *mux) +{ + struct turing_mux *turing = container_of(mux, struct turing_mux, mux); + + if (!leaf_enabled(turing)) + return 0; + + return measure_leaf(clk, mux); +} + static struct measure_clk qcs404_clocks[] = { - { "snoc_clk", &gcc, 0 }, - { "gcc_sys_noc_usb3_clk", &gcc, 1 }, - { "pnoc_clk", &gcc, 8 }, - { "gcc_pcnoc_usb2_clk", &gcc, 9 }, - { "gcc_pcnoc_usb3_clk", &gcc, 10 }, - { "gcc_gp1_clk", &gcc, 16 }, - { "gcc_gp2_clk", &gcc, 17 }, - { "gcc_gp3_clk", &gcc, 18 }, - { "gcc_bimc_gfx_clk", &gcc, 45 }, - { "aon_clk_src", &gcc, 50, &turing, 1}, - { "turing_wrapper_aon_clk", &gcc, 50, &turing, 2}, - { "turing_wrapper_cnoc_sway_aon_clk", &gcc, 50, &turing, 3}, - { "turing_wrapper_qos_ahbs_aon_clk", &gcc, 50, &turing, 4}, - { "q6ss_ahbm_aon_clk", &gcc, 50, &turing, 5}, - { "q6ss_ahbs_aon_clk", &gcc, 50, &turing, 6}, - { "turing_wrapper_bus_timeout_aon_clk", &gcc, 50, &turing, 7}, - { "turing_wrapper_rscc_aon_clk", &gcc, 50, &turing, 8}, - { "q6ss_alt_reset_aon_clk", &gcc, 50, &turing, 10}, - { "qos_fixed_lat_counter_clk_src", &gcc, 50, &turing, 11}, - { "turing_wrapper_qos_dmonitor_fixed_lat_counter_clk", &gcc, 50, &turing, 12}, - { "turing_wrapper_qos_danger_fixed_lat_counter_clk", &gcc, 50, &turing, 13}, - { "q6_xo_clk_src", &gcc, 50, &turing, 14}, - { "qos_xo_clk_src", &gcc, 50, &turing, 15}, - { "turing_wrapper_qos_xo_lat_counter_clk", &gcc, 50, &turing, 16}, - { "bcr_slp_clk_src", &gcc, 50, &turing, 19}, - { "q6ss_bcr_slp_clk", &gcc, 50, &turing, 20}, - { "turing_wrapper_cnoc_ahbs_clk", &gcc, 50, &turing, 28}, - { "q6ss_q6_axim_clk", &gcc, 50, &turing, 29}, - { "q6ss_sleep_clk_src", &gcc, 50, &turing, 33}, - { "qdsp6ss_xo_clk", &gcc, 50, &turing, 36}, - { "qdsp6ss_sleep_clk", &gcc, 50, &turing, 37}, - { "q6ss_dbg_in_clk", &gcc, 50, &turing, 39}, - { "gcc_usb_hs_system_clk", &gcc, 96 }, - { "gcc_usb_hs_inactivity_timers_clk", &gcc, 98 }, - { "gcc_usb2a_phy_sleep_clk", &gcc, 99 }, - { "gcc_usb_hs_phy_cfg_ahb_clk", &gcc, 100 }, - { "gcc_usb20_mock_utmi_clk", &gcc, 101 }, - { "gcc_sdcc1_apps_clk", &gcc, 104 }, - { "gcc_sdcc1_ahb_clk", &gcc, 105 }, - { "gcc_sdcc1_ice_core_clk", &gcc, 106 }, - { "gcc_sdcc2_apps_clk", &gcc, 112 }, - { "gcc_sdcc2_ahb_clk", &gcc, 113 }, - { "gcc_usb30_master_clk", &gcc, 120 }, - { "gcc_usb30_sleep_clk", &gcc, 121 }, - { "gcc_usb30_mock_utmi_clk", &gcc, 122 }, - { "gcc_usb3_phy_pipe_clk", &gcc, 123 }, - { "gcc_usb3_phy_aux_clk", &gcc, 124 }, - { "gcc_eth_axi_clk", &gcc, 128 }, - { "gcc_eth_rgmii_clk", &gcc, 129 }, - { "gcc_eth_slave_ahb_clk", &gcc, 130 }, - { "gcc_eth_ptp_clk", &gcc, 131 }, - { "gcc_blsp1_ahb_clk", &gcc, 136 }, - { "gcc_blsp1_qup1_spi_apps_clk", &gcc, 138 }, - { "wcnss_m_clk", &gcc, 138 }, - { "gcc_blsp1_qup1_i2c_apps_clk", &gcc, 139 }, - { "gcc_blsp1_uart1_apps_clk", &gcc, 140 }, - { "gcc_blsp1_qup2_spi_apps_clk", &gcc, 142 }, - { "gcc_blsp1_qup2_i2c_apps_clk", &gcc, 143 }, - { "gcc_blsp1_uart2_apps_clk", &gcc, 144 }, - { "gcc_blsp1_qup3_spi_apps_clk", &gcc, 146 }, - { "gcc_blsp1_qup3_i2c_apps_clk", &gcc, 147 }, - { "gcc_blsp1_qup4_spi_apps_clk", &gcc, 148 }, - { "gcc_blsp1_qup4_i2c_apps_clk", &gcc, 149 }, - { "gcc_blsp1_uart3_apps_clk", &gcc, 150 }, - { "gcc_blsp1_qup0_spi_apps_clk", &gcc, 152 }, - { "gcc_blsp1_qup0_i2c_apps_clk", &gcc, 153 }, - { "gcc_blsp1_uart0_apps_clk", &gcc, 154 }, - { "gcc_blsp2_ahb_clk", &gcc, 160 }, - { "gcc_blsp2_qup0_i2c_apps_clk", &gcc, 162 }, - { "gcc_blsp2_qup0_spi_apps_clk", &gcc, 163 }, - { "gcc_blsp2_uart0_apps_clk", &gcc, 164 }, - { "gcc_pcie_0_slv_axi_clk", &gcc, 168 }, - { "gcc_pcie_0_mstr_axi_clk", &gcc, 169 }, - { "gcc_pcie_0_cfg_ahb_clk", &gcc, 170 }, - { "gcc_pcie_0_aux_clk", &gcc, 171 }, - { "gcc_pcie_0_pipe_clk", &gcc, 172 }, - //{ "pcie0_pipe_clk", &gcc, 173, 1 }, - { "qpic_clk", &gcc, 192 }, - { "gcc_pdm_ahb_clk", &gcc, 208 }, - { "gcc_pdm2_clk", &gcc, 210 }, - { "gcc_pwm0_xo512_clk", &gcc, 211 }, - { "gcc_pwm1_xo512_clk", &gcc, 212 }, - { "gcc_pwm2_xo512_clk", &gcc, 213 }, - { "gcc_prng_ahb_clk", &gcc, 216 }, - { "gcc_geni_ir_s_clk", &gcc, 238 }, - { "gcc_boot_rom_ahb_clk", &gcc, 248 }, - { "ce1_clk", &gcc, 312 }, - { "bimc_clk", &gcc, 346 }, - //{ "bimc_fsm_ddr_clk", &gcc, 350, 1 }, - { "gcc_apss_ahb_clk", &gcc, 360 }, - { "gcc_dcc_clk", &gcc, 441 }, - { "gcc_oxili_gfx3d_clk", &gcc, 490 }, - { "gcc_oxili_ahb_clk", &gcc, 491 }, - { "gcc_mdss_hdmi_pclk_clk", &gcc, 497 }, - { "gcc_mdss_hdmi_app_clk", &gcc, 498 }, - { "gcc_mdss_ahb_clk", &gcc, 502 }, - { "gcc_mdss_axi_clk", &gcc, 503 }, - { "gcc_mdss_pclk0_clk", &gcc, 504 }, - { "gcc_mdss_mdp_clk", &gcc, 505 }, - { "gcc_mdss_vsync_clk", &gcc, 507 }, - { "gcc_mdss_byte0_clk", &gcc, 508 }, - { "gcc_mdss_esc0_clk", &gcc, 509 }, + { "snoc_clk", &gcc.mux, 0 }, + { "gcc_sys_noc_usb3_clk", &gcc.mux, 1 }, + { "pnoc_clk", &gcc.mux, 8 }, + { "gcc_pcnoc_usb2_clk", &gcc.mux, 9 }, + { "gcc_pcnoc_usb3_clk", &gcc.mux, 10 }, + { "gcc_gp1_clk", &gcc.mux, 16 }, + { "gcc_gp2_clk", &gcc.mux, 17 }, + { "gcc_gp3_clk", &gcc.mux, 18 }, + { "gcc_bimc_gfx_clk", &gcc.mux, 45 }, + { "aon_clk_src", &turing.mux, 1}, + { "turing_wrapper_aon_clk", &turing.mux, 2}, + { "turing_wrapper_cnoc_sway_aon_clk", &turing.mux, 3}, + { "turing_wrapper_qos_ahbs_aon_clk", &turing.mux, 4}, + { "q6ss_ahbm_aon_clk", &turing.mux, 5}, + { "q6ss_ahbs_aon_clk", &turing.mux, 6}, + { "turing_wrapper_bus_timeout_aon_clk", &turing.mux, 7}, + { "turing_wrapper_rscc_aon_clk", &turing.mux, 8}, + { "q6ss_alt_reset_aon_clk", &turing.mux, 10}, + { "qos_fixed_lat_counter_clk_src", &turing.mux, 11}, + { "turing_wrapper_qos_dmonitor_fixed_lat_counter_clk", &turing.mux, 12}, + { "turing_wrapper_qos_danger_fixed_lat_counter_clk", &turing.mux, 13}, + { "q6_xo_clk_src", &turing.mux, 14}, + { "qos_xo_clk_src", &turing.mux, 15}, + { "turing_wrapper_qos_xo_lat_counter_clk", &turing.mux, 16}, + { "bcr_slp_clk_src", &turing.mux, 19}, + { "q6ss_bcr_slp_clk", &turing.mux, 20}, + { "turing_wrapper_cnoc_ahbs_clk", &turing.mux, 28}, + { "q6ss_q6_axim_clk", &turing.mux, 29}, + { "q6ss_sleep_clk_src", &turing.mux, 33}, + { "qdsp6ss_xo_clk", &turing.mux, 36}, + { "qdsp6ss_sleep_clk", &turing.mux, 37}, + { "q6ss_dbg_in_clk", &turing.mux, 39}, + { "gcc_usb_hs_system_clk", &gcc.mux, 96 }, + { "gcc_usb_hs_inactivity_timers_clk", &gcc.mux, 98 }, + { "gcc_usb2a_phy_sleep_clk", &gcc.mux, 99 }, + { "gcc_usb_hs_phy_cfg_ahb_clk", &gcc.mux, 100 }, + { "gcc_usb20_mock_utmi_clk", &gcc.mux, 101 }, + { "gcc_sdcc1_apps_clk", &gcc.mux, 104 }, + { "gcc_sdcc1_ahb_clk", &gcc.mux, 105 }, + { "gcc_sdcc1_ice_core_clk", &gcc.mux, 106 }, + { "gcc_sdcc2_apps_clk", &gcc.mux, 112 }, + { "gcc_sdcc2_ahb_clk", &gcc.mux, 113 }, + { "gcc_usb30_master_clk", &gcc.mux, 120 }, + { "gcc_usb30_sleep_clk", &gcc.mux, 121 }, + { "gcc_usb30_mock_utmi_clk", &gcc.mux, 122 }, + { "gcc_usb3_phy_pipe_clk", &gcc.mux, 123 }, + { "gcc_usb3_phy_aux_clk", &gcc.mux, 124 }, + { "gcc_eth_axi_clk", &gcc.mux, 128 }, + { "gcc_eth_rgmii_clk", &gcc.mux, 129 }, + { "gcc_eth_slave_ahb_clk", &gcc.mux, 130 }, + { "gcc_eth_ptp_clk", &gcc.mux, 131 }, + { "gcc_blsp1_ahb_clk", &gcc.mux, 136 }, + { "gcc_blsp1_qup1_spi_apps_clk", &gcc.mux, 138 }, + { "wcnss_m_clk", &gcc.mux, 138 }, + { "gcc_blsp1_qup1_i2c_apps_clk", &gcc.mux, 139 }, + { "gcc_blsp1_uart1_apps_clk", &gcc.mux, 140 }, + { "gcc_blsp1_qup2_spi_apps_clk", &gcc.mux, 142 }, + { "gcc_blsp1_qup2_i2c_apps_clk", &gcc.mux, 143 }, + { "gcc_blsp1_uart2_apps_clk", &gcc.mux, 144 }, + { "gcc_blsp1_qup3_spi_apps_clk", &gcc.mux, 146 }, + { "gcc_blsp1_qup3_i2c_apps_clk", &gcc.mux, 147 }, + { "gcc_blsp1_qup4_spi_apps_clk", &gcc.mux, 148 }, + { "gcc_blsp1_qup4_i2c_apps_clk", &gcc.mux, 149 }, + { "gcc_blsp1_uart3_apps_clk", &gcc.mux, 150 }, + { "gcc_blsp1_qup0_spi_apps_clk", &gcc.mux, 152 }, + { "gcc_blsp1_qup0_i2c_apps_clk", &gcc.mux, 153 }, + { "gcc_blsp1_uart0_apps_clk", &gcc.mux, 154 }, + { "gcc_blsp2_ahb_clk", &gcc.mux, 160 }, + { "gcc_blsp2_qup0_i2c_apps_clk", &gcc.mux, 162 }, + { "gcc_blsp2_qup0_spi_apps_clk", &gcc.mux, 163 }, + { "gcc_blsp2_uart0_apps_clk", &gcc.mux, 164 }, + { "gcc_pcie_0_slv_axi_clk", &gcc.mux, 168 }, + { "gcc_pcie_0_mstr_axi_clk", &gcc.mux, 169 }, + { "gcc_pcie_0_cfg_ahb_clk", &gcc.mux, 170 }, + { "gcc_pcie_0_aux_clk", &gcc.mux, 171 }, + { "gcc_pcie_0_pipe_clk", &gcc.mux, 172 }, + //{ "pcie0_pipe_clk", &gcc.mux, 173, 1 }, + { "qpic_clk", &gcc.mux, 192 }, + { "gcc_pdm_ahb_clk", &gcc.mux, 208 }, + { "gcc_pdm2_clk", &gcc.mux, 210 }, + { "gcc_pwm0_xo512_clk", &gcc.mux, 211 }, + { "gcc_pwm1_xo512_clk", &gcc.mux, 212 }, + { "gcc_pwm2_xo512_clk", &gcc.mux, 213 }, + { "gcc_prng_ahb_clk", &gcc.mux, 216 }, + { "gcc_geni_ir_s_clk", &gcc.mux, 238 }, + { "gcc_boot_rom_ahb_clk", &gcc.mux, 248 }, + { "ce1_clk", &gcc.mux, 312 }, + { "bimc_clk", &gcc.mux, 346 }, + //{ "bimc_fsm_ddr_clk", &gcc.mux, 350, 1 }, + { "gcc_apss_ahb_clk", &gcc.mux, 360 }, + { "gcc_dcc_clk", &gcc.mux, 441 }, + { "gcc_oxili_gfx3d_clk", &gcc.mux, 490 }, + { "gcc_oxili_ahb_clk", &gcc.mux, 491 }, + { "gcc_mdss_hdmi_pclk_clk", &gcc.mux, 497 }, + { "gcc_mdss_hdmi_app_clk", &gcc.mux, 498 }, + { "gcc_mdss_ahb_clk", &gcc.mux, 502 }, + { "gcc_mdss_axi_clk", &gcc.mux, 503 }, + { "gcc_mdss_pclk0_clk", &gcc.mux, 504 }, + { "gcc_mdss_mdp_clk", &gcc.mux, 505 }, + { "gcc_mdss_vsync_clk", &gcc.mux, 507 }, + { "gcc_mdss_byte0_clk", &gcc.mux, 508 }, + { "gcc_mdss_esc0_clk", &gcc.mux, 509 }, {} }; diff --git a/sc8280xp.c b/sc8280xp.c index 482d6e4..9c010b9 100644 --- a/sc8280xp.c +++ b/sc8280xp.c @@ -39,19 +39,23 @@ #include "debugcc.h" -static struct debug_mux gcc = { - .phys = 0x00100000, - .size = 0x1f0000, +static struct gcc_mux gcc = { + .mux = { + .phys = 0x00100000, + .size = 0x1f0000, - .enable_reg = 0x62004, - .enable_mask = BIT(0), + .measure = measure_gcc, - .mux_reg = 0x62024, - .mux_mask = 0x1fff, + .enable_reg = 0x62004, + .enable_mask = BIT(0), - .div_reg = 0x62000, - .div_mask = 0xf, - .div_val = 2, + .mux_reg = 0x62024, + .mux_mask = 0x1fff, + + .div_reg = 0x62000, + .div_mask = 0xf, + .div_val = 2, + }, .xo_div4_reg = 0x62008, .debug_ctl_reg = 0x62038, @@ -63,6 +67,10 @@ static struct debug_mux disp0_cc = { .size = 0x20000, .block_name = "disp0", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x79, + .enable_reg = 0x500c, .enable_mask = BIT(0), @@ -79,6 +87,10 @@ static struct debug_mux disp1_cc = { .size = 0x20000, .block_name = "disp1", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x82, + .enable_reg = 0x500c, .enable_mask = BIT(0), @@ -99,334 +111,334 @@ static struct debug_mux mc_cc = { }; static struct measure_clk sc8280xp_clocks[] = { - { "gcc_aggre_noc_pcie0_tunnel_axi_clk", &gcc, 0x217 }, - { "gcc_aggre_noc_pcie1_tunnel_axi_clk", &gcc, 0x218 }, - { "gcc_aggre_noc_pcie_4_axi_clk", &gcc, 0x214 }, - { "gcc_aggre_noc_pcie_south_sf_axi_clk", &gcc, 0x215 }, - { "gcc_aggre_ufs_card_axi_clk", &gcc, 0x222 }, - { "gcc_aggre_ufs_phy_axi_clk", &gcc, 0x221 }, - { "gcc_aggre_usb3_mp_axi_clk", &gcc, 0x21b }, - { "gcc_aggre_usb3_prim_axi_clk", &gcc, 0x219 }, - { "gcc_aggre_usb3_sec_axi_clk", &gcc, 0x21a }, - { "gcc_aggre_usb4_1_axi_clk", &gcc, 0x21d }, - { "gcc_aggre_usb4_axi_clk", &gcc, 0x21c }, - { "gcc_aggre_usb_noc_axi_clk", &gcc, 0x220 }, - { "gcc_aggre_usb_noc_north_axi_clk", &gcc, 0x21f }, - { "gcc_aggre_usb_noc_south_axi_clk", &gcc, 0x21e }, - { "gcc_ahb2phy0_clk", &gcc, 0xfe }, - { "gcc_ahb2phy2_clk", &gcc, 0xff }, - { "gcc_camera_hf_axi_clk", &gcc, 0x6a }, - { "gcc_camera_sf_axi_clk", &gcc, 0x6b }, - { "gcc_camera_throttle_nrt_axi_clk", &gcc, 0x6d }, - { "gcc_camera_throttle_rt_axi_clk", &gcc, 0x6c }, - { "gcc_camera_throttle_xo_clk", &gcc, 0x6f }, - { "gcc_cfg_noc_usb3_mp_axi_clk", &gcc, 0x2c }, - { "gcc_cfg_noc_usb3_prim_axi_clk", &gcc, 0x2a }, - { "gcc_cfg_noc_usb3_sec_axi_clk", &gcc, 0x2b }, - { "gcc_cnoc_pcie0_tunnel_clk", &gcc, 0x1c }, - { "gcc_cnoc_pcie1_tunnel_clk", &gcc, 0x1d }, - { "gcc_cnoc_pcie4_qx_clk", &gcc, 0x18 }, - { "gcc_ddrss_gpu_axi_clk", &gcc, 0x155 }, - { "gcc_ddrss_pcie_sf_tbu_clk", &gcc, 0x156 }, - { "gcc_disp1_hf_axi_clk", &gcc, 0x7d }, - { "gcc_disp1_sf_axi_clk", &gcc, 0x7e }, - { "gcc_disp1_throttle_nrt_axi_clk", &gcc, 0x80 }, - { "gcc_disp1_throttle_rt_axi_clk", &gcc, 0x7f }, - { "gcc_disp_hf_axi_clk", &gcc, 0x74 }, - { "gcc_disp_sf_axi_clk", &gcc, 0x75 }, - { "gcc_disp_throttle_nrt_axi_clk", &gcc, 0x77 }, - { "gcc_disp_throttle_rt_axi_clk", &gcc, 0x76 }, - { "gcc_emac0_axi_clk", &gcc, 0x246 }, - { "gcc_emac0_ptp_clk", &gcc, 0x248 }, - { "gcc_emac0_rgmii_clk", &gcc, 0x249 }, - { "gcc_emac0_slv_ahb_clk", &gcc, 0x247 }, - { "gcc_emac1_axi_clk", &gcc, 0x24a }, - { "gcc_emac1_ptp_clk", &gcc, 0x24c }, - { "gcc_emac1_rgmii_clk", &gcc, 0x24d }, - { "gcc_emac1_slv_ahb_clk", &gcc, 0x24b }, - { "gcc_gp1_clk", &gcc, 0x18c }, - { "gcc_gp2_clk", &gcc, 0x18d }, - { "gcc_gp3_clk", &gcc, 0x18e }, - { "gcc_gp4_clk", &gcc, 0x290 }, - { "gcc_gp5_clk", &gcc, 0x291 }, - { "gcc_gpu_gpll0_clk_src", &gcc, 0x232 }, - { "gcc_gpu_gpll0_div_clk_src", &gcc, 0x233 }, - { "gcc_gpu_memnoc_gfx_clk", &gcc, 0x22e }, - { "gcc_gpu_snoc_dvm_gfx_clk", &gcc, 0x231 }, - { "gcc_gpu_tcu_throttle_ahb_clk", &gcc, 0x22b }, - { "gcc_gpu_tcu_throttle_clk", &gcc, 0x22f }, - { "gcc_pcie0_phy_rchng_clk", &gcc, 0x1d0 }, - { "gcc_pcie1_phy_rchng_clk", &gcc, 0x19f }, - { "gcc_pcie2a_phy_rchng_clk", &gcc, 0x1a9 }, - { "gcc_pcie2b_phy_rchng_clk", &gcc, 0x1b3 }, - { "gcc_pcie3a_phy_rchng_clk", &gcc, 0x1bd }, - { "gcc_pcie3b_phy_rchng_clk", &gcc, 0x1c7 }, - { "gcc_pcie4_phy_rchng_clk", &gcc, 0x196 }, - { "gcc_pcie_0_aux_clk", &gcc, 0x1ce }, - { "gcc_pcie_0_cfg_ahb_clk", &gcc, 0x1cd }, - { "gcc_pcie_0_mstr_axi_clk", &gcc, 0x1cc }, - { "gcc_pcie_0_pipe_clk", &gcc, 0x1cf }, - { "gcc_pcie_0_slv_axi_clk", &gcc, 0x1cb }, - { "gcc_pcie_0_slv_q2a_axi_clk", &gcc, 0x1ca }, - { "gcc_pcie_1_aux_clk", &gcc, 0x19d }, - { "gcc_pcie_1_cfg_ahb_clk", &gcc, 0x19c }, - { "gcc_pcie_1_mstr_axi_clk", &gcc, 0x19b }, - { "gcc_pcie_1_pipe_clk", &gcc, 0x19e }, - { "gcc_pcie_1_slv_axi_clk", &gcc, 0x19a }, - { "gcc_pcie_1_slv_q2a_axi_clk", &gcc, 0x199 }, - { "gcc_pcie_2a_aux_clk", &gcc, 0x1a6 }, - { "gcc_pcie_2a_cfg_ahb_clk", &gcc, 0x1a5 }, - { "gcc_pcie_2a_mstr_axi_clk", &gcc, 0x1a4 }, - { "gcc_pcie_2a_pipe_clk", &gcc, 0x1a7 }, - { "gcc_pcie_2a_pipediv2_clk", &gcc, 0x1a8 }, - { "gcc_pcie_2a_slv_axi_clk", &gcc, 0x1a3 }, - { "gcc_pcie_2a_slv_q2a_axi_clk", &gcc, 0x1a2 }, - { "gcc_pcie_2b_aux_clk", &gcc, 0x1b0 }, - { "gcc_pcie_2b_cfg_ahb_clk", &gcc, 0x1af }, - { "gcc_pcie_2b_mstr_axi_clk", &gcc, 0x1ae }, - { "gcc_pcie_2b_pipe_clk", &gcc, 0x1b1 }, - { "gcc_pcie_2b_pipediv2_clk", &gcc, 0x1b2 }, - { "gcc_pcie_2b_slv_axi_clk", &gcc, 0x1ad }, - { "gcc_pcie_2b_slv_q2a_axi_clk", &gcc, 0x1ac }, - { "gcc_pcie_3a_aux_clk", &gcc, 0x1ba }, - { "gcc_pcie_3a_cfg_ahb_clk", &gcc, 0x1b9 }, - { "gcc_pcie_3a_mstr_axi_clk", &gcc, 0x1b8 }, - { "gcc_pcie_3a_pipe_clk", &gcc, 0x1bb }, - { "gcc_pcie_3a_pipediv2_clk", &gcc, 0x1bc }, - { "gcc_pcie_3a_slv_axi_clk", &gcc, 0x1b7 }, - { "gcc_pcie_3a_slv_q2a_axi_clk", &gcc, 0x1b6 }, - { "gcc_pcie_3b_aux_clk", &gcc, 0x1c4 }, - { "gcc_pcie_3b_cfg_ahb_clk", &gcc, 0x1c3 }, - { "gcc_pcie_3b_mstr_axi_clk", &gcc, 0x1c2 }, - { "gcc_pcie_3b_pipe_clk", &gcc, 0x1c5 }, - { "gcc_pcie_3b_pipediv2_clk", &gcc, 0x1c6 }, - { "gcc_pcie_3b_slv_axi_clk", &gcc, 0x1c1 }, - { "gcc_pcie_3b_slv_q2a_axi_clk", &gcc, 0x1c0 }, - { "gcc_pcie_4_aux_clk", &gcc, 0x193 }, - { "gcc_pcie_4_cfg_ahb_clk", &gcc, 0x192 }, - { "gcc_pcie_4_mstr_axi_clk", &gcc, 0x191 }, - { "gcc_pcie_4_pipe_clk", &gcc, 0x194 }, - { "gcc_pcie_4_pipediv2_clk", &gcc, 0x195 }, - { "gcc_pcie_4_slv_axi_clk", &gcc, 0x190 }, - { "gcc_pcie_4_slv_q2a_axi_clk", &gcc, 0x18f }, - { "gcc_pcie_rscc_ahb_clk", &gcc, 0x8f }, - { "gcc_pcie_rscc_xo_clk", &gcc, 0x8e }, - { "gcc_pcie_throttle_cfg_clk", &gcc, 0x46 }, - { "gcc_pdm2_clk", &gcc, 0x122 }, - { "gcc_pdm_ahb_clk", &gcc, 0x120 }, - { "gcc_pdm_xo4_clk", &gcc, 0x121 }, - { "gcc_qmip_camera_nrt_ahb_clk", &gcc, 0x68 }, - { "gcc_qmip_camera_rt_ahb_clk", &gcc, 0x69 }, - { "gcc_qmip_disp1_ahb_clk", &gcc, 0x7b }, - { "gcc_qmip_disp1_rot_ahb_clk", &gcc, 0x7c }, - { "gcc_qmip_disp_ahb_clk", &gcc, 0x72 }, - { "gcc_qmip_disp_rot_ahb_clk", &gcc, 0x73 }, - { "gcc_qmip_video_cvp_ahb_clk", &gcc, 0x86 }, - { "gcc_qmip_video_vcodec_ahb_clk", &gcc, 0x87 }, - { "gcc_qupv3_wrap0_core_2x_clk", &gcc, 0x109 }, - { "gcc_qupv3_wrap0_core_clk", &gcc, 0x108 }, - { "gcc_qupv3_wrap0_qspi0_clk", &gcc, 0x112 }, - { "gcc_qupv3_wrap0_s0_clk", &gcc, 0x10a }, - { "gcc_qupv3_wrap0_s1_clk", &gcc, 0x10b }, - { "gcc_qupv3_wrap0_s2_clk", &gcc, 0x10c }, - { "gcc_qupv3_wrap0_s3_clk", &gcc, 0x10d }, - { "gcc_qupv3_wrap0_s4_clk", &gcc, 0x10e }, - { "gcc_qupv3_wrap0_s5_clk", &gcc, 0x10f }, - { "gcc_qupv3_wrap0_s6_clk", &gcc, 0x110 }, - { "gcc_qupv3_wrap0_s7_clk", &gcc, 0x111 }, - { "gcc_qupv3_wrap1_core_2x_clk", &gcc, 0x116 }, - { "gcc_qupv3_wrap1_core_clk", &gcc, 0x115 }, - { "gcc_qupv3_wrap1_qspi0_clk", &gcc, 0x11f }, - { "gcc_qupv3_wrap1_s0_clk", &gcc, 0x117 }, - { "gcc_qupv3_wrap1_s1_clk", &gcc, 0x118 }, - { "gcc_qupv3_wrap1_s2_clk", &gcc, 0x119 }, - { "gcc_qupv3_wrap1_s3_clk", &gcc, 0x11a }, - { "measure_only_gcc_qupv3_wrap1_s4_clk", &gcc, 0x11b }, - { "gcc_qupv3_wrap1_s5_clk", &gcc, 0x11c }, - { "gcc_qupv3_wrap1_s6_clk", &gcc, 0x11d }, - { "gcc_qupv3_wrap1_s7_clk", &gcc, 0x11e }, - { "gcc_qupv3_wrap2_core_2x_clk", &gcc, 0x251 }, - { "gcc_qupv3_wrap2_core_clk", &gcc, 0x250 }, - { "gcc_qupv3_wrap2_qspi0_clk", &gcc, 0x25a }, - { "gcc_qupv3_wrap2_s0_clk", &gcc, 0x252 }, - { "gcc_qupv3_wrap2_s1_clk", &gcc, 0x253 }, - { "gcc_qupv3_wrap2_s2_clk", &gcc, 0x254 }, - { "gcc_qupv3_wrap2_s3_clk", &gcc, 0x255 }, - { "gcc_qupv3_wrap2_s4_clk", &gcc, 0x256 }, - { "gcc_qupv3_wrap2_s5_clk", &gcc, 0x257 }, - { "gcc_qupv3_wrap2_s6_clk", &gcc, 0x258 }, - { "gcc_qupv3_wrap2_s7_clk", &gcc, 0x259 }, - { "gcc_qupv3_wrap_0_m_ahb_clk", &gcc, 0x106 }, - { "gcc_qupv3_wrap_0_s_ahb_clk", &gcc, 0x107 }, - { "measure_only_gcc_qupv3_wrap_1_m_ahb_clk", &gcc, 0x113 }, - { "measure_only_gcc_qupv3_wrap_1_s_ahb_clk", &gcc, 0x114 }, - { "gcc_qupv3_wrap_2_m_ahb_clk", &gcc, 0x24e }, - { "gcc_qupv3_wrap_2_s_ahb_clk", &gcc, 0x24f }, - { "gcc_sdcc2_ahb_clk", &gcc, 0x101 }, - { "gcc_sdcc2_apps_clk", &gcc, 0x100 }, - { "gcc_sdcc4_ahb_clk", &gcc, 0x104 }, - { "gcc_sdcc4_apps_clk", &gcc, 0x103 }, - { "gcc_sys_noc_usb_axi_clk", &gcc, 0x14 }, - { "gcc_ufs_card_ahb_clk", &gcc, 0x1d4 }, - { "gcc_ufs_card_axi_clk", &gcc, 0x1d3 }, - { "gcc_ufs_card_ice_core_clk", &gcc, 0x1da }, - { "gcc_ufs_card_phy_aux_clk", &gcc, 0x1db }, - { "gcc_ufs_card_rx_symbol_0_clk", &gcc, 0x1d6 }, - { "gcc_ufs_card_rx_symbol_1_clk", &gcc, 0x1dc }, - { "gcc_ufs_card_tx_symbol_0_clk", &gcc, 0x1d5 }, - { "gcc_ufs_card_unipro_core_clk", &gcc, 0x1d9 }, - { "gcc_ufs_phy_ahb_clk", &gcc, 0x1e0 }, - { "gcc_ufs_phy_axi_clk", &gcc, 0x1df }, - { "gcc_ufs_phy_ice_core_clk", &gcc, 0x1e6 }, - { "gcc_ufs_phy_phy_aux_clk", &gcc, 0x1e7 }, - { "gcc_ufs_phy_rx_symbol_0_clk", &gcc, 0x1e2 }, - { "gcc_ufs_phy_rx_symbol_1_clk", &gcc, 0x1e8 }, - { "gcc_ufs_phy_tx_symbol_0_clk", &gcc, 0x1e1 }, - { "gcc_ufs_phy_unipro_core_clk", &gcc, 0x1e5 }, - { "gcc_usb30_mp_master_clk", &gcc, 0xc5 }, - { "gcc_usb30_mp_mock_utmi_clk", &gcc, 0xc7 }, - { "gcc_usb30_prim_master_clk", &gcc, 0xb6 }, - { "gcc_usb30_prim_mock_utmi_clk", &gcc, 0xb8 }, - { "gcc_usb30_sec_master_clk", &gcc, 0xbf }, - { "gcc_usb30_sec_mock_utmi_clk", &gcc, 0xc1 }, - { "gcc_usb3_mp_phy_aux_clk", &gcc, 0xc8 }, - { "gcc_usb3_mp_phy_com_aux_clk", &gcc, 0xc9 }, - { "gcc_usb3_mp_phy_pipe_0_clk", &gcc, 0xca }, - { "gcc_usb3_mp_phy_pipe_1_clk", &gcc, 0xcb }, - { "gcc_usb3_prim_phy_aux_clk", &gcc, 0xb9 }, - { "gcc_usb3_prim_phy_com_aux_clk", &gcc, 0xba }, - { "gcc_usb3_prim_phy_pipe_clk", &gcc, 0xbb }, - { "gcc_usb3_sec_phy_aux_clk", &gcc, 0xc2 }, - { "gcc_usb3_sec_phy_com_aux_clk", &gcc, 0xc3 }, - { "gcc_usb3_sec_phy_pipe_clk", &gcc, 0xc4 }, - { "gcc_usb4_1_cfg_ahb_clk", &gcc, 0xf3 }, - { "gcc_usb4_1_dp_clk", &gcc, 0xf0 }, - { "gcc_usb4_1_master_clk", &gcc, 0xec }, - { "gcc_usb4_1_phy_p2rr2p_pipe_clk", &gcc, 0xf8 }, - { "gcc_usb4_1_phy_pcie_pipe_clk", &gcc, 0xee }, - { "gcc_usb4_1_phy_rx0_clk", &gcc, 0xf4 }, - { "gcc_usb4_1_phy_rx1_clk", &gcc, 0xf5 }, - { "gcc_usb4_1_phy_usb_pipe_clk", &gcc, 0xf2 }, - { "gcc_usb4_1_sb_if_clk", &gcc, 0xed }, - { "gcc_usb4_1_sys_clk", &gcc, 0xef }, - { "gcc_usb4_1_tmu_clk", &gcc, 0xf1 }, - { "gcc_usb4_cfg_ahb_clk", &gcc, 0xe1 }, - { "gcc_usb4_dp_clk", &gcc, 0xde }, - { "gcc_usb4_master_clk", &gcc, 0xda }, - { "gcc_usb4_phy_p2rr2p_pipe_clk", &gcc, 0xe6 }, - { "gcc_usb4_phy_pcie_pipe_clk", &gcc, 0xdc }, - { "gcc_usb4_phy_rx0_clk", &gcc, 0xe2 }, - { "gcc_usb4_phy_rx1_clk", &gcc, 0xe3 }, - { "gcc_usb4_phy_usb_pipe_clk", &gcc, 0xe0 }, - { "gcc_usb4_sb_if_clk", &gcc, 0xdb }, - { "gcc_usb4_sys_clk", &gcc, 0xdd }, - { "gcc_usb4_tmu_clk", &gcc, 0xdf }, - { "gcc_video_axi0_clk", &gcc, 0x88 }, - { "gcc_video_axi1_clk", &gcc, 0x89 }, - { "gcc_video_cvp_throttle_clk", &gcc, 0x8b }, - { "gcc_video_vcodec_throttle_clk", &gcc, 0x8a }, - { "measure_only_cnoc_clk", &gcc, 0x22 }, - { "measure_only_gcc_camera_ahb_clk", &gcc, 0x67 }, - { "measure_only_gcc_camera_xo_clk", &gcc, 0x6e }, - { "measure_only_gcc_disp1_ahb_clk", &gcc, 0x7a }, - { "measure_only_gcc_disp1_xo_clk", &gcc, 0x81 }, - { "measure_only_gcc_disp_ahb_clk", &gcc, 0x71 }, - { "measure_only_gcc_disp_xo_clk", &gcc, 0x78 }, - { "measure_only_gcc_gpu_cfg_ahb_clk", &gcc, 0x22a }, - { "measure_only_gcc_video_ahb_clk", &gcc, 0x85 }, - { "measure_only_gcc_video_xo_clk", &gcc, 0x8c }, - { "measure_only_ipa_2x_clk", &gcc, 0x225 }, - { "measure_only_memnoc_clk", &gcc, 0x15b }, - { "measure_only_snoc_clk", &gcc, 0xc }, - { "disp0_cc_mdss_ahb1_clk", &gcc, 0x79, &disp0_cc, 0x39 }, - { "disp0_cc_mdss_ahb_clk", &gcc, 0x79, &disp0_cc, 0x38 }, - { "disp0_cc_mdss_byte0_clk", &gcc, 0x79, &disp0_cc, 0x19 }, - { "disp0_cc_mdss_byte0_intf_clk", &gcc, 0x79, &disp0_cc, 0x1a }, - { "disp0_cc_mdss_byte1_clk", &gcc, 0x79, &disp0_cc, 0x1b }, - { "disp0_cc_mdss_byte1_intf_clk", &gcc, 0x79, &disp0_cc, 0x1c }, - { "disp0_cc_mdss_dptx0_aux_clk", &gcc, 0x79, &disp0_cc, 0x23 }, - { "disp0_cc_mdss_dptx0_link_clk", &gcc, 0x79, &disp0_cc, 0x1f }, - { "disp0_cc_mdss_dptx0_link_intf_clk", &gcc, 0x79, &disp0_cc, 0x20 }, - { "disp0_cc_mdss_dptx0_pixel0_clk", &gcc, 0x79, &disp0_cc, 0x24 }, - { "disp0_cc_mdss_dptx0_pixel1_clk", &gcc, 0x79, &disp0_cc, 0x25 }, - { "disp0_cc_mdss_dptx0_usb_router_link_intf_clk", &gcc, 0x79, &disp0_cc, 0x21 }, - { "disp0_cc_mdss_dptx1_aux_clk", &gcc, 0x79, &disp0_cc, 0x31 }, - { "disp0_cc_mdss_dptx1_link_clk", &gcc, 0x79, &disp0_cc, 0x2a }, - { "disp0_cc_mdss_dptx1_link_intf_clk", &gcc, 0x79, &disp0_cc, 0x2b }, - { "disp0_cc_mdss_dptx1_pixel0_clk", &gcc, 0x79, &disp0_cc, 0x26 }, - { "disp0_cc_mdss_dptx1_pixel1_clk", &gcc, 0x79, &disp0_cc, 0x27 }, - { "disp0_cc_mdss_dptx1_usb_router_link_intf_clk", &gcc, 0x79, &disp0_cc, 0x2c }, - { "disp0_cc_mdss_dptx2_aux_clk", &gcc, 0x79, &disp0_cc, 0x32 }, - { "disp0_cc_mdss_dptx2_link_clk", &gcc, 0x79, &disp0_cc, 0x2d }, - { "disp0_cc_mdss_dptx2_link_intf_clk", &gcc, 0x79, &disp0_cc, 0x2e }, - { "disp0_cc_mdss_dptx2_pixel0_clk", &gcc, 0x79, &disp0_cc, 0x28 }, - { "disp0_cc_mdss_dptx2_pixel1_clk", &gcc, 0x79, &disp0_cc, 0x29 }, - { "disp0_cc_mdss_dptx3_aux_clk", &gcc, 0x79, &disp0_cc, 0x37 }, - { "disp0_cc_mdss_dptx3_link_clk", &gcc, 0x79, &disp0_cc, 0x34 }, - { "disp0_cc_mdss_dptx3_link_intf_clk", &gcc, 0x79, &disp0_cc, 0x35 }, - { "disp0_cc_mdss_dptx3_pixel0_clk", &gcc, 0x79, &disp0_cc, 0x33 }, - { "disp0_cc_mdss_esc0_clk", &gcc, 0x79, &disp0_cc, 0x1d }, - { "disp0_cc_mdss_esc1_clk", &gcc, 0x79, &disp0_cc, 0x1e }, - { "disp0_cc_mdss_mdp1_clk", &gcc, 0x79, &disp0_cc, 0x12 }, - { "disp0_cc_mdss_mdp_clk", &gcc, 0x79, &disp0_cc, 0x11 }, - { "disp0_cc_mdss_mdp_lut1_clk", &gcc, 0x79, &disp0_cc, 0x16 }, - { "disp0_cc_mdss_mdp_lut_clk", &gcc, 0x79, &disp0_cc, 0x15 }, - { "disp0_cc_mdss_non_gdsc_ahb_clk", &gcc, 0x79, &disp0_cc, 0x3a }, - { "disp0_cc_mdss_pclk0_clk", &gcc, 0x79, &disp0_cc, 0xf }, - { "disp0_cc_mdss_pclk1_clk", &gcc, 0x79, &disp0_cc, 0x10 }, - { "disp0_cc_mdss_rot1_clk", &gcc, 0x79, &disp0_cc, 0x14 }, - { "disp0_cc_mdss_rot_clk", &gcc, 0x79, &disp0_cc, 0x13 }, - { "disp0_cc_mdss_rscc_ahb_clk", &gcc, 0x79, &disp0_cc, 0x3c }, - { "disp0_cc_mdss_rscc_vsync_clk", &gcc, 0x79, &disp0_cc, 0x3b }, - { "disp0_cc_mdss_vsync1_clk", &gcc, 0x79, &disp0_cc, 0x18 }, - { "disp0_cc_mdss_vsync_clk", &gcc, 0x79, &disp0_cc, 0x17 }, - { "disp0_cc_sleep_clk", &gcc, 0x79, &disp0_cc, 0x46 }, - { "disp0_cc_xo_clk", &gcc, 0x79, &disp0_cc, 0x45 }, - { "disp1_cc_mdss_ahb1_clk", &gcc, 0x82, &disp1_cc, 0x39 }, - { "disp1_cc_mdss_ahb_clk", &gcc, 0x82, &disp1_cc, 0x38 }, - { "disp1_cc_mdss_byte0_clk", &gcc, 0x82, &disp1_cc, 0x19 }, - { "disp1_cc_mdss_byte0_intf_clk", &gcc, 0x82, &disp1_cc, 0x1a }, - { "disp1_cc_mdss_byte1_clk", &gcc, 0x82, &disp1_cc, 0x1b }, - { "disp1_cc_mdss_byte1_intf_clk", &gcc, 0x82, &disp1_cc, 0x1c }, - { "disp1_cc_mdss_dptx0_aux_clk", &gcc, 0x82, &disp1_cc, 0x23 }, - { "disp1_cc_mdss_dptx0_link_clk", &gcc, 0x82, &disp1_cc, 0x1f }, - { "disp1_cc_mdss_dptx0_link_intf_clk", &gcc, 0x82, &disp1_cc, 0x20 }, - { "disp1_cc_mdss_dptx0_pixel0_clk", &gcc, 0x82, &disp1_cc, 0x24 }, - { "disp1_cc_mdss_dptx0_pixel1_clk", &gcc, 0x82, &disp1_cc, 0x25 }, - { "disp1_cc_mdss_dptx0_usb_router_link_intf_clk", &gcc, 0x82, &disp1_cc, 0x21 }, - { "disp1_cc_mdss_dptx1_aux_clk", &gcc, 0x82, &disp1_cc, 0x31 }, - { "disp1_cc_mdss_dptx1_link_clk", &gcc, 0x82, &disp1_cc, 0x2a }, - { "disp1_cc_mdss_dptx1_link_intf_clk", &gcc, 0x82, &disp1_cc, 0x2b }, - { "disp1_cc_mdss_dptx1_pixel0_clk", &gcc, 0x82, &disp1_cc, 0x26 }, - { "disp1_cc_mdss_dptx1_pixel1_clk", &gcc, 0x82, &disp1_cc, 0x27 }, - { "disp1_cc_mdss_dptx1_usb_router_link_intf_clk", &gcc, 0x82, &disp1_cc, 0x2c }, - { "disp1_cc_mdss_dptx2_aux_clk", &gcc, 0x82, &disp1_cc, 0x32 }, - { "disp1_cc_mdss_dptx2_link_clk", &gcc, 0x82, &disp1_cc, 0x2d }, - { "disp1_cc_mdss_dptx2_link_intf_clk", &gcc, 0x82, &disp1_cc, 0x2e }, - { "disp1_cc_mdss_dptx2_pixel0_clk", &gcc, 0x82, &disp1_cc, 0x28 }, - { "disp1_cc_mdss_dptx2_pixel1_clk", &gcc, 0x82, &disp1_cc, 0x29 }, - { "disp1_cc_mdss_dptx3_aux_clk", &gcc, 0x82, &disp1_cc, 0x37 }, - { "disp1_cc_mdss_dptx3_link_clk", &gcc, 0x82, &disp1_cc, 0x34 }, - { "disp1_cc_mdss_dptx3_link_intf_clk", &gcc, 0x82, &disp1_cc, 0x35 }, - { "disp1_cc_mdss_dptx3_pixel0_clk", &gcc, 0x82, &disp1_cc, 0x33 }, - { "disp1_cc_mdss_esc0_clk", &gcc, 0x82, &disp1_cc, 0x1d }, - { "disp1_cc_mdss_esc1_clk", &gcc, 0x82, &disp1_cc, 0x1e }, - { "disp1_cc_mdss_mdp1_clk", &gcc, 0x82, &disp1_cc, 0x12 }, - { "disp1_cc_mdss_mdp_clk", &gcc, 0x82, &disp1_cc, 0x11 }, - { "disp1_cc_mdss_mdp_lut1_clk", &gcc, 0x82, &disp1_cc, 0x16 }, - { "disp1_cc_mdss_mdp_lut_clk", &gcc, 0x82, &disp1_cc, 0x15 }, - { "disp1_cc_mdss_non_gdsc_ahb_clk", &gcc, 0x82, &disp1_cc, 0x3a }, - { "disp1_cc_mdss_pclk0_clk", &gcc, 0x82, &disp1_cc, 0xf }, - { "disp1_cc_mdss_pclk1_clk", &gcc, 0x82, &disp1_cc, 0x10 }, - { "disp1_cc_mdss_rot1_clk", &gcc, 0x82, &disp1_cc, 0x14 }, - { "disp1_cc_mdss_rot_clk", &gcc, 0x82, &disp1_cc, 0x13 }, - { "disp1_cc_mdss_rscc_ahb_clk", &gcc, 0x82, &disp1_cc, 0x3c }, - { "disp1_cc_mdss_rscc_vsync_clk", &gcc, 0x82, &disp1_cc, 0x3b }, - { "disp1_cc_mdss_vsync1_clk", &gcc, 0x82, &disp1_cc, 0x18 }, - { "disp1_cc_mdss_vsync_clk", &gcc, 0x82, &disp1_cc, 0x17 }, - { "disp1_cc_sleep_clk", &gcc, 0x82, &disp1_cc, 0x46 }, - { "disp1_cc_xo_clk", &gcc, 0x82, &disp1_cc, 0x45 }, - { "measure_only_mccc_clk", &gcc, 0xfeedbeef, &mc_cc, 0x50 }, + { "gcc_aggre_noc_pcie0_tunnel_axi_clk", &gcc.mux, 0x217 }, + { "gcc_aggre_noc_pcie1_tunnel_axi_clk", &gcc.mux, 0x218 }, + { "gcc_aggre_noc_pcie_4_axi_clk", &gcc.mux, 0x214 }, + { "gcc_aggre_noc_pcie_south_sf_axi_clk", &gcc.mux, 0x215 }, + { "gcc_aggre_ufs_card_axi_clk", &gcc.mux, 0x222 }, + { "gcc_aggre_ufs_phy_axi_clk", &gcc.mux, 0x221 }, + { "gcc_aggre_usb3_mp_axi_clk", &gcc.mux, 0x21b }, + { "gcc_aggre_usb3_prim_axi_clk", &gcc.mux, 0x219 }, + { "gcc_aggre_usb3_sec_axi_clk", &gcc.mux, 0x21a }, + { "gcc_aggre_usb4_1_axi_clk", &gcc.mux, 0x21d }, + { "gcc_aggre_usb4_axi_clk", &gcc.mux, 0x21c }, + { "gcc_aggre_usb_noc_axi_clk", &gcc.mux, 0x220 }, + { "gcc_aggre_usb_noc_north_axi_clk", &gcc.mux, 0x21f }, + { "gcc_aggre_usb_noc_south_axi_clk", &gcc.mux, 0x21e }, + { "gcc_ahb2phy0_clk", &gcc.mux, 0xfe }, + { "gcc_ahb2phy2_clk", &gcc.mux, 0xff }, + { "gcc_camera_hf_axi_clk", &gcc.mux, 0x6a }, + { "gcc_camera_sf_axi_clk", &gcc.mux, 0x6b }, + { "gcc_camera_throttle_nrt_axi_clk", &gcc.mux, 0x6d }, + { "gcc_camera_throttle_rt_axi_clk", &gcc.mux, 0x6c }, + { "gcc_camera_throttle_xo_clk", &gcc.mux, 0x6f }, + { "gcc_cfg_noc_usb3_mp_axi_clk", &gcc.mux, 0x2c }, + { "gcc_cfg_noc_usb3_prim_axi_clk", &gcc.mux, 0x2a }, + { "gcc_cfg_noc_usb3_sec_axi_clk", &gcc.mux, 0x2b }, + { "gcc_cnoc_pcie0_tunnel_clk", &gcc.mux, 0x1c }, + { "gcc_cnoc_pcie1_tunnel_clk", &gcc.mux, 0x1d }, + { "gcc_cnoc_pcie4_qx_clk", &gcc.mux, 0x18 }, + { "gcc_ddrss_gpu_axi_clk", &gcc.mux, 0x155 }, + { "gcc_ddrss_pcie_sf_tbu_clk", &gcc.mux, 0x156 }, + { "gcc_disp1_hf_axi_clk", &gcc.mux, 0x7d }, + { "gcc_disp1_sf_axi_clk", &gcc.mux, 0x7e }, + { "gcc_disp1_throttle_nrt_axi_clk", &gcc.mux, 0x80 }, + { "gcc_disp1_throttle_rt_axi_clk", &gcc.mux, 0x7f }, + { "gcc_disp_hf_axi_clk", &gcc.mux, 0x74 }, + { "gcc_disp_sf_axi_clk", &gcc.mux, 0x75 }, + { "gcc_disp_throttle_nrt_axi_clk", &gcc.mux, 0x77 }, + { "gcc_disp_throttle_rt_axi_clk", &gcc.mux, 0x76 }, + { "gcc_emac0_axi_clk", &gcc.mux, 0x246 }, + { "gcc_emac0_ptp_clk", &gcc.mux, 0x248 }, + { "gcc_emac0_rgmii_clk", &gcc.mux, 0x249 }, + { "gcc_emac0_slv_ahb_clk", &gcc.mux, 0x247 }, + { "gcc_emac1_axi_clk", &gcc.mux, 0x24a }, + { "gcc_emac1_ptp_clk", &gcc.mux, 0x24c }, + { "gcc_emac1_rgmii_clk", &gcc.mux, 0x24d }, + { "gcc_emac1_slv_ahb_clk", &gcc.mux, 0x24b }, + { "gcc_gp1_clk", &gcc.mux, 0x18c }, + { "gcc_gp2_clk", &gcc.mux, 0x18d }, + { "gcc_gp3_clk", &gcc.mux, 0x18e }, + { "gcc_gp4_clk", &gcc.mux, 0x290 }, + { "gcc_gp5_clk", &gcc.mux, 0x291 }, + { "gcc_gpu_gpll0_clk_src", &gcc.mux, 0x232 }, + { "gcc_gpu_gpll0_div_clk_src", &gcc.mux, 0x233 }, + { "gcc_gpu_memnoc_gfx_clk", &gcc.mux, 0x22e }, + { "gcc_gpu_snoc_dvm_gfx_clk", &gcc.mux, 0x231 }, + { "gcc_gpu_tcu_throttle_ahb_clk", &gcc.mux, 0x22b }, + { "gcc_gpu_tcu_throttle_clk", &gcc.mux, 0x22f }, + { "gcc_pcie0_phy_rchng_clk", &gcc.mux, 0x1d0 }, + { "gcc_pcie1_phy_rchng_clk", &gcc.mux, 0x19f }, + { "gcc_pcie2a_phy_rchng_clk", &gcc.mux, 0x1a9 }, + { "gcc_pcie2b_phy_rchng_clk", &gcc.mux, 0x1b3 }, + { "gcc_pcie3a_phy_rchng_clk", &gcc.mux, 0x1bd }, + { "gcc_pcie3b_phy_rchng_clk", &gcc.mux, 0x1c7 }, + { "gcc_pcie4_phy_rchng_clk", &gcc.mux, 0x196 }, + { "gcc_pcie_0_aux_clk", &gcc.mux, 0x1ce }, + { "gcc_pcie_0_cfg_ahb_clk", &gcc.mux, 0x1cd }, + { "gcc_pcie_0_mstr_axi_clk", &gcc.mux, 0x1cc }, + { "gcc_pcie_0_pipe_clk", &gcc.mux, 0x1cf }, + { "gcc_pcie_0_slv_axi_clk", &gcc.mux, 0x1cb }, + { "gcc_pcie_0_slv_q2a_axi_clk", &gcc.mux, 0x1ca }, + { "gcc_pcie_1_aux_clk", &gcc.mux, 0x19d }, + { "gcc_pcie_1_cfg_ahb_clk", &gcc.mux, 0x19c }, + { "gcc_pcie_1_mstr_axi_clk", &gcc.mux, 0x19b }, + { "gcc_pcie_1_pipe_clk", &gcc.mux, 0x19e }, + { "gcc_pcie_1_slv_axi_clk", &gcc.mux, 0x19a }, + { "gcc_pcie_1_slv_q2a_axi_clk", &gcc.mux, 0x199 }, + { "gcc_pcie_2a_aux_clk", &gcc.mux, 0x1a6 }, + { "gcc_pcie_2a_cfg_ahb_clk", &gcc.mux, 0x1a5 }, + { "gcc_pcie_2a_mstr_axi_clk", &gcc.mux, 0x1a4 }, + { "gcc_pcie_2a_pipe_clk", &gcc.mux, 0x1a7 }, + { "gcc_pcie_2a_pipediv2_clk", &gcc.mux, 0x1a8 }, + { "gcc_pcie_2a_slv_axi_clk", &gcc.mux, 0x1a3 }, + { "gcc_pcie_2a_slv_q2a_axi_clk", &gcc.mux, 0x1a2 }, + { "gcc_pcie_2b_aux_clk", &gcc.mux, 0x1b0 }, + { "gcc_pcie_2b_cfg_ahb_clk", &gcc.mux, 0x1af }, + { "gcc_pcie_2b_mstr_axi_clk", &gcc.mux, 0x1ae }, + { "gcc_pcie_2b_pipe_clk", &gcc.mux, 0x1b1 }, + { "gcc_pcie_2b_pipediv2_clk", &gcc.mux, 0x1b2 }, + { "gcc_pcie_2b_slv_axi_clk", &gcc.mux, 0x1ad }, + { "gcc_pcie_2b_slv_q2a_axi_clk", &gcc.mux, 0x1ac }, + { "gcc_pcie_3a_aux_clk", &gcc.mux, 0x1ba }, + { "gcc_pcie_3a_cfg_ahb_clk", &gcc.mux, 0x1b9 }, + { "gcc_pcie_3a_mstr_axi_clk", &gcc.mux, 0x1b8 }, + { "gcc_pcie_3a_pipe_clk", &gcc.mux, 0x1bb }, + { "gcc_pcie_3a_pipediv2_clk", &gcc.mux, 0x1bc }, + { "gcc_pcie_3a_slv_axi_clk", &gcc.mux, 0x1b7 }, + { "gcc_pcie_3a_slv_q2a_axi_clk", &gcc.mux, 0x1b6 }, + { "gcc_pcie_3b_aux_clk", &gcc.mux, 0x1c4 }, + { "gcc_pcie_3b_cfg_ahb_clk", &gcc.mux, 0x1c3 }, + { "gcc_pcie_3b_mstr_axi_clk", &gcc.mux, 0x1c2 }, + { "gcc_pcie_3b_pipe_clk", &gcc.mux, 0x1c5 }, + { "gcc_pcie_3b_pipediv2_clk", &gcc.mux, 0x1c6 }, + { "gcc_pcie_3b_slv_axi_clk", &gcc.mux, 0x1c1 }, + { "gcc_pcie_3b_slv_q2a_axi_clk", &gcc.mux, 0x1c0 }, + { "gcc_pcie_4_aux_clk", &gcc.mux, 0x193 }, + { "gcc_pcie_4_cfg_ahb_clk", &gcc.mux, 0x192 }, + { "gcc_pcie_4_mstr_axi_clk", &gcc.mux, 0x191 }, + { "gcc_pcie_4_pipe_clk", &gcc.mux, 0x194 }, + { "gcc_pcie_4_pipediv2_clk", &gcc.mux, 0x195 }, + { "gcc_pcie_4_slv_axi_clk", &gcc.mux, 0x190 }, + { "gcc_pcie_4_slv_q2a_axi_clk", &gcc.mux, 0x18f }, + { "gcc_pcie_rscc_ahb_clk", &gcc.mux, 0x8f }, + { "gcc_pcie_rscc_xo_clk", &gcc.mux, 0x8e }, + { "gcc_pcie_throttle_cfg_clk", &gcc.mux, 0x46 }, + { "gcc_pdm2_clk", &gcc.mux, 0x122 }, + { "gcc_pdm_ahb_clk", &gcc.mux, 0x120 }, + { "gcc_pdm_xo4_clk", &gcc.mux, 0x121 }, + { "gcc_qmip_camera_nrt_ahb_clk", &gcc.mux, 0x68 }, + { "gcc_qmip_camera_rt_ahb_clk", &gcc.mux, 0x69 }, + { "gcc_qmip_disp1_ahb_clk", &gcc.mux, 0x7b }, + { "gcc_qmip_disp1_rot_ahb_clk", &gcc.mux, 0x7c }, + { "gcc_qmip_disp_ahb_clk", &gcc.mux, 0x72 }, + { "gcc_qmip_disp_rot_ahb_clk", &gcc.mux, 0x73 }, + { "gcc_qmip_video_cvp_ahb_clk", &gcc.mux, 0x86 }, + { "gcc_qmip_video_vcodec_ahb_clk", &gcc.mux, 0x87 }, + { "gcc_qupv3_wrap0_core_2x_clk", &gcc.mux, 0x109 }, + { "gcc_qupv3_wrap0_core_clk", &gcc.mux, 0x108 }, + { "gcc_qupv3_wrap0_qspi0_clk", &gcc.mux, 0x112 }, + { "gcc_qupv3_wrap0_s0_clk", &gcc.mux, 0x10a }, + { "gcc_qupv3_wrap0_s1_clk", &gcc.mux, 0x10b }, + { "gcc_qupv3_wrap0_s2_clk", &gcc.mux, 0x10c }, + { "gcc_qupv3_wrap0_s3_clk", &gcc.mux, 0x10d }, + { "gcc_qupv3_wrap0_s4_clk", &gcc.mux, 0x10e }, + { "gcc_qupv3_wrap0_s5_clk", &gcc.mux, 0x10f }, + { "gcc_qupv3_wrap0_s6_clk", &gcc.mux, 0x110 }, + { "gcc_qupv3_wrap0_s7_clk", &gcc.mux, 0x111 }, + { "gcc_qupv3_wrap1_core_2x_clk", &gcc.mux, 0x116 }, + { "gcc_qupv3_wrap1_core_clk", &gcc.mux, 0x115 }, + { "gcc_qupv3_wrap1_qspi0_clk", &gcc.mux, 0x11f }, + { "gcc_qupv3_wrap1_s0_clk", &gcc.mux, 0x117 }, + { "gcc_qupv3_wrap1_s1_clk", &gcc.mux, 0x118 }, + { "gcc_qupv3_wrap1_s2_clk", &gcc.mux, 0x119 }, + { "gcc_qupv3_wrap1_s3_clk", &gcc.mux, 0x11a }, + { "measure_only_gcc_qupv3_wrap1_s4_clk", &gcc.mux, 0x11b }, + { "gcc_qupv3_wrap1_s5_clk", &gcc.mux, 0x11c }, + { "gcc_qupv3_wrap1_s6_clk", &gcc.mux, 0x11d }, + { "gcc_qupv3_wrap1_s7_clk", &gcc.mux, 0x11e }, + { "gcc_qupv3_wrap2_core_2x_clk", &gcc.mux, 0x251 }, + { "gcc_qupv3_wrap2_core_clk", &gcc.mux, 0x250 }, + { "gcc_qupv3_wrap2_qspi0_clk", &gcc.mux, 0x25a }, + { "gcc_qupv3_wrap2_s0_clk", &gcc.mux, 0x252 }, + { "gcc_qupv3_wrap2_s1_clk", &gcc.mux, 0x253 }, + { "gcc_qupv3_wrap2_s2_clk", &gcc.mux, 0x254 }, + { "gcc_qupv3_wrap2_s3_clk", &gcc.mux, 0x255 }, + { "gcc_qupv3_wrap2_s4_clk", &gcc.mux, 0x256 }, + { "gcc_qupv3_wrap2_s5_clk", &gcc.mux, 0x257 }, + { "gcc_qupv3_wrap2_s6_clk", &gcc.mux, 0x258 }, + { "gcc_qupv3_wrap2_s7_clk", &gcc.mux, 0x259 }, + { "gcc_qupv3_wrap_0_m_ahb_clk", &gcc.mux, 0x106 }, + { "gcc_qupv3_wrap_0_s_ahb_clk", &gcc.mux, 0x107 }, + { "measure_only_gcc_qupv3_wrap_1_m_ahb_clk", &gcc.mux, 0x113 }, + { "measure_only_gcc_qupv3_wrap_1_s_ahb_clk", &gcc.mux, 0x114 }, + { "gcc_qupv3_wrap_2_m_ahb_clk", &gcc.mux, 0x24e }, + { "gcc_qupv3_wrap_2_s_ahb_clk", &gcc.mux, 0x24f }, + { "gcc_sdcc2_ahb_clk", &gcc.mux, 0x101 }, + { "gcc_sdcc2_apps_clk", &gcc.mux, 0x100 }, + { "gcc_sdcc4_ahb_clk", &gcc.mux, 0x104 }, + { "gcc_sdcc4_apps_clk", &gcc.mux, 0x103 }, + { "gcc_sys_noc_usb_axi_clk", &gcc.mux, 0x14 }, + { "gcc_ufs_card_ahb_clk", &gcc.mux, 0x1d4 }, + { "gcc_ufs_card_axi_clk", &gcc.mux, 0x1d3 }, + { "gcc_ufs_card_ice_core_clk", &gcc.mux, 0x1da }, + { "gcc_ufs_card_phy_aux_clk", &gcc.mux, 0x1db }, + { "gcc_ufs_card_rx_symbol_0_clk", &gcc.mux, 0x1d6 }, + { "gcc_ufs_card_rx_symbol_1_clk", &gcc.mux, 0x1dc }, + { "gcc_ufs_card_tx_symbol_0_clk", &gcc.mux, 0x1d5 }, + { "gcc_ufs_card_unipro_core_clk", &gcc.mux, 0x1d9 }, + { "gcc_ufs_phy_ahb_clk", &gcc.mux, 0x1e0 }, + { "gcc_ufs_phy_axi_clk", &gcc.mux, 0x1df }, + { "gcc_ufs_phy_ice_core_clk", &gcc.mux, 0x1e6 }, + { "gcc_ufs_phy_phy_aux_clk", &gcc.mux, 0x1e7 }, + { "gcc_ufs_phy_rx_symbol_0_clk", &gcc.mux, 0x1e2 }, + { "gcc_ufs_phy_rx_symbol_1_clk", &gcc.mux, 0x1e8 }, + { "gcc_ufs_phy_tx_symbol_0_clk", &gcc.mux, 0x1e1 }, + { "gcc_ufs_phy_unipro_core_clk", &gcc.mux, 0x1e5 }, + { "gcc_usb30_mp_master_clk", &gcc.mux, 0xc5 }, + { "gcc_usb30_mp_mock_utmi_clk", &gcc.mux, 0xc7 }, + { "gcc_usb30_prim_master_clk", &gcc.mux, 0xb6 }, + { "gcc_usb30_prim_mock_utmi_clk", &gcc.mux, 0xb8 }, + { "gcc_usb30_sec_master_clk", &gcc.mux, 0xbf }, + { "gcc_usb30_sec_mock_utmi_clk", &gcc.mux, 0xc1 }, + { "gcc_usb3_mp_phy_aux_clk", &gcc.mux, 0xc8 }, + { "gcc_usb3_mp_phy_com_aux_clk", &gcc.mux, 0xc9 }, + { "gcc_usb3_mp_phy_pipe_0_clk", &gcc.mux, 0xca }, + { "gcc_usb3_mp_phy_pipe_1_clk", &gcc.mux, 0xcb }, + { "gcc_usb3_prim_phy_aux_clk", &gcc.mux, 0xb9 }, + { "gcc_usb3_prim_phy_com_aux_clk", &gcc.mux, 0xba }, + { "gcc_usb3_prim_phy_pipe_clk", &gcc.mux, 0xbb }, + { "gcc_usb3_sec_phy_aux_clk", &gcc.mux, 0xc2 }, + { "gcc_usb3_sec_phy_com_aux_clk", &gcc.mux, 0xc3 }, + { "gcc_usb3_sec_phy_pipe_clk", &gcc.mux, 0xc4 }, + { "gcc_usb4_1_cfg_ahb_clk", &gcc.mux, 0xf3 }, + { "gcc_usb4_1_dp_clk", &gcc.mux, 0xf0 }, + { "gcc_usb4_1_master_clk", &gcc.mux, 0xec }, + { "gcc_usb4_1_phy_p2rr2p_pipe_clk", &gcc.mux, 0xf8 }, + { "gcc_usb4_1_phy_pcie_pipe_clk", &gcc.mux, 0xee }, + { "gcc_usb4_1_phy_rx0_clk", &gcc.mux, 0xf4 }, + { "gcc_usb4_1_phy_rx1_clk", &gcc.mux, 0xf5 }, + { "gcc_usb4_1_phy_usb_pipe_clk", &gcc.mux, 0xf2 }, + { "gcc_usb4_1_sb_if_clk", &gcc.mux, 0xed }, + { "gcc_usb4_1_sys_clk", &gcc.mux, 0xef }, + { "gcc_usb4_1_tmu_clk", &gcc.mux, 0xf1 }, + { "gcc_usb4_cfg_ahb_clk", &gcc.mux, 0xe1 }, + { "gcc_usb4_dp_clk", &gcc.mux, 0xde }, + { "gcc_usb4_master_clk", &gcc.mux, 0xda }, + { "gcc_usb4_phy_p2rr2p_pipe_clk", &gcc.mux, 0xe6 }, + { "gcc_usb4_phy_pcie_pipe_clk", &gcc.mux, 0xdc }, + { "gcc_usb4_phy_rx0_clk", &gcc.mux, 0xe2 }, + { "gcc_usb4_phy_rx1_clk", &gcc.mux, 0xe3 }, + { "gcc_usb4_phy_usb_pipe_clk", &gcc.mux, 0xe0 }, + { "gcc_usb4_sb_if_clk", &gcc.mux, 0xdb }, + { "gcc_usb4_sys_clk", &gcc.mux, 0xdd }, + { "gcc_usb4_tmu_clk", &gcc.mux, 0xdf }, + { "gcc_video_axi0_clk", &gcc.mux, 0x88 }, + { "gcc_video_axi1_clk", &gcc.mux, 0x89 }, + { "gcc_video_cvp_throttle_clk", &gcc.mux, 0x8b }, + { "gcc_video_vcodec_throttle_clk", &gcc.mux, 0x8a }, + { "measure_only_cnoc_clk", &gcc.mux, 0x22 }, + { "measure_only_gcc_camera_ahb_clk", &gcc.mux, 0x67 }, + { "measure_only_gcc_camera_xo_clk", &gcc.mux, 0x6e }, + { "measure_only_gcc_disp1_ahb_clk", &gcc.mux, 0x7a }, + { "measure_only_gcc_disp1_xo_clk", &gcc.mux, 0x81 }, + { "measure_only_gcc_disp_ahb_clk", &gcc.mux, 0x71 }, + { "measure_only_gcc_disp_xo_clk", &gcc.mux, 0x78 }, + { "measure_only_gcc_gpu_cfg_ahb_clk", &gcc.mux, 0x22a }, + { "measure_only_gcc_video_ahb_clk", &gcc.mux, 0x85 }, + { "measure_only_gcc_video_xo_clk", &gcc.mux, 0x8c }, + { "measure_only_ipa_2x_clk", &gcc.mux, 0x225 }, + { "measure_only_memnoc_clk", &gcc.mux, 0x15b }, + { "measure_only_snoc_clk", &gcc.mux, 0xc }, + { "disp0_cc_mdss_ahb1_clk", &disp0_cc, 0x39 }, + { "disp0_cc_mdss_ahb_clk", &disp0_cc, 0x38 }, + { "disp0_cc_mdss_byte0_clk", &disp0_cc, 0x19 }, + { "disp0_cc_mdss_byte0_intf_clk", &disp0_cc, 0x1a }, + { "disp0_cc_mdss_byte1_clk", &disp0_cc, 0x1b }, + { "disp0_cc_mdss_byte1_intf_clk", &disp0_cc, 0x1c }, + { "disp0_cc_mdss_dptx0_aux_clk", &disp0_cc, 0x23 }, + { "disp0_cc_mdss_dptx0_link_clk", &disp0_cc, 0x1f }, + { "disp0_cc_mdss_dptx0_link_intf_clk", &disp0_cc, 0x20 }, + { "disp0_cc_mdss_dptx0_pixel0_clk", &disp0_cc, 0x24 }, + { "disp0_cc_mdss_dptx0_pixel1_clk", &disp0_cc, 0x25 }, + { "disp0_cc_mdss_dptx0_usb_router_link_intf_clk", &disp0_cc, 0x21 }, + { "disp0_cc_mdss_dptx1_aux_clk", &disp0_cc, 0x31 }, + { "disp0_cc_mdss_dptx1_link_clk", &disp0_cc, 0x2a }, + { "disp0_cc_mdss_dptx1_link_intf_clk", &disp0_cc, 0x2b }, + { "disp0_cc_mdss_dptx1_pixel0_clk", &disp0_cc, 0x26 }, + { "disp0_cc_mdss_dptx1_pixel1_clk", &disp0_cc, 0x27 }, + { "disp0_cc_mdss_dptx1_usb_router_link_intf_clk", &disp0_cc, 0x2c }, + { "disp0_cc_mdss_dptx2_aux_clk", &disp0_cc, 0x32 }, + { "disp0_cc_mdss_dptx2_link_clk", &disp0_cc, 0x2d }, + { "disp0_cc_mdss_dptx2_link_intf_clk", &disp0_cc, 0x2e }, + { "disp0_cc_mdss_dptx2_pixel0_clk", &disp0_cc, 0x28 }, + { "disp0_cc_mdss_dptx2_pixel1_clk", &disp0_cc, 0x29 }, + { "disp0_cc_mdss_dptx3_aux_clk", &disp0_cc, 0x37 }, + { "disp0_cc_mdss_dptx3_link_clk", &disp0_cc, 0x34 }, + { "disp0_cc_mdss_dptx3_link_intf_clk", &disp0_cc, 0x35 }, + { "disp0_cc_mdss_dptx3_pixel0_clk", &disp0_cc, 0x33 }, + { "disp0_cc_mdss_esc0_clk", &disp0_cc, 0x1d }, + { "disp0_cc_mdss_esc1_clk", &disp0_cc, 0x1e }, + { "disp0_cc_mdss_mdp1_clk", &disp0_cc, 0x12 }, + { "disp0_cc_mdss_mdp_clk", &disp0_cc, 0x11 }, + { "disp0_cc_mdss_mdp_lut1_clk", &disp0_cc, 0x16 }, + { "disp0_cc_mdss_mdp_lut_clk", &disp0_cc, 0x15 }, + { "disp0_cc_mdss_non_gdsc_ahb_clk", &disp0_cc, 0x3a }, + { "disp0_cc_mdss_pclk0_clk", &disp0_cc, 0xf }, + { "disp0_cc_mdss_pclk1_clk", &disp0_cc, 0x10 }, + { "disp0_cc_mdss_rot1_clk", &disp0_cc, 0x14 }, + { "disp0_cc_mdss_rot_clk", &disp0_cc, 0x13 }, + { "disp0_cc_mdss_rscc_ahb_clk", &disp0_cc, 0x3c }, + { "disp0_cc_mdss_rscc_vsync_clk", &disp0_cc, 0x3b }, + { "disp0_cc_mdss_vsync1_clk", &disp0_cc, 0x18 }, + { "disp0_cc_mdss_vsync_clk", &disp0_cc, 0x17 }, + { "disp0_cc_sleep_clk", &disp0_cc, 0x46 }, + { "disp0_cc_xo_clk", &disp0_cc, 0x45 }, + { "disp1_cc_mdss_ahb1_clk", &disp1_cc, 0x39 }, + { "disp1_cc_mdss_ahb_clk", &disp1_cc, 0x38 }, + { "disp1_cc_mdss_byte0_clk", &disp1_cc, 0x19 }, + { "disp1_cc_mdss_byte0_intf_clk", &disp1_cc, 0x1a }, + { "disp1_cc_mdss_byte1_clk", &disp1_cc, 0x1b }, + { "disp1_cc_mdss_byte1_intf_clk", &disp1_cc, 0x1c }, + { "disp1_cc_mdss_dptx0_aux_clk", &disp1_cc, 0x23 }, + { "disp1_cc_mdss_dptx0_link_clk", &disp1_cc, 0x1f }, + { "disp1_cc_mdss_dptx0_link_intf_clk", &disp1_cc, 0x20 }, + { "disp1_cc_mdss_dptx0_pixel0_clk", &disp1_cc, 0x24 }, + { "disp1_cc_mdss_dptx0_pixel1_clk", &disp1_cc, 0x25 }, + { "disp1_cc_mdss_dptx0_usb_router_link_intf_clk", &disp1_cc, 0x21 }, + { "disp1_cc_mdss_dptx1_aux_clk", &disp1_cc, 0x31 }, + { "disp1_cc_mdss_dptx1_link_clk", &disp1_cc, 0x2a }, + { "disp1_cc_mdss_dptx1_link_intf_clk", &disp1_cc, 0x2b }, + { "disp1_cc_mdss_dptx1_pixel0_clk", &disp1_cc, 0x26 }, + { "disp1_cc_mdss_dptx1_pixel1_clk", &disp1_cc, 0x27 }, + { "disp1_cc_mdss_dptx1_usb_router_link_intf_clk", &disp1_cc, 0x2c }, + { "disp1_cc_mdss_dptx2_aux_clk", &disp1_cc, 0x32 }, + { "disp1_cc_mdss_dptx2_link_clk", &disp1_cc, 0x2d }, + { "disp1_cc_mdss_dptx2_link_intf_clk", &disp1_cc, 0x2e }, + { "disp1_cc_mdss_dptx2_pixel0_clk", &disp1_cc, 0x28 }, + { "disp1_cc_mdss_dptx2_pixel1_clk", &disp1_cc, 0x29 }, + { "disp1_cc_mdss_dptx3_aux_clk", &disp1_cc, 0x37 }, + { "disp1_cc_mdss_dptx3_link_clk", &disp1_cc, 0x34 }, + { "disp1_cc_mdss_dptx3_link_intf_clk", &disp1_cc, 0x35 }, + { "disp1_cc_mdss_dptx3_pixel0_clk", &disp1_cc, 0x33 }, + { "disp1_cc_mdss_esc0_clk", &disp1_cc, 0x1d }, + { "disp1_cc_mdss_esc1_clk", &disp1_cc, 0x1e }, + { "disp1_cc_mdss_mdp1_clk", &disp1_cc, 0x12 }, + { "disp1_cc_mdss_mdp_clk", &disp1_cc, 0x11 }, + { "disp1_cc_mdss_mdp_lut1_clk", &disp1_cc, 0x16 }, + { "disp1_cc_mdss_mdp_lut_clk", &disp1_cc, 0x15 }, + { "disp1_cc_mdss_non_gdsc_ahb_clk", &disp1_cc, 0x3a }, + { "disp1_cc_mdss_pclk0_clk", &disp1_cc, 0xf }, + { "disp1_cc_mdss_pclk1_clk", &disp1_cc, 0x10 }, + { "disp1_cc_mdss_rot1_clk", &disp1_cc, 0x14 }, + { "disp1_cc_mdss_rot_clk", &disp1_cc, 0x13 }, + { "disp1_cc_mdss_rscc_ahb_clk", &disp1_cc, 0x3c }, + { "disp1_cc_mdss_rscc_vsync_clk", &disp1_cc, 0x3b }, + { "disp1_cc_mdss_vsync1_clk", &disp1_cc, 0x18 }, + { "disp1_cc_mdss_vsync_clk", &disp1_cc, 0x17 }, + { "disp1_cc_sleep_clk", &disp1_cc, 0x46 }, + { "disp1_cc_xo_clk", &disp1_cc, 0x45 }, + { "measure_only_mccc_clk", &mc_cc, 0x50 }, {} }; diff --git a/sdm845.c b/sdm845.c index a66abf9..0f2fb13 100644 --- a/sdm845.c +++ b/sdm845.c @@ -49,19 +49,23 @@ #define GCC_DEBUG_STATUS 0x62028 #define GCC_XO_DIV4_CBCR 0x43008 -static struct debug_mux gcc = { - .phys = GCC_BASE, - .size = GCC_SIZE, +static struct gcc_mux gcc = { + .mux = { + .phys = GCC_BASE, + .size = GCC_SIZE, - .enable_reg = GCC_DEBUG_CBCR, - .enable_mask = BIT(0), + .measure = measure_gcc, + + .enable_reg = GCC_DEBUG_CBCR, + .enable_mask = BIT(0), - .mux_reg = GCC_DEBUG_OFFSET, - .mux_mask = 0x3ff, + .mux_reg = GCC_DEBUG_OFFSET, + .mux_mask = 0x3ff, - .div_reg = GCC_DEBUG_POST_DIV, - .div_mask = 0xf, - .div_val = 4, + .div_reg = GCC_DEBUG_POST_DIV, + .div_mask = 0xf, + .div_val = 4, + }, .xo_div4_reg = GCC_XO_DIV4_CBCR, .debug_ctl_reg = GCC_DEBUG_CTL, @@ -73,6 +77,10 @@ static struct debug_mux cam_cc = { .size = 0x10000, .block_name = "cam", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 70, + .enable_reg = 0xc008, .enable_mask = BIT(0), @@ -88,6 +96,10 @@ static struct debug_mux cpu = { .size = 4096, .block_name = "cpu", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 214, + .enable_reg = 0x18, .enable_mask = BIT(0), @@ -105,6 +117,10 @@ static struct debug_mux disp_cc = { .size = 0x10000, .block_name = "disp", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 71, + .enable_reg = 0x600c, .enable_mask = BIT(0), @@ -120,6 +136,10 @@ static struct debug_mux gpu_cc = { .size = 0x9000, .block_name = "gpu", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 324, + .enable_reg = 0x1100, .enable_mask = BIT(0), @@ -135,6 +155,10 @@ static struct debug_mux video_cc = { .size = 0x10000, .block_name = "video", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 72, + .enable_reg = 0xa58, .enable_mask = BIT(0), @@ -146,252 +170,252 @@ static struct debug_mux video_cc = { }; static struct measure_clk sdm845_clocks[] = { - { "measure_only_snoc_clk", &gcc, 7 }, - { "gcc_sys_noc_cpuss_ahb_clk", &gcc, 12 }, - { "measure_only_cnoc_clk", &gcc, 21 }, - { "gcc_cfg_noc_usb3_prim_axi_clk", &gcc, 29 }, - { "gcc_cfg_noc_usb3_sec_axi_clk", &gcc, 30 }, - { "gcc_aggre_noc_pcie_tbu_clk", &gcc, 45 }, - { "gcc_video_ahb_clk", &gcc, 57 }, - { "gcc_camera_ahb_clk", &gcc, 58 }, - { "gcc_disp_ahb_clk", &gcc, 59 }, - { "gcc_qmip_video_ahb_clk", &gcc, 60 }, - { "gcc_qmip_camera_ahb_clk", &gcc, 61 }, - { "gcc_qmip_disp_ahb_clk", &gcc, 62 }, - { "gcc_video_axi_clk", &gcc, 63 }, - { "gcc_camera_axi_clk", &gcc, 64 }, - { "gcc_disp_axi_clk", &gcc, 65 }, - { "gcc_video_xo_clk", &gcc, 66 }, - { "gcc_camera_xo_clk", &gcc, 67 }, - { "gcc_disp_xo_clk", &gcc, 68 }, - { "cam_cc_mclk0_clk", &gcc, 70, &cam_cc, 1 }, - { "cam_cc_mclk1_clk", &gcc, 70, &cam_cc, 2 }, - { "cam_cc_mclk2_clk", &gcc, 70, &cam_cc, 3 }, - { "cam_cc_mclk3_clk", &gcc, 70, &cam_cc, 4 }, - { "cam_cc_csi0phytimer_clk", &gcc, 70, &cam_cc, 5 }, - { "cam_cc_csiphy0_clk", &gcc, 70, &cam_cc, 6 }, - { "cam_cc_csi1phytimer_clk", &gcc, 70, &cam_cc, 7 }, - { "cam_cc_csiphy1_clk", &gcc, 70, &cam_cc, 8 }, - { "cam_cc_csi2phytimer_clk", &gcc, 70, &cam_cc, 9 }, - { "cam_cc_csiphy2_clk", &gcc, 70, &cam_cc, 10 }, - { "cam_cc_bps_clk", &gcc, 70, &cam_cc, 11 }, - { "cam_cc_bps_axi_clk", &gcc, 70, &cam_cc, 12 }, - { "cam_cc_bps_areg_clk", &gcc, 70, &cam_cc, 13 }, - { "cam_cc_bps_ahb_clk", &gcc, 70, &cam_cc, 14 }, - { "cam_cc_ipe_0_clk", &gcc, 70, &cam_cc, 15 }, - { "cam_cc_ipe_0_axi_clk", &gcc, 70, &cam_cc, 16 }, - { "cam_cc_ipe_0_areg_clk", &gcc, 70, &cam_cc, 17 }, - { "cam_cc_ipe_0_ahb_clk", &gcc, 70, &cam_cc, 18 }, - { "cam_cc_ipe_1_clk", &gcc, 70, &cam_cc, 19 }, - { "cam_cc_ipe_1_axi_clk", &gcc, 70, &cam_cc, 20 }, - { "cam_cc_ipe_1_areg_clk", &gcc, 70, &cam_cc, 21 }, - { "cam_cc_ipe_1_ahb_clk", &gcc, 70, &cam_cc, 22 }, - { "cam_cc_ife_0_clk", &gcc, 70, &cam_cc, 23 }, - { "cam_cc_ife_0_dsp_clk", &gcc, 70, &cam_cc, 24 }, - { "cam_cc_ife_0_csid_clk", &gcc, 70, &cam_cc, 25 }, - { "cam_cc_ife_0_cphy_rx_clk", &gcc, 70, &cam_cc, 26 }, - { "cam_cc_ife_0_axi_clk", &gcc, 70, &cam_cc, 27 }, - { "cam_cc_ife_1_clk", &gcc, 70, &cam_cc, 29 }, - { "cam_cc_ife_1_dsp_clk", &gcc, 70, &cam_cc, 30 }, - { "cam_cc_ife_1_csid_clk", &gcc, 70, &cam_cc, 31 }, - { "cam_cc_ife_1_cphy_rx_clk", &gcc, 70, &cam_cc, 32 }, - { "cam_cc_ife_1_axi_clk", &gcc, 70, &cam_cc, 33 }, - { "cam_cc_ife_lite_clk", &gcc, 70, &cam_cc, 34 }, - { "cam_cc_ife_lite_csid_clk", &gcc, 70, &cam_cc, 35 }, - { "cam_cc_ife_lite_cphy_rx_clk", &gcc, 70, &cam_cc, 36 }, - { "cam_cc_jpeg_clk", &gcc, 70, &cam_cc, 37 }, - { "cam_cc_icp_clk", &gcc, 70, &cam_cc, 38 }, - { "cam_cc_fd_core_clk", &gcc, 70, &cam_cc, 40 }, - { "cam_cc_fd_core_uar_clk", &gcc, 70, &cam_cc, 41 }, - { "cam_cc_cci_clk", &gcc, 70, &cam_cc, 42 }, - { "cam_cc_lrme_clk", &gcc, 70, &cam_cc, 43 }, - { "cam_cc_cpas_ahb_clk", &gcc, 70, &cam_cc, 44 }, - { "cam_cc_camnoc_axi_clk", &gcc, 70, &cam_cc, 45 }, - { "cam_cc_soc_ahb_clk", &gcc, 70, &cam_cc, 46 }, - { "cam_cc_icp_atb_clk", &gcc, 70, &cam_cc, 47 }, - { "cam_cc_icp_cti_clk", &gcc, 70, &cam_cc, 48 }, - { "cam_cc_icp_ts_clk", &gcc, 70, &cam_cc, 49 }, - { "cam_cc_icp_apb_clk", &gcc, 70, &cam_cc, 50 }, - { "cam_cc_sys_tmr_clk", &gcc, 70, &cam_cc, 51 }, - { "cam_cc_camnoc_atb_clk", &gcc, 70, &cam_cc, 52 }, - { "cam_cc_csiphy3_clk", &gcc, 70, &cam_cc, 54 }, - { "disp_cc_mdss_pclk0_clk", &gcc, 71, &disp_cc, 1 }, - { "disp_cc_mdss_pclk1_clk", &gcc, 71, &disp_cc, 2 }, - { "disp_cc_mdss_mdp_clk", &gcc, 71, &disp_cc, 3 }, - { "disp_cc_mdss_rot_clk", &gcc, 71, &disp_cc, 4 }, - { "disp_cc_mdss_mdp_lut_clk", &gcc, 71, &disp_cc, 5 }, - { "disp_cc_mdss_vsync_clk", &gcc, 71, &disp_cc, 6 }, - { "disp_cc_mdss_byte0_clk", &gcc, 71, &disp_cc, 7 }, - { "disp_cc_mdss_byte0_intf_clk", &gcc, 71, &disp_cc, 8 }, - { "disp_cc_mdss_byte1_clk", &gcc, 71, &disp_cc, 9 }, - { "disp_cc_mdss_byte1_intf_clk", &gcc, 71, &disp_cc, 10 }, - { "disp_cc_mdss_esc0_clk", &gcc, 71, &disp_cc, 11 }, - { "disp_cc_mdss_esc1_clk", &gcc, 71, &disp_cc, 12 }, - { "disp_cc_mdss_dp_link_clk", &gcc, 71, &disp_cc, 13 }, - { "disp_cc_mdss_dp_link_intf_clk", &gcc, 71, &disp_cc, 14 }, - { "disp_cc_mdss_dp_crypto_clk", &gcc, 71, &disp_cc, 15 }, - { "disp_cc_mdss_dp_pixel_clk", &gcc, 71, &disp_cc, 16 }, - { "disp_cc_mdss_dp_pixel1_clk", &gcc, 71, &disp_cc, 17 }, - { "disp_cc_mdss_dp_aux_clk", &gcc, 71, &disp_cc, 18 }, - { "disp_cc_mdss_ahb_clk", &gcc, 71, &disp_cc, 19 }, - { "disp_cc_mdss_axi_clk", &gcc, 71, &disp_cc, 20 }, - { "disp_cc_mdss_qdss_at_clk", &gcc, 71, &disp_cc, 21 }, - { "disp_cc_mdss_qdss_tsctr_div8_clk", &gcc, 71, &disp_cc, 22 }, - { "disp_cc_mdss_rscc_ahb_clk", &gcc, 71, &disp_cc, 23 }, - { "disp_cc_mdss_rscc_vsync_clk", &gcc, 71, &disp_cc, 24 }, - { "video_cc_venus_ctl_core_clk", &gcc, 72, &video_cc, 1 }, - { "video_cc_vcodec0_core_clk", &gcc, 72, &video_cc, 2 }, - { "video_cc_vcodec1_core_clk", &gcc, 72, &video_cc, 3 }, - { "video_cc_venus_ctl_axi_clk", &gcc, 72, &video_cc, 4 }, - { "video_cc_vcodec0_axi_clk", &gcc, 72, &video_cc, 5 }, - { "video_cc_vcodec1_axi_clk", &gcc, 72, &video_cc, 6 }, - { "video_cc_qdss_trig_clk", &gcc, 72, &video_cc, 7 }, - { "video_cc_apb_clk", &gcc, 72, &video_cc, 8 }, - { "video_cc_venus_ahb_clk", &gcc, 72, &video_cc, 9 }, - { "video_cc_qdss_tsctr_div8_clk", &gcc, 72, &video_cc, 10 }, - { "video_cc_at_clk", &gcc, 72, &video_cc, 11 }, - { "gcc_disp_gpll0_clk_src", &gcc, 76 }, - { "gcc_disp_gpll0_div_clk_src", &gcc, 77 }, - { "gcc_usb30_prim_master_clk", &gcc, 95 }, - { "gcc_usb30_prim_sleep_clk", &gcc, 96 }, - { "gcc_usb30_prim_mock_utmi_clk", &gcc, 97 }, - { "gcc_usb3_prim_phy_aux_clk", &gcc, 98 }, - { "gcc_usb3_prim_phy_com_aux_clk", &gcc, 99 }, - { "gcc_usb3_prim_phy_pipe_clk", &gcc, 100 }, - { "gcc_usb30_sec_master_clk", &gcc, 101 }, - { "gcc_usb30_sec_sleep_clk", &gcc, 102 }, - { "gcc_usb30_sec_mock_utmi_clk", &gcc, 103 }, - { "gcc_usb3_sec_phy_aux_clk", &gcc, 104 }, - { "gcc_usb3_sec_phy_com_aux_clk", &gcc, 105 }, - { "gcc_usb3_sec_phy_pipe_clk", &gcc, 106 }, - { "gcc_usb_phy_cfg_ahb2phy_clk", &gcc, 111 }, - { "gcc_sdcc2_apps_clk", &gcc, 112 }, - { "gcc_sdcc2_ahb_clk", &gcc, 113 }, - { "gcc_sdcc4_apps_clk", &gcc, 114 }, - { "gcc_sdcc4_ahb_clk", &gcc, 115 }, - { "gcc_qupv3_wrap_0_m_ahb_clk", &gcc, 116 }, - { "gcc_qupv3_wrap_0_s_ahb_clk", &gcc, 117 }, - { "gcc_qupv3_wrap0_core_clk", &gcc, 118 }, - { "gcc_qupv3_wrap0_core_2x_clk", &gcc, 119 }, - { "gcc_qupv3_wrap0_s0_clk", &gcc, 120 }, - { "gcc_qupv3_wrap0_s1_clk", &gcc, 121 }, - { "gcc_qupv3_wrap0_s2_clk", &gcc, 122 }, - { "gcc_qupv3_wrap0_s3_clk", &gcc, 123 }, - { "gcc_qupv3_wrap0_s4_clk", &gcc, 124 }, - { "gcc_qupv3_wrap0_s5_clk", &gcc, 125 }, - { "gcc_qupv3_wrap0_s6_clk", &gcc, 126 }, - { "gcc_qupv3_wrap0_s7_clk", &gcc, 127 }, - { "gcc_qupv3_wrap1_core_2x_clk", &gcc, 128 }, - { "gcc_qupv3_wrap1_core_clk", &gcc, 129 }, - { "gcc_qupv3_wrap_1_m_ahb_clk", &gcc, 130 }, - { "gcc_qupv3_wrap_1_s_ahb_clk", &gcc, 131 }, - { "gcc_qupv3_wrap1_s0_clk", &gcc, 132 }, - { "gcc_qupv3_wrap1_s1_clk", &gcc, 133 }, - { "gcc_qupv3_wrap1_s2_clk", &gcc, 134 }, - { "gcc_qupv3_wrap1_s3_clk", &gcc, 135 }, - { "gcc_qupv3_wrap1_s4_clk", &gcc, 136 }, - { "gcc_qupv3_wrap1_s5_clk", &gcc, 137 }, - { "gcc_qupv3_wrap1_s6_clk", &gcc, 138 }, - { "gcc_qupv3_wrap1_s7_clk", &gcc, 139 }, - { "gcc_pdm_ahb_clk", &gcc, 140 }, - { "gcc_pdm_xo4_clk", &gcc, 141 }, - { "gcc_pdm2_clk", &gcc, 142 }, - { "gcc_prng_ahb_clk", &gcc, 143 }, - { "gcc_tsif_ahb_clk", &gcc, 144 }, - { "gcc_tsif_ref_clk", &gcc, 145 }, - { "gcc_tsif_inactivity_timers_clk", &gcc, 146 }, - { "gcc_boot_rom_ahb_clk", &gcc, 148 }, - { "gcc_ce1_clk", &gcc, 167 }, - { "gcc_ce1_axi_clk", &gcc, 168 }, - { "gcc_ce1_ahb_clk", &gcc, 169 }, - { "gcc_ddrss_gpu_axi_clk", &gcc, 187 }, - { "measure_only_bimc_clk", &gcc, 194 }, - { "gcc_cpuss_ahb_clk", &gcc, 206 }, - { "gcc_cpuss_gnoc_clk", &gcc, 207 }, - { "gcc_cpuss_rbcpr_clk", &gcc, 208 }, - { "gcc_cpuss_dvm_bus_clk", &gcc, 211 }, - { "pwrcl_clk", &gcc, 214, &cpu, 68, 16 }, - { "perfcl_clk", &gcc, 214, &cpu, 69, 16 }, - { "l3_clk", &gcc, 214, &cpu, 70, 16 }, - { "gcc_gp1_clk", &gcc, 222 }, - { "gcc_gp2_clk", &gcc, 223 }, - { "gcc_gp3_clk", &gcc, 224 }, - { "gcc_pcie_0_slv_q2a_axi_clk", &gcc, 225 }, - { "gcc_pcie_0_slv_axi_clk", &gcc, 226 }, - { "gcc_pcie_0_mstr_axi_clk", &gcc, 227 }, - { "gcc_pcie_0_cfg_ahb_clk", &gcc, 228 }, - { "gcc_pcie_0_aux_clk", &gcc, 229 }, - { "gcc_pcie_0_pipe_clk", &gcc, 230 }, - { "gcc_pcie_1_slv_q2a_axi_clk", &gcc, 232 }, - { "gcc_pcie_1_slv_axi_clk", &gcc, 233 }, - { "gcc_pcie_1_mstr_axi_clk", &gcc, 234 }, - { "gcc_pcie_1_cfg_ahb_clk", &gcc, 235 }, - { "gcc_pcie_1_aux_clk", &gcc, 236 }, - { "gcc_pcie_1_pipe_clk", &gcc, 237 }, - { "gcc_pcie_phy_aux_clk", &gcc, 239 }, - { "gcc_ufs_card_axi_clk", &gcc, 240 }, - { "gcc_ufs_card_ahb_clk", &gcc, 241 }, - { "gcc_ufs_card_tx_symbol_0_clk", &gcc, 242 }, - { "gcc_ufs_card_rx_symbol_0_clk", &gcc, 243 }, - { "gcc_ufs_card_unipro_core_clk", &gcc, 246 }, - { "gcc_ufs_card_ice_core_clk", &gcc, 247 }, - { "gcc_ufs_card_phy_aux_clk", &gcc, 248 }, - { "gcc_ufs_card_rx_symbol_1_clk", &gcc, 249 }, - { "gcc_ufs_phy_axi_clk", &gcc, 251 }, - { "gcc_ufs_phy_ahb_clk", &gcc, 252 }, - { "gcc_ufs_phy_tx_symbol_0_clk", &gcc, 253 }, - { "gcc_ufs_phy_rx_symbol_0_clk", &gcc, 254 }, - { "gcc_ufs_phy_unipro_core_clk", &gcc, 257 }, - { "gcc_ufs_phy_ice_core_clk", &gcc, 258 }, - { "gcc_ufs_phy_phy_aux_clk", &gcc, 259 }, - { "gcc_ufs_phy_rx_symbol_1_clk", &gcc, 260 }, - { "gcc_vddcx_vs_clk", &gcc, 268 }, - { "gcc_vddmx_vs_clk", &gcc, 269 }, - { "gcc_vdda_vs_clk", &gcc, 270 }, - { "gcc_vs_ctrl_clk", &gcc, 271 }, - { "gcc_vs_ctrl_ahb_clk", &gcc, 272 }, - { "gcc_mss_vs_clk", &gcc, 273 }, - { "gcc_gpu_vs_clk", &gcc, 274 }, - { "gcc_apc_vs_clk", &gcc, 275 }, - { "gcc_aggre_usb3_prim_axi_clk", &gcc, 283 }, - { "gcc_aggre_usb3_sec_axi_clk", &gcc, 284 }, - { "gcc_aggre_ufs_phy_axi_clk", &gcc, 285 }, - { "gcc_aggre_ufs_card_axi_clk", &gcc, 286 }, - { "measure_only_ipa_2x_clk", &gcc, 296 }, - { "gcc_mss_cfg_ahb_clk", &gcc, 301 }, - { "gcc_mss_mfab_axis_clk", &gcc, 302 }, - { "gcc_mss_axis2_clk", &gcc, 303 }, - { "gcc_mss_gpll0_div_clk_src", &gcc, 307 }, - { "gcc_mss_snoc_axi_clk", &gcc, 308 }, - { "gcc_mss_q6_memnoc_axi_clk", &gcc, 309 }, - { "gcc_gpu_cfg_ahb_clk", &gcc, 322 }, - { "gpu_cc_cxo_clk", &gcc, 324, &gpu_cc, 10 }, - { "gpu_cc_cxo_aon_clk", &gcc, 324, &gpu_cc, 11 }, - { "gpu_cc_gx_gfx3d_clk", &gcc, 324, &gpu_cc, 12 }, - { "gpu_cc_gx_vsense_clk", &gcc, 324, &gpu_cc, 13 }, - { "gpu_cc_gx_qdss_tsctr_clk", &gcc, 324, &gpu_cc, 14 }, - { "gpu_cc_gx_gmu_clk", &gcc, 324, &gpu_cc, 16 }, - { "gpu_cc_crc_ahb_clk", &gcc, 324, &gpu_cc, 18 }, - { "gpu_cc_cx_qdss_at_clk", &gcc, 324, &gpu_cc, 19 }, - { "gpu_cc_cx_qdss_tsctr_clk", &gcc, 324, &gpu_cc, 20 }, - { "gpu_cc_cx_apb_clk", &gcc, 324, &gpu_cc, 21 }, - { "gpu_cc_cx_snoc_dvm_clk", &gcc, 324, &gpu_cc, 22 }, - { "gpu_cc_sleep_clk", &gcc, 324, &gpu_cc, 23 }, - { "gpu_cc_cx_qdss_trig_clk", &gcc, 324, &gpu_cc, 24 }, - { "gpu_cc_cx_gmu_clk", &gcc, 324, &gpu_cc, 25 }, - { "gpu_cc_cx_gfx3d_clk", &gcc, 324, &gpu_cc, 26 }, - { "gpu_cc_cx_gfx3d_slv_clk", &gcc, 324, &gpu_cc, 27 }, - { "gpu_cc_rbcpr_clk", &gcc, 324, &gpu_cc, 28 }, - { "gpu_cc_rbcpr_ahb_clk", &gcc, 324, &gpu_cc, 29 }, - { "gpu_cc_acd_cxo_clk", &gcc, 324, &gpu_cc, 31 }, - { "gcc_gpu_memnoc_gfx_clk", &gcc, 325 }, - { "gcc_gpu_snoc_dvm_gfx_clk", &gcc, 327 }, - { "gcc_gpu_gpll0_clk_src", &gcc, 328 }, - { "gcc_gpu_gpll0_div_clk_src", &gcc, 329 }, - { "gcc_sdcc1_apps_clk", &gcc, 347 }, - { "gcc_sdcc1_ahb_clk", &gcc, 348 }, - { "gcc_sdcc1_ice_core_clk", &gcc, 349 }, - { "gcc_pcie_phy_refgen_clk", &gcc, 352 }, + { "measure_only_snoc_clk", &gcc.mux, 7 }, + { "gcc_sys_noc_cpuss_ahb_clk", &gcc.mux, 12 }, + { "measure_only_cnoc_clk", &gcc.mux, 21 }, + { "gcc_cfg_noc_usb3_prim_axi_clk", &gcc.mux, 29 }, + { "gcc_cfg_noc_usb3_sec_axi_clk", &gcc.mux, 30 }, + { "gcc_aggre_noc_pcie_tbu_clk", &gcc.mux, 45 }, + { "gcc_video_ahb_clk", &gcc.mux, 57 }, + { "gcc_camera_ahb_clk", &gcc.mux, 58 }, + { "gcc_disp_ahb_clk", &gcc.mux, 59 }, + { "gcc_qmip_video_ahb_clk", &gcc.mux, 60 }, + { "gcc_qmip_camera_ahb_clk", &gcc.mux, 61 }, + { "gcc_qmip_disp_ahb_clk", &gcc.mux, 62 }, + { "gcc_video_axi_clk", &gcc.mux, 63 }, + { "gcc_camera_axi_clk", &gcc.mux, 64 }, + { "gcc_disp_axi_clk", &gcc.mux, 65 }, + { "gcc_video_xo_clk", &gcc.mux, 66 }, + { "gcc_camera_xo_clk", &gcc.mux, 67 }, + { "gcc_disp_xo_clk", &gcc.mux, 68 }, + { "cam_cc_mclk0_clk", &cam_cc, 1 }, + { "cam_cc_mclk1_clk", &cam_cc, 2 }, + { "cam_cc_mclk2_clk", &cam_cc, 3 }, + { "cam_cc_mclk3_clk", &cam_cc, 4 }, + { "cam_cc_csi0phytimer_clk", &cam_cc, 5 }, + { "cam_cc_csiphy0_clk", &cam_cc, 6 }, + { "cam_cc_csi1phytimer_clk", &cam_cc, 7 }, + { "cam_cc_csiphy1_clk", &cam_cc, 8 }, + { "cam_cc_csi2phytimer_clk", &cam_cc, 9 }, + { "cam_cc_csiphy2_clk", &cam_cc, 10 }, + { "cam_cc_bps_clk", &cam_cc, 11 }, + { "cam_cc_bps_axi_clk", &cam_cc, 12 }, + { "cam_cc_bps_areg_clk", &cam_cc, 13 }, + { "cam_cc_bps_ahb_clk", &cam_cc, 14 }, + { "cam_cc_ipe_0_clk", &cam_cc, 15 }, + { "cam_cc_ipe_0_axi_clk", &cam_cc, 16 }, + { "cam_cc_ipe_0_areg_clk", &cam_cc, 17 }, + { "cam_cc_ipe_0_ahb_clk", &cam_cc, 18 }, + { "cam_cc_ipe_1_clk", &cam_cc, 19 }, + { "cam_cc_ipe_1_axi_clk", &cam_cc, 20 }, + { "cam_cc_ipe_1_areg_clk", &cam_cc, 21 }, + { "cam_cc_ipe_1_ahb_clk", &cam_cc, 22 }, + { "cam_cc_ife_0_clk", &cam_cc, 23 }, + { "cam_cc_ife_0_dsp_clk", &cam_cc, 24 }, + { "cam_cc_ife_0_csid_clk", &cam_cc, 25 }, + { "cam_cc_ife_0_cphy_rx_clk", &cam_cc, 26 }, + { "cam_cc_ife_0_axi_clk", &cam_cc, 27 }, + { "cam_cc_ife_1_clk", &cam_cc, 29 }, + { "cam_cc_ife_1_dsp_clk", &cam_cc, 30 }, + { "cam_cc_ife_1_csid_clk", &cam_cc, 31 }, + { "cam_cc_ife_1_cphy_rx_clk", &cam_cc, 32 }, + { "cam_cc_ife_1_axi_clk", &cam_cc, 33 }, + { "cam_cc_ife_lite_clk", &cam_cc, 34 }, + { "cam_cc_ife_lite_csid_clk", &cam_cc, 35 }, + { "cam_cc_ife_lite_cphy_rx_clk", &cam_cc, 36 }, + { "cam_cc_jpeg_clk", &cam_cc, 37 }, + { "cam_cc_icp_clk", &cam_cc, 38 }, + { "cam_cc_fd_core_clk", &cam_cc, 40 }, + { "cam_cc_fd_core_uar_clk", &cam_cc, 41 }, + { "cam_cc_cci_clk", &cam_cc, 42 }, + { "cam_cc_lrme_clk", &cam_cc, 43 }, + { "cam_cc_cpas_ahb_clk", &cam_cc, 44 }, + { "cam_cc_camnoc_axi_clk", &cam_cc, 45 }, + { "cam_cc_soc_ahb_clk", &cam_cc, 46 }, + { "cam_cc_icp_atb_clk", &cam_cc, 47 }, + { "cam_cc_icp_cti_clk", &cam_cc, 48 }, + { "cam_cc_icp_ts_clk", &cam_cc, 49 }, + { "cam_cc_icp_apb_clk", &cam_cc, 50 }, + { "cam_cc_sys_tmr_clk", &cam_cc, 51 }, + { "cam_cc_camnoc_atb_clk", &cam_cc, 52 }, + { "cam_cc_csiphy3_clk", &cam_cc, 54 }, + { "disp_cc_mdss_pclk0_clk", &disp_cc, 1 }, + { "disp_cc_mdss_pclk1_clk", &disp_cc, 2 }, + { "disp_cc_mdss_mdp_clk", &disp_cc, 3 }, + { "disp_cc_mdss_rot_clk", &disp_cc, 4 }, + { "disp_cc_mdss_mdp_lut_clk", &disp_cc, 5 }, + { "disp_cc_mdss_vsync_clk", &disp_cc, 6 }, + { "disp_cc_mdss_byte0_clk", &disp_cc, 7 }, + { "disp_cc_mdss_byte0_intf_clk", &disp_cc, 8 }, + { "disp_cc_mdss_byte1_clk", &disp_cc, 9 }, + { "disp_cc_mdss_byte1_intf_clk", &disp_cc, 10 }, + { "disp_cc_mdss_esc0_clk", &disp_cc, 11 }, + { "disp_cc_mdss_esc1_clk", &disp_cc, 12 }, + { "disp_cc_mdss_dp_link_clk", &disp_cc, 13 }, + { "disp_cc_mdss_dp_link_intf_clk", &disp_cc, 14 }, + { "disp_cc_mdss_dp_crypto_clk", &disp_cc, 15 }, + { "disp_cc_mdss_dp_pixel_clk", &disp_cc, 16 }, + { "disp_cc_mdss_dp_pixel1_clk", &disp_cc, 17 }, + { "disp_cc_mdss_dp_aux_clk", &disp_cc, 18 }, + { "disp_cc_mdss_ahb_clk", &disp_cc, 19 }, + { "disp_cc_mdss_axi_clk", &disp_cc, 20 }, + { "disp_cc_mdss_qdss_at_clk", &disp_cc, 21 }, + { "disp_cc_mdss_qdss_tsctr_div8_clk", &disp_cc, 22 }, + { "disp_cc_mdss_rscc_ahb_clk", &disp_cc, 23 }, + { "disp_cc_mdss_rscc_vsync_clk", &disp_cc, 24 }, + { "video_cc_venus_ctl_core_clk", &video_cc, 1 }, + { "video_cc_vcodec0_core_clk", &video_cc, 2 }, + { "video_cc_vcodec1_core_clk", &video_cc, 3 }, + { "video_cc_venus_ctl_axi_clk", &video_cc, 4 }, + { "video_cc_vcodec0_axi_clk", &video_cc, 5 }, + { "video_cc_vcodec1_axi_clk", &video_cc, 6 }, + { "video_cc_qdss_trig_clk", &video_cc, 7 }, + { "video_cc_apb_clk", &video_cc, 8 }, + { "video_cc_venus_ahb_clk", &video_cc, 9 }, + { "video_cc_qdss_tsctr_div8_clk", &video_cc, 10 }, + { "video_cc_at_clk", &video_cc, 11 }, + { "gcc_disp_gpll0_clk_src", &gcc.mux, 76 }, + { "gcc_disp_gpll0_div_clk_src", &gcc.mux, 77 }, + { "gcc_usb30_prim_master_clk", &gcc.mux, 95 }, + { "gcc_usb30_prim_sleep_clk", &gcc.mux, 96 }, + { "gcc_usb30_prim_mock_utmi_clk", &gcc.mux, 97 }, + { "gcc_usb3_prim_phy_aux_clk", &gcc.mux, 98 }, + { "gcc_usb3_prim_phy_com_aux_clk", &gcc.mux, 99 }, + { "gcc_usb3_prim_phy_pipe_clk", &gcc.mux, 100 }, + { "gcc_usb30_sec_master_clk", &gcc.mux, 101 }, + { "gcc_usb30_sec_sleep_clk", &gcc.mux, 102 }, + { "gcc_usb30_sec_mock_utmi_clk", &gcc.mux, 103 }, + { "gcc_usb3_sec_phy_aux_clk", &gcc.mux, 104 }, + { "gcc_usb3_sec_phy_com_aux_clk", &gcc.mux, 105 }, + { "gcc_usb3_sec_phy_pipe_clk", &gcc.mux, 106 }, + { "gcc_usb_phy_cfg_ahb2phy_clk", &gcc.mux, 111 }, + { "gcc_sdcc2_apps_clk", &gcc.mux, 112 }, + { "gcc_sdcc2_ahb_clk", &gcc.mux, 113 }, + { "gcc_sdcc4_apps_clk", &gcc.mux, 114 }, + { "gcc_sdcc4_ahb_clk", &gcc.mux, 115 }, + { "gcc_qupv3_wrap_0_m_ahb_clk", &gcc.mux, 116 }, + { "gcc_qupv3_wrap_0_s_ahb_clk", &gcc.mux, 117 }, + { "gcc_qupv3_wrap0_core_clk", &gcc.mux, 118 }, + { "gcc_qupv3_wrap0_core_2x_clk", &gcc.mux, 119 }, + { "gcc_qupv3_wrap0_s0_clk", &gcc.mux, 120 }, + { "gcc_qupv3_wrap0_s1_clk", &gcc.mux, 121 }, + { "gcc_qupv3_wrap0_s2_clk", &gcc.mux, 122 }, + { "gcc_qupv3_wrap0_s3_clk", &gcc.mux, 123 }, + { "gcc_qupv3_wrap0_s4_clk", &gcc.mux, 124 }, + { "gcc_qupv3_wrap0_s5_clk", &gcc.mux, 125 }, + { "gcc_qupv3_wrap0_s6_clk", &gcc.mux, 126 }, + { "gcc_qupv3_wrap0_s7_clk", &gcc.mux, 127 }, + { "gcc_qupv3_wrap1_core_2x_clk", &gcc.mux, 128 }, + { "gcc_qupv3_wrap1_core_clk", &gcc.mux, 129 }, + { "gcc_qupv3_wrap_1_m_ahb_clk", &gcc.mux, 130 }, + { "gcc_qupv3_wrap_1_s_ahb_clk", &gcc.mux, 131 }, + { "gcc_qupv3_wrap1_s0_clk", &gcc.mux, 132 }, + { "gcc_qupv3_wrap1_s1_clk", &gcc.mux, 133 }, + { "gcc_qupv3_wrap1_s2_clk", &gcc.mux, 134 }, + { "gcc_qupv3_wrap1_s3_clk", &gcc.mux, 135 }, + { "gcc_qupv3_wrap1_s4_clk", &gcc.mux, 136 }, + { "gcc_qupv3_wrap1_s5_clk", &gcc.mux, 137 }, + { "gcc_qupv3_wrap1_s6_clk", &gcc.mux, 138 }, + { "gcc_qupv3_wrap1_s7_clk", &gcc.mux, 139 }, + { "gcc_pdm_ahb_clk", &gcc.mux, 140 }, + { "gcc_pdm_xo4_clk", &gcc.mux, 141 }, + { "gcc_pdm2_clk", &gcc.mux, 142 }, + { "gcc_prng_ahb_clk", &gcc.mux, 143 }, + { "gcc_tsif_ahb_clk", &gcc.mux, 144 }, + { "gcc_tsif_ref_clk", &gcc.mux, 145 }, + { "gcc_tsif_inactivity_timers_clk", &gcc.mux, 146 }, + { "gcc_boot_rom_ahb_clk", &gcc.mux, 148 }, + { "gcc_ce1_clk", &gcc.mux, 167 }, + { "gcc_ce1_axi_clk", &gcc.mux, 168 }, + { "gcc_ce1_ahb_clk", &gcc.mux, 169 }, + { "gcc_ddrss_gpu_axi_clk", &gcc.mux, 187 }, + { "measure_only_bimc_clk", &gcc.mux, 194 }, + { "gcc_cpuss_ahb_clk", &gcc.mux, 206 }, + { "gcc_cpuss_gnoc_clk", &gcc.mux, 207 }, + { "gcc_cpuss_rbcpr_clk", &gcc.mux, 208 }, + { "gcc_cpuss_dvm_bus_clk", &gcc.mux, 211 }, + { "pwrcl_clk", &cpu, 68, 16 }, + { "perfcl_clk", &cpu, 69, 16 }, + { "l3_clk", &cpu, 70, 16 }, + { "gcc_gp1_clk", &gcc.mux, 222 }, + { "gcc_gp2_clk", &gcc.mux, 223 }, + { "gcc_gp3_clk", &gcc.mux, 224 }, + { "gcc_pcie_0_slv_q2a_axi_clk", &gcc.mux, 225 }, + { "gcc_pcie_0_slv_axi_clk", &gcc.mux, 226 }, + { "gcc_pcie_0_mstr_axi_clk", &gcc.mux, 227 }, + { "gcc_pcie_0_cfg_ahb_clk", &gcc.mux, 228 }, + { "gcc_pcie_0_aux_clk", &gcc.mux, 229 }, + { "gcc_pcie_0_pipe_clk", &gcc.mux, 230 }, + { "gcc_pcie_1_slv_q2a_axi_clk", &gcc.mux, 232 }, + { "gcc_pcie_1_slv_axi_clk", &gcc.mux, 233 }, + { "gcc_pcie_1_mstr_axi_clk", &gcc.mux, 234 }, + { "gcc_pcie_1_cfg_ahb_clk", &gcc.mux, 235 }, + { "gcc_pcie_1_aux_clk", &gcc.mux, 236 }, + { "gcc_pcie_1_pipe_clk", &gcc.mux, 237 }, + { "gcc_pcie_phy_aux_clk", &gcc.mux, 239 }, + { "gcc_ufs_card_axi_clk", &gcc.mux, 240 }, + { "gcc_ufs_card_ahb_clk", &gcc.mux, 241 }, + { "gcc_ufs_card_tx_symbol_0_clk", &gcc.mux, 242 }, + { "gcc_ufs_card_rx_symbol_0_clk", &gcc.mux, 243 }, + { "gcc_ufs_card_unipro_core_clk", &gcc.mux, 246 }, + { "gcc_ufs_card_ice_core_clk", &gcc.mux, 247 }, + { "gcc_ufs_card_phy_aux_clk", &gcc.mux, 248 }, + { "gcc_ufs_card_rx_symbol_1_clk", &gcc.mux, 249 }, + { "gcc_ufs_phy_axi_clk", &gcc.mux, 251 }, + { "gcc_ufs_phy_ahb_clk", &gcc.mux, 252 }, + { "gcc_ufs_phy_tx_symbol_0_clk", &gcc.mux, 253 }, + { "gcc_ufs_phy_rx_symbol_0_clk", &gcc.mux, 254 }, + { "gcc_ufs_phy_unipro_core_clk", &gcc.mux, 257 }, + { "gcc_ufs_phy_ice_core_clk", &gcc.mux, 258 }, + { "gcc_ufs_phy_phy_aux_clk", &gcc.mux, 259 }, + { "gcc_ufs_phy_rx_symbol_1_clk", &gcc.mux, 260 }, + { "gcc_vddcx_vs_clk", &gcc.mux, 268 }, + { "gcc_vddmx_vs_clk", &gcc.mux, 269 }, + { "gcc_vdda_vs_clk", &gcc.mux, 270 }, + { "gcc_vs_ctrl_clk", &gcc.mux, 271 }, + { "gcc_vs_ctrl_ahb_clk", &gcc.mux, 272 }, + { "gcc_mss_vs_clk", &gcc.mux, 273 }, + { "gcc_gpu_vs_clk", &gcc.mux, 274 }, + { "gcc_apc_vs_clk", &gcc.mux, 275 }, + { "gcc_aggre_usb3_prim_axi_clk", &gcc.mux, 283 }, + { "gcc_aggre_usb3_sec_axi_clk", &gcc.mux, 284 }, + { "gcc_aggre_ufs_phy_axi_clk", &gcc.mux, 285 }, + { "gcc_aggre_ufs_card_axi_clk", &gcc.mux, 286 }, + { "measure_only_ipa_2x_clk", &gcc.mux, 296 }, + { "gcc_mss_cfg_ahb_clk", &gcc.mux, 301 }, + { "gcc_mss_mfab_axis_clk", &gcc.mux, 302 }, + { "gcc_mss_axis2_clk", &gcc.mux, 303 }, + { "gcc_mss_gpll0_div_clk_src", &gcc.mux, 307 }, + { "gcc_mss_snoc_axi_clk", &gcc.mux, 308 }, + { "gcc_mss_q6_memnoc_axi_clk", &gcc.mux, 309 }, + { "gcc_gpu_cfg_ahb_clk", &gcc.mux, 322 }, + { "gpu_cc_cxo_clk", &gpu_cc, 10 }, + { "gpu_cc_cxo_aon_clk", &gpu_cc, 11 }, + { "gpu_cc_gx_gfx3d_clk", &gpu_cc, 12 }, + { "gpu_cc_gx_vsense_clk", &gpu_cc, 13 }, + { "gpu_cc_gx_qdss_tsctr_clk", &gpu_cc, 14 }, + { "gpu_cc_gx_gmu_clk", &gpu_cc, 16 }, + { "gpu_cc_crc_ahb_clk", &gpu_cc, 18 }, + { "gpu_cc_cx_qdss_at_clk", &gpu_cc, 19 }, + { "gpu_cc_cx_qdss_tsctr_clk", &gpu_cc, 20 }, + { "gpu_cc_cx_apb_clk", &gpu_cc, 21 }, + { "gpu_cc_cx_snoc_dvm_clk", &gpu_cc, 22 }, + { "gpu_cc_sleep_clk", &gpu_cc, 23 }, + { "gpu_cc_cx_qdss_trig_clk", &gpu_cc, 24 }, + { "gpu_cc_cx_gmu_clk", &gpu_cc, 25 }, + { "gpu_cc_cx_gfx3d_clk", &gpu_cc, 26 }, + { "gpu_cc_cx_gfx3d_slv_clk", &gpu_cc, 27 }, + { "gpu_cc_rbcpr_clk", &gpu_cc, 28 }, + { "gpu_cc_rbcpr_ahb_clk", &gpu_cc, 29 }, + { "gpu_cc_acd_cxo_clk", &gpu_cc, 31 }, + { "gcc_gpu_memnoc_gfx_clk", &gcc.mux, 325 }, + { "gcc_gpu_snoc_dvm_gfx_clk", &gcc.mux, 327 }, + { "gcc_gpu_gpll0_clk_src", &gcc.mux, 328 }, + { "gcc_gpu_gpll0_div_clk_src", &gcc.mux, 329 }, + { "gcc_sdcc1_apps_clk", &gcc.mux, 347 }, + { "gcc_sdcc1_ahb_clk", &gcc.mux, 348 }, + { "gcc_sdcc1_ice_core_clk", &gcc.mux, 349 }, + { "gcc_pcie_phy_refgen_clk", &gcc.mux, 352 }, {} }; diff --git a/sm6115.c b/sm6115.c index d796ae3..09659d6 100644 --- a/sm6115.c +++ b/sm6115.c @@ -12,11 +12,38 @@ #include "debugcc.h" +static struct gcc_mux gcc = { + .mux = { + .phys = 0x1400000, + .size = 0x1f0000, + + .measure = measure_gcc, + + .enable_reg = 0x30004, + .enable_mask = BIT(0), + + .mux_reg = 0x62000, + .mux_mask = 0x3ff, + + .div_reg = 0x30000, + .div_mask = 0xf, + .div_val = 4, + }, + + .xo_div4_reg = 0x28008, + .debug_ctl_reg = 0x62038, + .debug_status_reg = 0x6203c, +}; + static struct debug_mux cpu_cc = { .phys = 0xf111000, .size = 0x1000, .block_name = "cpu", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0xaf, + .enable_reg = 0x1c, .enable_mask = BIT(0), @@ -34,6 +61,10 @@ static struct debug_mux disp_cc = { .size = 0x20000, .block_name = "disp", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x42, + .enable_reg = 0x500c, .enable_mask = BIT(0), @@ -45,30 +76,15 @@ static struct debug_mux disp_cc = { .div_val = 4, }; -static struct debug_mux gcc = { - .phys = 0x1400000, - .size = 0x1f0000, - - .enable_reg = 0x30004, - .enable_mask = BIT(0), - - .mux_reg = 0x62000, - .mux_mask = 0x3ff, - - .div_reg = 0x30000, - .div_mask = 0xf, - .div_val = 4, - - .xo_div4_reg = 0x28008, - .debug_ctl_reg = 0x62038, - .debug_status_reg = 0x6203c, -}; - static struct debug_mux gpu_cc = { .phys = 0x5990000, .size = 0x9000, .block_name = "gpu", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0xe7, + .enable_reg = 0x1100, .enable_mask = BIT(0), @@ -81,131 +97,128 @@ static struct debug_mux gpu_cc = { }; static struct measure_clk sm6115_clocks[] = { - { "perfcl_clk", &gcc, 0xaf, &cpu_cc, 0x1 }, - { "pwrcl_clk", &gcc, 0xaf, &cpu_cc, 0x0 }, - //{ "cpu_cc_debug_mux", &gcc, 0xaf }, - //{ "disp_cc_debug_mux", &gcc, 0x42 }, - { "gcc_ahb2phy_csi_clk", &gcc, 0x63 }, - { "gcc_ahb2phy_usb_clk", &gcc, 0x64 }, - { "gcc_bimc_gpu_axi_clk", &gcc, 0x90 }, - { "gcc_boot_rom_ahb_clk", &gcc, 0x76 }, - { "gcc_cam_throttle_nrt_clk", &gcc, 0x4c }, - { "gcc_cam_throttle_rt_clk", &gcc, 0x4b }, - { "gcc_camera_ahb_clk", &gcc, 0x37 }, - { "gcc_camera_xo_clk", &gcc, 0x3f }, - { "gcc_camss_axi_clk", &gcc, 0x136 }, - { "gcc_camss_camnoc_atb_clk", &gcc, 0x138 }, - { "gcc_camss_camnoc_nts_xo_clk", &gcc, 0x139 }, - { "gcc_camss_cci_0_clk", &gcc, 0x134 }, - { "gcc_camss_cphy_0_clk", &gcc, 0x128 }, - { "gcc_camss_cphy_1_clk", &gcc, 0x129 }, - { "gcc_camss_cphy_2_clk", &gcc, 0x12a }, - { "gcc_camss_csi0phytimer_clk", &gcc, 0x11a }, - { "gcc_camss_csi1phytimer_clk", &gcc, 0x11b }, - { "gcc_camss_csi2phytimer_clk", &gcc, 0x11c }, - { "gcc_camss_mclk0_clk", &gcc, 0x11d }, - { "gcc_camss_mclk1_clk", &gcc, 0x11e }, - { "gcc_camss_mclk2_clk", &gcc, 0x11f }, - { "gcc_camss_mclk3_clk", &gcc, 0x120 }, - { "gcc_camss_nrt_axi_clk", &gcc, 0x13a }, - { "gcc_camss_ope_ahb_clk", &gcc, 0x133 }, - { "gcc_camss_ope_clk", &gcc, 0x131 }, - { "gcc_camss_rt_axi_clk", &gcc, 0x13c }, - { "gcc_camss_tfe_0_clk", &gcc, 0x121 }, - { "gcc_camss_tfe_0_cphy_rx_clk", &gcc, 0x125 }, - { "gcc_camss_tfe_0_csid_clk", &gcc, 0x12b }, - { "gcc_camss_tfe_1_clk", &gcc, 0x122 }, - { "gcc_camss_tfe_1_cphy_rx_clk", &gcc, 0x126 }, - { "gcc_camss_tfe_1_csid_clk", &gcc, 0x12d }, - { "gcc_camss_tfe_2_clk", &gcc, 0x123 }, - { "gcc_camss_tfe_2_cphy_rx_clk", &gcc, 0x127 }, - { "gcc_camss_tfe_2_csid_clk", &gcc, 0x12f }, - { "gcc_camss_top_ahb_clk", &gcc, 0x135 }, - { "gcc_cfg_noc_usb3_prim_axi_clk", &gcc, 0x1d }, - { "gcc_cpuss_gnoc_clk", &gcc, 0xaa }, - { "gcc_disp_ahb_clk", &gcc, 0x38 }, - { "gcc_disp_gpll0_div_clk_src", &gcc, 0x47 }, - { "gcc_disp_hf_axi_clk", &gcc, 0x3d }, - { "gcc_disp_throttle_core_clk", &gcc, 0x49 }, - { "gcc_disp_xo_clk", &gcc, 0x40 }, - { "gcc_gp1_clk", &gcc, 0xba }, - { "gcc_gp2_clk", &gcc, 0xbb }, - { "gcc_gp3_clk", &gcc, 0xbc }, - { "gcc_gpu_cfg_ahb_clk", &gcc, 0xe5 }, - { "gcc_gpu_gpll0_clk_src", &gcc, 0xeb }, - { "gcc_gpu_gpll0_div_clk_src", &gcc, 0xec }, - { "gcc_gpu_memnoc_gfx_clk", &gcc, 0xe8 }, - { "gcc_gpu_snoc_dvm_gfx_clk", &gcc, 0xea }, - { "gcc_gpu_throttle_core_clk", &gcc, 0xef }, - { "gcc_pdm2_clk", &gcc, 0x73 }, - { "gcc_pdm_ahb_clk", &gcc, 0x71 }, - { "gcc_pdm_xo4_clk", &gcc, 0x72 }, - { "gcc_prng_ahb_clk", &gcc, 0x74 }, - { "gcc_qmip_camera_nrt_ahb_clk", &gcc, 0x3a }, - { "gcc_qmip_camera_rt_ahb_clk", &gcc, 0x48 }, - { "gcc_qmip_disp_ahb_clk", &gcc, 0x3b }, - { "gcc_qmip_gpu_cfg_ahb_clk", &gcc, 0xed }, - { "gcc_qmip_video_vcodec_ahb_clk", &gcc, 0x39 }, - { "gcc_qupv3_wrap0_core_2x_clk", &gcc, 0x6a }, - { "gcc_qupv3_wrap0_core_clk", &gcc, 0x69 }, - { "gcc_qupv3_wrap_0_m_ahb_clk", &gcc, 0x67 }, - { "gcc_qupv3_wrap_0_s_ahb_clk", &gcc, 0x68 }, - { "gcc_sdcc1_ahb_clk", &gcc, 0xf3 }, - { "gcc_sdcc1_apps_clk", &gcc, 0xf2 }, - { "gcc_sdcc1_ice_core_clk", &gcc, 0xf4 }, - { "gcc_sdcc2_ahb_clk", &gcc, 0x66 }, - { "gcc_sdcc2_apps_clk", &gcc, 0x65 }, - { "gcc_sys_noc_cpuss_ahb_clk", &gcc, 0x9 }, - { "gcc_sys_noc_ufs_phy_axi_clk", &gcc, 0x19 }, - { "gcc_sys_noc_usb3_prim_axi_clk", &gcc, 0x18 }, - { "gcc_ufs_phy_ahb_clk", &gcc, 0x111 }, - { "gcc_ufs_phy_axi_clk", &gcc, 0x110 }, - { "gcc_ufs_phy_ice_core_clk", &gcc, 0x117 }, - { "gcc_ufs_phy_phy_aux_clk", &gcc, 0x118 }, - { "gcc_ufs_phy_rx_symbol_0_clk", &gcc, 0x113 }, - { "gcc_ufs_phy_tx_symbol_0_clk", &gcc, 0x112 }, - { "gcc_ufs_phy_unipro_core_clk", &gcc, 0x116 }, - { "gcc_usb30_prim_master_clk", &gcc, 0x5c }, - { "gcc_usb30_prim_mock_utmi_clk", &gcc, 0x5e }, - { "gcc_usb30_prim_sleep_clk", &gcc, 0x5d }, - { "gcc_usb3_prim_phy_com_aux_clk", &gcc, 0x5f }, - { "gcc_usb3_prim_phy_pipe_clk", &gcc, 0x60 }, - { "gcc_vcodec0_axi_clk", &gcc, 0x142 }, - { "gcc_venus_ahb_clk", &gcc, 0x143 }, - { "gcc_venus_ctl_axi_clk", &gcc, 0x141 }, - { "gcc_video_ahb_clk", &gcc, 0x36 }, - { "gcc_video_axi0_clk", &gcc, 0x3c }, - { "gcc_video_throttle_core_clk", &gcc, 0x4a }, - { "gcc_video_vcodec0_sys_clk", &gcc, 0x13f }, - { "gcc_video_venus_ctl_clk", &gcc, 0x13d }, - { "gcc_video_xo_clk", &gcc, 0x3e }, - //{ "gpu_cc_debug_mux", &gcc, 0xe7 }, - //{ "mc_cc_debug_mux", &gcc, 0x9e }, - { "measure_only_cnoc_clk", &gcc, 0x1a }, - { "measure_only_ipa_2x_clk", &gcc, 0xc6 }, - { "measure_only_snoc_clk", &gcc, 0x7 }, - { "disp_cc_mdss_ahb_clk", &gcc, 0x42, &disp_cc, 0x1a }, - { "disp_cc_mdss_byte0_clk", &gcc, 0x42, &disp_cc, 0x12 }, - { "disp_cc_mdss_byte0_intf_clk", &gcc, 0x42, &disp_cc, 0x13 }, - { "disp_cc_mdss_esc0_clk", &gcc, 0x42, &disp_cc, 0x14 }, - { "disp_cc_mdss_mdp_clk", &gcc, 0x42, &disp_cc, 0xe }, - { "disp_cc_mdss_mdp_lut_clk", &gcc, 0x42, &disp_cc, 0x10 }, - { "disp_cc_mdss_non_gdsc_ahb_clk", &gcc, 0x42, &disp_cc, 0x1b }, - { "disp_cc_mdss_pclk0_clk", &gcc, 0x42, &disp_cc, 0xd }, - { "disp_cc_mdss_rot_clk", &gcc, 0x42, &disp_cc, 0xf }, - { "disp_cc_mdss_vsync_clk", &gcc, 0x42, &disp_cc, 0x11 }, - { "disp_cc_sleep_clk", &gcc, 0x42, &disp_cc, 0x24 }, - { "disp_cc_xo_clk", &gcc, 0x42, &disp_cc, 0x23 }, - { "gpu_cc_ahb_clk", &gcc, 0xe7, &gpu_cc, 0x10 }, - { "gpu_cc_crc_ahb_clk", &gcc, 0xe7, &gpu_cc, 0x11 }, - { "gpu_cc_cx_gfx3d_clk", &gcc, 0xe7, &gpu_cc, 0x1a }, - { "gpu_cc_cx_gmu_clk", &gcc, 0xe7, &gpu_cc, 0x18 }, - { "gpu_cc_cx_snoc_dvm_clk", &gcc, 0xe7, &gpu_cc, 0x15 }, - { "gpu_cc_cxo_aon_clk", &gcc, 0xe7, &gpu_cc, 0xa }, - { "gpu_cc_cxo_clk", &gcc, 0xe7, &gpu_cc, 0x19 }, - { "gpu_cc_gx_cxo_clk", &gcc, 0xe7, &gpu_cc, 0xe }, - { "gpu_cc_gx_gfx3d_clk", &gcc, 0xe7, &gpu_cc, 0xb }, - { "gpu_cc_sleep_clk", &gcc, 0xe7, &gpu_cc, 0x16 }, + //{ "mc_cc_debug_mux", &gcc.mux, 0x9e }, + { "perfcl_clk", &cpu_cc, 0x1 }, + { "pwrcl_clk", &cpu_cc, 0x0 }, + { "gcc_ahb2phy_csi_clk", &gcc.mux, 0x63 }, + { "gcc_ahb2phy_usb_clk", &gcc.mux, 0x64 }, + { "gcc_bimc_gpu_axi_clk", &gcc.mux, 0x90 }, + { "gcc_boot_rom_ahb_clk", &gcc.mux, 0x76 }, + { "gcc_cam_throttle_nrt_clk", &gcc.mux, 0x4c }, + { "gcc_cam_throttle_rt_clk", &gcc.mux, 0x4b }, + { "gcc_camera_ahb_clk", &gcc.mux, 0x37 }, + { "gcc_camera_xo_clk", &gcc.mux, 0x3f }, + { "gcc_camss_axi_clk", &gcc.mux, 0x136 }, + { "gcc_camss_camnoc_atb_clk", &gcc.mux, 0x138 }, + { "gcc_camss_camnoc_nts_xo_clk", &gcc.mux, 0x139 }, + { "gcc_camss_cci_0_clk", &gcc.mux, 0x134 }, + { "gcc_camss_cphy_0_clk", &gcc.mux, 0x128 }, + { "gcc_camss_cphy_1_clk", &gcc.mux, 0x129 }, + { "gcc_camss_cphy_2_clk", &gcc.mux, 0x12a }, + { "gcc_camss_csi0phytimer_clk", &gcc.mux, 0x11a }, + { "gcc_camss_csi1phytimer_clk", &gcc.mux, 0x11b }, + { "gcc_camss_csi2phytimer_clk", &gcc.mux, 0x11c }, + { "gcc_camss_mclk0_clk", &gcc.mux, 0x11d }, + { "gcc_camss_mclk1_clk", &gcc.mux, 0x11e }, + { "gcc_camss_mclk2_clk", &gcc.mux, 0x11f }, + { "gcc_camss_mclk3_clk", &gcc.mux, 0x120 }, + { "gcc_camss_nrt_axi_clk", &gcc.mux, 0x13a }, + { "gcc_camss_ope_ahb_clk", &gcc.mux, 0x133 }, + { "gcc_camss_ope_clk", &gcc.mux, 0x131 }, + { "gcc_camss_rt_axi_clk", &gcc.mux, 0x13c }, + { "gcc_camss_tfe_0_clk", &gcc.mux, 0x121 }, + { "gcc_camss_tfe_0_cphy_rx_clk", &gcc.mux, 0x125 }, + { "gcc_camss_tfe_0_csid_clk", &gcc.mux, 0x12b }, + { "gcc_camss_tfe_1_clk", &gcc.mux, 0x122 }, + { "gcc_camss_tfe_1_cphy_rx_clk", &gcc.mux, 0x126 }, + { "gcc_camss_tfe_1_csid_clk", &gcc.mux, 0x12d }, + { "gcc_camss_tfe_2_clk", &gcc.mux, 0x123 }, + { "gcc_camss_tfe_2_cphy_rx_clk", &gcc.mux, 0x127 }, + { "gcc_camss_tfe_2_csid_clk", &gcc.mux, 0x12f }, + { "gcc_camss_top_ahb_clk", &gcc.mux, 0x135 }, + { "gcc_cfg_noc_usb3_prim_axi_clk", &gcc.mux, 0x1d }, + { "gcc_cpuss_gnoc_clk", &gcc.mux, 0xaa }, + { "gcc_disp_ahb_clk", &gcc.mux, 0x38 }, + { "gcc_disp_gpll0_div_clk_src", &gcc.mux, 0x47 }, + { "gcc_disp_hf_axi_clk", &gcc.mux, 0x3d }, + { "gcc_disp_throttle_core_clk", &gcc.mux, 0x49 }, + { "gcc_disp_xo_clk", &gcc.mux, 0x40 }, + { "gcc_gp1_clk", &gcc.mux, 0xba }, + { "gcc_gp2_clk", &gcc.mux, 0xbb }, + { "gcc_gp3_clk", &gcc.mux, 0xbc }, + { "gcc_gpu_cfg_ahb_clk", &gcc.mux, 0xe5 }, + { "gcc_gpu_gpll0_clk_src", &gcc.mux, 0xeb }, + { "gcc_gpu_gpll0_div_clk_src", &gcc.mux, 0xec }, + { "gcc_gpu_memnoc_gfx_clk", &gcc.mux, 0xe8 }, + { "gcc_gpu_snoc_dvm_gfx_clk", &gcc.mux, 0xea }, + { "gcc_gpu_throttle_core_clk", &gcc.mux, 0xef }, + { "gcc_pdm2_clk", &gcc.mux, 0x73 }, + { "gcc_pdm_ahb_clk", &gcc.mux, 0x71 }, + { "gcc_pdm_xo4_clk", &gcc.mux, 0x72 }, + { "gcc_prng_ahb_clk", &gcc.mux, 0x74 }, + { "gcc_qmip_camera_nrt_ahb_clk", &gcc.mux, 0x3a }, + { "gcc_qmip_camera_rt_ahb_clk", &gcc.mux, 0x48 }, + { "gcc_qmip_disp_ahb_clk", &gcc.mux, 0x3b }, + { "gcc_qmip_gpu_cfg_ahb_clk", &gcc.mux, 0xed }, + { "gcc_qmip_video_vcodec_ahb_clk", &gcc.mux, 0x39 }, + { "gcc_qupv3_wrap0_core_2x_clk", &gcc.mux, 0x6a }, + { "gcc_qupv3_wrap0_core_clk", &gcc.mux, 0x69 }, + { "gcc_qupv3_wrap_0_m_ahb_clk", &gcc.mux, 0x67 }, + { "gcc_qupv3_wrap_0_s_ahb_clk", &gcc.mux, 0x68 }, + { "gcc_sdcc1_ahb_clk", &gcc.mux, 0xf3 }, + { "gcc_sdcc1_apps_clk", &gcc.mux, 0xf2 }, + { "gcc_sdcc1_ice_core_clk", &gcc.mux, 0xf4 }, + { "gcc_sdcc2_ahb_clk", &gcc.mux, 0x66 }, + { "gcc_sdcc2_apps_clk", &gcc.mux, 0x65 }, + { "gcc_sys_noc_cpuss_ahb_clk", &gcc.mux, 0x9 }, + { "gcc_sys_noc_ufs_phy_axi_clk", &gcc.mux, 0x19 }, + { "gcc_sys_noc_usb3_prim_axi_clk", &gcc.mux, 0x18 }, + { "gcc_ufs_phy_ahb_clk", &gcc.mux, 0x111 }, + { "gcc_ufs_phy_axi_clk", &gcc.mux, 0x110 }, + { "gcc_ufs_phy_ice_core_clk", &gcc.mux, 0x117 }, + { "gcc_ufs_phy_phy_aux_clk", &gcc.mux, 0x118 }, + { "gcc_ufs_phy_rx_symbol_0_clk", &gcc.mux, 0x113 }, + { "gcc_ufs_phy_tx_symbol_0_clk", &gcc.mux, 0x112 }, + { "gcc_ufs_phy_unipro_core_clk", &gcc.mux, 0x116 }, + { "gcc_usb30_prim_master_clk", &gcc.mux, 0x5c }, + { "gcc_usb30_prim_mock_utmi_clk", &gcc.mux, 0x5e }, + { "gcc_usb30_prim_sleep_clk", &gcc.mux, 0x5d }, + { "gcc_usb3_prim_phy_com_aux_clk", &gcc.mux, 0x5f }, + { "gcc_usb3_prim_phy_pipe_clk", &gcc.mux, 0x60 }, + { "gcc_vcodec0_axi_clk", &gcc.mux, 0x142 }, + { "gcc_venus_ahb_clk", &gcc.mux, 0x143 }, + { "gcc_venus_ctl_axi_clk", &gcc.mux, 0x141 }, + { "gcc_video_ahb_clk", &gcc.mux, 0x36 }, + { "gcc_video_axi0_clk", &gcc.mux, 0x3c }, + { "gcc_video_throttle_core_clk", &gcc.mux, 0x4a }, + { "gcc_video_vcodec0_sys_clk", &gcc.mux, 0x13f }, + { "gcc_video_venus_ctl_clk", &gcc.mux, 0x13d }, + { "gcc_video_xo_clk", &gcc.mux, 0x3e }, + { "measure_only_cnoc_clk", &gcc.mux, 0x1a }, + { "measure_only_ipa_2x_clk", &gcc.mux, 0xc6 }, + { "measure_only_snoc_clk", &gcc.mux, 0x7 }, + { "disp_cc_mdss_ahb_clk", &disp_cc, 0x1a }, + { "disp_cc_mdss_byte0_clk", &disp_cc, 0x12 }, + { "disp_cc_mdss_byte0_intf_clk", &disp_cc, 0x13 }, + { "disp_cc_mdss_esc0_clk", &disp_cc, 0x14 }, + { "disp_cc_mdss_mdp_clk", &disp_cc, 0xe }, + { "disp_cc_mdss_mdp_lut_clk", &disp_cc, 0x10 }, + { "disp_cc_mdss_non_gdsc_ahb_clk", &disp_cc, 0x1b }, + { "disp_cc_mdss_pclk0_clk", &disp_cc, 0xd }, + { "disp_cc_mdss_rot_clk", &disp_cc, 0xf }, + { "disp_cc_mdss_vsync_clk", &disp_cc, 0x11 }, + { "disp_cc_sleep_clk", &disp_cc, 0x24 }, + { "disp_cc_xo_clk", &disp_cc, 0x23 }, + { "gpu_cc_ahb_clk", &gpu_cc, 0x10 }, + { "gpu_cc_crc_ahb_clk", &gpu_cc, 0x11 }, + { "gpu_cc_cx_gfx3d_clk", &gpu_cc, 0x1a }, + { "gpu_cc_cx_gmu_clk", &gpu_cc, 0x18 }, + { "gpu_cc_cx_snoc_dvm_clk", &gpu_cc, 0x15 }, + { "gpu_cc_cxo_aon_clk", &gpu_cc, 0xa }, + { "gpu_cc_cxo_clk", &gpu_cc, 0x19 }, + { "gpu_cc_gx_cxo_clk", &gpu_cc, 0xe }, + { "gpu_cc_gx_gfx3d_clk", &gpu_cc, 0xb }, + { "gpu_cc_sleep_clk", &gpu_cc, 0x16 }, {} }; diff --git a/sm6125.c b/sm6125.c index 19730db..d64af53 100644 --- a/sm6125.c +++ b/sm6125.c @@ -12,11 +12,36 @@ #include "debugcc.h" +static struct gcc_mux gcc = { + .mux = { + .phys = 0x1400000, + .size = 0x1f0000, + + .enable_reg = 0x30004, + .enable_mask = BIT(0), + + .mux_reg = 0x62000, + .mux_mask = 0x3ff, + + .div_reg = 0x30000, + .div_mask = 0xf, + .div_val = 1, + }, + + .xo_div4_reg = 0x28008, + .debug_ctl_reg = 0x62038, + .debug_status_reg = 0x6203c, +}; + static struct debug_mux cpu_cc = { .phys = 0xf111000, .size = 0x1000, .block_name = "cpu", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0xab, + .enable_reg = 0x1c, .enable_mask = BIT(0), @@ -30,30 +55,15 @@ static struct debug_mux cpu_cc = { .div_val = 8, }; -static struct debug_mux gcc = { - .phys = 0x1400000, - .size = 0x1f0000, - - .enable_reg = 0x30004, - .enable_mask = BIT(0), - - .mux_reg = 0x62000, - .mux_mask = 0x3ff, - - .div_reg = 0x30000, - .div_mask = 0xf, - .div_val = 1, - - .xo_div4_reg = 0x28008, - .debug_ctl_reg = 0x62038, - .debug_status_reg = 0x6203c, -}; - static struct debug_mux disp_cc = { .phys = 0x5f00000, .size = 0x20000, .block_name = "disp", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x41, + .enable_reg = 0x500c, .enable_mask = BIT(0), @@ -70,6 +80,10 @@ static struct debug_mux gpu_cc = { .size = 0x9000, .block_name = "gpu", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0xdd, + .enable_reg = 0x1100, .enable_mask = BIT(0), @@ -86,6 +100,10 @@ static struct debug_mux video_cc = { .size = 0x10000, .block_name = "video", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x42, + .enable_reg = 0x1100, .enable_mask = BIT(0), @@ -98,203 +116,203 @@ static struct debug_mux video_cc = { }; static struct measure_clk sm6125_clocks[] = { - { "perfcl_clk", &gcc, 0xab, &cpu_cc, 0x1 }, - { "pwrcl_clk", &gcc, 0xab, &cpu_cc, 0x0 }, - { "snoc_clk", &gcc, 0x7 }, - { "bimc_clk", &gcc, 0x97 }, - { "pnoc_clk", &gcc, 0x11 }, - { "gcc_ahb2phy_csi_clk", &gcc, 0x5f }, - { "gcc_ahb2phy_usb_clk", &gcc, 0x60 }, - { "gcc_apc_vs_clk", &gcc, 0xbf }, - { "gcc_boot_rom_ahb_clk", &gcc, 0x72 }, - { "gcc_camera_ahb_clk", &gcc, 0x36 }, - { "gcc_camera_xo_clk", &gcc, 0x3e }, - { "gcc_camss_cci_ahb_clk", &gcc, 0x11f }, - { "gcc_camss_cci_clk", &gcc, 0x11e }, - { "gcc_camss_cphy_csid0_clk", &gcc, 0x13a }, - { "gcc_camss_cphy_csid1_clk", &gcc, 0x140 }, - { "gcc_camss_cphy_csid2_clk", &gcc, 0x145 }, - { "gcc_camss_cphy_csid3_clk", &gcc, 0x14b }, - { "gcc_camss_cpp_ahb_clk", &gcc, 0x154 }, - { "gcc_camss_cpp_axi_clk", &gcc, 0x156 }, - { "gcc_camss_cpp_clk", &gcc, 0x153 }, - { "gcc_camss_cpp_tsctr_clk", &gcc, 0x158 }, - { "gcc_camss_cpp_vbif_ahb_clk", &gcc, 0x155 }, - { "gcc_camss_csi0_ahb_clk", &gcc, 0x13b }, - { "gcc_camss_csi0_clk", &gcc, 0x139 }, - { "gcc_camss_csi0phytimer_clk", &gcc, 0x120 }, - { "gcc_camss_csi0pix_clk", &gcc, 0x13d }, - { "gcc_camss_csi0rdi_clk", &gcc, 0x13c }, - { "gcc_camss_csi1_ahb_clk", &gcc, 0x141 }, - { "gcc_camss_csi1_clk", &gcc, 0x13f }, - { "gcc_camss_csi1phytimer_clk", &gcc, 0x121 }, - { "gcc_camss_csi1pix_clk", &gcc, 0x143 }, - { "gcc_camss_csi1rdi_clk", &gcc, 0x142 }, - { "gcc_camss_csi2_ahb_clk", &gcc, 0x146 }, - { "gcc_camss_csi2_clk", &gcc, 0x144 }, - { "gcc_camss_csi2phytimer_clk", &gcc, 0x122 }, - { "gcc_camss_csi2pix_clk", &gcc, 0x148 }, - { "gcc_camss_csi2rdi_clk", &gcc, 0x147 }, - { "gcc_camss_csi3_ahb_clk", &gcc, 0x14c }, - { "gcc_camss_csi3_clk", &gcc, 0x14a }, - { "gcc_camss_csi3pix_clk", &gcc, 0x14e }, - { "gcc_camss_csi3rdi_clk", &gcc, 0x14d }, - { "gcc_camss_csi_vfe0_clk", &gcc, 0x12e }, - { "gcc_camss_csi_vfe1_clk", &gcc, 0x12f }, - { "gcc_camss_csiphy0_clk", &gcc, 0x135 }, - { "gcc_camss_csiphy1_clk", &gcc, 0x136 }, - { "gcc_camss_csiphy2_clk", &gcc, 0x137 }, - { "gcc_camss_csiphy3_clk", &gcc, 0x138 }, - { "gcc_camss_gp0_clk", &gcc, 0x118 }, - { "gcc_camss_gp1_clk", &gcc, 0x119 }, - { "gcc_camss_ispif_ahb_clk", &gcc, 0x134 }, - { "gcc_camss_jpeg_ahb_clk", &gcc, 0x124 }, - { "gcc_camss_jpeg_axi_clk", &gcc, 0x125 }, - { "gcc_camss_jpeg_clk", &gcc, 0x123 }, - { "gcc_camss_jpeg_tsctr_clk", &gcc, 0x127 }, - { "gcc_camss_mclk0_clk", &gcc, 0x11a }, - { "gcc_camss_mclk1_clk", &gcc, 0x11b }, - { "gcc_camss_mclk2_clk", &gcc, 0x11c }, - { "gcc_camss_mclk3_clk", &gcc, 0x11d }, - { "gcc_camss_micro_ahb_clk", &gcc, 0x152 }, - { "gcc_camss_throttle_nrt_axi_clk", &gcc, 0x150 }, - { "gcc_camss_throttle_rt_axi_clk", &gcc, 0x151 }, - { "gcc_camss_top_ahb_clk", &gcc, 0x14f }, - { "gcc_camss_vfe0_ahb_clk", &gcc, 0x12a }, - { "gcc_camss_vfe0_clk", &gcc, 0x128 }, - { "gcc_camss_vfe0_stream_clk", &gcc, 0x129 }, - { "gcc_camss_vfe1_ahb_clk", &gcc, 0x12d }, - { "gcc_camss_vfe1_clk", &gcc, 0x12b }, - { "gcc_camss_vfe1_stream_clk", &gcc, 0x12c }, - { "gcc_camss_vfe_tsctr_clk", &gcc, 0x133 }, - { "gcc_camss_vfe_vbif_ahb_clk", &gcc, 0x130 }, - { "gcc_camss_vfe_vbif_axi_clk", &gcc, 0x131 }, - { "gcc_ce1_ahb_clk", &gcc, 0x82 }, - { "gcc_ce1_axi_clk", &gcc, 0x81 }, - { "gcc_ce1_clk", &gcc, 0x80 }, - { "gcc_cfg_noc_usb3_prim_axi_clk", &gcc, 0x1d }, - { "gcc_cpuss_ahb_clk", &gcc, 0xa5 }, - { "gcc_cpuss_gnoc_clk", &gcc, 0xa6 }, - { "gcc_cpuss_throttle_core_clk", &gcc, 0xae }, - { "gcc_cpuss_throttle_xo_clk", &gcc, 0xad }, - { "gcc_disp_ahb_clk", &gcc, 0x37 }, - { "gcc_disp_gpll0_div_clk_src", &gcc, 0x46 }, - { "gcc_disp_hf_axi_clk", &gcc, 0x3c }, - { "gcc_disp_throttle_core_clk", &gcc, 0x48 }, - { "gcc_disp_xo_clk", &gcc, 0x3f }, - { "gcc_gp1_clk", &gcc, 0xb6 }, - { "gcc_gp2_clk", &gcc, 0xb7 }, - { "gcc_gp3_clk", &gcc, 0xb8 }, - { "gcc_gpu_cfg_ahb_clk", &gcc, 0xdb }, - { "gcc_gpu_gpll0_clk_src", &gcc, 0xe1 }, - { "gcc_gpu_gpll0_div_clk_src", &gcc, 0xe2 }, - { "gcc_gpu_memnoc_gfx_clk", &gcc, 0xde }, - { "gcc_gpu_snoc_dvm_gfx_clk", &gcc, 0xe0 }, - { "gcc_gpu_throttle_core_clk", &gcc, 0xe5 }, - { "gcc_gpu_throttle_xo_clk", &gcc, 0xe4 }, - { "gcc_mss_vs_clk", &gcc, 0xbe }, - { "gcc_pdm2_clk", &gcc, 0x6f }, - { "gcc_pdm_ahb_clk", &gcc, 0x6d }, - { "gcc_pdm_xo4_clk", &gcc, 0x6e }, - { "gcc_prng_ahb_clk", &gcc, 0x70 }, - { "gcc_qmip_camera_nrt_ahb_clk", &gcc, 0x39 }, - { "gcc_qmip_camera_rt_ahb_clk", &gcc, 0x47 }, - { "gcc_qmip_cpuss_cfg_ahb_clk", &gcc, 0xac }, - { "gcc_qmip_disp_ahb_clk", &gcc, 0x3a }, - { "gcc_qmip_gpu_cfg_ahb_clk", &gcc, 0xe3 }, - { "gcc_qmip_video_vcodec_ahb_clk", &gcc, 0x38 }, - { "gcc_qupv3_wrap0_core_2x_clk", &gcc, 0x66 }, - { "gcc_qupv3_wrap0_core_clk", &gcc, 0x65 }, - { "gcc_qupv3_wrap0_s0_clk", &gcc, 0x67 }, - { "gcc_qupv3_wrap0_s1_clk", &gcc, 0x68 }, - { "gcc_qupv3_wrap0_s2_clk", &gcc, 0x69 }, - { "gcc_qupv3_wrap0_s3_clk", &gcc, 0x6a }, - { "gcc_qupv3_wrap0_s4_clk", &gcc, 0x6b }, - { "gcc_qupv3_wrap0_s5_clk", &gcc, 0x6c }, - { "gcc_qupv3_wrap1_core_2x_clk", &gcc, 0xed }, - { "gcc_qupv3_wrap1_core_clk", &gcc, 0xec }, - { "gcc_qupv3_wrap1_s0_clk", &gcc, 0xee }, - { "gcc_qupv3_wrap1_s1_clk", &gcc, 0xef }, - { "gcc_qupv3_wrap1_s2_clk", &gcc, 0xf0 }, - { "gcc_qupv3_wrap1_s3_clk", &gcc, 0xf1 }, - { "gcc_qupv3_wrap1_s4_clk", &gcc, 0xf2 }, - { "gcc_qupv3_wrap1_s5_clk", &gcc, 0xf3 }, - { "gcc_qupv3_wrap_0_m_ahb_clk", &gcc, 0x63 }, - { "gcc_qupv3_wrap_0_s_ahb_clk", &gcc, 0x64 }, - { "gcc_qupv3_wrap_1_m_ahb_clk", &gcc, 0xea }, - { "gcc_qupv3_wrap_1_s_ahb_clk", &gcc, 0xeb }, - { "gcc_sdcc1_ahb_clk", &gcc, 0xe8 }, - { "gcc_sdcc1_apps_clk", &gcc, 0xe7 }, - { "gcc_sdcc1_ice_core_clk", &gcc, 0xe9 }, - { "gcc_sdcc2_ahb_clk", &gcc, 0x62 }, - { "gcc_sdcc2_apps_clk", &gcc, 0x61 }, - { "gcc_sys_noc_cpuss_ahb_clk", &gcc, 0x9, }, - { "gcc_sys_noc_ufs_phy_axi_clk", &gcc, 0x19 }, - { "gcc_sys_noc_usb3_prim_axi_clk", &gcc, 0x18 }, - { "gcc_ufs_phy_ahb_clk", &gcc, 0x10f }, - { "gcc_ufs_phy_axi_clk", &gcc, 0x10e }, - { "gcc_ufs_phy_ice_core_clk", &gcc, 0x115 }, - { "gcc_ufs_phy_phy_aux_clk", &gcc, 0x116 }, - { "gcc_ufs_phy_rx_symbol_0_clk", &gcc, 0x111 }, - { "gcc_ufs_phy_tx_symbol_0_clk", &gcc, 0x110 }, - { "gcc_ufs_phy_unipro_core_clk", &gcc, 0x114 }, - { "gcc_usb30_prim_master_clk", &gcc, 0x58 }, - { "gcc_usb30_prim_mock_utmi_clk", &gcc, 0x5a }, - { "gcc_usb30_prim_sleep_clk", &gcc, 0x59 }, - { "gcc_usb3_prim_phy_com_aux_clk", &gcc, 0x5b }, - { "gcc_usb3_prim_phy_pipe_clk", &gcc, 0x5c }, - { "gcc_vdda_vs_clk", &gcc, 0xbb }, - { "gcc_vddcx_vs_clk", &gcc, 0xb9 }, - { "gcc_vddmx_vs_clk", &gcc, 0xba }, - { "gcc_video_ahb_clk", &gcc, 0x35 }, - { "gcc_video_axi0_clk", &gcc, 0x3b }, - { "gcc_video_throttle_core_clk", &gcc, 0x49 }, - { "gcc_video_xo_clk", &gcc, 0x3d }, - { "gcc_vs_ctrl_ahb_clk", &gcc, 0xbd }, - { "gcc_vs_ctrl_clk", &gcc, 0xbc }, - { "gcc_wcss_vs_clk", &gcc, 0xc0 }, - { "measure_only_ipa_2x_clk", &gcc, 0xc2 }, - - { "disp_cc_mdss_ahb_clk", &gcc, 0x41, &disp_cc, 0x1a }, - { "disp_cc_mdss_byte0_clk", &gcc, 0x41, &disp_cc, 0x12 }, - { "disp_cc_mdss_byte0_intf_clk", &gcc, 0x41, &disp_cc, 0x13 }, - { "disp_cc_mdss_dp_aux_clk", &gcc, 0x41, &disp_cc, 0x19 }, - { "disp_cc_mdss_dp_crypto_clk", &gcc, 0x41, &disp_cc, 0x17 }, - { "disp_cc_mdss_dp_link_clk", &gcc, 0x41, &disp_cc, 0x15 }, - { "disp_cc_mdss_dp_link_intf_clk", &gcc, 0x41, &disp_cc, 0x16 }, - { "disp_cc_mdss_dp_pixel_clk", &gcc, 0x41, &disp_cc, 0x18 }, - { "disp_cc_mdss_esc0_clk", &gcc, 0x41, &disp_cc, 0x14 }, - { "disp_cc_mdss_mdp_clk", &gcc, 0x41, &disp_cc, 0xe, }, - { "disp_cc_mdss_mdp_lut_clk", &gcc, 0x41, &disp_cc, 0x10 }, - { "disp_cc_mdss_non_gdsc_ahb_clk", &gcc, 0x41, &disp_cc, 0x1b }, - { "disp_cc_mdss_pclk0_clk", &gcc, 0x41, &disp_cc, 0xd, }, - { "disp_cc_mdss_rot_clk", &gcc, 0x41, &disp_cc, 0xf, }, - { "disp_cc_mdss_vsync_clk", &gcc, 0x41, &disp_cc, 0x11 }, - { "disp_cc_sleep_clk", &gcc, 0x41, &disp_cc, 0x24 }, - { "disp_cc_xo_clk", &gcc, 0x41, &disp_cc, 0x23 }, - - { "gpu_cc_ahb_clk", &gcc, 0xdd, &gpu_cc, 0x10 }, - { "gpu_cc_crc_ahb_clk", &gcc, 0xdd, &gpu_cc, 0x11 }, - { "gpu_cc_cx_apb_clk", &gcc, 0xdd, &gpu_cc, 0x14 }, - { "gpu_cc_cx_gfx3d_clk", &gcc, 0xdd, &gpu_cc, 0x1a }, - { "gpu_cc_cx_gfx3d_slv_clk", &gcc, 0xdd, &gpu_cc, 0x1b }, - { "gpu_cc_cx_gmu_clk", &gcc, 0xdd, &gpu_cc, 0x18 }, - { "gpu_cc_cx_snoc_dvm_clk", &gcc, 0xdd, &gpu_cc, 0x15 }, - { "gpu_cc_cxo_aon_clk", &gcc, 0xdd, &gpu_cc, 0xa }, - { "gpu_cc_cxo_clk", &gcc, 0xdd, &gpu_cc, 0x19 }, - { "gpu_cc_gx_cxo_clk", &gcc, 0xdd, &gpu_cc, 0xe }, - { "gpu_cc_gx_gfx3d_clk", &gcc, 0xdd, &gpu_cc, 0xb }, - { "gpu_cc_sleep_clk", &gcc, 0xdd, &gpu_cc, 0x16 }, - - { "video_cc_apb_clk", &gcc, 0x42, &video_cc, 0x8 }, - { "video_cc_at_clk", &gcc, 0x42, &video_cc, 0xb }, - { "video_cc_sleep_clk", &gcc, 0x42, &video_cc, 0xd }, - { "video_cc_vcodec0_axi_clk", &gcc, 0x42, &video_cc, 0x6 }, - { "video_cc_vcodec0_core_clk", &gcc, 0x42, &video_cc, 0x3 }, - { "video_cc_venus_ahb_clk", &gcc, 0x42, &video_cc, 0x9 }, - { "video_cc_venus_ctl_axi_clk", &gcc, 0x42, &video_cc, 0x5 }, - { "video_cc_venus_ctl_core_clk", &gcc, 0x42, &video_cc, 0x1 }, - { "video_cc_xo_clk", &gcc, 0x42, &video_cc, 0xc }, + { "perfcl_clk", &cpu_cc, 0x1 }, + { "pwrcl_clk", &cpu_cc, 0x0 }, + { "snoc_clk", &gcc.mux, 0x7 }, + { "bimc_clk", &gcc.mux, 0x97 }, + { "pnoc_clk", &gcc.mux, 0x11 }, + { "gcc_ahb2phy_csi_clk", &gcc.mux, 0x5f }, + { "gcc_ahb2phy_usb_clk", &gcc.mux, 0x60 }, + { "gcc_apc_vs_clk", &gcc.mux, 0xbf }, + { "gcc_boot_rom_ahb_clk", &gcc.mux, 0x72 }, + { "gcc_camera_ahb_clk", &gcc.mux, 0x36 }, + { "gcc_camera_xo_clk", &gcc.mux, 0x3e }, + { "gcc_camss_cci_ahb_clk", &gcc.mux, 0x11f }, + { "gcc_camss_cci_clk", &gcc.mux, 0x11e }, + { "gcc_camss_cphy_csid0_clk", &gcc.mux, 0x13a }, + { "gcc_camss_cphy_csid1_clk", &gcc.mux, 0x140 }, + { "gcc_camss_cphy_csid2_clk", &gcc.mux, 0x145 }, + { "gcc_camss_cphy_csid3_clk", &gcc.mux, 0x14b }, + { "gcc_camss_cpp_ahb_clk", &gcc.mux, 0x154 }, + { "gcc_camss_cpp_axi_clk", &gcc.mux, 0x156 }, + { "gcc_camss_cpp_clk", &gcc.mux, 0x153 }, + { "gcc_camss_cpp_tsctr_clk", &gcc.mux, 0x158 }, + { "gcc_camss_cpp_vbif_ahb_clk", &gcc.mux, 0x155 }, + { "gcc_camss_csi0_ahb_clk", &gcc.mux, 0x13b }, + { "gcc_camss_csi0_clk", &gcc.mux, 0x139 }, + { "gcc_camss_csi0phytimer_clk", &gcc.mux, 0x120 }, + { "gcc_camss_csi0pix_clk", &gcc.mux, 0x13d }, + { "gcc_camss_csi0rdi_clk", &gcc.mux, 0x13c }, + { "gcc_camss_csi1_ahb_clk", &gcc.mux, 0x141 }, + { "gcc_camss_csi1_clk", &gcc.mux, 0x13f }, + { "gcc_camss_csi1phytimer_clk", &gcc.mux, 0x121 }, + { "gcc_camss_csi1pix_clk", &gcc.mux, 0x143 }, + { "gcc_camss_csi1rdi_clk", &gcc.mux, 0x142 }, + { "gcc_camss_csi2_ahb_clk", &gcc.mux, 0x146 }, + { "gcc_camss_csi2_clk", &gcc.mux, 0x144 }, + { "gcc_camss_csi2phytimer_clk", &gcc.mux, 0x122 }, + { "gcc_camss_csi2pix_clk", &gcc.mux, 0x148 }, + { "gcc_camss_csi2rdi_clk", &gcc.mux, 0x147 }, + { "gcc_camss_csi3_ahb_clk", &gcc.mux, 0x14c }, + { "gcc_camss_csi3_clk", &gcc.mux, 0x14a }, + { "gcc_camss_csi3pix_clk", &gcc.mux, 0x14e }, + { "gcc_camss_csi3rdi_clk", &gcc.mux, 0x14d }, + { "gcc_camss_csi_vfe0_clk", &gcc.mux, 0x12e }, + { "gcc_camss_csi_vfe1_clk", &gcc.mux, 0x12f }, + { "gcc_camss_csiphy0_clk", &gcc.mux, 0x135 }, + { "gcc_camss_csiphy1_clk", &gcc.mux, 0x136 }, + { "gcc_camss_csiphy2_clk", &gcc.mux, 0x137 }, + { "gcc_camss_csiphy3_clk", &gcc.mux, 0x138 }, + { "gcc_camss_gp0_clk", &gcc.mux, 0x118 }, + { "gcc_camss_gp1_clk", &gcc.mux, 0x119 }, + { "gcc_camss_ispif_ahb_clk", &gcc.mux, 0x134 }, + { "gcc_camss_jpeg_ahb_clk", &gcc.mux, 0x124 }, + { "gcc_camss_jpeg_axi_clk", &gcc.mux, 0x125 }, + { "gcc_camss_jpeg_clk", &gcc.mux, 0x123 }, + { "gcc_camss_jpeg_tsctr_clk", &gcc.mux, 0x127 }, + { "gcc_camss_mclk0_clk", &gcc.mux, 0x11a }, + { "gcc_camss_mclk1_clk", &gcc.mux, 0x11b }, + { "gcc_camss_mclk2_clk", &gcc.mux, 0x11c }, + { "gcc_camss_mclk3_clk", &gcc.mux, 0x11d }, + { "gcc_camss_micro_ahb_clk", &gcc.mux, 0x152 }, + { "gcc_camss_throttle_nrt_axi_clk", &gcc.mux, 0x150 }, + { "gcc_camss_throttle_rt_axi_clk", &gcc.mux, 0x151 }, + { "gcc_camss_top_ahb_clk", &gcc.mux, 0x14f }, + { "gcc_camss_vfe0_ahb_clk", &gcc.mux, 0x12a }, + { "gcc_camss_vfe0_clk", &gcc.mux, 0x128 }, + { "gcc_camss_vfe0_stream_clk", &gcc.mux, 0x129 }, + { "gcc_camss_vfe1_ahb_clk", &gcc.mux, 0x12d }, + { "gcc_camss_vfe1_clk", &gcc.mux, 0x12b }, + { "gcc_camss_vfe1_stream_clk", &gcc.mux, 0x12c }, + { "gcc_camss_vfe_tsctr_clk", &gcc.mux, 0x133 }, + { "gcc_camss_vfe_vbif_ahb_clk", &gcc.mux, 0x130 }, + { "gcc_camss_vfe_vbif_axi_clk", &gcc.mux, 0x131 }, + { "gcc_ce1_ahb_clk", &gcc.mux, 0x82 }, + { "gcc_ce1_axi_clk", &gcc.mux, 0x81 }, + { "gcc_ce1_clk", &gcc.mux, 0x80 }, + { "gcc_cfg_noc_usb3_prim_axi_clk", &gcc.mux, 0x1d }, + { "gcc_cpuss_ahb_clk", &gcc.mux, 0xa5 }, + { "gcc_cpuss_gnoc_clk", &gcc.mux, 0xa6 }, + { "gcc_cpuss_throttle_core_clk", &gcc.mux, 0xae }, + { "gcc_cpuss_throttle_xo_clk", &gcc.mux, 0xad }, + { "gcc_disp_ahb_clk", &gcc.mux, 0x37 }, + { "gcc_disp_gpll0_div_clk_src", &gcc.mux, 0x46 }, + { "gcc_disp_hf_axi_clk", &gcc.mux, 0x3c }, + { "gcc_disp_throttle_core_clk", &gcc.mux, 0x48 }, + { "gcc_disp_xo_clk", &gcc.mux, 0x3f }, + { "gcc_gp1_clk", &gcc.mux, 0xb6 }, + { "gcc_gp2_clk", &gcc.mux, 0xb7 }, + { "gcc_gp3_clk", &gcc.mux, 0xb8 }, + { "gcc_gpu_cfg_ahb_clk", &gcc.mux, 0xdb }, + { "gcc_gpu_gpll0_clk_src", &gcc.mux, 0xe1 }, + { "gcc_gpu_gpll0_div_clk_src", &gcc.mux, 0xe2 }, + { "gcc_gpu_memnoc_gfx_clk", &gcc.mux, 0xde }, + { "gcc_gpu_snoc_dvm_gfx_clk", &gcc.mux, 0xe0 }, + { "gcc_gpu_throttle_core_clk", &gcc.mux, 0xe5 }, + { "gcc_gpu_throttle_xo_clk", &gcc.mux, 0xe4 }, + { "gcc_mss_vs_clk", &gcc.mux, 0xbe }, + { "gcc_pdm2_clk", &gcc.mux, 0x6f }, + { "gcc_pdm_ahb_clk", &gcc.mux, 0x6d }, + { "gcc_pdm_xo4_clk", &gcc.mux, 0x6e }, + { "gcc_prng_ahb_clk", &gcc.mux, 0x70 }, + { "gcc_qmip_camera_nrt_ahb_clk", &gcc.mux, 0x39 }, + { "gcc_qmip_camera_rt_ahb_clk", &gcc.mux, 0x47 }, + { "gcc_qmip_cpuss_cfg_ahb_clk", &gcc.mux, 0xac }, + { "gcc_qmip_disp_ahb_clk", &gcc.mux, 0x3a }, + { "gcc_qmip_gpu_cfg_ahb_clk", &gcc.mux, 0xe3 }, + { "gcc_qmip_video_vcodec_ahb_clk", &gcc.mux, 0x38 }, + { "gcc_qupv3_wrap0_core_2x_clk", &gcc.mux, 0x66 }, + { "gcc_qupv3_wrap0_core_clk", &gcc.mux, 0x65 }, + { "gcc_qupv3_wrap0_s0_clk", &gcc.mux, 0x67 }, + { "gcc_qupv3_wrap0_s1_clk", &gcc.mux, 0x68 }, + { "gcc_qupv3_wrap0_s2_clk", &gcc.mux, 0x69 }, + { "gcc_qupv3_wrap0_s3_clk", &gcc.mux, 0x6a }, + { "gcc_qupv3_wrap0_s4_clk", &gcc.mux, 0x6b }, + { "gcc_qupv3_wrap0_s5_clk", &gcc.mux, 0x6c }, + { "gcc_qupv3_wrap1_core_2x_clk", &gcc.mux, 0xed }, + { "gcc_qupv3_wrap1_core_clk", &gcc.mux, 0xec }, + { "gcc_qupv3_wrap1_s0_clk", &gcc.mux, 0xee }, + { "gcc_qupv3_wrap1_s1_clk", &gcc.mux, 0xef }, + { "gcc_qupv3_wrap1_s2_clk", &gcc.mux, 0xf0 }, + { "gcc_qupv3_wrap1_s3_clk", &gcc.mux, 0xf1 }, + { "gcc_qupv3_wrap1_s4_clk", &gcc.mux, 0xf2 }, + { "gcc_qupv3_wrap1_s5_clk", &gcc.mux, 0xf3 }, + { "gcc_qupv3_wrap_0_m_ahb_clk", &gcc.mux, 0x63 }, + { "gcc_qupv3_wrap_0_s_ahb_clk", &gcc.mux, 0x64 }, + { "gcc_qupv3_wrap_1_m_ahb_clk", &gcc.mux, 0xea }, + { "gcc_qupv3_wrap_1_s_ahb_clk", &gcc.mux, 0xeb }, + { "gcc_sdcc1_ahb_clk", &gcc.mux, 0xe8 }, + { "gcc_sdcc1_apps_clk", &gcc.mux, 0xe7 }, + { "gcc_sdcc1_ice_core_clk", &gcc.mux, 0xe9 }, + { "gcc_sdcc2_ahb_clk", &gcc.mux, 0x62 }, + { "gcc_sdcc2_apps_clk", &gcc.mux, 0x61 }, + { "gcc_sys_noc_cpuss_ahb_clk", &gcc.mux, 0x9, }, + { "gcc_sys_noc_ufs_phy_axi_clk", &gcc.mux, 0x19 }, + { "gcc_sys_noc_usb3_prim_axi_clk", &gcc.mux, 0x18 }, + { "gcc_ufs_phy_ahb_clk", &gcc.mux, 0x10f }, + { "gcc_ufs_phy_axi_clk", &gcc.mux, 0x10e }, + { "gcc_ufs_phy_ice_core_clk", &gcc.mux, 0x115 }, + { "gcc_ufs_phy_phy_aux_clk", &gcc.mux, 0x116 }, + { "gcc_ufs_phy_rx_symbol_0_clk", &gcc.mux, 0x111 }, + { "gcc_ufs_phy_tx_symbol_0_clk", &gcc.mux, 0x110 }, + { "gcc_ufs_phy_unipro_core_clk", &gcc.mux, 0x114 }, + { "gcc_usb30_prim_master_clk", &gcc.mux, 0x58 }, + { "gcc_usb30_prim_mock_utmi_clk", &gcc.mux, 0x5a }, + { "gcc_usb30_prim_sleep_clk", &gcc.mux, 0x59 }, + { "gcc_usb3_prim_phy_com_aux_clk", &gcc.mux, 0x5b }, + { "gcc_usb3_prim_phy_pipe_clk", &gcc.mux, 0x5c }, + { "gcc_vdda_vs_clk", &gcc.mux, 0xbb }, + { "gcc_vddcx_vs_clk", &gcc.mux, 0xb9 }, + { "gcc_vddmx_vs_clk", &gcc.mux, 0xba }, + { "gcc_video_ahb_clk", &gcc.mux, 0x35 }, + { "gcc_video_axi0_clk", &gcc.mux, 0x3b }, + { "gcc_video_throttle_core_clk", &gcc.mux, 0x49 }, + { "gcc_video_xo_clk", &gcc.mux, 0x3d }, + { "gcc_vs_ctrl_ahb_clk", &gcc.mux, 0xbd }, + { "gcc_vs_ctrl_clk", &gcc.mux, 0xbc }, + { "gcc_wcss_vs_clk", &gcc.mux, 0xc0 }, + { "measure_only_ipa_2x_clk", &gcc.mux, 0xc2 }, + + { "disp_cc_mdss_ahb_clk", &disp_cc, 0x1a }, + { "disp_cc_mdss_byte0_clk", &disp_cc, 0x12 }, + { "disp_cc_mdss_byte0_intf_clk", &disp_cc, 0x13 }, + { "disp_cc_mdss_dp_aux_clk", &disp_cc, 0x19 }, + { "disp_cc_mdss_dp_crypto_clk", &disp_cc, 0x17 }, + { "disp_cc_mdss_dp_link_clk", &disp_cc, 0x15 }, + { "disp_cc_mdss_dp_link_intf_clk", &disp_cc, 0x16 }, + { "disp_cc_mdss_dp_pixel_clk", &disp_cc, 0x18 }, + { "disp_cc_mdss_esc0_clk", &disp_cc, 0x14 }, + { "disp_cc_mdss_mdp_clk", &disp_cc, 0xe, }, + { "disp_cc_mdss_mdp_lut_clk", &disp_cc, 0x10 }, + { "disp_cc_mdss_non_gdsc_ahb_clk", &disp_cc, 0x1b }, + { "disp_cc_mdss_pclk0_clk", &disp_cc, 0xd, }, + { "disp_cc_mdss_rot_clk", &disp_cc, 0xf, }, + { "disp_cc_mdss_vsync_clk", &disp_cc, 0x11 }, + { "disp_cc_sleep_clk", &disp_cc, 0x24 }, + { "disp_cc_xo_clk", &disp_cc, 0x23 }, + + { "gpu_cc_ahb_clk", &gpu_cc, 0x10 }, + { "gpu_cc_crc_ahb_clk", &gpu_cc, 0x11 }, + { "gpu_cc_cx_apb_clk", &gpu_cc, 0x14 }, + { "gpu_cc_cx_gfx3d_clk", &gpu_cc, 0x1a }, + { "gpu_cc_cx_gfx3d_slv_clk", &gpu_cc, 0x1b }, + { "gpu_cc_cx_gmu_clk", &gpu_cc, 0x18 }, + { "gpu_cc_cx_snoc_dvm_clk", &gpu_cc, 0x15 }, + { "gpu_cc_cxo_aon_clk", &gpu_cc, 0xa }, + { "gpu_cc_cxo_clk", &gpu_cc, 0x19 }, + { "gpu_cc_gx_cxo_clk", &gpu_cc, 0xe }, + { "gpu_cc_gx_gfx3d_clk", &gpu_cc, 0xb }, + { "gpu_cc_sleep_clk", &gpu_cc, 0x16 }, + + { "video_cc_apb_clk", &video_cc, 0x8 }, + { "video_cc_at_clk", &video_cc, 0xb }, + { "video_cc_sleep_clk", &video_cc, 0xd }, + { "video_cc_vcodec0_axi_clk", &video_cc, 0x6 }, + { "video_cc_vcodec0_core_clk", &video_cc, 0x3 }, + { "video_cc_venus_ahb_clk", &video_cc, 0x9 }, + { "video_cc_venus_ctl_axi_clk", &video_cc, 0x5 }, + { "video_cc_venus_ctl_core_clk", &video_cc, 0x1 }, + { "video_cc_xo_clk", &video_cc, 0xc }, {} }; diff --git a/sm6350.c b/sm6350.c index e24e18b..739e193 100644 --- a/sm6350.c +++ b/sm6350.c @@ -12,11 +12,38 @@ #include "debugcc.h" +static struct gcc_mux gcc = { + .mux = { + .phys = 0x100000, + .size = 0x1f0000, + + .measure = measure_gcc, + + .enable_reg = 0x3500c, + .enable_mask = BIT(0), + + .mux_reg = 0x35f08, + .mux_mask = 0x3ff, + + .div_reg = 0x35008, + .div_mask = 0x7, + .div_val = 4, + }, + + .xo_div4_reg = 0x2c008, + .debug_ctl_reg = 0x35f24, + .debug_status_reg = 0x35f28, +}; + static struct debug_mux cpu_cc = { .phys = 0x182a0000, .size = 0x1000, .block_name = "cpu", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0xbe, + .enable_reg = 0x18, .enable_mask = BIT(0), @@ -35,6 +62,10 @@ static struct debug_mux disp_cc = { .size = 0x20000, .block_name = "disp", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x40, + .enable_reg = 0x3004, .enable_mask = BIT(0), @@ -46,30 +77,15 @@ static struct debug_mux disp_cc = { .div_val = 4, }; -static struct debug_mux gcc = { - .phys = 0x100000, - .size = 0x1f0000, - - .enable_reg = 0x3500c, - .enable_mask = BIT(0), - - .mux_reg = 0x35f08, - .mux_mask = 0x3ff, - - .div_reg = 0x35008, - .div_mask = 0x7, - .div_val = 4, - - .xo_div4_reg = 0x2c008, - .debug_ctl_reg = 0x35f24, - .debug_status_reg = 0x35f28, -}; - static struct debug_mux gpu_cc = { .phys = 0x3d90000, .size = 0x9000, .block_name = "gpu", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x107, + .enable_reg = 0x1100, .enable_mask = BIT(0), @@ -87,147 +103,146 @@ static struct debug_mux mc_cc = { .block_name = "mc", .measure = measure_mccc, + .parent = &gcc.mux, + .parent_mux_val = 0xab, }; static struct measure_clk sm6350_clocks[] = { - { "l3_clk", &gcc, 0xbe, &cpu_cc, 0x41 }, - { "pwrcl_clk", &gcc, 0xbe, &cpu_cc, 0x21 }, - { "perfcl_clk", &gcc, 0xbe, &cpu_cc, 0x25 }, - - //{ "cam_cc_debug_mux", &gcc, 0x3f }, - //{ "cpu_cc_debug_mux", &gcc, 0xbe }, - //{ "disp_cc_debug_mux", &gcc, 0x40 }, - { "gcc_aggre_ufs_phy_axi_clk", &gcc, 0xe2 }, - { "gcc_aggre_usb3_prim_axi_clk", &gcc, 0xe1 }, - { "gcc_boot_rom_ahb_clk", &gcc, 0x80 }, - { "gcc_camera_ahb_clk", &gcc, 0x32 }, - { "gcc_camera_axi_clk", &gcc, 0x36 }, - { "gcc_camera_throttle_nrt_axi_clk", &gcc, 0x4a }, - { "gcc_camera_throttle_rt_axi_clk", &gcc, 0x39 }, - { "gcc_camera_xo_clk", &gcc, 0x3c }, - { "gcc_ce1_ahb_clk", &gcc, 0x92 }, - { "gcc_ce1_axi_clk", &gcc, 0x91 }, - { "gcc_ce1_clk", &gcc, 0x90 }, - { "gcc_cfg_noc_usb3_prim_axi_clk", &gcc, 0x18 }, - { "gcc_cpuss_ahb_clk", &gcc, 0xb7 }, - { "gcc_cpuss_gnoc_clk", &gcc, 0xb8 }, - { "gcc_cpuss_rbcpr_clk", &gcc, 0xb9 }, - { "gcc_ddrss_gpu_axi_clk", &gcc, 0xa5 }, - { "gcc_disp_ahb_clk", &gcc, 0x33 }, - { "gcc_disp_axi_clk", &gcc, 0x37 }, - { "gcc_disp_cc_sleep_clk", &gcc, 0x49 }, - { "gcc_disp_cc_xo_clk", &gcc, 0x48 }, - { "gcc_disp_gpll0_clk", &gcc, 0x44 }, - { "gcc_disp_throttle_axi_clk", &gcc, 0x3a }, - { "gcc_disp_xo_clk", &gcc, 0x3d }, - { "gcc_gp1_clk", &gcc, 0xc5 }, - { "gcc_gp2_clk", &gcc, 0xc6 }, - { "gcc_gp3_clk", &gcc, 0xc7 }, - { "gcc_gpu_cfg_ahb_clk", &gcc, 0x105 }, - { "gcc_gpu_gpll0_clk", &gcc, 0x10b }, - { "gcc_gpu_gpll0_div_clk", &gcc, 0x10c }, - { "gcc_gpu_memnoc_gfx_clk", &gcc, 0x108 }, - { "gcc_gpu_snoc_dvm_gfx_clk", &gcc, 0x109 }, - { "gcc_npu_axi_clk", &gcc, 0x116 }, - { "gcc_npu_bwmon_axi_clk", &gcc, 0x11c }, - { "gcc_npu_bwmon_dma_cfg_ahb_clk", &gcc, 0x11d }, - { "gcc_npu_bwmon_dsp_cfg_ahb_clk", &gcc, 0x11e }, - { "gcc_npu_cfg_ahb_clk", &gcc, 0x115 }, - { "gcc_npu_dma_clk", &gcc, 0x11b }, - { "gcc_npu_gpll0_clk", &gcc, 0x118 }, - { "gcc_npu_gpll0_div_clk", &gcc, 0x119 }, - { "gcc_pdm2_clk", &gcc, 0x7d }, - { "gcc_pdm_ahb_clk", &gcc, 0x7b }, - { "gcc_pdm_xo4_clk", &gcc, 0x7c }, - { "gcc_prng_ahb_clk", &gcc, 0x7e }, - { "gcc_qupv3_wrap0_core_2x_clk", &gcc, 0x6a }, - { "gcc_qupv3_wrap0_core_clk", &gcc, 0x69 }, - { "gcc_qupv3_wrap0_s0_clk", &gcc, 0x6b }, - { "gcc_qupv3_wrap0_s1_clk", &gcc, 0x6c }, - { "gcc_qupv3_wrap0_s2_clk", &gcc, 0x6d }, - { "gcc_qupv3_wrap0_s3_clk", &gcc, 0x6e }, - { "gcc_qupv3_wrap0_s4_clk", &gcc, 0x6f }, - { "gcc_qupv3_wrap0_s5_clk", &gcc, 0x70 }, - { "gcc_qupv3_wrap1_core_2x_clk", &gcc, 0x71 }, - { "gcc_qupv3_wrap1_core_clk", &gcc, 0x72 }, - { "gcc_qupv3_wrap1_s0_clk", &gcc, 0x75 }, - { "gcc_qupv3_wrap1_s1_clk", &gcc, 0x76 }, - { "gcc_qupv3_wrap1_s2_clk", &gcc, 0x77 }, - { "gcc_qupv3_wrap1_s3_clk", &gcc, 0x78 }, - { "gcc_qupv3_wrap1_s4_clk", &gcc, 0x79 }, - { "gcc_qupv3_wrap1_s5_clk", &gcc, 0x7a }, - { "gcc_qupv3_wrap_0_m_ahb_clk", &gcc, 0x67 }, - { "gcc_qupv3_wrap_0_s_ahb_clk", &gcc, 0x68 }, - { "gcc_qupv3_wrap_1_m_ahb_clk", &gcc, 0x73 }, - { "gcc_qupv3_wrap_1_s_ahb_clk", &gcc, 0x74 }, - { "gcc_sdcc1_ahb_clk", &gcc, 0x112 }, - { "gcc_sdcc1_apps_clk", &gcc, 0x113 }, - { "gcc_sdcc1_ice_core_clk", &gcc, 0x114 }, - { "gcc_sdcc2_ahb_clk", &gcc, 0x66 }, - { "gcc_sdcc2_apps_clk", &gcc, 0x65 }, - { "gcc_sys_noc_cpuss_ahb_clk", &gcc, 0x9 }, - { "gcc_ufs_phy_ahb_clk", &gcc, 0xc8 }, - { "gcc_ufs_phy_axi_clk", &gcc, 0xcc }, - { "gcc_ufs_phy_ice_core_clk", &gcc, 0xd1 }, - { "gcc_ufs_phy_phy_aux_clk", &gcc, 0xd2 }, - { "gcc_ufs_phy_rx_symbol_0_clk", &gcc, 0xca }, - { "gcc_ufs_phy_rx_symbol_1_clk", &gcc, 0xcb }, - { "gcc_ufs_phy_tx_symbol_0_clk", &gcc, 0xc9 }, - { "gcc_ufs_phy_unipro_core_clk", &gcc, 0xd0 }, - { "gcc_usb30_prim_master_clk", &gcc, 0x5b }, - { "gcc_usb30_prim_mock_utmi_clk", &gcc, 0x5d }, - { "gcc_usb30_prim_sleep_clk", &gcc, 0x5c }, - { "gcc_usb3_prim_phy_aux_clk", &gcc, 0x5e }, - { "gcc_usb3_prim_phy_com_aux_clk", &gcc, 0x5f }, - { "gcc_usb3_prim_phy_pipe_clk", &gcc, 0x60 }, - { "gcc_video_ahb_clk", &gcc, 0x31 }, - { "gcc_video_axi_clk", &gcc, 0x35 }, - { "gcc_video_throttle_axi_clk", &gcc, 0x38 }, - { "gcc_video_xo_clk", &gcc, 0x3b }, - //{ "gpu_cc_debug_mux", &gcc, 0x107 }, - //{ "mc_cc_debug_mux", &gcc, 0xab }, - { "measure_only_cnoc_clk", &gcc, 0x14 }, - { "measure_only_ipa_2x_clk", &gcc, 0xec }, - { "measure_only_snoc_clk", &gcc, 0x07 }, - //{ "npu_cc_debug_mux", &gcc, 0x11a }, - //{ "video_cc_debug_mux", &gcc, 0x41 }, - - { "disp_cc_mdss_ahb_clk", &gcc, 0x40, &disp_cc, 0x14 }, - { "disp_cc_mdss_byte0_clk", &gcc, 0x40, &disp_cc, 0xc }, - { "disp_cc_mdss_byte0_intf_clk", &gcc, 0x40, &disp_cc, 0xd }, - { "disp_cc_mdss_dp_aux_clk", &gcc, 0x40, &disp_cc, 0x13 }, - { "disp_cc_mdss_dp_crypto_clk", &gcc, 0x40, &disp_cc, 0x11 }, - { "disp_cc_mdss_dp_link_clk", &gcc, 0x40, &disp_cc, 0xf }, - { "disp_cc_mdss_dp_link_intf_clk", &gcc, 0x40, &disp_cc, 0x10 }, - { "disp_cc_mdss_dp_pixel_clk", &gcc, 0x40, &disp_cc, 0x12 }, - { "disp_cc_mdss_esc0_clk", &gcc, 0x40, &disp_cc, 0xe }, - { "disp_cc_mdss_mdp_clk", &gcc, 0x40, &disp_cc, 0x8 }, - { "disp_cc_mdss_mdp_lut_clk", &gcc, 0x40, &disp_cc, 0xa }, - { "disp_cc_mdss_non_gdsc_ahb_clk", &gcc, 0x40, &disp_cc, 0x15 }, - { "disp_cc_mdss_pclk0_clk", &gcc, 0x40, &disp_cc, 0x7 }, - { "disp_cc_mdss_rot_clk", &gcc, 0x40, &disp_cc, 0x9 }, - { "disp_cc_mdss_rscc_ahb_clk", &gcc, 0x40, &disp_cc, 0x17 }, - { "disp_cc_mdss_rscc_vsync_clk", &gcc, 0x40, &disp_cc, 0x16 }, - { "disp_cc_mdss_vsync_clk", &gcc, 0x40, &disp_cc, 0xb }, - { "disp_cc_sleep_clk", &gcc, 0x40, &disp_cc, 0x1d }, - { "disp_cc_xo_clk", &gcc, 0x40, &disp_cc, 0x1e }, - - { "gpu_cc_acd_ahb_clk", &gcc, 0x107, &gpu_cc, 0x20 }, - { "gpu_cc_acd_cxo_clk", &gcc, 0x107, &gpu_cc, 0x1f }, - { "gpu_cc_ahb_clk", &gcc, 0x107, &gpu_cc, 0x11 }, - { "gpu_cc_crc_ahb_clk", &gcc, 0x107, &gpu_cc, 0x12 }, - { "gpu_cc_cx_gfx3d_clk", &gcc, 0x107, &gpu_cc, 0x1a }, - { "gpu_cc_cx_gfx3d_slv_clk", &gcc, 0x107, &gpu_cc, 0x1b }, - { "gpu_cc_cx_gmu_clk", &gcc, 0x107, &gpu_cc, 0x19 }, - { "gpu_cc_cx_snoc_dvm_clk", &gcc, 0x107, &gpu_cc, 0x16 }, - { "gpu_cc_cxo_aon_clk", &gcc, 0x107, &gpu_cc, 0xb }, - { "gpu_cc_cxo_clk", &gcc, 0x107, &gpu_cc, 0xa }, - { "gpu_cc_gx_cxo_clk", &gcc, 0x107, &gpu_cc, 0xf }, - { "gpu_cc_gx_gfx3d_clk", &gcc, 0x107, &gpu_cc, 0xc }, - { "gpu_cc_gx_gmu_clk", &gcc, 0x107, &gpu_cc, 0x10 }, - { "gpu_cc_gx_vsense_clk", &gcc, 0x107, &gpu_cc, 0xd }, - - { "mccc_clk", &gcc, 0xab, &mc_cc, 0x50 }, + //{ "cam_cc_debug_mux", &gcc.mux, 0x3f }, + //{ "npu_cc_debug_mux", &gcc.mux, 0x11a }, + //{ "video_cc_debug_mux", &gcc.mux, 0x41 }, + + { "l3_clk", &cpu_cc, 0x41 }, + { "pwrcl_clk", &cpu_cc, 0x21 }, + { "perfcl_clk", &cpu_cc, 0x25 }, + + { "gcc_aggre_ufs_phy_axi_clk", &gcc.mux, 0xe2 }, + { "gcc_aggre_usb3_prim_axi_clk", &gcc.mux, 0xe1 }, + { "gcc_boot_rom_ahb_clk", &gcc.mux, 0x80 }, + { "gcc_camera_ahb_clk", &gcc.mux, 0x32 }, + { "gcc_camera_axi_clk", &gcc.mux, 0x36 }, + { "gcc_camera_throttle_nrt_axi_clk", &gcc.mux, 0x4a }, + { "gcc_camera_throttle_rt_axi_clk", &gcc.mux, 0x39 }, + { "gcc_camera_xo_clk", &gcc.mux, 0x3c }, + { "gcc_ce1_ahb_clk", &gcc.mux, 0x92 }, + { "gcc_ce1_axi_clk", &gcc.mux, 0x91 }, + { "gcc_ce1_clk", &gcc.mux, 0x90 }, + { "gcc_cfg_noc_usb3_prim_axi_clk", &gcc.mux, 0x18 }, + { "gcc_cpuss_ahb_clk", &gcc.mux, 0xb7 }, + { "gcc_cpuss_gnoc_clk", &gcc.mux, 0xb8 }, + { "gcc_cpuss_rbcpr_clk", &gcc.mux, 0xb9 }, + { "gcc_ddrss_gpu_axi_clk", &gcc.mux, 0xa5 }, + { "gcc_disp_ahb_clk", &gcc.mux, 0x33 }, + { "gcc_disp_axi_clk", &gcc.mux, 0x37 }, + { "gcc_disp_cc_sleep_clk", &gcc.mux, 0x49 }, + { "gcc_disp_cc_xo_clk", &gcc.mux, 0x48 }, + { "gcc_disp_gpll0_clk", &gcc.mux, 0x44 }, + { "gcc_disp_throttle_axi_clk", &gcc.mux, 0x3a }, + { "gcc_disp_xo_clk", &gcc.mux, 0x3d }, + { "gcc_gp1_clk", &gcc.mux, 0xc5 }, + { "gcc_gp2_clk", &gcc.mux, 0xc6 }, + { "gcc_gp3_clk", &gcc.mux, 0xc7 }, + { "gcc_gpu_cfg_ahb_clk", &gcc.mux, 0x105 }, + { "gcc_gpu_gpll0_clk", &gcc.mux, 0x10b }, + { "gcc_gpu_gpll0_div_clk", &gcc.mux, 0x10c }, + { "gcc_gpu_memnoc_gfx_clk", &gcc.mux, 0x108 }, + { "gcc_gpu_snoc_dvm_gfx_clk", &gcc.mux, 0x109 }, + { "gcc_npu_axi_clk", &gcc.mux, 0x116 }, + { "gcc_npu_bwmon_axi_clk", &gcc.mux, 0x11c }, + { "gcc_npu_bwmon_dma_cfg_ahb_clk", &gcc.mux, 0x11d }, + { "gcc_npu_bwmon_dsp_cfg_ahb_clk", &gcc.mux, 0x11e }, + { "gcc_npu_cfg_ahb_clk", &gcc.mux, 0x115 }, + { "gcc_npu_dma_clk", &gcc.mux, 0x11b }, + { "gcc_npu_gpll0_clk", &gcc.mux, 0x118 }, + { "gcc_npu_gpll0_div_clk", &gcc.mux, 0x119 }, + { "gcc_pdm2_clk", &gcc.mux, 0x7d }, + { "gcc_pdm_ahb_clk", &gcc.mux, 0x7b }, + { "gcc_pdm_xo4_clk", &gcc.mux, 0x7c }, + { "gcc_prng_ahb_clk", &gcc.mux, 0x7e }, + { "gcc_qupv3_wrap0_core_2x_clk", &gcc.mux, 0x6a }, + { "gcc_qupv3_wrap0_core_clk", &gcc.mux, 0x69 }, + { "gcc_qupv3_wrap0_s0_clk", &gcc.mux, 0x6b }, + { "gcc_qupv3_wrap0_s1_clk", &gcc.mux, 0x6c }, + { "gcc_qupv3_wrap0_s2_clk", &gcc.mux, 0x6d }, + { "gcc_qupv3_wrap0_s3_clk", &gcc.mux, 0x6e }, + { "gcc_qupv3_wrap0_s4_clk", &gcc.mux, 0x6f }, + { "gcc_qupv3_wrap0_s5_clk", &gcc.mux, 0x70 }, + { "gcc_qupv3_wrap1_core_2x_clk", &gcc.mux, 0x71 }, + { "gcc_qupv3_wrap1_core_clk", &gcc.mux, 0x72 }, + { "gcc_qupv3_wrap1_s0_clk", &gcc.mux, 0x75 }, + { "gcc_qupv3_wrap1_s1_clk", &gcc.mux, 0x76 }, + { "gcc_qupv3_wrap1_s2_clk", &gcc.mux, 0x77 }, + { "gcc_qupv3_wrap1_s3_clk", &gcc.mux, 0x78 }, + { "gcc_qupv3_wrap1_s4_clk", &gcc.mux, 0x79 }, + { "gcc_qupv3_wrap1_s5_clk", &gcc.mux, 0x7a }, + { "gcc_qupv3_wrap_0_m_ahb_clk", &gcc.mux, 0x67 }, + { "gcc_qupv3_wrap_0_s_ahb_clk", &gcc.mux, 0x68 }, + { "gcc_qupv3_wrap_1_m_ahb_clk", &gcc.mux, 0x73 }, + { "gcc_qupv3_wrap_1_s_ahb_clk", &gcc.mux, 0x74 }, + { "gcc_sdcc1_ahb_clk", &gcc.mux, 0x112 }, + { "gcc_sdcc1_apps_clk", &gcc.mux, 0x113 }, + { "gcc_sdcc1_ice_core_clk", &gcc.mux, 0x114 }, + { "gcc_sdcc2_ahb_clk", &gcc.mux, 0x66 }, + { "gcc_sdcc2_apps_clk", &gcc.mux, 0x65 }, + { "gcc_sys_noc_cpuss_ahb_clk", &gcc.mux, 0x9 }, + { "gcc_ufs_phy_ahb_clk", &gcc.mux, 0xc8 }, + { "gcc_ufs_phy_axi_clk", &gcc.mux, 0xcc }, + { "gcc_ufs_phy_ice_core_clk", &gcc.mux, 0xd1 }, + { "gcc_ufs_phy_phy_aux_clk", &gcc.mux, 0xd2 }, + { "gcc_ufs_phy_rx_symbol_0_clk", &gcc.mux, 0xca }, + { "gcc_ufs_phy_rx_symbol_1_clk", &gcc.mux, 0xcb }, + { "gcc_ufs_phy_tx_symbol_0_clk", &gcc.mux, 0xc9 }, + { "gcc_ufs_phy_unipro_core_clk", &gcc.mux, 0xd0 }, + { "gcc_usb30_prim_master_clk", &gcc.mux, 0x5b }, + { "gcc_usb30_prim_mock_utmi_clk", &gcc.mux, 0x5d }, + { "gcc_usb30_prim_sleep_clk", &gcc.mux, 0x5c }, + { "gcc_usb3_prim_phy_aux_clk", &gcc.mux, 0x5e }, + { "gcc_usb3_prim_phy_com_aux_clk", &gcc.mux, 0x5f }, + { "gcc_usb3_prim_phy_pipe_clk", &gcc.mux, 0x60 }, + { "gcc_video_ahb_clk", &gcc.mux, 0x31 }, + { "gcc_video_axi_clk", &gcc.mux, 0x35 }, + { "gcc_video_throttle_axi_clk", &gcc.mux, 0x38 }, + { "gcc_video_xo_clk", &gcc.mux, 0x3b }, + { "measure_only_cnoc_clk", &gcc.mux, 0x14 }, + { "measure_only_ipa_2x_clk", &gcc.mux, 0xec }, + { "measure_only_snoc_clk", &gcc.mux, 0x07 }, + + { "disp_cc_mdss_ahb_clk", &disp_cc, 0x14 }, + { "disp_cc_mdss_byte0_clk", &disp_cc, 0xc }, + { "disp_cc_mdss_byte0_intf_clk", &disp_cc, 0xd }, + { "disp_cc_mdss_dp_aux_clk", &disp_cc, 0x13 }, + { "disp_cc_mdss_dp_crypto_clk", &disp_cc, 0x11 }, + { "disp_cc_mdss_dp_link_clk", &disp_cc, 0xf }, + { "disp_cc_mdss_dp_link_intf_clk", &disp_cc, 0x10 }, + { "disp_cc_mdss_dp_pixel_clk", &disp_cc, 0x12 }, + { "disp_cc_mdss_esc0_clk", &disp_cc, 0xe }, + { "disp_cc_mdss_mdp_clk", &disp_cc, 0x8 }, + { "disp_cc_mdss_mdp_lut_clk", &disp_cc, 0xa }, + { "disp_cc_mdss_non_gdsc_ahb_clk", &disp_cc, 0x15 }, + { "disp_cc_mdss_pclk0_clk", &disp_cc, 0x7 }, + { "disp_cc_mdss_rot_clk", &disp_cc, 0x9 }, + { "disp_cc_mdss_rscc_ahb_clk", &disp_cc, 0x17 }, + { "disp_cc_mdss_rscc_vsync_clk", &disp_cc, 0x16 }, + { "disp_cc_mdss_vsync_clk", &disp_cc, 0xb }, + { "disp_cc_sleep_clk", &disp_cc, 0x1d }, + { "disp_cc_xo_clk", &disp_cc, 0x1e }, + + { "gpu_cc_acd_ahb_clk", &gpu_cc, 0x20 }, + { "gpu_cc_acd_cxo_clk", &gpu_cc, 0x1f }, + { "gpu_cc_ahb_clk", &gpu_cc, 0x11 }, + { "gpu_cc_crc_ahb_clk", &gpu_cc, 0x12 }, + { "gpu_cc_cx_gfx3d_clk", &gpu_cc, 0x1a }, + { "gpu_cc_cx_gfx3d_slv_clk", &gpu_cc, 0x1b }, + { "gpu_cc_cx_gmu_clk", &gpu_cc, 0x19 }, + { "gpu_cc_cx_snoc_dvm_clk", &gpu_cc, 0x16 }, + { "gpu_cc_cxo_aon_clk", &gpu_cc, 0xb }, + { "gpu_cc_cxo_clk", &gpu_cc, 0xa }, + { "gpu_cc_gx_cxo_clk", &gpu_cc, 0xf }, + { "gpu_cc_gx_gfx3d_clk", &gpu_cc, 0xc }, + { "gpu_cc_gx_gmu_clk", &gpu_cc, 0x10 }, + { "gpu_cc_gx_vsense_clk", &gpu_cc, 0xd }, + + { "mccc_clk", &mc_cc, 0x50 }, {} }; diff --git a/sm6375.c b/sm6375.c index ad4943d..cf7f8d4 100644 --- a/sm6375.c +++ b/sm6375.c @@ -12,11 +12,36 @@ #include "debugcc.h" +static struct gcc_mux gcc = { + .mux = { + .phys = 0x1400000, + .size = 0x1f0000, + + .enable_reg = 0x30004, + .enable_mask = BIT(0), + + .mux_reg = 0x62000, + .mux_mask = 0x3ff, + + .div_reg = 0x30000, + .div_mask = 0xf, + .div_val = 1, + }, + + .xo_div4_reg = 0x28008, + .debug_ctl_reg = 0x62038, + .debug_status_reg = 0x6203c, +}; + static struct debug_mux cpu_cc = { .phys = 0xfaa0000, .size = 0x1000, .block_name = "cpu", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0xbf, + .enable_reg = 0x18, .enable_mask = BIT(0), @@ -35,6 +60,10 @@ static struct debug_mux disp_cc = { .size = 0x20000, .block_name = "disp", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x43, + .enable_reg = 0x3004, .enable_mask = BIT(0), @@ -46,30 +75,15 @@ static struct debug_mux disp_cc = { .div_val = 4, }; -static struct debug_mux gcc = { - .phys = 0x1400000, - .size = 0x1f0000, - - .enable_reg = 0x30004, - .enable_mask = BIT(0), - - .mux_reg = 0x62000, - .mux_mask = 0x3ff, - - .div_reg = 0x30000, - .div_mask = 0xf, - .div_val = 1, - - .xo_div4_reg = 0x28008, - .debug_ctl_reg = 0x62038, - .debug_status_reg = 0x6203c, -}; - static struct debug_mux gpu_cc = { .phys = 0x5990000, .size = 0x9000, .block_name = "gpu", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0xfb, + .enable_reg = 0x1100, .enable_mask = BIT(0), @@ -88,165 +102,164 @@ static struct debug_mux mc_cc = { .block_name = "mc", .measure = measure_mccc, + .parent = &gcc.mux, + .parent_mux_val = 0xae, }; static struct measure_clk sm6375_clocks[] = { - { "l3_clk", &gcc, 0xbf, &cpu_cc, 0x41 }, - { "perfcl_clk", &gcc, 0xbf, &cpu_cc, 0x25 }, - { "pwrcl_clk", &gcc, 0xbf, &cpu_cc, 0x21 }, - //{ "cpu_cc_debug_mux", &gcc, 0xbf }, - //{ "disp_cc_debug_mux", &gcc, 0x43 }, - { "gcc_ahb2phy_csi_clk", &gcc, 0x67 }, - { "gcc_ahb2phy_usb_clk", &gcc, 0x68 }, - { "gcc_bimc_gpu_axi_clk", &gcc, 0x9d }, - { "gcc_boot_rom_ahb_clk", &gcc, 0x84 }, - { "gcc_cam_throttle_nrt_clk", &gcc, 0x4d }, - { "gcc_cam_throttle_rt_clk", &gcc, 0x4c }, - { "gcc_camss_axi_clk", &gcc, 0x154 }, - { "gcc_camss_cci_0_clk", &gcc, 0x151 }, - { "gcc_camss_cci_1_clk", &gcc, 0x152 }, - { "gcc_camss_cphy_0_clk", &gcc, 0x140 }, - { "gcc_camss_cphy_1_clk", &gcc, 0x141 }, - { "gcc_camss_cphy_2_clk", &gcc, 0x142 }, - { "gcc_camss_cphy_3_clk", &gcc, 0x143 }, - { "gcc_camss_csi0phytimer_clk", &gcc, 0x130 }, - { "gcc_camss_csi1phytimer_clk", &gcc, 0x131 }, - { "gcc_camss_csi2phytimer_clk", &gcc, 0x132 }, - { "gcc_camss_csi3phytimer_clk", &gcc, 0x133 }, - { "gcc_camss_mclk0_clk", &gcc, 0x134 }, - { "gcc_camss_mclk1_clk", &gcc, 0x135 }, - { "gcc_camss_mclk2_clk", &gcc, 0x136 }, - { "gcc_camss_mclk3_clk", &gcc, 0x137 }, - { "gcc_camss_mclk4_clk", &gcc, 0x138 }, - { "gcc_camss_nrt_axi_clk", &gcc, 0x158 }, - { "gcc_camss_ope_ahb_clk", &gcc, 0x150 }, - { "gcc_camss_ope_clk", &gcc, 0x14e }, - { "gcc_camss_rt_axi_clk", &gcc, 0x15a }, - { "gcc_camss_tfe_0_clk", &gcc, 0x139 }, - { "gcc_camss_tfe_0_cphy_rx_clk", &gcc, 0x13d }, - { "gcc_camss_tfe_0_csid_clk", &gcc, 0x144 }, - { "gcc_camss_tfe_1_clk", &gcc, 0x13a }, - { "gcc_camss_tfe_1_cphy_rx_clk", &gcc, 0x13e }, - { "gcc_camss_tfe_1_csid_clk", &gcc, 0x146 }, - { "gcc_camss_tfe_2_clk", &gcc, 0x13b }, - { "gcc_camss_tfe_2_cphy_rx_clk", &gcc, 0x13f }, - { "gcc_camss_tfe_2_csid_clk", &gcc, 0x148 }, - { "gcc_camss_top_ahb_clk", &gcc, 0x153 }, - { "gcc_cfg_noc_usb3_prim_axi_clk", &gcc, 0x1f }, - { "gcc_disp_gpll0_div_clk_src", &gcc, 0x48 }, - { "gcc_disp_hf_axi_clk", &gcc, 0x3e }, - { "gcc_disp_sleep_clk", &gcc, 0x4e }, - { "gcc_disp_throttle_core_clk", &gcc, 0x4a }, - { "gcc_gp1_clk", &gcc, 0xca }, - { "gcc_gp2_clk", &gcc, 0xcb }, - { "gcc_gp3_clk", &gcc, 0xcc }, - { "gcc_gpu_gpll0_clk_src", &gcc, 0xff }, - { "gcc_gpu_gpll0_div_clk_src", &gcc, 0x100 }, - { "gcc_gpu_memnoc_gfx_clk", &gcc, 0xfc }, - { "gcc_gpu_snoc_dvm_gfx_clk", &gcc, 0xfe }, - { "gcc_gpu_throttle_core_clk", &gcc, 0x103 }, - { "gcc_pdm2_clk", &gcc, 0x81 }, - { "gcc_pdm_ahb_clk", &gcc, 0x7f }, - { "gcc_pdm_xo4_clk", &gcc, 0x80 }, - { "gcc_prng_ahb_clk", &gcc, 0x82 }, - { "gcc_qmip_camera_nrt_ahb_clk", &gcc, 0x3b }, - { "gcc_qmip_camera_rt_ahb_clk", &gcc, 0x49 }, - { "gcc_qmip_disp_ahb_clk", &gcc, 0x3c }, - { "gcc_qmip_gpu_cfg_ahb_clk", &gcc, 0x101 }, - { "gcc_qmip_video_vcodec_ahb_clk", &gcc, 0x3a }, - { "gcc_qupv3_wrap0_core_2x_clk", &gcc, 0x6e }, - { "gcc_qupv3_wrap0_core_clk", &gcc, 0x6d }, - { "gcc_qupv3_wrap0_s0_clk", &gcc, 0x6f }, - { "gcc_qupv3_wrap0_s1_clk", &gcc, 0x70 }, - { "gcc_qupv3_wrap0_s2_clk", &gcc, 0x71 }, - { "gcc_qupv3_wrap0_s3_clk", &gcc, 0x72 }, - { "gcc_qupv3_wrap0_s4_clk", &gcc, 0x73 }, - { "gcc_qupv3_wrap0_s5_clk", &gcc, 0x74 }, - { "gcc_qupv3_wrap1_core_2x_clk", &gcc, 0x78 }, - { "gcc_qupv3_wrap1_core_clk", &gcc, 0x77 }, - { "gcc_qupv3_wrap1_s0_clk", &gcc, 0x79 }, - { "gcc_qupv3_wrap1_s1_clk", &gcc, 0x7a }, - { "gcc_qupv3_wrap1_s2_clk", &gcc, 0x7b }, - { "gcc_qupv3_wrap1_s3_clk", &gcc, 0x7c }, - { "gcc_qupv3_wrap1_s5_clk", &gcc, 0x7e }, - { "gcc_qupv3_wrap_0_m_ahb_clk", &gcc, 0x6b }, - { "gcc_qupv3_wrap_0_s_ahb_clk", &gcc, 0x6c }, - { "gcc_sdcc1_ahb_clk", &gcc, 0x108 }, - { "gcc_sdcc1_apps_clk", &gcc, 0x107 }, - { "gcc_sdcc1_ice_core_clk", &gcc, 0x109 }, - { "gcc_sdcc2_ahb_clk", &gcc, 0x6a }, - { "gcc_sdcc2_apps_clk", &gcc, 0x69 }, - { "gcc_sys_noc_cpuss_ahb_clk", &gcc, 0x9 }, - { "gcc_sys_noc_ufs_phy_axi_clk", &gcc, 0x1b }, - { "gcc_sys_noc_usb3_prim_axi_clk", &gcc, 0x1a }, - { "gcc_ufs_phy_ahb_clk", &gcc, 0x127 }, - { "gcc_ufs_phy_axi_clk", &gcc, 0x126 }, - { "gcc_ufs_phy_ice_core_clk", &gcc, 0x12d }, - { "gcc_ufs_phy_phy_aux_clk", &gcc, 0x12e }, - { "gcc_ufs_phy_rx_symbol_0_clk", &gcc, 0x129 }, - { "gcc_ufs_phy_tx_symbol_0_clk", &gcc, 0x128 }, - { "gcc_ufs_phy_unipro_core_clk", &gcc, 0x12c }, - { "gcc_usb30_prim_master_clk", &gcc, 0x5e }, - { "gcc_usb30_prim_mock_utmi_clk", &gcc, 0x60 }, - { "gcc_usb30_prim_sleep_clk", &gcc, 0x5f }, - { "gcc_usb3_prim_phy_com_aux_clk", &gcc, 0x61 }, - { "gcc_usb3_prim_phy_pipe_clk", &gcc, 0x62 }, - { "gcc_vcodec0_axi_clk", &gcc, 0x160 }, - { "gcc_venus_ahb_clk", &gcc, 0x161 }, - { "gcc_venus_ctl_axi_clk", &gcc, 0x15f }, - { "gcc_video_axi0_clk", &gcc, 0x3d }, - { "gcc_video_throttle_core_clk", &gcc, 0x4b }, - { "gcc_video_vcodec0_sys_clk", &gcc, 0x15d }, - { "gcc_video_venus_ctl_clk", &gcc, 0x15b }, - { "gcc_video_xo_clk", &gcc, 0x3f }, - //{ "gpu_cc_debug_mux", &gcc, 0xfb }, - //{ "mc_cc_debug_mux", &gcc, 0xae }, - { "measure_only_cnoc_clk", &gcc, 0x1d }, - { "measure_only_gcc_camera_ahb_clk", &gcc, 0x38 }, - { "measure_only_gcc_camera_xo_clk", &gcc, 0x40 }, - { "measure_only_gcc_cpuss_gnoc_clk", &gcc, 0xba }, - { "measure_only_gcc_disp_ahb_clk", &gcc, 0x39 }, - { "measure_only_gcc_disp_xo_clk", &gcc, 0x41 }, - { "measure_only_gcc_gpu_cfg_ahb_clk", &gcc, 0xf9 }, - { "measure_only_gcc_qupv3_wrap1_s4_clk", &gcc, 0x7d }, - { "measure_only_gcc_qupv3_wrap_1_m_ahb_clk", &gcc, 0x75 }, - { "measure_only_gcc_qupv3_wrap_1_s_ahb_clk", &gcc, 0x76 }, - { "measure_only_gcc_video_ahb_clk", &gcc, 0x37 }, - { "measure_only_hwkm_ahb_clk", &gcc, 0x166 }, - { "measure_only_hwkm_km_core_clk", &gcc, 0x167 }, - { "measure_only_ipa_2x_clk", &gcc, 0xd7 }, - { "measure_only_pka_ahb_clk", &gcc, 0x162 }, - { "measure_only_pka_core_clk", &gcc, 0x163 }, - { "measure_only_snoc_clk", &gcc, 0x7 }, + { "l3_clk", &cpu_cc, 0x41 }, + { "perfcl_clk", &cpu_cc, 0x25 }, + { "pwrcl_clk", &cpu_cc, 0x21 }, + + { "gcc_ahb2phy_csi_clk", &gcc.mux, 0x67 }, + { "gcc_ahb2phy_usb_clk", &gcc.mux, 0x68 }, + { "gcc_bimc_gpu_axi_clk", &gcc.mux, 0x9d }, + { "gcc_boot_rom_ahb_clk", &gcc.mux, 0x84 }, + { "gcc_cam_throttle_nrt_clk", &gcc.mux, 0x4d }, + { "gcc_cam_throttle_rt_clk", &gcc.mux, 0x4c }, + { "gcc_camss_axi_clk", &gcc.mux, 0x154 }, + { "gcc_camss_cci_0_clk", &gcc.mux, 0x151 }, + { "gcc_camss_cci_1_clk", &gcc.mux, 0x152 }, + { "gcc_camss_cphy_0_clk", &gcc.mux, 0x140 }, + { "gcc_camss_cphy_1_clk", &gcc.mux, 0x141 }, + { "gcc_camss_cphy_2_clk", &gcc.mux, 0x142 }, + { "gcc_camss_cphy_3_clk", &gcc.mux, 0x143 }, + { "gcc_camss_csi0phytimer_clk", &gcc.mux, 0x130 }, + { "gcc_camss_csi1phytimer_clk", &gcc.mux, 0x131 }, + { "gcc_camss_csi2phytimer_clk", &gcc.mux, 0x132 }, + { "gcc_camss_csi3phytimer_clk", &gcc.mux, 0x133 }, + { "gcc_camss_mclk0_clk", &gcc.mux, 0x134 }, + { "gcc_camss_mclk1_clk", &gcc.mux, 0x135 }, + { "gcc_camss_mclk2_clk", &gcc.mux, 0x136 }, + { "gcc_camss_mclk3_clk", &gcc.mux, 0x137 }, + { "gcc_camss_mclk4_clk", &gcc.mux, 0x138 }, + { "gcc_camss_nrt_axi_clk", &gcc.mux, 0x158 }, + { "gcc_camss_ope_ahb_clk", &gcc.mux, 0x150 }, + { "gcc_camss_ope_clk", &gcc.mux, 0x14e }, + { "gcc_camss_rt_axi_clk", &gcc.mux, 0x15a }, + { "gcc_camss_tfe_0_clk", &gcc.mux, 0x139 }, + { "gcc_camss_tfe_0_cphy_rx_clk", &gcc.mux, 0x13d }, + { "gcc_camss_tfe_0_csid_clk", &gcc.mux, 0x144 }, + { "gcc_camss_tfe_1_clk", &gcc.mux, 0x13a }, + { "gcc_camss_tfe_1_cphy_rx_clk", &gcc.mux, 0x13e }, + { "gcc_camss_tfe_1_csid_clk", &gcc.mux, 0x146 }, + { "gcc_camss_tfe_2_clk", &gcc.mux, 0x13b }, + { "gcc_camss_tfe_2_cphy_rx_clk", &gcc.mux, 0x13f }, + { "gcc_camss_tfe_2_csid_clk", &gcc.mux, 0x148 }, + { "gcc_camss_top_ahb_clk", &gcc.mux, 0x153 }, + { "gcc_cfg_noc_usb3_prim_axi_clk", &gcc.mux, 0x1f }, + { "gcc_disp_gpll0_div_clk_src", &gcc.mux, 0x48 }, + { "gcc_disp_hf_axi_clk", &gcc.mux, 0x3e }, + { "gcc_disp_sleep_clk", &gcc.mux, 0x4e }, + { "gcc_disp_throttle_core_clk", &gcc.mux, 0x4a }, + { "gcc_gp1_clk", &gcc.mux, 0xca }, + { "gcc_gp2_clk", &gcc.mux, 0xcb }, + { "gcc_gp3_clk", &gcc.mux, 0xcc }, + { "gcc_gpu_gpll0_clk_src", &gcc.mux, 0xff }, + { "gcc_gpu_gpll0_div_clk_src", &gcc.mux, 0x100 }, + { "gcc_gpu_memnoc_gfx_clk", &gcc.mux, 0xfc }, + { "gcc_gpu_snoc_dvm_gfx_clk", &gcc.mux, 0xfe }, + { "gcc_gpu_throttle_core_clk", &gcc.mux, 0x103 }, + { "gcc_pdm2_clk", &gcc.mux, 0x81 }, + { "gcc_pdm_ahb_clk", &gcc.mux, 0x7f }, + { "gcc_pdm_xo4_clk", &gcc.mux, 0x80 }, + { "gcc_prng_ahb_clk", &gcc.mux, 0x82 }, + { "gcc_qmip_camera_nrt_ahb_clk", &gcc.mux, 0x3b }, + { "gcc_qmip_camera_rt_ahb_clk", &gcc.mux, 0x49 }, + { "gcc_qmip_disp_ahb_clk", &gcc.mux, 0x3c }, + { "gcc_qmip_gpu_cfg_ahb_clk", &gcc.mux, 0x101 }, + { "gcc_qmip_video_vcodec_ahb_clk", &gcc.mux, 0x3a }, + { "gcc_qupv3_wrap0_core_2x_clk", &gcc.mux, 0x6e }, + { "gcc_qupv3_wrap0_core_clk", &gcc.mux, 0x6d }, + { "gcc_qupv3_wrap0_s0_clk", &gcc.mux, 0x6f }, + { "gcc_qupv3_wrap0_s1_clk", &gcc.mux, 0x70 }, + { "gcc_qupv3_wrap0_s2_clk", &gcc.mux, 0x71 }, + { "gcc_qupv3_wrap0_s3_clk", &gcc.mux, 0x72 }, + { "gcc_qupv3_wrap0_s4_clk", &gcc.mux, 0x73 }, + { "gcc_qupv3_wrap0_s5_clk", &gcc.mux, 0x74 }, + { "gcc_qupv3_wrap1_core_2x_clk", &gcc.mux, 0x78 }, + { "gcc_qupv3_wrap1_core_clk", &gcc.mux, 0x77 }, + { "gcc_qupv3_wrap1_s0_clk", &gcc.mux, 0x79 }, + { "gcc_qupv3_wrap1_s1_clk", &gcc.mux, 0x7a }, + { "gcc_qupv3_wrap1_s2_clk", &gcc.mux, 0x7b }, + { "gcc_qupv3_wrap1_s3_clk", &gcc.mux, 0x7c }, + { "gcc_qupv3_wrap1_s5_clk", &gcc.mux, 0x7e }, + { "gcc_qupv3_wrap_0_m_ahb_clk", &gcc.mux, 0x6b }, + { "gcc_qupv3_wrap_0_s_ahb_clk", &gcc.mux, 0x6c }, + { "gcc_sdcc1_ahb_clk", &gcc.mux, 0x108 }, + { "gcc_sdcc1_apps_clk", &gcc.mux, 0x107 }, + { "gcc_sdcc1_ice_core_clk", &gcc.mux, 0x109 }, + { "gcc_sdcc2_ahb_clk", &gcc.mux, 0x6a }, + { "gcc_sdcc2_apps_clk", &gcc.mux, 0x69 }, + { "gcc_sys_noc_cpuss_ahb_clk", &gcc.mux, 0x9 }, + { "gcc_sys_noc_ufs_phy_axi_clk", &gcc.mux, 0x1b }, + { "gcc_sys_noc_usb3_prim_axi_clk", &gcc.mux, 0x1a }, + { "gcc_ufs_phy_ahb_clk", &gcc.mux, 0x127 }, + { "gcc_ufs_phy_axi_clk", &gcc.mux, 0x126 }, + { "gcc_ufs_phy_ice_core_clk", &gcc.mux, 0x12d }, + { "gcc_ufs_phy_phy_aux_clk", &gcc.mux, 0x12e }, + { "gcc_ufs_phy_rx_symbol_0_clk", &gcc.mux, 0x129 }, + { "gcc_ufs_phy_tx_symbol_0_clk", &gcc.mux, 0x128 }, + { "gcc_ufs_phy_unipro_core_clk", &gcc.mux, 0x12c }, + { "gcc_usb30_prim_master_clk", &gcc.mux, 0x5e }, + { "gcc_usb30_prim_mock_utmi_clk", &gcc.mux, 0x60 }, + { "gcc_usb30_prim_sleep_clk", &gcc.mux, 0x5f }, + { "gcc_usb3_prim_phy_com_aux_clk", &gcc.mux, 0x61 }, + { "gcc_usb3_prim_phy_pipe_clk", &gcc.mux, 0x62 }, + { "gcc_vcodec0_axi_clk", &gcc.mux, 0x160 }, + { "gcc_venus_ahb_clk", &gcc.mux, 0x161 }, + { "gcc_venus_ctl_axi_clk", &gcc.mux, 0x15f }, + { "gcc_video_axi0_clk", &gcc.mux, 0x3d }, + { "gcc_video_throttle_core_clk", &gcc.mux, 0x4b }, + { "gcc_video_vcodec0_sys_clk", &gcc.mux, 0x15d }, + { "gcc_video_venus_ctl_clk", &gcc.mux, 0x15b }, + { "gcc_video_xo_clk", &gcc.mux, 0x3f }, + { "measure_only_cnoc_clk", &gcc.mux, 0x1d }, + { "measure_only_gcc_camera_ahb_clk", &gcc.mux, 0x38 }, + { "measure_only_gcc_camera_xo_clk", &gcc.mux, 0x40 }, + { "measure_only_gcc_cpuss_gnoc_clk", &gcc.mux, 0xba }, + { "measure_only_gcc_disp_ahb_clk", &gcc.mux, 0x39 }, + { "measure_only_gcc_disp_xo_clk", &gcc.mux, 0x41 }, + { "measure_only_gcc_gpu_cfg_ahb_clk", &gcc.mux, 0xf9 }, + { "measure_only_gcc_qupv3_wrap1_s4_clk", &gcc.mux, 0x7d }, + { "measure_only_gcc_qupv3_wrap_1_m_ahb_clk", &gcc.mux, 0x75 }, + { "measure_only_gcc_qupv3_wrap_1_s_ahb_clk", &gcc.mux, 0x76 }, + { "measure_only_gcc_video_ahb_clk", &gcc.mux, 0x37 }, + { "measure_only_hwkm_ahb_clk", &gcc.mux, 0x166 }, + { "measure_only_hwkm_km_core_clk", &gcc.mux, 0x167 }, + { "measure_only_ipa_2x_clk", &gcc.mux, 0xd7 }, + { "measure_only_pka_ahb_clk", &gcc.mux, 0x162 }, + { "measure_only_pka_core_clk", &gcc.mux, 0x163 }, + { "measure_only_snoc_clk", &gcc.mux, 0x7 }, - { "disp_cc_mdss_ahb_clk", &gcc, 0x43, &disp_cc, 0x14 }, - { "disp_cc_mdss_byte0_clk", &gcc, 0x43, &disp_cc, 0xc }, - { "disp_cc_mdss_byte0_intf_clk", &gcc, 0x43, &disp_cc, 0xd }, - { "disp_cc_mdss_esc0_clk", &gcc, 0x43, &disp_cc, 0xe }, - { "disp_cc_mdss_mdp_clk", &gcc, 0x43, &disp_cc, 0x8 }, - { "disp_cc_mdss_mdp_lut_clk", &gcc, 0x43, &disp_cc, 0xa }, - { "disp_cc_mdss_non_gdsc_ahb_clk", &gcc, 0x43, &disp_cc, 0x15 }, - { "disp_cc_mdss_pclk0_clk", &gcc, 0x43, &disp_cc, 0x7 }, - { "disp_cc_mdss_rot_clk", &gcc, 0x43, &disp_cc, 0x9 }, - { "disp_cc_mdss_rscc_ahb_clk", &gcc, 0x43, &disp_cc, 0x17 }, - { "disp_cc_mdss_rscc_vsync_clk", &gcc, 0x43, &disp_cc, 0x16 }, - { "disp_cc_mdss_vsync_clk", &gcc, 0x43, &disp_cc, 0xb }, - { "measure_only_disp_cc_sleep_clk", &gcc, 0x43, &disp_cc, 0x1d }, - { "measure_only_disp_cc_xo_clk", &gcc, 0x43, &disp_cc, 0x1e }, + { "disp_cc_mdss_ahb_clk", &disp_cc, 0x14 }, + { "disp_cc_mdss_byte0_clk", &disp_cc, 0xc }, + { "disp_cc_mdss_byte0_intf_clk", &disp_cc, 0xd }, + { "disp_cc_mdss_esc0_clk", &disp_cc, 0xe }, + { "disp_cc_mdss_mdp_clk", &disp_cc, 0x8 }, + { "disp_cc_mdss_mdp_lut_clk", &disp_cc, 0xa }, + { "disp_cc_mdss_non_gdsc_ahb_clk", &disp_cc, 0x15 }, + { "disp_cc_mdss_pclk0_clk", &disp_cc, 0x7 }, + { "disp_cc_mdss_rot_clk", &disp_cc, 0x9 }, + { "disp_cc_mdss_rscc_ahb_clk", &disp_cc, 0x17 }, + { "disp_cc_mdss_rscc_vsync_clk", &disp_cc, 0x16 }, + { "disp_cc_mdss_vsync_clk", &disp_cc, 0xb }, + { "measure_only_disp_cc_sleep_clk", &disp_cc, 0x1d }, + { "measure_only_disp_cc_xo_clk", &disp_cc, 0x1e }, - { "gpu_cc_ahb_clk", &gcc, 0xfb, &gpu_cc, 0x11 }, - { "gpu_cc_cx_gfx3d_clk", &gcc, 0xfb, &gpu_cc, 0x1a }, - { "gpu_cc_cx_gfx3d_slv_clk", &gcc, 0xfb, &gpu_cc, 0x1b }, - { "gpu_cc_cx_gmu_clk", &gcc, 0xfb, &gpu_cc, 0x19 }, - { "gpu_cc_cx_snoc_dvm_clk", &gcc, 0xfb, &gpu_cc, 0x16 }, - { "gpu_cc_cxo_aon_clk", &gcc, 0xfb, &gpu_cc, 0xb }, - { "gpu_cc_cxo_clk", &gcc, 0xfb, &gpu_cc, 0xa }, - { "gpu_cc_gx_cxo_clk", &gcc, 0xfb, &gpu_cc, 0xf }, - { "gpu_cc_gx_gfx3d_clk", &gcc, 0xfb, &gpu_cc, 0xc }, - { "gpu_cc_gx_gmu_clk", &gcc, 0xfb, &gpu_cc, 0x10 }, - { "gpu_cc_sleep_clk", &gcc, 0xfb, &gpu_cc, 0x17 }, + { "gpu_cc_ahb_clk", &gpu_cc, 0x11 }, + { "gpu_cc_cx_gfx3d_clk", &gpu_cc, 0x1a }, + { "gpu_cc_cx_gfx3d_slv_clk", &gpu_cc, 0x1b }, + { "gpu_cc_cx_gmu_clk", &gpu_cc, 0x19 }, + { "gpu_cc_cx_snoc_dvm_clk", &gpu_cc, 0x16 }, + { "gpu_cc_cxo_aon_clk", &gpu_cc, 0xb }, + { "gpu_cc_cxo_clk", &gpu_cc, 0xa }, + { "gpu_cc_gx_cxo_clk", &gpu_cc, 0xf }, + { "gpu_cc_gx_gfx3d_clk", &gpu_cc, 0xc }, + { "gpu_cc_gx_gmu_clk", &gpu_cc, 0x10 }, + { "gpu_cc_sleep_clk", &gpu_cc, 0x17 }, - { "mccc_clk", &gcc, 0xae, &mc_cc, 0x220 }, + { "mccc_clk", &mc_cc, 0x220 }, {} }; diff --git a/sm8150.c b/sm8150.c index 56ce342..4b0c05d 100644 --- a/sm8150.c +++ b/sm8150.c @@ -39,19 +39,23 @@ #include "debugcc.h" -static struct debug_mux gcc = { - .phys = 0x100000, - .size = 0x1f0000, +static struct gcc_mux gcc = { + .mux = { + .phys = 0x100000, + .size = 0x1f0000, - .enable_reg = 0x62008, - .enable_mask = BIT(0), + .measure = measure_gcc, - .mux_reg = 0x62000, - .mux_mask = 0x3ff, + .enable_reg = 0x62008, + .enable_mask = BIT(0), - .div_reg = 0x62004, - .div_mask = 0xf, - .div_val = 1, + .mux_reg = 0x62000, + .mux_mask = 0x3ff, + + .div_reg = 0x62004, + .div_mask = 0xf, + .div_val = 1, + }, .xo_div4_reg = 0x43008, .debug_ctl_reg = 0x62038, @@ -63,6 +67,10 @@ static struct debug_mux cam_cc = { .size = 0x10000, .block_name = "cam", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x55, + .enable_reg = 0xd008, .enable_mask = BIT(0), @@ -79,6 +87,10 @@ static struct debug_mux disp_cc = { .size = 0x10000, .block_name = "disp", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x56, + .enable_reg = 0x500c, .enable_mask = BIT(0), @@ -95,6 +107,10 @@ static struct debug_mux gpu_cc = { .size = 0x9000, .block_name = "gpu", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x162, + .enable_reg = 0x1100, .enable_mask = BIT(0), @@ -111,6 +127,10 @@ static struct debug_mux video_cc = { .size = 0x10000, .block_name = "video", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x57, + .enable_reg = 0x940, .enable_mask = BIT(0), @@ -127,6 +147,10 @@ static struct debug_mux npu_cc = { .size = 0x10000, .block_name = "npu", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x180, + .enable_reg = 0x3008, .enable_mask = BIT(0), @@ -144,6 +168,8 @@ static struct debug_mux mc_cc = { .block_name = "mc", .measure = measure_mccc, + .parent = &gcc.mux, + .parent_mux_val = 0xd0, }; static struct debug_mux cpu_cc = { @@ -151,6 +177,10 @@ static struct debug_mux cpu_cc = { .size = 0x1000, .block_name = "cpu", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0xe8, + .enable_reg = 0x18, .enable_mask = BIT(0), @@ -165,269 +195,262 @@ static struct debug_mux cpu_cc = { }; static struct measure_clk sm8150_clocks[] = { - { "cam_cc_bps_ahb_clk", &gcc, 0x55, &cam_cc, 0xe }, - { "cam_cc_bps_areg_clk", &gcc, 0x55, &cam_cc, 0xd }, - { "cam_cc_bps_axi_clk", &gcc, 0x55, &cam_cc, 0xc }, - { "cam_cc_bps_clk", &gcc, 0x55, &cam_cc, 0xb }, - { "cam_cc_camnoc_axi_clk", &gcc, 0x55, &cam_cc, 0x27 }, - { "cam_cc_camnoc_dcd_xo_clk", &gcc, 0x55, &cam_cc, 0x33 }, - { "cam_cc_cci_0_clk", &gcc, 0x55, &cam_cc, 0x2a }, - { "cam_cc_cci_1_clk", &gcc, 0x55, &cam_cc, 0x3b }, - { "cam_cc_core_ahb_clk", &gcc, 0x55, &cam_cc, 0x2e }, - { "cam_cc_cpas_ahb_clk", &gcc, 0x55, &cam_cc, 0x2c }, - { "cam_cc_csi0phytimer_clk", &gcc, 0x55, &cam_cc, 0x5 }, - { "cam_cc_csi1phytimer_clk", &gcc, 0x55, &cam_cc, 0x7 }, - { "cam_cc_csi2phytimer_clk", &gcc, 0x55, &cam_cc, 0x9 }, - { "cam_cc_csi3phytimer_clk", &gcc, 0x55, &cam_cc, 0x35 }, - { "cam_cc_csiphy0_clk", &gcc, 0x55, &cam_cc, 0x6 }, - { "cam_cc_csiphy1_clk", &gcc, 0x55, &cam_cc, 0x8 }, - { "cam_cc_csiphy2_clk", &gcc, 0x55, &cam_cc, 0xa }, - { "cam_cc_csiphy3_clk", &gcc, 0x55, &cam_cc, 0x36 }, - { "cam_cc_fd_core_clk", &gcc, 0x55, &cam_cc, 0x28 }, - { "cam_cc_fd_core_uar_clk", &gcc, 0x55, &cam_cc, 0x29 }, - { "cam_cc_icp_ahb_clk", &gcc, 0x55, &cam_cc, 0x37 }, - { "cam_cc_icp_clk", &gcc, 0x55, &cam_cc, 0x26 }, - { "cam_cc_ife_0_axi_clk", &gcc, 0x55, &cam_cc, 0x1b }, - { "cam_cc_ife_0_clk", &gcc, 0x55, &cam_cc, 0x17 }, - { "cam_cc_ife_0_cphy_rx_clk", &gcc, 0x55, &cam_cc, 0x1a }, - { "cam_cc_ife_0_csid_clk", &gcc, 0x55, &cam_cc, 0x19 }, - { "cam_cc_ife_0_dsp_clk", &gcc, 0x55, &cam_cc, 0x18 }, - { "cam_cc_ife_1_axi_clk", &gcc, 0x55, &cam_cc, 0x21 }, - { "cam_cc_ife_1_clk", &gcc, 0x55, &cam_cc, 0x1d }, - { "cam_cc_ife_1_cphy_rx_clk", &gcc, 0x55, &cam_cc, 0x20 }, - { "cam_cc_ife_1_csid_clk", &gcc, 0x55, &cam_cc, 0x1f }, - { "cam_cc_ife_1_dsp_clk", &gcc, 0x55, &cam_cc, 0x1e }, - { "cam_cc_ife_lite_0_clk", &gcc, 0x55, &cam_cc, 0x22 }, - { "cam_cc_ife_lite_0_cphy_rx_clk", &gcc, 0x55, &cam_cc, 0x24 }, - { "cam_cc_ife_lite_0_csid_clk", &gcc, 0x55, &cam_cc, 0x23 }, - { "cam_cc_ife_lite_1_clk", &gcc, 0x55, &cam_cc, 0x38 }, - { "cam_cc_ife_lite_1_cphy_rx_clk", &gcc, 0x55, &cam_cc, 0x3a }, - { "cam_cc_ife_lite_1_csid_clk", &gcc, 0x55, &cam_cc, 0x39 }, - { "cam_cc_ipe_0_ahb_clk", &gcc, 0x55, &cam_cc, 0x12 }, - { "cam_cc_ipe_0_areg_clk", &gcc, 0x55, &cam_cc, 0x11 }, - { "cam_cc_ipe_0_axi_clk", &gcc, 0x55, &cam_cc, 0x10 }, - { "cam_cc_ipe_0_clk", &gcc, 0x55, &cam_cc, 0xf }, - { "cam_cc_ipe_1_ahb_clk", &gcc, 0x55, &cam_cc, 0x16 }, - { "cam_cc_ipe_1_areg_clk", &gcc, 0x55, &cam_cc, 0x15 }, - { "cam_cc_ipe_1_axi_clk", &gcc, 0x55, &cam_cc, 0x14 }, - { "cam_cc_ipe_1_clk", &gcc, 0x55, &cam_cc, 0x13 }, - { "cam_cc_jpeg_clk", &gcc, 0x55, &cam_cc, 0x25 }, - { "cam_cc_lrme_clk", &gcc, 0x55, &cam_cc, 0x2b }, - { "cam_cc_mclk0_clk", &gcc, 0x55, &cam_cc, 0x1 }, - { "cam_cc_mclk1_clk", &gcc, 0x55, &cam_cc, 0x2 }, - { "cam_cc_mclk2_clk", &gcc, 0x55, &cam_cc, 0x3 }, - { "cam_cc_mclk3_clk", &gcc, 0x55, &cam_cc, 0x4 }, - - { "disp_cc_mdss_ahb_clk", &gcc, 0x56, &disp_cc, 0x2b }, - { "disp_cc_mdss_byte0_clk", &gcc, 0x56, &disp_cc, 0x15 }, - { "disp_cc_mdss_byte0_intf_clk", &gcc, 0x56, &disp_cc, 0x16 }, - { "disp_cc_mdss_byte1_clk", &gcc, 0x56, &disp_cc, 0x17 }, - { "disp_cc_mdss_byte1_intf_clk", &gcc, 0x56, &disp_cc, 0x18 }, - { "disp_cc_mdss_dp_aux1_clk", &gcc, 0x56, &disp_cc, 0x25 }, - { "disp_cc_mdss_dp_aux_clk", &gcc, 0x56, &disp_cc, 0x20 }, - { "disp_cc_mdss_dp_crypto1_clk", &gcc, 0x56, &disp_cc, 0x24 }, - { "disp_cc_mdss_dp_crypto_clk", &gcc, 0x56, &disp_cc, 0x1d }, - { "disp_cc_mdss_dp_link1_clk", &gcc, 0x56, &disp_cc, 0x22 }, - { "disp_cc_mdss_dp_link1_intf_clk", &gcc, 0x56, &disp_cc, 0x23 }, - { "disp_cc_mdss_dp_link_clk", &gcc, 0x56, &disp_cc, 0x1b }, - { "disp_cc_mdss_dp_link_intf_clk", &gcc, 0x56, &disp_cc, 0x1c }, - { "disp_cc_mdss_dp_pixel1_clk", &gcc, 0x56, &disp_cc, 0x1f }, - { "disp_cc_mdss_dp_pixel2_clk", &gcc, 0x56, &disp_cc, 0x21 }, - { "disp_cc_mdss_dp_pixel_clk", &gcc, 0x56, &disp_cc, 0x1e }, - { "disp_cc_mdss_edp_aux_clk", &gcc, 0x56, &disp_cc, 0x29 }, - { "disp_cc_mdss_edp_gtc_clk", &gcc, 0x56, &disp_cc, 0x2a }, - { "disp_cc_mdss_edp_link_clk", &gcc, 0x56, &disp_cc, 0x27 }, - { "disp_cc_mdss_edp_link_intf_clk", &gcc, 0x56, &disp_cc, 0x28 }, - { "disp_cc_mdss_edp_pixel_clk", &gcc, 0x56, &disp_cc, 0x26 }, - { "disp_cc_mdss_esc0_clk", &gcc, 0x56, &disp_cc, 0x19 }, - { "disp_cc_mdss_esc1_clk", &gcc, 0x56, &disp_cc, 0x1a }, - { "disp_cc_mdss_mdp_clk", &gcc, 0x56, &disp_cc, 0x11 }, - { "disp_cc_mdss_mdp_lut_clk", &gcc, 0x56, &disp_cc, 0x13 }, - { "disp_cc_mdss_non_gdsc_ahb_clk", &gcc, 0x56, &disp_cc, 0x2c }, - { "disp_cc_mdss_pclk0_clk", &gcc, 0x56, &disp_cc, 0xf }, - { "disp_cc_mdss_pclk1_clk", &gcc, 0x56, &disp_cc, 0x10 }, - { "disp_cc_mdss_rot_clk", &gcc, 0x56, &disp_cc, 0x12 }, - { "disp_cc_mdss_rscc_ahb_clk", &gcc, 0x56, &disp_cc, 0x2e }, - { "disp_cc_mdss_rscc_vsync_clk", &gcc, 0x56, &disp_cc, 0x2d }, - { "disp_cc_mdss_vsync_clk", &gcc, 0x56, &disp_cc, 0x14 }, - { "disp_cc_xo_clk", &gcc, 0x56, &disp_cc, 0x36 }, - - // { "cpu_cc_debug_mux", &gcc, 0xe8 }, - // { "cam_cc_debug_mux", &gcc, 0x55 }, - // { "disp_cc_debug_mux", &gcc, 0x56 }, - { "measure_only_cdsp_clk", &gcc, 0xdb, NULL, 0, 2 }, - { "measure_only_snoc_clk", &gcc, 0x7 }, - { "measure_only_cnoc_clk", &gcc, 0x19 }, - { "measure_only_mccc_clk", &gcc, 0xd0, &mc_cc, 0x50 }, - { "measure_only_ipa_2x_clk", &gcc, 0x147 }, - { "gcc_aggre_noc_pcie_tbu_clk", &gcc, 0x36 }, - { "gcc_aggre_ufs_card_axi_clk", &gcc, 0x141 }, - { "gcc_aggre_ufs_phy_axi_clk", &gcc, 0x140 }, - { "gcc_aggre_usb3_prim_axi_clk", &gcc, 0x13e }, - { "gcc_aggre_usb3_sec_axi_clk", &gcc, 0x13f }, - { "gcc_camera_ahb_clk", &gcc, 0x43 }, - { "gcc_camera_hf_axi_clk", &gcc, 0x4d }, - { "gcc_camera_sf_axi_clk", &gcc, 0x4e }, - { "gcc_camera_xo_clk", &gcc, 0x52 }, - { "gcc_ce1_ahb_clk", &gcc, 0xb6 }, - { "gcc_ce1_axi_clk", &gcc, 0xb5 }, - { "gcc_ce1_clk", &gcc, 0xb4 }, - { "gcc_cfg_noc_usb3_prim_axi_clk", &gcc, 0x22 }, - { "gcc_cfg_noc_usb3_sec_axi_clk", &gcc, 0x23 }, - { "gcc_cpuss_ahb_clk", &gcc, 0xe0 }, - { "gcc_cpuss_rbcpr_clk", &gcc, 0xe2 }, - { "gcc_ddrss_gpu_axi_clk", &gcc, 0xc0 }, - { "gcc_disp_ahb_clk", &gcc, 0x44 }, - { "gcc_disp_hf_axi_clk", &gcc, 0x4f }, - { "gcc_disp_sf_axi_clk", &gcc, 0x50 }, - { "gcc_disp_xo_clk", &gcc, 0x53 }, - { "gcc_emac_axi_clk", &gcc, 0x18d }, - { "gcc_emac_ptp_clk", &gcc, 0x190 }, - { "gcc_emac_rgmii_clk", &gcc, 0x18f }, - { "gcc_emac_slv_ahb_clk", &gcc, 0x18e }, - { "gcc_gp1_clk", &gcc, 0xf0 }, - { "gcc_gp2_clk", &gcc, 0xf1 }, - { "gcc_gp3_clk", &gcc, 0xf2 }, - { "gcc_gpu_cfg_ahb_clk", &gcc, 0x160 }, - { "gcc_gpu_gpll0_clk_src", &gcc, 0x166 }, - { "gcc_gpu_gpll0_div_clk_src", &gcc, 0x167 }, - { "gcc_gpu_memnoc_gfx_clk", &gcc, 0x163 }, - { "gcc_gpu_snoc_dvm_gfx_clk", &gcc, 0x165 }, - { "gcc_npu_at_clk", &gcc, 0x17d }, - { "gcc_npu_axi_clk", &gcc, 0x17b }, - { "gcc_npu_cfg_ahb_clk", &gcc, 0x17a }, - { "gcc_npu_gpll0_clk_src", &gcc, 0x17e }, - { "gcc_npu_gpll0_div_clk_src", &gcc, 0x17f }, - { "gcc_npu_trig_clk", &gcc, 0x17c }, - { "gcc_pcie0_phy_refgen_clk", &gcc, 0x104 }, - { "gcc_pcie1_phy_refgen_clk", &gcc, 0x105 }, - { "gcc_pcie_0_aux_clk", &gcc, 0xf7 }, - { "gcc_pcie_0_cfg_ahb_clk", &gcc, 0xf6 }, - { "gcc_pcie_0_mstr_axi_clk", &gcc, 0xf5 }, - { "gcc_pcie_0_pipe_clk", &gcc, 0xf8 }, - { "gcc_pcie_0_slv_axi_clk", &gcc, 0xf4 }, - { "gcc_pcie_0_slv_q2a_axi_clk", &gcc, 0xf3 }, - { "gcc_pcie_1_aux_clk", &gcc, 0xff }, - { "gcc_pcie_1_cfg_ahb_clk", &gcc, 0xfe }, - { "gcc_pcie_1_mstr_axi_clk", &gcc, 0xfd }, - { "gcc_pcie_1_pipe_clk", &gcc, 0x100 }, - { "gcc_pcie_1_slv_axi_clk", &gcc, 0xfc }, - { "gcc_pcie_1_slv_q2a_axi_clk", &gcc, 0xfb }, - { "gcc_pcie_phy_aux_clk", &gcc, 0x103 }, - { "gcc_pdm2_clk", &gcc, 0x9a }, - { "gcc_pdm_ahb_clk", &gcc, 0x98 }, - { "gcc_pdm_xo4_clk", &gcc, 0x99 }, - { "gcc_prng_ahb_clk", &gcc, 0x9b }, - { "gcc_qspi_cnoc_periph_ahb_clk", &gcc, 0x178 }, - { "gcc_qspi_core_clk", &gcc, 0x179 }, - { "gcc_qupv3_wrap0_core_2x_clk", &gcc, 0x85 }, - { "gcc_qupv3_wrap0_core_clk", &gcc, 0x84 }, - { "gcc_qupv3_wrap0_s0_clk", &gcc, 0x86 }, - { "gcc_qupv3_wrap0_s1_clk", &gcc, 0x87 }, - { "gcc_qupv3_wrap0_s2_clk", &gcc, 0x88 }, - { "gcc_qupv3_wrap0_s3_clk", &gcc, 0x89 }, - { "gcc_qupv3_wrap0_s4_clk", &gcc, 0x8a }, - { "gcc_qupv3_wrap0_s5_clk", &gcc, 0x8b }, - { "gcc_qupv3_wrap0_s6_clk", &gcc, 0x8c }, - { "gcc_qupv3_wrap0_s7_clk", &gcc, 0x8d }, - { "gcc_qupv3_wrap1_core_2x_clk", &gcc, 0x91 }, - { "gcc_qupv3_wrap1_core_clk", &gcc, 0x90 }, - { "gcc_qupv3_wrap1_s0_clk", &gcc, 0x92 }, - { "gcc_qupv3_wrap1_s1_clk", &gcc, 0x93 }, - { "gcc_qupv3_wrap1_s2_clk", &gcc, 0x94 }, - { "gcc_qupv3_wrap1_s3_clk", &gcc, 0x95 }, - { "gcc_qupv3_wrap1_s4_clk", &gcc, 0x96 }, - { "gcc_qupv3_wrap1_s5_clk", &gcc, 0x97 }, - { "gcc_qupv3_wrap2_core_2x_clk", &gcc, 0x184 }, - { "gcc_qupv3_wrap2_core_clk", &gcc, 0x183 }, - { "gcc_qupv3_wrap2_s0_clk", &gcc, 0x185 }, - { "gcc_qupv3_wrap2_s1_clk", &gcc, 0x186 }, - { "gcc_qupv3_wrap2_s2_clk", &gcc, 0x187 }, - { "gcc_qupv3_wrap2_s3_clk", &gcc, 0x188 }, - { "gcc_qupv3_wrap2_s4_clk", &gcc, 0x189 }, - { "gcc_qupv3_wrap2_s5_clk", &gcc, 0x18a }, - { "gcc_sdcc2_ahb_clk", &gcc, 0x7f }, - { "gcc_sdcc2_apps_clk", &gcc, 0x7e }, - { "gcc_sdcc4_ahb_clk", &gcc, 0x81 }, - { "gcc_sdcc4_apps_clk", &gcc, 0x80 }, - { "gcc_sys_noc_cpuss_ahb_clk", &gcc, 0xc }, - { "gcc_tsif_ahb_clk", &gcc, 0x9c }, - { "gcc_tsif_ref_clk", &gcc, 0x9d }, - { "gcc_ufs_card_ahb_clk", &gcc, 0x107 }, - { "gcc_ufs_card_axi_clk", &gcc, 0x106 }, - { "gcc_ufs_card_ice_core_clk", &gcc, 0x10d }, - { "gcc_ufs_card_phy_aux_clk", &gcc, 0x10e }, - { "gcc_ufs_card_rx_symbol_0_clk", &gcc, 0x109 }, - { "gcc_ufs_card_rx_symbol_1_clk", &gcc, 0x10f }, - { "gcc_ufs_card_tx_symbol_0_clk", &gcc, 0x108 }, - { "gcc_ufs_card_unipro_core_clk", &gcc, 0x10c }, - { "gcc_ufs_phy_ahb_clk", &gcc, 0x113 }, - { "gcc_ufs_phy_axi_clk", &gcc, 0x112 }, - { "gcc_ufs_phy_ice_core_clk", &gcc, 0x119 }, - { "gcc_ufs_phy_phy_aux_clk", &gcc, 0x11a }, - { "gcc_ufs_phy_rx_symbol_0_clk", &gcc, 0x115 }, - { "gcc_ufs_phy_rx_symbol_1_clk", &gcc, 0x11b }, - { "gcc_ufs_phy_tx_symbol_0_clk", &gcc, 0x114 }, - { "gcc_ufs_phy_unipro_core_clk", &gcc, 0x118 }, - { "gcc_usb30_prim_master_clk", &gcc, 0x6b }, - { "gcc_usb30_prim_mock_utmi_clk", &gcc, 0x6d }, - { "gcc_usb30_sec_master_clk", &gcc, 0x72 }, - { "gcc_usb30_sec_mock_utmi_clk", &gcc, 0x74 }, - { "gcc_usb3_prim_phy_aux_clk", &gcc, 0x6e }, - { "gcc_usb3_prim_phy_com_aux_clk", &gcc, 0x6f }, - { "gcc_usb3_prim_phy_pipe_clk", &gcc, 0x70 }, - { "gcc_usb3_sec_phy_aux_clk", &gcc, 0x75 }, - { "gcc_usb3_sec_phy_com_aux_clk", &gcc, 0x76 }, - { "gcc_usb3_sec_phy_pipe_clk", &gcc, 0x77 }, - { "gcc_video_ahb_clk", &gcc, 0x42 }, - { "gcc_video_axi0_clk", &gcc, 0x4a }, - { "gcc_video_axi1_clk", &gcc, 0x4b }, - { "gcc_video_axic_clk", &gcc, 0x4c }, - { "gcc_video_xo_clk", &gcc, 0x51 }, - // { "gpu_cc_debug_mux", &gcc, 0x162 }, - // { "mc_cc_debug_mux", &gcc, 0xd0 }, - // { "npu_cc_debug_mux", &gcc, 0x180 }, - // { "video_cc_debug_mux", &gcc, 0x57 }, - - { "gpu_cc_ahb_clk", &gcc, 0x162, &gpu_cc, 0x10 }, - { "gpu_cc_cx_apb_clk", &gcc, 0x162, &gpu_cc, 0x14 }, - { "gpu_cc_cx_gmu_clk", &gcc, 0x162, &gpu_cc, 0x18 }, - { "gpu_cc_cx_qdss_at_clk", &gcc, 0x162, &gpu_cc, 0x12 }, - { "gpu_cc_cx_qdss_trig_clk", &gcc, 0x162, &gpu_cc, 0x17 }, - { "gpu_cc_cx_snoc_dvm_clk", &gcc, 0x162, &gpu_cc, 0x15 }, - { "gpu_cc_cxo_aon_clk", &gcc, 0x162, &gpu_cc, 0xa }, - { "gpu_cc_cxo_clk", &gcc, 0x162, &gpu_cc, 0x19 }, - { "gpu_cc_gx_gmu_clk", &gcc, 0x162, &gpu_cc, 0xf }, - { "gpu_cc_gx_vsense_clk", &gcc, 0x162, &gpu_cc, 0xc }, - { "measure_only_gpu_cc_cx_gfx3d_clk", &gcc, 0x162, &gpu_cc, 0x1a }, - { "measure_only_gpu_cc_cx_gfx3d_slv_clk", &gcc, 0x162, &gpu_cc, 0x1b }, - { "measure_only_gpu_cc_gx_gfx3d_clk", &gcc, 0x162, &gpu_cc, 0xb }, - - { "npu_cc_armwic_core_clk", &gcc, 0x180, &npu_cc, 0x4 }, - { "npu_cc_bto_core_clk", &gcc, 0x180, &npu_cc, 0x12 }, - { "npu_cc_bwmon_clk", &gcc, 0x180, &npu_cc, 0xf }, - { "npu_cc_cal_dp_cdc_clk", &gcc, 0x180, &npu_cc, 0x8 }, - { "npu_cc_cal_dp_clk", &gcc, 0x180, &npu_cc, 0x1 }, - { "npu_cc_comp_noc_axi_clk", &gcc, 0x180, &npu_cc, 0x9 }, - { "npu_cc_conf_noc_ahb_clk", &gcc, 0x180, &npu_cc, 0xa }, - { "npu_cc_npu_core_apb_clk", &gcc, 0x180, &npu_cc, 0xe }, - { "npu_cc_npu_core_atb_clk", &gcc, 0x180, &npu_cc, 0xb }, - { "npu_cc_npu_core_clk", &gcc, 0x180, &npu_cc, 0x2 }, - { "npu_cc_npu_core_cti_clk", &gcc, 0x180, &npu_cc, 0xc }, - { "npu_cc_npu_cpc_clk", &gcc, 0x180, &npu_cc, 0x3 }, - { "npu_cc_perf_cnt_clk", &gcc, 0x180, &npu_cc, 0x10 }, - { "npu_cc_xo_clk", &gcc, 0x180, &npu_cc, 0x11 }, - - { "video_cc_iris_ahb_clk", &gcc, 0x57, &video_cc, 0x7 }, - { "video_cc_mvs0_core_clk", &gcc, 0x57, &video_cc, 0x3 }, - { "video_cc_mvs1_core_clk", &gcc, 0x57, &video_cc, 0x5 }, - { "video_cc_mvsc_core_clk", &gcc, 0x57, &video_cc, 0x1 }, - { "video_cc_xo_clk", &gcc, 0x57, &video_cc, 0x8 }, - - { "l3_clk", &gcc, 0xe8, &cpu_cc, 0x46, 16 }, - { "pwrcl_clk", &gcc, 0xe8, &cpu_cc, 0x44, 16 }, - { "perfcl_clk", &gcc, 0xe8, &cpu_cc, 0x45, 16 }, - { "perfpcl_clk", &gcc, 0xe8, &cpu_cc, 0x47, 16 }, + { "cam_cc_bps_ahb_clk", &cam_cc, 0xe }, + { "cam_cc_bps_areg_clk", &cam_cc, 0xd }, + { "cam_cc_bps_axi_clk", &cam_cc, 0xc }, + { "cam_cc_bps_clk", &cam_cc, 0xb }, + { "cam_cc_camnoc_axi_clk", &cam_cc, 0x27 }, + { "cam_cc_camnoc_dcd_xo_clk", &cam_cc, 0x33 }, + { "cam_cc_cci_0_clk", &cam_cc, 0x2a }, + { "cam_cc_cci_1_clk", &cam_cc, 0x3b }, + { "cam_cc_core_ahb_clk", &cam_cc, 0x2e }, + { "cam_cc_cpas_ahb_clk", &cam_cc, 0x2c }, + { "cam_cc_csi0phytimer_clk", &cam_cc, 0x5 }, + { "cam_cc_csi1phytimer_clk", &cam_cc, 0x7 }, + { "cam_cc_csi2phytimer_clk", &cam_cc, 0x9 }, + { "cam_cc_csi3phytimer_clk", &cam_cc, 0x35 }, + { "cam_cc_csiphy0_clk", &cam_cc, 0x6 }, + { "cam_cc_csiphy1_clk", &cam_cc, 0x8 }, + { "cam_cc_csiphy2_clk", &cam_cc, 0xa }, + { "cam_cc_csiphy3_clk", &cam_cc, 0x36 }, + { "cam_cc_fd_core_clk", &cam_cc, 0x28 }, + { "cam_cc_fd_core_uar_clk", &cam_cc, 0x29 }, + { "cam_cc_icp_ahb_clk", &cam_cc, 0x37 }, + { "cam_cc_icp_clk", &cam_cc, 0x26 }, + { "cam_cc_ife_0_axi_clk", &cam_cc, 0x1b }, + { "cam_cc_ife_0_clk", &cam_cc, 0x17 }, + { "cam_cc_ife_0_cphy_rx_clk", &cam_cc, 0x1a }, + { "cam_cc_ife_0_csid_clk", &cam_cc, 0x19 }, + { "cam_cc_ife_0_dsp_clk", &cam_cc, 0x18 }, + { "cam_cc_ife_1_axi_clk", &cam_cc, 0x21 }, + { "cam_cc_ife_1_clk", &cam_cc, 0x1d }, + { "cam_cc_ife_1_cphy_rx_clk", &cam_cc, 0x20 }, + { "cam_cc_ife_1_csid_clk", &cam_cc, 0x1f }, + { "cam_cc_ife_1_dsp_clk", &cam_cc, 0x1e }, + { "cam_cc_ife_lite_0_clk", &cam_cc, 0x22 }, + { "cam_cc_ife_lite_0_cphy_rx_clk", &cam_cc, 0x24 }, + { "cam_cc_ife_lite_0_csid_clk", &cam_cc, 0x23 }, + { "cam_cc_ife_lite_1_clk", &cam_cc, 0x38 }, + { "cam_cc_ife_lite_1_cphy_rx_clk", &cam_cc, 0x3a }, + { "cam_cc_ife_lite_1_csid_clk", &cam_cc, 0x39 }, + { "cam_cc_ipe_0_ahb_clk", &cam_cc, 0x12 }, + { "cam_cc_ipe_0_areg_clk", &cam_cc, 0x11 }, + { "cam_cc_ipe_0_axi_clk", &cam_cc, 0x10 }, + { "cam_cc_ipe_0_clk", &cam_cc, 0xf }, + { "cam_cc_ipe_1_ahb_clk", &cam_cc, 0x16 }, + { "cam_cc_ipe_1_areg_clk", &cam_cc, 0x15 }, + { "cam_cc_ipe_1_axi_clk", &cam_cc, 0x14 }, + { "cam_cc_ipe_1_clk", &cam_cc, 0x13 }, + { "cam_cc_jpeg_clk", &cam_cc, 0x25 }, + { "cam_cc_lrme_clk", &cam_cc, 0x2b }, + { "cam_cc_mclk0_clk", &cam_cc, 0x1 }, + { "cam_cc_mclk1_clk", &cam_cc, 0x2 }, + { "cam_cc_mclk2_clk", &cam_cc, 0x3 }, + { "cam_cc_mclk3_clk", &cam_cc, 0x4 }, + + { "disp_cc_mdss_ahb_clk", &disp_cc, 0x2b }, + { "disp_cc_mdss_byte0_clk", &disp_cc, 0x15 }, + { "disp_cc_mdss_byte0_intf_clk", &disp_cc, 0x16 }, + { "disp_cc_mdss_byte1_clk", &disp_cc, 0x17 }, + { "disp_cc_mdss_byte1_intf_clk", &disp_cc, 0x18 }, + { "disp_cc_mdss_dp_aux1_clk", &disp_cc, 0x25 }, + { "disp_cc_mdss_dp_aux_clk", &disp_cc, 0x20 }, + { "disp_cc_mdss_dp_crypto1_clk", &disp_cc, 0x24 }, + { "disp_cc_mdss_dp_crypto_clk", &disp_cc, 0x1d }, + { "disp_cc_mdss_dp_link1_clk", &disp_cc, 0x22 }, + { "disp_cc_mdss_dp_link1_intf_clk", &disp_cc, 0x23 }, + { "disp_cc_mdss_dp_link_clk", &disp_cc, 0x1b }, + { "disp_cc_mdss_dp_link_intf_clk", &disp_cc, 0x1c }, + { "disp_cc_mdss_dp_pixel1_clk", &disp_cc, 0x1f }, + { "disp_cc_mdss_dp_pixel2_clk", &disp_cc, 0x21 }, + { "disp_cc_mdss_dp_pixel_clk", &disp_cc, 0x1e }, + { "disp_cc_mdss_edp_aux_clk", &disp_cc, 0x29 }, + { "disp_cc_mdss_edp_gtc_clk", &disp_cc, 0x2a }, + { "disp_cc_mdss_edp_link_clk", &disp_cc, 0x27 }, + { "disp_cc_mdss_edp_link_intf_clk", &disp_cc, 0x28 }, + { "disp_cc_mdss_edp_pixel_clk", &disp_cc, 0x26 }, + { "disp_cc_mdss_esc0_clk", &disp_cc, 0x19 }, + { "disp_cc_mdss_esc1_clk", &disp_cc, 0x1a }, + { "disp_cc_mdss_mdp_clk", &disp_cc, 0x11 }, + { "disp_cc_mdss_mdp_lut_clk", &disp_cc, 0x13 }, + { "disp_cc_mdss_non_gdsc_ahb_clk", &disp_cc, 0x2c }, + { "disp_cc_mdss_pclk0_clk", &disp_cc, 0xf }, + { "disp_cc_mdss_pclk1_clk", &disp_cc, 0x10 }, + { "disp_cc_mdss_rot_clk", &disp_cc, 0x12 }, + { "disp_cc_mdss_rscc_ahb_clk", &disp_cc, 0x2e }, + { "disp_cc_mdss_rscc_vsync_clk", &disp_cc, 0x2d }, + { "disp_cc_mdss_vsync_clk", &disp_cc, 0x14 }, + { "disp_cc_xo_clk", &disp_cc, 0x36 }, + + { "measure_only_cdsp_clk", &gcc.mux, 0xdb, 2 }, + { "measure_only_snoc_clk", &gcc.mux, 0x7 }, + { "measure_only_cnoc_clk", &gcc.mux, 0x19 }, + { "measure_only_mccc_clk", &mc_cc, 0x50 }, + { "measure_only_ipa_2x_clk", &gcc.mux, 0x147 }, + { "gcc_aggre_noc_pcie_tbu_clk", &gcc.mux, 0x36 }, + { "gcc_aggre_ufs_card_axi_clk", &gcc.mux, 0x141 }, + { "gcc_aggre_ufs_phy_axi_clk", &gcc.mux, 0x140 }, + { "gcc_aggre_usb3_prim_axi_clk", &gcc.mux, 0x13e }, + { "gcc_aggre_usb3_sec_axi_clk", &gcc.mux, 0x13f }, + { "gcc_camera_ahb_clk", &gcc.mux, 0x43 }, + { "gcc_camera_hf_axi_clk", &gcc.mux, 0x4d }, + { "gcc_camera_sf_axi_clk", &gcc.mux, 0x4e }, + { "gcc_camera_xo_clk", &gcc.mux, 0x52 }, + { "gcc_ce1_ahb_clk", &gcc.mux, 0xb6 }, + { "gcc_ce1_axi_clk", &gcc.mux, 0xb5 }, + { "gcc_ce1_clk", &gcc.mux, 0xb4 }, + { "gcc_cfg_noc_usb3_prim_axi_clk", &gcc.mux, 0x22 }, + { "gcc_cfg_noc_usb3_sec_axi_clk", &gcc.mux, 0x23 }, + { "gcc_cpuss_ahb_clk", &gcc.mux, 0xe0 }, + { "gcc_cpuss_rbcpr_clk", &gcc.mux, 0xe2 }, + { "gcc_ddrss_gpu_axi_clk", &gcc.mux, 0xc0 }, + { "gcc_disp_ahb_clk", &gcc.mux, 0x44 }, + { "gcc_disp_hf_axi_clk", &gcc.mux, 0x4f }, + { "gcc_disp_sf_axi_clk", &gcc.mux, 0x50 }, + { "gcc_disp_xo_clk", &gcc.mux, 0x53 }, + { "gcc_emac_axi_clk", &gcc.mux, 0x18d }, + { "gcc_emac_ptp_clk", &gcc.mux, 0x190 }, + { "gcc_emac_rgmii_clk", &gcc.mux, 0x18f }, + { "gcc_emac_slv_ahb_clk", &gcc.mux, 0x18e }, + { "gcc_gp1_clk", &gcc.mux, 0xf0 }, + { "gcc_gp2_clk", &gcc.mux, 0xf1 }, + { "gcc_gp3_clk", &gcc.mux, 0xf2 }, + { "gcc_gpu_cfg_ahb_clk", &gcc.mux, 0x160 }, + { "gcc_gpu_gpll0_clk_src", &gcc.mux, 0x166 }, + { "gcc_gpu_gpll0_div_clk_src", &gcc.mux, 0x167 }, + { "gcc_gpu_memnoc_gfx_clk", &gcc.mux, 0x163 }, + { "gcc_gpu_snoc_dvm_gfx_clk", &gcc.mux, 0x165 }, + { "gcc_npu_at_clk", &gcc.mux, 0x17d }, + { "gcc_npu_axi_clk", &gcc.mux, 0x17b }, + { "gcc_npu_cfg_ahb_clk", &gcc.mux, 0x17a }, + { "gcc_npu_gpll0_clk_src", &gcc.mux, 0x17e }, + { "gcc_npu_gpll0_div_clk_src", &gcc.mux, 0x17f }, + { "gcc_npu_trig_clk", &gcc.mux, 0x17c }, + { "gcc_pcie0_phy_refgen_clk", &gcc.mux, 0x104 }, + { "gcc_pcie1_phy_refgen_clk", &gcc.mux, 0x105 }, + { "gcc_pcie_0_aux_clk", &gcc.mux, 0xf7 }, + { "gcc_pcie_0_cfg_ahb_clk", &gcc.mux, 0xf6 }, + { "gcc_pcie_0_mstr_axi_clk", &gcc.mux, 0xf5 }, + { "gcc_pcie_0_pipe_clk", &gcc.mux, 0xf8 }, + { "gcc_pcie_0_slv_axi_clk", &gcc.mux, 0xf4 }, + { "gcc_pcie_0_slv_q2a_axi_clk", &gcc.mux, 0xf3 }, + { "gcc_pcie_1_aux_clk", &gcc.mux, 0xff }, + { "gcc_pcie_1_cfg_ahb_clk", &gcc.mux, 0xfe }, + { "gcc_pcie_1_mstr_axi_clk", &gcc.mux, 0xfd }, + { "gcc_pcie_1_pipe_clk", &gcc.mux, 0x100 }, + { "gcc_pcie_1_slv_axi_clk", &gcc.mux, 0xfc }, + { "gcc_pcie_1_slv_q2a_axi_clk", &gcc.mux, 0xfb }, + { "gcc_pcie_phy_aux_clk", &gcc.mux, 0x103 }, + { "gcc_pdm2_clk", &gcc.mux, 0x9a }, + { "gcc_pdm_ahb_clk", &gcc.mux, 0x98 }, + { "gcc_pdm_xo4_clk", &gcc.mux, 0x99 }, + { "gcc_prng_ahb_clk", &gcc.mux, 0x9b }, + { "gcc_qspi_cnoc_periph_ahb_clk", &gcc.mux, 0x178 }, + { "gcc_qspi_core_clk", &gcc.mux, 0x179 }, + { "gcc_qupv3_wrap0_core_2x_clk", &gcc.mux, 0x85 }, + { "gcc_qupv3_wrap0_core_clk", &gcc.mux, 0x84 }, + { "gcc_qupv3_wrap0_s0_clk", &gcc.mux, 0x86 }, + { "gcc_qupv3_wrap0_s1_clk", &gcc.mux, 0x87 }, + { "gcc_qupv3_wrap0_s2_clk", &gcc.mux, 0x88 }, + { "gcc_qupv3_wrap0_s3_clk", &gcc.mux, 0x89 }, + { "gcc_qupv3_wrap0_s4_clk", &gcc.mux, 0x8a }, + { "gcc_qupv3_wrap0_s5_clk", &gcc.mux, 0x8b }, + { "gcc_qupv3_wrap0_s6_clk", &gcc.mux, 0x8c }, + { "gcc_qupv3_wrap0_s7_clk", &gcc.mux, 0x8d }, + { "gcc_qupv3_wrap1_core_2x_clk", &gcc.mux, 0x91 }, + { "gcc_qupv3_wrap1_core_clk", &gcc.mux, 0x90 }, + { "gcc_qupv3_wrap1_s0_clk", &gcc.mux, 0x92 }, + { "gcc_qupv3_wrap1_s1_clk", &gcc.mux, 0x93 }, + { "gcc_qupv3_wrap1_s2_clk", &gcc.mux, 0x94 }, + { "gcc_qupv3_wrap1_s3_clk", &gcc.mux, 0x95 }, + { "gcc_qupv3_wrap1_s4_clk", &gcc.mux, 0x96 }, + { "gcc_qupv3_wrap1_s5_clk", &gcc.mux, 0x97 }, + { "gcc_qupv3_wrap2_core_2x_clk", &gcc.mux, 0x184 }, + { "gcc_qupv3_wrap2_core_clk", &gcc.mux, 0x183 }, + { "gcc_qupv3_wrap2_s0_clk", &gcc.mux, 0x185 }, + { "gcc_qupv3_wrap2_s1_clk", &gcc.mux, 0x186 }, + { "gcc_qupv3_wrap2_s2_clk", &gcc.mux, 0x187 }, + { "gcc_qupv3_wrap2_s3_clk", &gcc.mux, 0x188 }, + { "gcc_qupv3_wrap2_s4_clk", &gcc.mux, 0x189 }, + { "gcc_qupv3_wrap2_s5_clk", &gcc.mux, 0x18a }, + { "gcc_sdcc2_ahb_clk", &gcc.mux, 0x7f }, + { "gcc_sdcc2_apps_clk", &gcc.mux, 0x7e }, + { "gcc_sdcc4_ahb_clk", &gcc.mux, 0x81 }, + { "gcc_sdcc4_apps_clk", &gcc.mux, 0x80 }, + { "gcc_sys_noc_cpuss_ahb_clk", &gcc.mux, 0xc }, + { "gcc_tsif_ahb_clk", &gcc.mux, 0x9c }, + { "gcc_tsif_ref_clk", &gcc.mux, 0x9d }, + { "gcc_ufs_card_ahb_clk", &gcc.mux, 0x107 }, + { "gcc_ufs_card_axi_clk", &gcc.mux, 0x106 }, + { "gcc_ufs_card_ice_core_clk", &gcc.mux, 0x10d }, + { "gcc_ufs_card_phy_aux_clk", &gcc.mux, 0x10e }, + { "gcc_ufs_card_rx_symbol_0_clk", &gcc.mux, 0x109 }, + { "gcc_ufs_card_rx_symbol_1_clk", &gcc.mux, 0x10f }, + { "gcc_ufs_card_tx_symbol_0_clk", &gcc.mux, 0x108 }, + { "gcc_ufs_card_unipro_core_clk", &gcc.mux, 0x10c }, + { "gcc_ufs_phy_ahb_clk", &gcc.mux, 0x113 }, + { "gcc_ufs_phy_axi_clk", &gcc.mux, 0x112 }, + { "gcc_ufs_phy_ice_core_clk", &gcc.mux, 0x119 }, + { "gcc_ufs_phy_phy_aux_clk", &gcc.mux, 0x11a }, + { "gcc_ufs_phy_rx_symbol_0_clk", &gcc.mux, 0x115 }, + { "gcc_ufs_phy_rx_symbol_1_clk", &gcc.mux, 0x11b }, + { "gcc_ufs_phy_tx_symbol_0_clk", &gcc.mux, 0x114 }, + { "gcc_ufs_phy_unipro_core_clk", &gcc.mux, 0x118 }, + { "gcc_usb30_prim_master_clk", &gcc.mux, 0x6b }, + { "gcc_usb30_prim_mock_utmi_clk", &gcc.mux, 0x6d }, + { "gcc_usb30_sec_master_clk", &gcc.mux, 0x72 }, + { "gcc_usb30_sec_mock_utmi_clk", &gcc.mux, 0x74 }, + { "gcc_usb3_prim_phy_aux_clk", &gcc.mux, 0x6e }, + { "gcc_usb3_prim_phy_com_aux_clk", &gcc.mux, 0x6f }, + { "gcc_usb3_prim_phy_pipe_clk", &gcc.mux, 0x70 }, + { "gcc_usb3_sec_phy_aux_clk", &gcc.mux, 0x75 }, + { "gcc_usb3_sec_phy_com_aux_clk", &gcc.mux, 0x76 }, + { "gcc_usb3_sec_phy_pipe_clk", &gcc.mux, 0x77 }, + { "gcc_video_ahb_clk", &gcc.mux, 0x42 }, + { "gcc_video_axi0_clk", &gcc.mux, 0x4a }, + { "gcc_video_axi1_clk", &gcc.mux, 0x4b }, + { "gcc_video_axic_clk", &gcc.mux, 0x4c }, + { "gcc_video_xo_clk", &gcc.mux, 0x51 }, + + { "gpu_cc_ahb_clk", &gpu_cc, 0x10 }, + { "gpu_cc_cx_apb_clk", &gpu_cc, 0x14 }, + { "gpu_cc_cx_gmu_clk", &gpu_cc, 0x18 }, + { "gpu_cc_cx_qdss_at_clk", &gpu_cc, 0x12 }, + { "gpu_cc_cx_qdss_trig_clk", &gpu_cc, 0x17 }, + { "gpu_cc_cx_snoc_dvm_clk", &gpu_cc, 0x15 }, + { "gpu_cc_cxo_aon_clk", &gpu_cc, 0xa }, + { "gpu_cc_cxo_clk", &gpu_cc, 0x19 }, + { "gpu_cc_gx_gmu_clk", &gpu_cc, 0xf }, + { "gpu_cc_gx_vsense_clk", &gpu_cc, 0xc }, + { "measure_only_gpu_cc_cx_gfx3d_clk", &gpu_cc, 0x1a }, + { "measure_only_gpu_cc_cx_gfx3d_slv_clk", &gpu_cc, 0x1b }, + { "measure_only_gpu_cc_gx_gfx3d_clk", &gpu_cc, 0xb }, + + { "npu_cc_armwic_core_clk", &npu_cc, 0x4 }, + { "npu_cc_bto_core_clk", &npu_cc, 0x12 }, + { "npu_cc_bwmon_clk", &npu_cc, 0xf }, + { "npu_cc_cal_dp_cdc_clk", &npu_cc, 0x8 }, + { "npu_cc_cal_dp_clk", &npu_cc, 0x1 }, + { "npu_cc_comp_noc_axi_clk", &npu_cc, 0x9 }, + { "npu_cc_conf_noc_ahb_clk", &npu_cc, 0xa }, + { "npu_cc_npu_core_apb_clk", &npu_cc, 0xe }, + { "npu_cc_npu_core_atb_clk", &npu_cc, 0xb }, + { "npu_cc_npu_core_clk", &npu_cc, 0x2 }, + { "npu_cc_npu_core_cti_clk", &npu_cc, 0xc }, + { "npu_cc_npu_cpc_clk", &npu_cc, 0x3 }, + { "npu_cc_perf_cnt_clk", &npu_cc, 0x10 }, + { "npu_cc_xo_clk", &npu_cc, 0x11 }, + + { "video_cc_iris_ahb_clk", &video_cc, 0x7 }, + { "video_cc_mvs0_core_clk", &video_cc, 0x3 }, + { "video_cc_mvs1_core_clk", &video_cc, 0x5 }, + { "video_cc_mvsc_core_clk", &video_cc, 0x1 }, + { "video_cc_xo_clk", &video_cc, 0x8 }, + + { "l3_clk", &cpu_cc, 0x46, 16 }, + { "pwrcl_clk", &cpu_cc, 0x44, 16 }, + { "perfcl_clk", &cpu_cc, 0x45, 16 }, + { "perfpcl_clk", &cpu_cc, 0x47, 16 }, {} }; diff --git a/sm8250.c b/sm8250.c index 1776b5a..e4e8d0a 100644 --- a/sm8250.c +++ b/sm8250.c @@ -39,19 +39,23 @@ #include "debugcc.h" -static struct debug_mux gcc = { - .phys = 0x100000, - .size = 0x1f0000, +static struct gcc_mux gcc = { + .mux = { + .phys = 0x100000, + .size = 0x1f0000, - .enable_reg = 0x62008, - .enable_mask = BIT(0), + .measure = measure_gcc, - .mux_reg = 0x62000, - .mux_mask = 0x3ff, + .enable_reg = 0x62008, + .enable_mask = BIT(0), - .div_reg = 0x62004, - .div_mask = 0xf, - .div_val = 2, + .mux_reg = 0x62000, + .mux_mask = 0x3ff, + + .div_reg = 0x62004, + .div_mask = 0xf, + .div_val = 2, + }, .xo_div4_reg = 0x4300c, .debug_ctl_reg = 0x62038, @@ -63,6 +67,10 @@ static struct debug_mux cam_cc = { .size = 0x10000, .block_name = "cam", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x55, + .enable_reg = 0xd008, .enable_mask = BIT(0), @@ -79,6 +87,10 @@ static struct debug_mux disp_cc = { .size = 0x20000, .block_name = "disp", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x56, + .enable_reg = 0x500c, .enable_mask = BIT(0), @@ -95,6 +107,10 @@ static struct debug_mux gpu_cc = { .size = 0x9000, .block_name = "gpu", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x163, + .enable_reg = 0x1100, .enable_mask = BIT(0), @@ -111,6 +127,10 @@ static struct debug_mux npu_cc = { .size = 0x10000, .block_name = "npu", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x180, + .enable_reg = 0x3008, .enable_mask = BIT(0), @@ -127,6 +147,10 @@ static struct debug_mux video_cc = { .size = 0x10000, .block_name = "video", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x57, + .enable_reg = 0xebc, .enable_mask = BIT(0), @@ -144,6 +168,8 @@ static struct debug_mux mc_cc = { .block_name = "mc", .measure = measure_mccc, + .parent = &gcc.mux, + .parent_mux_val = 0xd1, }; static struct debug_mux apss_cc = { @@ -151,6 +177,10 @@ static struct debug_mux apss_cc = { .size = /* 0x1c */ 0x1000, .block_name = "apss", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0xe7, + .enable_reg = 0x0, .enable_mask = BIT(0), @@ -165,324 +195,317 @@ static struct debug_mux apss_cc = { }; static struct measure_clk sm8250_clocks[] = { - { "cam_cc_bps_ahb_clk", &gcc, 0x55, &cam_cc, 0x18 }, - { "cam_cc_bps_areg_clk", &gcc, 0x55, &cam_cc, 0x17 }, - { "cam_cc_bps_axi_clk", &gcc, 0x55, &cam_cc, 0x16 }, - { "cam_cc_bps_clk", &gcc, 0x55, &cam_cc, 0x14 }, - { "cam_cc_camnoc_axi_clk", &gcc, 0x55, &cam_cc, 0x3c }, - { "cam_cc_camnoc_dcd_xo_clk", &gcc, 0x55, &cam_cc, 0x3d }, - { "cam_cc_cci_0_clk", &gcc, 0x55, &cam_cc, 0x39 }, - { "cam_cc_cci_1_clk", &gcc, 0x55, &cam_cc, 0x3a }, - { "cam_cc_core_ahb_clk", &gcc, 0x55, &cam_cc, 0x40 }, - { "cam_cc_cpas_ahb_clk", &gcc, 0x55, &cam_cc, 0x3b }, - { "cam_cc_csi0phytimer_clk", &gcc, 0x55, &cam_cc, 0x8 }, - { "cam_cc_csi1phytimer_clk", &gcc, 0x55, &cam_cc, 0xa }, - { "cam_cc_csi2phytimer_clk", &gcc, 0x55, &cam_cc, 0xc }, - { "cam_cc_csi3phytimer_clk", &gcc, 0x55, &cam_cc, 0xe }, - { "cam_cc_csi4phytimer_clk", &gcc, 0x55, &cam_cc, 0x10 }, - { "cam_cc_csi5phytimer_clk", &gcc, 0x55, &cam_cc, 0x12 }, - { "cam_cc_csiphy0_clk", &gcc, 0x55, &cam_cc, 0x9 }, - { "cam_cc_csiphy1_clk", &gcc, 0x55, &cam_cc, 0xb }, - { "cam_cc_csiphy2_clk", &gcc, 0x55, &cam_cc, 0xd }, - { "cam_cc_csiphy3_clk", &gcc, 0x55, &cam_cc, 0xf }, - { "cam_cc_csiphy4_clk", &gcc, 0x55, &cam_cc, 0x11 }, - { "cam_cc_csiphy5_clk", &gcc, 0x55, &cam_cc, 0x13 }, - { "cam_cc_fd_core_clk", &gcc, 0x55, &cam_cc, 0x37 }, - { "cam_cc_fd_core_uar_clk", &gcc, 0x55, &cam_cc, 0x38 }, - { "cam_cc_gdsc_clk", &gcc, 0x55, &cam_cc, 0x41 }, - { "cam_cc_icp_ahb_clk", &gcc, 0x55, &cam_cc, 0x36 }, - { "cam_cc_icp_clk", &gcc, 0x55, &cam_cc, 0x35 }, - { "cam_cc_ife_0_ahb_clk", &gcc, 0x55, &cam_cc, 0x26 }, - { "cam_cc_ife_0_areg_clk", &gcc, 0x55, &cam_cc, 0x1f }, - { "cam_cc_ife_0_axi_clk", &gcc, 0x55, &cam_cc, 0x25 }, - { "cam_cc_ife_0_clk", &gcc, 0x55, &cam_cc, 0x1e }, - { "cam_cc_ife_0_cphy_rx_clk", &gcc, 0x55, &cam_cc, 0x24 }, - { "cam_cc_ife_0_csid_clk", &gcc, 0x55, &cam_cc, 0x22 }, - { "cam_cc_ife_0_dsp_clk", &gcc, 0x55, &cam_cc, 0x21 }, - { "cam_cc_ife_1_ahb_clk", &gcc, 0x55, &cam_cc, 0x2e }, - { "cam_cc_ife_1_areg_clk", &gcc, 0x55, &cam_cc, 0x29 }, - { "cam_cc_ife_1_axi_clk", &gcc, 0x55, &cam_cc, 0x2d }, - { "cam_cc_ife_1_clk", &gcc, 0x55, &cam_cc, 0x27 }, - { "cam_cc_ife_1_cphy_rx_clk", &gcc, 0x55, &cam_cc, 0x2c }, - { "cam_cc_ife_1_csid_clk", &gcc, 0x55, &cam_cc, 0x2b }, - { "cam_cc_ife_1_dsp_clk", &gcc, 0x55, &cam_cc, 0x2a }, - { "cam_cc_ife_lite_ahb_clk", &gcc, 0x55, &cam_cc, 0x32 }, - { "cam_cc_ife_lite_axi_clk", &gcc, 0x55, &cam_cc, 0x49 }, - { "cam_cc_ife_lite_clk", &gcc, 0x55, &cam_cc, 0x2f }, - { "cam_cc_ife_lite_cphy_rx_clk", &gcc, 0x55, &cam_cc, 0x31 }, - { "cam_cc_ife_lite_csid_clk", &gcc, 0x55, &cam_cc, 0x30 }, - { "cam_cc_ipe_0_ahb_clk", &gcc, 0x55, &cam_cc, 0x1d }, - { "cam_cc_ipe_0_areg_clk", &gcc, 0x55, &cam_cc, 0x1c }, - { "cam_cc_ipe_0_axi_clk", &gcc, 0x55, &cam_cc, 0x1b }, - { "cam_cc_ipe_0_clk", &gcc, 0x55, &cam_cc, 0x19 }, - { "cam_cc_jpeg_clk", &gcc, 0x55, &cam_cc, 0x33 }, - { "cam_cc_mclk0_clk", &gcc, 0x55, &cam_cc, 0x1 }, - { "cam_cc_mclk1_clk", &gcc, 0x55, &cam_cc, 0x2 }, - { "cam_cc_mclk2_clk", &gcc, 0x55, &cam_cc, 0x3 }, - { "cam_cc_mclk3_clk", &gcc, 0x55, &cam_cc, 0x4 }, - { "cam_cc_mclk4_clk", &gcc, 0x55, &cam_cc, 0x5 }, - { "cam_cc_mclk5_clk", &gcc, 0x55, &cam_cc, 0x6 }, - { "cam_cc_mclk6_clk", &gcc, 0x55, &cam_cc, 0x7 }, - { "cam_cc_sbi_ahb_clk", &gcc, 0x55, &cam_cc, 0x4e }, - { "cam_cc_sbi_axi_clk", &gcc, 0x55, &cam_cc, 0x4d }, - { "cam_cc_sbi_clk", &gcc, 0x55, &cam_cc, 0x4a }, - { "cam_cc_sbi_cphy_rx_clk", &gcc, 0x55, &cam_cc, 0x4c }, - { "cam_cc_sbi_csid_clk", &gcc, 0x55, &cam_cc, 0x4b }, - { "cam_cc_sbi_ife_0_clk", &gcc, 0x55, &cam_cc, 0x4f }, - { "cam_cc_sbi_ife_1_clk", &gcc, 0x55, &cam_cc, 0x50 }, - { "cam_cc_sleep_clk", &gcc, 0x55, &cam_cc, 0x42 }, - - { "disp_cc_mdss_ahb_clk", &gcc, 0x56, &disp_cc, 0x2b }, - { "disp_cc_mdss_byte0_clk", &gcc, 0x56, &disp_cc, 0x15 }, - { "disp_cc_mdss_byte0_intf_clk", &gcc, 0x56, &disp_cc, 0x16 }, - { "disp_cc_mdss_byte1_clk", &gcc, 0x56, &disp_cc, 0x17 }, - { "disp_cc_mdss_byte1_intf_clk", &gcc, 0x56, &disp_cc, 0x18 }, - { "disp_cc_mdss_dp_aux1_clk", &gcc, 0x56, &disp_cc, 0x25 }, - { "disp_cc_mdss_dp_aux_clk", &gcc, 0x56, &disp_cc, 0x20 }, - { "disp_cc_mdss_dp_link1_clk", &gcc, 0x56, &disp_cc, 0x22 }, - { "disp_cc_mdss_dp_link1_intf_clk", &gcc, 0x56, &disp_cc, 0x23 }, - { "disp_cc_mdss_dp_link_clk", &gcc, 0x56, &disp_cc, 0x1b }, - { "disp_cc_mdss_dp_link_intf_clk", &gcc, 0x56, &disp_cc, 0x1c }, - { "disp_cc_mdss_dp_pixel1_clk", &gcc, 0x56, &disp_cc, 0x1f }, - { "disp_cc_mdss_dp_pixel2_clk", &gcc, 0x56, &disp_cc, 0x21 }, - { "disp_cc_mdss_dp_pixel_clk", &gcc, 0x56, &disp_cc, 0x1e }, - { "disp_cc_mdss_edp_aux_clk", &gcc, 0x56, &disp_cc, 0x29 }, - { "disp_cc_mdss_edp_gtc_clk", &gcc, 0x56, &disp_cc, 0x2a }, - { "disp_cc_mdss_edp_link_clk", &gcc, 0x56, &disp_cc, 0x27 }, - { "disp_cc_mdss_edp_link_intf_clk", &gcc, 0x56, &disp_cc, 0x28 }, - { "disp_cc_mdss_edp_pixel_clk", &gcc, 0x56, &disp_cc, 0x26 }, - { "disp_cc_mdss_esc0_clk", &gcc, 0x56, &disp_cc, 0x19 }, - { "disp_cc_mdss_esc1_clk", &gcc, 0x56, &disp_cc, 0x1a }, - { "disp_cc_mdss_mdp_clk", &gcc, 0x56, &disp_cc, 0x11 }, - { "disp_cc_mdss_mdp_lut_clk", &gcc, 0x56, &disp_cc, 0x13 }, - { "disp_cc_mdss_non_gdsc_ahb_clk", &gcc, 0x56, &disp_cc, 0x2c }, - { "disp_cc_mdss_pclk0_clk", &gcc, 0x56, &disp_cc, 0xf }, - { "disp_cc_mdss_pclk1_clk", &gcc, 0x56, &disp_cc, 0x10 }, - { "disp_cc_mdss_rot_clk", &gcc, 0x56, &disp_cc, 0x12 }, - { "disp_cc_mdss_rscc_ahb_clk", &gcc, 0x56, &disp_cc, 0x2e }, - { "disp_cc_mdss_rscc_vsync_clk", &gcc, 0x56, &disp_cc, 0x2d }, - { "disp_cc_mdss_vsync_clk", &gcc, 0x56, &disp_cc, 0x14 }, - { "disp_cc_sleep_clk", &gcc, 0x56, &disp_cc, 0x37 }, - { "disp_cc_xo_clk", &gcc, 0x56, &disp_cc, 0x36 }, - - // { "apss_cc_debug_mux", &gcc, 0xe7 }, - // { "cam_cc_debug_mux", &gcc, 0x55 }, - // { "disp_cc_debug_mux", &gcc, 0x56 }, - { "gcc_aggre_noc_pcie_tbu_clk", &gcc, 0x36 }, - { "gcc_aggre_ufs_card_axi_clk", &gcc, 0x142 }, - { "gcc_aggre_ufs_phy_axi_clk", &gcc, 0x141 }, - { "gcc_aggre_usb3_prim_axi_clk", &gcc, 0x13f }, - { "gcc_aggre_usb3_sec_axi_clk", &gcc, 0x140 }, - { "gcc_boot_rom_ahb_clk", &gcc, 0xa3 }, - { "gcc_camera_ahb_clk", &gcc, 0x44 }, - { "gcc_camera_hf_axi_clk", &gcc, 0x4d }, - { "gcc_camera_sf_axi_clk", &gcc, 0x4e }, - { "gcc_camera_xo_clk", &gcc, 0x52 }, - { "gcc_cfg_noc_usb3_prim_axi_clk", &gcc, 0x21 }, - { "gcc_cfg_noc_usb3_sec_axi_clk", &gcc, 0x22 }, - { "gcc_cpuss_ahb_clk", &gcc, 0xe0 }, - { "gcc_cpuss_dvm_bus_clk", &gcc, 0xe4 }, - { "gcc_cpuss_rbcpr_clk", &gcc, 0xe1 }, - { "gcc_ddrss_gpu_axi_clk", &gcc, 0xc4 }, - { "gcc_ddrss_pcie_sf_tbu_clk", &gcc, 0xc5 }, - { "gcc_disp_ahb_clk", &gcc, 0x45 }, - { "gcc_disp_hf_axi_clk", &gcc, 0x4f }, - { "gcc_disp_sf_axi_clk", &gcc, 0x50 }, - { "gcc_disp_xo_clk", &gcc, 0x53 }, - { "gcc_gp1_clk", &gcc, 0xef }, - { "gcc_gp2_clk", &gcc, 0xf0 }, - { "gcc_gp3_clk", &gcc, 0xf1 }, - { "gcc_gpu_cfg_ahb_clk", &gcc, 0x161 }, - { "gcc_gpu_gpll0_clk_src", &gcc, 0x167 }, - { "gcc_gpu_gpll0_div_clk_src", &gcc, 0x168 }, - { "gcc_gpu_memnoc_gfx_clk", &gcc, 0x164 }, - { "gcc_gpu_snoc_dvm_gfx_clk", &gcc, 0x166 }, - { "gcc_npu_axi_clk", &gcc, 0x17a }, - { "gcc_npu_bwmon_axi_clk", &gcc, 0x19a }, - { "gcc_npu_bwmon_cfg_ahb_clk", &gcc, 0x199 }, - { "gcc_npu_cfg_ahb_clk", &gcc, 0x179 }, - { "gcc_npu_dma_clk", &gcc, 0x17b }, - { "gcc_npu_gpll0_clk_src", &gcc, 0x17e }, - { "gcc_npu_gpll0_div_clk_src", &gcc, 0x17f }, - { "gcc_pcie0_phy_refgen_clk", &gcc, 0x103 }, - { "gcc_pcie1_phy_refgen_clk", &gcc, 0x104 }, - { "gcc_pcie2_phy_refgen_clk", &gcc, 0x105 }, - { "gcc_pcie_0_aux_clk", &gcc, 0xf6 }, - { "gcc_pcie_0_cfg_ahb_clk", &gcc, 0xf5 }, - { "gcc_pcie_0_mstr_axi_clk", &gcc, 0xf4 }, - { "gcc_pcie_0_pipe_clk", &gcc, 0xf7 }, - { "gcc_pcie_0_slv_axi_clk", &gcc, 0xf3 }, - { "gcc_pcie_0_slv_q2a_axi_clk", &gcc, 0xf2 }, - { "gcc_pcie_1_aux_clk", &gcc, 0xfe }, - { "gcc_pcie_1_cfg_ahb_clk", &gcc, 0xfd }, - { "gcc_pcie_1_mstr_axi_clk", &gcc, 0xfc }, - { "gcc_pcie_1_pipe_clk", &gcc, 0xff }, - { "gcc_pcie_1_slv_axi_clk", &gcc, 0xfb }, - { "gcc_pcie_1_slv_q2a_axi_clk", &gcc, 0xfa }, - { "gcc_pcie_2_aux_clk", &gcc, 0x191 }, - { "gcc_pcie_2_cfg_ahb_clk", &gcc, 0x190 }, - { "gcc_pcie_2_mstr_axi_clk", &gcc, 0x18f }, - { "gcc_pcie_2_pipe_clk", &gcc, 0x192 }, - { "gcc_pcie_2_slv_axi_clk", &gcc, 0x18e }, - { "gcc_pcie_2_slv_q2a_axi_clk", &gcc, 0x18d }, - { "gcc_pcie_phy_aux_clk", &gcc, 0x102 }, - { "gcc_pdm2_clk", &gcc, 0x9d }, - { "gcc_pdm_ahb_clk", &gcc, 0x9b }, - { "gcc_pdm_xo4_clk", &gcc, 0x9c }, - { "gcc_prng_ahb_clk", &gcc, 0x9e }, - { "gcc_qmip_camera_nrt_ahb_clk", &gcc, 0x48 }, - { "gcc_qmip_camera_rt_ahb_clk", &gcc, 0x49 }, - { "gcc_qmip_disp_ahb_clk", &gcc, 0x4a }, - { "gcc_qmip_video_cvp_ahb_clk", &gcc, 0x46 }, - { "gcc_qmip_video_vcodec_ahb_clk", &gcc, 0x47 }, - { "gcc_qupv3_wrap0_core_2x_clk", &gcc, 0x88 }, - { "gcc_qupv3_wrap0_core_clk", &gcc, 0x87 }, - { "gcc_qupv3_wrap0_s0_clk", &gcc, 0x89 }, - { "gcc_qupv3_wrap0_s1_clk", &gcc, 0x8a }, - { "gcc_qupv3_wrap0_s2_clk", &gcc, 0x8b }, - { "gcc_qupv3_wrap0_s3_clk", &gcc, 0x8c }, - { "gcc_qupv3_wrap0_s4_clk", &gcc, 0x8d }, - { "gcc_qupv3_wrap0_s5_clk", &gcc, 0x8e }, - { "gcc_qupv3_wrap0_s6_clk", &gcc, 0x8f }, - { "gcc_qupv3_wrap0_s7_clk", &gcc, 0x90 }, - { "gcc_qupv3_wrap1_core_2x_clk", &gcc, 0x94 }, - { "gcc_qupv3_wrap1_core_clk", &gcc, 0x93 }, - { "gcc_qupv3_wrap1_s0_clk", &gcc, 0x95 }, - { "gcc_qupv3_wrap1_s1_clk", &gcc, 0x96 }, - { "gcc_qupv3_wrap1_s2_clk", &gcc, 0x97 }, - { "gcc_qupv3_wrap1_s3_clk", &gcc, 0x98 }, - { "gcc_qupv3_wrap1_s4_clk", &gcc, 0x99 }, - { "gcc_qupv3_wrap1_s5_clk", &gcc, 0x9a }, - { "gcc_qupv3_wrap2_core_2x_clk", &gcc, 0x184 }, - { "gcc_qupv3_wrap2_core_clk", &gcc, 0x183 }, - { "gcc_qupv3_wrap2_s0_clk", &gcc, 0x185 }, - { "gcc_qupv3_wrap2_s1_clk", &gcc, 0x186 }, - { "gcc_qupv3_wrap2_s2_clk", &gcc, 0x187 }, - { "gcc_qupv3_wrap2_s3_clk", &gcc, 0x188 }, - { "gcc_qupv3_wrap2_s4_clk", &gcc, 0x189 }, - { "gcc_qupv3_wrap2_s5_clk", &gcc, 0x18a }, - { "gcc_qupv3_wrap_0_m_ahb_clk", &gcc, 0x85 }, - { "gcc_qupv3_wrap_0_s_ahb_clk", &gcc, 0x86 }, - { "gcc_qupv3_wrap_1_m_ahb_clk", &gcc, 0x91 }, - { "gcc_qupv3_wrap_1_s_ahb_clk", &gcc, 0x92 }, - { "gcc_qupv3_wrap_2_m_ahb_clk", &gcc, 0x181 }, - { "gcc_qupv3_wrap_2_s_ahb_clk", &gcc, 0x182 }, - { "gcc_sdcc2_ahb_clk", &gcc, 0x82 }, - { "gcc_sdcc2_apps_clk", &gcc, 0x81 }, - { "gcc_sdcc4_ahb_clk", &gcc, 0x84 }, - { "gcc_sdcc4_apps_clk", &gcc, 0x83 }, - { "gcc_sys_noc_cpuss_ahb_clk", &gcc, 0xc }, - { "gcc_tsif_ahb_clk", &gcc, 0x9f }, - { "gcc_tsif_inactivity_timers_clk", &gcc, 0xa1 }, - { "gcc_tsif_ref_clk", &gcc, 0xa0 }, - { "gcc_ufs_card_ahb_clk", &gcc, 0x107 }, - { "gcc_ufs_card_axi_clk", &gcc, 0x106 }, - { "gcc_ufs_card_ice_core_clk", &gcc, 0x10d }, - { "gcc_ufs_card_phy_aux_clk", &gcc, 0x10e }, - { "gcc_ufs_card_rx_symbol_0_clk", &gcc, 0x109 }, - { "gcc_ufs_card_rx_symbol_1_clk", &gcc, 0x10f }, - { "gcc_ufs_card_tx_symbol_0_clk", &gcc, 0x108 }, - { "gcc_ufs_card_unipro_core_clk", &gcc, 0x10c }, - { "gcc_ufs_phy_ahb_clk", &gcc, 0x113 }, - { "gcc_ufs_phy_axi_clk", &gcc, 0x112 }, - { "gcc_ufs_phy_ice_core_clk", &gcc, 0x119 }, - { "gcc_ufs_phy_phy_aux_clk", &gcc, 0x11a }, - { "gcc_ufs_phy_rx_symbol_0_clk", &gcc, 0x115 }, - { "gcc_ufs_phy_rx_symbol_1_clk", &gcc, 0x11b }, - { "gcc_ufs_phy_tx_symbol_0_clk", &gcc, 0x114 }, - { "gcc_ufs_phy_unipro_core_clk", &gcc, 0x118 }, - { "gcc_usb30_prim_master_clk", &gcc, 0x6e }, - { "gcc_usb30_prim_mock_utmi_clk", &gcc, 0x70 }, - { "gcc_usb30_prim_sleep_clk", &gcc, 0x6f }, - { "gcc_usb30_sec_master_clk", &gcc, 0x75 }, - { "gcc_usb30_sec_mock_utmi_clk", &gcc, 0x77 }, - { "gcc_usb30_sec_sleep_clk", &gcc, 0x76 }, - { "gcc_usb3_prim_phy_aux_clk", &gcc, 0x71 }, - { "gcc_usb3_prim_phy_com_aux_clk", &gcc, 0x72 }, - { "gcc_usb3_prim_phy_pipe_clk", &gcc, 0x73 }, - { "gcc_usb3_sec_phy_aux_clk", &gcc, 0x78 }, - { "gcc_usb3_sec_phy_com_aux_clk", &gcc, 0x79 }, - { "gcc_usb3_sec_phy_pipe_clk", &gcc, 0x7a }, - { "gcc_video_ahb_clk", &gcc, 0x43 }, - { "gcc_video_axi0_clk", &gcc, 0x4b }, - { "gcc_video_axi1_clk", &gcc, 0x4c }, - { "gcc_video_xo_clk", &gcc, 0x51 }, - // { "gpu_cc_debug_mux", &gcc, 0x163 }, - // { "mc_cc_debug_mux", &gcc, 0xd1 }, - { "measure_only_cnoc_clk", &gcc, 0x19 }, - { "measure_only_ipa_2x_clk", &gcc, 0x147 }, - { "measure_only_memnoc_clk", &gcc, 0xcc }, - { "measure_only_snoc_clk", &gcc, 0x7 }, - // { "npu_cc_debug_mux", &gcc, 0x180 }, - // { "video_cc_debug_mux", &gcc, 0x57 }, - - { "gpu_cc_ahb_clk", &gcc, 0x163, &gpu_cc, 0x10 }, - { "gpu_cc_crc_ahb_clk", &gcc, 0x163, &gpu_cc, 0x11 }, - { "gpu_cc_cx_apb_clk", &gcc, 0x163, &gpu_cc, 0x14 }, - { "gpu_cc_cx_gmu_clk", &gcc, 0x163, &gpu_cc, 0x18 }, - { "gpu_cc_cx_qdss_at_clk", &gcc, 0x163, &gpu_cc, 0x12 }, - { "gpu_cc_cx_qdss_trig_clk", &gcc, 0x163, &gpu_cc, 0x17 }, - { "gpu_cc_cx_qdss_tsctr_clk", &gcc, 0x163, &gpu_cc, 0x13 }, - { "gpu_cc_cx_snoc_dvm_clk", &gcc, 0x163, &gpu_cc, 0x15 }, - { "gpu_cc_cxo_aon_clk", &gcc, 0x163, &gpu_cc, 0xa }, - { "gpu_cc_cxo_clk", &gcc, 0x163, &gpu_cc, 0x19 }, - { "gpu_cc_gx_gmu_clk", &gcc, 0x163, &gpu_cc, 0xf }, - { "gpu_cc_gx_qdss_tsctr_clk", &gcc, 0x163, &gpu_cc, 0xd }, - { "gpu_cc_gx_vsense_clk", &gcc, 0x163, &gpu_cc, 0xc }, - { "gpu_cc_sleep_clk", &gcc, 0x163, &gpu_cc, 0x16 }, - { "measure_only_gpu_cc_cx_gfx3d_clk", &gcc, 0x163, &gpu_cc, 0x1a }, - { "measure_only_gpu_cc_cx_gfx3d_slv_clk", &gcc, 0x163, &gpu_cc, 0x1b }, - { "measure_only_gpu_cc_gx_gfx3d_clk", &gcc, 0x163, &gpu_cc, 0xb }, - - { "npu_cc_atb_clk", &gcc, 0x180, &npu_cc, 0x17 }, - { "npu_cc_bto_core_clk", &gcc, 0x180, &npu_cc, 0x19 }, - { "npu_cc_bwmon_clk", &gcc, 0x180, &npu_cc, 0x18 }, - { "npu_cc_cal_hm0_cdc_clk", &gcc, 0x180, &npu_cc, 0xb }, - { "npu_cc_cal_hm0_clk", &gcc, 0x180, &npu_cc, 0x2 }, - { "npu_cc_cal_hm0_dpm_ip_clk", &gcc, 0x180, &npu_cc, 0xc }, - { "npu_cc_cal_hm0_perf_cnt_clk", &gcc, 0x180, &npu_cc, 0xd }, - { "npu_cc_cal_hm1_cdc_clk", &gcc, 0x180, &npu_cc, 0xe }, - { "npu_cc_cal_hm1_clk", &gcc, 0x180, &npu_cc, 0x3 }, - { "npu_cc_cal_hm1_dpm_ip_clk", &gcc, 0x180, &npu_cc, 0xf }, - { "npu_cc_cal_hm1_perf_cnt_clk", &gcc, 0x180, &npu_cc, 0x10 }, - { "npu_cc_core_clk", &gcc, 0x180, &npu_cc, 0x4 }, - { "npu_cc_dl_dpm_clk", &gcc, 0x180, &npu_cc, 0x23 }, - { "npu_cc_dl_llm_clk", &gcc, 0x180, &npu_cc, 0x22 }, - { "npu_cc_dpm_clk", &gcc, 0x180, &npu_cc, 0x8 }, - { "npu_cc_dpm_temp_clk", &gcc, 0x180, &npu_cc, 0x14 }, - { "npu_cc_dpm_xo_clk", &gcc, 0x180, &npu_cc, 0xa }, - { "npu_cc_dsp_ahbm_clk", &gcc, 0x180, &npu_cc, 0x1c }, - { "npu_cc_dsp_ahbs_clk", &gcc, 0x180, &npu_cc, 0x1b }, - { "npu_cc_dsp_axi_clk", &gcc, 0x180, &npu_cc, 0x1e }, - { "npu_cc_dsp_bwmon_ahb_clk", &gcc, 0x180, &npu_cc, 0x1d }, - { "npu_cc_dsp_bwmon_clk", &gcc, 0x180, &npu_cc, 0x1f }, - { "npu_cc_isense_clk", &gcc, 0x180, &npu_cc, 0x7 }, - { "npu_cc_llm_clk", &gcc, 0x180, &npu_cc, 0x6 }, - { "npu_cc_llm_curr_clk", &gcc, 0x180, &npu_cc, 0x21 }, - { "npu_cc_llm_temp_clk", &gcc, 0x180, &npu_cc, 0x15 }, - { "npu_cc_llm_xo_clk", &gcc, 0x180, &npu_cc, 0x9 }, - { "npu_cc_noc_ahb_clk", &gcc, 0x180, &npu_cc, 0x13 }, - { "npu_cc_noc_axi_clk", &gcc, 0x180, &npu_cc, 0x12 }, - { "npu_cc_noc_dma_clk", &gcc, 0x180, &npu_cc, 0x11 }, - { "npu_cc_rsc_xo_clk", &gcc, 0x180, &npu_cc, 0x1a }, - { "npu_cc_s2p_clk", &gcc, 0x180, &npu_cc, 0x16 }, - { "npu_cc_xo_clk", &gcc, 0x180, &npu_cc, 0x1 }, - - { "video_cc_ahb_clk", &gcc, 0x57, &video_cc, 0x7 }, - { "video_cc_mvs0_clk", &gcc, 0x57, &video_cc, 0x3 }, - { "video_cc_mvs0c_clk", &gcc, 0x57, &video_cc, 0x1 }, - { "video_cc_mvs1_clk", &gcc, 0x57, &video_cc, 0x5 }, - { "video_cc_mvs1_div2_clk", &gcc, 0x57, &video_cc, 0x8 }, - { "video_cc_mvs1c_clk", &gcc, 0x57, &video_cc, 0x9 }, - { "video_cc_sleep_clk", &gcc, 0x57, &video_cc, 0xc }, - { "video_cc_xo_clk", &gcc, 0x57, &video_cc, 0xb }, - - { "measure_only_mccc_clk", &gcc, 0xd1, &mc_cc, 0x50 }, - - { "measure_only_apcs_gold_post_acd_clk", &gcc, 0xe7, &apss_cc, 0x25, /* TODO: Are these pre_div_vals? */ 8 }, - { "measure_only_apcs_goldplus_post_acd_clk", &gcc, 0xe7, &apss_cc, 0x61, /* TODO: Are these pre_div_vals? */ 8 }, - { "measure_only_apcs_l3_post_acd_clk", &gcc, 0xe7, &apss_cc, 0x41, /* TODO: Are these pre_div_vals? */ 4 }, - { "measure_only_apcs_silver_post_acd_clk", &gcc, 0xe7, &apss_cc, 0x21, /* TODO: Are these pre_div_vals? */ 4 }, + { "cam_cc_bps_ahb_clk", &cam_cc, 0x18 }, + { "cam_cc_bps_areg_clk", &cam_cc, 0x17 }, + { "cam_cc_bps_axi_clk", &cam_cc, 0x16 }, + { "cam_cc_bps_clk", &cam_cc, 0x14 }, + { "cam_cc_camnoc_axi_clk", &cam_cc, 0x3c }, + { "cam_cc_camnoc_dcd_xo_clk", &cam_cc, 0x3d }, + { "cam_cc_cci_0_clk", &cam_cc, 0x39 }, + { "cam_cc_cci_1_clk", &cam_cc, 0x3a }, + { "cam_cc_core_ahb_clk", &cam_cc, 0x40 }, + { "cam_cc_cpas_ahb_clk", &cam_cc, 0x3b }, + { "cam_cc_csi0phytimer_clk", &cam_cc, 0x8 }, + { "cam_cc_csi1phytimer_clk", &cam_cc, 0xa }, + { "cam_cc_csi2phytimer_clk", &cam_cc, 0xc }, + { "cam_cc_csi3phytimer_clk", &cam_cc, 0xe }, + { "cam_cc_csi4phytimer_clk", &cam_cc, 0x10 }, + { "cam_cc_csi5phytimer_clk", &cam_cc, 0x12 }, + { "cam_cc_csiphy0_clk", &cam_cc, 0x9 }, + { "cam_cc_csiphy1_clk", &cam_cc, 0xb }, + { "cam_cc_csiphy2_clk", &cam_cc, 0xd }, + { "cam_cc_csiphy3_clk", &cam_cc, 0xf }, + { "cam_cc_csiphy4_clk", &cam_cc, 0x11 }, + { "cam_cc_csiphy5_clk", &cam_cc, 0x13 }, + { "cam_cc_fd_core_clk", &cam_cc, 0x37 }, + { "cam_cc_fd_core_uar_clk", &cam_cc, 0x38 }, + { "cam_cc_gdsc_clk", &cam_cc, 0x41 }, + { "cam_cc_icp_ahb_clk", &cam_cc, 0x36 }, + { "cam_cc_icp_clk", &cam_cc, 0x35 }, + { "cam_cc_ife_0_ahb_clk", &cam_cc, 0x26 }, + { "cam_cc_ife_0_areg_clk", &cam_cc, 0x1f }, + { "cam_cc_ife_0_axi_clk", &cam_cc, 0x25 }, + { "cam_cc_ife_0_clk", &cam_cc, 0x1e }, + { "cam_cc_ife_0_cphy_rx_clk", &cam_cc, 0x24 }, + { "cam_cc_ife_0_csid_clk", &cam_cc, 0x22 }, + { "cam_cc_ife_0_dsp_clk", &cam_cc, 0x21 }, + { "cam_cc_ife_1_ahb_clk", &cam_cc, 0x2e }, + { "cam_cc_ife_1_areg_clk", &cam_cc, 0x29 }, + { "cam_cc_ife_1_axi_clk", &cam_cc, 0x2d }, + { "cam_cc_ife_1_clk", &cam_cc, 0x27 }, + { "cam_cc_ife_1_cphy_rx_clk", &cam_cc, 0x2c }, + { "cam_cc_ife_1_csid_clk", &cam_cc, 0x2b }, + { "cam_cc_ife_1_dsp_clk", &cam_cc, 0x2a }, + { "cam_cc_ife_lite_ahb_clk", &cam_cc, 0x32 }, + { "cam_cc_ife_lite_axi_clk", &cam_cc, 0x49 }, + { "cam_cc_ife_lite_clk", &cam_cc, 0x2f }, + { "cam_cc_ife_lite_cphy_rx_clk", &cam_cc, 0x31 }, + { "cam_cc_ife_lite_csid_clk", &cam_cc, 0x30 }, + { "cam_cc_ipe_0_ahb_clk", &cam_cc, 0x1d }, + { "cam_cc_ipe_0_areg_clk", &cam_cc, 0x1c }, + { "cam_cc_ipe_0_axi_clk", &cam_cc, 0x1b }, + { "cam_cc_ipe_0_clk", &cam_cc, 0x19 }, + { "cam_cc_jpeg_clk", &cam_cc, 0x33 }, + { "cam_cc_mclk0_clk", &cam_cc, 0x1 }, + { "cam_cc_mclk1_clk", &cam_cc, 0x2 }, + { "cam_cc_mclk2_clk", &cam_cc, 0x3 }, + { "cam_cc_mclk3_clk", &cam_cc, 0x4 }, + { "cam_cc_mclk4_clk", &cam_cc, 0x5 }, + { "cam_cc_mclk5_clk", &cam_cc, 0x6 }, + { "cam_cc_mclk6_clk", &cam_cc, 0x7 }, + { "cam_cc_sbi_ahb_clk", &cam_cc, 0x4e }, + { "cam_cc_sbi_axi_clk", &cam_cc, 0x4d }, + { "cam_cc_sbi_clk", &cam_cc, 0x4a }, + { "cam_cc_sbi_cphy_rx_clk", &cam_cc, 0x4c }, + { "cam_cc_sbi_csid_clk", &cam_cc, 0x4b }, + { "cam_cc_sbi_ife_0_clk", &cam_cc, 0x4f }, + { "cam_cc_sbi_ife_1_clk", &cam_cc, 0x50 }, + { "cam_cc_sleep_clk", &cam_cc, 0x42 }, + + { "disp_cc_mdss_ahb_clk", &disp_cc, 0x2b }, + { "disp_cc_mdss_byte0_clk", &disp_cc, 0x15 }, + { "disp_cc_mdss_byte0_intf_clk", &disp_cc, 0x16 }, + { "disp_cc_mdss_byte1_clk", &disp_cc, 0x17 }, + { "disp_cc_mdss_byte1_intf_clk", &disp_cc, 0x18 }, + { "disp_cc_mdss_dp_aux1_clk", &disp_cc, 0x25 }, + { "disp_cc_mdss_dp_aux_clk", &disp_cc, 0x20 }, + { "disp_cc_mdss_dp_link1_clk", &disp_cc, 0x22 }, + { "disp_cc_mdss_dp_link1_intf_clk", &disp_cc, 0x23 }, + { "disp_cc_mdss_dp_link_clk", &disp_cc, 0x1b }, + { "disp_cc_mdss_dp_link_intf_clk", &disp_cc, 0x1c }, + { "disp_cc_mdss_dp_pixel1_clk", &disp_cc, 0x1f }, + { "disp_cc_mdss_dp_pixel2_clk", &disp_cc, 0x21 }, + { "disp_cc_mdss_dp_pixel_clk", &disp_cc, 0x1e }, + { "disp_cc_mdss_edp_aux_clk", &disp_cc, 0x29 }, + { "disp_cc_mdss_edp_gtc_clk", &disp_cc, 0x2a }, + { "disp_cc_mdss_edp_link_clk", &disp_cc, 0x27 }, + { "disp_cc_mdss_edp_link_intf_clk", &disp_cc, 0x28 }, + { "disp_cc_mdss_edp_pixel_clk", &disp_cc, 0x26 }, + { "disp_cc_mdss_esc0_clk", &disp_cc, 0x19 }, + { "disp_cc_mdss_esc1_clk", &disp_cc, 0x1a }, + { "disp_cc_mdss_mdp_clk", &disp_cc, 0x11 }, + { "disp_cc_mdss_mdp_lut_clk", &disp_cc, 0x13 }, + { "disp_cc_mdss_non_gdsc_ahb_clk", &disp_cc, 0x2c }, + { "disp_cc_mdss_pclk0_clk", &disp_cc, 0xf }, + { "disp_cc_mdss_pclk1_clk", &disp_cc, 0x10 }, + { "disp_cc_mdss_rot_clk", &disp_cc, 0x12 }, + { "disp_cc_mdss_rscc_ahb_clk", &disp_cc, 0x2e }, + { "disp_cc_mdss_rscc_vsync_clk", &disp_cc, 0x2d }, + { "disp_cc_mdss_vsync_clk", &disp_cc, 0x14 }, + { "disp_cc_sleep_clk", &disp_cc, 0x37 }, + { "disp_cc_xo_clk", &disp_cc, 0x36 }, + + { "gcc_aggre_noc_pcie_tbu_clk", &gcc.mux, 0x36 }, + { "gcc_aggre_ufs_card_axi_clk", &gcc.mux, 0x142 }, + { "gcc_aggre_ufs_phy_axi_clk", &gcc.mux, 0x141 }, + { "gcc_aggre_usb3_prim_axi_clk", &gcc.mux, 0x13f }, + { "gcc_aggre_usb3_sec_axi_clk", &gcc.mux, 0x140 }, + { "gcc_boot_rom_ahb_clk", &gcc.mux, 0xa3 }, + { "gcc_camera_ahb_clk", &gcc.mux, 0x44 }, + { "gcc_camera_hf_axi_clk", &gcc.mux, 0x4d }, + { "gcc_camera_sf_axi_clk", &gcc.mux, 0x4e }, + { "gcc_camera_xo_clk", &gcc.mux, 0x52 }, + { "gcc_cfg_noc_usb3_prim_axi_clk", &gcc.mux, 0x21 }, + { "gcc_cfg_noc_usb3_sec_axi_clk", &gcc.mux, 0x22 }, + { "gcc_cpuss_ahb_clk", &gcc.mux, 0xe0 }, + { "gcc_cpuss_dvm_bus_clk", &gcc.mux, 0xe4 }, + { "gcc_cpuss_rbcpr_clk", &gcc.mux, 0xe1 }, + { "gcc_ddrss_gpu_axi_clk", &gcc.mux, 0xc4 }, + { "gcc_ddrss_pcie_sf_tbu_clk", &gcc.mux, 0xc5 }, + { "gcc_disp_ahb_clk", &gcc.mux, 0x45 }, + { "gcc_disp_hf_axi_clk", &gcc.mux, 0x4f }, + { "gcc_disp_sf_axi_clk", &gcc.mux, 0x50 }, + { "gcc_disp_xo_clk", &gcc.mux, 0x53 }, + { "gcc_gp1_clk", &gcc.mux, 0xef }, + { "gcc_gp2_clk", &gcc.mux, 0xf0 }, + { "gcc_gp3_clk", &gcc.mux, 0xf1 }, + { "gcc_gpu_cfg_ahb_clk", &gcc.mux, 0x161 }, + { "gcc_gpu_gpll0_clk_src", &gcc.mux, 0x167 }, + { "gcc_gpu_gpll0_div_clk_src", &gcc.mux, 0x168 }, + { "gcc_gpu_memnoc_gfx_clk", &gcc.mux, 0x164 }, + { "gcc_gpu_snoc_dvm_gfx_clk", &gcc.mux, 0x166 }, + { "gcc_npu_axi_clk", &gcc.mux, 0x17a }, + { "gcc_npu_bwmon_axi_clk", &gcc.mux, 0x19a }, + { "gcc_npu_bwmon_cfg_ahb_clk", &gcc.mux, 0x199 }, + { "gcc_npu_cfg_ahb_clk", &gcc.mux, 0x179 }, + { "gcc_npu_dma_clk", &gcc.mux, 0x17b }, + { "gcc_npu_gpll0_clk_src", &gcc.mux, 0x17e }, + { "gcc_npu_gpll0_div_clk_src", &gcc.mux, 0x17f }, + { "gcc_pcie0_phy_refgen_clk", &gcc.mux, 0x103 }, + { "gcc_pcie1_phy_refgen_clk", &gcc.mux, 0x104 }, + { "gcc_pcie2_phy_refgen_clk", &gcc.mux, 0x105 }, + { "gcc_pcie_0_aux_clk", &gcc.mux, 0xf6 }, + { "gcc_pcie_0_cfg_ahb_clk", &gcc.mux, 0xf5 }, + { "gcc_pcie_0_mstr_axi_clk", &gcc.mux, 0xf4 }, + { "gcc_pcie_0_pipe_clk", &gcc.mux, 0xf7 }, + { "gcc_pcie_0_slv_axi_clk", &gcc.mux, 0xf3 }, + { "gcc_pcie_0_slv_q2a_axi_clk", &gcc.mux, 0xf2 }, + { "gcc_pcie_1_aux_clk", &gcc.mux, 0xfe }, + { "gcc_pcie_1_cfg_ahb_clk", &gcc.mux, 0xfd }, + { "gcc_pcie_1_mstr_axi_clk", &gcc.mux, 0xfc }, + { "gcc_pcie_1_pipe_clk", &gcc.mux, 0xff }, + { "gcc_pcie_1_slv_axi_clk", &gcc.mux, 0xfb }, + { "gcc_pcie_1_slv_q2a_axi_clk", &gcc.mux, 0xfa }, + { "gcc_pcie_2_aux_clk", &gcc.mux, 0x191 }, + { "gcc_pcie_2_cfg_ahb_clk", &gcc.mux, 0x190 }, + { "gcc_pcie_2_mstr_axi_clk", &gcc.mux, 0x18f }, + { "gcc_pcie_2_pipe_clk", &gcc.mux, 0x192 }, + { "gcc_pcie_2_slv_axi_clk", &gcc.mux, 0x18e }, + { "gcc_pcie_2_slv_q2a_axi_clk", &gcc.mux, 0x18d }, + { "gcc_pcie_phy_aux_clk", &gcc.mux, 0x102 }, + { "gcc_pdm2_clk", &gcc.mux, 0x9d }, + { "gcc_pdm_ahb_clk", &gcc.mux, 0x9b }, + { "gcc_pdm_xo4_clk", &gcc.mux, 0x9c }, + { "gcc_prng_ahb_clk", &gcc.mux, 0x9e }, + { "gcc_qmip_camera_nrt_ahb_clk", &gcc.mux, 0x48 }, + { "gcc_qmip_camera_rt_ahb_clk", &gcc.mux, 0x49 }, + { "gcc_qmip_disp_ahb_clk", &gcc.mux, 0x4a }, + { "gcc_qmip_video_cvp_ahb_clk", &gcc.mux, 0x46 }, + { "gcc_qmip_video_vcodec_ahb_clk", &gcc.mux, 0x47 }, + { "gcc_qupv3_wrap0_core_2x_clk", &gcc.mux, 0x88 }, + { "gcc_qupv3_wrap0_core_clk", &gcc.mux, 0x87 }, + { "gcc_qupv3_wrap0_s0_clk", &gcc.mux, 0x89 }, + { "gcc_qupv3_wrap0_s1_clk", &gcc.mux, 0x8a }, + { "gcc_qupv3_wrap0_s2_clk", &gcc.mux, 0x8b }, + { "gcc_qupv3_wrap0_s3_clk", &gcc.mux, 0x8c }, + { "gcc_qupv3_wrap0_s4_clk", &gcc.mux, 0x8d }, + { "gcc_qupv3_wrap0_s5_clk", &gcc.mux, 0x8e }, + { "gcc_qupv3_wrap0_s6_clk", &gcc.mux, 0x8f }, + { "gcc_qupv3_wrap0_s7_clk", &gcc.mux, 0x90 }, + { "gcc_qupv3_wrap1_core_2x_clk", &gcc.mux, 0x94 }, + { "gcc_qupv3_wrap1_core_clk", &gcc.mux, 0x93 }, + { "gcc_qupv3_wrap1_s0_clk", &gcc.mux, 0x95 }, + { "gcc_qupv3_wrap1_s1_clk", &gcc.mux, 0x96 }, + { "gcc_qupv3_wrap1_s2_clk", &gcc.mux, 0x97 }, + { "gcc_qupv3_wrap1_s3_clk", &gcc.mux, 0x98 }, + { "gcc_qupv3_wrap1_s4_clk", &gcc.mux, 0x99 }, + { "gcc_qupv3_wrap1_s5_clk", &gcc.mux, 0x9a }, + { "gcc_qupv3_wrap2_core_2x_clk", &gcc.mux, 0x184 }, + { "gcc_qupv3_wrap2_core_clk", &gcc.mux, 0x183 }, + { "gcc_qupv3_wrap2_s0_clk", &gcc.mux, 0x185 }, + { "gcc_qupv3_wrap2_s1_clk", &gcc.mux, 0x186 }, + { "gcc_qupv3_wrap2_s2_clk", &gcc.mux, 0x187 }, + { "gcc_qupv3_wrap2_s3_clk", &gcc.mux, 0x188 }, + { "gcc_qupv3_wrap2_s4_clk", &gcc.mux, 0x189 }, + { "gcc_qupv3_wrap2_s5_clk", &gcc.mux, 0x18a }, + { "gcc_qupv3_wrap_0_m_ahb_clk", &gcc.mux, 0x85 }, + { "gcc_qupv3_wrap_0_s_ahb_clk", &gcc.mux, 0x86 }, + { "gcc_qupv3_wrap_1_m_ahb_clk", &gcc.mux, 0x91 }, + { "gcc_qupv3_wrap_1_s_ahb_clk", &gcc.mux, 0x92 }, + { "gcc_qupv3_wrap_2_m_ahb_clk", &gcc.mux, 0x181 }, + { "gcc_qupv3_wrap_2_s_ahb_clk", &gcc.mux, 0x182 }, + { "gcc_sdcc2_ahb_clk", &gcc.mux, 0x82 }, + { "gcc_sdcc2_apps_clk", &gcc.mux, 0x81 }, + { "gcc_sdcc4_ahb_clk", &gcc.mux, 0x84 }, + { "gcc_sdcc4_apps_clk", &gcc.mux, 0x83 }, + { "gcc_sys_noc_cpuss_ahb_clk", &gcc.mux, 0xc }, + { "gcc_tsif_ahb_clk", &gcc.mux, 0x9f }, + { "gcc_tsif_inactivity_timers_clk", &gcc.mux, 0xa1 }, + { "gcc_tsif_ref_clk", &gcc.mux, 0xa0 }, + { "gcc_ufs_card_ahb_clk", &gcc.mux, 0x107 }, + { "gcc_ufs_card_axi_clk", &gcc.mux, 0x106 }, + { "gcc_ufs_card_ice_core_clk", &gcc.mux, 0x10d }, + { "gcc_ufs_card_phy_aux_clk", &gcc.mux, 0x10e }, + { "gcc_ufs_card_rx_symbol_0_clk", &gcc.mux, 0x109 }, + { "gcc_ufs_card_rx_symbol_1_clk", &gcc.mux, 0x10f }, + { "gcc_ufs_card_tx_symbol_0_clk", &gcc.mux, 0x108 }, + { "gcc_ufs_card_unipro_core_clk", &gcc.mux, 0x10c }, + { "gcc_ufs_phy_ahb_clk", &gcc.mux, 0x113 }, + { "gcc_ufs_phy_axi_clk", &gcc.mux, 0x112 }, + { "gcc_ufs_phy_ice_core_clk", &gcc.mux, 0x119 }, + { "gcc_ufs_phy_phy_aux_clk", &gcc.mux, 0x11a }, + { "gcc_ufs_phy_rx_symbol_0_clk", &gcc.mux, 0x115 }, + { "gcc_ufs_phy_rx_symbol_1_clk", &gcc.mux, 0x11b }, + { "gcc_ufs_phy_tx_symbol_0_clk", &gcc.mux, 0x114 }, + { "gcc_ufs_phy_unipro_core_clk", &gcc.mux, 0x118 }, + { "gcc_usb30_prim_master_clk", &gcc.mux, 0x6e }, + { "gcc_usb30_prim_mock_utmi_clk", &gcc.mux, 0x70 }, + { "gcc_usb30_prim_sleep_clk", &gcc.mux, 0x6f }, + { "gcc_usb30_sec_master_clk", &gcc.mux, 0x75 }, + { "gcc_usb30_sec_mock_utmi_clk", &gcc.mux, 0x77 }, + { "gcc_usb30_sec_sleep_clk", &gcc.mux, 0x76 }, + { "gcc_usb3_prim_phy_aux_clk", &gcc.mux, 0x71 }, + { "gcc_usb3_prim_phy_com_aux_clk", &gcc.mux, 0x72 }, + { "gcc_usb3_prim_phy_pipe_clk", &gcc.mux, 0x73 }, + { "gcc_usb3_sec_phy_aux_clk", &gcc.mux, 0x78 }, + { "gcc_usb3_sec_phy_com_aux_clk", &gcc.mux, 0x79 }, + { "gcc_usb3_sec_phy_pipe_clk", &gcc.mux, 0x7a }, + { "gcc_video_ahb_clk", &gcc.mux, 0x43 }, + { "gcc_video_axi0_clk", &gcc.mux, 0x4b }, + { "gcc_video_axi1_clk", &gcc.mux, 0x4c }, + { "gcc_video_xo_clk", &gcc.mux, 0x51 }, + { "measure_only_cnoc_clk", &gcc.mux, 0x19 }, + { "measure_only_ipa_2x_clk", &gcc.mux, 0x147 }, + { "measure_only_memnoc_clk", &gcc.mux, 0xcc }, + { "measure_only_snoc_clk", &gcc.mux, 0x7 }, + + { "gpu_cc_ahb_clk", &gpu_cc, 0x10 }, + { "gpu_cc_crc_ahb_clk", &gpu_cc, 0x11 }, + { "gpu_cc_cx_apb_clk", &gpu_cc, 0x14 }, + { "gpu_cc_cx_gmu_clk", &gpu_cc, 0x18 }, + { "gpu_cc_cx_qdss_at_clk", &gpu_cc, 0x12 }, + { "gpu_cc_cx_qdss_trig_clk", &gpu_cc, 0x17 }, + { "gpu_cc_cx_qdss_tsctr_clk", &gpu_cc, 0x13 }, + { "gpu_cc_cx_snoc_dvm_clk", &gpu_cc, 0x15 }, + { "gpu_cc_cxo_aon_clk", &gpu_cc, 0xa }, + { "gpu_cc_cxo_clk", &gpu_cc, 0x19 }, + { "gpu_cc_gx_gmu_clk", &gpu_cc, 0xf }, + { "gpu_cc_gx_qdss_tsctr_clk", &gpu_cc, 0xd }, + { "gpu_cc_gx_vsense_clk", &gpu_cc, 0xc }, + { "gpu_cc_sleep_clk", &gpu_cc, 0x16 }, + { "measure_only_gpu_cc_cx_gfx3d_clk", &gpu_cc, 0x1a }, + { "measure_only_gpu_cc_cx_gfx3d_slv_clk", &gpu_cc, 0x1b }, + { "measure_only_gpu_cc_gx_gfx3d_clk", &gpu_cc, 0xb }, + + { "npu_cc_atb_clk", &npu_cc, 0x17 }, + { "npu_cc_bto_core_clk", &npu_cc, 0x19 }, + { "npu_cc_bwmon_clk", &npu_cc, 0x18 }, + { "npu_cc_cal_hm0_cdc_clk", &npu_cc, 0xb }, + { "npu_cc_cal_hm0_clk", &npu_cc, 0x2 }, + { "npu_cc_cal_hm0_dpm_ip_clk", &npu_cc, 0xc }, + { "npu_cc_cal_hm0_perf_cnt_clk", &npu_cc, 0xd }, + { "npu_cc_cal_hm1_cdc_clk", &npu_cc, 0xe }, + { "npu_cc_cal_hm1_clk", &npu_cc, 0x3 }, + { "npu_cc_cal_hm1_dpm_ip_clk", &npu_cc, 0xf }, + { "npu_cc_cal_hm1_perf_cnt_clk", &npu_cc, 0x10 }, + { "npu_cc_core_clk", &npu_cc, 0x4 }, + { "npu_cc_dl_dpm_clk", &npu_cc, 0x23 }, + { "npu_cc_dl_llm_clk", &npu_cc, 0x22 }, + { "npu_cc_dpm_clk", &npu_cc, 0x8 }, + { "npu_cc_dpm_temp_clk", &npu_cc, 0x14 }, + { "npu_cc_dpm_xo_clk", &npu_cc, 0xa }, + { "npu_cc_dsp_ahbm_clk", &npu_cc, 0x1c }, + { "npu_cc_dsp_ahbs_clk", &npu_cc, 0x1b }, + { "npu_cc_dsp_axi_clk", &npu_cc, 0x1e }, + { "npu_cc_dsp_bwmon_ahb_clk", &npu_cc, 0x1d }, + { "npu_cc_dsp_bwmon_clk", &npu_cc, 0x1f }, + { "npu_cc_isense_clk", &npu_cc, 0x7 }, + { "npu_cc_llm_clk", &npu_cc, 0x6 }, + { "npu_cc_llm_curr_clk", &npu_cc, 0x21 }, + { "npu_cc_llm_temp_clk", &npu_cc, 0x15 }, + { "npu_cc_llm_xo_clk", &npu_cc, 0x9 }, + { "npu_cc_noc_ahb_clk", &npu_cc, 0x13 }, + { "npu_cc_noc_axi_clk", &npu_cc, 0x12 }, + { "npu_cc_noc_dma_clk", &npu_cc, 0x11 }, + { "npu_cc_rsc_xo_clk", &npu_cc, 0x1a }, + { "npu_cc_s2p_clk", &npu_cc, 0x16 }, + { "npu_cc_xo_clk", &npu_cc, 0x1 }, + + { "video_cc_ahb_clk", &video_cc, 0x7 }, + { "video_cc_mvs0_clk", &video_cc, 0x3 }, + { "video_cc_mvs0c_clk", &video_cc, 0x1 }, + { "video_cc_mvs1_clk", &video_cc, 0x5 }, + { "video_cc_mvs1_div2_clk", &video_cc, 0x8 }, + { "video_cc_mvs1c_clk", &video_cc, 0x9 }, + { "video_cc_sleep_clk", &video_cc, 0xc }, + { "video_cc_xo_clk", &video_cc, 0xb }, + + { "measure_only_mccc_clk", &mc_cc, 0x50 }, + + { "measure_only_apcs_gold_post_acd_clk", &apss_cc, 0x25, /* TODO: Are these pre_div_vals? */ 8 }, + { "measure_only_apcs_goldplus_post_acd_clk", &apss_cc, 0x61, /* TODO: Are these pre_div_vals? */ 8 }, + { "measure_only_apcs_l3_post_acd_clk", &apss_cc, 0x41, /* TODO: Are these pre_div_vals? */ 4 }, + { "measure_only_apcs_silver_post_acd_clk", &apss_cc, 0x21, /* TODO: Are these pre_div_vals? */ 4 }, {} }; diff --git a/sm8350.c b/sm8350.c index 0e52f2a..38beaeb 100644 --- a/sm8350.c +++ b/sm8350.c @@ -39,19 +39,21 @@ #include "debugcc.h" -static struct debug_mux gcc = { - .phys = 0x162000, - .size = 0x1f0000, +static struct gcc_mux gcc = { + .mux = { + .phys = 0x162000, + .size = 0x1f0000, - .enable_reg = 0x8, - .enable_mask = BIT(0), + .enable_reg = 0x8, + .enable_mask = BIT(0), - .mux_reg = 0x0, - .mux_mask = 0x3ff, + .mux_reg = 0x0, + .mux_mask = 0x3ff, - .div_reg = 0x4, - .div_mask = 0xf, - .div_val = 2, + .div_reg = 0x4, + .div_mask = 0xf, + .div_val = 2, + }, .xo_div4_reg = 0xc, .debug_ctl_reg = 0x38, @@ -63,6 +65,10 @@ static struct debug_mux cam_cc = { .size = 0x10000, .block_name = "cam", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x4d, + .enable_reg = 0xd008, .enable_mask = BIT(0), @@ -79,6 +85,10 @@ static struct debug_mux disp_cc = { .size = 0x10000, .block_name = "disp", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x53, + .enable_reg = 0x500c, .enable_mask = BIT(0), @@ -95,6 +105,10 @@ static struct debug_mux gpu_cc = { .size = 0x9000, .block_name = "gpu", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x153, + .enable_reg = 0x1100, .enable_mask = BIT(0), @@ -111,6 +125,10 @@ static struct debug_mux video_cc = { .size = 0x10000, .block_name = "video", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x5a, + .enable_reg = 0xebc, .enable_mask = BIT(0), @@ -140,273 +158,273 @@ struct measure_clk { static struct measure_clk sm8350_clocks[] = { /* cam_cc_debug_mux is 0x4D */ - { "cam_cc_bps_ahb_clk", &gcc, 0x4D, &cam_cc, 0x18 }, - { "cam_cc_bps_areg_clk", &gcc, 0x4D, &cam_cc, 0x17 }, - { "cam_cc_bps_axi_clk", &gcc, 0x4D, &cam_cc, 0x16 }, - { "cam_cc_bps_clk", &gcc, 0x4D, &cam_cc, 0x14 }, - { "cam_cc_camnoc_axi_clk", &gcc, 0x4D, &cam_cc, 0x3C }, - { "cam_cc_camnoc_dcd_xo_clk", &gcc, 0x4D, &cam_cc, 0x3D }, - { "cam_cc_cci_0_clk", &gcc, 0x4D, &cam_cc, 0x39 }, - { "cam_cc_cci_1_clk", &gcc, 0x4D, &cam_cc, 0x3A }, - { "cam_cc_core_ahb_clk", &gcc, 0x4D, &cam_cc, 0x40 }, - { "cam_cc_cpas_ahb_clk", &gcc, 0x4D, &cam_cc, 0x3B }, - { "cam_cc_csi0phytimer_clk", &gcc, 0x4D, &cam_cc, 0x8 }, - { "cam_cc_csi1phytimer_clk", &gcc, 0x4D, &cam_cc, 0xA }, - { "cam_cc_csi2phytimer_clk", &gcc, 0x4D, &cam_cc, 0xC }, - { "cam_cc_csi3phytimer_clk", &gcc, 0x4D, &cam_cc, 0xE }, - { "cam_cc_csi4phytimer_clk", &gcc, 0x4D, &cam_cc, 0x10 }, - { "cam_cc_csi5phytimer_clk", &gcc, 0x4D, &cam_cc, 0x12 }, - { "cam_cc_csiphy0_clk", &gcc, 0x4D, &cam_cc, 0x9 }, - { "cam_cc_csiphy1_clk", &gcc, 0x4D, &cam_cc, 0xB }, - { "cam_cc_csiphy2_clk", &gcc, 0x4D, &cam_cc, 0xD }, - { "cam_cc_csiphy3_clk", &gcc, 0x4D, &cam_cc, 0xF }, - { "cam_cc_csiphy4_clk", &gcc, 0x4D, &cam_cc, 0x11 }, - { "cam_cc_csiphy5_clk", &gcc, 0x4D, &cam_cc, 0x13 }, - { "cam_cc_icp_ahb_clk", &gcc, 0x4D, &cam_cc, 0x36 }, - { "cam_cc_icp_clk", &gcc, 0x4D, &cam_cc, 0x35 }, - { "cam_cc_ife_0_ahb_clk", &gcc, 0x4D, &cam_cc, 0x26 }, - { "cam_cc_ife_0_areg_clk", &gcc, 0x4D, &cam_cc, 0x1F }, - { "cam_cc_ife_0_axi_clk", &gcc, 0x4D, &cam_cc, 0x25 }, - { "cam_cc_ife_0_clk", &gcc, 0x4D, &cam_cc, 0x1E }, - { "cam_cc_ife_0_cphy_rx_clk", &gcc, 0x4D, &cam_cc, 0x24 }, - { "cam_cc_ife_0_csid_clk", &gcc, 0x4D, &cam_cc, 0x22 }, - { "cam_cc_ife_0_dsp_clk", &gcc, 0x4D, &cam_cc, 0x21 }, - { "cam_cc_ife_1_ahb_clk", &gcc, 0x4D, &cam_cc, 0x2E }, - { "cam_cc_ife_1_areg_clk", &gcc, 0x4D, &cam_cc, 0x29 }, - { "cam_cc_ife_1_axi_clk", &gcc, 0x4D, &cam_cc, 0x2D }, - { "cam_cc_ife_1_clk", &gcc, 0x4D, &cam_cc, 0x27 }, - { "cam_cc_ife_1_cphy_rx_clk", &gcc, 0x4D, &cam_cc, 0x2C }, - { "cam_cc_ife_1_csid_clk", &gcc, 0x4D, &cam_cc, 0x2B }, - { "cam_cc_ife_1_dsp_clk", &gcc, 0x4D, &cam_cc, 0x2A }, - { "cam_cc_ife_2_ahb_clk", &gcc, 0x4D, &cam_cc, 0x54 }, - { "cam_cc_ife_2_areg_clk", &gcc, 0x4D, &cam_cc, 0x37 }, - { "cam_cc_ife_2_axi_clk", &gcc, 0x4D, &cam_cc, 0x53 }, - { "cam_cc_ife_2_clk", &gcc, 0x4D, &cam_cc, 0x7 }, - { "cam_cc_ife_2_cphy_rx_clk", &gcc, 0x4D, &cam_cc, 0x52 }, - { "cam_cc_ife_2_csid_clk", &gcc, 0x4D, &cam_cc, 0x51 }, - { "cam_cc_ife_lite_ahb_clk", &gcc, 0x4D, &cam_cc, 0x32 }, - { "cam_cc_ife_lite_axi_clk", &gcc, 0x4D, &cam_cc, 0x49 }, - { "cam_cc_ife_lite_clk", &gcc, 0x4D, &cam_cc, 0x2F }, - { "cam_cc_ife_lite_cphy_rx_clk", &gcc, 0x4D, &cam_cc, 0x31 }, - { "cam_cc_ife_lite_csid_clk", &gcc, 0x4D, &cam_cc, 0x30 }, - { "cam_cc_ipe_0_ahb_clk", &gcc, 0x4D, &cam_cc, 0x1D }, - { "cam_cc_ipe_0_areg_clk", &gcc, 0x4D, &cam_cc, 0x1C }, - { "cam_cc_ipe_0_axi_clk", &gcc, 0x4D, &cam_cc, 0x1B }, - { "cam_cc_ipe_0_clk", &gcc, 0x4D, &cam_cc, 0x19 }, - { "cam_cc_jpeg_clk", &gcc, 0x4D, &cam_cc, 0x33 }, - { "cam_cc_mclk0_clk", &gcc, 0x4D, &cam_cc, 0x1 }, - { "cam_cc_mclk1_clk", &gcc, 0x4D, &cam_cc, 0x2 }, - { "cam_cc_mclk2_clk", &gcc, 0x4D, &cam_cc, 0x3 }, - { "cam_cc_mclk3_clk", &gcc, 0x4D, &cam_cc, 0x4 }, - { "cam_cc_mclk4_clk", &gcc, 0x4D, &cam_cc, 0x5 }, - { "cam_cc_mclk5_clk", &gcc, 0x4D, &cam_cc, 0x6 }, - { "cam_cc_sbi_ahb_clk", &gcc, 0x4D, &cam_cc, 0x4E }, - { "cam_cc_sbi_axi_clk", &gcc, 0x4D, &cam_cc, 0x4D }, - { "cam_cc_sbi_clk", &gcc, 0x4D, &cam_cc, 0x4A }, - { "cam_cc_sbi_cphy_rx_0_clk", &gcc, 0x4D, &cam_cc, 0x4C }, - { "cam_cc_sbi_cphy_rx_1_clk", &gcc, 0x4D, &cam_cc, 0x56 }, - { "cam_cc_sbi_csid_0_clk", &gcc, 0x4D, &cam_cc, 0x4B }, - { "cam_cc_sbi_csid_1_clk", &gcc, 0x4D, &cam_cc, 0x57 }, - { "cam_cc_sbi_ife_0_clk", &gcc, 0x4D, &cam_cc, 0x4F }, - { "cam_cc_sbi_ife_1_clk", &gcc, 0x4D, &cam_cc, 0x50 }, - { "cam_cc_sbi_ife_2_clk", &gcc, 0x4D, &cam_cc, 0x55 }, - { "cam_cc_sleep_clk", &gcc, 0x4D, &cam_cc, 0x42 }, + { "cam_cc_bps_ahb_clk", &cam_cc, 0x18 }, + { "cam_cc_bps_areg_clk", &cam_cc, 0x17 }, + { "cam_cc_bps_axi_clk", &cam_cc, 0x16 }, + { "cam_cc_bps_clk", &cam_cc, 0x14 }, + { "cam_cc_camnoc_axi_clk", &cam_cc, 0x3C }, + { "cam_cc_camnoc_dcd_xo_clk", &cam_cc, 0x3D }, + { "cam_cc_cci_0_clk", &cam_cc, 0x39 }, + { "cam_cc_cci_1_clk", &cam_cc, 0x3A }, + { "cam_cc_core_ahb_clk", &cam_cc, 0x40 }, + { "cam_cc_cpas_ahb_clk", &cam_cc, 0x3B }, + { "cam_cc_csi0phytimer_clk", &cam_cc, 0x8 }, + { "cam_cc_csi1phytimer_clk", &cam_cc, 0xA }, + { "cam_cc_csi2phytimer_clk", &cam_cc, 0xC }, + { "cam_cc_csi3phytimer_clk", &cam_cc, 0xE }, + { "cam_cc_csi4phytimer_clk", &cam_cc, 0x10 }, + { "cam_cc_csi5phytimer_clk", &cam_cc, 0x12 }, + { "cam_cc_csiphy0_clk", &cam_cc, 0x9 }, + { "cam_cc_csiphy1_clk", &cam_cc, 0xB }, + { "cam_cc_csiphy2_clk", &cam_cc, 0xD }, + { "cam_cc_csiphy3_clk", &cam_cc, 0xF }, + { "cam_cc_csiphy4_clk", &cam_cc, 0x11 }, + { "cam_cc_csiphy5_clk", &cam_cc, 0x13 }, + { "cam_cc_icp_ahb_clk", &cam_cc, 0x36 }, + { "cam_cc_icp_clk", &cam_cc, 0x35 }, + { "cam_cc_ife_0_ahb_clk", &cam_cc, 0x26 }, + { "cam_cc_ife_0_areg_clk", &cam_cc, 0x1F }, + { "cam_cc_ife_0_axi_clk", &cam_cc, 0x25 }, + { "cam_cc_ife_0_clk", &cam_cc, 0x1E }, + { "cam_cc_ife_0_cphy_rx_clk", &cam_cc, 0x24 }, + { "cam_cc_ife_0_csid_clk", &cam_cc, 0x22 }, + { "cam_cc_ife_0_dsp_clk", &cam_cc, 0x21 }, + { "cam_cc_ife_1_ahb_clk", &cam_cc, 0x2E }, + { "cam_cc_ife_1_areg_clk", &cam_cc, 0x29 }, + { "cam_cc_ife_1_axi_clk", &cam_cc, 0x2D }, + { "cam_cc_ife_1_clk", &cam_cc, 0x27 }, + { "cam_cc_ife_1_cphy_rx_clk", &cam_cc, 0x2C }, + { "cam_cc_ife_1_csid_clk", &cam_cc, 0x2B }, + { "cam_cc_ife_1_dsp_clk", &cam_cc, 0x2A }, + { "cam_cc_ife_2_ahb_clk", &cam_cc, 0x54 }, + { "cam_cc_ife_2_areg_clk", &cam_cc, 0x37 }, + { "cam_cc_ife_2_axi_clk", &cam_cc, 0x53 }, + { "cam_cc_ife_2_clk", &cam_cc, 0x7 }, + { "cam_cc_ife_2_cphy_rx_clk", &cam_cc, 0x52 }, + { "cam_cc_ife_2_csid_clk", &cam_cc, 0x51 }, + { "cam_cc_ife_lite_ahb_clk", &cam_cc, 0x32 }, + { "cam_cc_ife_lite_axi_clk", &cam_cc, 0x49 }, + { "cam_cc_ife_lite_clk", &cam_cc, 0x2F }, + { "cam_cc_ife_lite_cphy_rx_clk", &cam_cc, 0x31 }, + { "cam_cc_ife_lite_csid_clk", &cam_cc, 0x30 }, + { "cam_cc_ipe_0_ahb_clk", &cam_cc, 0x1D }, + { "cam_cc_ipe_0_areg_clk", &cam_cc, 0x1C }, + { "cam_cc_ipe_0_axi_clk", &cam_cc, 0x1B }, + { "cam_cc_ipe_0_clk", &cam_cc, 0x19 }, + { "cam_cc_jpeg_clk", &cam_cc, 0x33 }, + { "cam_cc_mclk0_clk", &cam_cc, 0x1 }, + { "cam_cc_mclk1_clk", &cam_cc, 0x2 }, + { "cam_cc_mclk2_clk", &cam_cc, 0x3 }, + { "cam_cc_mclk3_clk", &cam_cc, 0x4 }, + { "cam_cc_mclk4_clk", &cam_cc, 0x5 }, + { "cam_cc_mclk5_clk", &cam_cc, 0x6 }, + { "cam_cc_sbi_ahb_clk", &cam_cc, 0x4E }, + { "cam_cc_sbi_axi_clk", &cam_cc, 0x4D }, + { "cam_cc_sbi_clk", &cam_cc, 0x4A }, + { "cam_cc_sbi_cphy_rx_0_clk", &cam_cc, 0x4C }, + { "cam_cc_sbi_cphy_rx_1_clk", &cam_cc, 0x56 }, + { "cam_cc_sbi_csid_0_clk", &cam_cc, 0x4B }, + { "cam_cc_sbi_csid_1_clk", &cam_cc, 0x57 }, + { "cam_cc_sbi_ife_0_clk", &cam_cc, 0x4F }, + { "cam_cc_sbi_ife_1_clk", &cam_cc, 0x50 }, + { "cam_cc_sbi_ife_2_clk", &cam_cc, 0x55 }, + { "cam_cc_sleep_clk", &cam_cc, 0x42 }, /* disp_cc_debug_mux is 0x53 */ - { "disp_cc_mdss_ahb_clk", &gcc, 0x53, &disp_cc, 0x2A }, - { "disp_cc_mdss_byte0_clk", &gcc, 0x53, &disp_cc, 0x15 }, - { "disp_cc_mdss_byte0_intf_clk", &gcc, 0x53, &disp_cc, 0x16 }, - { "disp_cc_mdss_byte1_clk", &gcc, 0x53, &disp_cc, 0x17 }, - { "disp_cc_mdss_byte1_intf_clk", &gcc, 0x53, &disp_cc, 0x18 }, - { "disp_cc_mdss_dp_aux1_clk", &gcc, 0x53, &disp_cc, 0x25 }, - { "disp_cc_mdss_dp_aux_clk", &gcc, 0x53, &disp_cc, 0x20 }, - { "disp_cc_mdss_dp_link1_clk", &gcc, 0x53, &disp_cc, 0x22 }, - { "disp_cc_mdss_dp_link1_intf_clk", &gcc, 0x53, &disp_cc, 0x23 }, - { "disp_cc_mdss_dp_link_clk", &gcc, 0x53, &disp_cc, 0x1B }, - { "disp_cc_mdss_dp_link_intf_clk", &gcc, 0x53, &disp_cc, 0x1C }, - { "disp_cc_mdss_dp_pixel1_clk", &gcc, 0x53, &disp_cc, 0x1F }, - { "disp_cc_mdss_dp_pixel2_clk", &gcc, 0x53, &disp_cc, 0x21 }, - { "disp_cc_mdss_dp_pixel_clk", &gcc, 0x53, &disp_cc, 0x1E }, - { "disp_cc_mdss_edp_aux_clk", &gcc, 0x53, &disp_cc, 0x29 }, - { "disp_cc_mdss_edp_link_clk", &gcc, 0x53, &disp_cc, 0x27 }, - { "disp_cc_mdss_edp_link_intf_clk", &gcc, 0x53, &disp_cc, 0x28 }, - { "disp_cc_mdss_edp_pixel_clk", &gcc, 0x53, &disp_cc, 0x26 }, - { "disp_cc_mdss_esc0_clk", &gcc, 0x53, &disp_cc, 0x19 }, - { "disp_cc_mdss_esc1_clk", &gcc, 0x53, &disp_cc, 0x1A }, - { "disp_cc_mdss_mdp_clk", &gcc, 0x53, &disp_cc, 0x11 }, - { "disp_cc_mdss_mdp_lut_clk", &gcc, 0x53, &disp_cc, 0x13 }, - { "disp_cc_mdss_non_gdsc_ahb_clk", &gcc, 0x53, &disp_cc, 0x2B }, - { "disp_cc_mdss_pclk0_clk", &gcc, 0x53, &disp_cc, 0xF }, - { "disp_cc_mdss_pclk1_clk", &gcc, 0x53, &disp_cc, 0x10 }, - { "disp_cc_mdss_rot_clk", &gcc, 0x53, &disp_cc, 0x12 }, - { "disp_cc_mdss_rscc_ahb_clk", &gcc, 0x53, &disp_cc, 0x2D }, - { "disp_cc_mdss_rscc_vsync_clk", &gcc, 0x53, &disp_cc, 0x2C }, - { "disp_cc_mdss_vsync_clk", &gcc, 0x53, &disp_cc, 0x14 }, - { "disp_cc_sleep_clk", &gcc, 0x53, &disp_cc, 0x36 }, -// gcc - { "core_bi_pll_test_se", &gcc, 0x5 }, - { "gcc_aggre_noc_pcie_0_axi_clk", &gcc, 0x138 }, - { "gcc_aggre_noc_pcie_1_axi_clk", &gcc, 0x139 }, - { "gcc_aggre_noc_pcie_tbu_clk", &gcc, 0x34 }, - { "gcc_aggre_ufs_card_axi_clk", &gcc, 0x13D }, - { "gcc_aggre_ufs_phy_axi_clk", &gcc, 0x13C }, - { "gcc_aggre_usb3_prim_axi_clk", &gcc, 0x13A }, - { "gcc_aggre_usb3_sec_axi_clk", &gcc, 0x13B }, - { "gcc_boot_rom_ahb_clk", &gcc, 0xA8 }, - { "gcc_camera_ahb_clk", &gcc, 0x47 }, - { "gcc_camera_hf_axi_clk", &gcc, 0x4A }, - { "gcc_camera_sf_axi_clk", &gcc, 0x4B }, - { "gcc_camera_xo_clk", &gcc, 0x4C }, - { "gcc_cfg_noc_usb3_prim_axi_clk", &gcc, 0x1F }, - { "gcc_cfg_noc_usb3_sec_axi_clk", &gcc, 0x20 }, - { "gcc_ddrss_gpu_axi_clk", &gcc, 0xC9 }, - { "gcc_ddrss_pcie_sf_tbu_clk", &gcc, 0xCA }, - { "gcc_disp_ahb_clk", &gcc, 0x4E }, - { "gcc_disp_hf_axi_clk", &gcc, 0x50 }, - { "gcc_disp_sf_axi_clk", &gcc, 0x51 }, - { "gcc_disp_xo_clk", &gcc, 0x52 }, - { "gcc_gp1_clk", &gcc, 0xF1 }, - { "gcc_gp2_clk", &gcc, 0xF2 }, - { "gcc_gp3_clk", &gcc, 0xF3 }, - { "gcc_gpu_cfg_ahb_clk", &gcc, 0x151 }, - { "gcc_gpu_gpll0_clk_src", &gcc, 0x158 }, - { "gcc_gpu_gpll0_div_clk_src", &gcc, 0x159 }, - { "gcc_gpu_memnoc_gfx_clk", &gcc, 0x154 }, - { "gcc_gpu_snoc_dvm_gfx_clk", &gcc, 0x157 }, - { "gcc_pcie0_phy_rchng_clk", &gcc, 0xFA }, - { "gcc_pcie1_phy_rchng_clk", &gcc, 0x103 }, - { "gcc_pcie_0_aux_clk", &gcc, 0xF8 }, - { "gcc_pcie_0_cfg_ahb_clk", &gcc, 0xF7 }, - { "gcc_pcie_0_mstr_axi_clk", &gcc, 0xF6 }, - { "gcc_pcie_0_pipe_clk", &gcc, 0xF9 }, - { "gcc_pcie_0_slv_axi_clk", &gcc, 0xF5 }, - { "gcc_pcie_0_slv_q2a_axi_clk", &gcc, 0xF4 }, - { "gcc_pcie_1_aux_clk", &gcc, 0x101 }, - { "gcc_pcie_1_cfg_ahb_clk", &gcc, 0x100 }, - { "gcc_pcie_1_mstr_axi_clk", &gcc, 0xFF }, - { "gcc_pcie_1_pipe_clk", &gcc, 0x102 }, - { "gcc_pcie_1_slv_axi_clk", &gcc, 0xFE }, - { "gcc_pcie_1_slv_q2a_axi_clk", &gcc, 0xFD }, - { "gcc_pdm2_clk", &gcc, 0x9E }, - { "gcc_pdm_ahb_clk", &gcc, 0x9C }, - { "gcc_pdm_xo4_clk", &gcc, 0x9D }, - { "gcc_qmip_camera_nrt_ahb_clk", &gcc, 0x48 }, - { "gcc_qmip_camera_rt_ahb_clk", &gcc, 0x49 }, - { "gcc_qmip_disp_ahb_clk", &gcc, 0x4F }, - { "gcc_qmip_video_cvp_ahb_clk", &gcc, 0x55 }, - { "gcc_qmip_video_vcodec_ahb_clk", &gcc, 0x56 }, - { "gcc_qupv3_wrap0_core_2x_clk", &gcc, 0x89 }, - { "gcc_qupv3_wrap0_core_clk", &gcc, 0x88 }, - { "gcc_qupv3_wrap0_s0_clk", &gcc, 0x8A }, - { "gcc_qupv3_wrap0_s1_clk", &gcc, 0x8B }, - { "gcc_qupv3_wrap0_s2_clk", &gcc, 0x8C }, - { "gcc_qupv3_wrap0_s3_clk", &gcc, 0x8D }, - { "gcc_qupv3_wrap0_s4_clk", &gcc, 0x8E }, - { "gcc_qupv3_wrap0_s5_clk", &gcc, 0x8F }, - { "gcc_qupv3_wrap0_s6_clk", &gcc, 0x90 }, - { "gcc_qupv3_wrap0_s7_clk", &gcc, 0x91 }, - { "gcc_qupv3_wrap1_core_2x_clk", &gcc, 0x95 }, - { "gcc_qupv3_wrap1_core_clk", &gcc, 0x94 }, - { "gcc_qupv3_wrap1_s0_clk", &gcc, 0x96 }, - { "gcc_qupv3_wrap1_s1_clk", &gcc, 0x97 }, - { "gcc_qupv3_wrap1_s2_clk", &gcc, 0x98 }, - { "gcc_qupv3_wrap1_s3_clk", &gcc, 0x99 }, - { "gcc_qupv3_wrap1_s4_clk", &gcc, 0x9A }, - { "gcc_qupv3_wrap2_core_2x_clk", &gcc, 0x16E }, - { "gcc_qupv3_wrap2_core_clk", &gcc, 0x16D }, - { "gcc_qupv3_wrap2_s0_clk", &gcc, 0x16F }, - { "gcc_qupv3_wrap2_s1_clk", &gcc, 0x170 }, - { "gcc_qupv3_wrap2_s2_clk", &gcc, 0x171 }, - { "gcc_qupv3_wrap2_s3_clk", &gcc, 0x172 }, - { "gcc_qupv3_wrap2_s4_clk", &gcc, 0x173 }, - { "gcc_qupv3_wrap2_s5_clk", &gcc, 0x174 }, - { "gcc_qupv3_wrap_0_m_ahb_clk", &gcc, 0x86 }, - { "gcc_qupv3_wrap_0_s_ahb_clk", &gcc, 0x87 }, - { "gcc_qupv3_wrap_2_m_ahb_clk", &gcc, 0x16B }, - { "gcc_qupv3_wrap_2_s_ahb_clk", &gcc, 0x16C }, - { "gcc_sdcc2_ahb_clk", &gcc, 0x83 }, - { "gcc_sdcc2_apps_clk", &gcc, 0x82 }, - { "gcc_sdcc4_ahb_clk", &gcc, 0x85 }, - { "gcc_sdcc4_apps_clk", &gcc, 0x84 }, - { "gcc_throttle_pcie_ahb_clk", &gcc, 0x40 }, - { "gcc_ufs_card_ahb_clk", &gcc, 0x107 }, - { "gcc_ufs_card_axi_clk", &gcc, 0x106 }, - { "gcc_ufs_card_ice_core_clk", &gcc, 0x10D }, - { "gcc_ufs_card_phy_aux_clk", &gcc, 0x10E }, - { "gcc_ufs_card_rx_symbol_0_clk", &gcc, 0x109 }, - { "gcc_ufs_card_rx_symbol_1_clk", &gcc, 0x10F }, - { "gcc_ufs_card_tx_symbol_0_clk", &gcc, 0x108 }, - { "gcc_ufs_card_unipro_core_clk", &gcc, 0x10C }, - { "gcc_ufs_phy_ahb_clk", &gcc, 0x113 }, - { "gcc_ufs_phy_axi_clk", &gcc, 0x112 }, - { "gcc_ufs_phy_ice_core_clk", &gcc, 0x119 }, - { "gcc_ufs_phy_phy_aux_clk", &gcc, 0x11A }, - { "gcc_ufs_phy_rx_symbol_0_clk", &gcc, 0x115 }, - { "gcc_ufs_phy_rx_symbol_1_clk", &gcc, 0x11B }, - { "gcc_ufs_phy_tx_symbol_0_clk", &gcc, 0x114 }, - { "gcc_ufs_phy_unipro_core_clk", &gcc, 0x118 }, - { "gcc_usb30_prim_master_clk", &gcc, 0x6D }, - { "gcc_usb30_prim_mock_utmi_clk", &gcc, 0x6F }, - { "gcc_usb30_prim_sleep_clk", &gcc, 0x6E }, - { "gcc_usb30_sec_master_clk", &gcc, 0x76 }, - { "gcc_usb30_sec_mock_utmi_clk", &gcc, 0x78 }, - { "gcc_usb30_sec_sleep_clk", &gcc, 0x77 }, - { "gcc_usb3_prim_phy_aux_clk", &gcc, 0x70 }, - { "gcc_usb3_prim_phy_com_aux_clk", &gcc, 0x71 }, - { "gcc_usb3_prim_phy_pipe_clk", &gcc, 0x72 }, - { "gcc_usb3_sec_phy_aux_clk", &gcc, 0x79 }, - { "gcc_usb3_sec_phy_com_aux_clk", &gcc, 0x7A }, - { "gcc_usb3_sec_phy_pipe_clk", &gcc, 0x7B }, - { "gcc_video_ahb_clk", &gcc, 0x54 }, - { "gcc_video_axi0_clk", &gcc, 0x57 }, - { "gcc_video_axi1_clk", &gcc, 0x58 }, - { "gcc_video_xo_clk", &gcc, 0x59 }, - { "gpu_cc_debug_mux", &gcc, 0x153 }, - { "measure_only_cnoc_clk", &gcc, 0x18 }, - { "measure_only_ipa_2x_clk", &gcc, 0x140 }, - { "measure_only_memnoc_clk", &gcc, 0xCF }, - { "measure_only_snoc_clk", &gcc, 0x9 }, - { "pcie_0_pipe_clk", &gcc, 0xFB }, - { "pcie_1_pipe_clk", &gcc, 0x104 }, - { "ufs_card_rx_symbol_0_clk", &gcc, 0x10B }, - { "ufs_card_rx_symbol_1_clk", &gcc, 0x110 }, - { "ufs_card_tx_symbol_0_clk", &gcc, 0x10A }, - { "ufs_phy_rx_symbol_0_clk", &gcc, 0x117 }, - { "ufs_phy_rx_symbol_1_clk", &gcc, 0x11C }, - { "ufs_phy_tx_symbol_0_clk", &gcc, 0x116 }, - { "usb3_phy_wrapper_gcc_usb30_pipe_clk", &gcc, 0x7C }, - { "usb3_uni_phy_sec_gcc_usb30_pipe_clk", &gcc, 0x7D }, - { "mc_cc_debug_mux", &gcc, 0xD3 }, + { "disp_cc_mdss_ahb_clk", &disp_cc, 0x2A }, + { "disp_cc_mdss_byte0_clk", &disp_cc, 0x15 }, + { "disp_cc_mdss_byte0_intf_clk", &disp_cc, 0x16 }, + { "disp_cc_mdss_byte1_clk", &disp_cc, 0x17 }, + { "disp_cc_mdss_byte1_intf_clk", &disp_cc, 0x18 }, + { "disp_cc_mdss_dp_aux1_clk", &disp_cc, 0x25 }, + { "disp_cc_mdss_dp_aux_clk", &disp_cc, 0x20 }, + { "disp_cc_mdss_dp_link1_clk", &disp_cc, 0x22 }, + { "disp_cc_mdss_dp_link1_intf_clk", &disp_cc, 0x23 }, + { "disp_cc_mdss_dp_link_clk", &disp_cc, 0x1B }, + { "disp_cc_mdss_dp_link_intf_clk", &disp_cc, 0x1C }, + { "disp_cc_mdss_dp_pixel1_clk", &disp_cc, 0x1F }, + { "disp_cc_mdss_dp_pixel2_clk", &disp_cc, 0x21 }, + { "disp_cc_mdss_dp_pixel_clk", &disp_cc, 0x1E }, + { "disp_cc_mdss_edp_aux_clk", &disp_cc, 0x29 }, + { "disp_cc_mdss_edp_link_clk", &disp_cc, 0x27 }, + { "disp_cc_mdss_edp_link_intf_clk", &disp_cc, 0x28 }, + { "disp_cc_mdss_edp_pixel_clk", &disp_cc, 0x26 }, + { "disp_cc_mdss_esc0_clk", &disp_cc, 0x19 }, + { "disp_cc_mdss_esc1_clk", &disp_cc, 0x1A }, + { "disp_cc_mdss_mdp_clk", &disp_cc, 0x11 }, + { "disp_cc_mdss_mdp_lut_clk", &disp_cc, 0x13 }, + { "disp_cc_mdss_non_gdsc_ahb_clk", &disp_cc, 0x2B }, + { "disp_cc_mdss_pclk0_clk", &disp_cc, 0xF }, + { "disp_cc_mdss_pclk1_clk", &disp_cc, 0x10 }, + { "disp_cc_mdss_rot_clk", &disp_cc, 0x12 }, + { "disp_cc_mdss_rscc_ahb_clk", &disp_cc, 0x2D }, + { "disp_cc_mdss_rscc_vsync_clk", &disp_cc, 0x2C }, + { "disp_cc_mdss_vsync_clk", &disp_cc, 0x14 }, + { "disp_cc_sleep_clk", &disp_cc, 0x36 }, + + { "core_bi_pll_test_se", &gcc.mux, 0x5 }, + { "gcc_aggre_noc_pcie_0_axi_clk", &gcc.mux, 0x138 }, + { "gcc_aggre_noc_pcie_1_axi_clk", &gcc.mux, 0x139 }, + { "gcc_aggre_noc_pcie_tbu_clk", &gcc.mux, 0x34 }, + { "gcc_aggre_ufs_card_axi_clk", &gcc.mux, 0x13D }, + { "gcc_aggre_ufs_phy_axi_clk", &gcc.mux, 0x13C }, + { "gcc_aggre_usb3_prim_axi_clk", &gcc.mux, 0x13A }, + { "gcc_aggre_usb3_sec_axi_clk", &gcc.mux, 0x13B }, + { "gcc_boot_rom_ahb_clk", &gcc.mux, 0xA8 }, + { "gcc_camera_ahb_clk", &gcc.mux, 0x47 }, + { "gcc_camera_hf_axi_clk", &gcc.mux, 0x4A }, + { "gcc_camera_sf_axi_clk", &gcc.mux, 0x4B }, + { "gcc_camera_xo_clk", &gcc.mux, 0x4C }, + { "gcc_cfg_noc_usb3_prim_axi_clk", &gcc.mux, 0x1F }, + { "gcc_cfg_noc_usb3_sec_axi_clk", &gcc.mux, 0x20 }, + { "gcc_ddrss_gpu_axi_clk", &gcc.mux, 0xC9 }, + { "gcc_ddrss_pcie_sf_tbu_clk", &gcc.mux, 0xCA }, + { "gcc_disp_ahb_clk", &gcc.mux, 0x4E }, + { "gcc_disp_hf_axi_clk", &gcc.mux, 0x50 }, + { "gcc_disp_sf_axi_clk", &gcc.mux, 0x51 }, + { "gcc_disp_xo_clk", &gcc.mux, 0x52 }, + { "gcc_gp1_clk", &gcc.mux, 0xF1 }, + { "gcc_gp2_clk", &gcc.mux, 0xF2 }, + { "gcc_gp3_clk", &gcc.mux, 0xF3 }, + { "gcc_gpu_cfg_ahb_clk", &gcc.mux, 0x151 }, + { "gcc_gpu_gpll0_clk_src", &gcc.mux, 0x158 }, + { "gcc_gpu_gpll0_div_clk_src", &gcc.mux, 0x159 }, + { "gcc_gpu_memnoc_gfx_clk", &gcc.mux, 0x154 }, + { "gcc_gpu_snoc_dvm_gfx_clk", &gcc.mux, 0x157 }, + { "gcc_pcie0_phy_rchng_clk", &gcc.mux, 0xFA }, + { "gcc_pcie1_phy_rchng_clk", &gcc.mux, 0x103 }, + { "gcc_pcie_0_aux_clk", &gcc.mux, 0xF8 }, + { "gcc_pcie_0_cfg_ahb_clk", &gcc.mux, 0xF7 }, + { "gcc_pcie_0_mstr_axi_clk", &gcc.mux, 0xF6 }, + { "gcc_pcie_0_pipe_clk", &gcc.mux, 0xF9 }, + { "gcc_pcie_0_slv_axi_clk", &gcc.mux, 0xF5 }, + { "gcc_pcie_0_slv_q2a_axi_clk", &gcc.mux, 0xF4 }, + { "gcc_pcie_1_aux_clk", &gcc.mux, 0x101 }, + { "gcc_pcie_1_cfg_ahb_clk", &gcc.mux, 0x100 }, + { "gcc_pcie_1_mstr_axi_clk", &gcc.mux, 0xFF }, + { "gcc_pcie_1_pipe_clk", &gcc.mux, 0x102 }, + { "gcc_pcie_1_slv_axi_clk", &gcc.mux, 0xFE }, + { "gcc_pcie_1_slv_q2a_axi_clk", &gcc.mux, 0xFD }, + { "gcc_pdm2_clk", &gcc.mux, 0x9E }, + { "gcc_pdm_ahb_clk", &gcc.mux, 0x9C }, + { "gcc_pdm_xo4_clk", &gcc.mux, 0x9D }, + { "gcc_qmip_camera_nrt_ahb_clk", &gcc.mux, 0x48 }, + { "gcc_qmip_camera_rt_ahb_clk", &gcc.mux, 0x49 }, + { "gcc_qmip_disp_ahb_clk", &gcc.mux, 0x4F }, + { "gcc_qmip_video_cvp_ahb_clk", &gcc.mux, 0x55 }, + { "gcc_qmip_video_vcodec_ahb_clk", &gcc.mux, 0x56 }, + { "gcc_qupv3_wrap0_core_2x_clk", &gcc.mux, 0x89 }, + { "gcc_qupv3_wrap0_core_clk", &gcc.mux, 0x88 }, + { "gcc_qupv3_wrap0_s0_clk", &gcc.mux, 0x8A }, + { "gcc_qupv3_wrap0_s1_clk", &gcc.mux, 0x8B }, + { "gcc_qupv3_wrap0_s2_clk", &gcc.mux, 0x8C }, + { "gcc_qupv3_wrap0_s3_clk", &gcc.mux, 0x8D }, + { "gcc_qupv3_wrap0_s4_clk", &gcc.mux, 0x8E }, + { "gcc_qupv3_wrap0_s5_clk", &gcc.mux, 0x8F }, + { "gcc_qupv3_wrap0_s6_clk", &gcc.mux, 0x90 }, + { "gcc_qupv3_wrap0_s7_clk", &gcc.mux, 0x91 }, + { "gcc_qupv3_wrap1_core_2x_clk", &gcc.mux, 0x95 }, + { "gcc_qupv3_wrap1_core_clk", &gcc.mux, 0x94 }, + { "gcc_qupv3_wrap1_s0_clk", &gcc.mux, 0x96 }, + { "gcc_qupv3_wrap1_s1_clk", &gcc.mux, 0x97 }, + { "gcc_qupv3_wrap1_s2_clk", &gcc.mux, 0x98 }, + { "gcc_qupv3_wrap1_s3_clk", &gcc.mux, 0x99 }, + { "gcc_qupv3_wrap1_s4_clk", &gcc.mux, 0x9A }, + { "gcc_qupv3_wrap2_core_2x_clk", &gcc.mux, 0x16E }, + { "gcc_qupv3_wrap2_core_clk", &gcc.mux, 0x16D }, + { "gcc_qupv3_wrap2_s0_clk", &gcc.mux, 0x16F }, + { "gcc_qupv3_wrap2_s1_clk", &gcc.mux, 0x170 }, + { "gcc_qupv3_wrap2_s2_clk", &gcc.mux, 0x171 }, + { "gcc_qupv3_wrap2_s3_clk", &gcc.mux, 0x172 }, + { "gcc_qupv3_wrap2_s4_clk", &gcc.mux, 0x173 }, + { "gcc_qupv3_wrap2_s5_clk", &gcc.mux, 0x174 }, + { "gcc_qupv3_wrap_0_m_ahb_clk", &gcc.mux, 0x86 }, + { "gcc_qupv3_wrap_0_s_ahb_clk", &gcc.mux, 0x87 }, + { "gcc_qupv3_wrap_2_m_ahb_clk", &gcc.mux, 0x16B }, + { "gcc_qupv3_wrap_2_s_ahb_clk", &gcc.mux, 0x16C }, + { "gcc_sdcc2_ahb_clk", &gcc.mux, 0x83 }, + { "gcc_sdcc2_apps_clk", &gcc.mux, 0x82 }, + { "gcc_sdcc4_ahb_clk", &gcc.mux, 0x85 }, + { "gcc_sdcc4_apps_clk", &gcc.mux, 0x84 }, + { "gcc_throttle_pcie_ahb_clk", &gcc.mux, 0x40 }, + { "gcc_ufs_card_ahb_clk", &gcc.mux, 0x107 }, + { "gcc_ufs_card_axi_clk", &gcc.mux, 0x106 }, + { "gcc_ufs_card_ice_core_clk", &gcc.mux, 0x10D }, + { "gcc_ufs_card_phy_aux_clk", &gcc.mux, 0x10E }, + { "gcc_ufs_card_rx_symbol_0_clk", &gcc.mux, 0x109 }, + { "gcc_ufs_card_rx_symbol_1_clk", &gcc.mux, 0x10F }, + { "gcc_ufs_card_tx_symbol_0_clk", &gcc.mux, 0x108 }, + { "gcc_ufs_card_unipro_core_clk", &gcc.mux, 0x10C }, + { "gcc_ufs_phy_ahb_clk", &gcc.mux, 0x113 }, + { "gcc_ufs_phy_axi_clk", &gcc.mux, 0x112 }, + { "gcc_ufs_phy_ice_core_clk", &gcc.mux, 0x119 }, + { "gcc_ufs_phy_phy_aux_clk", &gcc.mux, 0x11A }, + { "gcc_ufs_phy_rx_symbol_0_clk", &gcc.mux, 0x115 }, + { "gcc_ufs_phy_rx_symbol_1_clk", &gcc.mux, 0x11B }, + { "gcc_ufs_phy_tx_symbol_0_clk", &gcc.mux, 0x114 }, + { "gcc_ufs_phy_unipro_core_clk", &gcc.mux, 0x118 }, + { "gcc_usb30_prim_master_clk", &gcc.mux, 0x6D }, + { "gcc_usb30_prim_mock_utmi_clk", &gcc.mux, 0x6F }, + { "gcc_usb30_prim_sleep_clk", &gcc.mux, 0x6E }, + { "gcc_usb30_sec_master_clk", &gcc.mux, 0x76 }, + { "gcc_usb30_sec_mock_utmi_clk", &gcc.mux, 0x78 }, + { "gcc_usb30_sec_sleep_clk", &gcc.mux, 0x77 }, + { "gcc_usb3_prim_phy_aux_clk", &gcc.mux, 0x70 }, + { "gcc_usb3_prim_phy_com_aux_clk", &gcc.mux, 0x71 }, + { "gcc_usb3_prim_phy_pipe_clk", &gcc.mux, 0x72 }, + { "gcc_usb3_sec_phy_aux_clk", &gcc.mux, 0x79 }, + { "gcc_usb3_sec_phy_com_aux_clk", &gcc.mux, 0x7A }, + { "gcc_usb3_sec_phy_pipe_clk", &gcc.mux, 0x7B }, + { "gcc_video_ahb_clk", &gcc.mux, 0x54 }, + { "gcc_video_axi0_clk", &gcc.mux, 0x57 }, + { "gcc_video_axi1_clk", &gcc.mux, 0x58 }, + { "gcc_video_xo_clk", &gcc.mux, 0x59 }, + { "gpu_cc_debug_mux", &gcc.mux, 0x153 }, + { "measure_only_cnoc_clk", &gcc.mux, 0x18 }, + { "measure_only_ipa_2x_clk", &gcc.mux, 0x140 }, + { "measure_only_memnoc_clk", &gcc.mux, 0xCF }, + { "measure_only_snoc_clk", &gcc.mux, 0x9 }, + { "pcie_0_pipe_clk", &gcc.mux, 0xFB }, + { "pcie_1_pipe_clk", &gcc.mux, 0x104 }, + { "ufs_card_rx_symbol_0_clk", &gcc.mux, 0x10B }, + { "ufs_card_rx_symbol_1_clk", &gcc.mux, 0x110 }, + { "ufs_card_tx_symbol_0_clk", &gcc.mux, 0x10A }, + { "ufs_phy_rx_symbol_0_clk", &gcc.mux, 0x117 }, + { "ufs_phy_rx_symbol_1_clk", &gcc.mux, 0x11C }, + { "ufs_phy_tx_symbol_0_clk", &gcc.mux, 0x116 }, + { "usb3_phy_wrapper_gcc_usb30_pipe_clk", &gcc.mux, 0x7C }, + { "usb3_uni_phy_sec_gcc_usb30_pipe_clk", &gcc.mux, 0x7D }, + { "mc_cc_debug_mux", &gcc.mux, 0xD3 }, /* gpu_cc_debug_mux is 0x153 */ - { "gpu_cc_ahb_clk", &gcc, 0x153, &gpu_cc, 0x12 }, - { "gpu_cc_cb_clk", &gcc, 0x153, &gpu_cc, 0x26 }, - { "gpu_cc_crc_ahb_clk", &gcc, 0x153, &gpu_cc, 0x13 }, - { "gpu_cc_cx_apb_clk", &gcc, 0x153, &gpu_cc, 0x16 }, - { "gpu_cc_cx_gmu_clk", &gcc, 0x153, &gpu_cc, 0x1A }, - { "gpu_cc_cx_qdss_at_clk", &gcc, 0x153, &gpu_cc, 0x14 }, - { "gpu_cc_cx_qdss_trig_clk", &gcc, 0x153, &gpu_cc, 0x19 }, - { "gpu_cc_cx_qdss_tsctr_clk", &gcc, 0x153, &gpu_cc, 0x15 }, - { "gpu_cc_cx_snoc_dvm_clk", &gcc, 0x153, &gpu_cc, 0x17 }, - { "gpu_cc_cxo_aon_clk", &gcc, 0x153, &gpu_cc, 0xB }, - { "gpu_cc_cxo_clk", &gcc, 0x153, &gpu_cc, 0x1B }, - { "gpu_cc_freq_measure_clk", &gcc, 0x153, &gpu_cc, 0xC }, - { "gpu_cc_gx_gmu_clk", &gcc, 0x153, &gpu_cc, 0x11 }, - { "gpu_cc_gx_qdss_tsctr_clk", &gcc, 0x153, &gpu_cc, 0xF }, - { "gpu_cc_gx_vsense_clk", &gcc, 0x153, &gpu_cc, 0xE }, - { "gpu_cc_hub_aon_clk", &gcc, 0x153, &gpu_cc, 0x27 }, - { "gpu_cc_hub_cx_int_clk", &gcc, 0x153, &gpu_cc, 0x1C }, - { "gpu_cc_mnd1x_0_gfx3d_clk", &gcc, 0x153, &gpu_cc, 0x21 }, - { "gpu_cc_mnd1x_1_gfx3d_clk", &gcc, 0x153, &gpu_cc, 0x22 }, - { "gpu_cc_sleep_clk", &gcc, 0x153, &gpu_cc, 0x18 }, - { "measure_only_gpu_cc_cx_gfx3d_clk", &gcc, 0x153, &gpu_cc, 0x1D }, - { "measure_only_gpu_cc_cx_gfx3d_slv_clk", &gcc, 0x153, &gpu_cc, 0x1E }, - { "measure_only_gpu_cc_gx_gfx3d_clk", &gcc, 0x153, &gpu_cc, 0xD }, + { "gpu_cc_ahb_clk", &gpu_cc, 0x12 }, + { "gpu_cc_cb_clk", &gpu_cc, 0x26 }, + { "gpu_cc_crc_ahb_clk", &gpu_cc, 0x13 }, + { "gpu_cc_cx_apb_clk", &gpu_cc, 0x16 }, + { "gpu_cc_cx_gmu_clk", &gpu_cc, 0x1A }, + { "gpu_cc_cx_qdss_at_clk", &gpu_cc, 0x14 }, + { "gpu_cc_cx_qdss_trig_clk", &gpu_cc, 0x19 }, + { "gpu_cc_cx_qdss_tsctr_clk", &gpu_cc, 0x15 }, + { "gpu_cc_cx_snoc_dvm_clk", &gpu_cc, 0x17 }, + { "gpu_cc_cxo_aon_clk", &gpu_cc, 0xB }, + { "gpu_cc_cxo_clk", &gpu_cc, 0x1B }, + { "gpu_cc_freq_measure_clk", &gpu_cc, 0xC }, + { "gpu_cc_gx_gmu_clk", &gpu_cc, 0x11 }, + { "gpu_cc_gx_qdss_tsctr_clk", &gpu_cc, 0xF }, + { "gpu_cc_gx_vsense_clk", &gpu_cc, 0xE }, + { "gpu_cc_hub_aon_clk", &gpu_cc, 0x27 }, + { "gpu_cc_hub_cx_int_clk", &gpu_cc, 0x1C }, + { "gpu_cc_mnd1x_0_gfx3d_clk", &gpu_cc, 0x21 }, + { "gpu_cc_mnd1x_1_gfx3d_clk", &gpu_cc, 0x22 }, + { "gpu_cc_sleep_clk", &gpu_cc, 0x18 }, + { "measure_only_gpu_cc_cx_gfx3d_clk", &gpu_cc, 0x1D }, + { "measure_only_gpu_cc_cx_gfx3d_slv_clk", &gpu_cc, 0x1E }, + { "measure_only_gpu_cc_gx_gfx3d_clk", &gpu_cc, 0xD }, /* video_cc_debug_mux is 0x5A */ - { "video_cc_mvs0_clk", &gcc, 0x5A, &video_cc, 0x3 }, - { "video_cc_mvs0c_clk", &gcc, 0x5A, &video_cc, 0x1 }, - { "video_cc_mvs1_clk", &gcc, 0x5A, &video_cc, 0x5 }, - { "video_cc_mvs1_div2_clk", &gcc, 0x5A, &video_cc, 0x8 }, - { "video_cc_mvs1c_clk", &gcc, 0x5A, &video_cc, 0x9 }, - { "video_cc_sleep_clk", &gcc, 0x5A, &video_cc, 0xC }, + { "video_cc_mvs0_clk", &video_cc, 0x3 }, + { "video_cc_mvs0c_clk", &video_cc, 0x1 }, + { "video_cc_mvs1_clk", &video_cc, 0x5 }, + { "video_cc_mvs1_div2_clk", &video_cc, 0x8 }, + { "video_cc_mvs1c_clk", &video_cc, 0x9 }, + { "video_cc_sleep_clk", &video_cc, 0xC }, {} }; diff --git a/sm8450.c b/sm8450.c index a04de12..7d40328 100644 --- a/sm8450.c +++ b/sm8450.c @@ -42,19 +42,23 @@ /* Enabling APSS can cause Bus error issues, so do not enable them by default */ #define ENABLE_SM8450_APSS_CLOCKS 0 -static struct debug_mux gcc = { - .phys = 0x100000, - .size = 0x1f0000, +static struct gcc_mux gcc = { + .mux = { + .phys = 0x100000, + .size = 0x1f0000, - .enable_reg = 0x72008, - .enable_mask = BIT(0), + .measure = measure_gcc, - .mux_reg = 0x72000, - .mux_mask = 0x3ff, + .enable_reg = 0x72008, + .enable_mask = BIT(0), - .div_reg = 0x72004, - .div_mask = 0xf, - .div_val = 2, + .mux_reg = 0x72000, + .mux_mask = 0x3ff, + + .div_reg = 0x72004, + .div_mask = 0xf, + .div_val = 2, + }, .xo_div4_reg = 0x7200c, .debug_ctl_reg = 0x72038, @@ -66,6 +70,10 @@ static struct debug_mux apss_cc = { .phys = 0x17a80000, .size = 0x21000, + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x117, + .enable_reg = 0x20108, .enable_mask = BIT(0), @@ -84,6 +92,10 @@ static struct debug_mux cam_cc = { .size = 0x20000, .block_name = "cam", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x6b, + .enable_reg = 0x14008, .enable_mask = BIT(0), @@ -100,6 +112,10 @@ static struct debug_mux disp_cc = { .size = 0x20000, .block_name = "disp", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x71, + .enable_reg = 0xd00c, .enable_mask = BIT(0), @@ -116,6 +132,10 @@ static struct debug_mux gpu_cc = { .size = 0xa000, .block_name = "gpu", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x16e, + .enable_reg = 0x9274, .enable_mask = BIT(0), @@ -132,6 +152,10 @@ static struct debug_mux video_cc = { .size = 0x10000, .block_name = "video", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x7a, + .enable_reg = 0x80ec, .enable_mask = BIT(0), @@ -143,311 +167,289 @@ static struct debug_mux video_cc = { .div_val = 3, }; -/* -struct measure_clk { - char *name; - struct debug_mux *primary; - int mux; - int post_div; - - struct debug_mux *leaf; - int leaf_mux; - int leaf_div; - - unsigned int fixed_div; -}; -*/ - static struct measure_clk sm8450_clocks[] = { #if ENABLE_SM8450_APSS_CLOCKS -/* apss_cc_debug_mux is 0x117 */ - { "measure_only_apcs_gold_post_acd_clk", &gcc, 0x117, &apss_cc, 0x4, 8 }, - { "measure_only_apcs_goldplus_post_acd_clk", &gcc, 0x117, &apss_cc, 0x8, 8 }, - { "measure_only_apcs_l3_post_acd_clk", &gcc, 0x117, &apss_cc, 0x6, 4 }, - { "measure_only_apcs_silver_post_acd_clk", &gcc, 0x117, &apss_cc, 0x2, 4 }, + { "measure_only_apcs_gold_post_acd_clk", &apss_cc, 0x4, 8 }, + { "measure_only_apcs_goldplus_post_acd_clk", &apss_cc, 0x8, 8 }, + { "measure_only_apcs_l3_post_acd_clk", &apss_cc, 0x6, 4 }, + { "measure_only_apcs_silver_post_acd_clk", &apss_cc, 0x2, 4 }, #endif -/* cam_cc_debug_mux is 0x6b */ - { "cam_cc_bps_ahb_clk", &gcc, 0x6b, &cam_cc, 0x17 }, - { "cam_cc_bps_clk", &gcc, 0x6b, &cam_cc, 0x18 }, - { "cam_cc_bps_fast_ahb_clk", &gcc, 0x6b, &cam_cc, 0x16 }, - { "cam_cc_camnoc_axi_clk", &gcc, 0x6b, &cam_cc, 0x49 }, - { "cam_cc_camnoc_dcd_xo_clk", &gcc, 0x6b, &cam_cc, 0x4A }, - { "cam_cc_cci_0_clk", &gcc, 0x6b, &cam_cc, 0x44 }, - { "cam_cc_cci_1_clk", &gcc, 0x6b, &cam_cc, 0x45 }, - { "cam_cc_core_ahb_clk", &gcc, 0x6b, &cam_cc, 0x4D }, - { "cam_cc_cpas_ahb_clk", &gcc, 0x6b, &cam_cc, 0x46 }, - { "cam_cc_cpas_bps_clk", &gcc, 0x6b, &cam_cc, 0x19 }, - { "cam_cc_cpas_fast_ahb_clk", &gcc, 0x6b, &cam_cc, 0x47 }, - { "cam_cc_cpas_ife_0_clk", &gcc, 0x6b, &cam_cc, 0x25 }, - { "cam_cc_cpas_ife_1_clk", &gcc, 0x6b, &cam_cc, 0x2A }, - { "cam_cc_cpas_ife_2_clk", &gcc, 0x6b, &cam_cc, 0x2F }, - { "cam_cc_cpas_ife_lite_clk", &gcc, 0x6b, &cam_cc, 0x34 }, - { "cam_cc_cpas_ipe_nps_clk", &gcc, 0x6b, &cam_cc, 0x1B }, - { "cam_cc_cpas_sbi_clk", &gcc, 0x6b, &cam_cc, 0x22 }, - { "cam_cc_cpas_sfe_0_clk", &gcc, 0x6b, &cam_cc, 0x39 }, - { "cam_cc_cpas_sfe_1_clk", &gcc, 0x6b, &cam_cc, 0x3D }, - { "cam_cc_csi0phytimer_clk", &gcc, 0x6b, &cam_cc, 0x9 }, - { "cam_cc_csi1phytimer_clk", &gcc, 0x6b, &cam_cc, 0xC }, - { "cam_cc_csi2phytimer_clk", &gcc, 0x6b, &cam_cc, 0xE }, - { "cam_cc_csi3phytimer_clk", &gcc, 0x6b, &cam_cc, 0x10 }, - { "cam_cc_csi4phytimer_clk", &gcc, 0x6b, &cam_cc, 0x12 }, - { "cam_cc_csi5phytimer_clk", &gcc, 0x6b, &cam_cc, 0x14 }, - { "cam_cc_csid_clk", &gcc, 0x6b, &cam_cc, 0x48 }, - { "cam_cc_csid_csiphy_rx_clk", &gcc, 0x6b, &cam_cc, 0xB }, - { "cam_cc_csiphy0_clk", &gcc, 0x6b, &cam_cc, 0xA }, - { "cam_cc_csiphy1_clk", &gcc, 0x6b, &cam_cc, 0xD }, - { "cam_cc_csiphy2_clk", &gcc, 0x6b, &cam_cc, 0xF }, - { "cam_cc_csiphy3_clk", &gcc, 0x6b, &cam_cc, 0x11 }, - { "cam_cc_csiphy4_clk", &gcc, 0x6b, &cam_cc, 0x13 }, - { "cam_cc_csiphy5_clk", &gcc, 0x6b, &cam_cc, 0x15 }, - { "cam_cc_gdsc_clk", &gcc, 0x6b, &cam_cc, 0x4E }, - { "cam_cc_icp_ahb_clk", &gcc, 0x6b, &cam_cc, 0x43 }, - { "cam_cc_icp_clk", &gcc, 0x6b, &cam_cc, 0x42 }, - { "cam_cc_ife_0_clk", &gcc, 0x6b, &cam_cc, 0x24 }, - { "cam_cc_ife_0_dsp_clk", &gcc, 0x6b, &cam_cc, 0x26 }, - { "cam_cc_ife_0_fast_ahb_clk", &gcc, 0x6b, &cam_cc, 0x28 }, - { "cam_cc_ife_1_clk", &gcc, 0x6b, &cam_cc, 0x29 }, - { "cam_cc_ife_1_dsp_clk", &gcc, 0x6b, &cam_cc, 0x2B }, - { "cam_cc_ife_1_fast_ahb_clk", &gcc, 0x6b, &cam_cc, 0x2D }, - { "cam_cc_ife_2_clk", &gcc, 0x6b, &cam_cc, 0x2E }, - { "cam_cc_ife_2_dsp_clk", &gcc, 0x6b, &cam_cc, 0x30 }, - { "cam_cc_ife_2_fast_ahb_clk", &gcc, 0x6b, &cam_cc, 0x32 }, - { "cam_cc_ife_lite_ahb_clk", &gcc, 0x6b, &cam_cc, 0x37 }, - { "cam_cc_ife_lite_clk", &gcc, 0x6b, &cam_cc, 0x33 }, - { "cam_cc_ife_lite_cphy_rx_clk", &gcc, 0x6b, &cam_cc, 0x36 }, - { "cam_cc_ife_lite_csid_clk", &gcc, 0x6b, &cam_cc, 0x35 }, - { "cam_cc_ipe_nps_ahb_clk", &gcc, 0x6b, &cam_cc, 0x1E }, - { "cam_cc_ipe_nps_clk", &gcc, 0x6b, &cam_cc, 0x1A }, - { "cam_cc_ipe_nps_fast_ahb_clk", &gcc, 0x6b, &cam_cc, 0x1F }, - { "cam_cc_ipe_pps_clk", &gcc, 0x6b, &cam_cc, 0x1C }, - { "cam_cc_ipe_pps_fast_ahb_clk", &gcc, 0x6b, &cam_cc, 0x20 }, - { "cam_cc_jpeg_clk", &gcc, 0x6b, &cam_cc, 0x40 }, - { "cam_cc_mclk0_clk", &gcc, 0x6b, &cam_cc, 0x1 }, - { "cam_cc_mclk1_clk", &gcc, 0x6b, &cam_cc, 0x2 }, - { "cam_cc_mclk2_clk", &gcc, 0x6b, &cam_cc, 0x3 }, - { "cam_cc_mclk3_clk", &gcc, 0x6b, &cam_cc, 0x4 }, - { "cam_cc_mclk4_clk", &gcc, 0x6b, &cam_cc, 0x5 }, - { "cam_cc_mclk5_clk", &gcc, 0x6b, &cam_cc, 0x6 }, - { "cam_cc_mclk6_clk", &gcc, 0x6b, &cam_cc, 0x7 }, - { "cam_cc_mclk7_clk", &gcc, 0x6b, &cam_cc, 0x8 }, - { "cam_cc_qdss_debug_clk", &gcc, 0x6b, &cam_cc, 0x4B }, - { "cam_cc_qdss_debug_xo_clk", &gcc, 0x6b, &cam_cc, 0x4C }, - { "cam_cc_sbi_ahb_clk", &gcc, 0x6b, &cam_cc, 0x23 }, - { "cam_cc_sbi_clk", &gcc, 0x6b, &cam_cc, 0x21 }, - { "cam_cc_sfe_0_clk", &gcc, 0x6b, &cam_cc, 0x38 }, - { "cam_cc_sfe_0_fast_ahb_clk", &gcc, 0x6b, &cam_cc, 0x3B }, - { "cam_cc_sfe_1_clk", &gcc, 0x6b, &cam_cc, 0x3C }, - { "cam_cc_sfe_1_fast_ahb_clk", &gcc, 0x6b, &cam_cc, 0x3F }, - { "cam_cc_sleep_clk", &gcc, 0x6b, &cam_cc, 0x4F }, -/* disp_cc_debug_mux is 0x71 */ - { "disp_cc_mdss_ahb1_clk", &gcc, 0x71, &disp_cc, 0x39 }, - { "disp_cc_mdss_ahb_clk", &gcc, 0x71, &disp_cc, 0x34 }, - { "disp_cc_mdss_byte0_clk", &gcc, 0x71, &disp_cc, 0x15 }, - { "disp_cc_mdss_byte0_intf_clk", &gcc, 0x71, &disp_cc, 0x16 }, - { "disp_cc_mdss_byte1_clk", &gcc, 0x71, &disp_cc, 0x17 }, - { "disp_cc_mdss_byte1_intf_clk", &gcc, 0x71, &disp_cc, 0x18 }, - { "disp_cc_mdss_dptx0_aux_clk", &gcc, 0x71, &disp_cc, 0x21 }, - { "disp_cc_mdss_dptx0_crypto_clk", &gcc, 0x71, &disp_cc, 0x1E }, - { "disp_cc_mdss_dptx0_link_clk", &gcc, 0x71, &disp_cc, 0x1B }, - { "disp_cc_mdss_dptx0_link_intf_clk", &gcc, 0x71, &disp_cc, 0x1D }, - { "disp_cc_mdss_dptx0_pixel0_clk", &gcc, 0x71, &disp_cc, 0x1F }, - { "disp_cc_mdss_dptx0_pixel1_clk", &gcc, 0x71, &disp_cc, 0x20 }, - { "disp_cc_mdss_dptx0_usb_router_link_intf_clk", &gcc, 0x71, &disp_cc, 0x1C }, - { "disp_cc_mdss_dptx1_aux_clk", &gcc, 0x71, &disp_cc, 0x28 }, - { "disp_cc_mdss_dptx1_crypto_clk", &gcc, 0x71, &disp_cc, 0x27 }, - { "disp_cc_mdss_dptx1_link_clk", &gcc, 0x71, &disp_cc, 0x24 }, - { "disp_cc_mdss_dptx1_link_intf_clk", &gcc, 0x71, &disp_cc, 0x26 }, - { "disp_cc_mdss_dptx1_pixel0_clk", &gcc, 0x71, &disp_cc, 0x22 }, - { "disp_cc_mdss_dptx1_pixel1_clk", &gcc, 0x71, &disp_cc, 0x23 }, - { "disp_cc_mdss_dptx1_usb_router_link_intf_clk", &gcc, 0x71, &disp_cc, 0x25 }, - { "disp_cc_mdss_dptx2_aux_clk", &gcc, 0x71, &disp_cc, 0x2E }, - { "disp_cc_mdss_dptx2_crypto_clk", &gcc, 0x71, &disp_cc, 0x2D }, - { "disp_cc_mdss_dptx2_link_clk", &gcc, 0x71, &disp_cc, 0x2B }, - { "disp_cc_mdss_dptx2_link_intf_clk", &gcc, 0x71, &disp_cc, 0x2C }, - { "disp_cc_mdss_dptx2_pixel0_clk", &gcc, 0x71, &disp_cc, 0x29 }, - { "disp_cc_mdss_dptx2_pixel1_clk", &gcc, 0x71, &disp_cc, 0x2A }, - { "disp_cc_mdss_dptx3_aux_clk", &gcc, 0x71, &disp_cc, 0x32 }, - { "disp_cc_mdss_dptx3_crypto_clk", &gcc, 0x71, &disp_cc, 0x33 }, - { "disp_cc_mdss_dptx3_link_clk", &gcc, 0x71, &disp_cc, 0x30 }, - { "disp_cc_mdss_dptx3_link_intf_clk", &gcc, 0x71, &disp_cc, 0x31 }, - { "disp_cc_mdss_dptx3_pixel0_clk", &gcc, 0x71, &disp_cc, 0x2F }, - { "disp_cc_mdss_esc0_clk", &gcc, 0x71, &disp_cc, 0x19 }, - { "disp_cc_mdss_esc1_clk", &gcc, 0x71, &disp_cc, 0x1A }, - { "disp_cc_mdss_mdp1_clk", &gcc, 0x71, &disp_cc, 0x35 }, - { "disp_cc_mdss_mdp_clk", &gcc, 0x71, &disp_cc, 0x11 }, - { "disp_cc_mdss_mdp_lut1_clk", &gcc, 0x71, &disp_cc, 0x37 }, - { "disp_cc_mdss_mdp_lut_clk", &gcc, 0x71, &disp_cc, 0x13 }, - { "disp_cc_mdss_non_gdsc_ahb_clk", &gcc, 0x71, &disp_cc, 0x3A }, - { "disp_cc_mdss_pclk0_clk", &gcc, 0x71, &disp_cc, 0xF }, - { "disp_cc_mdss_pclk1_clk", &gcc, 0x71, &disp_cc, 0x10 }, - { "disp_cc_mdss_rot1_clk", &gcc, 0x71, &disp_cc, 0x36 }, - { "disp_cc_mdss_rot_clk", &gcc, 0x71, &disp_cc, 0x12 }, - { "disp_cc_mdss_rscc_ahb_clk", &gcc, 0x71, &disp_cc, 0x3C }, - { "disp_cc_mdss_rscc_vsync_clk", &gcc, 0x71, &disp_cc, 0x3B }, - { "disp_cc_mdss_vsync1_clk", &gcc, 0x71, &disp_cc, 0x38 }, - { "disp_cc_mdss_vsync_clk", &gcc, 0x71, &disp_cc, 0x14 }, - { "disp_cc_sleep_clk", &gcc, 0x71, &disp_cc, 0x45 }, - { "disp_cc_xo_clk", &gcc, 0x71, &disp_cc, 0x44 }, -// gcc - //{ "apss_cc_debug_mux", &gcc, 0x117 }, - //{ "cam_cc_debug_mux", &gcc, 0x6B }, - //{ "disp_cc_debug_mux", &gcc, 0x71 }, - { "gcc_aggre_noc_pcie_0_axi_clk", &gcc, 0x3D }, - { "gcc_aggre_noc_pcie_1_axi_clk", &gcc, 0x3E }, - { "gcc_aggre_ufs_phy_axi_clk", &gcc, 0x40 }, - { "gcc_aggre_usb3_prim_axi_clk", &gcc, 0x3F }, - { "gcc_boot_rom_ahb_clk", &gcc, 0xD9 }, - { "gcc_camera_ahb_clk", &gcc, 0x63 }, - { "gcc_camera_hf_axi_clk", &gcc, 0x66 }, - { "gcc_camera_sf_axi_clk", &gcc, 0x68 }, - { "gcc_camera_xo_clk", &gcc, 0x6A }, - { "gcc_cfg_noc_pcie_anoc_ahb_clk", &gcc, 0x2D }, - { "gcc_cfg_noc_usb3_prim_axi_clk", &gcc, 0x20 }, - { "gcc_ddrss_gpu_axi_clk", &gcc, 0xF5 }, - { "gcc_ddrss_pcie_sf_tbu_clk", &gcc, 0xF6 }, - { "gcc_disp_ahb_clk", &gcc, 0x6C }, - { "gcc_disp_hf_axi_clk", &gcc, 0x6E }, - { "gcc_disp_sf_axi_clk", &gcc, 0x6F }, - { "gcc_disp_xo_clk", &gcc, 0x70 }, - { "gcc_gp1_clk", &gcc, 0x122 }, - { "gcc_gp2_clk", &gcc, 0x123 }, - { "gcc_gp3_clk", &gcc, 0x124 }, - { "gcc_gpu_cfg_ahb_clk", &gcc, 0x16B }, - { "gcc_gpu_gpll0_clk_src", &gcc, 0x172 }, - { "gcc_gpu_gpll0_div_clk_src", &gcc, 0x173 }, - { "gcc_gpu_memnoc_gfx_clk", &gcc, 0x16F }, - { "gcc_gpu_snoc_dvm_gfx_clk", &gcc, 0x171 }, - { "gcc_pcie_0_aux_clk", &gcc, 0x12A }, - { "gcc_pcie_0_cfg_ahb_clk", &gcc, 0x129 }, - { "gcc_pcie_0_mstr_axi_clk", &gcc, 0x128 }, - { "gcc_pcie_0_phy_rchng_clk", &gcc, 0x12C }, - { "gcc_pcie_0_pipe_clk", &gcc, 0x12B }, - { "gcc_pcie_0_slv_axi_clk", &gcc, 0x127 }, - { "gcc_pcie_0_slv_q2a_axi_clk", &gcc, 0x126 }, - { "gcc_pcie_1_aux_clk", &gcc, 0x133 }, - { "gcc_pcie_1_cfg_ahb_clk", &gcc, 0x132 }, - { "gcc_pcie_1_mstr_axi_clk", &gcc, 0x131 }, - { "gcc_pcie_1_phy_aux_clk", &gcc, 0x134 }, - { "gcc_pcie_1_phy_rchng_clk", &gcc, 0x136 }, - { "gcc_pcie_1_pipe_clk", &gcc, 0x135 }, - { "gcc_pcie_1_slv_axi_clk", &gcc, 0x130 }, - { "gcc_pcie_1_slv_q2a_axi_clk", &gcc, 0x12F }, - { "gcc_pdm2_clk", &gcc, 0xCB }, - { "gcc_pdm_ahb_clk", &gcc, 0xC9 }, - { "gcc_pdm_xo4_clk", &gcc, 0xCA }, - { "gcc_qmip_camera_nrt_ahb_clk", &gcc, 0x64 }, - { "gcc_qmip_camera_rt_ahb_clk", &gcc, 0x65 }, - { "gcc_qmip_disp_ahb_clk", &gcc, 0x6D }, - { "gcc_qmip_gpu_ahb_clk", &gcc, 0x16C }, - { "gcc_qmip_pcie_ahb_clk", &gcc, 0x125 }, - { "gcc_qmip_video_cv_cpu_ahb_clk", &gcc, 0x76 }, - { "gcc_qmip_video_cvp_ahb_clk", &gcc, 0x73 }, - { "gcc_qmip_video_v_cpu_ahb_clk", &gcc, 0x75 }, - { "gcc_qmip_video_vcodec_ahb_clk", &gcc, 0x74 }, - { "gcc_qupv3_wrap0_core_2x_clk", &gcc, 0xAA }, - { "gcc_qupv3_wrap0_core_clk", &gcc, 0xA9 }, - { "gcc_qupv3_wrap0_s0_clk", &gcc, 0xAB }, - { "gcc_qupv3_wrap0_s1_clk", &gcc, 0xAC }, - { "gcc_qupv3_wrap0_s2_clk", &gcc, 0xAD }, - { "gcc_qupv3_wrap0_s3_clk", &gcc, 0xAE }, - { "gcc_qupv3_wrap0_s4_clk", &gcc, 0xAF }, - { "gcc_qupv3_wrap0_s5_clk", &gcc, 0xB0 }, - { "gcc_qupv3_wrap0_s6_clk", &gcc, 0xB1 }, - { "gcc_qupv3_wrap0_s7_clk", &gcc, 0xB2 }, - { "gcc_qupv3_wrap1_core_2x_clk", &gcc, 0xB6 }, - { "gcc_qupv3_wrap1_core_clk", &gcc, 0xB5 }, - { "gcc_qupv3_wrap1_s0_clk", &gcc, 0xB7 }, - { "gcc_qupv3_wrap1_s1_clk", &gcc, 0xB8 }, - { "gcc_qupv3_wrap1_s2_clk", &gcc, 0xB9 }, - { "gcc_qupv3_wrap1_s3_clk", &gcc, 0xBA }, - { "gcc_qupv3_wrap1_s4_clk", &gcc, 0xBB }, - { "gcc_qupv3_wrap1_s5_clk", &gcc, 0xBC }, - { "gcc_qupv3_wrap1_s6_clk", &gcc, 0xBD }, - { "gcc_qupv3_wrap2_core_2x_clk", &gcc, 0xC1 }, - { "gcc_qupv3_wrap2_core_clk", &gcc, 0xC0 }, - { "gcc_qupv3_wrap2_s0_clk", &gcc, 0xC2 }, - { "gcc_qupv3_wrap2_s1_clk", &gcc, 0xC3 }, - { "gcc_qupv3_wrap2_s2_clk", &gcc, 0xC4 }, - { "gcc_qupv3_wrap2_s3_clk", &gcc, 0xC5 }, - { "gcc_qupv3_wrap2_s4_clk", &gcc, 0xC6 }, - { "gcc_qupv3_wrap2_s5_clk", &gcc, 0xC7 }, - { "gcc_qupv3_wrap2_s6_clk", &gcc, 0xC8 }, - { "gcc_qupv3_wrap_0_m_ahb_clk", &gcc, 0xA7 }, - { "gcc_qupv3_wrap_0_s_ahb_clk", &gcc, 0xA8 }, - { "gcc_qupv3_wrap_1_m_ahb_clk", &gcc, 0xB3 }, - { "gcc_qupv3_wrap_1_s_ahb_clk", &gcc, 0xB4 }, - { "gcc_qupv3_wrap_2_m_ahb_clk", &gcc, 0xBE }, - { "gcc_qupv3_wrap_2_s_ahb_clk", &gcc, 0xBF }, - { "gcc_sdcc2_ahb_clk", &gcc, 0xA2 }, - { "gcc_sdcc2_apps_clk", &gcc, 0xA1 }, - { "gcc_sdcc2_at_clk", &gcc, 0xA3 }, - { "gcc_sdcc4_ahb_clk", &gcc, 0xA5 }, - { "gcc_sdcc4_apps_clk", &gcc, 0xA4 }, - { "gcc_sdcc4_at_clk", &gcc, 0xA6 }, - { "gcc_ufs_phy_ahb_clk", &gcc, 0x13B }, - { "gcc_ufs_phy_axi_clk", &gcc, 0x13A }, - { "gcc_ufs_phy_ice_core_clk", &gcc, 0x141 }, - { "gcc_ufs_phy_phy_aux_clk", &gcc, 0x142 }, - { "gcc_ufs_phy_rx_symbol_0_clk", &gcc, 0x13D }, - { "gcc_ufs_phy_rx_symbol_1_clk", &gcc, 0x143 }, - { "gcc_ufs_phy_tx_symbol_0_clk", &gcc, 0x13C }, - { "gcc_ufs_phy_unipro_core_clk", &gcc, 0x140 }, - { "gcc_usb30_prim_master_clk", &gcc, 0x94 }, - { "gcc_usb30_prim_mock_utmi_clk", &gcc, 0x96 }, - { "gcc_usb30_prim_sleep_clk", &gcc, 0x95 }, - { "gcc_usb3_prim_phy_aux_clk", &gcc, 0x97 }, - { "gcc_usb3_prim_phy_com_aux_clk", &gcc, 0x98 }, - { "gcc_usb3_prim_phy_pipe_clk", &gcc, 0x99 }, - { "gcc_video_ahb_clk", &gcc, 0x72 }, - { "gcc_video_axi0_clk", &gcc, 0x77 }, - { "gcc_video_axi1_clk", &gcc, 0x78 }, - { "gcc_video_xo_clk", &gcc, 0x79 }, - //{ "gpu_cc_debug_mux", &gcc, 0x16E }, - { "measure_only_cnoc_clk", &gcc, 0x19 }, - { "measure_only_ipa_2x_clk", &gcc, 0x158 }, - { "measure_only_memnoc_clk", &gcc, 0xFB }, - { "measure_only_snoc_clk", &gcc, 0xC }, - { "pcie_0_pipe_clk", &gcc, 0x12D }, - { "pcie_1_phy_aux_clk", &gcc, 0x138 }, - { "pcie_1_pipe_clk", &gcc, 0x137 }, - { "ufs_phy_rx_symbol_0_clk", &gcc, 0x13F }, - { "ufs_phy_rx_symbol_1_clk", &gcc, 0x144 }, - { "ufs_phy_tx_symbol_0_clk", &gcc, 0x13E }, - { "usb3_phy_wrapper_gcc_usb30_pipe_clk", &gcc, 0x9D }, - //{ "video_cc_debug_mux", &gcc, 0x7A }, - { "mc_cc_debug_mux", &gcc, 0x100 }, -/* gpu_cc_debug_mux is 0x16e */ - { "gpu_cc_ahb_clk", &gcc, 0x16e, &gpu_cc, 0x16 }, - { "gpu_cc_crc_ahb_clk", &gcc, 0x16e, &gpu_cc, 0x17 }, - { "gpu_cc_cx_apb_clk", &gcc, 0x16e, &gpu_cc, 0x1A }, - { "gpu_cc_cx_ff_clk", &gcc, 0x16e, &gpu_cc, 0x21 }, - { "gpu_cc_cx_gmu_clk", &gcc, 0x16e, &gpu_cc, 0x1E }, - { "gpu_cc_cx_snoc_dvm_clk", &gcc, 0x16e, &gpu_cc, 0x1B }, - { "gpu_cc_cxo_aon_clk", &gcc, 0x16e, &gpu_cc, 0xB }, - { "gpu_cc_cxo_clk", &gcc, 0x16e, &gpu_cc, 0x1F }, - { "gpu_cc_demet_clk", &gcc, 0x16e, &gpu_cc, 0xD }, - { "gpu_cc_freq_measure_clk", &gcc, 0x16e, &gpu_cc, 0xC }, - { "gpu_cc_gx_ff_clk", &gcc, 0x16e, &gpu_cc, 0x13 }, - { "gpu_cc_gx_gfx3d_rdvm_clk", &gcc, 0x16e, &gpu_cc, 0x15 }, - { "gpu_cc_gx_gmu_clk", &gcc, 0x16e, &gpu_cc, 0x12 }, - { "gpu_cc_gx_vsense_clk", &gcc, 0x16e, &gpu_cc, 0xF }, - { "gpu_cc_hub_aon_clk", &gcc, 0x16e, &gpu_cc, 0x2F }, - { "gpu_cc_hub_cx_int_clk", &gcc, 0x16e, &gpu_cc, 0x20 }, - { "gpu_cc_memnoc_gfx_clk", &gcc, 0x16e, &gpu_cc, 0x22 }, - { "gpu_cc_mnd1x_0_gfx3d_clk", &gcc, 0x16e, &gpu_cc, 0x29 }, - { "gpu_cc_mnd1x_1_gfx3d_clk", &gcc, 0x16e, &gpu_cc, 0x2A }, - { "gpu_cc_sleep_clk", &gcc, 0x16e, &gpu_cc, 0x1C }, - { "measure_only_gpu_cc_cx_gfx3d_clk", &gcc, 0x16e, &gpu_cc, 0x25 }, - { "measure_only_gpu_cc_cx_gfx3d_slv_clk", &gcc, 0x16e, &gpu_cc, 0x26 }, - { "measure_only_gpu_cc_gx_gfx3d_clk", &gcc, 0x16e, &gpu_cc, 0xE }, -/* video_cc_debug_mux is 0x7A */ - { "video_cc_ahb_clk", &gcc, 0x7a, &video_cc, 0x7 }, - { "video_cc_mvs0_clk", &gcc, 0x7a, &video_cc, 0x3 }, - { "video_cc_mvs0c_clk", &gcc, 0x7a, &video_cc, 0x1 }, - { "video_cc_mvs1_clk", &gcc, 0x7a, &video_cc, 0x5 }, - { "video_cc_mvs1c_clk", &gcc, 0x7a, &video_cc, 0x9 }, - { "video_cc_sleep_clk", &gcc, 0x7a, &video_cc, 0xC }, - { "video_cc_xo_clk", &gcc, 0x7a, &video_cc, 0xB }, + { "cam_cc_bps_ahb_clk", &cam_cc, 0x17 }, + { "cam_cc_bps_clk", &cam_cc, 0x18 }, + { "cam_cc_bps_fast_ahb_clk", &cam_cc, 0x16 }, + { "cam_cc_camnoc_axi_clk", &cam_cc, 0x49 }, + { "cam_cc_camnoc_dcd_xo_clk", &cam_cc, 0x4A }, + { "cam_cc_cci_0_clk", &cam_cc, 0x44 }, + { "cam_cc_cci_1_clk", &cam_cc, 0x45 }, + { "cam_cc_core_ahb_clk", &cam_cc, 0x4D }, + { "cam_cc_cpas_ahb_clk", &cam_cc, 0x46 }, + { "cam_cc_cpas_bps_clk", &cam_cc, 0x19 }, + { "cam_cc_cpas_fast_ahb_clk", &cam_cc, 0x47 }, + { "cam_cc_cpas_ife_0_clk", &cam_cc, 0x25 }, + { "cam_cc_cpas_ife_1_clk", &cam_cc, 0x2A }, + { "cam_cc_cpas_ife_2_clk", &cam_cc, 0x2F }, + { "cam_cc_cpas_ife_lite_clk", &cam_cc, 0x34 }, + { "cam_cc_cpas_ipe_nps_clk", &cam_cc, 0x1B }, + { "cam_cc_cpas_sbi_clk", &cam_cc, 0x22 }, + { "cam_cc_cpas_sfe_0_clk", &cam_cc, 0x39 }, + { "cam_cc_cpas_sfe_1_clk", &cam_cc, 0x3D }, + { "cam_cc_csi0phytimer_clk", &cam_cc, 0x9 }, + { "cam_cc_csi1phytimer_clk", &cam_cc, 0xC }, + { "cam_cc_csi2phytimer_clk", &cam_cc, 0xE }, + { "cam_cc_csi3phytimer_clk", &cam_cc, 0x10 }, + { "cam_cc_csi4phytimer_clk", &cam_cc, 0x12 }, + { "cam_cc_csi5phytimer_clk", &cam_cc, 0x14 }, + { "cam_cc_csid_clk", &cam_cc, 0x48 }, + { "cam_cc_csid_csiphy_rx_clk", &cam_cc, 0xB }, + { "cam_cc_csiphy0_clk", &cam_cc, 0xA }, + { "cam_cc_csiphy1_clk", &cam_cc, 0xD }, + { "cam_cc_csiphy2_clk", &cam_cc, 0xF }, + { "cam_cc_csiphy3_clk", &cam_cc, 0x11 }, + { "cam_cc_csiphy4_clk", &cam_cc, 0x13 }, + { "cam_cc_csiphy5_clk", &cam_cc, 0x15 }, + { "cam_cc_gdsc_clk", &cam_cc, 0x4E }, + { "cam_cc_icp_ahb_clk", &cam_cc, 0x43 }, + { "cam_cc_icp_clk", &cam_cc, 0x42 }, + { "cam_cc_ife_0_clk", &cam_cc, 0x24 }, + { "cam_cc_ife_0_dsp_clk", &cam_cc, 0x26 }, + { "cam_cc_ife_0_fast_ahb_clk", &cam_cc, 0x28 }, + { "cam_cc_ife_1_clk", &cam_cc, 0x29 }, + { "cam_cc_ife_1_dsp_clk", &cam_cc, 0x2B }, + { "cam_cc_ife_1_fast_ahb_clk", &cam_cc, 0x2D }, + { "cam_cc_ife_2_clk", &cam_cc, 0x2E }, + { "cam_cc_ife_2_dsp_clk", &cam_cc, 0x30 }, + { "cam_cc_ife_2_fast_ahb_clk", &cam_cc, 0x32 }, + { "cam_cc_ife_lite_ahb_clk", &cam_cc, 0x37 }, + { "cam_cc_ife_lite_clk", &cam_cc, 0x33 }, + { "cam_cc_ife_lite_cphy_rx_clk", &cam_cc, 0x36 }, + { "cam_cc_ife_lite_csid_clk", &cam_cc, 0x35 }, + { "cam_cc_ipe_nps_ahb_clk", &cam_cc, 0x1E }, + { "cam_cc_ipe_nps_clk", &cam_cc, 0x1A }, + { "cam_cc_ipe_nps_fast_ahb_clk", &cam_cc, 0x1F }, + { "cam_cc_ipe_pps_clk", &cam_cc, 0x1C }, + { "cam_cc_ipe_pps_fast_ahb_clk", &cam_cc, 0x20 }, + { "cam_cc_jpeg_clk", &cam_cc, 0x40 }, + { "cam_cc_mclk0_clk", &cam_cc, 0x1 }, + { "cam_cc_mclk1_clk", &cam_cc, 0x2 }, + { "cam_cc_mclk2_clk", &cam_cc, 0x3 }, + { "cam_cc_mclk3_clk", &cam_cc, 0x4 }, + { "cam_cc_mclk4_clk", &cam_cc, 0x5 }, + { "cam_cc_mclk5_clk", &cam_cc, 0x6 }, + { "cam_cc_mclk6_clk", &cam_cc, 0x7 }, + { "cam_cc_mclk7_clk", &cam_cc, 0x8 }, + { "cam_cc_qdss_debug_clk", &cam_cc, 0x4B }, + { "cam_cc_qdss_debug_xo_clk", &cam_cc, 0x4C }, + { "cam_cc_sbi_ahb_clk", &cam_cc, 0x23 }, + { "cam_cc_sbi_clk", &cam_cc, 0x21 }, + { "cam_cc_sfe_0_clk", &cam_cc, 0x38 }, + { "cam_cc_sfe_0_fast_ahb_clk", &cam_cc, 0x3B }, + { "cam_cc_sfe_1_clk", &cam_cc, 0x3C }, + { "cam_cc_sfe_1_fast_ahb_clk", &cam_cc, 0x3F }, + { "cam_cc_sleep_clk", &cam_cc, 0x4F }, + + { "disp_cc_mdss_ahb1_clk", &disp_cc, 0x39 }, + { "disp_cc_mdss_ahb_clk", &disp_cc, 0x34 }, + { "disp_cc_mdss_byte0_clk", &disp_cc, 0x15 }, + { "disp_cc_mdss_byte0_intf_clk", &disp_cc, 0x16 }, + { "disp_cc_mdss_byte1_clk", &disp_cc, 0x17 }, + { "disp_cc_mdss_byte1_intf_clk", &disp_cc, 0x18 }, + { "disp_cc_mdss_dptx0_aux_clk", &disp_cc, 0x21 }, + { "disp_cc_mdss_dptx0_crypto_clk", &disp_cc, 0x1E }, + { "disp_cc_mdss_dptx0_link_clk", &disp_cc, 0x1B }, + { "disp_cc_mdss_dptx0_link_intf_clk", &disp_cc, 0x1D }, + { "disp_cc_mdss_dptx0_pixel0_clk", &disp_cc, 0x1F }, + { "disp_cc_mdss_dptx0_pixel1_clk", &disp_cc, 0x20 }, + { "disp_cc_mdss_dptx0_usb_router_link_intf_clk", &disp_cc, 0x1C }, + { "disp_cc_mdss_dptx1_aux_clk", &disp_cc, 0x28 }, + { "disp_cc_mdss_dptx1_crypto_clk", &disp_cc, 0x27 }, + { "disp_cc_mdss_dptx1_link_clk", &disp_cc, 0x24 }, + { "disp_cc_mdss_dptx1_link_intf_clk", &disp_cc, 0x26 }, + { "disp_cc_mdss_dptx1_pixel0_clk", &disp_cc, 0x22 }, + { "disp_cc_mdss_dptx1_pixel1_clk", &disp_cc, 0x23 }, + { "disp_cc_mdss_dptx1_usb_router_link_intf_clk", &disp_cc, 0x25 }, + { "disp_cc_mdss_dptx2_aux_clk", &disp_cc, 0x2E }, + { "disp_cc_mdss_dptx2_crypto_clk", &disp_cc, 0x2D }, + { "disp_cc_mdss_dptx2_link_clk", &disp_cc, 0x2B }, + { "disp_cc_mdss_dptx2_link_intf_clk", &disp_cc, 0x2C }, + { "disp_cc_mdss_dptx2_pixel0_clk", &disp_cc, 0x29 }, + { "disp_cc_mdss_dptx2_pixel1_clk", &disp_cc, 0x2A }, + { "disp_cc_mdss_dptx3_aux_clk", &disp_cc, 0x32 }, + { "disp_cc_mdss_dptx3_crypto_clk", &disp_cc, 0x33 }, + { "disp_cc_mdss_dptx3_link_clk", &disp_cc, 0x30 }, + { "disp_cc_mdss_dptx3_link_intf_clk", &disp_cc, 0x31 }, + { "disp_cc_mdss_dptx3_pixel0_clk", &disp_cc, 0x2F }, + { "disp_cc_mdss_esc0_clk", &disp_cc, 0x19 }, + { "disp_cc_mdss_esc1_clk", &disp_cc, 0x1A }, + { "disp_cc_mdss_mdp1_clk", &disp_cc, 0x35 }, + { "disp_cc_mdss_mdp_clk", &disp_cc, 0x11 }, + { "disp_cc_mdss_mdp_lut1_clk", &disp_cc, 0x37 }, + { "disp_cc_mdss_mdp_lut_clk", &disp_cc, 0x13 }, + { "disp_cc_mdss_non_gdsc_ahb_clk", &disp_cc, 0x3A }, + { "disp_cc_mdss_pclk0_clk", &disp_cc, 0xF }, + { "disp_cc_mdss_pclk1_clk", &disp_cc, 0x10 }, + { "disp_cc_mdss_rot1_clk", &disp_cc, 0x36 }, + { "disp_cc_mdss_rot_clk", &disp_cc, 0x12 }, + { "disp_cc_mdss_rscc_ahb_clk", &disp_cc, 0x3C }, + { "disp_cc_mdss_rscc_vsync_clk", &disp_cc, 0x3B }, + { "disp_cc_mdss_vsync1_clk", &disp_cc, 0x38 }, + { "disp_cc_mdss_vsync_clk", &disp_cc, 0x14 }, + { "disp_cc_sleep_clk", &disp_cc, 0x45 }, + { "disp_cc_xo_clk", &disp_cc, 0x44 }, + + { "gcc_aggre_noc_pcie_0_axi_clk", &gcc.mux, 0x3D }, + { "gcc_aggre_noc_pcie_1_axi_clk", &gcc.mux, 0x3E }, + { "gcc_aggre_ufs_phy_axi_clk", &gcc.mux, 0x40 }, + { "gcc_aggre_usb3_prim_axi_clk", &gcc.mux, 0x3F }, + { "gcc_boot_rom_ahb_clk", &gcc.mux, 0xD9 }, + { "gcc_camera_ahb_clk", &gcc.mux, 0x63 }, + { "gcc_camera_hf_axi_clk", &gcc.mux, 0x66 }, + { "gcc_camera_sf_axi_clk", &gcc.mux, 0x68 }, + { "gcc_camera_xo_clk", &gcc.mux, 0x6A }, + { "gcc_cfg_noc_pcie_anoc_ahb_clk", &gcc.mux, 0x2D }, + { "gcc_cfg_noc_usb3_prim_axi_clk", &gcc.mux, 0x20 }, + { "gcc_ddrss_gpu_axi_clk", &gcc.mux, 0xF5 }, + { "gcc_ddrss_pcie_sf_tbu_clk", &gcc.mux, 0xF6 }, + { "gcc_disp_ahb_clk", &gcc.mux, 0x6C }, + { "gcc_disp_hf_axi_clk", &gcc.mux, 0x6E }, + { "gcc_disp_sf_axi_clk", &gcc.mux, 0x6F }, + { "gcc_disp_xo_clk", &gcc.mux, 0x70 }, + { "gcc_gp1_clk", &gcc.mux, 0x122 }, + { "gcc_gp2_clk", &gcc.mux, 0x123 }, + { "gcc_gp3_clk", &gcc.mux, 0x124 }, + { "gcc_gpu_cfg_ahb_clk", &gcc.mux, 0x16B }, + { "gcc_gpu_gpll0_clk_src", &gcc.mux, 0x172 }, + { "gcc_gpu_gpll0_div_clk_src", &gcc.mux, 0x173 }, + { "gcc_gpu_memnoc_gfx_clk", &gcc.mux, 0x16F }, + { "gcc_gpu_snoc_dvm_gfx_clk", &gcc.mux, 0x171 }, + { "gcc_pcie_0_aux_clk", &gcc.mux, 0x12A }, + { "gcc_pcie_0_cfg_ahb_clk", &gcc.mux, 0x129 }, + { "gcc_pcie_0_mstr_axi_clk", &gcc.mux, 0x128 }, + { "gcc_pcie_0_phy_rchng_clk", &gcc.mux, 0x12C }, + { "gcc_pcie_0_pipe_clk", &gcc.mux, 0x12B }, + { "gcc_pcie_0_slv_axi_clk", &gcc.mux, 0x127 }, + { "gcc_pcie_0_slv_q2a_axi_clk", &gcc.mux, 0x126 }, + { "gcc_pcie_1_aux_clk", &gcc.mux, 0x133 }, + { "gcc_pcie_1_cfg_ahb_clk", &gcc.mux, 0x132 }, + { "gcc_pcie_1_mstr_axi_clk", &gcc.mux, 0x131 }, + { "gcc_pcie_1_phy_aux_clk", &gcc.mux, 0x134 }, + { "gcc_pcie_1_phy_rchng_clk", &gcc.mux, 0x136 }, + { "gcc_pcie_1_pipe_clk", &gcc.mux, 0x135 }, + { "gcc_pcie_1_slv_axi_clk", &gcc.mux, 0x130 }, + { "gcc_pcie_1_slv_q2a_axi_clk", &gcc.mux, 0x12F }, + { "gcc_pdm2_clk", &gcc.mux, 0xCB }, + { "gcc_pdm_ahb_clk", &gcc.mux, 0xC9 }, + { "gcc_pdm_xo4_clk", &gcc.mux, 0xCA }, + { "gcc_qmip_camera_nrt_ahb_clk", &gcc.mux, 0x64 }, + { "gcc_qmip_camera_rt_ahb_clk", &gcc.mux, 0x65 }, + { "gcc_qmip_disp_ahb_clk", &gcc.mux, 0x6D }, + { "gcc_qmip_gpu_ahb_clk", &gcc.mux, 0x16C }, + { "gcc_qmip_pcie_ahb_clk", &gcc.mux, 0x125 }, + { "gcc_qmip_video_cv_cpu_ahb_clk", &gcc.mux, 0x76 }, + { "gcc_qmip_video_cvp_ahb_clk", &gcc.mux, 0x73 }, + { "gcc_qmip_video_v_cpu_ahb_clk", &gcc.mux, 0x75 }, + { "gcc_qmip_video_vcodec_ahb_clk", &gcc.mux, 0x74 }, + { "gcc_qupv3_wrap0_core_2x_clk", &gcc.mux, 0xAA }, + { "gcc_qupv3_wrap0_core_clk", &gcc.mux, 0xA9 }, + { "gcc_qupv3_wrap0_s0_clk", &gcc.mux, 0xAB }, + { "gcc_qupv3_wrap0_s1_clk", &gcc.mux, 0xAC }, + { "gcc_qupv3_wrap0_s2_clk", &gcc.mux, 0xAD }, + { "gcc_qupv3_wrap0_s3_clk", &gcc.mux, 0xAE }, + { "gcc_qupv3_wrap0_s4_clk", &gcc.mux, 0xAF }, + { "gcc_qupv3_wrap0_s5_clk", &gcc.mux, 0xB0 }, + { "gcc_qupv3_wrap0_s6_clk", &gcc.mux, 0xB1 }, + { "gcc_qupv3_wrap0_s7_clk", &gcc.mux, 0xB2 }, + { "gcc_qupv3_wrap1_core_2x_clk", &gcc.mux, 0xB6 }, + { "gcc_qupv3_wrap1_core_clk", &gcc.mux, 0xB5 }, + { "gcc_qupv3_wrap1_s0_clk", &gcc.mux, 0xB7 }, + { "gcc_qupv3_wrap1_s1_clk", &gcc.mux, 0xB8 }, + { "gcc_qupv3_wrap1_s2_clk", &gcc.mux, 0xB9 }, + { "gcc_qupv3_wrap1_s3_clk", &gcc.mux, 0xBA }, + { "gcc_qupv3_wrap1_s4_clk", &gcc.mux, 0xBB }, + { "gcc_qupv3_wrap1_s5_clk", &gcc.mux, 0xBC }, + { "gcc_qupv3_wrap1_s6_clk", &gcc.mux, 0xBD }, + { "gcc_qupv3_wrap2_core_2x_clk", &gcc.mux, 0xC1 }, + { "gcc_qupv3_wrap2_core_clk", &gcc.mux, 0xC0 }, + { "gcc_qupv3_wrap2_s0_clk", &gcc.mux, 0xC2 }, + { "gcc_qupv3_wrap2_s1_clk", &gcc.mux, 0xC3 }, + { "gcc_qupv3_wrap2_s2_clk", &gcc.mux, 0xC4 }, + { "gcc_qupv3_wrap2_s3_clk", &gcc.mux, 0xC5 }, + { "gcc_qupv3_wrap2_s4_clk", &gcc.mux, 0xC6 }, + { "gcc_qupv3_wrap2_s5_clk", &gcc.mux, 0xC7 }, + { "gcc_qupv3_wrap2_s6_clk", &gcc.mux, 0xC8 }, + { "gcc_qupv3_wrap_0_m_ahb_clk", &gcc.mux, 0xA7 }, + { "gcc_qupv3_wrap_0_s_ahb_clk", &gcc.mux, 0xA8 }, + { "gcc_qupv3_wrap_1_m_ahb_clk", &gcc.mux, 0xB3 }, + { "gcc_qupv3_wrap_1_s_ahb_clk", &gcc.mux, 0xB4 }, + { "gcc_qupv3_wrap_2_m_ahb_clk", &gcc.mux, 0xBE }, + { "gcc_qupv3_wrap_2_s_ahb_clk", &gcc.mux, 0xBF }, + { "gcc_sdcc2_ahb_clk", &gcc.mux, 0xA2 }, + { "gcc_sdcc2_apps_clk", &gcc.mux, 0xA1 }, + { "gcc_sdcc2_at_clk", &gcc.mux, 0xA3 }, + { "gcc_sdcc4_ahb_clk", &gcc.mux, 0xA5 }, + { "gcc_sdcc4_apps_clk", &gcc.mux, 0xA4 }, + { "gcc_sdcc4_at_clk", &gcc.mux, 0xA6 }, + { "gcc_ufs_phy_ahb_clk", &gcc.mux, 0x13B }, + { "gcc_ufs_phy_axi_clk", &gcc.mux, 0x13A }, + { "gcc_ufs_phy_ice_core_clk", &gcc.mux, 0x141 }, + { "gcc_ufs_phy_phy_aux_clk", &gcc.mux, 0x142 }, + { "gcc_ufs_phy_rx_symbol_0_clk", &gcc.mux, 0x13D }, + { "gcc_ufs_phy_rx_symbol_1_clk", &gcc.mux, 0x143 }, + { "gcc_ufs_phy_tx_symbol_0_clk", &gcc.mux, 0x13C }, + { "gcc_ufs_phy_unipro_core_clk", &gcc.mux, 0x140 }, + { "gcc_usb30_prim_master_clk", &gcc.mux, 0x94 }, + { "gcc_usb30_prim_mock_utmi_clk", &gcc.mux, 0x96 }, + { "gcc_usb30_prim_sleep_clk", &gcc.mux, 0x95 }, + { "gcc_usb3_prim_phy_aux_clk", &gcc.mux, 0x97 }, + { "gcc_usb3_prim_phy_com_aux_clk", &gcc.mux, 0x98 }, + { "gcc_usb3_prim_phy_pipe_clk", &gcc.mux, 0x99 }, + { "gcc_video_ahb_clk", &gcc.mux, 0x72 }, + { "gcc_video_axi0_clk", &gcc.mux, 0x77 }, + { "gcc_video_axi1_clk", &gcc.mux, 0x78 }, + { "gcc_video_xo_clk", &gcc.mux, 0x79 }, + { "measure_only_cnoc_clk", &gcc.mux, 0x19 }, + { "measure_only_ipa_2x_clk", &gcc.mux, 0x158 }, + { "measure_only_memnoc_clk", &gcc.mux, 0xFB }, + { "measure_only_snoc_clk", &gcc.mux, 0xC }, + { "pcie_0_pipe_clk", &gcc.mux, 0x12D }, + { "pcie_1_phy_aux_clk", &gcc.mux, 0x138 }, + { "pcie_1_pipe_clk", &gcc.mux, 0x137 }, + { "ufs_phy_rx_symbol_0_clk", &gcc.mux, 0x13F }, + { "ufs_phy_rx_symbol_1_clk", &gcc.mux, 0x144 }, + { "ufs_phy_tx_symbol_0_clk", &gcc.mux, 0x13E }, + { "usb3_phy_wrapper_gcc_usb30_pipe_clk", &gcc.mux, 0x9D }, + { "mc_cc_debug_mux", &gcc.mux, 0x100 }, + + { "gpu_cc_ahb_clk", &gpu_cc, 0x16 }, + { "gpu_cc_crc_ahb_clk", &gpu_cc, 0x17 }, + { "gpu_cc_cx_apb_clk", &gpu_cc, 0x1A }, + { "gpu_cc_cx_ff_clk", &gpu_cc, 0x21 }, + { "gpu_cc_cx_gmu_clk", &gpu_cc, 0x1E }, + { "gpu_cc_cx_snoc_dvm_clk", &gpu_cc, 0x1B }, + { "gpu_cc_cxo_aon_clk", &gpu_cc, 0xB }, + { "gpu_cc_cxo_clk", &gpu_cc, 0x1F }, + { "gpu_cc_demet_clk", &gpu_cc, 0xD }, + { "gpu_cc_freq_measure_clk", &gpu_cc, 0xC }, + { "gpu_cc_gx_ff_clk", &gpu_cc, 0x13 }, + { "gpu_cc_gx_gfx3d_rdvm_clk", &gpu_cc, 0x15 }, + { "gpu_cc_gx_gmu_clk", &gpu_cc, 0x12 }, + { "gpu_cc_gx_vsense_clk", &gpu_cc, 0xF }, + { "gpu_cc_hub_aon_clk", &gpu_cc, 0x2F }, + { "gpu_cc_hub_cx_int_clk", &gpu_cc, 0x20 }, + { "gpu_cc_memnoc_gfx_clk", &gpu_cc, 0x22 }, + { "gpu_cc_mnd1x_0_gfx3d_clk", &gpu_cc, 0x29 }, + { "gpu_cc_mnd1x_1_gfx3d_clk", &gpu_cc, 0x2A }, + { "gpu_cc_sleep_clk", &gpu_cc, 0x1C }, + { "measure_only_gpu_cc_cx_gfx3d_clk", &gpu_cc, 0x25 }, + { "measure_only_gpu_cc_cx_gfx3d_slv_clk", &gpu_cc, 0x26 }, + { "measure_only_gpu_cc_gx_gfx3d_clk", &gpu_cc, 0xE }, + + { "video_cc_ahb_clk", &video_cc, 0x7 }, + { "video_cc_mvs0_clk", &video_cc, 0x3 }, + { "video_cc_mvs0c_clk", &video_cc, 0x1 }, + { "video_cc_mvs1_clk", &video_cc, 0x5 }, + { "video_cc_mvs1c_clk", &video_cc, 0x9 }, + { "video_cc_sleep_clk", &video_cc, 0xC }, + { "video_cc_xo_clk", &video_cc, 0xB }, {} }; diff --git a/sm8550.c b/sm8550.c index 9e698be..ced2325 100644 --- a/sm8550.c +++ b/sm8550.c @@ -42,19 +42,23 @@ /* Enabling APSS can cause Bus error issues, so do not enable them by default */ #define ENABLE_SM8550_APSS_CLOCKS 0 -static struct debug_mux gcc = { - .phys = 0x100000, - .size = 0x1f4200, +static struct gcc_mux gcc = { + .mux = { + .phys = 0x100000, + .size = 0x1f4200, - .enable_reg = 0x62004, - .enable_mask = BIT(0), + .measure = measure_gcc, - .mux_reg = 0x62024, - .mux_mask = 0x3ff, + .enable_reg = 0x62004, + .enable_mask = BIT(0), - .div_reg = 0x62000, - .div_mask = 0xf, - .div_val = 2, + .mux_reg = 0x62024, + .mux_mask = 0x3ff, + + .div_reg = 0x62000, + .div_mask = 0xf, + .div_val = 2, + }, .xo_div4_reg = 0x62008, .debug_ctl_reg = 0x62048, @@ -66,6 +70,10 @@ static struct debug_mux apss_cc = { .phys = 0x17a80000, .size = 0x21000, + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x122, + .enable_reg = 0x20108, .enable_mask = BIT(0), @@ -84,6 +92,10 @@ static struct debug_mux cam_cc = { .size = 0x20000, .block_name = "cam", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x69, + .enable_reg = 0x14008, .enable_mask = BIT(0), @@ -100,6 +112,10 @@ static struct debug_mux disp_cc = { .size = 0x20000, .block_name = "disp", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x6e, + .enable_reg = 0xd004, .enable_mask = BIT(0), @@ -116,6 +132,10 @@ static struct debug_mux gpu_cc = { .size = 0xa000, .block_name = "gpu", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x178, + .enable_reg = 0x9274, .enable_mask = BIT(0), @@ -132,6 +152,10 @@ static struct debug_mux video_cc = { .size = 0x10000, .block_name = "video", + .measure = measure_leaf, + .parent = &gcc.mux, + .parent_mux_val = 0x77, + .enable_reg = 0x80fc, .enable_mask = BIT(0), @@ -144,304 +168,297 @@ static struct debug_mux video_cc = { }; static struct measure_clk sm8550_clocks[] = { + // { "mc_cc_debug_mux or ddrss_gcc_debug_clk", &gcc.mux, 0xFD }, #if ENABLE_SM8550_APSS_CLOCKS -/* apss_cc_debug_mux is 0x122 */ - { "measure_only_apcs_gold_post_acd_clk", &gcc, 0x122, &apss_cc, 0x4, 8 }, - { "measure_only_apcs_goldplus_post_acd_clk", &gcc, 0x122, &apss_cc, 0x8, 8 }, - { "measure_only_apcs_l3_post_acd_clk", &gcc, 0x122, &apss_cc, 0x6, 4 }, - { "measure_only_apcs_silver_post_acd_clk", &gcc, 0x122, &apss_cc, 0x2, 4 }, + { "measure_only_apcs_gold_post_acd_clk", &apss_cc, 0x4, 8 }, + { "measure_only_apcs_goldplus_post_acd_clk", &apss_cc, 0x8, 8 }, + { "measure_only_apcs_l3_post_acd_clk", &apss_cc, 0x6, 4 }, + { "measure_only_apcs_silver_post_acd_clk", &apss_cc, 0x2, 4 }, #endif -/* cam_cc_debug_mux is 0x69 */ - { "cam_cc_bps_ahb_clk", &gcc, 0x69, &cam_cc, 0x17 }, - { "cam_cc_bps_clk", &gcc, 0x69, &cam_cc, 0x18 }, - { "cam_cc_bps_fast_ahb_clk", &gcc, 0x69, &cam_cc, 0x16 }, - { "cam_cc_camnoc_axi_clk", &gcc, 0x69, &cam_cc, 0x49 }, - { "cam_cc_camnoc_dcd_xo_clk", &gcc, 0x69, &cam_cc, 0x4A }, - { "cam_cc_camnoc_xo_clk", &gcc, 0x69, &cam_cc, 0x6 }, - { "cam_cc_cci_0_clk", &gcc, 0x69, &cam_cc, 0x44 }, - { "cam_cc_cci_1_clk", &gcc, 0x69, &cam_cc, 0x45 }, - { "cam_cc_cci_2_clk", &gcc, 0x69, &cam_cc, 0x61 }, - { "cam_cc_core_ahb_clk", &gcc, 0x69, &cam_cc, 0x4D }, - { "cam_cc_cpas_ahb_clk", &gcc, 0x69, &cam_cc, 0x46 }, - { "cam_cc_cpas_bps_clk", &gcc, 0x69, &cam_cc, 0x19 }, - { "cam_cc_cpas_cre_clk", &gcc, 0x69, &cam_cc, 0x5D }, - { "cam_cc_cpas_fast_ahb_clk", &gcc, 0x69, &cam_cc, 0x47 }, - { "cam_cc_cpas_ife_0_clk", &gcc, 0x69, &cam_cc, 0x25 }, - { "cam_cc_cpas_ife_1_clk", &gcc, 0x69, &cam_cc, 0x2A }, - { "cam_cc_cpas_ife_2_clk", &gcc, 0x69, &cam_cc, 0x2F }, - { "cam_cc_cpas_ife_lite_clk", &gcc, 0x69, &cam_cc, 0x34 }, - { "cam_cc_cpas_ipe_nps_clk", &gcc, 0x69, &cam_cc, 0x1B }, - { "cam_cc_cpas_sbi_clk", &gcc, 0x69, &cam_cc, 0x22 }, - { "cam_cc_cpas_sfe_0_clk", &gcc, 0x69, &cam_cc, 0x39 }, - { "cam_cc_cpas_sfe_1_clk", &gcc, 0x69, &cam_cc, 0x3D }, - { "cam_cc_cre_ahb_clk", &gcc, 0x69, &cam_cc, 0x5E }, - { "cam_cc_cre_clk", &gcc, 0x69, &cam_cc, 0x5C }, - { "cam_cc_csi0phytimer_clk", &gcc, 0x69, &cam_cc, 0x9 }, - { "cam_cc_csi1phytimer_clk", &gcc, 0x69, &cam_cc, 0xC }, - { "cam_cc_csi2phytimer_clk", &gcc, 0x69, &cam_cc, 0xE }, - { "cam_cc_csi3phytimer_clk", &gcc, 0x69, &cam_cc, 0x1 }, - { "cam_cc_csi4phytimer_clk", &gcc, 0x69, &cam_cc, 0x12 }, - { "cam_cc_csi5phytimer_clk", &gcc, 0x69, &cam_cc, 0x14 }, - { "cam_cc_csi6phytimer_clk", &gcc, 0x69, &cam_cc, 0x58 }, - { "cam_cc_csi7phytimer_clk", &gcc, 0x69, &cam_cc, 0x5A }, - { "cam_cc_csid_clk", &gcc, 0x69, &cam_cc, 0x48 }, - { "cam_cc_csid_csiphy_rx_clk", &gcc, 0x69, &cam_cc, 0xB }, - { "cam_cc_csiphy0_clk", &gcc, 0x69, &cam_cc, 0xA }, - { "cam_cc_csiphy1_clk", &gcc, 0x69, &cam_cc, 0xD }, - { "cam_cc_csiphy2_clk", &gcc, 0x69, &cam_cc, 0xF }, - { "cam_cc_csiphy3_clk", &gcc, 0x69, &cam_cc, 0x11 }, - { "cam_cc_csiphy4_clk", &gcc, 0x69, &cam_cc, 0x13 }, - { "cam_cc_csiphy5_clk", &gcc, 0x69, &cam_cc, 0x15 }, - { "cam_cc_csiphy6_clk", &gcc, 0x69, &cam_cc, 0x59 }, - { "cam_cc_csiphy7_clk", &gcc, 0x69, &cam_cc, 0x5B }, - { "cam_cc_drv_ahb_clk", &gcc, 0x69, &cam_cc, 0x75 }, - { "cam_cc_drv_xo_clk", &gcc, 0x69, &cam_cc, 0x74 }, - { "cam_cc_gdsc_clk", &gcc, 0x69, &cam_cc, 0x4E }, - { "cam_cc_icp_ahb_clk", &gcc, 0x69, &cam_cc, 0x43 }, - { "cam_cc_icp_clk", &gcc, 0x69, &cam_cc, 0x42 }, - { "cam_cc_ife_0_clk", &gcc, 0x69, &cam_cc, 0x24 }, - { "cam_cc_ife_0_dsp_clk", &gcc, 0x69, &cam_cc, 0x26 }, - { "cam_cc_ife_0_fast_ahb_clk", &gcc, 0x69, &cam_cc, 0x28 }, - { "cam_cc_ife_1_clk", &gcc, 0x69, &cam_cc, 0x29 }, - { "cam_cc_ife_1_dsp_clk", &gcc, 0x69, &cam_cc, 0x2B }, - { "cam_cc_ife_1_fast_ahb_clk", &gcc, 0x69, &cam_cc, 0x2D }, - { "cam_cc_ife_2_clk", &gcc, 0x69, &cam_cc, 0x2E }, - { "cam_cc_ife_2_dsp_clk", &gcc, 0x69, &cam_cc, 0x3 }, - { "cam_cc_ife_2_fast_ahb_clk", &gcc, 0x69, &cam_cc, 0x32 }, - { "cam_cc_ife_lite_ahb_clk", &gcc, 0x69, &cam_cc, 0x37 }, - { "cam_cc_ife_lite_clk", &gcc, 0x69, &cam_cc, 0x33 }, - { "cam_cc_ife_lite_cphy_rx_clk", &gcc, 0x69, &cam_cc, 0x36 }, - { "cam_cc_ife_lite_csid_clk", &gcc, 0x69, &cam_cc, 0x35 }, - { "cam_cc_ipe_nps_ahb_clk", &gcc, 0x69, &cam_cc, 0x1E }, - { "cam_cc_ipe_nps_clk", &gcc, 0x69, &cam_cc, 0x1A }, - { "cam_cc_ipe_nps_fast_ahb_clk", &gcc, 0x69, &cam_cc, 0x1F }, - { "cam_cc_ipe_pps_clk", &gcc, 0x69, &cam_cc, 0x1C }, - { "cam_cc_ipe_pps_fast_ahb_clk", &gcc, 0x69, &cam_cc, 0x2 }, - { "cam_cc_jpeg_1_clk", &gcc, 0x69, &cam_cc, 0x5F }, - { "cam_cc_jpeg_clk", &gcc, 0x69, &cam_cc, 0x4 }, - { "cam_cc_mclk0_clk", &gcc, 0x69, &cam_cc, 0x1 }, - { "cam_cc_mclk1_clk", &gcc, 0x69, &cam_cc, 0x2 }, - { "cam_cc_mclk2_clk", &gcc, 0x69, &cam_cc, 0x3 }, - { "cam_cc_mclk3_clk", &gcc, 0x69, &cam_cc, 0x4 }, - { "cam_cc_mclk4_clk", &gcc, 0x69, &cam_cc, 0x5 }, - { "cam_cc_mclk5_clk", &gcc, 0x69, &cam_cc, 0x6 }, - { "cam_cc_mclk6_clk", &gcc, 0x69, &cam_cc, 0x7 }, - { "cam_cc_mclk7_clk", &gcc, 0x69, &cam_cc, 0x8 }, - { "cam_cc_qdss_debug_clk", &gcc, 0x69, &cam_cc, 0x4B }, - { "cam_cc_qdss_debug_xo_clk", &gcc, 0x69, &cam_cc, 0x4C }, - { "cam_cc_sbi_clk", &gcc, 0x69, &cam_cc, 0x21 }, - { "cam_cc_sbi_fast_ahb_clk", &gcc, 0x69, &cam_cc, 0x23 }, - { "cam_cc_sfe_0_clk", &gcc, 0x69, &cam_cc, 0x38 }, - { "cam_cc_sfe_0_fast_ahb_clk", &gcc, 0x69, &cam_cc, 0x3B }, - { "cam_cc_sfe_1_clk", &gcc, 0x69, &cam_cc, 0x3C }, - { "cam_cc_sfe_1_fast_ahb_clk", &gcc, 0x69, &cam_cc, 0x3F }, - { "cam_cc_sleep_clk", &gcc, 0x69, &cam_cc, 0x4F }, -/* disp_cc_debug_mux is 0x6e */ - { "disp_cc_mdss_accu_clk", &gcc, 0x6E, &disp_cc, 0x46 }, - { "disp_cc_mdss_ahb1_clk", &gcc, 0x6E, &disp_cc, 0x37 }, - { "disp_cc_mdss_ahb_clk", &gcc, 0x6E, &disp_cc, 0x33 }, - { "disp_cc_mdss_byte0_clk", &gcc, 0x6E, &disp_cc, 0x14 }, - { "disp_cc_mdss_byte0_intf_clk", &gcc, 0x6E, &disp_cc, 0x15 }, - { "disp_cc_mdss_byte1_clk", &gcc, 0x6E, &disp_cc, 0x16 }, - { "disp_cc_mdss_byte1_intf_clk", &gcc, 0x6E, &disp_cc, 0x17 }, - { "disp_cc_mdss_dptx0_aux_clk", &gcc, 0x6E, &disp_cc, 0x2 }, - { "disp_cc_mdss_dptx0_crypto_clk", &gcc, 0x6E, &disp_cc, 0x1D }, - { "disp_cc_mdss_dptx0_link_clk", &gcc, 0x6E, &disp_cc, 0x1A }, - { "disp_cc_mdss_dptx0_link_intf_clk", &gcc, 0x6E, &disp_cc, 0x1C }, - { "disp_cc_mdss_dptx0_pixel0_clk", &gcc, 0x6E, &disp_cc, 0x1E }, - { "disp_cc_mdss_dptx0_pixel1_clk", &gcc, 0x6E, &disp_cc, 0x1F }, - { "disp_cc_mdss_dptx0_usb_router_link_intf_clk", &gcc, 0x6E, &disp_cc, 0x1B }, - { "disp_cc_mdss_dptx1_aux_clk", &gcc, 0x6E, &disp_cc, 0x27 }, - { "disp_cc_mdss_dptx1_crypto_clk", &gcc, 0x6E, &disp_cc, 0x26 }, - { "disp_cc_mdss_dptx1_link_clk", &gcc, 0x6E, &disp_cc, 0x23 }, - { "disp_cc_mdss_dptx1_link_intf_clk", &gcc, 0x6E, &disp_cc, 0x25 }, - { "disp_cc_mdss_dptx1_pixel0_clk", &gcc, 0x6E, &disp_cc, 0x21 }, - { "disp_cc_mdss_dptx1_pixel1_clk", &gcc, 0x6E, &disp_cc, 0x22 }, - { "disp_cc_mdss_dptx1_usb_router_link_intf_clk", &gcc, 0x6E, &disp_cc, 0x24 }, - { "disp_cc_mdss_dptx2_aux_clk", &gcc, 0x6E, &disp_cc, 0x2D }, - { "disp_cc_mdss_dptx2_crypto_clk", &gcc, 0x6E, &disp_cc, 0x2C }, - { "disp_cc_mdss_dptx2_link_clk", &gcc, 0x6E, &disp_cc, 0x2A }, - { "disp_cc_mdss_dptx2_link_intf_clk", &gcc, 0x6E, &disp_cc, 0x2B }, - { "disp_cc_mdss_dptx2_pixel0_clk", &gcc, 0x6E, &disp_cc, 0x28 }, - { "disp_cc_mdss_dptx2_pixel1_clk", &gcc, 0x6E, &disp_cc, 0x29 }, - { "disp_cc_mdss_dptx3_aux_clk", &gcc, 0x6E, &disp_cc, 0x31 }, - { "disp_cc_mdss_dptx3_crypto_clk", &gcc, 0x6E, &disp_cc, 0x32 }, - { "disp_cc_mdss_dptx3_link_clk", &gcc, 0x6E, &disp_cc, 0x2F }, - { "disp_cc_mdss_dptx3_link_intf_clk", &gcc, 0x6E, &disp_cc, 0x3 }, - { "disp_cc_mdss_dptx3_pixel0_clk", &gcc, 0x6E, &disp_cc, 0x2E }, - { "disp_cc_mdss_esc0_clk", &gcc, 0x6E, &disp_cc, 0x18 }, - { "disp_cc_mdss_esc1_clk", &gcc, 0x6E, &disp_cc, 0x19 }, - { "disp_cc_mdss_mdp1_clk", &gcc, 0x6E, &disp_cc, 0x34 }, - { "disp_cc_mdss_mdp_clk", &gcc, 0x6E, &disp_cc, 0x11 }, - { "disp_cc_mdss_mdp_lut1_clk", &gcc, 0x6E, &disp_cc, 0x35 }, - { "disp_cc_mdss_mdp_lut_clk", &gcc, 0x6E, &disp_cc, 0x12 }, - { "disp_cc_mdss_non_gdsc_ahb_clk", &gcc, 0x6E, &disp_cc, 0x38 }, - { "disp_cc_mdss_pclk0_clk", &gcc, 0x6E, &disp_cc, 0xF }, - { "disp_cc_mdss_pclk1_clk", &gcc, 0x6E, &disp_cc, 0x1 }, - { "disp_cc_mdss_rscc_ahb_clk", &gcc, 0x6E, &disp_cc, 0x3A }, - { "disp_cc_mdss_rscc_vsync_clk", &gcc, 0x6E, &disp_cc, 0x39 }, - { "disp_cc_mdss_vsync1_clk", &gcc, 0x6E, &disp_cc, 0x36 }, - { "disp_cc_mdss_vsync_clk", &gcc, 0x6E, &disp_cc, 0x13 }, - { "disp_cc_sleep_clk", &gcc, 0x6E, &disp_cc, 0x47 }, - { "disp_cc_xo_clk", &gcc, 0x6E, &disp_cc, 0x45 }, -// gcc - //{ "apss_cc_debug_mux", &gcc, 0x122 }, - //{ "cam_cc_debug_mux", &gcc, 0x69 }, - //{ "disp_cc_debug_mux", &gcc, 0x6E }, - { "gcc_aggre_noc_pcie_axi_clk", &gcc, 0x3E }, - { "gcc_aggre_ufs_phy_axi_clk", &gcc, 0x4 }, - { "gcc_aggre_usb3_prim_axi_clk", &gcc, 0x3F }, - { "gcc_ahb2phy_0_clk", &gcc, 0x9A }, - { "gcc_boot_rom_ahb_clk", &gcc, 0xD7 }, - { "gcc_camera_ahb_clk", &gcc, 0x61 }, - { "gcc_camera_hf_axi_clk", &gcc, 0x64 }, - { "gcc_camera_sf_axi_clk", &gcc, 0x66 }, - { "gcc_camera_xo_clk", &gcc, 0x68 }, - { "gcc_cfg_noc_pcie_anoc_ahb_clk", &gcc, 0x2C }, - { "gcc_cfg_noc_usb3_prim_axi_clk", &gcc, 0x1F }, - { "gcc_cnoc_pcie_sf_axi_clk", &gcc, 0x19 }, - { "gcc_ddrss_gpu_axi_clk", &gcc, 0xF1 }, - { "gcc_ddrss_pcie_sf_qtb_clk", &gcc, 0xF2 }, - { "gcc_disp_ahb_clk", &gcc, 0x6A }, - { "gcc_disp_hf_axi_clk", &gcc, 0x6C }, - { "gcc_disp_xo_clk", &gcc, 0x6D }, - { "gcc_gp1_clk", &gcc, 0x12F }, - { "gcc_gp2_clk", &gcc, 0x13 }, - { "gcc_gp3_clk", &gcc, 0x131 }, - { "gcc_gpu_cfg_ahb_clk", &gcc, 0x175 }, - { "gcc_gpu_gpll0_clk_src", &gcc, 0x17C }, - { "gcc_gpu_gpll0_div_clk_src", &gcc, 0x17D }, - { "gcc_gpu_memnoc_gfx_clk", &gcc, 0x179 }, - { "gcc_gpu_snoc_dvm_gfx_clk", &gcc, 0x17B }, - { "gcc_pcie_0_aux_clk", &gcc, 0x137 }, - { "gcc_pcie_0_cfg_ahb_clk", &gcc, 0x136 }, - { "gcc_pcie_0_mstr_axi_clk", &gcc, 0x135 }, - { "gcc_pcie_0_phy_rchng_clk", &gcc, 0x139 }, - { "gcc_pcie_0_pipe_clk", &gcc, 0x138 }, - { "gcc_pcie_0_slv_axi_clk", &gcc, 0x134 }, - { "gcc_pcie_0_slv_q2a_axi_clk", &gcc, 0x133 }, - { "gcc_pcie_1_aux_clk", &gcc, 0x14 }, - { "gcc_pcie_1_cfg_ahb_clk", &gcc, 0x13F }, - { "gcc_pcie_1_mstr_axi_clk", &gcc, 0x13E }, - { "gcc_pcie_1_phy_aux_clk", &gcc, 0x141 }, - { "gcc_pcie_1_phy_rchng_clk", &gcc, 0x143 }, - { "gcc_pcie_1_pipe_clk", &gcc, 0x142 }, - { "gcc_pcie_1_slv_axi_clk", &gcc, 0x13D }, - { "gcc_pcie_1_slv_q2a_axi_clk", &gcc, 0x13C }, - { "gcc_pdm2_clk", &gcc, 0xC8 }, - { "gcc_pdm_ahb_clk", &gcc, 0xC6 }, - { "gcc_pdm_xo4_clk", &gcc, 0xC7 }, - { "gcc_qmip_camera_nrt_ahb_clk", &gcc, 0x62 }, - { "gcc_qmip_camera_rt_ahb_clk", &gcc, 0x63 }, - { "gcc_qmip_disp_ahb_clk", &gcc, 0x6B }, - { "gcc_qmip_gpu_ahb_clk", &gcc, 0x176 }, - { "gcc_qmip_pcie_ahb_clk", &gcc, 0x132 }, - { "gcc_qmip_video_cv_cpu_ahb_clk", &gcc, 0x73 }, - { "gcc_qmip_video_cvp_ahb_clk", &gcc, 0x7 }, - { "gcc_qmip_video_v_cpu_ahb_clk", &gcc, 0x72 }, - { "gcc_qmip_video_vcodec_ahb_clk", &gcc, 0x71 }, - { "gcc_qupv3_i2c_core_clk", &gcc, 0xA2 }, - { "gcc_qupv3_i2c_s0_clk", &gcc, 0xA3 }, - { "gcc_qupv3_i2c_s1_clk", &gcc, 0xA4 }, - { "gcc_qupv3_i2c_s2_clk", &gcc, 0xA5 }, - { "gcc_qupv3_i2c_s3_clk", &gcc, 0xA6 }, - { "gcc_qupv3_i2c_s4_clk", &gcc, 0xA7 }, - { "gcc_qupv3_i2c_s5_clk", &gcc, 0xA8 }, - { "gcc_qupv3_i2c_s6_clk", &gcc, 0xA9 }, - { "gcc_qupv3_i2c_s7_clk", &gcc, 0xAA }, - { "gcc_qupv3_i2c_s8_clk", &gcc, 0xAB }, - { "gcc_qupv3_i2c_s9_clk", &gcc, 0xAC }, - { "gcc_qupv3_i2c_s_ahb_clk", &gcc, 0xA1 }, - { "gcc_qupv3_wrap1_core_2x_clk", &gcc, 0xB }, - { "gcc_qupv3_wrap1_core_clk", &gcc, 0xAF }, - { "gcc_qupv3_wrap1_s0_clk", &gcc, 0xB2 }, - { "gcc_qupv3_wrap1_s1_clk", &gcc, 0xB3 }, - { "gcc_qupv3_wrap1_s2_clk", &gcc, 0xB4 }, - { "gcc_qupv3_wrap1_s3_clk", &gcc, 0xB5 }, - { "gcc_qupv3_wrap1_s4_clk", &gcc, 0xB6 }, - { "gcc_qupv3_wrap1_s5_clk", &gcc, 0xB7 }, - { "gcc_qupv3_wrap1_s6_clk", &gcc, 0xB8 }, - { "gcc_qupv3_wrap1_s7_clk", &gcc, 0xB9 }, - { "gcc_qupv3_wrap2_core_2x_clk", &gcc, 0xBD }, - { "gcc_qupv3_wrap2_core_clk", &gcc, 0xBC }, - { "gcc_qupv3_wrap2_s0_clk", &gcc, 0xBE }, - { "gcc_qupv3_wrap2_s1_clk", &gcc, 0xBF }, - { "gcc_qupv3_wrap2_s2_clk", &gcc, 0xC }, - { "gcc_qupv3_wrap2_s3_clk", &gcc, 0xC1 }, - { "gcc_qupv3_wrap2_s4_clk", &gcc, 0xC2 }, - { "gcc_qupv3_wrap2_s5_clk", &gcc, 0xC3 }, - { "gcc_qupv3_wrap2_s6_clk", &gcc, 0xC4 }, - { "gcc_qupv3_wrap2_s7_clk", &gcc, 0xC5 }, - { "gcc_qupv3_wrap_1_m_ahb_clk", &gcc, 0xAD }, - { "gcc_qupv3_wrap_1_s_ahb_clk", &gcc, 0xAE }, - { "gcc_qupv3_wrap_2_m_ahb_clk", &gcc, 0xBA }, - { "gcc_qupv3_wrap_2_s_ahb_clk", &gcc, 0xBB }, - { "gcc_sdcc2_ahb_clk", &gcc, 0x9C }, - { "gcc_sdcc2_apps_clk", &gcc, 0x9B }, - { "gcc_sdcc4_ahb_clk", &gcc, 0x9F }, - { "gcc_sdcc4_apps_clk", &gcc, 0x9E }, - { "gcc_ufs_phy_ahb_clk", &gcc, 0x148 }, - { "gcc_ufs_phy_axi_clk", &gcc, 0x147 }, - { "gcc_ufs_phy_ice_core_clk", &gcc, 0x14E }, - { "gcc_ufs_phy_phy_aux_clk", &gcc, 0x14F }, - { "gcc_ufs_phy_rx_symbol_0_clk", &gcc, 0x14A }, - { "gcc_ufs_phy_rx_symbol_1_clk", &gcc, 0x15 }, - { "gcc_ufs_phy_tx_symbol_0_clk", &gcc, 0x149 }, - { "gcc_ufs_phy_unipro_core_clk", &gcc, 0x14D }, - { "gcc_usb30_prim_master_clk", &gcc, 0x8E }, - { "gcc_usb30_prim_mock_utmi_clk", &gcc, 0x9 }, - { "gcc_usb30_prim_sleep_clk", &gcc, 0x8F }, - { "gcc_usb3_prim_phy_aux_clk", &gcc, 0x91 }, - { "gcc_usb3_prim_phy_com_aux_clk", &gcc, 0x92 }, - { "gcc_usb3_prim_phy_pipe_clk", &gcc, 0x93 }, - { "gcc_video_ahb_clk", &gcc, 0x6F }, - { "gcc_video_axi0_clk", &gcc, 0x74 }, - { "gcc_video_axi1_clk", &gcc, 0x75 }, - { "gcc_video_xo_clk", &gcc, 0x76 }, - //{ "gpu_cc_debug_mux", &gcc, 0x178 }, - { "measure_only_cnoc_clk", &gcc, 0x17 }, - { "measure_only_ipa_2x_clk", &gcc, 0x161 }, - { "measure_only_memnoc_clk", &gcc, 0xF7 }, - { "measure_only_snoc_clk", &gcc, 0xB }, - { "pcie_0_pipe_clk", &gcc, 0x13A }, - { "pcie_1_phy_aux_clk", &gcc, 0x145 }, - { "pcie_1_pipe_clk", &gcc, 0x144 }, - { "ufs_phy_rx_symbol_0_clk", &gcc, 0x14C }, - { "ufs_phy_rx_symbol_1_clk", &gcc, 0x152 }, - { "ufs_phy_tx_symbol_0_clk", &gcc, 0x14B }, - { "usb3_phy_wrapper_gcc_usb30_pipe_clk", &gcc, 0x97 }, - //{ "video_cc_debug_mux", &gcc, 0x77 }, - { "mc_cc_debug_mux or ddrss_gcc_debug_clk", &gcc, 0xFD }, -/* gpu_cc_debug_mux is 0x178 */ - { "gpu_cc_ahb_clk", &gcc, 0x178, &gpu_cc, 0x16 }, - { "gpu_cc_crc_ahb_clk", &gcc, 0x178, &gpu_cc, 0x17 }, - { "gpu_cc_cx_ff_clk", &gcc, 0x178, &gpu_cc, 0x2 }, - { "gpu_cc_cx_gmu_clk", &gcc, 0x178, &gpu_cc, 0x1D }, - { "gpu_cc_cxo_aon_clk", &gcc, 0x178, &gpu_cc, 0xB }, - { "gpu_cc_cxo_clk", &gcc, 0x178, &gpu_cc, 0x1E }, - { "gpu_cc_demet_clk", &gcc, 0x178, &gpu_cc, 0xD }, - { "gpu_cc_freq_measure_clk", &gcc, 0x178, &gpu_cc, 0xC }, - { "gpu_cc_gx_ff_clk", &gcc, 0x178, &gpu_cc, 0x13 }, - { "gpu_cc_gx_gfx3d_rdvm_clk", &gcc, 0x178, &gpu_cc, 0x15 }, - { "gpu_cc_gx_gmu_clk", &gcc, 0x178, &gpu_cc, 0x12 }, - { "gpu_cc_gx_vsense_clk", &gcc, 0x178, &gpu_cc, 0xF }, - { "gpu_cc_hub_aon_clk", &gcc, 0x178, &gpu_cc, 0x2D }, - { "gpu_cc_hub_cx_int_clk", &gcc, 0x178, &gpu_cc, 0x1F }, - { "gpu_cc_memnoc_gfx_clk", &gcc, 0x178, &gpu_cc, 0x21 }, - { "gpu_cc_mnd1x_0_gfx3d_clk", &gcc, 0x178, &gpu_cc, 0x28 }, - { "gpu_cc_mnd1x_1_gfx3d_clk", &gcc, 0x178, &gpu_cc, 0x29 }, - { "gpu_cc_sleep_clk", &gcc, 0x178, &gpu_cc, 0x1B }, - { "measure_only_gpu_cc_cx_gfx3d_clk", &gcc, 0x178, &gpu_cc, 0x24 }, - { "measure_only_gpu_cc_cx_gfx3d_slv_clk", &gcc, 0x178, &gpu_cc, 0x25 }, - { "measure_only_gpu_cc_gx_gfx3d_clk", &gcc, 0x178, &gpu_cc, 0xE }, -/* video_cc_debug_mux is 0x77 */ - { "video_cc_ahb_clk", &gcc, 0x77, &video_cc, 0x7 }, - { "video_cc_mvs0_clk", &gcc, 0x77, &video_cc, 0x3 }, - { "video_cc_mvs0c_clk", &gcc, 0x77, &video_cc, 0x1 }, - { "video_cc_mvs1_clk", &gcc, 0x77, &video_cc, 0x5 }, - { "video_cc_mvs1c_clk", &gcc, 0x77, &video_cc, 0x9 }, - { "video_cc_sleep_clk", &gcc, 0x77, &video_cc, 0xC }, - { "video_cc_xo_clk", &gcc, 0x77, &video_cc, 0xB }, + { "cam_cc_bps_ahb_clk", &cam_cc, 0x17 }, + { "cam_cc_bps_clk", &cam_cc, 0x18 }, + { "cam_cc_bps_fast_ahb_clk", &cam_cc, 0x16 }, + { "cam_cc_camnoc_axi_clk", &cam_cc, 0x49 }, + { "cam_cc_camnoc_dcd_xo_clk", &cam_cc, 0x4A }, + { "cam_cc_camnoc_xo_clk", &cam_cc, 0x6 }, + { "cam_cc_cci_0_clk", &cam_cc, 0x44 }, + { "cam_cc_cci_1_clk", &cam_cc, 0x45 }, + { "cam_cc_cci_2_clk", &cam_cc, 0x61 }, + { "cam_cc_core_ahb_clk", &cam_cc, 0x4D }, + { "cam_cc_cpas_ahb_clk", &cam_cc, 0x46 }, + { "cam_cc_cpas_bps_clk", &cam_cc, 0x19 }, + { "cam_cc_cpas_cre_clk", &cam_cc, 0x5D }, + { "cam_cc_cpas_fast_ahb_clk", &cam_cc, 0x47 }, + { "cam_cc_cpas_ife_0_clk", &cam_cc, 0x25 }, + { "cam_cc_cpas_ife_1_clk", &cam_cc, 0x2A }, + { "cam_cc_cpas_ife_2_clk", &cam_cc, 0x2F }, + { "cam_cc_cpas_ife_lite_clk", &cam_cc, 0x34 }, + { "cam_cc_cpas_ipe_nps_clk", &cam_cc, 0x1B }, + { "cam_cc_cpas_sbi_clk", &cam_cc, 0x22 }, + { "cam_cc_cpas_sfe_0_clk", &cam_cc, 0x39 }, + { "cam_cc_cpas_sfe_1_clk", &cam_cc, 0x3D }, + { "cam_cc_cre_ahb_clk", &cam_cc, 0x5E }, + { "cam_cc_cre_clk", &cam_cc, 0x5C }, + { "cam_cc_csi0phytimer_clk", &cam_cc, 0x9 }, + { "cam_cc_csi1phytimer_clk", &cam_cc, 0xC }, + { "cam_cc_csi2phytimer_clk", &cam_cc, 0xE }, + { "cam_cc_csi3phytimer_clk", &cam_cc, 0x1 }, + { "cam_cc_csi4phytimer_clk", &cam_cc, 0x12 }, + { "cam_cc_csi5phytimer_clk", &cam_cc, 0x14 }, + { "cam_cc_csi6phytimer_clk", &cam_cc, 0x58 }, + { "cam_cc_csi7phytimer_clk", &cam_cc, 0x5A }, + { "cam_cc_csid_clk", &cam_cc, 0x48 }, + { "cam_cc_csid_csiphy_rx_clk", &cam_cc, 0xB }, + { "cam_cc_csiphy0_clk", &cam_cc, 0xA }, + { "cam_cc_csiphy1_clk", &cam_cc, 0xD }, + { "cam_cc_csiphy2_clk", &cam_cc, 0xF }, + { "cam_cc_csiphy3_clk", &cam_cc, 0x11 }, + { "cam_cc_csiphy4_clk", &cam_cc, 0x13 }, + { "cam_cc_csiphy5_clk", &cam_cc, 0x15 }, + { "cam_cc_csiphy6_clk", &cam_cc, 0x59 }, + { "cam_cc_csiphy7_clk", &cam_cc, 0x5B }, + { "cam_cc_drv_ahb_clk", &cam_cc, 0x75 }, + { "cam_cc_drv_xo_clk", &cam_cc, 0x74 }, + { "cam_cc_gdsc_clk", &cam_cc, 0x4E }, + { "cam_cc_icp_ahb_clk", &cam_cc, 0x43 }, + { "cam_cc_icp_clk", &cam_cc, 0x42 }, + { "cam_cc_ife_0_clk", &cam_cc, 0x24 }, + { "cam_cc_ife_0_dsp_clk", &cam_cc, 0x26 }, + { "cam_cc_ife_0_fast_ahb_clk", &cam_cc, 0x28 }, + { "cam_cc_ife_1_clk", &cam_cc, 0x29 }, + { "cam_cc_ife_1_dsp_clk", &cam_cc, 0x2B }, + { "cam_cc_ife_1_fast_ahb_clk", &cam_cc, 0x2D }, + { "cam_cc_ife_2_clk", &cam_cc, 0x2E }, + { "cam_cc_ife_2_dsp_clk", &cam_cc, 0x3 }, + { "cam_cc_ife_2_fast_ahb_clk", &cam_cc, 0x32 }, + { "cam_cc_ife_lite_ahb_clk", &cam_cc, 0x37 }, + { "cam_cc_ife_lite_clk", &cam_cc, 0x33 }, + { "cam_cc_ife_lite_cphy_rx_clk", &cam_cc, 0x36 }, + { "cam_cc_ife_lite_csid_clk", &cam_cc, 0x35 }, + { "cam_cc_ipe_nps_ahb_clk", &cam_cc, 0x1E }, + { "cam_cc_ipe_nps_clk", &cam_cc, 0x1A }, + { "cam_cc_ipe_nps_fast_ahb_clk", &cam_cc, 0x1F }, + { "cam_cc_ipe_pps_clk", &cam_cc, 0x1C }, + { "cam_cc_ipe_pps_fast_ahb_clk", &cam_cc, 0x2 }, + { "cam_cc_jpeg_1_clk", &cam_cc, 0x5F }, + { "cam_cc_jpeg_clk", &cam_cc, 0x4 }, + { "cam_cc_mclk0_clk", &cam_cc, 0x1 }, + { "cam_cc_mclk1_clk", &cam_cc, 0x2 }, + { "cam_cc_mclk2_clk", &cam_cc, 0x3 }, + { "cam_cc_mclk3_clk", &cam_cc, 0x4 }, + { "cam_cc_mclk4_clk", &cam_cc, 0x5 }, + { "cam_cc_mclk5_clk", &cam_cc, 0x6 }, + { "cam_cc_mclk6_clk", &cam_cc, 0x7 }, + { "cam_cc_mclk7_clk", &cam_cc, 0x8 }, + { "cam_cc_qdss_debug_clk", &cam_cc, 0x4B }, + { "cam_cc_qdss_debug_xo_clk", &cam_cc, 0x4C }, + { "cam_cc_sbi_clk", &cam_cc, 0x21 }, + { "cam_cc_sbi_fast_ahb_clk", &cam_cc, 0x23 }, + { "cam_cc_sfe_0_clk", &cam_cc, 0x38 }, + { "cam_cc_sfe_0_fast_ahb_clk", &cam_cc, 0x3B }, + { "cam_cc_sfe_1_clk", &cam_cc, 0x3C }, + { "cam_cc_sfe_1_fast_ahb_clk", &cam_cc, 0x3F }, + { "cam_cc_sleep_clk", &cam_cc, 0x4F }, + + { "disp_cc_mdss_accu_clk", &disp_cc, 0x46 }, + { "disp_cc_mdss_ahb1_clk", &disp_cc, 0x37 }, + { "disp_cc_mdss_ahb_clk", &disp_cc, 0x33 }, + { "disp_cc_mdss_byte0_clk", &disp_cc, 0x14 }, + { "disp_cc_mdss_byte0_intf_clk", &disp_cc, 0x15 }, + { "disp_cc_mdss_byte1_clk", &disp_cc, 0x16 }, + { "disp_cc_mdss_byte1_intf_clk", &disp_cc, 0x17 }, + { "disp_cc_mdss_dptx0_aux_clk", &disp_cc, 0x2 }, + { "disp_cc_mdss_dptx0_crypto_clk", &disp_cc, 0x1D }, + { "disp_cc_mdss_dptx0_link_clk", &disp_cc, 0x1A }, + { "disp_cc_mdss_dptx0_link_intf_clk", &disp_cc, 0x1C }, + { "disp_cc_mdss_dptx0_pixel0_clk", &disp_cc, 0x1E }, + { "disp_cc_mdss_dptx0_pixel1_clk", &disp_cc, 0x1F }, + { "disp_cc_mdss_dptx0_usb_router_link_intf_clk", &disp_cc, 0x1B }, + { "disp_cc_mdss_dptx1_aux_clk", &disp_cc, 0x27 }, + { "disp_cc_mdss_dptx1_crypto_clk", &disp_cc, 0x26 }, + { "disp_cc_mdss_dptx1_link_clk", &disp_cc, 0x23 }, + { "disp_cc_mdss_dptx1_link_intf_clk", &disp_cc, 0x25 }, + { "disp_cc_mdss_dptx1_pixel0_clk", &disp_cc, 0x21 }, + { "disp_cc_mdss_dptx1_pixel1_clk", &disp_cc, 0x22 }, + { "disp_cc_mdss_dptx1_usb_router_link_intf_clk", &disp_cc, 0x24 }, + { "disp_cc_mdss_dptx2_aux_clk", &disp_cc, 0x2D }, + { "disp_cc_mdss_dptx2_crypto_clk", &disp_cc, 0x2C }, + { "disp_cc_mdss_dptx2_link_clk", &disp_cc, 0x2A }, + { "disp_cc_mdss_dptx2_link_intf_clk", &disp_cc, 0x2B }, + { "disp_cc_mdss_dptx2_pixel0_clk", &disp_cc, 0x28 }, + { "disp_cc_mdss_dptx2_pixel1_clk", &disp_cc, 0x29 }, + { "disp_cc_mdss_dptx3_aux_clk", &disp_cc, 0x31 }, + { "disp_cc_mdss_dptx3_crypto_clk", &disp_cc, 0x32 }, + { "disp_cc_mdss_dptx3_link_clk", &disp_cc, 0x2F }, + { "disp_cc_mdss_dptx3_link_intf_clk", &disp_cc, 0x3 }, + { "disp_cc_mdss_dptx3_pixel0_clk", &disp_cc, 0x2E }, + { "disp_cc_mdss_esc0_clk", &disp_cc, 0x18 }, + { "disp_cc_mdss_esc1_clk", &disp_cc, 0x19 }, + { "disp_cc_mdss_mdp1_clk", &disp_cc, 0x34 }, + { "disp_cc_mdss_mdp_clk", &disp_cc, 0x11 }, + { "disp_cc_mdss_mdp_lut1_clk", &disp_cc, 0x35 }, + { "disp_cc_mdss_mdp_lut_clk", &disp_cc, 0x12 }, + { "disp_cc_mdss_non_gdsc_ahb_clk", &disp_cc, 0x38 }, + { "disp_cc_mdss_pclk0_clk", &disp_cc, 0xF }, + { "disp_cc_mdss_pclk1_clk", &disp_cc, 0x1 }, + { "disp_cc_mdss_rscc_ahb_clk", &disp_cc, 0x3A }, + { "disp_cc_mdss_rscc_vsync_clk", &disp_cc, 0x39 }, + { "disp_cc_mdss_vsync1_clk", &disp_cc, 0x36 }, + { "disp_cc_mdss_vsync_clk", &disp_cc, 0x13 }, + { "disp_cc_sleep_clk", &disp_cc, 0x47 }, + { "disp_cc_xo_clk", &disp_cc, 0x45 }, + + { "gcc_aggre_noc_pcie_axi_clk", &gcc.mux, 0x3E }, + { "gcc_aggre_ufs_phy_axi_clk", &gcc.mux, 0x4 }, + { "gcc_aggre_usb3_prim_axi_clk", &gcc.mux, 0x3F }, + { "gcc_ahb2phy_0_clk", &gcc.mux, 0x9A }, + { "gcc_boot_rom_ahb_clk", &gcc.mux, 0xD7 }, + { "gcc_camera_ahb_clk", &gcc.mux, 0x61 }, + { "gcc_camera_hf_axi_clk", &gcc.mux, 0x64 }, + { "gcc_camera_sf_axi_clk", &gcc.mux, 0x66 }, + { "gcc_camera_xo_clk", &gcc.mux, 0x68 }, + { "gcc_cfg_noc_pcie_anoc_ahb_clk", &gcc.mux, 0x2C }, + { "gcc_cfg_noc_usb3_prim_axi_clk", &gcc.mux, 0x1F }, + { "gcc_cnoc_pcie_sf_axi_clk", &gcc.mux, 0x19 }, + { "gcc_ddrss_gpu_axi_clk", &gcc.mux, 0xF1 }, + { "gcc_ddrss_pcie_sf_qtb_clk", &gcc.mux, 0xF2 }, + { "gcc_disp_ahb_clk", &gcc.mux, 0x6A }, + { "gcc_disp_hf_axi_clk", &gcc.mux, 0x6C }, + { "gcc_disp_xo_clk", &gcc.mux, 0x6D }, + { "gcc_gp1_clk", &gcc.mux, 0x12F }, + { "gcc_gp2_clk", &gcc.mux, 0x13 }, + { "gcc_gp3_clk", &gcc.mux, 0x131 }, + { "gcc_gpu_cfg_ahb_clk", &gcc.mux, 0x175 }, + { "gcc_gpu_gpll0_clk_src", &gcc.mux, 0x17C }, + { "gcc_gpu_gpll0_div_clk_src", &gcc.mux, 0x17D }, + { "gcc_gpu_memnoc_gfx_clk", &gcc.mux, 0x179 }, + { "gcc_gpu_snoc_dvm_gfx_clk", &gcc.mux, 0x17B }, + { "gcc_pcie_0_aux_clk", &gcc.mux, 0x137 }, + { "gcc_pcie_0_cfg_ahb_clk", &gcc.mux, 0x136 }, + { "gcc_pcie_0_mstr_axi_clk", &gcc.mux, 0x135 }, + { "gcc_pcie_0_phy_rchng_clk", &gcc.mux, 0x139 }, + { "gcc_pcie_0_pipe_clk", &gcc.mux, 0x138 }, + { "gcc_pcie_0_slv_axi_clk", &gcc.mux, 0x134 }, + { "gcc_pcie_0_slv_q2a_axi_clk", &gcc.mux, 0x133 }, + { "gcc_pcie_1_aux_clk", &gcc.mux, 0x14 }, + { "gcc_pcie_1_cfg_ahb_clk", &gcc.mux, 0x13F }, + { "gcc_pcie_1_mstr_axi_clk", &gcc.mux, 0x13E }, + { "gcc_pcie_1_phy_aux_clk", &gcc.mux, 0x141 }, + { "gcc_pcie_1_phy_rchng_clk", &gcc.mux, 0x143 }, + { "gcc_pcie_1_pipe_clk", &gcc.mux, 0x142 }, + { "gcc_pcie_1_slv_axi_clk", &gcc.mux, 0x13D }, + { "gcc_pcie_1_slv_q2a_axi_clk", &gcc.mux, 0x13C }, + { "gcc_pdm2_clk", &gcc.mux, 0xC8 }, + { "gcc_pdm_ahb_clk", &gcc.mux, 0xC6 }, + { "gcc_pdm_xo4_clk", &gcc.mux, 0xC7 }, + { "gcc_qmip_camera_nrt_ahb_clk", &gcc.mux, 0x62 }, + { "gcc_qmip_camera_rt_ahb_clk", &gcc.mux, 0x63 }, + { "gcc_qmip_disp_ahb_clk", &gcc.mux, 0x6B }, + { "gcc_qmip_gpu_ahb_clk", &gcc.mux, 0x176 }, + { "gcc_qmip_pcie_ahb_clk", &gcc.mux, 0x132 }, + { "gcc_qmip_video_cv_cpu_ahb_clk", &gcc.mux, 0x73 }, + { "gcc_qmip_video_cvp_ahb_clk", &gcc.mux, 0x7 }, + { "gcc_qmip_video_v_cpu_ahb_clk", &gcc.mux, 0x72 }, + { "gcc_qmip_video_vcodec_ahb_clk", &gcc.mux, 0x71 }, + { "gcc_qupv3_i2c_core_clk", &gcc.mux, 0xA2 }, + { "gcc_qupv3_i2c_s0_clk", &gcc.mux, 0xA3 }, + { "gcc_qupv3_i2c_s1_clk", &gcc.mux, 0xA4 }, + { "gcc_qupv3_i2c_s2_clk", &gcc.mux, 0xA5 }, + { "gcc_qupv3_i2c_s3_clk", &gcc.mux, 0xA6 }, + { "gcc_qupv3_i2c_s4_clk", &gcc.mux, 0xA7 }, + { "gcc_qupv3_i2c_s5_clk", &gcc.mux, 0xA8 }, + { "gcc_qupv3_i2c_s6_clk", &gcc.mux, 0xA9 }, + { "gcc_qupv3_i2c_s7_clk", &gcc.mux, 0xAA }, + { "gcc_qupv3_i2c_s8_clk", &gcc.mux, 0xAB }, + { "gcc_qupv3_i2c_s9_clk", &gcc.mux, 0xAC }, + { "gcc_qupv3_i2c_s_ahb_clk", &gcc.mux, 0xA1 }, + { "gcc_qupv3_wrap1_core_2x_clk", &gcc.mux, 0xB }, + { "gcc_qupv3_wrap1_core_clk", &gcc.mux, 0xAF }, + { "gcc_qupv3_wrap1_s0_clk", &gcc.mux, 0xB2 }, + { "gcc_qupv3_wrap1_s1_clk", &gcc.mux, 0xB3 }, + { "gcc_qupv3_wrap1_s2_clk", &gcc.mux, 0xB4 }, + { "gcc_qupv3_wrap1_s3_clk", &gcc.mux, 0xB5 }, + { "gcc_qupv3_wrap1_s4_clk", &gcc.mux, 0xB6 }, + { "gcc_qupv3_wrap1_s5_clk", &gcc.mux, 0xB7 }, + { "gcc_qupv3_wrap1_s6_clk", &gcc.mux, 0xB8 }, + { "gcc_qupv3_wrap1_s7_clk", &gcc.mux, 0xB9 }, + { "gcc_qupv3_wrap2_core_2x_clk", &gcc.mux, 0xBD }, + { "gcc_qupv3_wrap2_core_clk", &gcc.mux, 0xBC }, + { "gcc_qupv3_wrap2_s0_clk", &gcc.mux, 0xBE }, + { "gcc_qupv3_wrap2_s1_clk", &gcc.mux, 0xBF }, + { "gcc_qupv3_wrap2_s2_clk", &gcc.mux, 0xC }, + { "gcc_qupv3_wrap2_s3_clk", &gcc.mux, 0xC1 }, + { "gcc_qupv3_wrap2_s4_clk", &gcc.mux, 0xC2 }, + { "gcc_qupv3_wrap2_s5_clk", &gcc.mux, 0xC3 }, + { "gcc_qupv3_wrap2_s6_clk", &gcc.mux, 0xC4 }, + { "gcc_qupv3_wrap2_s7_clk", &gcc.mux, 0xC5 }, + { "gcc_qupv3_wrap_1_m_ahb_clk", &gcc.mux, 0xAD }, + { "gcc_qupv3_wrap_1_s_ahb_clk", &gcc.mux, 0xAE }, + { "gcc_qupv3_wrap_2_m_ahb_clk", &gcc.mux, 0xBA }, + { "gcc_qupv3_wrap_2_s_ahb_clk", &gcc.mux, 0xBB }, + { "gcc_sdcc2_ahb_clk", &gcc.mux, 0x9C }, + { "gcc_sdcc2_apps_clk", &gcc.mux, 0x9B }, + { "gcc_sdcc4_ahb_clk", &gcc.mux, 0x9F }, + { "gcc_sdcc4_apps_clk", &gcc.mux, 0x9E }, + { "gcc_ufs_phy_ahb_clk", &gcc.mux, 0x148 }, + { "gcc_ufs_phy_axi_clk", &gcc.mux, 0x147 }, + { "gcc_ufs_phy_ice_core_clk", &gcc.mux, 0x14E }, + { "gcc_ufs_phy_phy_aux_clk", &gcc.mux, 0x14F }, + { "gcc_ufs_phy_rx_symbol_0_clk", &gcc.mux, 0x14A }, + { "gcc_ufs_phy_rx_symbol_1_clk", &gcc.mux, 0x15 }, + { "gcc_ufs_phy_tx_symbol_0_clk", &gcc.mux, 0x149 }, + { "gcc_ufs_phy_unipro_core_clk", &gcc.mux, 0x14D }, + { "gcc_usb30_prim_master_clk", &gcc.mux, 0x8E }, + { "gcc_usb30_prim_mock_utmi_clk", &gcc.mux, 0x9 }, + { "gcc_usb30_prim_sleep_clk", &gcc.mux, 0x8F }, + { "gcc_usb3_prim_phy_aux_clk", &gcc.mux, 0x91 }, + { "gcc_usb3_prim_phy_com_aux_clk", &gcc.mux, 0x92 }, + { "gcc_usb3_prim_phy_pipe_clk", &gcc.mux, 0x93 }, + { "gcc_video_ahb_clk", &gcc.mux, 0x6F }, + { "gcc_video_axi0_clk", &gcc.mux, 0x74 }, + { "gcc_video_axi1_clk", &gcc.mux, 0x75 }, + { "gcc_video_xo_clk", &gcc.mux, 0x76 }, + { "measure_only_cnoc_clk", &gcc.mux, 0x17 }, + { "measure_only_ipa_2x_clk", &gcc.mux, 0x161 }, + { "measure_only_memnoc_clk", &gcc.mux, 0xF7 }, + { "measure_only_snoc_clk", &gcc.mux, 0xB }, + { "pcie_0_pipe_clk", &gcc.mux, 0x13A }, + { "pcie_1_phy_aux_clk", &gcc.mux, 0x145 }, + { "pcie_1_pipe_clk", &gcc.mux, 0x144 }, + { "ufs_phy_rx_symbol_0_clk", &gcc.mux, 0x14C }, + { "ufs_phy_rx_symbol_1_clk", &gcc.mux, 0x152 }, + { "ufs_phy_tx_symbol_0_clk", &gcc.mux, 0x14B }, + { "usb3_phy_wrapper_gcc_usb30_pipe_clk", &gcc.mux, 0x97 }, + + { "gpu_cc_ahb_clk", &gpu_cc, 0x16 }, + { "gpu_cc_crc_ahb_clk", &gpu_cc, 0x17 }, + { "gpu_cc_cx_ff_clk", &gpu_cc, 0x2 }, + { "gpu_cc_cx_gmu_clk", &gpu_cc, 0x1D }, + { "gpu_cc_cxo_aon_clk", &gpu_cc, 0xB }, + { "gpu_cc_cxo_clk", &gpu_cc, 0x1E }, + { "gpu_cc_demet_clk", &gpu_cc, 0xD }, + { "gpu_cc_freq_measure_clk", &gpu_cc, 0xC }, + { "gpu_cc_gx_ff_clk", &gpu_cc, 0x13 }, + { "gpu_cc_gx_gfx3d_rdvm_clk", &gpu_cc, 0x15 }, + { "gpu_cc_gx_gmu_clk", &gpu_cc, 0x12 }, + { "gpu_cc_gx_vsense_clk", &gpu_cc, 0xF }, + { "gpu_cc_hub_aon_clk", &gpu_cc, 0x2D }, + { "gpu_cc_hub_cx_int_clk", &gpu_cc, 0x1F }, + { "gpu_cc_memnoc_gfx_clk", &gpu_cc, 0x21 }, + { "gpu_cc_mnd1x_0_gfx3d_clk", &gpu_cc, 0x28 }, + { "gpu_cc_mnd1x_1_gfx3d_clk", &gpu_cc, 0x29 }, + { "gpu_cc_sleep_clk", &gpu_cc, 0x1B }, + { "measure_only_gpu_cc_cx_gfx3d_clk", &gpu_cc, 0x24 }, + { "measure_only_gpu_cc_cx_gfx3d_slv_clk", &gpu_cc, 0x25 }, + { "measure_only_gpu_cc_gx_gfx3d_clk", &gpu_cc, 0xE }, + + { "video_cc_ahb_clk", &video_cc, 0x7 }, + { "video_cc_mvs0_clk", &video_cc, 0x3 }, + { "video_cc_mvs0c_clk", &video_cc, 0x1 }, + { "video_cc_mvs1_clk", &video_cc, 0x5 }, + { "video_cc_mvs1c_clk", &video_cc, 0x9 }, + { "video_cc_sleep_clk", &video_cc, 0xC }, + { "video_cc_xo_clk", &video_cc, 0xB }, {} };