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microcode.gmc
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; INSTRUCTION FETCHING STATES ------------------------------------------------------------------------------------------
fetch: ; mar <- [pc], t1 <- [pc]
pcoe, regr, marce, t1ce, anop, #f1
f1: ; mdr <- Mmem[[mar]], t2 <- [t1] + 1
maroe, ibread, mdrce, t1oe, coe, aadd, t2ce, #f2
f2: ; ir <- [mdr]
irce, mdroe, mdrget, anop, #decode
; SPECIAL DECODE STATE -------------------------------------------------------------------------------------------------
decode: ; pc <- [t2]
pcoe, regw, t2oe ; No next state, determined by decode ROM
; EXECUTION STATES -----------------------------------------------------------------------------------------------------
; FORM 1 & FORM 4 ------------------------------------------------------------------------------------------------------
; Begin execution for Form 1 & Form 4 instructions using registers ---------------------------------
form1r: ; t1 <- [rx]
$01, $02, $03, $04, $05, $06, $08 ; Opcodes
rx, regr, t1ce, anop, #ex1
ex1: ; t2 <- [t1] <op> [ry]
ry, regr, t1oe, aop, t2ce, frce, #t2_to_rd
t2_to_rd: ; rd <- [t2]
rd, regw, t2oe, anop, #fetch ; Execution complete
; Begin execution states for Form 1 & Form 4 instructions with immediate ---------------------------
form1i: ; t1 <- [rx]
$11, $12, $13, $14, $15, $16, $18 ; Opcodes
rx, regr, t1ce, anop, #ex2
ex2: ; t2 <- [t1] <op> uext(imm7)
ui7, t1oe, aop, t2ce, frce, #t2_to_rd
; FORM 2 ---------------------------------------------------------------------------------------------------------------
; Execution states for MOV and NOT instructions using registers ------------------------------------
movnotreg: ; t2 <- OP([r])
$07, $09
rx, regr, aop, t2ce, #t2_to_rd
; Execution state for MOV using an immediate value -------------------------------------------------
movi: ; rd <- uext(imm9)
$19
rd, regw, ui9, anop, #fetch
; Execution states for NOT using an immediate value ------------------------------------------------
noti: ; t2 <- !uext(imm9)
$17
ui9, t2ce, aop, #t2_to_rd
; Execution states for CMP using registers ---------------------------------------------------------
cmpr: ; t1 <- [rd]
$0a
rd, regr, t1ce, anop, #ex7
ex7: ; [t1] - [rx]
rx, regr, t1oe, asub, frce, #fetch
; Execution states for CMP using an immediate value ------------------------------------------------
cmpi: ; t1 <- [rd]
$1a
rd, regr, t1ce, anop, #ex9
ex9: ; [t1] - uext(imm9)
ui9, t1oe, asub, frce, #fetch
; FORM 3 ---------------------------------------------------------------------------------------------------------------
; Note that PC is already stored in t1 during any state following decode
; Execution states for LDR immediate address ------------------------------------------------------
ldria: ; t2 <- [t1] + sext(imm9)
$0c
t1oe, si9, aadd, t2ce, #ldaddr_and_read_to_rd
ldaddr_and_read_to_rd: ; mar <- [t2]
t2oe, marce, anop, #read_to_rd
read_to_rd: ; mdr <- Mmem[[mar]]
maroe, ibread, mdrce, anop, #ex10
ex10: ; rd <- [mdr]
rd, regw, mdroe, mdrget, anop, #fetch
; Execution states for LDR offset register ---------------------------------------------------------
ldror:
$0e
rx, regr, t1ce, anop, #ex11
ex11:
ry, regr, t1oe, aadd, t2ce, #ldaddr_and_read_to_rd
; Execution states for LDR offset immediate --------------------------------------------------------
ldroi:
$1e
rx, regr, t1ce, anop, #ex12
ex12:
si7, t1oe, aadd, t2ce, #ldaddr_and_read_to_rd
; Execution states for STR immediate address ------------------------------------------------------
stria: ; t2 <- [t1] + sext(imm9)
$1c
t1oe, si9, aadd, t2ce, #store_rd_at_addr
store_rd_at_addr: ; mar <- [t2]
t2oe, marce, anop, #ex13
ex13: ; mdr <- [rd]
rd, regr, mdrput, mdrce, anop, #ex14
ex14: ; Mmem[[mar]] <- [mdr]
mdroe, maroe, ibwrite, anop, #fetch
; Execution states for STR offset register --------------------------------------------------------
stror: ; t1 <- [rx]
$0d
rx, regr, t1ce, anop, #ex15
ex15: ; t2 <- [t1] + [ry]
ry, regr, t1oe, aadd, t2ce, #store_rd_at_addr
; Execution states for STR offset immediate --------------------------------------------------------
stroi: ; t1 <- [rx]
$1d
rx, regr, t1ce, anop, #ex16
ex16: ; t2 <- [t1] + sext(imm7)
t1oe, si7, aadd, t2ce, #store_rd_at_addr
; FORM 5 ---------------------------------------------------------------------------------------------------------------
lea: ; t2 <- [t1] + sext(imm9)
$1b
t1oe, si9, aadd, t2ce, #t2_to_rd
; BRANCHING ------------------------------------------------------------------------------------------------------------
; Checking condition truthiness requires its own state
; Execution states for Bcc -------------------------------------------------------------------------
check_cc:
$0f
froe, ccoe, anop, ctest, #branch ; Only move on to branch if condition code is true
branch: ; t2 <- [t1] + sext(imm7) iff cc
t1oe, si7, aadd, t2ce, #replace_pc
replace_pc: ; PC <- [t2]
pcoe, regw, t2oe, anop, #fetch
; Execution states for BLcc ------------------------------------------------------------------------
; Note that pc++ is already in t2 right after decode state
check_cc_bl:
$1f
froe, ccoe, anop, ctest, #link
link: ; LR <- [t2]
lroe, regw, t2oe, anop, #branch