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kiwi.gen.h
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// this file auto-generated by the e_cpu assembler -- edits will be overwritten
#ifndef _GEN_kiwi_H_
#define _GEN_kiwi_H_
// from assembler DEF directives:
#define GPS_CHANS 12 // DEFp 0xc
#define NUM_CMDS_OTHER 0 // DEFp 0x0
#define USE_SDR // DEFh 0x1
#define VAL_USE_SDR 1
#define USE_GPS // DEFh 0x1
#define VAL_USE_GPS 1
#define ARTIX_7A35 // DEFh 0x1
#define VAL_ARTIX_7A35 1
//#define ZYNQ_7007 // DEFh 0x0
#define VAL_ZYNQ_7007 0
#define FPGA_VER 1 // DEFp 0x1
#define FW_ID 20480 // DEFp 0x5000
#define ADC_BITS 14 // DEFp 0xe
#define DEFAULT_NSYNC 2 // DEFp 0x2
#define USE_GEN // DEFh 0x1
#define VAL_USE_GEN 1
#define USE_CPU_CTR // DEFh 0x1
#define VAL_USE_CPU_CTR 1
#define USE_LOGGER // DEFh 0x1
#define VAL_USE_LOGGER 1
#define USE_DEBUG // DEFh 0x1
#define VAL_USE_DEBUG 1
//#define USE_RX_SEQ // DEFh 0x0
#define VAL_USE_RX_SEQ 0
#define USE_VIVADO // DEFh 0x1
#define VAL_USE_VIVADO 1
#define SERIES_7 // DEFh 0x1
#define VAL_SERIES_7 1
//#define SPI_PUMP_CHECK // DEFh 0x0
#define VAL_SPI_PUMP_CHECK 0
//#define STACK_CHECK // DEFh 0x0
#define VAL_STACK_CHECK 0
//#define SND_SEQ_CHECK // DEFh 0x0
#define VAL_SND_SEQ_CHECK 0
//#define SND_TIMING_CK // DEFh 0x0
#define VAL_SND_TIMING_CK 0
#define FPGA_ID_RX4_WF4 0 // DEFp 0x0
#define FPGA_ID_RX8_WF2 1 // DEFp 0x1
#define FPGA_ID_RX3_WF3 2 // DEFp 0x2
#define FPGA_ID_RX14_WF0 3 // DEFp 0x3
#define FPGA_ID_OTHER 4 // DEFp 0x4
#define NUM_CMDS_BASE 14 // DEFp 0xe
#define NUM_CMDS_SDR 12 // DEFp 0xc
#define NUM_CMDS_GPS 16 // DEFp 0x10
#define NUM_CMDS 42 // DEFp 0x2a
#define SPI_32 // DEFh 0x1
#define VAL_SPI_32 1
#define SPIBUF_W 2048 // DEFp 0x800
#define SPIBUF_B 4096 // DEFp 0x1000
#define SPIBUF_BMAX 4094 // DEFp 0xffe
#define RX1_WIDE_DECIM 823 // DEFp 0x337
#define RX2_WIDE_DECIM 4 // DEFp 0x4
#define RX1_STD_DECIM 505 // DEFp 0x1f9
#define RX2_STD_DECIM 11 // DEFp 0xb
#define MAX_SND_RATE 20250 // DEFp 0x4f1a
#define MIN_SND_RATE 12000 // DEFp 0x2ee0
#define SND_RATE_3CH 20250 // DEFp 0x4f1a
#define SND_RATE_4CH 12000 // DEFp 0x2ee0
#define SND_RATE_8CH 12000 // DEFp 0x2ee0
#define SND_RATE_14CH 12000 // DEFp 0x2ee0
#define RX_DECIM_3CH 3292 // DEFp 0xcdc
#define RX_DECIM_4CH 5555 // DEFp 0x15b3
#define RX_DECIM_8CH 5555 // DEFp 0x15b3
#define RX_DECIM_14CH 5555 // DEFp 0x15b3
#define RXBUF_SIZE_3CH 16384 // DEFp 0x4000
#define RXBUF_SIZE_4CH 8192 // DEFp 0x2000
#define RXBUF_SIZE_8CH 16384 // DEFp 0x4000
#define RXBUF_SIZE_14CH 32768 // DEFp 0x8000
#define NRX_IQW 3 // DEFp 0x3
#define NRX_SPI 2047 // DEFp 0x7ff
#define NRX_OVHD 5 // DEFp 0x5
#define NRX_SAMPS_RPT 8 // DEFp 0x8
//#define USE_RX_CIC24 // DEFh 0x0
#define VAL_USE_RX_CIC24 0
#define RX1_BITS 22 // DEFp 0x16
#define RX2_BITS 18 // DEFp 0x12
#define RXO_BITS 24 // DEFp 0x18
#define RX1_STAGES 3 // DEFp 0x3
#define RX2_STAGES 5 // DEFp 0x5
#define MAX_ZOOM 14 // DEFp 0xe
#define NWF_FFT 8192 // DEFp 0x2000
#define NWF_IQW 2 // DEFp 0x2
#define NWF_NXFER 9 // DEFp 0x9
#define NWF_SAMPS 911 // DEFp 0x38f
#define NWF_SAMPS_RPT 50 // DEFp 0x32
#define NWF_SAMPS_LOOP 18 // DEFp 0x12
#define NWF_SAMPS_LOOP2 900 // DEFp 0x384
#define NWF_SAMPS_REM 11 // DEFp 0xb
#define USE_WF_1CIC // DEFh 0x1
#define VAL_USE_WF_1CIC 1
#define USE_WF_CIC24 // DEFh 0x1
#define VAL_USE_WF_CIC24 1
//#define USE_WF_MEM24 // DEFh 0x0
#define VAL_USE_WF_MEM24 0
//#define USE_WF_NEW // DEFh 0x0
#define VAL_USE_WF_NEW 0
#define WF1_STAGES 5 // DEFp 0x5
#define WF2_STAGES 5 // DEFp 0x5
#define WF1_BITS 24 // DEFp 0x18
#define WF2_BITS 24 // DEFp 0x18
#define WFO_BITS 16 // DEFp 0x10
#define WF_1CIC_MAXD 8192 // DEFp 0x2000
#define WF_2CIC_MAXD 0 // DEFp 0x0
#define MAX_GPS_CHANS 12 // DEFp 0xc
#define GPS_INTEG_BITS 20 // DEFp 0x14
#define GPS_REPL_BITS 18 // DEFp 0x12
#define MAX_NAV_BITS 128 // DEFp 0x80
#define GPS_RPT 32 // DEFp 0x20
#define GPS_SAMPS 256 // DEFp 0x100
#define GPS_SAMPS_RPT 32 // DEFp 0x20
#define GPS_SAMPS_LOOP 8 // DEFp 0x8
#define GPS_IQ_SAMPS 255 // DEFp 0xff
#define GPS_IQ_SAMPS_W 1020 // DEFp 0x3fc
#define L1_CODEBITS 10 // DEFp 0xa
#define L1_CODELEN 1023 // DEFp 0x3ff
#define E1B_MODE 2048 // DEFp 0x800
#define E1B_CODEBITS 12 // DEFp 0xc
#define E1B_CODELEN 4092 // DEFp 0xffc
#define E1B_CODE_XFERS 2 // DEFp 0x2
#define E1B_CODE_LOOP 2046 // DEFp 0x7fe
#define E1B_CODE_RPT 32 // DEFp 0x20
#define E1B_CODE_LOOP2 63 // DEFp 0x3f
#define E1B_CODE_LOOP3 2016 // DEFp 0x7e0
#define E1B_CODE_REM 30 // DEFp 0x1e
#define GET_CHAN_IQ 1 // DEFb 0x1
#define GET_SRQ 2 // DEFb 0x2
#define GET_SNAPSHOT 4 // DEFb 0x4
#define HOST_RX 8 // DEFb 0x8
#define GET_RX_SRQ 16 // DEFb 0x10
#define GET_CPU_CTR0 32 // DEFb 0x20
#define GET_CPU_CTR1 64 // DEFb 0x40
#define GET_CPU_CTR2 128 // DEFb 0x80
#define GET_CPU_CTR3 256 // DEFb 0x100
#define GET_STATUS 512 // DEFb 0x200
#define HOST_TX 1 // DEFb 0x1
#define SET_MASK 2 // DEFb 0x2
#define SET_CHAN 4 // DEFb 0x4
#define SET_CG_NCO 8 // DEFb 0x8
#define SET_LO_NCO 16 // DEFb 0x10
#define SET_SAT 32 // DEFb 0x20
#define SET_E1B_CODE 64 // DEFb 0x40
#define SET_PAUSE 128 // DEFb 0x80
#define SET_CTRL 1024 // DEFb 0x400
#define SET_RX_CHAN 1 // DEFb 0x1
#define SET_RX_FREQ 2 // DEFb 0x2
#define FREQ_L 4 // DEFb 0x4
#define SET_RX_NSAMPS 8 // DEFb 0x8
#define SET_GEN_FREQ 16 // DEFb 0x10
#define SET_GEN_ATTN 32 // DEFb 0x20
#define SET_WF_CHAN 64 // DEFb 0x40
#define SET_WF_FREQ 128 // DEFb 0x80
#define SET_WF_DECIM 256 // DEFb 0x100
#define WF_SAMPLER_RST 512 // DEFb 0x200
#define SET_CNT_MASK 1024 // DEFb 0x400
#define HOST_RST 1 // DEFb 0x1
#define HOST_RDY 2 // DEFb 0x2
#define GET_MEMORY 4 // DEFb 0x4
#define GPS_SAMPLER_RST 8 // DEFb 0x8
#define GET_GPS_SAMPLES 16 // DEFb 0x10
#define GET_LOG 32 // DEFb 0x20
#define PUT_LOG 64 // DEFb 0x40
#define LOG_RST 128 // DEFb 0x80
#define GET_RX_SAMP 1 // DEFb 0x1
#define RX_BUFFER_RST 2 // DEFb 0x2
#define RX_GET_BUF_CTR 4 // DEFb 0x4
#define SET_WF_CONTIN 8 // DEFb 0x8
#define GET_WF_SAMP_I 16 // DEFb 0x10
#define GET_WF_SAMP_Q 32 // DEFb 0x20
#define CLR_RX_OVFL 64 // DEFb 0x40
#define FREEZE_TOS 128 // DEFb 0x80
#define CPU_CTR_CLR 256 // DEFb 0x100
#define CPU_CTR_ENA 512 // DEFb 0x200
#define CPU_CTR_DIS 1024 // DEFb 0x400
#define WF_SAMP_RD_RST 1 // DEFb 0x1
#define WF_SAMP_WR_RST 2 // DEFb 0x2
#define WF_SAMP_CONTIN 4 // DEFb 0x4
#define WF_SAMP_SYNC 8 // DEFb 0x8
#define STAT_FPGA_ID 15 // DEFp 0xf
#define STAT_USER 240 // DEFp 0xf0
#define STAT_DNA_DATA 16 // DEFb 0x10
#define STAT_FPGA_VER 3840 // DEFp 0xf00
#define STAT_FW_ID 28672 // DEFp 0x7000
#define STAT_OVFL 32768 // DEFb 0x8000
#define CTRL_0001 1 // DEFb 0x1
#define CTRL_0002 2 // DEFb 0x2
#define CTRL_0004 4 // DEFb 0x4
#define CTRL_0008 8 // DEFb 0x8
#define CTRL_0010 16 // DEFb 0x10
#define CTRL_0020 32 // DEFb 0x20
#define CTRL_0040 64 // DEFb 0x40
#define CTRL_0080 128 // DEFb 0x80
#define CTRL_USE_GEN 1024 // DEFb 0x400
#define CTRL_OSC_EN 256 // DEFb 0x100
#define CTRL_EEPROM_WP 512 // DEFb 0x200
#define CTRL_UNUSED_OUT 512 // DEFb 0x200
#define CTRL_CMD_READY 2048 // DEFb 0x800
#define CTRL_SND_INTR 4096 // DEFb 0x1000
#define CTRL_DNA_READ 8192 // DEFb 0x2000
#define CTRL_DNA_SHIFT 16384 // DEFb 0x4000
#define CTRL_DNA_CLK 32768 // DEFb 0x8000
#endif