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Basic description of RISC-V32 I + M + ZIFENCEI ISA #698

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clebreto opened this issue Jan 24, 2024 · 0 comments · May be fixed by #781
Open
14 of 22 tasks

Basic description of RISC-V32 I + M + ZIFENCEI ISA #698

clebreto opened this issue Jan 24, 2024 · 0 comments · May be fixed by #781

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@clebreto
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clebreto commented Jan 24, 2024

Provide:

Docs:

  • riscv-spec-20191213.pdf
  • a cheatsheet
  • As decribed on the GCC RISC-V Options pages : General-purpose computing base extension, ‘g’ will expand to ‘i’, ‘m’, ‘a’, ‘f’, ‘d’, ‘zicsr’ and ‘zifencei’.
  • Assembly and execution of risc-v assembly code generated by jasminc compiler can be easily achieved on Macos arm M1 / M2 / M3 with the homebrew precompiled binaries of riscv-tools (compiler and spike) for Sonoma : bottle
./jasminc -arch=risc-v ./tests/success/risc-v/basics.jazz -o basics.s
/opt/homebrew/bin/riscv64-unknown-elf-gcc basics -o basics
/opt/homebrew/bin/spike pk basics

To dump objdump:

/opt/homebrew/bin/riscv64-unknown-elf-objdump execution.o -D

To check if the assembly code syntaxically valid with respect to risc-v isa, use /opt/homebrew/bin/riscv64-unknown-elf-as

@clebreto clebreto added this to the Jasmin for RISC-V milestone Jan 24, 2024
@clebreto clebreto changed the title Basic description of RISC-V ISA Basic description of RISC-V32I + G ISA Jan 24, 2024
@vbgl vbgl added the risc-v label Jan 24, 2024
@clebreto clebreto changed the title Basic description of RISC-V32I + G ISA Basic description of RISC-V32 I + M + ZIFENCEI ISA Apr 9, 2024
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