Epyc 7002 series

[heavyarms2112]

Hey there. I'm back again this time trying to work this on Epcy 7002 series chip. 7V12 to be precise.
Does the below info seem correct?

CPUs: 1
CPUID: 00830F10
Package Type: 4
P0 - Enabled - FID = 62 - DID = 8 - VID = 48 - Ratio = 24.50 - vCore = 1.10000
P1 - Enabled - FID = 64 - DID = A - VID = 58 - Ratio = 20.00 - vCore = 1.00000
P2 - Enabled - FID = 5A - DID = C - VID = 68 - Ratio = 15.00 - vCore = 0.90000
P3 - Disabled
P4 - Disabled
P5 - Disabled
P6 - Disabled
P7 - Disabled
C6 State - Package - Disabled
C6 State - Core - Enabled

Will changing p-state work on this?

[irusanov]

Since it is Zen2, it would probably not work, but I have no experience and access to server chips and can't be sure.
The output looks ok.

[heavyarms2112]

@irusanov could you help debugging? I have done this on zen2 chips and epyc chips infact. it works on 7502 QS/OEM, 7742 QS/OEM chips.

side note: you're saying it works on zen1 chips? cause I was able to do this on 7551p chip and that's a zen1

[irusanov]

@heavyarms2112 Yes, P-Sates were working fine on first gen (not sure if on all AGESA versions though) and that's what the original ZenStates-Linux was created for. Then they got replaced with hardware P-States and the script is kind of obsolete now.
You say that it was working on 7xx2 QS chips, so it might possible on the 7V12, but I have absolutely no experience with server SKUs.

If P-States work, then you should be able to verify it by monitoring the cpu frequency.

[heavyarms2112]

@heavyarms2112 Yes, P-Sates were working fine on first gen (not sure if on all AGESA versions though) and that's what the original ZenStates-Linux was created for. Then they got replaced with hardware P-States and the script is kind of obsolete now. You say that it was working on 7xx2 QS chips, so it might possible on the 7V12, but I have absolutely no experience with server SKUs.

If P-States work, then you should be able to verify it by monitoring the cpu frequency.

Yea I tried it. The changes aren't reflected in the actual clocks.
SMU test response is 1.
Even --oc-frequency and --oc-vid says applied but the core clocks drop to 400 MHz.

[irusanov]

Command IDs for setting OC frequency and VID are most probably different on EPYC.

[heavyarms2112]

Command IDs for setting OC frequency and VID are most probably different on EPYC.

actually it seems like the p-states doesn't change even with a successful set response

./zenstates.py -p 0 -f 66 -d 8 -v 48
Current P0: Enabled - FID = 62 - DID = 8 - VID = 48 - Ratio = 24.50 - vCore = 1.10000
Setting FID to 66
Setting DID to 8
Setting VID to 48
New P0: Enabled - FID = 66 - DID = 8 - VID = 48 - Ratio = 25.50 - vCore = 1.10000

root@e1:~/git_repos/zenstates-custom/ZenStates-Rome-ES# ./zenstates.py -l
P0 - Enabled - FID = 62 - DID = 8 - VID = 48 - Ratio = 24.50 - vCore = 1.10000
P1 - Enabled - FID = 64 - DID = A - VID = 58 - Ratio = 20.00 - vCore = 1.00000
P2 - Disabled
P3 - Disabled
P4 - Disabled
P5 - Disabled
P6 - Disabled
P7 - Disabled
C6 State - Package - Disabled
C6 State - Core - Enabled

[heavyarms2112]

had some success in changing some BIOS settings. Was able to get an all core boost of ~3100 MHz at low temps and around 3+ GHz sustained. So I guess like you said it's matter of figuring out what commands to be sent to the SMU.

Every 0.1s: grep "^[c]pu MHz" /proc/cpuinfo

cpu MHz : 3066.116
cpu MHz : 3055.833
cpu MHz : 3074.775
cpu MHz : 3056.080
cpu MHz : 3055.356
cpu MHz : 3055.144
cpu MHz : 3055.268
cpu MHz : 3063.107
cpu MHz : 3055.535
cpu MHz : 3055.558
cpu MHz : 2744.954
cpu MHz : 3055.700
cpu MHz : 3054.291