From 7cbac01bec4effab63ada99a540fecbd7efd06f0 Mon Sep 17 00:00:00 2001 From: "Dementiev, Roman" Date: Wed, 5 Oct 2022 09:07:51 +0200 Subject: [PATCH 1/4] address KW warning Change-Id: Iae7f9362957e8596b30032a8d67688378ff472b8 --- src/pcm-sensor-server.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/pcm-sensor-server.cpp b/src/pcm-sensor-server.cpp index c9523083..539eaf6a 100644 --- a/src/pcm-sensor-server.cpp +++ b/src/pcm-sensor-server.cpp @@ -164,6 +164,8 @@ std::ostream& operator<<( std::ostream& os, date const & d ) { return os; } +/* Not used right now + std::string read_ndctl_info( std::ofstream& logfile ) { int pipes[2]; if ( pipe( pipes ) == -1 ) { @@ -196,6 +198,8 @@ std::string read_ndctl_info( std::ofstream& logfile ) { return ndctl.str(); } +*/ + class HTTPServer; class SignalHandler { From 2632cf5b57cc3ada5f26d39c455685db815d2056 Mon Sep 17 00:00:00 2001 From: "Dementiev, Roman" Date: Wed, 12 Oct 2022 15:53:47 +0200 Subject: [PATCH 2/4] pcm-memory: option to enforce output flush Change-Id: Iae95d8416a2d37e8692ce74dd862cf017d7b0c68 --- src/pcm-memory.cpp | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/pcm-memory.cpp b/src/pcm-memory.cpp index d2bf536f..5f119a2f 100644 --- a/src/pcm-memory.cpp +++ b/src/pcm-memory.cpp @@ -69,6 +69,7 @@ bool anyPmem(const ServerUncoreMemoryMetrics & metrics) } bool skipInactiveChannels = true; +bool enforceFlush = false; void print_help(const string & prog_name) { @@ -92,6 +93,7 @@ void print_help(const string & prog_name) cout << " -i[=number] | /i[=number] => allow to determine number of iterations\n"; cout << " -silent => silence information output and print only measurements\n"; cout << " -u => update measurements instead of printing new ones\n"; + cout << " -f | /f => enforce flushing output\n"; #ifdef _MSC_VER cout << " --uninstallDriver | --installDriver=> (un)install driver\n"; #endif @@ -1100,6 +1102,11 @@ int main(int argc, char * argv[]) print_update = true; continue; } + else if (check_argument_equals(*argv, { "-f", "/f" })) + { + enforceFlush = true; + continue; + } #ifdef _MSC_VER else if (check_argument_equals(*argv, {"--uninstallDriver"})) { @@ -1206,7 +1213,7 @@ int main(int argc, char * argv[]) mainLoop([&]() { - if(!csv) cout << flush; + if (enforceFlush || !csv) cout << flush; calibratedSleep(delay, sysCmd, mainLoop, m); From 947f77441781af70a8f941093511948499ab8a5e Mon Sep 17 00:00:00 2001 From: Thomas Willhalm Date: Tue, 18 Oct 2022 13:02:41 +0200 Subject: [PATCH 3/4] additional files that can be ignored --- .bdsignore.all | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.bdsignore.all b/.bdsignore.all index be8d9e7a..a5ff86ea 100644 --- a/.bdsignore.all +++ b/.bdsignore.all @@ -14,6 +14,7 @@ Intel_SSA My Inspector XE Results - pcm .gitignore .gitattributes +.github .*\.txt .*\.pdf .*\.docx @@ -35,3 +36,4 @@ My Inspector XE Results - pcm .cproject .project makefile +sources From fbd489e57c67d3a75fb2b5d2ce3a8d31d8728faf Mon Sep 17 00:00:00 2001 From: "Dementiev, Roman" Date: Tue, 18 Oct 2022 13:37:23 +0200 Subject: [PATCH 4/4] implement RPL support From the perfmon perspective RPL is ADL with different CPU models according to the latest https://download.01.org/perfmon/mapfile.csv Change-Id: I9a31586924ce12f136c233967285cf705a503bc3 --- src/bw.cpp | 21 ++++++++++++++++++++- src/bw.h | 12 +++++++++++- src/cpucounters.cpp | 30 +++++++++++++++++++++++++++--- src/cpucounters.h | 14 ++++++++++++-- 4 files changed, 70 insertions(+), 7 deletions(-) diff --git a/src/bw.cpp b/src/bw.cpp index 09779df1..dd03074e 100644 --- a/src/bw.cpp +++ b/src/bw.cpp @@ -102,6 +102,25 @@ uint64 ClientBW::getIoRequests() return mmioRange->read32(PCM_CLIENT_IMC_DRAM_IO_REQUESTS - PCM_CLIENT_IMC_EVENT_BASE); } +#define PCM_ADL_IMC_EVENT_BASE (0xd000) +#define PCM_ADL_IMC_DRAM_DATA_READS (0x858) +#define PCM_ADL_IMC_DRAM_DATA_WRITES (0x8A0) + +ADLClientBW::ADLClientBW() +{ + mmioRange = std::make_shared(getClientIMCStartAddr() + PCM_ADL_IMC_EVENT_BASE, 0x1000); +} + +uint64 ADLClientBW::getImcReads() +{ + return mmioRange->read32(PCM_ADL_IMC_DRAM_DATA_READS); +} + +uint64 ADLClientBW::getImcWrites() +{ + return mmioRange->read32(PCM_ADL_IMC_DRAM_DATA_WRITES); +} + #define PCM_SERVER_IMC_DRAM_DATA_READS (0x2290) #define PCM_SERVER_IMC_DRAM_DATA_WRITES (0x2298) #define PCM_SERVER_IMC_PMM_DATA_READS (0x22a0) @@ -179,4 +198,4 @@ uint64 ServerBW::getPMMWrites() return result; } -} // namespace pcm \ No newline at end of file +} // namespace pcm diff --git a/src/bw.h b/src/bw.h index 79dfaad6..8853b32f 100644 --- a/src/bw.h +++ b/src/bw.h @@ -41,6 +41,16 @@ namespace pcm { uint64 getImcWrites() override; }; + class ADLClientBW : public FreeRunningBWCounters + { + std::shared_ptr mmioRange; + public: + ADLClientBW(); + + uint64 getImcReads() override; + uint64 getImcWrites() override; + }; + class ClientBW : public FreeRunningBWCounters { std::shared_ptr mmioRange; @@ -70,4 +80,4 @@ class ServerBW uint64 getPMMWrites(); }; -} // namespace pcm \ No newline at end of file +} // namespace pcm diff --git a/src/cpucounters.cpp b/src/cpucounters.cpp index 189e8898..db5d4894 100644 --- a/src/cpucounters.cpp +++ b/src/cpucounters.cpp @@ -800,7 +800,8 @@ void PCM::initCStateSupportTables() case APOLLO_LAKE: case DENVERTON: case ADL: - case SNOWRIDGE: + case RPL: + case SNOWRIDGE: PCM_CSTATE_ARRAY(pkgCStateMsr, PCM_PARAM_PROTECT({0, 0, 0x3F8, 0, 0x3F9, 0, 0x3FA, 0, 0, 0, 0 }) ); case NEHALEM_EP: case NEHALEM: @@ -868,7 +869,8 @@ void PCM::initCStateSupportTables() case DENVERTON: PCM_SKL_PATH_CASES case ADL: - case SNOWRIDGE: + case RPL: + case SNOWRIDGE: case ICX: PCM_CSTATE_ARRAY(coreCStateMsr, PCM_PARAM_PROTECT({0, 0, 0, 0x3FC, 0, 0, 0x3FD, 0x3FE, 0, 0, 0}) ); case KNL: @@ -1507,6 +1509,7 @@ bool PCM::detectNominalFrequency() || cpu_model == SNOWRIDGE || cpu_model == KNL || cpu_model == ADL + || cpu_model == RPL || cpu_model == SKX || cpu_model == ICX ) ? (100000000ULL) : (133333333ULL); @@ -1637,9 +1640,16 @@ void PCM::initUncoreObjects() switch (cpu_model) { case TGL: - case ADL: + case ADL: // TGLClientBW works fine for ADL + case RPL: // TGLClientBW works fine for ADL clientBW = std::make_shared(); break; +/* Disabled since ADLClientBW requires 2x multiplier for BW on top + case ADL: + case RPL: + clientBW = std::make_shared(); + break; +*/ default: clientBW = std::make_shared(); } @@ -2377,6 +2387,7 @@ bool PCM::isCPUModelSupported(const int model_) || model_ == RKL || model_ == TGL || model_ == ADL + || model_ == RPL || model_ == SKX || model_ == ICX ); @@ -2414,6 +2425,11 @@ bool PCM::checkModel() case ADL_1: cpu_model = ADL; break; + case RPL_1: + case RPL_2: + case RPL_3: + cpu_model = RPL; + break; } if(!isCPUModelSupported((int)cpu_model)) @@ -2540,6 +2556,11 @@ PCM::ErrorCode PCM::program(const PCM::ProgramMode mode_, const void * parameter canUsePerf = false; if (!silent) std::cerr << "Installed Linux kernel perf does not support hardware top-down level-1 counters. Using direct PMU programming instead.\n"; } + if (canUsePerf && (cpu_model == ADL || cpu_model == RPL)) + { + canUsePerf = false; + if (!silent) std::cerr << "Linux kernel perf rejects an architectural event on your platform. Using direct PMU programming instead.\n"; + } if (canUsePerf == false && noMSRMode()) { @@ -2597,6 +2618,7 @@ PCM::ErrorCode PCM::program(const PCM::ProgramMode mode_, const void * parameter else switch ( cpu_model ) { case ADL: + case RPL: hybridAtomEventDesc[0].event_number = ARCH_LLC_MISS_EVTNR; hybridAtomEventDesc[0].umask_value = ARCH_LLC_MISS_UMASK; hybridAtomEventDesc[1].event_number = ARCH_LLC_REFERENCE_EVTNR; @@ -3889,6 +3911,8 @@ const char * PCM::getUArchCodename(const int32 cpu_model_param) const return "Tiger Lake"; case ADL: return "Alder Lake"; + case RPL: + return "Raptor Lake"; case SKX: if (cpu_model_param >= 0) { diff --git a/src/cpucounters.h b/src/cpucounters.h index 25ead6e8..a0c61b42 100644 --- a/src/cpucounters.h +++ b/src/cpucounters.h @@ -1159,6 +1159,7 @@ class PCM_API PCM switch (cpu_model) { case ADL: + case RPL: if (topology[coreID].core_type == TopologyEntry::Atom) { return std::make_pair(OFFCORE_RESPONSE_0_EVTNR, event + 1); @@ -1170,6 +1171,7 @@ class PCM_API PCM switch (cpu_model) { case ADL: // ADL big core (GLC) + case RPL: useGLCOCREvent = true; break; } @@ -1363,6 +1365,10 @@ class PCM_API PCM TGL_1 = 141, ADL = 151, ADL_1 = 154, + RPL = 0xb7, + RPL_1 = 0xba, + RPL_2 = 0xbf, + RPL_3 = 0xbe, BDX = 79, KNL = 87, SKL = 94, @@ -1551,6 +1557,7 @@ class PCM_API PCM switch (cpu_model) { case ADL: + case RPL: return 6; case SNOWRIDGE: return 4; @@ -1837,6 +1844,7 @@ class PCM_API PCM || cpu_model == PCM::SKX || cpu_model == PCM::ICX || cpu_model == PCM::ADL + || cpu_model == PCM::RPL ); } @@ -2061,6 +2069,8 @@ class PCM_API PCM || cpu_model == IVY_BRIDGE || cpu_model == HASWELL || cpu_model == BROADWELL + || cpu_model == ADL + || cpu_model == RPL || useSKLPath() ; } @@ -3319,7 +3329,7 @@ uint64 getL2CacheMisses(const CounterStateType & before, const CounterStateType auto pcm = PCM::getInstance(); if (pcm->isL2CacheMissesAvailable() == false) return 0ULL; const auto cpu_model = pcm->getCPUModel(); - if (pcm->useSkylakeEvents() || cpu_model == PCM::SNOWRIDGE || cpu_model == PCM::ADL) { + if (pcm->useSkylakeEvents() || cpu_model == PCM::SNOWRIDGE || cpu_model == PCM::ADL || cpu_model == PCM::RPL) { return after.Event[BasicCounterState::SKLL2MissPos] - before.Event[BasicCounterState::SKLL2MissPos]; } if (pcm->isAtom() || cpu_model == PCM::KNL) @@ -3414,7 +3424,7 @@ uint64 getL3CacheHitsSnoop(const CounterStateType & before, const CounterStateTy auto pcm = PCM::getInstance(); if (!pcm->isL3CacheHitsSnoopAvailable()) return 0; const auto cpu_model = pcm->getCPUModel(); - if (cpu_model == PCM::SNOWRIDGE || cpu_model == PCM::ADL) + if (cpu_model == PCM::SNOWRIDGE || cpu_model == PCM::ADL || cpu_model == PCM::RPL) { const int64 misses = getL3CacheMisses(before, after); const int64 refs = after.Event[BasicCounterState::ArchLLCRefPos] - before.Event[BasicCounterState::ArchLLCRefPos];