unsigned(r_blnd) => antialiased_red,

[AnttiLukats]

in viciv.hdl

          unsigned(r_blnd) => antialiased_red,
          unsigned(g_blnd) => antialiased_green,
          unsigned(b_blnd) => antialiased_blue

reported as bad VHDL syntax by Vviado synthesis

[gardners]

Please indicate the commit ID, and some more context would be helpful. Is
there more detail in the error message?

On Sat, Apr 9, 2016 at 5:58 PM, Antti Lukats [email protected]
wrote:

in viciv.hdl

      unsigned(r_blnd) => antialiased_red,
      unsigned(g_blnd) => antialiased_green,
      unsigned(b_blnd) => antialiased_blue

reported as bad VHDL syntax by Vviado synthesis

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#48

[gardners]

This one might be fixable by changing them to something like:

r_blnd => std_logic_vector(antialiased_red)

Otherwise, you will need to harmonise the types somehow.

[pmprog]

I got my board, your change results in the following error

[Synth 8-959] output designator r_blnd cannot contain an actual type-conversion ["/home/user/Code/c65gs/viciv.vhdl":1107]

I also had to comment out
use work.version.all;
from uart_monitor.vhdl, as it was saying it didn't exist

[gardners]

Hello,

version.vhdl is generated by running the make file first: it generates
version strings based on the git commit ID.

As for the Vivado error, I'm not sure off the top of my head what the
correct Vivado-compatible solution is there. Some research will probably
be required.

Paul.

On Mon, Apr 11, 2016 at 12:57 AM, Marq Watkin [email protected]
wrote:

I got my board, your change results in the following error

[Synth 8-959] output designator r_blnd cannot contain an actual type-conversion ["/home/user/Code/c65gs/viciv.vhdl":1107]

I also had to comment out
use work.version.all;
from uart_monitor.vhdl, as it was saying it didn't exist

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#48 (comment)

[AnttiLukats]

I have to say that I was VERY surprised to see that code, see it would never come to my mind to try to-do type type conversion on the left side of => in the port map... from my head I would have assumed it is truly illegal... it really wonders me that ISE eats that... well it does, and vivado does not...

i can commit fix later, but description HOWTO

1. add 3 signals
2. do type conversion outside the port map
3. assign in the port map converted signal

antialiased_red <= unsigned(antialiased_red_from_blender);
antialiased_green <= unsigned(antialiased_green_from_blender);
antialiased_blue <= unsigned(antialiased_blue_from_blender);

antialiasblender: component alpha_blend_top
port map (clk1x => pixelclock,
--snip
r_blnd => antialiased_red_from_blender,
g_blnd => antialiased_green_from_blender,
b_blnd => antialiased_blue_from_blender);

I know, I know this solution uses 6 more VHDL code lines than the original code :(

But it truly fixes the issue.

[gardners]

Hello,

Oh well. If 6 extra lines is all that is required, then this is no big
problem.

Paul.

On Sat, Apr 16, 2016 at 5:12 AM, Antti Lukats [email protected]
wrote:

I have to say that I was VERY surprised to see that code, see it would
never come to my mind to try to-do type type conversion on the left side of
=> in the port map... from my head I would have assumed it is truly
illegal... it really wonders me that ISE eats that... well it does, and
vivado does not...

i can commit fix later, but description HOWTO

1. add 3 signals
2. do type conversion outside the port map
3. assign in the port map converted signal

antialiased_red <= unsigned(antialiased_red_from_blender);
antialiased_green <= unsigned(antialiased_green_from_blender);
antialiased_blue <= unsigned(antialiased_blue_from_blender);

antialiasblender: component alpha_blend_top
port map (clk1x => pixelclock,
--snip
r_blnd => antialiased_red_from_blender,
g_blnd => antialiased_green_from_blender,
b_blnd => antialiased_blue_from_blender);

I know, I know this solution uses 6 more VHDL code lines than the original
code :(

But it truly fixes the issue.

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#48 (comment)