diff --git a/.gitignore b/.gitignore index f5ad955..5119f27 100644 --- a/.gitignore +++ b/.gitignore @@ -2,3 +2,4 @@ *.swp *.pyc *.out +modelsim.ini diff --git a/sim/Makefile b/sim/Makefile index 4de2917..de24d0f 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -1,413 +1,20 @@ -# Generated by vmake version 10.3d +ifneq (,$(findstring Microsoft,$(shell uname -r))) + vsim = vsim.exe +else + vsim = vsim +endif -# Define path to each library -LIB_STD = /opt/altera/15.0/modelsim_ase/linuxaloem/../std -LIB_IEEE = /opt/altera/15.0/modelsim_ase/linuxaloem/../ieee -LIB_WORK = /home/flozzone/repos/uni/DDCA/sim/work +compile: + $(vsim) -c -do "do compile.do;quit -f" -# Define path to each design unit -IEEE__std_logic_1164 = $(LIB_IEEE)/_lib.qdb -STD__textio = $(LIB_STD)/_lib.qdb -IEEE__numeric_std = $(LIB_IEEE)/_lib.qdb -WORK__wb__rtl = $(LIB_WORK)/_lib.qdb -WORK__wb = $(LIB_WORK)/_lib.qdb -WORK__txt_util__body = $(LIB_WORK)/_lib.qdb -WORK__txt_util = $(LIB_WORK)/_lib.qdb -WORK__testbench_util_pkg__body = $(LIB_WORK)/_lib.qdb -WORK__testbench_util_pkg = $(LIB_WORK)/_lib.qdb -WORK__sync_pkg = $(LIB_WORK)/_lib.qdb -WORK__sync__beh = $(LIB_WORK)/_lib.qdb -WORK__sync = $(LIB_WORK)/_lib.qdb -WORK__serial_port_wrapper__behavior = $(LIB_WORK)/_lib.qdb -WORK__serial_port_wrapper = $(LIB_WORK)/_lib.qdb -WORK__serial_port_transmitter_pkg = $(LIB_WORK)/_lib.qdb -WORK__serial_port_transmitter__beh = $(LIB_WORK)/_lib.qdb -WORK__serial_port_transmitter = $(LIB_WORK)/_lib.qdb -WORK__serial_port_testbench__beh = $(LIB_WORK)/_lib.qdb -WORK__serial_port_testbench = $(LIB_WORK)/_lib.qdb -WORK__serial_port_receiver_pkg = $(LIB_WORK)/_lib.qdb -WORK__serial_port_receiver__beh = $(LIB_WORK)/_lib.qdb -WORK__serial_port_receiver = $(LIB_WORK)/_lib.qdb -WORK__serial_port_pkg = $(LIB_WORK)/_lib.qdb -WORK__serial_port__serial_port_struc = $(LIB_WORK)/_lib.qdb -WORK__serial_port = $(LIB_WORK)/_lib.qdb -WORK__regfile_tb__arch = $(LIB_WORK)/_lib.qdb -WORK__regfile_tb = $(LIB_WORK)/_lib.qdb -WORK__regfile__rtl = $(LIB_WORK)/_lib.qdb -WORK__regfile = $(LIB_WORK)/_lib.qdb -WORK__ram_pkg = $(LIB_WORK)/_lib.qdb -WORK__pll__syn = $(LIB_WORK)/_lib.qdb -WORK__pll = $(LIB_WORK)/_lib.qdb -WORK__pipeline__rtl = $(LIB_WORK)/_lib.qdb -WORK__pipeline = $(LIB_WORK)/_lib.qdb -WORK__op_pack = $(LIB_WORK)/_lib.qdb -WORK__ocram_altera__syn = $(LIB_WORK)/_lib.qdb -WORK__ocram_altera = $(LIB_WORK)/_lib.qdb -WORK__mimi__rtl = $(LIB_WORK)/_lib.qdb -WORK__mimi = $(LIB_WORK)/_lib.qdb -WORK__memu_tb__arch = $(LIB_WORK)/_lib.qdb -WORK__memu_tb = $(LIB_WORK)/_lib.qdb -WORK__memu__rtl = $(LIB_WORK)/_lib.qdb -WORK__memu = $(LIB_WORK)/_lib.qdb -WORK__mem__rtl = $(LIB_WORK)/_lib.qdb -WORK__mem = $(LIB_WORK)/_lib.qdb -WORK__math_pkg__body = $(LIB_WORK)/_lib.qdb -WORK__math_pkg = $(LIB_WORK)/_lib.qdb -WORK__level1_tb__arch = $(LIB_WORK)/_lib.qdb -WORK__level1_tb = $(LIB_WORK)/_lib.qdb -WORK__jmpu__rtl = $(LIB_WORK)/_lib.qdb -WORK__jmpu = $(LIB_WORK)/_lib.qdb -WORK__imem_altera__syn = $(LIB_WORK)/_lib.qdb -WORK__imem_altera = $(LIB_WORK)/_lib.qdb -WORK__fwd__rtl = $(LIB_WORK)/_lib.qdb -WORK__fwd = $(LIB_WORK)/_lib.qdb -WORK__fifo_1c1r1w__mixed = $(LIB_WORK)/_lib.qdb -WORK__fifo_1c1r1w = $(LIB_WORK)/_lib.qdb -WORK__fetch__rtl = $(LIB_WORK)/_lib.qdb -WORK__fetch = $(LIB_WORK)/_lib.qdb -WORK__exec_tb__arch = $(LIB_WORK)/_lib.qdb -WORK__exec_tb = $(LIB_WORK)/_lib.qdb -WORK__exec__rtl = $(LIB_WORK)/_lib.qdb -WORK__exec = $(LIB_WORK)/_lib.qdb -WORK__dp_ram_1c1r1w__beh = $(LIB_WORK)/_lib.qdb -WORK__dp_ram_1c1r1w = $(LIB_WORK)/_lib.qdb -WORK__decode__rtl = $(LIB_WORK)/_lib.qdb -WORK__decode = $(LIB_WORK)/_lib.qdb -WORK__ctrl__rtl = $(LIB_WORK)/_lib.qdb -WORK__ctrl = $(LIB_WORK)/_lib.qdb -WORK__core_tb__rtl = $(LIB_WORK)/_lib.qdb -WORK__core_tb = $(LIB_WORK)/_lib.qdb -WORK__core_pack = $(LIB_WORK)/_lib.qdb -WORK__core__rtl = $(LIB_WORK)/_lib.qdb -WORK__core = $(LIB_WORK)/_lib.qdb -WORK__alu_tb__arch = $(LIB_WORK)/_lib.qdb -WORK__alu_tb = $(LIB_WORK)/_lib.qdb -WORK__alu__rtl = $(LIB_WORK)/_lib.qdb -WORK__alu = $(LIB_WORK)/_lib.qdb -VCOM = vcom -VLOG = vlog -VOPT = vopt -SCCOM = sccom - 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Try ```make compile``` (If this works go straight to step 2, If not do Substeps) + 1. If it does not compile alter ```sim/compile.do``` to match your project files + 2. Try ```make clean``` then go to Step 1 +2. Use ```make level1``` to start the test and run it! :) + +*The Output gets written to ```report.txt``` and only the summary is shown in the Terminal.* \ No newline at end of file diff --git a/sim/compile.do b/sim/compile.do new file mode 100644 index 0000000..29381f2 --- /dev/null +++ b/sim/compile.do @@ -0,0 +1,45 @@ +vlib work +vmap work work + +vcom -reportprogress 300 -work work -2008 -explicit -check_synthesis -O0 -check_synthesis ../src/core_pack.vhd +vcom -reportprogress 300 -work work -2008 -explicit -check_synthesis -O0 -check_synthesis ../src/op_pack.vhd +vcom -reportprogress 300 -work work -2008 -explicit -check_synthesis -O0 -check_synthesis ../src/ctrl.vhd +vcom -reportprogress 300 -work work -2008 -explicit -check_synthesis -O0 -check_synthesis ../src/regfile.vhd +vcom -reportprogress 300 -work work -2008 -explicit -check_synthesis -O0 -check_synthesis ../src/decode.vhd +vcom -reportprogress 300 -work work -2002 -explicit ../src/ram/src/dp_ram_1c1r1w.vhd +vcom -reportprogress 300 -work work -2002 -explicit ../src/ram/src/dp_ram_1c1r1w_beh.vhd +vcom -reportprogress 300 -work work -2008 -explicit -check_synthesis -O0 -check_synthesis ../src/alu.vhd +vcom -reportprogress 300 -work work -2008 -explicit -check_synthesis -O0 -check_synthesis ../src/exec.vhd +vcom -reportprogress 300 -work work -2008 -explicit -check_synthesis -O0 -check_synthesis ../src/imem_altera.vhd +vcom -reportprogress 300 -work work -2008 -explicit -check_synthesis -O0 -check_synthesis ../src/fetch.vhd +vcom -reportprogress 300 -work work -2002 -explicit ../src/math/src/math_pkg.vhd +vcom -reportprogress 300 -work work -2002 -explicit ../src/ram/src/ram_pkg.vhd +vcom -reportprogress 300 -work work -2002 -explicit ../src/ram/src/fifo_1c1r1w.vhd +vcom -reportprogress 300 -work work -2002 -explicit ../src/ram/src/fifo_1c1r1w_mixed.vhd +vcom -reportprogress 300 -work work -2008 -explicit -check_synthesis -O0 -check_synthesis ../src/fwd.vhd +vcom -reportprogress 300 -work work -2008 -explicit -check_synthesis -O0 -check_synthesis ../src/jmpu.vhd +vcom -reportprogress 300 -work work -2008 -explicit -check_synthesis -O0 -check_synthesis ../src/memu.vhd +vcom -reportprogress 300 -work work -2008 -explicit -check_synthesis -O0 -check_synthesis ../src/mem.vhd +vcom -reportprogress 300 -work work -2008 -explicit -check_synthesis -O0 -check_synthesis ../src/pll_altera.vhd +vcom -reportprogress 300 -work work -2008 -explicit -check_synthesis -O0 -check_synthesis ../src/ocram_altera.vhd +vcom -reportprogress 300 -work work -2008 -explicit -check_synthesis -O0 -check_synthesis ../src/wb.vhd +vcom -reportprogress 300 -work work -2008 -explicit -check_synthesis -O0 -check_synthesis ../src/pipeline.vhd +vcom -reportprogress 300 -work work -2002 -explicit ../src/synchronizer/src/sync_pkg.vhd +vcom -reportprogress 300 -work work -2002 -explicit ../src/synchronizer/src/sync.vhd +vcom -reportprogress 300 -work work -2002 -explicit ../src/synchronizer/src/sync_beh.vhd +vcom -reportprogress 300 -work work -2002 -explicit ../src/serial_port/src/serial_port_receiver_pkg.vhd +vcom -reportprogress 300 -work work -2002 -explicit ../src/serial_port/src/serial_port_receiver.vhd +vcom -reportprogress 300 -work work -2002 -explicit ../src/serial_port/src/serial_port_receiver_beh.vhd +vcom -reportprogress 300 -work work -2002 -explicit ../src/serial_port/src/serial_port_transmitter_pkg.vhd +vcom -reportprogress 300 -work work -2002 -explicit ../src/serial_port/src/serial_port_transmitter.vhd +vcom -reportprogress 300 -work work -2002 -explicit ../src/serial_port/src/serial_port_transmitter_beh.vhd +vcom -reportprogress 300 -work work -2002 -explicit ../src/serial_port/src/serial_port_pkg.vhd +vcom -reportprogress 300 -work work -2002 -explicit ../src/serial_port/src/serial_port.vhd +vcom -reportprogress 300 -work work -2002 -explicit ../src/serial_port/src/serial_port_beh.vhd +vcom -reportprogress 300 -work work -2002 -explicit ../src/testbench_util/src/testbench_util_pkg.vhd +vcom -reportprogress 300 -work work -2002 -explicit ../src/serial_port/src/serial_port_testbench.vhd +vcom -reportprogress 300 -work work -2008 -explicit -check_synthesis -O0 -check_synthesis ../src/serial_port_wrapper.vhd +vcom -reportprogress 300 -work work -2002 -explicit txt_util.vhd +vcom -reportprogress 300 -work work -2008 -explicit -check_synthesis -O0 -check_synthesis ../src/core.vhd +vcom -reportprogress 300 -work work -2008 -explicit -check_synthesis -O0 -check_synthesis ../src/mimi.vhd +vcom -reportprogress 300 -work work -2002 -explicit level1_tb.vhd \ No newline at end of file diff --git a/src/testbenches/level1_tb.vhd b/sim/level1_tb.vhd similarity index 100% rename from src/testbenches/level1_tb.vhd rename to sim/level1_tb.vhd diff --git a/sim/testrunner.do b/sim/testrunner.do deleted file mode 100644 index a6f4d1b..0000000 --- a/sim/testrunner.do +++ /dev/null @@ -1,49 +0,0 @@ -# -# Test runner for testbenches -# - - -# USAGE: do testrunner.do TESTBENCH [SPECIFIC_DATA_FILE] -# EXAMPLE: do testrunner.do regfile -# EXAMPLE: do testrunner.do regfile test_001.do - -if { $argc == 0 } { - echo "testbench parameter missing" - echo "usage: do testrunner.do TESTBENCH \[SPECIFIC_DATA_FILE\]" - return -} - -set tb $1 -set data_path "testbench/$tb/data/" -set wave_path "testbench/$tb/wave.do" - -if { [file isdirectory $data_path] == 0 } { - echo "Directory at $data_path does not exist." - return -} - -if { $argc > 1 } { - set testfiles $data_path$2 - if { [file exists $testfiles] == 0 } { - puts "$specific does not exist" - return - } -} else { - set pattern "*" - set glob_pattern $data_path$pattern - set testfiles [lsort [glob $glob_pattern ] ] -} - -do util.do - -load_testbench ${tb} - -foreach file $testfiles { - echo "Running test $file" - - set filename [file rootname [lindex [file split $file] end]] - force testfile $filename - do $file - - run 20ns -} diff --git a/src/testbenches/txt_util.vhd b/sim/txt_util.vhd similarity index 96% rename from src/testbenches/txt_util.vhd rename to sim/txt_util.vhd index d42303b..e242858 100644 --- a/src/testbenches/txt_util.vhd +++ b/sim/txt_util.vhd @@ -1,586 +1,586 @@ -library ieee; -use ieee.std_logic_1164.all; -use std.textio.all; - - -package txt_util is - - -- prints a message to the screen - procedure print(text: string); - - -- prints the message when active - -- useful for debug switches - procedure print(active: boolean; text: string); - - -- converts std_logic into a character - function chr(sl: std_logic) return character; - - -- converts std_logic into a string (1 to 1) - function str(sl: std_logic) return string; - - -- converts std_logic_vector into a string (binary base) - function str(slv: std_logic_vector) return string; - - -- converts boolean into a string - function str(b: boolean) return string; - - -- converts an integer into a single character - -- (can also be used for hex conversion and other bases) - function chr(int: integer) return character; - - -- converts integer into string using specified base - function str(int: integer; base: integer) return string; - - -- converts integer to string, using base 10 - function str(int: integer) return string; - - -- convert std_logic_vector into a string in hex format - function hstr(slv: std_logic_vector) return string; - - - -- functions to manipulate strings - ----------------------------------- - - -- convert a character to upper case - function to_upper(c: character) return character; - - -- convert a character to lower case - function to_lower(c: character) return character; - - -- convert a string to upper case - function to_upper(s: string) return string; - - -- convert a string to lower case - function to_lower(s: string) return string; - - - - -- functions to convert strings into other formats - -------------------------------------------------- - - -- converts a character into std_logic - function to_std_logic(c: character) return std_logic; - - -- converts a string into std_logic_vector - function to_std_logic_vector(s: string) return std_logic_vector; - - - - -- file I/O - ----------- - - -- read variable length string from input file - procedure str_read(file in_file: TEXT; - res_string: out string); - - -- print string to a file and start new line - procedure print(file out_file: TEXT; - new_string: in string); - - -- print character to a file and start new line - procedure print(file out_file: TEXT; - char: in character); - -end txt_util; - - - - -package body txt_util is - - - - - -- prints text to the screen - - procedure print(text: string) is - variable msg_line: line; - begin - write(msg_line, text); - writeline(output, msg_line); - end print; - - - - - -- prints text to the screen when active - - procedure print(active: boolean; text: string) is - begin - if active then - print(text); - end if; - end print; - - - -- converts std_logic into a character - - function chr(sl: std_logic) return character is - variable c: character; - begin - case sl is - when 'U' => c:= 'U'; - when 'X' => c:= 'X'; - when '0' => c:= '0'; - when '1' => c:= '1'; - when 'Z' => c:= 'Z'; - when 'W' => c:= 'W'; - when 'L' => c:= 'L'; - when 'H' => c:= 'H'; - when '-' => c:= '-'; - end case; - return c; - end chr; - - - - -- converts std_logic into a string (1 to 1) - - function str(sl: std_logic) return string is - variable s: string(1 to 1); - begin - s(1) := chr(sl); - return s; - end str; - - - - -- converts std_logic_vector into a string (binary base) - -- (this also takes care of the fact that the range of - -- a string is natural while a std_logic_vector may - -- have an integer range) - - function str(slv: std_logic_vector) return string is - variable result : string (1 to slv'length); - variable r : integer; - begin - r := 1; - for i in slv'range loop - result(r) := chr(slv(i)); - r := r + 1; - end loop; - return result; - end str; - - - function str(b: boolean) return string is - - begin - if b then - return "true"; - else - return "false"; - end if; - end str; - - - -- converts an integer into a character - -- for 0 to 9 the obvious mapping is used, higher - -- values are mapped to the characters A-Z - -- (this is usefull for systems with base > 10) - -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) - - function chr(int: integer) return character is - variable c: character; - begin - case int is - when 0 => c := '0'; - when 1 => c := '1'; - when 2 => c := '2'; - when 3 => c := '3'; - when 4 => c := '4'; - when 5 => c := '5'; - when 6 => c := '6'; - when 7 => c := '7'; - when 8 => c := '8'; - when 9 => c := '9'; - when 10 => c := 'A'; - when 11 => c := 'B'; - when 12 => c := 'C'; - when 13 => c := 'D'; - when 14 => c := 'E'; - when 15 => c := 'F'; - when 16 => c := 'G'; - when 17 => c := 'H'; - when 18 => c := 'I'; - when 19 => c := 'J'; - when 20 => c := 'K'; - when 21 => c := 'L'; - when 22 => c := 'M'; - when 23 => c := 'N'; - when 24 => c := 'O'; - when 25 => c := 'P'; - when 26 => c := 'Q'; - when 27 => c := 'R'; - when 28 => c := 'S'; - when 29 => c := 'T'; - when 30 => c := 'U'; - when 31 => c := 'V'; - when 32 => c := 'W'; - when 33 => c := 'X'; - when 34 => c := 'Y'; - when 35 => c := 'Z'; - when others => c := '?'; - end case; - return c; - end chr; - - - - -- convert integer to string using specified base - -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) - - function str(int: integer; base: integer) return string is - - variable temp: string(1 to 10); - variable num: integer; - variable abs_int: integer; - variable len: integer := 1; - variable power: integer := 1; - - begin - - -- bug fix for negative numbers - abs_int := abs(int); - - num := abs_int; - - while num >= base loop -- Determine how many - len := len + 1; -- characters required - num := num / base; -- to represent the - end loop ; -- number. - - for i in len downto 1 loop -- Convert the number to - temp(i) := chr(abs_int/power mod base); -- a string starting - power := power * base; -- with the right hand - end loop ; -- side. - - -- return result and add sign if required - if int < 0 then - return '-'& temp(1 to len); - else - return temp(1 to len); - end if; - - end str; - - - -- convert integer to string, using base 10 - function str(int: integer) return string is - - begin - - return str(int, 10) ; - - end str; - - - - -- converts a std_logic_vector into a hex string. - function hstr(slv: std_logic_vector) return string is - variable hexlen: integer; - variable longslv : std_logic_vector(67 downto 0) := (others => '0'); - variable hex : string(1 to 16); - variable fourbit : std_logic_vector(3 downto 0); - begin - hexlen := (slv'left+1)/4; - if (slv'left+1) mod 4 /= 0 then - hexlen := hexlen + 1; - end if; - longslv(slv'left downto 0) := slv; - for i in (hexlen -1) downto 0 loop - fourbit := longslv(((i*4)+3) downto (i*4)); - case fourbit is - when "0000" => hex(hexlen -I) := '0'; - when "0001" => hex(hexlen -I) := '1'; - when "0010" => hex(hexlen -I) := '2'; - when "0011" => hex(hexlen -I) := '3'; - when "0100" => hex(hexlen -I) := '4'; - when "0101" => hex(hexlen -I) := '5'; - when "0110" => hex(hexlen -I) := '6'; - when "0111" => hex(hexlen -I) := '7'; - when "1000" => hex(hexlen -I) := '8'; - when "1001" => hex(hexlen -I) := '9'; - when "1010" => hex(hexlen -I) := 'A'; - when "1011" => hex(hexlen -I) := 'B'; - when "1100" => hex(hexlen -I) := 'C'; - when "1101" => hex(hexlen -I) := 'D'; - when "1110" => hex(hexlen -I) := 'E'; - when "1111" => hex(hexlen -I) := 'F'; - when "ZZZZ" => hex(hexlen -I) := 'z'; - when "UUUU" => hex(hexlen -I) := 'u'; - when "XXXX" => hex(hexlen -I) := 'x'; - when others => hex(hexlen -I) := '?'; - end case; - end loop; - return hex(1 to hexlen); - end hstr; - - - - -- functions to manipulate strings - ----------------------------------- - - - -- convert a character to upper case - - function to_upper(c: character) return character is - - variable u: character; - - begin - - case c is - when 'a' => u := 'A'; - when 'b' => u := 'B'; - when 'c' => u := 'C'; - when 'd' => u := 'D'; - when 'e' => u := 'E'; - when 'f' => u := 'F'; - when 'g' => u := 'G'; - when 'h' => u := 'H'; - when 'i' => u := 'I'; - when 'j' => u := 'J'; - when 'k' => u := 'K'; - when 'l' => u := 'L'; - when 'm' => u := 'M'; - when 'n' => u := 'N'; - when 'o' => u := 'O'; - when 'p' => u := 'P'; - when 'q' => u := 'Q'; - when 'r' => u := 'R'; - when 's' => u := 'S'; - when 't' => u := 'T'; - when 'u' => u := 'U'; - when 'v' => u := 'V'; - when 'w' => u := 'W'; - when 'x' => u := 'X'; - when 'y' => u := 'Y'; - when 'z' => u := 'Z'; - when others => u := c; - end case; - - return u; - - end to_upper; - - - -- convert a character to lower case - - function to_lower(c: character) return character is - - variable l: character; - - begin - - case c is - when 'A' => l := 'a'; - when 'B' => l := 'b'; - when 'C' => l := 'c'; - when 'D' => l := 'd'; - when 'E' => l := 'e'; - when 'F' => l := 'f'; - when 'G' => l := 'g'; - when 'H' => l := 'h'; - when 'I' => l := 'i'; - when 'J' => l := 'j'; - when 'K' => l := 'k'; - when 'L' => l := 'l'; - when 'M' => l := 'm'; - when 'N' => l := 'n'; - when 'O' => l := 'o'; - when 'P' => l := 'p'; - when 'Q' => l := 'q'; - when 'R' => l := 'r'; - when 'S' => l := 's'; - when 'T' => l := 't'; - when 'U' => l := 'u'; - when 'V' => l := 'v'; - when 'W' => l := 'w'; - when 'X' => l := 'x'; - when 'Y' => l := 'y'; - when 'Z' => l := 'z'; - when others => l := c; - end case; - - return l; - - end to_lower; - - - - -- convert a string to upper case - - function to_upper(s: string) return string is - - variable uppercase: string (s'range); - - begin - - for i in s'range loop - uppercase(i):= to_upper(s(i)); - end loop; - return uppercase; - - end to_upper; - - - - -- convert a string to lower case - - function to_lower(s: string) return string is - - variable lowercase: string (s'range); - - begin - - for i in s'range loop - lowercase(i):= to_lower(s(i)); - end loop; - return lowercase; - - end to_lower; - - - --- functions to convert strings into other types - - --- converts a character into a std_logic - -function to_std_logic(c: character) return std_logic is - variable sl: std_logic; - begin - case c is - when 'U' => - sl := 'U'; - when 'X' => - sl := 'X'; - when '0' => - sl := '0'; - when '1' => - sl := '1'; - when 'Z' => - sl := 'Z'; - when 'W' => - sl := 'W'; - when 'L' => - sl := 'L'; - when 'H' => - sl := 'H'; - when '-' => - sl := '-'; - when others => - sl := 'X'; - end case; - return sl; - end to_std_logic; - - --- converts a string into std_logic_vector - -function to_std_logic_vector(s: string) return std_logic_vector is - variable slv: std_logic_vector(s'high-s'low downto 0); - variable k: integer; -begin - k := s'high-s'low; - for i in s'range loop - slv(k) := to_std_logic(s(i)); - k := k - 1; - end loop; - return slv; -end to_std_logic_vector; - - - - - - ----------------- --- file I/O -- ----------------- - - - --- read variable length string from input file - -procedure str_read(file in_file: TEXT; - res_string: out string) is - - variable l: line; - variable c: character; - variable is_string: boolean; - - begin - - readline(in_file, l); - -- clear the contents of the result string - for i in res_string'range loop - res_string(i) := ' '; - end loop; - -- read all characters of the line, up to the length - -- of the results string - for i in res_string'range loop - read(l, c, is_string); - res_string(i) := c; - if not is_string then -- found end of line - exit; - end if; - end loop; - -end str_read; - - --- print string to a file -procedure print(file out_file: TEXT; - new_string: in string) is - - variable l: line; - - begin - - write(l, new_string); - writeline(out_file, l); - -end print; - - --- print character to a file and start new line -procedure print(file out_file: TEXT; - char: in character) is - - variable l: line; - - begin - - write(l, char); - writeline(out_file, l); - -end print; - - - --- appends contents of a string to a file until line feed occurs --- (LF is considered to be the end of the string) - -procedure str_write(file out_file: TEXT; - new_string: in string) is - begin - - for i in new_string'range loop - print(out_file, new_string(i)); - if new_string(i) = LF then -- end of string - exit; - end if; - end loop; - -end str_write; - - - - -end txt_util; - - - - +library ieee; +use ieee.std_logic_1164.all; +use std.textio.all; + + +package txt_util is + + -- prints a message to the screen + procedure print(text: string); + + -- prints the message when active + -- useful for debug switches + procedure print(active: boolean; text: string); + + -- converts std_logic into a character + function chr(sl: std_logic) return character; + + -- converts std_logic into a string (1 to 1) + function str(sl: std_logic) return string; + + -- converts std_logic_vector into a string (binary base) + function str(slv: std_logic_vector) return string; + + -- converts boolean into a string + function str(b: boolean) return string; + + -- converts an integer into a single character + -- (can also be used for hex conversion and other bases) + function chr(int: integer) return character; + + -- converts integer into string using specified base + function str(int: integer; base: integer) return string; + + -- converts integer to string, using base 10 + function str(int: integer) return string; + + -- convert std_logic_vector into a string in hex format + function hstr(slv: std_logic_vector) return string; + + + -- functions to manipulate strings + ----------------------------------- + + -- convert a character to upper case + function to_upper(c: character) return character; + + -- convert a character to lower case + function to_lower(c: character) return character; + + -- convert a string to upper case + function to_upper(s: string) return string; + + -- convert a string to lower case + function to_lower(s: string) return string; + + + + -- functions to convert strings into other formats + -------------------------------------------------- + + -- converts a character into std_logic + function to_std_logic(c: character) return std_logic; + + -- converts a string into std_logic_vector + function to_std_logic_vector(s: string) return std_logic_vector; + + + + -- file I/O + ----------- + + -- read variable length string from input file + procedure str_read(file in_file: TEXT; + res_string: out string); + + -- print string to a file and start new line + procedure print(file out_file: TEXT; + new_string: in string); + + -- print character to a file and start new line + procedure print(file out_file: TEXT; + char: in character); + +end txt_util; + + + + +package body txt_util is + + + + + -- prints text to the screen + + procedure print(text: string) is + variable msg_line: line; + begin + write(msg_line, text); + writeline(output, msg_line); + end print; + + + + + -- prints text to the screen when active + + procedure print(active: boolean; text: string) is + begin + if active then + print(text); + end if; + end print; + + + -- converts std_logic into a character + + function chr(sl: std_logic) return character is + variable c: character; + begin + case sl is + when 'U' => c:= 'U'; + when 'X' => c:= 'X'; + when '0' => c:= '0'; + when '1' => c:= '1'; + when 'Z' => c:= 'Z'; + when 'W' => c:= 'W'; + when 'L' => c:= 'L'; + when 'H' => c:= 'H'; + when '-' => c:= '-'; + end case; + return c; + end chr; + + + + -- converts std_logic into a string (1 to 1) + + function str(sl: std_logic) return string is + variable s: string(1 to 1); + begin + s(1) := chr(sl); + return s; + end str; + + + + -- converts std_logic_vector into a string (binary base) + -- (this also takes care of the fact that the range of + -- a string is natural while a std_logic_vector may + -- have an integer range) + + function str(slv: std_logic_vector) return string is + variable result : string (1 to slv'length); + variable r : integer; + begin + r := 1; + for i in slv'range loop + result(r) := chr(slv(i)); + r := r + 1; + end loop; + return result; + end str; + + + function str(b: boolean) return string is + + begin + if b then + return "true"; + else + return "false"; + end if; + end str; + + + -- converts an integer into a character + -- for 0 to 9 the obvious mapping is used, higher + -- values are mapped to the characters A-Z + -- (this is usefull for systems with base > 10) + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function chr(int: integer) return character is + variable c: character; + begin + case int is + when 0 => c := '0'; + when 1 => c := '1'; + when 2 => c := '2'; + when 3 => c := '3'; + when 4 => c := '4'; + when 5 => c := '5'; + when 6 => c := '6'; + when 7 => c := '7'; + when 8 => c := '8'; + when 9 => c := '9'; + when 10 => c := 'A'; + when 11 => c := 'B'; + when 12 => c := 'C'; + when 13 => c := 'D'; + when 14 => c := 'E'; + when 15 => c := 'F'; + when 16 => c := 'G'; + when 17 => c := 'H'; + when 18 => c := 'I'; + when 19 => c := 'J'; + when 20 => c := 'K'; + when 21 => c := 'L'; + when 22 => c := 'M'; + when 23 => c := 'N'; + when 24 => c := 'O'; + when 25 => c := 'P'; + when 26 => c := 'Q'; + when 27 => c := 'R'; + when 28 => c := 'S'; + when 29 => c := 'T'; + when 30 => c := 'U'; + when 31 => c := 'V'; + when 32 => c := 'W'; + when 33 => c := 'X'; + when 34 => c := 'Y'; + when 35 => c := 'Z'; + when others => c := '?'; + end case; + return c; + end chr; + + + + -- convert integer to string using specified base + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function str(int: integer; base: integer) return string is + + variable temp: string(1 to 10); + variable num: integer; + variable abs_int: integer; + variable len: integer := 1; + variable power: integer := 1; + + begin + + -- bug fix for negative numbers + abs_int := abs(int); + + num := abs_int; + + while num >= base loop -- Determine how many + len := len + 1; -- characters required + num := num / base; -- to represent the + end loop ; -- number. + + for i in len downto 1 loop -- Convert the number to + temp(i) := chr(abs_int/power mod base); -- a string starting + power := power * base; -- with the right hand + end loop ; -- side. + + -- return result and add sign if required + if int < 0 then + return '-'& temp(1 to len); + else + return temp(1 to len); + end if; + + end str; + + + -- convert integer to string, using base 10 + function str(int: integer) return string is + + begin + + return str(int, 10) ; + + end str; + + + + -- converts a std_logic_vector into a hex string. + function hstr(slv: std_logic_vector) return string is + variable hexlen: integer; + variable longslv : std_logic_vector(67 downto 0) := (others => '0'); + variable hex : string(1 to 16); + variable fourbit : std_logic_vector(3 downto 0); + begin + hexlen := (slv'left+1)/4; + if (slv'left+1) mod 4 /= 0 then + hexlen := hexlen + 1; + end if; + longslv(slv'left downto 0) := slv; + for i in (hexlen -1) downto 0 loop + fourbit := longslv(((i*4)+3) downto (i*4)); + case fourbit is + when "0000" => hex(hexlen -I) := '0'; + when "0001" => hex(hexlen -I) := '1'; + when "0010" => hex(hexlen -I) := '2'; + when "0011" => hex(hexlen -I) := '3'; + when "0100" => hex(hexlen -I) := '4'; + when "0101" => hex(hexlen -I) := '5'; + when "0110" => hex(hexlen -I) := '6'; + when "0111" => hex(hexlen -I) := '7'; + when "1000" => hex(hexlen -I) := '8'; + when "1001" => hex(hexlen -I) := '9'; + when "1010" => hex(hexlen -I) := 'A'; + when "1011" => hex(hexlen -I) := 'B'; + when "1100" => hex(hexlen -I) := 'C'; + when "1101" => hex(hexlen -I) := 'D'; + when "1110" => hex(hexlen -I) := 'E'; + when "1111" => hex(hexlen -I) := 'F'; + when "ZZZZ" => hex(hexlen -I) := 'z'; + when "UUUU" => hex(hexlen -I) := 'u'; + when "XXXX" => hex(hexlen -I) := 'x'; + when others => hex(hexlen -I) := '?'; + end case; + end loop; + return hex(1 to hexlen); + end hstr; + + + + -- functions to manipulate strings + ----------------------------------- + + + -- convert a character to upper case + + function to_upper(c: character) return character is + + variable u: character; + + begin + + case c is + when 'a' => u := 'A'; + when 'b' => u := 'B'; + when 'c' => u := 'C'; + when 'd' => u := 'D'; + when 'e' => u := 'E'; + when 'f' => u := 'F'; + when 'g' => u := 'G'; + when 'h' => u := 'H'; + when 'i' => u := 'I'; + when 'j' => u := 'J'; + when 'k' => u := 'K'; + when 'l' => u := 'L'; + when 'm' => u := 'M'; + when 'n' => u := 'N'; + when 'o' => u := 'O'; + when 'p' => u := 'P'; + when 'q' => u := 'Q'; + when 'r' => u := 'R'; + when 's' => u := 'S'; + when 't' => u := 'T'; + when 'u' => u := 'U'; + when 'v' => u := 'V'; + when 'w' => u := 'W'; + when 'x' => u := 'X'; + when 'y' => u := 'Y'; + when 'z' => u := 'Z'; + when others => u := c; + end case; + + return u; + + end to_upper; + + + -- convert a character to lower case + + function to_lower(c: character) return character is + + variable l: character; + + begin + + case c is + when 'A' => l := 'a'; + when 'B' => l := 'b'; + when 'C' => l := 'c'; + when 'D' => l := 'd'; + when 'E' => l := 'e'; + when 'F' => l := 'f'; + when 'G' => l := 'g'; + when 'H' => l := 'h'; + when 'I' => l := 'i'; + when 'J' => l := 'j'; + when 'K' => l := 'k'; + when 'L' => l := 'l'; + when 'M' => l := 'm'; + when 'N' => l := 'n'; + when 'O' => l := 'o'; + when 'P' => l := 'p'; + when 'Q' => l := 'q'; + when 'R' => l := 'r'; + when 'S' => l := 's'; + when 'T' => l := 't'; + when 'U' => l := 'u'; + when 'V' => l := 'v'; + when 'W' => l := 'w'; + when 'X' => l := 'x'; + when 'Y' => l := 'y'; + when 'Z' => l := 'z'; + when others => l := c; + end case; + + return l; + + end to_lower; + + + + -- convert a string to upper case + + function to_upper(s: string) return string is + + variable uppercase: string (s'range); + + begin + + for i in s'range loop + uppercase(i):= to_upper(s(i)); + end loop; + return uppercase; + + end to_upper; + + + + -- convert a string to lower case + + function to_lower(s: string) return string is + + variable lowercase: string (s'range); + + begin + + for i in s'range loop + lowercase(i):= to_lower(s(i)); + end loop; + return lowercase; + + end to_lower; + + + +-- functions to convert strings into other types + + +-- converts a character into a std_logic + +function to_std_logic(c: character) return std_logic is + variable sl: std_logic; + begin + case c is + when 'U' => + sl := 'U'; + when 'X' => + sl := 'X'; + when '0' => + sl := '0'; + when '1' => + sl := '1'; + when 'Z' => + sl := 'Z'; + when 'W' => + sl := 'W'; + when 'L' => + sl := 'L'; + when 'H' => + sl := 'H'; + when '-' => + sl := '-'; + when others => + sl := 'X'; + end case; + return sl; + end to_std_logic; + + +-- converts a string into std_logic_vector + +function to_std_logic_vector(s: string) return std_logic_vector is + variable slv: std_logic_vector(s'high-s'low downto 0); + variable k: integer; +begin + k := s'high-s'low; + for i in s'range loop + slv(k) := to_std_logic(s(i)); + k := k - 1; + end loop; + return slv; +end to_std_logic_vector; + + + + + + +---------------- +-- file I/O -- +---------------- + + + +-- read variable length string from input file + +procedure str_read(file in_file: TEXT; + res_string: out string) is + + variable l: line; + variable c: character; + variable is_string: boolean; + + begin + + readline(in_file, l); + -- clear the contents of the result string + for i in res_string'range loop + res_string(i) := ' '; + end loop; + -- read all characters of the line, up to the length + -- of the results string + for i in res_string'range loop + read(l, c, is_string); + res_string(i) := c; + if not is_string then -- found end of line + exit; + end if; + end loop; + +end str_read; + + +-- print string to a file +procedure print(file out_file: TEXT; + new_string: in string) is + + variable l: line; + + begin + + write(l, new_string); + writeline(out_file, l); + +end print; + + +-- print character to a file and start new line +procedure print(file out_file: TEXT; + char: in character) is + + variable l: line; + + begin + + write(l, char); + writeline(out_file, l); + +end print; + + + +-- appends contents of a string to a file until line feed occurs +-- (LF is considered to be the end of the string) + +procedure str_write(file out_file: TEXT; + new_string: in string) is + begin + + for i in new_string'range loop + print(out_file, new_string(i)); + if new_string(i) = LF then -- end of string + exit; + end if; + end loop; + +end str_write; + + + + +end txt_util; + + + + diff --git a/sim/util.do b/sim/util.do index 5f9f2ef..a16882f 100644 --- a/sim/util.do +++ b/sim/util.do @@ -58,7 +58,9 @@ proc load_testbench {name} { proc backup {path} { if {[file exists ${path}.orig] == 0} { - file copy $path ${path}.orig + if {[file exists $path] == 1} { + file copy $path ${path}.orig + } } } diff --git a/sim/wave_alu.do b/sim/wave_alu.do deleted file mode 100644 index 631b09d..0000000 --- a/sim/wave_alu.do +++ /dev/null @@ -1,33 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate /alu_tb/clk -add wave -noupdate /alu_tb/i_op -add wave -noupdate /alu_tb/i_A -add wave -noupdate /alu_tb/i_B -add wave -noupdate /alu_tb/o_R -add wave -noupdate /alu_tb/o_Z -add wave -noupdate /alu_tb/o_V -add wave -noupdate /alu_tb/alu_inst/op -add wave -noupdate /alu_tb/alu_inst/A -add wave -noupdate /alu_tb/alu_inst/B -add wave -noupdate /alu_tb/alu_inst/R -add wave -noupdate /alu_tb/alu_inst/Z -add wave -noupdate /alu_tb/alu_inst/V -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {0 ps} 0} -quietly wave cursor active 0 -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ps -update -WaveRestoreZoom {0 ps} {1 ns} diff --git a/sim/wave_protokoll.do b/sim/wave_protokoll.do deleted file mode 100644 index efd04d7..0000000 --- a/sim/wave_protokoll.do +++ /dev/null @@ -1,157 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -expand -group fetch -radix decimal /level1_tb/pipeline_inst/fetch_inst/pc_out -add wave -noupdate -expand -group fetch -radix hexadecimal /level1_tb/pipeline_inst/fetch_inst/instr -add wave -noupdate -expand -group pipeline -childformat {{/level1_tb/pipeline_inst/mem_out.address -radix decimal} {/level1_tb/pipeline_inst/mem_out.wrdata -radix decimal -childformat {{/level1_tb/pipeline_inst/mem_out.wrdata(31) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(30) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(29) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(28) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(27) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(26) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(25) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(24) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(23) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(22) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(21) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(20) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(19) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(18) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(17) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(16) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(15) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(14) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(13) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(12) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(11) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(10) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(9) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(8) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(7) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(6) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(5) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(4) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(3) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(2) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(1) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(0) -radix hexadecimal}}}} -expand -subitemconfig {/level1_tb/pipeline_inst/mem_out.address {-height 15 -radix decimal} /level1_tb/pipeline_inst/mem_out.wrdata {-height 15 -radix decimal -childformat {{/level1_tb/pipeline_inst/mem_out.wrdata(31) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(30) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(29) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(28) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(27) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(26) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(25) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(24) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(23) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(22) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(21) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(20) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(19) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(18) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(17) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(16) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(15) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(14) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(13) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(12) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(11) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(10) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(9) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(8) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(7) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(6) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(5) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(4) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(3) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(2) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(1) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_out.wrdata(0) -radix hexadecimal}}} /level1_tb/pipeline_inst/mem_out.wrdata(31) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_out.wrdata(30) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_out.wrdata(29) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_out.wrdata(28) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_out.wrdata(27) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_out.wrdata(26) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_out.wrdata(25) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_out.wrdata(24) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_out.wrdata(23) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_out.wrdata(22) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_out.wrdata(21) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_out.wrdata(20) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_out.wrdata(19) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_out.wrdata(18) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_out.wrdata(17) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_out.wrdata(16) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_out.wrdata(15) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_out.wrdata(14) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_out.wrdata(13) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_out.wrdata(12) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_out.wrdata(11) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_out.wrdata(10) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_out.wrdata(9) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_out.wrdata(8) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_out.wrdata(7) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_out.wrdata(6) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_out.wrdata(5) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_out.wrdata(4) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_out.wrdata(3) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_out.wrdata(2) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_out.wrdata(1) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_out.wrdata(0) {-height 15 -radix hexadecimal}} /level1_tb/pipeline_inst/mem_out -TreeUpdate [SetDefaultTree] -quietly WaveActivateNextPane -add wave -noupdate -expand -group pipeline -childformat {{/level1_tb/s_mem_in.rddata -radix hexadecimal}} -expand -subitemconfig {/level1_tb/s_mem_in.rddata {-height 15 -radix hexadecimal}} /level1_tb/s_mem_in -add wave -noupdate -expand -group pipeline /level1_tb/s_intr -add wave -noupdate -expand -group pipeline -childformat {{/level1_tb/r_mem_out.address -radix binary -childformat {{/level1_tb/r_mem_out.address(20) -radix binary} {/level1_tb/r_mem_out.address(19) -radix binary} {/level1_tb/r_mem_out.address(18) -radix binary} {/level1_tb/r_mem_out.address(17) -radix binary} {/level1_tb/r_mem_out.address(16) -radix binary} {/level1_tb/r_mem_out.address(15) -radix binary} {/level1_tb/r_mem_out.address(14) -radix binary} {/level1_tb/r_mem_out.address(13) -radix binary} {/level1_tb/r_mem_out.address(12) -radix binary} {/level1_tb/r_mem_out.address(11) -radix binary} {/level1_tb/r_mem_out.address(10) -radix binary} {/level1_tb/r_mem_out.address(9) -radix binary} {/level1_tb/r_mem_out.address(8) -radix binary} {/level1_tb/r_mem_out.address(7) -radix binary} {/level1_tb/r_mem_out.address(6) -radix binary} {/level1_tb/r_mem_out.address(5) -radix binary} {/level1_tb/r_mem_out.address(4) -radix binary} {/level1_tb/r_mem_out.address(3) -radix binary} {/level1_tb/r_mem_out.address(2) -radix binary} {/level1_tb/r_mem_out.address(1) -radix binary} {/level1_tb/r_mem_out.address(0) -radix binary}}} {/level1_tb/r_mem_out.wrdata -radix hexadecimal}} -expand -subitemconfig {/level1_tb/r_mem_out.address {-height 15 -radix binary -childformat {{/level1_tb/r_mem_out.address(20) -radix binary} {/level1_tb/r_mem_out.address(19) -radix binary} {/level1_tb/r_mem_out.address(18) -radix binary} {/level1_tb/r_mem_out.address(17) -radix binary} {/level1_tb/r_mem_out.address(16) -radix binary} {/level1_tb/r_mem_out.address(15) -radix binary} {/level1_tb/r_mem_out.address(14) -radix binary} {/level1_tb/r_mem_out.address(13) -radix binary} {/level1_tb/r_mem_out.address(12) -radix binary} {/level1_tb/r_mem_out.address(11) -radix binary} {/level1_tb/r_mem_out.address(10) -radix binary} {/level1_tb/r_mem_out.address(9) -radix binary} {/level1_tb/r_mem_out.address(8) -radix binary} {/level1_tb/r_mem_out.address(7) -radix binary} {/level1_tb/r_mem_out.address(6) -radix binary} {/level1_tb/r_mem_out.address(5) -radix binary} {/level1_tb/r_mem_out.address(4) -radix binary} {/level1_tb/r_mem_out.address(3) -radix binary} {/level1_tb/r_mem_out.address(2) -radix binary} {/level1_tb/r_mem_out.address(1) -radix binary} {/level1_tb/r_mem_out.address(0) -radix binary}}} /level1_tb/r_mem_out.address(20) {-height 15 -radix binary} /level1_tb/r_mem_out.address(19) {-height 15 -radix binary} /level1_tb/r_mem_out.address(18) {-height 15 -radix binary} /level1_tb/r_mem_out.address(17) {-height 15 -radix binary} /level1_tb/r_mem_out.address(16) {-height 15 -radix binary} /level1_tb/r_mem_out.address(15) {-height 15 -radix binary} /level1_tb/r_mem_out.address(14) {-height 15 -radix binary} /level1_tb/r_mem_out.address(13) {-height 15 -radix binary} /level1_tb/r_mem_out.address(12) {-height 15 -radix binary} /level1_tb/r_mem_out.address(11) {-height 15 -radix binary} /level1_tb/r_mem_out.address(10) {-height 15 -radix binary} /level1_tb/r_mem_out.address(9) {-height 15 -radix binary} /level1_tb/r_mem_out.address(8) {-height 15 -radix binary} /level1_tb/r_mem_out.address(7) {-height 15 -radix binary} /level1_tb/r_mem_out.address(6) {-height 15 -radix binary} /level1_tb/r_mem_out.address(5) {-height 15 -radix binary} /level1_tb/r_mem_out.address(4) {-height 15 -radix binary} /level1_tb/r_mem_out.address(3) {-height 15 -radix binary} /level1_tb/r_mem_out.address(2) {-height 15 -radix binary} /level1_tb/r_mem_out.address(1) {-height 15 -radix binary} /level1_tb/r_mem_out.address(0) {-height 15 -radix binary} /level1_tb/r_mem_out.wrdata {-height 15 -radix hexadecimal}} /level1_tb/r_mem_out -add wave -noupdate -expand -group pipeline -childformat {{/level1_tb/a_mem_out.wrdata -radix hexadecimal}} -expand -subitemconfig {/level1_tb/a_mem_out.wrdata {-height 15 -radix hexadecimal}} /level1_tb/a_mem_out -add wave -noupdate -group fetch /level1_tb/pipeline_inst/fetch_inst/pcsrc -add wave -noupdate -group fetch /level1_tb/pipeline_inst/fetch_inst/pc_in -add wave -noupdate -group fetch /level1_tb/pipeline_inst/fetch_inst/pc_out -add wave -noupdate -group fetch /level1_tb/pipeline_inst/fetch_inst/instr -add wave -noupdate -group fetch /level1_tb/pipeline_inst/fetch_inst/imem_addr -add wave -noupdate -group fetch /level1_tb/pipeline_inst/fetch_inst/int_pc -add wave -noupdate -group fetch /level1_tb/pipeline_inst/fetch_inst/int_pc_next -add wave -noupdate -expand -group decode -group regfile /level1_tb/pipeline_inst/decode_inst/regfile_inst/clk -add wave -noupdate -expand -group decode -group regfile /level1_tb/pipeline_inst/decode_inst/regfile_inst/reset -add wave -noupdate -expand -group decode -group regfile /level1_tb/pipeline_inst/decode_inst/regfile_inst/stall -add wave -noupdate -expand -group decode -group regfile /level1_tb/pipeline_inst/decode_inst/regfile_inst/rdaddr1 -add wave -noupdate -expand -group decode -group regfile /level1_tb/pipeline_inst/decode_inst/regfile_inst/rdaddr2 -add wave -noupdate -expand -group decode -group regfile /level1_tb/pipeline_inst/decode_inst/regfile_inst/rddata1 -add wave -noupdate -expand -group decode -group regfile /level1_tb/pipeline_inst/decode_inst/regfile_inst/rddata2 -add wave -noupdate -expand -group decode -group regfile /level1_tb/pipeline_inst/decode_inst/regfile_inst/wraddr -add wave -noupdate -expand -group decode -group regfile /level1_tb/pipeline_inst/decode_inst/regfile_inst/wrdata -add wave -noupdate -expand -group decode -group regfile /level1_tb/pipeline_inst/decode_inst/regfile_inst/regwrite -add wave -noupdate -expand -group decode -group regfile /level1_tb/pipeline_inst/decode_inst/regfile_inst/register_A -add wave -noupdate -expand -group decode -group regfile /level1_tb/pipeline_inst/decode_inst/regfile_inst/latch_rddata1 -add wave -noupdate -expand -group decode -group regfile /level1_tb/pipeline_inst/decode_inst/regfile_inst/latch_rddata1_next -add wave -noupdate -expand -group decode -group regfile /level1_tb/pipeline_inst/decode_inst/regfile_inst/latch_rddata2 -add wave -noupdate -expand -group decode -group regfile /level1_tb/pipeline_inst/decode_inst/regfile_inst/latch_rddata2_next -add wave -noupdate -expand -group decode -group regfile /level1_tb/pipeline_inst/decode_inst/regfile_inst/output_rddata1 -add wave -noupdate -expand -group decode -group regfile /level1_tb/pipeline_inst/decode_inst/regfile_inst/output_rddata2 -add wave -noupdate -expand -group decode -group regfile /level1_tb/pipeline_inst/decode_inst/regfile_inst/int_regwrite -add wave -noupdate -expand -group decode -group regfile /level1_tb/pipeline_inst/decode_inst/regfile_inst/int_wr_zero -add wave -noupdate -expand -group decode -group regfile /level1_tb/pipeline_inst/decode_inst/regfile_inst/ZERO -add wave -noupdate -expand -group decode -radix decimal /level1_tb/pipeline_inst/decode_inst/pc_in -add wave -noupdate -expand -group decode -radix hexadecimal /level1_tb/pipeline_inst/decode_inst/instr -add wave -noupdate -expand -group decode /level1_tb/pipeline_inst/decode_inst/dbg_instr -add wave -noupdate -expand -group decode -radix decimal -childformat {{/level1_tb/pipeline_inst/decode_inst/wraddr(4) -radix decimal} {/level1_tb/pipeline_inst/decode_inst/wraddr(3) -radix decimal} {/level1_tb/pipeline_inst/decode_inst/wraddr(2) -radix decimal} {/level1_tb/pipeline_inst/decode_inst/wraddr(1) -radix decimal} {/level1_tb/pipeline_inst/decode_inst/wraddr(0) -radix decimal}} -subitemconfig {/level1_tb/pipeline_inst/decode_inst/wraddr(4) {-height 15 -radix decimal} /level1_tb/pipeline_inst/decode_inst/wraddr(3) {-height 15 -radix decimal} /level1_tb/pipeline_inst/decode_inst/wraddr(2) {-height 15 -radix decimal} /level1_tb/pipeline_inst/decode_inst/wraddr(1) {-height 15 -radix decimal} /level1_tb/pipeline_inst/decode_inst/wraddr(0) {-height 15 -radix decimal}} /level1_tb/pipeline_inst/decode_inst/wraddr -add wave -noupdate -expand -group decode -radix hexadecimal -childformat {{/level1_tb/pipeline_inst/decode_inst/wrdata(31) -radix hexadecimal} {/level1_tb/pipeline_inst/decode_inst/wrdata(30) -radix hexadecimal} {/level1_tb/pipeline_inst/decode_inst/wrdata(29) -radix hexadecimal} {/level1_tb/pipeline_inst/decode_inst/wrdata(28) -radix hexadecimal} {/level1_tb/pipeline_inst/decode_inst/wrdata(27) -radix hexadecimal} {/level1_tb/pipeline_inst/decode_inst/wrdata(26) -radix hexadecimal} {/level1_tb/pipeline_inst/decode_inst/wrdata(25) -radix hexadecimal} {/level1_tb/pipeline_inst/decode_inst/wrdata(24) -radix hexadecimal} {/level1_tb/pipeline_inst/decode_inst/wrdata(23) -radix hexadecimal} {/level1_tb/pipeline_inst/decode_inst/wrdata(22) -radix hexadecimal} {/level1_tb/pipeline_inst/decode_inst/wrdata(21) -radix hexadecimal} {/level1_tb/pipeline_inst/decode_inst/wrdata(20) -radix hexadecimal} {/level1_tb/pipeline_inst/decode_inst/wrdata(19) -radix hexadecimal} {/level1_tb/pipeline_inst/decode_inst/wrdata(18) -radix hexadecimal} {/level1_tb/pipeline_inst/decode_inst/wrdata(17) -radix hexadecimal} {/level1_tb/pipeline_inst/decode_inst/wrdata(16) -radix hexadecimal} {/level1_tb/pipeline_inst/decode_inst/wrdata(15) -radix hexadecimal} {/level1_tb/pipeline_inst/decode_inst/wrdata(14) -radix hexadecimal} {/level1_tb/pipeline_inst/decode_inst/wrdata(13) -radix hexadecimal} {/level1_tb/pipeline_inst/decode_inst/wrdata(12) -radix hexadecimal} {/level1_tb/pipeline_inst/decode_inst/wrdata(11) -radix hexadecimal} {/level1_tb/pipeline_inst/decode_inst/wrdata(10) -radix hexadecimal} {/level1_tb/pipeline_inst/decode_inst/wrdata(9) -radix hexadecimal} {/level1_tb/pipeline_inst/decode_inst/wrdata(8) -radix hexadecimal} {/level1_tb/pipeline_inst/decode_inst/wrdata(7) -radix hexadecimal} {/level1_tb/pipeline_inst/decode_inst/wrdata(6) -radix hexadecimal} {/level1_tb/pipeline_inst/decode_inst/wrdata(5) -radix hexadecimal} {/level1_tb/pipeline_inst/decode_inst/wrdata(4) -radix hexadecimal} {/level1_tb/pipeline_inst/decode_inst/wrdata(3) -radix hexadecimal} {/level1_tb/pipeline_inst/decode_inst/wrdata(2) -radix hexadecimal} {/level1_tb/pipeline_inst/decode_inst/wrdata(1) -radix hexadecimal} {/level1_tb/pipeline_inst/decode_inst/wrdata(0) -radix hexadecimal}} -subitemconfig {/level1_tb/pipeline_inst/decode_inst/wrdata(31) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/decode_inst/wrdata(30) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/decode_inst/wrdata(29) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/decode_inst/wrdata(28) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/decode_inst/wrdata(27) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/decode_inst/wrdata(26) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/decode_inst/wrdata(25) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/decode_inst/wrdata(24) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/decode_inst/wrdata(23) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/decode_inst/wrdata(22) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/decode_inst/wrdata(21) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/decode_inst/wrdata(20) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/decode_inst/wrdata(19) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/decode_inst/wrdata(18) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/decode_inst/wrdata(17) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/decode_inst/wrdata(16) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/decode_inst/wrdata(15) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/decode_inst/wrdata(14) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/decode_inst/wrdata(13) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/decode_inst/wrdata(12) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/decode_inst/wrdata(11) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/decode_inst/wrdata(10) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/decode_inst/wrdata(9) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/decode_inst/wrdata(8) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/decode_inst/wrdata(7) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/decode_inst/wrdata(6) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/decode_inst/wrdata(5) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/decode_inst/wrdata(4) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/decode_inst/wrdata(3) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/decode_inst/wrdata(2) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/decode_inst/wrdata(1) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/decode_inst/wrdata(0) {-height 15 -radix hexadecimal}} /level1_tb/pipeline_inst/decode_inst/wrdata -add wave -noupdate -expand -group decode /level1_tb/pipeline_inst/decode_inst/regwrite -add wave -noupdate -expand -group decode -radix decimal /level1_tb/pipeline_inst/decode_inst/pc_out -add wave -noupdate -expand -group decode /level1_tb/pipeline_inst/decode_inst/exec_op -add wave -noupdate -expand -group decode /level1_tb/pipeline_inst/decode_inst/cop0_op -add wave -noupdate -expand -group decode /level1_tb/pipeline_inst/decode_inst/jmp_op -add wave -noupdate -expand -group decode /level1_tb/pipeline_inst/decode_inst/mem_op -add wave -noupdate -expand -group decode /level1_tb/pipeline_inst/decode_inst/wb_op -add wave -noupdate -expand -group decode /level1_tb/pipeline_inst/decode_inst/exc_dec -add wave -noupdate -expand -group decode /level1_tb/pipeline_inst/decode_inst/taradr -add wave -noupdate -expand -group decode /level1_tb/pipeline_inst/decode_inst/adrim -add wave -noupdate -expand -group decode /level1_tb/pipeline_inst/decode_inst/func -add wave -noupdate -expand -group decode /level1_tb/pipeline_inst/decode_inst/shamt -add wave -noupdate -expand -group decode /level1_tb/pipeline_inst/decode_inst/Ird -add wave -noupdate -expand -group decode /level1_tb/pipeline_inst/decode_inst/rd -add wave -noupdate -expand -group decode /level1_tb/pipeline_inst/decode_inst/rt -add wave -noupdate -expand -group decode /level1_tb/pipeline_inst/decode_inst/rs -add wave -noupdate -expand -group decode /level1_tb/pipeline_inst/decode_inst/opcode -add wave -noupdate -expand -group decode /level1_tb/pipeline_inst/decode_inst/int_rdaddr1 -add wave -noupdate -expand -group decode /level1_tb/pipeline_inst/decode_inst/int_rdaddr2 -add wave -noupdate -expand -group decode /level1_tb/pipeline_inst/decode_inst/int_rddata1 -add wave -noupdate -expand -group decode /level1_tb/pipeline_inst/decode_inst/int_rddata2 -add wave -noupdate -expand -group exec -group alu /level1_tb/pipeline_inst/exec_inst/alu_inst/op -add wave -noupdate -expand -group exec -group alu /level1_tb/pipeline_inst/exec_inst/alu_inst/A -add wave -noupdate -expand -group exec -group alu /level1_tb/pipeline_inst/exec_inst/alu_inst/B -add wave -noupdate -expand -group exec -group alu /level1_tb/pipeline_inst/exec_inst/alu_inst/R -add wave -noupdate -expand -group exec -group alu /level1_tb/pipeline_inst/exec_inst/alu_inst/Z -add wave -noupdate -expand -group exec -group alu /level1_tb/pipeline_inst/exec_inst/alu_inst/V -add wave -noupdate -expand -group exec -radix decimal /level1_tb/pipeline_inst/exec_inst/pc_in -add wave -noupdate -expand -group exec /level1_tb/pipeline_inst/exec_inst/op -add wave -noupdate -expand -group exec -radix decimal /level1_tb/pipeline_inst/exec_inst/pc_out -add wave -noupdate -expand -group exec -radix decimal /level1_tb/pipeline_inst/exec_inst/rd -add wave -noupdate -expand -group exec /level1_tb/pipeline_inst/exec_inst/rs -add wave -noupdate -expand -group exec /level1_tb/pipeline_inst/exec_inst/rt -add wave -noupdate -expand -group exec -radix hexadecimal /level1_tb/pipeline_inst/exec_inst/aluresult -add wave -noupdate -expand -group exec -radix hexadecimal -childformat {{/level1_tb/pipeline_inst/exec_inst/wrdata(31) -radix hexadecimal} {/level1_tb/pipeline_inst/exec_inst/wrdata(30) -radix hexadecimal} {/level1_tb/pipeline_inst/exec_inst/wrdata(29) -radix hexadecimal} {/level1_tb/pipeline_inst/exec_inst/wrdata(28) -radix hexadecimal} {/level1_tb/pipeline_inst/exec_inst/wrdata(27) -radix hexadecimal} {/level1_tb/pipeline_inst/exec_inst/wrdata(26) -radix hexadecimal} {/level1_tb/pipeline_inst/exec_inst/wrdata(25) -radix hexadecimal} {/level1_tb/pipeline_inst/exec_inst/wrdata(24) -radix hexadecimal} {/level1_tb/pipeline_inst/exec_inst/wrdata(23) -radix hexadecimal} {/level1_tb/pipeline_inst/exec_inst/wrdata(22) -radix hexadecimal} {/level1_tb/pipeline_inst/exec_inst/wrdata(21) -radix hexadecimal} {/level1_tb/pipeline_inst/exec_inst/wrdata(20) -radix hexadecimal} {/level1_tb/pipeline_inst/exec_inst/wrdata(19) -radix hexadecimal} {/level1_tb/pipeline_inst/exec_inst/wrdata(18) -radix hexadecimal} {/level1_tb/pipeline_inst/exec_inst/wrdata(17) -radix hexadecimal} {/level1_tb/pipeline_inst/exec_inst/wrdata(16) -radix hexadecimal} {/level1_tb/pipeline_inst/exec_inst/wrdata(15) -radix hexadecimal} {/level1_tb/pipeline_inst/exec_inst/wrdata(14) -radix hexadecimal} {/level1_tb/pipeline_inst/exec_inst/wrdata(13) -radix hexadecimal} {/level1_tb/pipeline_inst/exec_inst/wrdata(12) -radix hexadecimal} {/level1_tb/pipeline_inst/exec_inst/wrdata(11) -radix hexadecimal} {/level1_tb/pipeline_inst/exec_inst/wrdata(10) -radix hexadecimal} {/level1_tb/pipeline_inst/exec_inst/wrdata(9) -radix hexadecimal} {/level1_tb/pipeline_inst/exec_inst/wrdata(8) -radix hexadecimal} {/level1_tb/pipeline_inst/exec_inst/wrdata(7) -radix hexadecimal} {/level1_tb/pipeline_inst/exec_inst/wrdata(6) -radix hexadecimal} {/level1_tb/pipeline_inst/exec_inst/wrdata(5) -radix hexadecimal} {/level1_tb/pipeline_inst/exec_inst/wrdata(4) -radix hexadecimal} {/level1_tb/pipeline_inst/exec_inst/wrdata(3) -radix hexadecimal} {/level1_tb/pipeline_inst/exec_inst/wrdata(2) -radix hexadecimal} {/level1_tb/pipeline_inst/exec_inst/wrdata(1) -radix hexadecimal} {/level1_tb/pipeline_inst/exec_inst/wrdata(0) -radix hexadecimal}} -subitemconfig {/level1_tb/pipeline_inst/exec_inst/wrdata(31) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/exec_inst/wrdata(30) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/exec_inst/wrdata(29) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/exec_inst/wrdata(28) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/exec_inst/wrdata(27) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/exec_inst/wrdata(26) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/exec_inst/wrdata(25) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/exec_inst/wrdata(24) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/exec_inst/wrdata(23) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/exec_inst/wrdata(22) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/exec_inst/wrdata(21) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/exec_inst/wrdata(20) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/exec_inst/wrdata(19) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/exec_inst/wrdata(18) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/exec_inst/wrdata(17) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/exec_inst/wrdata(16) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/exec_inst/wrdata(15) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/exec_inst/wrdata(14) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/exec_inst/wrdata(13) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/exec_inst/wrdata(12) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/exec_inst/wrdata(11) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/exec_inst/wrdata(10) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/exec_inst/wrdata(9) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/exec_inst/wrdata(8) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/exec_inst/wrdata(7) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/exec_inst/wrdata(6) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/exec_inst/wrdata(5) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/exec_inst/wrdata(4) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/exec_inst/wrdata(3) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/exec_inst/wrdata(2) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/exec_inst/wrdata(1) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/exec_inst/wrdata(0) {-height 15 -radix hexadecimal}} /level1_tb/pipeline_inst/exec_inst/wrdata -add wave -noupdate -expand -group exec /level1_tb/pipeline_inst/exec_inst/zero -add wave -noupdate -expand -group exec /level1_tb/pipeline_inst/exec_inst/neg -add wave -noupdate -expand -group exec -radix decimal /level1_tb/pipeline_inst/exec_inst/new_pc -add wave -noupdate -expand -group exec /level1_tb/pipeline_inst/exec_inst/memop_in -add wave -noupdate -expand -group exec /level1_tb/pipeline_inst/exec_inst/memop_out -add wave -noupdate -expand -group exec /level1_tb/pipeline_inst/exec_inst/jmpop_in -add wave -noupdate -expand -group exec /level1_tb/pipeline_inst/exec_inst/jmpop_out -add wave -noupdate -expand -group exec /level1_tb/pipeline_inst/exec_inst/wbop_in -add wave -noupdate -expand -group exec /level1_tb/pipeline_inst/exec_inst/wbop_out -add wave -noupdate -expand -group exec /level1_tb/pipeline_inst/exec_inst/forwardA -add wave -noupdate -expand -group exec /level1_tb/pipeline_inst/exec_inst/forwardB -add wave -noupdate -expand -group exec -radix hexadecimal /level1_tb/pipeline_inst/exec_inst/cop0_rddata -add wave -noupdate -expand -group exec -radix hexadecimal /level1_tb/pipeline_inst/exec_inst/mem_aluresult -add wave -noupdate -expand -group exec -radix hexadecimal /level1_tb/pipeline_inst/exec_inst/wb_result -add wave -noupdate -expand -group exec /level1_tb/pipeline_inst/exec_inst/exc_ovf -add wave -noupdate -expand -group exec -radix hexadecimal /level1_tb/pipeline_inst/exec_inst/int_alu_A -add wave -noupdate -expand -group exec -radix hexadecimal /level1_tb/pipeline_inst/exec_inst/int_alu_B -add wave -noupdate -expand -group exec -radix hexadecimal /level1_tb/pipeline_inst/exec_inst/int_alu_R -add wave -noupdate -expand -group exec /level1_tb/pipeline_inst/exec_inst/int_alu_Z -add wave -noupdate -expand -group exec /level1_tb/pipeline_inst/exec_inst/int_alu_V -add wave -noupdate -expand -group exec /level1_tb/pipeline_inst/exec_inst/int_pc_in -add wave -noupdate -expand -group exec /level1_tb/pipeline_inst/exec_inst/int_op -add wave -noupdate -expand -group exec /level1_tb/pipeline_inst/exec_inst/int_memop_in -add wave -noupdate -expand -group exec /level1_tb/pipeline_inst/exec_inst/int_jmpop_in -add wave -noupdate -expand -group exec /level1_tb/pipeline_inst/exec_inst/int_wbop_in -add wave -noupdate -expand -group exec /level1_tb/pipeline_inst/exec_inst/int_wbop_out -add wave -noupdate -expand -group exec /level1_tb/pipeline_inst/exec_inst/int_exc_ovf -add wave -noupdate -expand -group memory /level1_tb/pipeline_inst/mem_inst/mem_op -add wave -noupdate -expand -group memory /level1_tb/pipeline_inst/mem_inst/jmp_op -add wave -noupdate -expand -group memory -radix decimal /level1_tb/pipeline_inst/mem_inst/pc_in -add wave -noupdate -expand -group memory -radix decimal /level1_tb/pipeline_inst/mem_inst/rd_in -add wave -noupdate -expand -group memory -radix hexadecimal /level1_tb/pipeline_inst/mem_inst/aluresult_in -add wave -noupdate -expand -group memory -radix hexadecimal -childformat {{/level1_tb/pipeline_inst/mem_inst/wrdata(31) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/wrdata(30) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/wrdata(29) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/wrdata(28) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/wrdata(27) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/wrdata(26) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/wrdata(25) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/wrdata(24) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/wrdata(23) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/wrdata(22) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/wrdata(21) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/wrdata(20) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/wrdata(19) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/wrdata(18) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/wrdata(17) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/wrdata(16) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/wrdata(15) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/wrdata(14) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/wrdata(13) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/wrdata(12) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/wrdata(11) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/wrdata(10) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/wrdata(9) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/wrdata(8) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/wrdata(7) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/wrdata(6) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/wrdata(5) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/wrdata(4) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/wrdata(3) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/wrdata(2) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/wrdata(1) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/wrdata(0) -radix hexadecimal}} -subitemconfig {/level1_tb/pipeline_inst/mem_inst/wrdata(31) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/wrdata(30) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/wrdata(29) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/wrdata(28) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/wrdata(27) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/wrdata(26) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/wrdata(25) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/wrdata(24) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/wrdata(23) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/wrdata(22) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/wrdata(21) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/wrdata(20) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/wrdata(19) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/wrdata(18) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/wrdata(17) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/wrdata(16) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/wrdata(15) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/wrdata(14) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/wrdata(13) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/wrdata(12) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/wrdata(11) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/wrdata(10) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/wrdata(9) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/wrdata(8) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/wrdata(7) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/wrdata(6) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/wrdata(5) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/wrdata(4) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/wrdata(3) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/wrdata(2) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/wrdata(1) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/wrdata(0) {-height 15 -radix hexadecimal}} /level1_tb/pipeline_inst/mem_inst/wrdata -add wave -noupdate -expand -group memory /level1_tb/pipeline_inst/mem_inst/zero -add wave -noupdate -expand -group memory /level1_tb/pipeline_inst/mem_inst/neg -add wave -noupdate -expand -group memory -radix decimal /level1_tb/pipeline_inst/mem_inst/new_pc_in -add wave -noupdate -expand -group memory -radix decimal /level1_tb/pipeline_inst/mem_inst/pc_out -add wave -noupdate -expand -group memory /level1_tb/pipeline_inst/mem_inst/pcsrc -add wave -noupdate -expand -group memory -radix decimal /level1_tb/pipeline_inst/mem_inst/rd_out -add wave -noupdate -expand -group memory -radix hexadecimal /level1_tb/pipeline_inst/mem_inst/aluresult_out -add wave -noupdate -expand -group memory -radix hexadecimal /level1_tb/pipeline_inst/mem_inst/memresult -add wave -noupdate -expand -group memory -radix decimal /level1_tb/pipeline_inst/mem_inst/new_pc_out -add wave -noupdate -expand -group memory /level1_tb/pipeline_inst/mem_inst/wbop_in -add wave -noupdate -expand -group memory /level1_tb/pipeline_inst/mem_inst/wbop_out -add wave -noupdate -expand -group memory -expand /level1_tb/pipeline_inst/mem_inst/mem_out -add wave -noupdate -expand -group memory -radix hexadecimal -childformat {{/level1_tb/pipeline_inst/mem_inst/mem_data(31) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/mem_data(30) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/mem_data(29) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/mem_data(28) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/mem_data(27) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/mem_data(26) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/mem_data(25) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/mem_data(24) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/mem_data(23) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/mem_data(22) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/mem_data(21) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/mem_data(20) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/mem_data(19) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/mem_data(18) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/mem_data(17) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/mem_data(16) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/mem_data(15) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/mem_data(14) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/mem_data(13) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/mem_data(12) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/mem_data(11) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/mem_data(10) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/mem_data(9) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/mem_data(8) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/mem_data(7) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/mem_data(6) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/mem_data(5) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/mem_data(4) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/mem_data(3) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/mem_data(2) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/mem_data(1) -radix hexadecimal} {/level1_tb/pipeline_inst/mem_inst/mem_data(0) -radix hexadecimal}} -subitemconfig {/level1_tb/pipeline_inst/mem_inst/mem_data(31) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/mem_data(30) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/mem_data(29) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/mem_data(28) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/mem_data(27) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/mem_data(26) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/mem_data(25) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/mem_data(24) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/mem_data(23) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/mem_data(22) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/mem_data(21) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/mem_data(20) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/mem_data(19) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/mem_data(18) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/mem_data(17) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/mem_data(16) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/mem_data(15) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/mem_data(14) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/mem_data(13) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/mem_data(12) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/mem_data(11) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/mem_data(10) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/mem_data(9) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/mem_data(8) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/mem_data(7) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/mem_data(6) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/mem_data(5) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/mem_data(4) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/mem_data(3) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/mem_data(2) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/mem_data(1) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/mem_inst/mem_data(0) {-height 15 -radix hexadecimal}} /level1_tb/pipeline_inst/mem_inst/mem_data -add wave -noupdate -expand -group memory /level1_tb/pipeline_inst/mem_inst/exc_load -add wave -noupdate -expand -group memory /level1_tb/pipeline_inst/mem_inst/exc_store -add wave -noupdate -expand -group {write back} /level1_tb/pipeline_inst/wb_inst/op -add wave -noupdate -expand -group {write back} -radix decimal /level1_tb/pipeline_inst/wb_inst/rd_in -add wave -noupdate -expand -group {write back} -radix hexadecimal /level1_tb/pipeline_inst/wb_inst/aluresult -add wave -noupdate -expand -group {write back} -radix hexadecimal /level1_tb/pipeline_inst/wb_inst/memresult -add wave -noupdate -expand -group {write back} -radix decimal -childformat {{/level1_tb/pipeline_inst/wb_inst/rd_out(4) -radix decimal} {/level1_tb/pipeline_inst/wb_inst/rd_out(3) -radix decimal} {/level1_tb/pipeline_inst/wb_inst/rd_out(2) -radix decimal} {/level1_tb/pipeline_inst/wb_inst/rd_out(1) -radix decimal} {/level1_tb/pipeline_inst/wb_inst/rd_out(0) -radix decimal}} -subitemconfig {/level1_tb/pipeline_inst/wb_inst/rd_out(4) {-height 15 -radix decimal} /level1_tb/pipeline_inst/wb_inst/rd_out(3) {-height 15 -radix decimal} /level1_tb/pipeline_inst/wb_inst/rd_out(2) {-height 15 -radix decimal} /level1_tb/pipeline_inst/wb_inst/rd_out(1) {-height 15 -radix decimal} /level1_tb/pipeline_inst/wb_inst/rd_out(0) {-height 15 -radix decimal}} /level1_tb/pipeline_inst/wb_inst/rd_out -add wave -noupdate -expand -group {write back} -radix hexadecimal -childformat {{/level1_tb/pipeline_inst/wb_inst/result(31) -radix hexadecimal} {/level1_tb/pipeline_inst/wb_inst/result(30) -radix hexadecimal} {/level1_tb/pipeline_inst/wb_inst/result(29) -radix hexadecimal} {/level1_tb/pipeline_inst/wb_inst/result(28) -radix hexadecimal} {/level1_tb/pipeline_inst/wb_inst/result(27) -radix hexadecimal} {/level1_tb/pipeline_inst/wb_inst/result(26) -radix hexadecimal} {/level1_tb/pipeline_inst/wb_inst/result(25) -radix hexadecimal} {/level1_tb/pipeline_inst/wb_inst/result(24) -radix hexadecimal} {/level1_tb/pipeline_inst/wb_inst/result(23) -radix hexadecimal} {/level1_tb/pipeline_inst/wb_inst/result(22) -radix hexadecimal} {/level1_tb/pipeline_inst/wb_inst/result(21) -radix hexadecimal} {/level1_tb/pipeline_inst/wb_inst/result(20) -radix hexadecimal} {/level1_tb/pipeline_inst/wb_inst/result(19) -radix hexadecimal} {/level1_tb/pipeline_inst/wb_inst/result(18) -radix hexadecimal} {/level1_tb/pipeline_inst/wb_inst/result(17) -radix hexadecimal} {/level1_tb/pipeline_inst/wb_inst/result(16) -radix hexadecimal} {/level1_tb/pipeline_inst/wb_inst/result(15) -radix hexadecimal} {/level1_tb/pipeline_inst/wb_inst/result(14) -radix hexadecimal} {/level1_tb/pipeline_inst/wb_inst/result(13) -radix hexadecimal} {/level1_tb/pipeline_inst/wb_inst/result(12) -radix hexadecimal} {/level1_tb/pipeline_inst/wb_inst/result(11) -radix hexadecimal} {/level1_tb/pipeline_inst/wb_inst/result(10) -radix hexadecimal} {/level1_tb/pipeline_inst/wb_inst/result(9) -radix hexadecimal} {/level1_tb/pipeline_inst/wb_inst/result(8) -radix hexadecimal} {/level1_tb/pipeline_inst/wb_inst/result(7) -radix hexadecimal} {/level1_tb/pipeline_inst/wb_inst/result(6) -radix hexadecimal} {/level1_tb/pipeline_inst/wb_inst/result(5) -radix hexadecimal} {/level1_tb/pipeline_inst/wb_inst/result(4) -radix hexadecimal} {/level1_tb/pipeline_inst/wb_inst/result(3) -radix hexadecimal} {/level1_tb/pipeline_inst/wb_inst/result(2) -radix hexadecimal} {/level1_tb/pipeline_inst/wb_inst/result(1) -radix hexadecimal} {/level1_tb/pipeline_inst/wb_inst/result(0) -radix hexadecimal}} -subitemconfig {/level1_tb/pipeline_inst/wb_inst/result(31) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/wb_inst/result(30) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/wb_inst/result(29) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/wb_inst/result(28) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/wb_inst/result(27) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/wb_inst/result(26) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/wb_inst/result(25) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/wb_inst/result(24) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/wb_inst/result(23) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/wb_inst/result(22) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/wb_inst/result(21) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/wb_inst/result(20) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/wb_inst/result(19) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/wb_inst/result(18) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/wb_inst/result(17) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/wb_inst/result(16) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/wb_inst/result(15) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/wb_inst/result(14) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/wb_inst/result(13) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/wb_inst/result(12) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/wb_inst/result(11) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/wb_inst/result(10) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/wb_inst/result(9) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/wb_inst/result(8) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/wb_inst/result(7) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/wb_inst/result(6) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/wb_inst/result(5) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/wb_inst/result(4) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/wb_inst/result(3) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/wb_inst/result(2) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/wb_inst/result(1) {-height 15 -radix hexadecimal} /level1_tb/pipeline_inst/wb_inst/result(0) {-height 15 -radix hexadecimal}} /level1_tb/pipeline_inst/wb_inst/result -add wave -noupdate -expand -group {write back} /level1_tb/pipeline_inst/wb_inst/regwrite -add wave -noupdate -expand -group {external memory} /level1_tb/memory_inst/address -add wave -noupdate -expand -group {external memory} /level1_tb/memory_inst/byteena -add wave -noupdate -expand -group {external memory} /level1_tb/memory_inst/data -add wave -noupdate -expand -group {external memory} /level1_tb/memory_inst/wren -add wave -noupdate -expand -group {external memory} -radix hexadecimal /level1_tb/memory_inst/q -add wave -noupdate -expand -group {external memory} /level1_tb/memory_inst/sub_wire0 -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 3} {0 fs} 0} {{Cursor 4} {36000 fs} 0} -quietly wave cursor active 2 -configure wave -namecolwidth 173 -configure wave -valuecolwidth 136 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits us -update -WaveRestoreZoom {0 fs} {108200 fs}