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chipset_enable.c
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/*
* This file is part of the flashrom project.
*
* Copyright (C) 2000 Silicon Integrated System Corporation
* Copyright (C) 2005-2009 coresystems GmbH
* Copyright (C) 2006 Uwe Hermann <[email protected]>
* Copyright (C) 2007,2008,2009 Carl-Daniel Hailfinger
* Copyright (C) 2009 Kontron Modular Computers GmbH
* Copyright (C) 2011, 2012 Stefan Tauner
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*
* Contains the chipset specific flash enables.
*/
#define _LARGEFILE64_SOURCE
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <inttypes.h>
#include <errno.h>
#include "flash.h"
#include "programmer.h"
#include "hwaccess.h"
#define NOT_DONE_YET 1
#if defined(__i386__) || defined(__x86_64__)
static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
{
uint8_t tmp;
/*
* ROM Write enable, 0xFFFC0000-0xFFFDFFFF and
* 0xFFFE0000-0xFFFFFFFF ROM select enable.
*/
tmp = pci_read_byte(dev, 0x47);
tmp |= 0x46;
rpci_write_byte(dev, 0x47, tmp);
return 0;
}
static int enable_flash_rdc_r8610(struct pci_dev *dev, const char *name)
{
uint8_t tmp;
/* enable ROMCS for writes */
tmp = pci_read_byte(dev, 0x43);
tmp |= 0x80;
pci_write_byte(dev, 0x43, tmp);
/* read the bootstrapping register */
tmp = pci_read_byte(dev, 0x40) & 0x3;
switch (tmp) {
case 3:
internal_buses_supported = BUS_FWH;
break;
case 2:
internal_buses_supported = BUS_LPC;
break;
default:
internal_buses_supported = BUS_PARALLEL;
break;
}
return 0;
}
static int enable_flash_sis85c496(struct pci_dev *dev, const char *name)
{
uint8_t tmp;
tmp = pci_read_byte(dev, 0xd0);
tmp |= 0xf8;
rpci_write_byte(dev, 0xd0, tmp);
return 0;
}
static int enable_flash_sis_mapping(struct pci_dev *dev, const char *name)
{
#define SIS_MAPREG 0x40
uint8_t new, newer;
/* Extended BIOS enable = 1, Lower BIOS Enable = 1 */
/* This is 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */
new = pci_read_byte(dev, SIS_MAPREG);
new &= (~0x04); /* No idea why we clear bit 2. */
new |= 0xb; /* 0x3 for some chipsets, bit 7 seems to be don't care. */
rpci_write_byte(dev, SIS_MAPREG, new);
newer = pci_read_byte(dev, SIS_MAPREG);
if (newer != new) { /* FIXME: share this with other code? */
msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n",
SIS_MAPREG, new, name);
msg_pinfo("Stuck at 0x%02x.\n", newer);
return -1;
}
return 0;
}
static struct pci_dev *find_southbridge(uint16_t vendor, const char *name)
{
struct pci_dev *sbdev;
sbdev = pci_dev_find_vendorclass(vendor, 0x0601);
if (!sbdev)
sbdev = pci_dev_find_vendorclass(vendor, 0x0680);
if (!sbdev)
sbdev = pci_dev_find_vendorclass(vendor, 0x0000);
if (!sbdev)
msg_perr("No southbridge found for %s!\n", name);
if (sbdev)
msg_pdbg("Found southbridge %04x:%04x at %02x:%02x:%01x\n",
sbdev->vendor_id, sbdev->device_id,
sbdev->bus, sbdev->dev, sbdev->func);
return sbdev;
}
static int enable_flash_sis501(struct pci_dev *dev, const char *name)
{
uint8_t tmp;
int ret = 0;
struct pci_dev *sbdev;
sbdev = find_southbridge(dev->vendor_id, name);
if (!sbdev)
return -1;
ret = enable_flash_sis_mapping(sbdev, name);
tmp = sio_read(0x22, 0x80);
tmp &= (~0x20);
tmp |= 0x4;
sio_write(0x22, 0x80, tmp);
tmp = sio_read(0x22, 0x70);
tmp &= (~0x20);
tmp |= 0x4;
sio_write(0x22, 0x70, tmp);
return ret;
}
static int enable_flash_sis5511(struct pci_dev *dev, const char *name)
{
uint8_t tmp;
int ret = 0;
struct pci_dev *sbdev;
sbdev = find_southbridge(dev->vendor_id, name);
if (!sbdev)
return -1;
ret = enable_flash_sis_mapping(sbdev, name);
tmp = sio_read(0x22, 0x50);
tmp &= (~0x20);
tmp |= 0x4;
sio_write(0x22, 0x50, tmp);
return ret;
}
static int enable_flash_sis5x0(struct pci_dev *dev, const char *name, uint8_t dis_mask, uint8_t en_mask)
{
#define SIS_REG 0x45
uint8_t new, newer;
int ret = 0;
struct pci_dev *sbdev;
sbdev = find_southbridge(dev->vendor_id, name);
if (!sbdev)
return -1;
ret = enable_flash_sis_mapping(sbdev, name);
new = pci_read_byte(sbdev, SIS_REG);
new &= (~dis_mask);
new |= en_mask;
rpci_write_byte(sbdev, SIS_REG, new);
newer = pci_read_byte(sbdev, SIS_REG);
if (newer != new) { /* FIXME: share this with other code? */
msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", SIS_REG, new, name);
msg_pinfo("Stuck at 0x%02x\n", newer);
ret = -1;
}
return ret;
}
static int enable_flash_sis530(struct pci_dev *dev, const char *name)
{
return enable_flash_sis5x0(dev, name, 0x20, 0x04);
}
static int enable_flash_sis540(struct pci_dev *dev, const char *name)
{
return enable_flash_sis5x0(dev, name, 0x80, 0x40);
}
/* Datasheet:
* - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
* - URL: http://www.intel.com/design/intarch/datashts/290562.htm
* - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
* - Order Number: 290562-001
*/
static int enable_flash_piix4(struct pci_dev *dev, const char *name)
{
uint16_t old, new;
uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
internal_buses_supported = BUS_PARALLEL;
old = pci_read_word(dev, xbcs);
/* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
* FFF00000-FFF7FFFF are forwarded to ISA).
* Note: This bit is reserved on PIIX/PIIX3/MPIIX.
* Set bit 7: Extended BIOS Enable (PCI master accesses to
* FFF80000-FFFDFFFF are forwarded to ISA).
* Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
* the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
* of 1 Mbyte, or the aliases at the top of 4 Gbyte
* (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
* Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
* Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
*/
if (dev->device_id == 0x122e || dev->device_id == 0x7000
|| dev->device_id == 0x1234)
new = old | 0x00c4; /* PIIX/PIIX3/MPIIX: Bit 9 is reserved. */
else
new = old | 0x02c4;
if (new == old)
return 0;
rpci_write_word(dev, xbcs, new);
if (pci_read_word(dev, xbcs) != new) { /* FIXME: share this with other code? */
msg_pinfo("Setting register 0x%04x to 0x%04x on %s failed (WARNING ONLY).\n", xbcs, new, name);
return -1;
}
return 0;
}
/*
* See ie. page 375 of "Intel I/O Controller Hub 7 (ICH7) Family Datasheet"
* http://download.intel.com/design/chipsets/datashts/30701303.pdf
*/
static int enable_flash_ich(struct pci_dev *dev, const char *name, uint8_t bios_cntl)
{
uint8_t old, new, wanted;
/*
* Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, in Tunnel Creek it is even 32b, but
* just treating it as 8 bit wide seems to work fine in practice.
*/
wanted = old = pci_read_byte(dev, bios_cntl);
/*
* Quote from the 6 Series datasheet (Document Number: 324645-004):
* "Bit 5: SMM BIOS Write Protect Disable (SMM_BWP)
* 1 = BIOS region SMM protection is enabled.
* The BIOS Region is not writable unless all processors are in SMM."
* In earlier chipsets this bit is reserved.
*
* Try to unset it in any case.
* It won't hurt and makes sense in some cases according to Stefan Reinauer.
*/
wanted &= ~(1 << 5);
/* Set BIOS Write Enable */
wanted |= (1 << 0);
/* Only write the register if it's necessary */
if (wanted != old) {
rpci_write_byte(dev, bios_cntl, wanted);
new = pci_read_byte(dev, bios_cntl);
} else
new = old;
msg_pdbg("\nBIOS_CNTL = 0x%02x: ", new);
msg_pdbg("BIOS Lock Enable: %sabled, ", (new & (1 << 1)) ? "en" : "dis");
msg_pdbg("BIOS Write Enable: %sabled\n", (new & (1 << 0)) ? "en" : "dis");
if (new & (1 << 5))
msg_pwarn("Warning: BIOS region SMM protection is enabled!\n");
if (new != wanted)
msg_pwarn("Warning: Setting Bios Control at 0x%x from 0x%02x to 0x%02x on %s failed.\n"
"New value is 0x%02x.\n", bios_cntl, old, wanted, name, new);
/* Return an error if we could not set the write enable */
if (!(new & (1 << 0)))
return -1;
return 0;
}
static int enable_flash_ich_4e(struct pci_dev *dev, const char *name)
{
/*
* Note: ICH5 has registers similar to FWH_SEL1, FWH_SEL2 and
* FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and
* FB_DEC_EN2.
*/
internal_buses_supported = BUS_FWH;
return enable_flash_ich(dev, name, 0x4e);
}
static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
{
uint32_t fwh_conf;
int i, tmp;
char *idsel = NULL;
int max_decode_fwh_idsel = 0, max_decode_fwh_decode = 0;
int contiguous = 1;
idsel = extract_programmer_param("fwh_idsel");
if (idsel && strlen(idsel)) {
uint64_t fwh_idsel_old, fwh_idsel;
errno = 0;
/* Base 16, nothing else makes sense. */
fwh_idsel = (uint64_t)strtoull(idsel, NULL, 16);
if (errno) {
msg_perr("Error: fwh_idsel= specified, but value could "
"not be converted.\n");
goto idsel_garbage_out;
}
if (fwh_idsel & 0xffff000000000000ULL) {
msg_perr("Error: fwh_idsel= specified, but value had "
"unused bits set.\n");
goto idsel_garbage_out;
}
fwh_idsel_old = pci_read_long(dev, 0xd0);
fwh_idsel_old <<= 16;
fwh_idsel_old |= pci_read_word(dev, 0xd4);
msg_pdbg("\nSetting IDSEL from 0x%012" PRIx64 " to "
"0x%012" PRIx64 " for top 16 MB.", fwh_idsel_old,
fwh_idsel);
rpci_write_long(dev, 0xd0, (fwh_idsel >> 16) & 0xffffffff);
rpci_write_word(dev, 0xd4, fwh_idsel & 0xffff);
/* FIXME: Decode settings are not changed. */
} else if (idsel) {
msg_perr("Error: fwh_idsel= specified, but no value given.\n");
idsel_garbage_out:
free(idsel);
return ERROR_FATAL;
}
free(idsel);
/* Ignore all legacy ranges below 1 MB.
* We currently only support flashing the chip which responds to
* IDSEL=0. To support IDSEL!=0, flashbase and decode size calculations
* have to be adjusted.
*/
/* FWH_SEL1 */
fwh_conf = pci_read_long(dev, 0xd0);
for (i = 7; i >= 0; i--) {
tmp = (fwh_conf >> (i * 4)) & 0xf;
msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
(0x1ff8 + i) * 0x80000,
(0x1ff0 + i) * 0x80000,
tmp);
if ((tmp == 0) && contiguous) {
max_decode_fwh_idsel = (8 - i) * 0x80000;
} else {
contiguous = 0;
}
}
/* FWH_SEL2 */
fwh_conf = pci_read_word(dev, 0xd4);
for (i = 3; i >= 0; i--) {
tmp = (fwh_conf >> (i * 4)) & 0xf;
msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
(0xff4 + i) * 0x100000,
(0xff0 + i) * 0x100000,
tmp);
if ((tmp == 0) && contiguous) {
max_decode_fwh_idsel = (8 - i) * 0x100000;
} else {
contiguous = 0;
}
}
contiguous = 1;
/* FWH_DEC_EN1 */
fwh_conf = pci_read_word(dev, 0xd8);
for (i = 7; i >= 0; i--) {
tmp = (fwh_conf >> (i + 0x8)) & 0x1;
msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled",
(0x1ff8 + i) * 0x80000,
(0x1ff0 + i) * 0x80000,
tmp ? "en" : "dis");
if ((tmp == 1) && contiguous) {
max_decode_fwh_decode = (8 - i) * 0x80000;
} else {
contiguous = 0;
}
}
for (i = 3; i >= 0; i--) {
tmp = (fwh_conf >> i) & 0x1;
msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled",
(0xff4 + i) * 0x100000,
(0xff0 + i) * 0x100000,
tmp ? "en" : "dis");
if ((tmp == 1) && contiguous) {
max_decode_fwh_decode = (8 - i) * 0x100000;
} else {
contiguous = 0;
}
}
max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode);
msg_pdbg("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh);
/* If we're called by enable_flash_ich_dc_spi, it will override
* internal_buses_supported anyway.
*/
internal_buses_supported = BUS_FWH;
return enable_flash_ich(dev, name, 0xdc);
}
static int enable_flash_poulsbo(struct pci_dev *dev, const char *name)
{
uint16_t old, new;
int err;
if ((err = enable_flash_ich(dev, name, 0xd8)) != 0)
return err;
old = pci_read_byte(dev, 0xd9);
msg_pdbg("BIOS Prefetch Enable: %sabled, ",
(old & 1) ? "en" : "dis");
new = old & ~1;
if (new != old)
rpci_write_byte(dev, 0xd9, new);
internal_buses_supported = BUS_FWH;
return 0;
}
static int enable_flash_tunnelcreek(struct pci_dev *dev, const char *name)
{
uint16_t old, new;
uint32_t tmp, bnt;
void *rcrb;
int ret;
/* Enable Flash Writes */
ret = enable_flash_ich(dev, name, 0xd8);
if (ret == ERROR_FATAL)
return ret;
/* Make sure BIOS prefetch mechanism is disabled */
old = pci_read_byte(dev, 0xd9);
msg_pdbg("BIOS Prefetch Enable: %sabled, ", (old & 1) ? "en" : "dis");
new = old & ~1;
if (new != old)
rpci_write_byte(dev, 0xd9, new);
/* Get physical address of Root Complex Register Block */
tmp = pci_read_long(dev, 0xf0) & 0xffffc000;
msg_pdbg("\nRoot Complex Register Block address = 0x%x\n", tmp);
/* Map RCBA to virtual memory */
rcrb = physmap("ICH RCRB", tmp, 0x4000);
/* Test Boot BIOS Strap Status */
bnt = mmio_readl(rcrb + 0x3410);
if (bnt & 0x02) {
/* If strapped to LPC, no SPI initialization is required */
internal_buses_supported = BUS_FWH;
return 0;
}
/* This adds BUS_SPI */
if (ich_init_spi(dev, tmp, rcrb, 7) != 0) {
if (!ret)
ret = ERROR_NONFATAL;
}
return ret;
}
static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
enum ich_chipset ich_generation)
{
int ret, ret_spi;
uint8_t bbs, buc;
uint32_t tmp, gcs;
void *rcrb;
const char *const *straps_names;
static const char *const straps_names_EP80579[] = { "SPI", "reserved", "reserved", "LPC" };
static const char *const straps_names_ich7_nm10[] = { "reserved", "SPI", "PCI", "LPC" };
static const char *const straps_names_ich8910[] = { "SPI", "SPI", "PCI", "LPC" };
static const char *const straps_names_pch567[] = { "LPC", "reserved", "PCI", "SPI" };
static const char *const straps_names_pch8[] = { "LPC", "reserved", "reserved", "SPI" };
static const char *const straps_names_pch8_lp[] = { "SPI", "LPC", "unknown", "unknown" };
static const char *const straps_names_unknown[] = { "unknown", "unknown", "unknown", "unknown" };
switch (ich_generation) {
case CHIPSET_ICH7:
/* EP80579 may need further changes, but this is the least
* intrusive way to get correct BOOT Strap printing without
* changing the rest of its code path). */
if (strcmp(name, "EP80579") == 0)
straps_names = straps_names_EP80579;
else
straps_names = straps_names_ich7_nm10;
break;
case CHIPSET_ICH8:
case CHIPSET_ICH9:
case CHIPSET_ICH10:
straps_names = straps_names_ich8910;
break;
case CHIPSET_5_SERIES_IBEX_PEAK:
case CHIPSET_6_SERIES_COUGAR_POINT:
case CHIPSET_7_SERIES_PANTHER_POINT:
straps_names = straps_names_pch567;
break;
case CHIPSET_8_SERIES_LYNX_POINT:
straps_names = straps_names_pch8;
break;
case CHIPSET_8_SERIES_LYNX_POINT_LP:
straps_names = straps_names_pch8_lp;
break;
case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet
straps_names = straps_names_unknown;
break;
default:
msg_gerr("%s: unknown ICH generation. Please report!\n",
__func__);
straps_names = straps_names_unknown;
break;
}
/* Enable Flash Writes */
ret = enable_flash_ich_dc(dev, name);
if (ret == ERROR_FATAL)
return ret;
/* Get physical address of Root Complex Register Block */
tmp = pci_read_long(dev, 0xf0) & 0xffffc000;
msg_pdbg("Root Complex Register Block address = 0x%x\n", tmp);
/* Map RCBA to virtual memory */
rcrb = physmap("ICH RCRB", tmp, 0x4000);
gcs = mmio_readl(rcrb + 0x3410);
msg_pdbg("GCS = 0x%x: ", gcs);
msg_pdbg("BIOS Interface Lock-Down: %sabled, ",
(gcs & 0x1) ? "en" : "dis");
switch (ich_generation) {
case CHIPSET_8_SERIES_LYNX_POINT_LP:
case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet
/* Lynx Point LP uses a single bit for GCS */
bbs = (gcs >> 10) & 0x1;
break;
default:
/* Older chipsets use two bits for GCS */
bbs = (gcs >> 10) & 0x3;
break;
}
msg_pdbg("Boot BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]);
buc = mmio_readb(rcrb + 0x3414);
msg_pdbg("Top Swap : %s\n",
(buc & 1) ? "enabled (A16 inverted)" : "not enabled");
/* It seems the ICH7 does not support SPI and LPC chips at the same
* time. At least not with our current code. So we prevent searching
* on ICH7 when the southbridge is strapped to LPC
*/
internal_buses_supported = BUS_FWH;
if (ich_generation == CHIPSET_ICH7) {
if (bbs == 0x03) {
/* If strapped to LPC, no further SPI initialization is
* required. */
return ret;
} else {
/* Disable LPC/FWH if strapped to PCI or SPI */
internal_buses_supported = BUS_NONE;
}
}
/* This adds BUS_SPI */
ret_spi = ich_init_spi(dev, tmp, rcrb, ich_generation);
if (ret_spi == ERROR_FATAL)
return ret_spi;
if (ret || ret_spi)
ret = ERROR_NONFATAL;
return ret;
}
static int enable_flash_ich7(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_dc_spi(dev, name, CHIPSET_ICH7);
}
static int enable_flash_ich8(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_dc_spi(dev, name, CHIPSET_ICH8);
}
static int enable_flash_ich9(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_dc_spi(dev, name, CHIPSET_ICH9);
}
static int enable_flash_ich10(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_dc_spi(dev, name, CHIPSET_ICH10);
}
/* Ibex Peak aka. 5 series & 3400 series */
static int enable_flash_pch5(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_dc_spi(dev, name, CHIPSET_5_SERIES_IBEX_PEAK);
}
/* Cougar Point aka. 6 series & c200 series */
static int enable_flash_pch6(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_dc_spi(dev, name, CHIPSET_6_SERIES_COUGAR_POINT);
}
/* Panther Point aka. 7 series */
static int enable_flash_pch7(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_dc_spi(dev, name, CHIPSET_7_SERIES_PANTHER_POINT);
}
/* Lynx Point aka. 8 series */
static int enable_flash_pch8(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_dc_spi(dev, name, CHIPSET_8_SERIES_LYNX_POINT);
}
/* Lynx Point aka. 8 series low-power */
static int enable_flash_pch8_lp(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_dc_spi(dev, name, CHIPSET_8_SERIES_LYNX_POINT_LP);
}
/* Wellsburg (for Haswell-EP Xeons) */
static int enable_flash_pch8_wb(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_dc_spi(dev, name, CHIPSET_8_SERIES_WELLSBURG);
}
static int via_no_byte_merge(struct pci_dev *dev, const char *name)
{
uint8_t val;
val = pci_read_byte(dev, 0x71);
if (val & 0x40) {
msg_pdbg("Disabling byte merging\n");
val &= ~0x40;
rpci_write_byte(dev, 0x71, val);
}
return NOT_DONE_YET; /* need to find south bridge, too */
}
static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
{
uint8_t val;
/* Enable ROM decode range (1MB) FFC00000 - FFFFFFFF. */
rpci_write_byte(dev, 0x41, 0x7f);
/* ROM write enable */
val = pci_read_byte(dev, 0x40);
val |= 0x10;
rpci_write_byte(dev, 0x40, val);
if (pci_read_byte(dev, 0x40) != val) {
msg_pwarn("\nWarning: Failed to enable flash write on \"%s\"\n", name);
return -1;
}
if (dev->device_id == 0x3227) { /* VT8237/VT8237R */
/* All memory cycles, not just ROM ones, go to LPC. */
val = pci_read_byte(dev, 0x59);
val &= ~0x80;
rpci_write_byte(dev, 0x59, val);
}
return 0;
}
static int enable_flash_vt_vx(struct pci_dev *dev, const char *name)
{
struct pci_dev *south_north = pci_dev_find(0x1106, 0xa353);
if (south_north == NULL) {
msg_perr("Could not find South-North Module Interface Control device!\n");
return ERROR_FATAL;
}
msg_pdbg("Strapped to ");
if ((pci_read_byte(south_north, 0x56) & 0x01) == 0) {
msg_pdbg("LPC.\n");
return enable_flash_vt823x(dev, name);
}
msg_pdbg("SPI.\n");
uint32_t mmio_base;
void *mmio_base_physmapped;
uint32_t spi_cntl;
#define SPI_CNTL_LEN 0x08
uint32_t spi0_mm_base = 0;
switch(dev->device_id) {
case 0x8353: /* VX800/VX820 */
spi0_mm_base = pci_read_long(dev, 0xbc) << 8;
break;
case 0x8409: /* VX855/VX875 */
case 0x8410: /* VX900 */
mmio_base = pci_read_long(dev, 0xbc) << 8;
mmio_base_physmapped = physmap("VIA VX MMIO register", mmio_base, SPI_CNTL_LEN);
if (mmio_base_physmapped == ERROR_PTR) {
physunmap(mmio_base_physmapped, SPI_CNTL_LEN);
return ERROR_FATAL;
}
/* Offset 0 - Bit 0 holds SPI Bus0 Enable Bit. */
spi_cntl = mmio_readl(mmio_base_physmapped) + 0x00;
if ((spi_cntl & 0x01) == 0) {
msg_pdbg ("SPI Bus0 disabled!\n");
physunmap(mmio_base_physmapped, SPI_CNTL_LEN);
return ERROR_FATAL;
}
/* Offset 1-3 has SPI Bus Memory Map Base Address: */
spi0_mm_base = spi_cntl & 0xFFFFFF00;
/* Offset 4 - Bit 0 holds SPI Bus1 Enable Bit. */
spi_cntl = mmio_readl(mmio_base_physmapped) + 0x04;
if ((spi_cntl & 0x01) == 1)
msg_pdbg2("SPI Bus1 is enabled too.\n");
physunmap(mmio_base_physmapped, SPI_CNTL_LEN);
break;
default:
msg_perr("%s: Unsupported chipset %x:%x!\n", __func__, dev->vendor_id, dev->device_id);
return ERROR_FATAL;
}
return via_init_spi(dev, spi0_mm_base);
}
static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name)
{
return via_init_spi(dev, pci_read_long(dev, 0xbc) << 8);
}
static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
{
uint8_t reg8;
#define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
#define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
#define CS5530_RESET_CONTROL_REG 0x44 /* F0 index 0x44 */
#define CS5530_USB_SHADOW_REG 0x43 /* F0 index 0x43 */
#define LOWER_ROM_ADDRESS_RANGE (1 << 0)
#define ROM_WRITE_ENABLE (1 << 1)
#define UPPER_ROM_ADDRESS_RANGE (1 << 2)
#define BIOS_ROM_POSITIVE_DECODE (1 << 5)
#define CS5530_ISA_MASTER (1 << 7)
#define CS5530_ENABLE_SA2320 (1 << 2)
#define CS5530_ENABLE_SA20 (1 << 6)
internal_buses_supported = BUS_PARALLEL;
/* Decode 0x000E0000-0x000FFFFF (128 kB), not just 64 kB, and
* decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 kB.
* FIXME: Should we really touch the low mapping below 1 MB? Flashrom
* ignores that region completely.
* Make the configured ROM areas writable.
*/
reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG);
reg8 |= LOWER_ROM_ADDRESS_RANGE;
reg8 |= UPPER_ROM_ADDRESS_RANGE;
reg8 |= ROM_WRITE_ENABLE;
rpci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
/* Set positive decode on ROM. */
reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2);
reg8 |= BIOS_ROM_POSITIVE_DECODE;
rpci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
reg8 = pci_read_byte(dev, CS5530_RESET_CONTROL_REG);
if (reg8 & CS5530_ISA_MASTER) {
/* We have A0-A23 available. */
max_rom_decode.parallel = 16 * 1024 * 1024;
} else {
reg8 = pci_read_byte(dev, CS5530_USB_SHADOW_REG);
if (reg8 & CS5530_ENABLE_SA2320) {
/* We have A0-19, A20-A23 available. */
max_rom_decode.parallel = 16 * 1024 * 1024;
} else if (reg8 & CS5530_ENABLE_SA20) {
/* We have A0-19, A20 available. */
max_rom_decode.parallel = 2 * 1024 * 1024;
} else {
/* A20 and above are not active. */
max_rom_decode.parallel = 1024 * 1024;
}
}
return 0;
}
/*
* Geode systems write protect the BIOS via RCONFs (cache settings similar
* to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22.
*
* Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
* To enable write to NOR Boot flash for the benefit of systems that have such
* a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
*/
static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
{
#define MSR_RCONF_DEFAULT 0x1808
#define MSR_NORF_CTL 0x51400018
msr_t msr;
/* Geode only has a single core */
if (setup_cpu_msr(0))
return -1;
msr = rdmsr(MSR_RCONF_DEFAULT);
if ((msr.hi >> 24) != 0x22) {
msr.hi &= 0xfbffffff;
wrmsr(MSR_RCONF_DEFAULT, msr);
}
msr = rdmsr(MSR_NORF_CTL);
/* Raise WE_CS3 bit. */
msr.lo |= 0x08;
wrmsr(MSR_NORF_CTL, msr);
cleanup_cpu_msr();
#undef MSR_RCONF_DEFAULT
#undef MSR_NORF_CTL
return 0;
}
static int enable_flash_sc1100(struct pci_dev *dev, const char *name)
{
#define SC_REG 0x52
uint8_t new;
rpci_write_byte(dev, SC_REG, 0xee);
new = pci_read_byte(dev, SC_REG);
if (new != 0xee) { /* FIXME: share this with other code? */
msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", SC_REG, new, name);
return -1;
}
return 0;
}
/* Works for AMD-8111, VIA VT82C586A/B, VIA VT82C686A/B. */
static int enable_flash_amd8111(struct pci_dev *dev, const char *name)
{
#define AMD_MAPREG 0x43
#define AMD_ENREG 0x40
uint8_t old, new;
/* Enable decoding at 0xffb00000 to 0xffffffff. */
old = pci_read_byte(dev, AMD_MAPREG);
new = old | 0xC0;
if (new != old) {
rpci_write_byte(dev, AMD_MAPREG, new);
if (pci_read_byte(dev, AMD_MAPREG) != new) {
msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n",
AMD_MAPREG, new, name);
}
}
/* Enable 'ROM write' bit. */
old = pci_read_byte(dev, AMD_ENREG);
new = old | 0x01;
if (new == old)
return 0;
rpci_write_byte(dev, AMD_ENREG, new);
if (pci_read_byte(dev, AMD_ENREG) != new) {
msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n",
AMD_ENREG, new, name);
return -1;
}
return 0;
}
static int enable_flash_sb600(struct pci_dev *dev, const char *name)
{
uint32_t prot;
uint8_t reg;
int ret;
/* Clear ROM protect 0-3. */
for (reg = 0x50; reg < 0x60; reg += 4) {
prot = pci_read_long(dev, reg);
/* No protection flags for this region?*/
if ((prot & 0x3) == 0)
continue;
msg_pinfo("SB600 %s%sprotected from 0x%08x to 0x%08x\n",
(prot & 0x1) ? "write " : "",
(prot & 0x2) ? "read " : "",
(prot & 0xfffff800),
(prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
prot &= 0xfffffffc;
rpci_write_byte(dev, reg, prot);
prot = pci_read_long(dev, reg);
if (prot & 0x3)
msg_perr("SB600 %s%sunprotect failed from 0x%08x to 0x%08x\n",
(prot & 0x1) ? "write " : "",
(prot & 0x2) ? "read " : "",
(prot & 0xfffff800),
(prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
}
internal_buses_supported = BUS_LPC | BUS_FWH;
ret = sb600_probe_spi(dev);
/* Read ROM strap override register. */
OUTB(0x8f, 0xcd6);
reg = INB(0xcd7);
reg &= 0x0e;
msg_pdbg("ROM strap override is %sactive", (reg & 0x02) ? "" : "not ");
if (reg & 0x02) {
switch ((reg & 0x0c) >> 2) {
case 0x00:
msg_pdbg(": LPC");
break;
case 0x01:
msg_pdbg(": PCI");
break;
case 0x02:
msg_pdbg(": FWH");
break;
case 0x03:
msg_pdbg(": SPI");
break;
}
}
msg_pdbg("\n");
/* Force enable SPI ROM in SB600 PM register.
* If we enable SPI ROM here, we have to disable it after we leave.
* But how can we know which ROM we are going to handle? So we have
* to trade off. We only access LPC ROM if we boot via LPC ROM. And
* only SPI ROM if we boot via SPI ROM. If you want to access SPI on
* boards with LPC straps, you have to use the code below.
*/
/*
OUTB(0x8f, 0xcd6);
OUTB(0x0e, 0xcd7);
*/
return ret;
}
/* sets bit 0 in 0x6d */
static int enable_flash_nvidia_common(struct pci_dev *dev, const char *name)
{
uint8_t old, new;
old = pci_read_byte(dev, 0x6d);
new = old | 0x01;
if (new == old)
return 0;
rpci_write_byte(dev, 0x6d, new);
if (pci_read_byte(dev, 0x6d) != new) {