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dummy.ptx
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dummy.ptx
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//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-34097967
// Cuda compilation tools, release 12.4, V12.4.131
// Based on NVVM 7.0.1
//
.version 8.4
.target sm_90a
.address_size 64
// .globl _Z14add_one_kernelPim
// _ZZ14add_one_kernelPimE9smem_data has been demoted
// _ZZ14add_one_kernelPimE3bar has been demoted
//dummy.cu:5 __global__ void add_one_kernel(int* data, size_t offset)
.visible .entry _Z14add_one_kernelPim(
.param .u64 _Z14add_one_kernelPim_param_0,
.param .u64 _Z14add_one_kernelPim_param_1
)
{
.reg .pred %p<10>;
.reg .b32 %r<29>;
.reg .b64 %rd<19>;
// demoted variable
.shared .align 16 .b8 _ZZ14add_one_kernelPimE9smem_data[4096];
// demoted variable
.shared .align 8 .b8 _ZZ14add_one_kernelPimE3bar[8];
ld.param.u64 %rd4, [_Z14add_one_kernelPim_param_0];
ld.param.u64 %rd5, [_Z14add_one_kernelPim_param_1];
mov.u32 %r28, %tid.x;
setp.ne.s32 %p1, %r28, 0;
@%p1 bra $L__BB0_2;
mov.u32 %r8, %ntid.x;
mov.u32 %r7, _ZZ14add_one_kernelPimE3bar;
// begin inline asm
mbarrier.init.shared.b64 [%r7], %r8;
// end inline asm
// begin inline asm
fence.proxy.async.shared::cta;
// end inline asm
$L__BB0_2:
bar.sync 0;
@%p1 bra $L__BB0_4;
cvta.to.global.u64 %rd7, %rd4;
shl.b64 %rd8, %rd5, 2;
add.s64 %rd6, %rd7, %rd8;
mov.u32 %r9, _ZZ14add_one_kernelPimE9smem_data;
mov.u32 %r13, 4096;
mov.u32 %r11, _ZZ14add_one_kernelPimE3bar;
// begin inline asm
cp.async.bulk.shared::cluster.global.mbarrier::complete_tx::bytes [%r9], [%rd6], %r13, [%r11];
// end inline asm
// begin inline asm
mbarrier.expect_tx.relaxed.cta.shared::cta.b64 [%r11], %r13;
// end inline asm
$L__BB0_4:
mov.u32 %r14, _ZZ14add_one_kernelPimE3bar;
mov.u32 %r15, 1;
// begin inline asm
mbarrier.arrive.shared::cta.b64 %rd9, [%r14], %r15; // 2.
// end inline asm
// begin inline asm
mov.u64 %rd10, %globaltimer;
// end inline asm
mov.u32 %r27, 0;
bra.uni $L__BB0_5;
$L__BB0_17:
add.s32 %r27, %r27, 1;
$L__BB0_5:
// begin inline asm
{
.reg .pred p;
mbarrier.try_wait.shared.b64 p, [%r14], %rd9;
selp.b32 %r17, 1, 0, p;
}
// end inline asm
setp.eq.s32 %p3, %r17, 0;
@%p3 bra $L__BB0_12;
bra.uni $L__BB0_6;
$L__BB0_12:
setp.lt.s32 %p7, %r27, 16;
@%p7 bra $L__BB0_17;
// begin inline asm
mov.u64 %rd14, %globaltimer;
// end inline asm
sub.s64 %rd3, %rd14, %rd10;
setp.lt.s64 %p8, %rd3, 4000000;
@%p8 bra $L__BB0_15;
bra.uni $L__BB0_14;
$L__BB0_15:
setp.lt.s64 %p9, %rd3, 40000;
@%p9 bra $L__BB0_5;
shr.s64 %rd15, %rd3, 63;
shr.u64 %rd16, %rd15, 62;
add.s64 %rd17, %rd3, %rd16;
shr.u64 %rd18, %rd17, 2;
cvt.u32.u64 %r26, %rd18;
// begin inline asm
nanosleep.u32 %r26;
// end inline asm
bra.uni $L__BB0_5;
$L__BB0_14:
mov.u32 %r25, 1000000;
// begin inline asm
nanosleep.u32 %r25;
// end inline asm
bra.uni $L__BB0_5;
$L__BB0_6:
setp.gt.u32 %p4, %r28, 1023;
@%p4 bra $L__BB0_9;
mov.u32 %r3, %ntid.x;
mov.u32 %r20, _ZZ14add_one_kernelPimE9smem_data;
$L__BB0_8:
shl.b32 %r19, %r28, 2;
add.s32 %r21, %r20, %r19;
ld.shared.u32 %r22, [%r21];
add.s32 %r23, %r22, 1;
st.shared.u32 [%r21], %r23;
add.s32 %r28, %r28, %r3;
setp.lt.u32 %p5, %r28, 1024;
@%p5 bra $L__BB0_8;
$L__BB0_9:
// begin inline asm
fence.proxy.async.shared::cta;
// end inline asm
bar.sync 0;
@%p1 bra $L__BB0_11;
shl.b64 %rd13, %rd5, 2;
add.s64 %rd12, %rd4, %rd13;
mov.u32 %r24, _ZZ14add_one_kernelPimE9smem_data;
// begin inline asm
cp.async.bulk.global.shared::cta.bulk_group [%rd12], [%r24], 4096;
// end inline asm
// begin inline asm
cp.async.bulk.commit_group;
// end inline asm
// begin inline asm
cp.async.bulk.wait_group.read 0;
// end inline asm
$L__BB0_11:
ret;
}