From 36a0db0e342e3f406798ca56dd79e79433bf5ebb Mon Sep 17 00:00:00 2001 From: Andrew Dennison Date: Sat, 2 Sep 2023 11:44:09 +1000 Subject: [PATCH] vexrisc_smp: fix DMA bus address_width calculation --- litex/soc/cores/cpu/vexriscv_smp/core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py index 18780e187e..47f0f5aee6 100755 --- a/litex/soc/cores/cpu/vexriscv_smp/core.py +++ b/litex/soc/cores/cpu/vexriscv_smp/core.py @@ -337,7 +337,7 @@ def __init__(self, platform, variant): # DMA. if VexRiscvSMP.coherent_dma: - self.dma_bus = dma_bus = wishbone.Interface(data_width=VexRiscvSMP.dcache_width) + self.dma_bus = dma_bus = wishbone.Interface(data_width=VexRiscvSMP.dcache_width, address_width=32) dma_bus_stall = Signal() dma_bus_inhibit = Signal() self.cpu_params.update(