From 27fde8b549dfaf671ca97e55eb32172b3f67118f Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 27 Jul 2023 11:42:49 +0200 Subject: [PATCH] stream: Switch back to LiteX FIFO, but add an additional output buffer, seems to be working... --- litex/soc/interconnect/stream.py | 32 ++++++++++++++++++-------------- 1 file changed, 18 insertions(+), 14 deletions(-) diff --git a/litex/soc/interconnect/stream.py b/litex/soc/interconnect/stream.py index 6e035bcd64..22b58095a6 100644 --- a/litex/soc/interconnect/stream.py +++ b/litex/soc/interconnect/stream.py @@ -281,25 +281,29 @@ def __init__(self, layout, depth, buffered): #from verilog_axis.axis_async_fifo import AXISAsyncFIFO #AXISAsyncFIFO.add_sources(platform) -class AsyncFIFO(_AsyncFIFOWrapper): +#class AsyncFIFO(_AsyncFIFOWrapper): +# def __init__(self, layout, depth=None, buffered=False): +# depth = 4 if depth is None else depth +# assert depth >= 4 +# buffered = True +# _AsyncFIFOWrapper.__init__(self, +# layout = layout, +# depth = depth, +# buffered = buffered +# ) + +class AsyncFIFO(_FIFOWrapper): def __init__(self, layout, depth=None, buffered=False): depth = 4 if depth is None else depth assert depth >= 4 - buffered = True - _AsyncFIFOWrapper.__init__(self, + buffered = True # FIXME: Required on Efinix... + _FIFOWrapper.__init__(self, + fifo_class = fifo.AsyncFIFOBuffered if buffered else fifo.AsyncFIFO, layout = layout, - depth = depth, - buffered = buffered + depth = depth ) - -#class AsyncFIFO(_FIFOWrapper): -# def __init__(self, layout, depth=None, buffered=False): -# depth = 4 if depth is None else depth -# assert depth >= 4 -# _FIFOWrapper.__init__(self, -# fifo_class = fifo.AsyncFIFOBuffered if buffered else fifo.AsyncFIFO, -# layout = layout, -# depth = depth) + # FIXME: Additional buffer required on Efinix... + ClockDomainsRenamer("read")(BufferizeEndpoints({"source": DIR_SOURCE})(self)) # ClockDomainCrossing ------------------------------------------------------------------------------