diff --git a/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
index 349cac96..75956785 100644
--- a/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /*
  *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
  *
diff --git a/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
index 5d7fd112..c4870ff6 100644
--- a/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /*	
 	StriVe housekeeping SPI testbench.
 */
diff --git a/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v b/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
index eac5e680..5cb7e87e 100644
--- a/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /*
  *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
  *
diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
index f8de811c..7a1ec297 100644
--- a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 
 `timescale 1 ns / 1 ps
 
diff --git a/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v b/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
index ef215a25..70086655 100644
--- a/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /*	
  *	StriVe housekeeping pass-thru mode SPI testbench.
  */
diff --git a/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v b/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
index ca86f6d9..fdc1ded0 100644
--- a/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /*
  *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
  *
diff --git a/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v b/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
index d9448e96..95f461a5 100644
--- a/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 
 `timescale 1 ns / 1 ps
 
diff --git a/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v b/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
index e664641c..14a9f2f8 100644
--- a/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /*
  *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
  *
diff --git a/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
index b22309e3..c320587b 100644
--- a/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 
 `timescale 1 ns / 1 ps
 
diff --git a/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v b/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
index 02fef690..42ff14b2 100644
--- a/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /*
  *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
  *
diff --git a/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v b/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
index 7de54631..532e5680 100644
--- a/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /*
  *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
  *
diff --git a/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
index 7d4237ab..66754481 100644
--- a/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /*
  *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
  *
diff --git a/verilog/dv/caravel/spiflash.v b/verilog/dv/caravel/spiflash.v
index 0b236e0e..d4a82d9d 100644
--- a/verilog/dv/caravel/spiflash.v
+++ b/verilog/dv/caravel/spiflash.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /*
  *  PicoSoC - A simple example SoC using PicoRV32
  *
diff --git a/verilog/dv/caravel/tbuart.v b/verilog/dv/caravel/tbuart.v
index 97c4283a..f623a60f 100644
--- a/verilog/dv/caravel/tbuart.v
+++ b/verilog/dv/caravel/tbuart.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /*
  *  PicoSoC - A simple example SoC using PicoRV32
  *
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
index 0205af32..cefe5831 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
+++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 
 `timescale 1 ns / 1 ps
 
diff --git a/verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v b/verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v
index b378e1af..61c7bf49 100644
--- a/verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v
+++ b/verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 
 `timescale 1 ns / 1 ps
 
diff --git a/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v b/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v
index 96833b84..ec76925e 100644
--- a/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v
+++ b/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 
 `timescale 1 ns / 1 ps
 
diff --git a/verilog/dv/dummy_slave.v b/verilog/dv/dummy_slave.v
index 857ce0e8..52ec1cd4 100644
--- a/verilog/dv/dummy_slave.v
+++ b/verilog/dv/dummy_slave.v
@@ -1,3 +1,4 @@
+`default_nettype none
 module dummy_slave(
     input wb_clk_i,
     input wb_rst_i,
diff --git a/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v b/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v
index ddee1a56..67c0aa26 100644
--- a/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v
+++ b/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 
 
 `timescale 1 ns / 1 ps
diff --git a/verilog/dv/wb_utests/intercon_wb/intercon_wb_tb.v b/verilog/dv/wb_utests/intercon_wb/intercon_wb_tb.v
index 14702f90..21393306 100644
--- a/verilog/dv/wb_utests/intercon_wb/intercon_wb_tb.v
+++ b/verilog/dv/wb_utests/intercon_wb/intercon_wb_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 
 
 `timescale 1 ns / 1 ps
diff --git a/verilog/dv/wb_utests/la_wb/la_wb_tb.v b/verilog/dv/wb_utests/la_wb/la_wb_tb.v
index 2c501868..4c8a23c8 100644
--- a/verilog/dv/wb_utests/la_wb/la_wb_tb.v
+++ b/verilog/dv/wb_utests/la_wb/la_wb_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 `timescale 1 ns / 1 ps
 
 `include "la_wb.v"
diff --git a/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v b/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v
index 2c2afd72..d268736f 100644
--- a/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v
+++ b/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 
 
 `timescale 1 ns / 1 ps
diff --git a/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v b/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v
index a4c01d0e..1fde261d 100644
--- a/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v
+++ b/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 
 
 `timescale 1 ns / 1 ps
diff --git a/verilog/dv/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v b/verilog/dv/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v
index 0275a2c1..5d34c67f 100644
--- a/verilog/dv/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v
+++ b/verilog/dv/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 
 
 `timescale 1 ns / 1 ps
diff --git a/verilog/dv/wb_utests/spimemio_wb/spimemio_wb_tb.v b/verilog/dv/wb_utests/spimemio_wb/spimemio_wb_tb.v
index b75e6fc3..0fb5b093 100644
--- a/verilog/dv/wb_utests/spimemio_wb/spimemio_wb_tb.v
+++ b/verilog/dv/wb_utests/spimemio_wb/spimemio_wb_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 
 
 `timescale 1 ns / 1 ps
diff --git a/verilog/dv/wb_utests/storage_wb/storage_wb_tb.v b/verilog/dv/wb_utests/storage_wb/storage_wb_tb.v
index 460f6d7c..e19690e7 100644
--- a/verilog/dv/wb_utests/storage_wb/storage_wb_tb.v
+++ b/verilog/dv/wb_utests/storage_wb/storage_wb_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 // `define DBG
 
 `define STORAGE_BASE_ADR  32'h0100_0000
diff --git a/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v b/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
index 00860164..d4f0326f 100644
--- a/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
+++ b/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 
 `timescale 1 ns / 1 ps
 
diff --git a/verilog/dv/wb_utests/uart_wb/uart_wb_tb.v b/verilog/dv/wb_utests/uart_wb/uart_wb_tb.v
index 6063060e..56b93f63 100644
--- a/verilog/dv/wb_utests/uart_wb/uart_wb_tb.v
+++ b/verilog/dv/wb_utests/uart_wb/uart_wb_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 
 
 `timescale 1 ns / 1 ps
@@ -18,6 +19,9 @@ module uart_wb_tb;
 
 	wire wb_ack_o;
 	wire [31:0] wb_dat_o;
+
+    wire tbuart_rx;
+	wire ser_rx;
   
     initial begin
         wb_clk_i = 0; 
@@ -146,4 +150,4 @@ module uart_wb_tb;
 		.ser_rx(ser_rx)
 	);
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/verilog/gl/DFFRAM.v b/verilog/gl/DFFRAM.v
index c46f8d87..f0a55fee 100644
--- a/verilog/gl/DFFRAM.v
+++ b/verilog/gl/DFFRAM.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
 
 module DFFRAM(CLK, EN, VPWR, VGND, A, Di, Do, WE);
diff --git a/verilog/gl/digital_pll.v b/verilog/gl/digital_pll.v
index 0b1f5ed9..4310af0c 100644
--- a/verilog/gl/digital_pll.v
+++ b/verilog/gl/digital_pll.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
 
 module digital_pll(dco, enable, osc, resetb, VPWR, VGND, clockp, div, ext_trim);
diff --git a/verilog/gl/gpio_control_block.v b/verilog/gl/gpio_control_block.v
index 57c53f6f..9796422d 100644
--- a/verilog/gl/gpio_control_block.v
+++ b/verilog/gl/gpio_control_block.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
 
 module gpio_control_block(mgmt_gpio_in, mgmt_gpio_oeb, mgmt_gpio_out, pad_gpio_ana_en, pad_gpio_ana_pol, pad_gpio_ana_sel, pad_gpio_holdover, pad_gpio_ib_mode_sel, pad_gpio_in, pad_gpio_inenb, pad_gpio_out, pad_gpio_outenb, pad_gpio_slow_sel, pad_gpio_vtrip_sel, resetn, serial_clock, serial_data_in, serial_data_out, user_gpio_in, user_gpio_oeb, user_gpio_out, VPWR, VGND, pad_gpio_dm);
diff --git a/verilog/gl/simple_por.v b/verilog/gl/simple_por.v
index bf90099e..22914449 100644
--- a/verilog/gl/simple_por.v
+++ b/verilog/gl/simple_por.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
 
 module simple_por(porb_h, vdd3v3, vss, VPWR, VGND);
diff --git a/verilog/gl/storage.v b/verilog/gl/storage.v
index e82d48ba..a629e826 100644
--- a/verilog/gl/storage.v
+++ b/verilog/gl/storage.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
 
 module storage(mgmt_clk, mgmt_ena_ro, VPWR, VGND, mgmt_addr, mgmt_addr_ro, mgmt_ena, mgmt_rdata, mgmt_rdata_ro, mgmt_wdata, mgmt_wen, mgmt_wen_mask);
diff --git a/verilog/gl/user_id_programming.v b/verilog/gl/user_id_programming.v
index 715e184c..b941b6b2 100644
--- a/verilog/gl/user_id_programming.v
+++ b/verilog/gl/user_id_programming.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
 
 module user_id_programming(vdd1v8, vss, VPWR, VGND, mask_rev);
diff --git a/verilog/gl/user_proj_example.v b/verilog/gl/user_proj_example.v
index a80278bf..74638c0c 100644
--- a/verilog/gl/user_proj_example.v
+++ b/verilog/gl/user_proj_example.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
 
 module user_proj_example(vccd1, vccd2, vdda1, vdda2, vssa1, vssa2, vssd1, vssd2, wb_clk_i, wb_rst_i, wbs_ack_o, wbs_cyc_i, wbs_stb_i, wbs_we_i, VPWR, VGND, io_in, io_oeb, io_out, la_data_in, la_data_out, la_oen, wbs_adr_i, wbs_dat_i, wbs_dat_o, wbs_sel_i);
diff --git a/verilog/rtl/DFFRAM.v b/verilog/rtl/DFFRAM.v
index d6d2d339..c6af2a6e 100644
--- a/verilog/rtl/DFFRAM.v
+++ b/verilog/rtl/DFFRAM.v
@@ -1,3 +1,4 @@
+`default_nettype none
 `ifndef USE_CUSTOM_DFFRAM
 
 module DFFRAM(
diff --git a/verilog/rtl/DFFRAMBB.v b/verilog/rtl/DFFRAMBB.v
index 1b88ef74..712a2531 100644
--- a/verilog/rtl/DFFRAMBB.v
+++ b/verilog/rtl/DFFRAMBB.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /*
     Building blocks for DFF based RAM compiler for SKY130A 
     BYTE        :   8 memory cells used as a building block for WORD module
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 24a2f3fc..784fdae5 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /*--------------------------------------------------------------*/
 /* caravel, a project harness for the Google/SkyWater sky130	*/
 /* fabrication process and open source PDK			*/
diff --git a/verilog/rtl/caravel_clocking.v b/verilog/rtl/caravel_clocking.v
index 1b1555fc..aa49d6f4 100644
--- a/verilog/rtl/caravel_clocking.v
+++ b/verilog/rtl/caravel_clocking.v
@@ -1,3 +1,4 @@
+`default_nettype none
 // This routine synchronizes the 
 
 module caravel_clocking(
diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v
index 36b08df2..2a2bea78 100644
--- a/verilog/rtl/chip_io.v
+++ b/verilog/rtl/chip_io.v
@@ -1,3 +1,4 @@
+`default_nettype none
 module chip_io(
 	// Package Pins
 	inout  vddio,		// Common padframe/ESD supply
diff --git a/verilog/rtl/clock_div.v b/verilog/rtl/clock_div.v
index 01d03a82..54bf194b 100644
--- a/verilog/rtl/clock_div.v
+++ b/verilog/rtl/clock_div.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /* Integer-N clock divider */
  
 module clock_div #(
diff --git a/verilog/rtl/convert_gpio_sigs.v b/verilog/rtl/convert_gpio_sigs.v
index cac5141f..c7d53f38 100644
--- a/verilog/rtl/convert_gpio_sigs.v
+++ b/verilog/rtl/convert_gpio_sigs.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /* Convert the standard set of GPIO signals: input, output, output_enb,
  * pullup, and pulldown into the set needed by the s8 GPIO pads:
  * input, output, output_enb, input_enb, mode.  Note that dm[2] on
diff --git a/verilog/rtl/counter_timer_high.v b/verilog/rtl/counter_timer_high.v
index 76db8b99..b66ee6b5 100755
--- a/verilog/rtl/counter_timer_high.v
+++ b/verilog/rtl/counter_timer_high.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /* Simple 32-bit counter-timer for Caravel. */
 
 /* Counter acts as high 32 bits of a 64-bit counter
diff --git a/verilog/rtl/counter_timer_low.v b/verilog/rtl/counter_timer_low.v
index b9e1191b..f0505a76 100755
--- a/verilog/rtl/counter_timer_low.v
+++ b/verilog/rtl/counter_timer_low.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /* Simple 32-bit counter-timer for Caravel. */
 
 /* Counter acts as low 32 bits of a 64-bit counter
diff --git a/verilog/rtl/defines.v b/verilog/rtl/defines.v
index 7233b8a2..1aec1557 100644
--- a/verilog/rtl/defines.v
+++ b/verilog/rtl/defines.v
@@ -1,3 +1,4 @@
+`default_nettype none
 // Global parameters
 
 `define MPRJ_IO_PADS 38
diff --git a/verilog/rtl/digital_pll.v b/verilog/rtl/digital_pll.v
index 06ceaf98..dac708ad 100644
--- a/verilog/rtl/digital_pll.v
+++ b/verilog/rtl/digital_pll.v
@@ -1,3 +1,4 @@
+`default_nettype none
 // Digital PLL (ring oscillator + controller)
 // Technically this is a frequency locked loop, not a phase locked loop.
 
diff --git a/verilog/rtl/digital_pll_controller.v b/verilog/rtl/digital_pll_controller.v
index d4f7a4c8..1437c932 100644
--- a/verilog/rtl/digital_pll_controller.v
+++ b/verilog/rtl/digital_pll_controller.v
@@ -1,3 +1,4 @@
+`default_nettype none
 // (True) digital PLL
 //
 // Output goes to a trimmable ring oscillator (see documentation).
diff --git a/verilog/rtl/gpio_control_block.v b/verilog/rtl/gpio_control_block.v
index bca5aa33..ed3d531a 100644
--- a/verilog/rtl/gpio_control_block.v
+++ b/verilog/rtl/gpio_control_block.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /* 
  *---------------------------------------------------------------------
  * See gpio_control_block for description.  This module is like
diff --git a/verilog/rtl/gpio_wb.v b/verilog/rtl/gpio_wb.v
index e4e92e97..77d1f3a6 100644
--- a/verilog/rtl/gpio_wb.v
+++ b/verilog/rtl/gpio_wb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 module gpio_wb # (
     parameter BASE_ADR  = 32'h 2100_0000,
     parameter GPIO_DATA = 8'h 00,
diff --git a/verilog/rtl/housekeeping_spi.v b/verilog/rtl/housekeeping_spi.v
index cc8d5d00..bd09dcb5 100644
--- a/verilog/rtl/housekeeping_spi.v
+++ b/verilog/rtl/housekeeping_spi.v
@@ -1,3 +1,4 @@
+`default_nettype none
 //-------------------------------------
 // SPI controller for Caravel (PicoSoC)
 //-------------------------------------
diff --git a/verilog/rtl/la_wb.v b/verilog/rtl/la_wb.v
index 68e0cc00..9b963aff 100644
--- a/verilog/rtl/la_wb.v
+++ b/verilog/rtl/la_wb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 module la_wb # (
     parameter BASE_ADR  = 32'h 2200_0000,
     parameter LA_DATA_0 = 8'h00,
diff --git a/verilog/rtl/mem_wb.v b/verilog/rtl/mem_wb.v
index 8688f9a0..55f9eefc 100644
--- a/verilog/rtl/mem_wb.v
+++ b/verilog/rtl/mem_wb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 module mem_wb (
 `ifdef USE_POWER_PINS
     input VPWR,
diff --git a/verilog/rtl/mgmt_core.v b/verilog/rtl/mgmt_core.v
index 50043c41..21e36dc7 100644
--- a/verilog/rtl/mgmt_core.v
+++ b/verilog/rtl/mgmt_core.v
@@ -1,3 +1,4 @@
+`default_nettype none
 module mgmt_core (
 `ifdef USE_POWER_PINS
 	inout vdd1v8,	   
diff --git a/verilog/rtl/mgmt_protect.v b/verilog/rtl/mgmt_protect.v
index 4dcf1117..f8fe7fb3 100644
--- a/verilog/rtl/mgmt_protect.v
+++ b/verilog/rtl/mgmt_protect.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /*----------------------------------------------------------------------*/
 /* Buffers protecting the management region from the user region.	*/
 /* This mainly consists of tristate buffers that are enabled by a	*/
diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v
index df81c2ce..8d3e1f77 100644
--- a/verilog/rtl/mgmt_soc.v
+++ b/verilog/rtl/mgmt_soc.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /*
  *  PicoSoC - A simple example SoC using PicoRV32
  *
diff --git a/verilog/rtl/mprj_ctrl.v b/verilog/rtl/mprj_ctrl.v
index e70ac93f..6b17fe20 100644
--- a/verilog/rtl/mprj_ctrl.v
+++ b/verilog/rtl/mprj_ctrl.v
@@ -1,3 +1,4 @@
+`default_nettype none
 module mprj_ctrl_wb #(
     parameter BASE_ADR  = 32'h 2300_0000,
     parameter XFER      = 8'h 00,
diff --git a/verilog/rtl/mprj_io.v b/verilog/rtl/mprj_io.v
index 5bc4483f..11a7dc33 100644
--- a/verilog/rtl/mprj_io.v
+++ b/verilog/rtl/mprj_io.v
@@ -1,3 +1,4 @@
+`default_nettype none
 module mprj_io #(
     parameter AREA1PADS = 18	// Highest numbered pad in area 1
 ) (
diff --git a/verilog/rtl/pads.v b/verilog/rtl/pads.v
index 9ce690a4..a423124f 100644
--- a/verilog/rtl/pads.v
+++ b/verilog/rtl/pads.v
@@ -1,3 +1,4 @@
+`default_nettype none
 `ifndef TOP_ROUTING 
 	`define USER1_ABUTMENT_PINS \
 	.AMUXBUS_A(analog_a),\
diff --git a/verilog/rtl/picorv32.v b/verilog/rtl/picorv32.v
index cbbbb609..60dea84a 100644
--- a/verilog/rtl/picorv32.v
+++ b/verilog/rtl/picorv32.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /*
  *  PicoRV32 -- A Small RISC-V (RV32I) Processor Core
  *
diff --git a/verilog/rtl/ring_osc2x13.v b/verilog/rtl/ring_osc2x13.v
index 9bf6252b..719da6e0 100644
--- a/verilog/rtl/ring_osc2x13.v
+++ b/verilog/rtl/ring_osc2x13.v
@@ -1,3 +1,4 @@
+`default_nettype none
 // Tunable ring oscillator---synthesizable (physical) version.
 //
 // NOTE:  This netlist cannot be simulated correctly due to lack
diff --git a/verilog/rtl/simple_por.v b/verilog/rtl/simple_por.v
index f308fbf6..2c51e9a0 100644
--- a/verilog/rtl/simple_por.v
+++ b/verilog/rtl/simple_por.v
@@ -1,3 +1,4 @@
+`default_nettype none
 `timescale 1 ns / 1 ps
 
 module simple_por(
diff --git a/verilog/rtl/simple_spi_master.v b/verilog/rtl/simple_spi_master.v
index 447f0f11..8a81954b 100755
--- a/verilog/rtl/simple_spi_master.v
+++ b/verilog/rtl/simple_spi_master.v
@@ -1,3 +1,4 @@
+`default_nettype none
 //----------------------------------------------------------------------------
 // Module: simple_spi_master
 //
diff --git a/verilog/rtl/simpleuart.v b/verilog/rtl/simpleuart.v
index 54a3cb4e..66e19159 100644
--- a/verilog/rtl/simpleuart.v
+++ b/verilog/rtl/simpleuart.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /*
  *  PicoSoC - A simple example SoC using PicoRV32
  *
@@ -44,6 +45,7 @@ module simpleuart_wb # (
     wire [31:0] simpleuart_reg_div_do;
     wire [31:0] simpleuart_reg_dat_do;
     wire [31:0] simpleuart_reg_cfg_do;
+    wire reg_dat_wait;
 
     wire resetn = ~wb_rst_i;
     wire valid = wb_stb_i && wb_cyc_i; 
@@ -125,6 +127,8 @@ module simpleuart (
     reg [31:0] send_divcnt;
     reg send_dummy;
 
+    wire reg_ena_do;
+
     assign reg_div_do = cfg_divider;
     assign reg_ena_do = {31'd0, enabled};
 
diff --git a/verilog/rtl/spimemio.v b/verilog/rtl/spimemio.v
index 074fff7b..a982981f 100644
--- a/verilog/rtl/spimemio.v
+++ b/verilog/rtl/spimemio.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /*
  *  PicoSoC - A simple example SoC using PicoRV32
  *
diff --git a/verilog/rtl/sram_1rw1r_32_256_8_sky130.v b/verilog/rtl/sram_1rw1r_32_256_8_sky130.v
index 67f6baac..cf0489d1 100644
--- a/verilog/rtl/sram_1rw1r_32_256_8_sky130.v
+++ b/verilog/rtl/sram_1rw1r_32_256_8_sky130.v
@@ -1,3 +1,4 @@
+`default_nettype none
 // OpenRAM SRAM model
 // Words: 256
 // Word size: 32
diff --git a/verilog/rtl/storage.v b/verilog/rtl/storage.v
index e16ab5e2..fe0eae7b 100644
--- a/verilog/rtl/storage.v
+++ b/verilog/rtl/storage.v
@@ -1,3 +1,4 @@
+`default_nettype none
  
 module storage (
     // MGMT_AREA R/W Interface 
diff --git a/verilog/rtl/storage_bridge_wb.v b/verilog/rtl/storage_bridge_wb.v
index aabcc36e..ddce210d 100644
--- a/verilog/rtl/storage_bridge_wb.v
+++ b/verilog/rtl/storage_bridge_wb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 module storage_bridge_wb (
     // MGMT_AREA R/W WB Interface
     input wb_clk_i,
diff --git a/verilog/rtl/sysctrl.v b/verilog/rtl/sysctrl.v
index 6c2d3765..8a0ac428 100644
--- a/verilog/rtl/sysctrl.v
+++ b/verilog/rtl/sysctrl.v
@@ -1,3 +1,4 @@
+`default_nettype none
 module sysctrl_wb #(
     parameter BASE_ADR     = 32'h2F00_0000,
     parameter PWRGOOD	   = 8'h00,
diff --git a/verilog/rtl/user_id_programming.v b/verilog/rtl/user_id_programming.v
index 5133605f..d3186c17 100644
--- a/verilog/rtl/user_id_programming.v
+++ b/verilog/rtl/user_id_programming.v
@@ -1,3 +1,4 @@
+`default_nettype none
 // This module represents an unprogrammed mask revision
 // block that is configured with via programming on the
 // chip top level.  This value is passed to the block as
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index f1feed5a..6c1c1174 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /*
  *-------------------------------------------------------------
  *
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 488e4cc5..549353ea 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /*
  *-------------------------------------------------------------
  *
diff --git a/verilog/rtl/wb_intercon.v b/verilog/rtl/wb_intercon.v
index 1397cd45..7d9ddb14 100644
--- a/verilog/rtl/wb_intercon.v
+++ b/verilog/rtl/wb_intercon.v
@@ -1,3 +1,4 @@
+`default_nettype none
 module wb_intercon #(
     parameter DW = 32,          // Data Width
     parameter AW = 32,          // Address Width
diff --git a/verilog/stubs/sky130_fd_io__top_xres4v2.v b/verilog/stubs/sky130_fd_io__top_xres4v2.v
index 49f75637..43109f96 100644
--- a/verilog/stubs/sky130_fd_io__top_xres4v2.v
+++ b/verilog/stubs/sky130_fd_io__top_xres4v2.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /*
  * Copyright 2020 The SkyWater PDK Authors
  *