Generated cpu data memory size

[cheeef]

It seems that the generated data memory size stays constant no matter how complex the component is. Is there any way to find out how much is actually needed?

For certain blocks this might be difficult to estimate but it should quite constant for others. In order to generate components which fit into smaller FPGA's like lattice ICE40 this needs to addressed.

[dawsonjon]

Hi,

Have added some features that should help. It is possible to change the size of the data memory, but this has previously only been accessible via the python api and it wasn't documented.
I have added a command line option to c2verilog to change the memory size:

c2verilog memory_size=2048 myfile.c

The default is 4096x32 and the maximum is 65536x32.

Also the verilog now generates a simulation warning if stack overflow occurs. There is also an output "exception" which goes high when there is a stack overflow. You could monitor this in hardware to check to check that you haven't run out of memory.

Working out how much memory you need is tricky (e.g. recursive functions). There are a couple of options.

In a simple program, you could estimate the stack space by adding together the size of all the variables in all of the function calls, and then add some margin.

In a more complex program, it might be more practical to thoroughly exercise the component either in simulation or in hardware and ensure that stack overflow does not occur.

Another issue that you might have in small FPGAs such as ICE40 is the lack of hardware multipliers (the design of the verilog code assumes that these are available). If there is interest, I could add an option to calculate multiplies using shifts and adds.

Hope this helps
Jon

[cheeef]

Thanks. Do have an idea how much RAM the Webserver-Demo might need? I'm not sure it's even worth trying to port it to ICE40 or create a simulation when the resource requirements are too high from the beginning with.