From 187a87ca177ed2add3ebd4feafae1dc9481c90cf Mon Sep 17 00:00:00 2001
From: Peter Lebbing <peter@digitalbrains.com>
Date: Sat, 7 Sep 2024 09:37:03 +0200
Subject: [PATCH] Revert "Skip failing test-suite CI on 1.8"

This reverts commit a847d3752ebfcfc6025c240b41e77724c2eb51ca.
---
 test-suite/Main.hs | 24 +-----------------------
 1 file changed, 1 insertion(+), 23 deletions(-)

diff --git a/test-suite/Main.hs b/test-suite/Main.hs
index 0fa3563..1e360dd 100644
--- a/test-suite/Main.hs
+++ b/test-suite/Main.hs
@@ -185,17 +185,12 @@ runClashTest = defaultMain $ clashTestRoot
                                                       ]
                           }
           in runTest "Floating" _opts
-
--- "Unmatchable constant as case subject"
-#if MIN_VERSION_clash_lib(1,9,0)
         , runTest "XpmCdcArraySingle" $ def
             { hdlTargets=[VHDL, Verilog]
             , hdlLoad=[Vivado]
             , hdlSim=[Vivado]
             , buildTargets=BuildSpecific ["tb" <> show n | n <- [(0::Int)..7]]
             }
-#endif
-
         , runTest "XpmCdcGray" $ def
             { hdlTargets=[VHDL, Verilog]
             , hdlLoad=[Vivado]
@@ -203,23 +198,11 @@ runClashTest = defaultMain $ clashTestRoot
             , buildTargets=BuildSpecific ["tb" <> show n | n <- [(0::Int)..7]]
             }
         , runTest "XpmCdcHandshake" $ def
-            { hdlTargets=
-                [
-
--- (Vivado) ERROR: [VRFC 10-2989] 'tuple3_0_sel0_std_logic_vector' is not declared [/tmp/clash-test_XpmCdcHandshake-71223bd02c6e132d/vivado-tb0/XpmCdcHandshake.tb0/top_4.vhdl:122]
-#if MIN_VERSION_clash_lib(1,9,0)
-                  VHDL,
-#endif
-
-                  Verilog
-                ]
+            { hdlTargets=[VHDL, Verilog]
             , hdlLoad=[Vivado]
             , hdlSim=[Vivado]
             , buildTargets=BuildSpecific ["tb" <> show n | n <- [(0::Int)..6]]
             }
-
--- "Unmatchable constant as case subject"
-#if MIN_VERSION_clash_lib(1,9,0)
         , runTest "XpmCdcPulse" $ def
             { hdlTargets=[VHDL, Verilog]
             , hdlLoad=[Vivado]
@@ -238,8 +221,6 @@ runClashTest = defaultMain $ clashTestRoot
             , hdlSim=[Vivado]
             , buildTargets=BuildSpecific ["tb" <> show n | n <- [(0::Int)..7]]
             }
-#endif
-
         , runTest "DnaPortE2" def
             { hdlTargets=[VHDL, Verilog]
             , hdlLoad=[Vivado]
@@ -305,8 +286,6 @@ runClashTest = defaultMain $ clashTestRoot
                                                 ]
                     }
           in runTest "Ila" _opts
--- Pattern match failure in 'do' block at /home/peter/src/clash/clash-cores/test-suite/shouldwork/Xilinx/Ila.hs:103:3-8
-#if MIN_VERSION_clash_lib(1,9,0)
         , let _opts =
                 def{ hdlTargets=[VHDL, Verilog, SystemVerilog]
                     , buildTargets=BuildSpecific [ "testWithDefaultsOne"
@@ -317,7 +296,6 @@ runClashTest = defaultMain $ clashTestRoot
                                                 ]
                     }
           in outputTest "Ila" _opts
-#endif
         , outputTest "VIO" def{
             hdlTargets=[VHDL]
           , buildTargets=BuildSpecific ["withSetName", "withSetNameNoResult"]