diff --git a/.clang-format b/.clang-format index 15012747148..2b438bf57cc 100644 --- a/.clang-format +++ b/.clang-format @@ -32,11 +32,14 @@ ColumnLimit: 100 ConstructorInitializerIndentWidth: 8 ContinuationIndentWidth: 8 ForEachMacros: + - 'ARRAY_FOR_EACH' + - 'ARRAY_FOR_EACH_PTR' - 'FOR_EACH' - 'FOR_EACH_FIXED_ARG' - 'FOR_EACH_IDX' - 'FOR_EACH_IDX_FIXED_ARG' - 'FOR_EACH_NONEMPTY_TERM' + - 'FOR_EACH_FIXED_ARG_NONEMPTY_TERM' - 'RB_FOR_EACH' - 'RB_FOR_EACH_CONTAINER' - 'SYS_DLIST_FOR_EACH_CONTAINER' @@ -66,8 +69,16 @@ ForEachMacros: - 'Z_GENLIST_FOR_EACH_NODE' - 'Z_GENLIST_FOR_EACH_NODE_SAFE' - 'STRUCT_SECTION_FOREACH' + - 'STRUCT_SECTION_FOREACH_ALTERNATE' - 'TYPE_SECTION_FOREACH' - 'K_SPINLOCK' + - 'COAP_RESOURCE_FOREACH' + - 'COAP_SERVICE_FOREACH' + - 'COAP_SERVICE_FOREACH_RESOURCE' + - 'HTTP_RESOURCE_FOREACH' + - 'HTTP_SERVER_CONTENT_TYPE_FOREACH' + - 'HTTP_SERVICE_FOREACH' + - 'HTTP_SERVICE_FOREACH_RESOURCE' IfMacros: - 'CHECKIF' # Disabled for now, see bug https://github.com/zephyrproject-rtos/zephyr/issues/48520 @@ -82,8 +93,10 @@ IncludeCategories: - Regex: '.*' Priority: 3 IndentCaseLabels: false +IndentGotoLabels: false IndentWidth: 8 InsertBraces: true +SpaceBeforeInheritanceColon: False SpaceBeforeParens: ControlStatementsExceptControlMacros SortIncludes: Never UseTab: ForContinuationAndIndentation diff --git a/.codechecker.yml b/.codechecker.yml new file mode 100644 index 00000000000..d00e66ca4f7 --- /dev/null +++ b/.codechecker.yml @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024, Basalte bv + +analyzer: + # Start by disabling all + - --disable-all + + # Enable the sensitive profile + - --enable=sensitive + + # Disable unused cases + - --disable=boost + - --disable=mpi + + # Many identifiers in zephyr start with _ + - --disable=clang-diagnostic-reserved-identifier + - --disable=clang-diagnostic-reserved-macro-identifier + + # Cleanup + - --clean diff --git a/.github/ISSUE_TEMPLATE/001_bug_report.md b/.github/ISSUE_TEMPLATE/001_bug_report.md index 57f8652b65b..a3d0677184b 100644 --- a/.github/ISSUE_TEMPLATE/001_bug_report.md +++ b/.github/ISSUE_TEMPLATE/001_bug_report.md @@ -6,8 +6,8 @@ labels: bug assignees: '' --- - -**Notes (delete this)** + **Describe the bug** + **To Reproduce** + **Expected behavior** + **Impact** + **Logs and console output** + **Environment (please complete the following information):** + - OS: (e.g. Linux, MacOS, Windows) - Toolchain (e.g Zephyr SDK, ...) - Commit SHA or Version used **Additional context** + diff --git a/.github/ISSUE_TEMPLATE/002_enhancement.md b/.github/ISSUE_TEMPLATE/002_enhancement.md index 615db8fec2e..36dd018047d 100644 --- a/.github/ISSUE_TEMPLATE/002_enhancement.md +++ b/.github/ISSUE_TEMPLATE/002_enhancement.md @@ -8,13 +8,21 @@ assignees: '' --- **Is your enhancement proposal related to a problem? Please describe.** + **Describe the solution you'd like** + **Describe alternatives you've considered** + **Additional context** + diff --git a/.github/ISSUE_TEMPLATE/003_rfc-proposal.md b/.github/ISSUE_TEMPLATE/003_rfc-proposal.md index fbb1fc8a1e1..9cea2d2dac2 100644 --- a/.github/ISSUE_TEMPLATE/003_rfc-proposal.md +++ b/.github/ISSUE_TEMPLATE/003_rfc-proposal.md @@ -9,43 +9,52 @@ assignees: '' ## Introduction + ### Problem description - + ### Proposed change - + ## Detailed RFC - + ### Proposed change (Detailed) - + ### Dependencies - + ### Concerns and Unresolved Questions - + ## Alternatives - + diff --git a/.github/ISSUE_TEMPLATE/004_feature_request.md b/.github/ISSUE_TEMPLATE/004_feature_request.md index 3ffc06790ef..63aa536c8f5 100644 --- a/.github/ISSUE_TEMPLATE/004_feature_request.md +++ b/.github/ISSUE_TEMPLATE/004_feature_request.md @@ -8,13 +8,21 @@ assignees: '' --- **Is your feature request related to a problem? Please describe.** + **Describe the solution you'd like** + **Describe alternatives you've considered** + **Additional context** + diff --git a/.github/SECURITY.md b/.github/SECURITY.md index 02a5582ae87..42354f627cf 100644 --- a/.github/SECURITY.md +++ b/.github/SECURITY.md @@ -11,9 +11,9 @@ updates: At this time, with the latest release of v3.6, the supported versions are: - - v2.7: Current LTS - - v3.5: Prior release - - v3.6: Current release + - v3.7: Current LTS + - v3.6: Prior release + - v2.7: Prior LTS ## Reporting process diff --git a/.github/workflows/backport_issue_check.yml b/.github/workflows/backport_issue_check.yml index 95175ecf1bb..ecaaf352827 100644 --- a/.github/workflows/backport_issue_check.yml +++ b/.github/workflows/backport_issue_check.yml @@ -2,12 +2,20 @@ name: Backport Issue Check on: pull_request_target: + types: + - edited + - opened + - reopened + - synchronize branches: - v*-branch jobs: backport: name: Backport Issue Check + concurrency: + group: backport-issue-check-${{ github.ref }} + cancel-in-progress: true runs-on: ubuntu-22.04 if: github.repository == 'zephyrproject-rtos/zephyr' diff --git a/.github/workflows/bsim-tests-publish.yaml b/.github/workflows/bsim-tests-publish.yaml index aad33a22339..72608b36b24 100644 --- a/.github/workflows/bsim-tests-publish.yaml +++ b/.github/workflows/bsim-tests-publish.yaml @@ -13,7 +13,7 @@ jobs: steps: - name: Download artifacts - uses: dawidd6/action-download-artifact@v3 + uses: dawidd6/action-download-artifact@v6 with: run_id: ${{ github.event.workflow_run.id }} diff --git a/.github/workflows/bsim-tests.yaml b/.github/workflows/bsim-tests.yaml index 52d384e92fd..0c50ca5d6fd 100644 --- a/.github/workflows/bsim-tests.yaml +++ b/.github/workflows/bsim-tests.yaml @@ -8,6 +8,8 @@ on: - "west.yml" - "subsys/bluetooth/**" - "tests/bsim/**" + - "boards/nordic/nrf5*/*dt*" + - "dts/*/nordic/**" - "tests/bluetooth/common/testlib/**" - "samples/bluetooth/**" - "boards/posix/**" @@ -34,18 +36,13 @@ jobs: runs-on: group: zephyr-runner-v2-linux-x64-4xlarge container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.11.20240324 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.14.20240823 options: '--entrypoint /bin/bash' env: ZEPHYR_TOOLCHAIN_VARIANT: zephyr BSIM_OUT_PATH: /opt/bsim/ BSIM_COMPONENTS_PATH: /opt/bsim/components EDTT_PATH: ../tools/edtt - bsim_bt_52_test_results_file: ./bsim_bt/52_bsim_results.xml - bsim_bt_53_test_results_file: ./bsim_bt/53_bsim_results.xml - bsim_bt_53split_test_results_file: ./bsim_bt/53_bsim_split_results.xml - bsim_net_52_test_results_file: ./bsim_net/52_bsim_results.xml - bsim_uart_test_results_file: ./bsim_uart/uart_bsim_results.xml steps: - name: Apply container owner mismatch workaround run: | @@ -90,7 +87,7 @@ jobs: echo "ZEPHYR_SDK_INSTALL_DIR=/opt/toolchains/zephyr-sdk-$( cat SDK_VERSION )" >> $GITHUB_ENV - name: Check common triggering files - uses: tj-actions/changed-files@v44 + uses: tj-actions/changed-files@v45 id: check-common-files with: files: | @@ -103,9 +100,11 @@ jobs: include/zephyr/arch/posix/ scripts/native_simulator/ tests/bsim/* + boards/nordic/nrf5*/*dt* + dts/*/nordic/ - name: Check if Bluethooth files changed - uses: tj-actions/changed-files@v44 + uses: tj-actions/changed-files@v45 id: check-bluetooth-files with: files: | @@ -114,7 +113,7 @@ jobs: subsys/bluetooth/ - name: Check if Networking files changed - uses: tj-actions/changed-files@v44 + uses: tj-actions/changed-files@v45 id: check-networking-files with: files: | @@ -127,7 +126,7 @@ jobs: include/zephyr/net/ieee802154* - name: Check if UART files changed - uses: tj-actions/changed-files@v44 + uses: tj-actions/changed-files@v45 id: check-uart-files with: files: | @@ -137,10 +136,10 @@ jobs: - name: Update BabbleSim to manifest revision if: > - steps.check-bluetooth-files.outputs.any_changed == 'true' - || steps.check-networking-files.outputs.any_changed == 'true' - || steps.check-uart-files.outputs.any_changed == 'true' - || steps.check-common-files.outputs.any_changed == 'true' + steps.check-bluetooth-files.outputs.any_modified == 'true' + || steps.check-networking-files.outputs.any_modified == 'true' + || steps.check-uart-files.outputs.any_modified == 'true' + || steps.check-common-files.outputs.any_modified == 'true' run: | export BSIM_VERSION=$( west list bsim -f {revision} ) echo "Manifest points to bsim sha $BSIM_VERSION" @@ -151,61 +150,41 @@ jobs: make everything -s -j 8 - name: Run Bluetooth Tests with BSIM - if: steps.check-bluetooth-files.outputs.any_changed == 'true' || steps.check-common-files.outputs.any_changed == 'true' + if: steps.check-bluetooth-files.outputs.any_modified == 'true' || steps.check-common-files.outputs.any_modified == 'true' run: | - export ZEPHYR_BASE=${PWD} - # Build and run the BT tests for nrf52_bsim: - nice tests/bsim/bluetooth/compile.sh - RESULTS_FILE=${ZEPHYR_BASE}/${bsim_bt_52_test_results_file} \ - TESTS_FILE=tests/bsim/bluetooth/tests.nrf52bsim.txt tests/bsim/run_parallel.sh - # Build and run the BT controller tests also for the nrf5340bsim/nrf5340/cpunet - nice tests/bsim/bluetooth/compile.nrf5340bsim_nrf5340_cpunet.sh - BOARD=nrf5340bsim/nrf5340/cpunet \ - RESULTS_FILE=${ZEPHYR_BASE}/${bsim_bt_53_test_results_file} \ - TESTS_FILE=tests/bsim/bluetooth/tests.nrf5340bsim_nrf5340_cpunet.txt \ - tests/bsim/run_parallel.sh - # Build and run the nrf5340 split stack tests set - nice tests/bsim/bluetooth/compile.nrf5340bsim_nrf5340_cpuapp.sh - BOARD=nrf5340bsim/nrf5340/cpuapp \ - RESULTS_FILE=${ZEPHYR_BASE}/${bsim_bt_53split_test_results_file} \ - TESTS_FILE=tests/bsim/bluetooth/tests.nrf5340bsim_nrf5340_cpuapp.txt \ - tests/bsim/run_parallel.sh + tests/bsim/ci.bt.sh - name: Run Networking Tests with BSIM - if: steps.check-networking-files.outputs.any_changed == 'true' || steps.check-common-files.outputs.any_changed == 'true' + if: steps.check-networking-files.outputs.any_modified == 'true' || steps.check-common-files.outputs.any_modified == 'true' run: | - export ZEPHYR_BASE=${PWD} - WORK_DIR=${ZEPHYR_BASE}/bsim_net nice tests/bsim/net/compile.sh - RESULTS_FILE=${ZEPHYR_BASE}/${bsim_net_52_test_results_file} \ - SEARCH_PATH=tests/bsim/net/ tests/bsim/run_parallel.sh + tests/bsim/ci.net.sh - name: Run UART Tests with BSIM - if: steps.check-uart-files.outputs.any_changed == 'true' || steps.check-common-files.outputs.any_changed == 'true' + if: steps.check-uart-files.outputs.any_modified == 'true' || steps.check-common-files.outputs.any_modified == 'true' run: | - echo "UART: Single device tests" - ./scripts/twister -T tests/drivers/uart/ --force-color --inline-logs -v -M -p nrf52_bsim \ - --fixture gpio_loopback -- -uart0_loopback - echo "UART: Multi device tests" - export ZEPHYR_BASE=${PWD} - WORK_DIR=${ZEPHYR_BASE}/bsim_uart nice tests/bsim/drivers/uart/compile.sh - RESULTS_FILE=${ZEPHYR_BASE}/${bsim_uart_test_results_file} \ - SEARCH_PATH=tests/bsim/drivers/uart/ tests/bsim/run_parallel.sh - - - name: Upload Test Results + tests/bsim/ci.uart.sh + + - name: Merge Test Results + run: | + pip3 install junitparser junit2html + junitparser merge --glob "./bsim_*/*bsim_results.*.xml" "./twister-out/twister.xml" junit.xml + junit2html junit.xml junit.html + + - name: Upload Unit Test Results in HTML if: always() uses: actions/upload-artifact@v4 with: - name: bsim-test-results + name: HTML Unit Test Results + if-no-files-found: ignore path: | - ./bsim_bt/52_bsim_results.xml - ./bsim_bt/53_bsim_results.xml - ./bsim_bt/53_bsim_split_results.xml - ./bsim_net/52_bsim_results.xml - ./bsim_uart/uart_bsim_results.xml - ./twister-out/twister.xml - ./twister-out/twister.json - ${{ github.event_path }} - if-no-files-found: warn + junit.html + + - name: Publish Unit Test Results + uses: EnricoMi/publish-unit-test-result-action@v2 + with: + check_name: Bsim Test Results + files: "junit.xml" + comment_mode: off - name: Upload Event Details if: always() diff --git a/.github/workflows/clang.yaml b/.github/workflows/clang.yaml index 77a36a0c931..e88141a9e23 100644 --- a/.github/workflows/clang.yaml +++ b/.github/workflows/clang.yaml @@ -12,7 +12,7 @@ jobs: runs-on: group: zephyr-runner-v2-linux-x64-4xlarge container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.11.20240324 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.14.20240823 options: '--entrypoint /bin/bash' strategy: fail-fast: false diff --git a/.github/workflows/codecov.yaml b/.github/workflows/codecov.yaml index 19c50aba9b4..aa81056cdfd 100644 --- a/.github/workflows/codecov.yaml +++ b/.github/workflows/codecov.yaml @@ -14,7 +14,7 @@ jobs: runs-on: group: zephyr-runner-v2-linux-x64-4xlarge container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.11.20240324 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.14.20240823 options: '--entrypoint /bin/bash' strategy: fail-fast: false diff --git a/.github/workflows/compliance.yml b/.github/workflows/compliance.yml index 09c0767cd19..c8ffedcb77b 100644 --- a/.github/workflows/compliance.yml +++ b/.github/workflows/compliance.yml @@ -1,6 +1,12 @@ name: Compliance Checks -on: pull_request +on: + pull_request: + types: + - edited + - opened + - reopened + - synchronize jobs: check_compliance: @@ -32,7 +38,7 @@ jobs: run: | pip3 install setuptools pip3 install wheel - pip3 install python-magic lxml junitparser gitlint pylint pykwalify yamllint + pip3 install python-magic lxml junitparser gitlint pylint pykwalify yamllint clang-format unidiff sphinx-lint pip3 install west - name: west setup @@ -52,6 +58,14 @@ jobs: west config manifest.group-filter -- +ci,-optional west update -o=--depth=1 -n 2>&1 1> west.update.log || west update -o=--depth=1 -n 2>&1 1> west.update2.log + - name: Check for PR description + if: ${{ github.event.pull_request.body == '' }} + continue-on-error: true + id: pr_description + run: | + echo "Pull request description cannot be empty." + exit 1 + - name: Run Compliance Tests continue-on-error: true id: compliance @@ -80,19 +94,33 @@ jobs: exit 1; fi + warns=("ClangFormat") files=($(./scripts/ci/check_compliance.py -l)) + for file in "${files[@]}"; do f="${file}.txt" if [[ -s $f ]]; then - errors=$(cat $f) - errors="${errors//'%'/'%25'}" - errors="${errors//$'\n'/'%0A'}" - errors="${errors//$'\r'/'%0D'}" - echo "::error file=${f}::$errors" - exit=1 + results=$(cat $f) + results="${results//'%'/'%25'}" + results="${results//$'\n'/'%0A'}" + results="${results//$'\r'/'%0D'}" + + if [[ "${warns[@]}" =~ "${file}" ]]; then + echo "::warning file=${f}::$results" + else + echo "::error file=${f}::$results" + exit=1 + fi fi done if [ "${exit}" == "1" ]; then + echo "Compliance error, check for error messages in the \"Run Compliance Tests\" step" + echo "You can run this step locally with the ./scripts/ci/check_compliance.py script." + exit 1; + fi + + if [ "${{ steps.pr_description.outcome }}" == "failure" ]; then + echo "PR description cannot be empty" exit 1; fi diff --git a/.github/workflows/devicetree_checks.yml b/.github/workflows/devicetree_checks.yml index d0bf180c0f3..060a5d95973 100644 --- a/.github/workflows/devicetree_checks.yml +++ b/.github/workflows/devicetree_checks.yml @@ -28,11 +28,6 @@ jobs: matrix: python-version: ['3.10', '3.11', '3.12'] os: [ubuntu-22.04, macos-14, windows-2022] - exclude: - - os: macos-14 - python-version: 3.6 - - os: windows-2022 - python-version: 3.6 steps: - name: checkout uses: actions/checkout@v4 diff --git a/.github/workflows/doc-build.yml b/.github/workflows/doc-build.yml index e8d53405257..1872a824604 100644 --- a/.github/workflows/doc-build.yml +++ b/.github/workflows/doc-build.yml @@ -17,7 +17,10 @@ env: # The latest CMake available directly with apt is 3.18, but we need >=3.20 # so we fetch that through pip. CMAKE_VERSION: 3.20.5 - DOXYGEN_VERSION: 1.9.6 + DOXYGEN_VERSION: 1.12.0 + # Job count is set to 2 less than the vCPU count of 16 because the total available RAM is 32GiB + # and each sphinx-build process may use more than 2GiB of RAM. + JOB_COUNT: 14 jobs: doc-file-check: @@ -26,7 +29,7 @@ jobs: if: > github.repository_owner == 'zephyrproject-rtos' outputs: - file_check: ${{ steps.check-doc-files.outputs.any_changed }} + file_check: ${{ steps.check-doc-files.outputs.any_modified }} steps: - name: checkout uses: actions/checkout@v4 @@ -34,7 +37,7 @@ jobs: ref: ${{ github.event.pull_request.head.sha }} fetch-depth: 0 - name: Check if Documentation related files changed - uses: tj-actions/changed-files@v44 + uses: tj-actions/changed-files@v45 id: check-doc-files with: files: | @@ -50,6 +53,8 @@ jobs: scripts/dts/ doc/requirements.txt .github/workflows/doc-build.yml + scripts/pylib/pytest-twister-harness/src/twister_harness/device/device_adapter.py + scripts/pylib/pytest-twister-harness/src/twister_harness/helpers/shell.py doc-build-html: name: "Documentation Build (HTML)" @@ -57,20 +62,13 @@ jobs: if: > github.repository_owner == 'zephyrproject-rtos' && ( needs.doc-file-check.outputs.file_check == 'true' || github.event_name != 'pull_request' ) - runs-on: - group: zephyr-runner-v2-linux-x64-4xlarge + runs-on: ubuntu-22.04 timeout-minutes: 90 concurrency: group: doc-build-html-${{ github.ref }} cancel-in-progress: true steps: - - name: Print cloud service information - run: | - echo "ZEPHYR_RUNNER_CLOUD_PROVIDER = ${ZEPHYR_RUNNER_CLOUD_PROVIDER}" - echo "ZEPHYR_RUNNER_CLOUD_NODE = ${ZEPHYR_RUNNER_CLOUD_NODE}" - echo "ZEPHYR_RUNNER_CLOUD_POD = ${ZEPHYR_RUNNER_CLOUD_POD}" - - name: install-pkgs run: | sudo apt-get update @@ -130,7 +128,11 @@ jobs: else DOC_TARGET="html" fi - DOC_TAG=${DOC_TAG} SPHINXOPTS_EXTRA="-q -t publish" make -C doc ${DOC_TARGET} + + DOC_TAG=${DOC_TAG} \ + SPHINXOPTS="-j ${JOB_COUNT} -W --keep-going -T" \ + SPHINXOPTS_EXTRA="-q -t publish" \ + make -C doc ${DOC_TARGET} # API documentation coverage python3 -m coverxygen --xml-dir doc/_build/html/doxygen/xml/ --src-dir include/ --output doc-coverage.info @@ -140,9 +142,9 @@ jobs: - name: compress-docs run: | - tar cfJ html-output.tar.xz --directory=doc/_build html - tar cfJ api-output.tar.xz --directory=doc/_build html/doxygen/html - tar cfJ api-coverage.tar.xz coverage-report + tar --use-compress-program="xz -T0" -cf html-output.tar.xz --directory=doc/_build html + tar --use-compress-program="xz -T0" -cf api-output.tar.xz --directory=doc/_build html/doxygen/html + tar --use-compress-program="xz -T0" -cf api-coverage.tar.xz coverage-report - name: upload-build uses: actions/upload-artifact@v4 @@ -183,8 +185,7 @@ jobs: if: | github.event_name != 'pull_request' && github.repository_owner == 'zephyrproject-rtos' - runs-on: - group: zephyr-runner-v2-linux-x64-4xlarge + runs-on: ubuntu-22.04 container: texlive/texlive:latest timeout-minutes: 120 concurrency: @@ -196,19 +197,13 @@ jobs: run: | git config --global --add safe.directory ${GITHUB_WORKSPACE} - - name: Print cloud service information - run: | - echo "ZEPHYR_RUNNER_CLOUD_PROVIDER = ${ZEPHYR_RUNNER_CLOUD_PROVIDER}" - echo "ZEPHYR_RUNNER_CLOUD_NODE = ${ZEPHYR_RUNNER_CLOUD_NODE}" - echo "ZEPHYR_RUNNER_CLOUD_POD = ${ZEPHYR_RUNNER_CLOUD_POD}" - - name: checkout uses: actions/checkout@v4 - name: install-pkgs run: | apt-get update - apt-get install -y python3-pip python3-venv ninja-build doxygen graphviz librsvg2-bin + apt-get install -y python3-pip python3-venv ninja-build doxygen graphviz librsvg2-bin imagemagick - name: cache-pip uses: actions/cache@v4 @@ -243,7 +238,10 @@ jobs: DOC_TAG="development" fi - DOC_TAG=${DOC_TAG} SPHINXOPTS="-q -j auto" LATEXMKOPTS="-quiet -halt-on-error" make -C doc pdf + DOC_TAG=${DOC_TAG} \ + SPHINXOPTS="-q -j ${JOB_COUNT}" \ + LATEXMKOPTS="-quiet -halt-on-error" \ + make -C doc pdf - name: upload-build if: always() diff --git a/.github/workflows/doc-publish-pr.yml b/.github/workflows/doc-publish-pr.yml index e35c6d65120..b202b0a790a 100644 --- a/.github/workflows/doc-publish-pr.yml +++ b/.github/workflows/doc-publish-pr.yml @@ -21,7 +21,7 @@ jobs: steps: - name: Download artifacts - uses: dawidd6/action-download-artifact@v3 + uses: dawidd6/action-download-artifact@v6 with: workflow: doc-build.yml run_id: ${{ github.event.workflow_run.id }} diff --git a/.github/workflows/doc-publish.yml b/.github/workflows/doc-publish.yml index 869cfceaad2..51c451c75ea 100644 --- a/.github/workflows/doc-publish.yml +++ b/.github/workflows/doc-publish.yml @@ -24,7 +24,7 @@ jobs: steps: - name: Download artifacts - uses: dawidd6/action-download-artifact@v3 + uses: dawidd6/action-download-artifact@v6 with: workflow: doc-build.yml run_id: ${{ github.event.workflow_run.id }} diff --git a/.github/workflows/errno.yml b/.github/workflows/errno.yml index 593fe916deb..b1f7e6f4e62 100644 --- a/.github/workflows/errno.yml +++ b/.github/workflows/errno.yml @@ -10,7 +10,7 @@ jobs: check-errno: runs-on: ubuntu-22.04 container: - image: ghcr.io/zephyrproject-rtos/ci:v0.26.11 + image: ghcr.io/zephyrproject-rtos/ci:v0.26.13 steps: - name: Apply container owner mismatch workaround diff --git a/.github/workflows/footprint-tracking.yml b/.github/workflows/footprint-tracking.yml index ede9f52602e..08b858af477 100644 --- a/.github/workflows/footprint-tracking.yml +++ b/.github/workflows/footprint-tracking.yml @@ -26,7 +26,7 @@ jobs: group: zephyr-runner-v2-linux-x64-4xlarge if: github.repository_owner == 'zephyrproject-rtos' container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.11.20240324 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.14.20240823 options: '--entrypoint /bin/bash' strategy: fail-fast: false diff --git a/.github/workflows/hello_world_multiplatform.yaml b/.github/workflows/hello_world_multiplatform.yaml index bcd11ee3ecc..08fd42d7866 100644 --- a/.github/workflows/hello_world_multiplatform.yaml +++ b/.github/workflows/hello_world_multiplatform.yaml @@ -26,7 +26,7 @@ jobs: strategy: fail-fast: false matrix: - os: [ubuntu-22.04, macos-12, macos-14, windows-2022] + os: [ubuntu-22.04, ubuntu-24.04, macos-13, macos-14, windows-2022] runs-on: ${{ matrix.os }} steps: - name: Checkout diff --git a/.github/workflows/manifest.yml b/.github/workflows/manifest.yml index 040ec957e39..76b80f66504 100644 --- a/.github/workflows/manifest.yml +++ b/.github/workflows/manifest.yml @@ -26,12 +26,13 @@ jobs: west init -l . || true - name: Manifest - uses: zephyrproject-rtos/action-manifest@v1.2.2 + uses: zephyrproject-rtos/action-manifest@v1.3.1 with: github-token: ${{ secrets.ZB_GITHUB_TOKEN }} manifest-path: 'west.yml' checkout-path: 'zephyrproject/zephyr' use-tree-checkout: 'true' + check-impostor-commits: 'true' label-prefix: 'manifest-' verbosity-level: '1' labels: 'manifest' diff --git a/.github/workflows/release.yml b/.github/workflows/release.yml index ccecd17df80..002485b9d80 100644 --- a/.github/workflows/release.yml +++ b/.github/workflows/release.yml @@ -21,7 +21,7 @@ jobs: echo "TRIMMED_VERSION=${GITHUB_REF#refs/tags/v}" >> $GITHUB_OUTPUT - name: REUSE Compliance Check - uses: fsfe/reuse-action@v1 + uses: fsfe/reuse-action@v4 with: args: spdx -o zephyr-${{ steps.get_version.outputs.VERSION }}.spdx diff --git a/.github/workflows/scorecards.yml b/.github/workflows/scorecards.yml new file mode 100644 index 00000000000..e2325da0a4a --- /dev/null +++ b/.github/workflows/scorecards.yml @@ -0,0 +1,61 @@ +# This workflow uses actions that are not certified by GitHub. They are provided +# by a third-party and are governed by separate terms of service, privacy +# policy, and support documentation. + +name: Scorecards supply-chain security +on: + # For Branch-Protection check. Only the default branch is supported. See + # https://github.com/ossf/scorecard/blob/main/docs/checks.md#branch-protection + branch_protection_rule: + # To guarantee Maintained check is occasionally updated. See + # https://github.com/ossf/scorecard/blob/main/docs/checks.md#maintained + schedule: + - cron: '43 7 * * 6' + push: + branches: + - main + +permissions: read-all + +jobs: + analysis: + name: Scorecard analysis + runs-on: ubuntu-latest + permissions: + # Needed for Code scanning upload + security-events: write + # Needed for GitHub OIDC token if publish_results is true + id-token: write + + steps: + - name: "Checkout code" + uses: actions/checkout@692973e3d937129bcbf40652eb9f2f61becf3332 # v4.1.7 + with: + persist-credentials: false + + - name: "Run analysis" + uses: ossf/scorecard-action@62b2cac7ed8198b15735ed49ab1e5cf35480ba46 # v2.4.0 + with: + results_file: results.sarif + results_format: sarif + # Publish results to OpenSSF REST API for easy access by consumers. + # - Allows the repository to include the Scorecard badge. + # - See https://github.com/ossf/scorecard-action#publishing-results. + publish_results: true + + # Upload the results as artifacts (optional). Commenting out will disable + # uploads of run results in SARIF format to the repository Actions tab. + # https://docs.github.com/en/actions/advanced-guides/storing-workflow-data-as-artifacts + - name: "Upload artifact" + uses: actions/upload-artifact@89ef406dd8d7e03cfd12d9e0a4a378f454709029 # v4.3.5 + with: + name: SARIF file + path: results.sarif + retention-days: 5 + + # Upload the results to GitHub's code scanning dashboard (optional). + # Commenting out will disable upload of results to your repo's Code Scanning dashboard + - name: "Upload to code-scanning" + uses: github/codeql-action/upload-sarif@afb54ba388a7dca6ecae48f608c4ff05ff4cc77a # v3.25.15 + with: + sarif_file: results.sarif diff --git a/.github/workflows/stale_issue.yml b/.github/workflows/stale_issue.yml index 8dc31370125..f71e485ff8e 100644 --- a/.github/workflows/stale_issue.yml +++ b/.github/workflows/stale_issue.yml @@ -9,7 +9,7 @@ jobs: runs-on: ubuntu-22.04 if: github.repository == 'zephyrproject-rtos/zephyr' steps: - - uses: actions/stale@v8 + - uses: actions/stale@v9 with: stale-pr-message: 'This pull request has been marked as stale because it has been open (more than) 60 days with no activity. Remove the stale label or add a comment saying that you diff --git a/.github/workflows/twister.yaml b/.github/workflows/twister.yaml index 40f9fe04c2d..cc3c9e3ffdf 100644 --- a/.github/workflows/twister.yaml +++ b/.github/workflows/twister.yaml @@ -25,7 +25,7 @@ jobs: runs-on: group: zephyr-runner-v2-linux-x64-4xlarge container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.11.20240324 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.14.20240823 options: '--entrypoint /bin/bash' outputs: subset: ${{ steps.output-services.outputs.subset }} @@ -129,7 +129,7 @@ jobs: needs: twister-build-prep if: needs.twister-build-prep.outputs.size != 0 container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.11.20240324 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.14.20240823 options: '--entrypoint /bin/bash' strategy: fail-fast: false @@ -310,7 +310,7 @@ jobs: if: success() || failure() steps: - # Needed for opensearch and upload script + # Needed for elasticearch and upload script - if: github.event_name == 'push' || github.event_name == 'schedule' name: Checkout uses: actions/checkout@v4 @@ -324,7 +324,7 @@ jobs: path: artifacts - if: github.event_name == 'push' || github.event_name == 'schedule' - name: Upload to opensearch + name: Upload to elasticsearch run: | pip3 install elasticsearch # set run date on upload to get consistent and unified data across the matrix. diff --git a/.github/workflows/twister_tests_blackbox.yml b/.github/workflows/twister_tests_blackbox.yml index edec21e28d3..8845c7eddd4 100644 --- a/.github/workflows/twister_tests_blackbox.yml +++ b/.github/workflows/twister_tests_blackbox.yml @@ -24,7 +24,7 @@ jobs: python-version: ['3.10', '3.11', '3.12'] os: [ubuntu-22.04] container: - image: ghcr.io/zephyrproject-rtos/ci:v0.26.11 + image: ghcr.io/zephyrproject-rtos/ci:v0.26.13 steps: - name: Apply Container Owner Mismatch Workaround @@ -43,6 +43,8 @@ jobs: echo "$HOME/.local/bin" >> $GITHUB_PATH west init -l . || true + # we do not depend on any hals, tools or bootloader, save some time and space... + west config manifest.group-filter -- -hal,-tools,-bootloader west config --global update.narrow true west update --path-cache /github/cache/zephyrproject 2>&1 1> west.update.log || west update --path-cache /github/cache/zephyrproject 2>&1 1> west.update.log || ( rm -rf ../modules ../bootloader ../tools && west update --path-cache /github/cache/zephyrproject) west forall -c 'git reset --hard HEAD' diff --git a/.github/workflows/west_cmds.yml b/.github/workflows/west_cmds.yml index f3de00d82bb..d910bf15a29 100644 --- a/.github/workflows/west_cmds.yml +++ b/.github/workflows/west_cmds.yml @@ -31,11 +31,6 @@ jobs: matrix: python-version: ['3.10', '3.11', '3.12'] os: [ubuntu-22.04, macos-14, windows-2022] - exclude: - - os: macos-14 - python-version: 3.6 - - os: windows-2022 - python-version: 3.6 steps: - name: checkout uses: actions/checkout@v4 diff --git a/.gitignore b/.gitignore index 15636eaaeac..266b95a424a 100644 --- a/.gitignore +++ b/.gitignore @@ -7,8 +7,10 @@ *.swp *.swo *~ -.\#* + +# Emacs \#*\# + build*/ !doc/build/ !scripts/build @@ -27,6 +29,8 @@ outdir outdir-* scripts/basic/fixdep scripts/gen_idt/gen_idt +coverage-report +doc-coverage.info doc/_build doc/doxygen doc/xml @@ -39,6 +43,7 @@ sanity-out* twister-out* bsim_out bsim_bt_out +myresults.xml tests/RunResults.xml scripts/grub doc/reference/kconfig/*.rst @@ -52,6 +57,7 @@ venv .venv .DS_Store .clangd +new.info # CI output compliance.xml @@ -70,6 +76,7 @@ tags BinaryFiles.txt BoardYml.txt Checkpatch.txt +ClangFormat.txt DevicetreeBindings.txt GitDiffCheck.txt Gitlint.txt @@ -84,4 +91,5 @@ MaintainersFormat.txt ModulesMaintainers.txt Nits.txt Pylint.txt +SphinxLint.txt YAMLLint.txt diff --git a/.mailmap b/.mailmap index bbf2b53318f..050d05cce9f 100644 --- a/.mailmap +++ b/.mailmap @@ -61,6 +61,7 @@ Lixin Guo Łukasz Mazur Manuel Argüelles Manuel Argüelles +Manuel Argüelles Marc Herbert <46978960+marc-hb@users.noreply.github.com> Marin Jurjević Mariusz Ryndzionek diff --git a/CMakeLists.txt b/CMakeLists.txt index f87a7d8553d..952acccbba8 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -109,6 +109,10 @@ add_library(zephyr_interface INTERFACE) # flags that come with zephyr_interface. zephyr_library_named(zephyr) +if(CONFIG_LEGACY_GENERATED_INCLUDE_PATH) + zephyr_include_directories(${PROJECT_BINARY_DIR}/include/generated/zephyr) +endif() + zephyr_include_directories( include ${PROJECT_BINARY_DIR}/include/generated @@ -188,6 +192,7 @@ get_property(OPTIMIZE_FOR_NO_OPTIMIZATIONS_FLAG TARGET compiler PROPERTY no_opti get_property(OPTIMIZE_FOR_DEBUG_FLAG TARGET compiler PROPERTY optimization_debug) get_property(OPTIMIZE_FOR_SPEED_FLAG TARGET compiler PROPERTY optimization_speed) get_property(OPTIMIZE_FOR_SIZE_FLAG TARGET compiler PROPERTY optimization_size) +get_property(OPTIMIZE_FOR_SIZE_AGGRESSIVE_FLAG TARGET compiler PROPERTY optimization_size_aggressive) # From kconfig choice, pick the actual OPTIMIZATION_FLAG to use. # Kconfig choice ensures only one of these CONFIG_*_OPTIMIZATIONS is set. @@ -199,6 +204,8 @@ elseif(CONFIG_SPEED_OPTIMIZATIONS) set(OPTIMIZATION_FLAG ${OPTIMIZE_FOR_SPEED_FLAG}) elseif(CONFIG_SIZE_OPTIMIZATIONS) set(OPTIMIZATION_FLAG ${OPTIMIZE_FOR_SIZE_FLAG}) # Default in kconfig +elseif(CONFIG_SIZE_OPTIMIZATIONS_AGGRESSIVE) + set(OPTIMIZATION_FLAG ${OPTIMIZE_FOR_SIZE_AGGRESSIVE_FLAG}) else() message(FATAL_ERROR "Unreachable code. Expected optimization level to have been chosen. See Kconfig.zephyr") @@ -353,8 +360,21 @@ zephyr_compile_options( $<$:-D_ASMLANGUAGE> ) -# @Intent: Set fundamental linker specific flags -toolchain_ld_base() +find_package(Deprecated COMPONENTS toolchain_ld_base) + +if(DEFINED TOOLCHAIN_LD_FLAGS) + zephyr_ld_options(${TOOLCHAIN_LD_FLAGS}) +endif() + +zephyr_link_libraries(PROPERTY base) + +zephyr_link_libraries_ifndef(CONFIG_LINKER_USE_RELAX PROPERTY no_relax) + +zephyr_link_libraries_ifdef(CONFIG_LINKER_USE_RELAX PROPERTY relax) + +# Sort the common symbols and each input section by alignment +# in descending order to minimize padding between these symbols. +zephyr_link_libraries_ifdef(CONFIG_LINKER_SORT_BY_ALIGNMENT PROPERTY sort_alignment) toolchain_ld_force_undefined_symbols( _OffsetAbsSyms @@ -362,13 +382,37 @@ toolchain_ld_force_undefined_symbols( ) if(NOT CONFIG_NATIVE_BUILD) - # @Intent: Set linker specific flags for bare metal target - toolchain_ld_baremetal() + find_package(Deprecated COMPONENTS toolchain_ld_baremetal) + + zephyr_link_libraries(PROPERTY baremetal) + + # Note that some architectures will skip this flag if set to error, even + # though the compiler flag check passes (e.g. ARC and Xtensa). So warning + # should be the default for now. + # + # Skip this for native application as Zephyr only provides + # additions to the host toolchain linker script. The relocation + # sections (.rel*) requires us to override those provided + # by host toolchain. As we can't account for all possible + # combination of compiler and linker on all machines used + # for development, it is better to turn this off. + # + # CONFIG_LINKER_ORPHAN_SECTION_PLACE is to place the orphan sections + # without any warnings or errors, which is the default behavior. + # So there is no need to explicitly set a linker flag. + if(CONFIG_LINKER_ORPHAN_SECTION_WARN) + zephyr_link_libraries(PROPERTY orphan_warning) + elseif(CONFIG_LINKER_ORPHAN_SECTION_ERROR) + zephyr_link_libraries(PROPERTY orphan_error) + endif() endif() -if(CONFIG_CPP AND NOT CONFIG_MINIMAL_LIBCPP AND NOT CONFIG_NATIVE_LIBRARY) - # @Intent: Set linker specific flags for C++ - toolchain_ld_cpp() +if(CONFIG_CPP) + if(NOT CONFIG_MINIMAL_LIBCPP AND NOT CONFIG_NATIVE_LIBRARY) + find_package(Deprecated COMPONENTS toolchain_ld_cpp) + endif() + + zephyr_link_libraries(PROPERTY cpp_base) endif() # @Intent: Add the basic toolchain warning flags @@ -541,9 +585,9 @@ if(ZEPHYR_GIT_INDEX) endif() add_custom_command( - OUTPUT ${PROJECT_BINARY_DIR}/include/generated/version.h + OUTPUT ${PROJECT_BINARY_DIR}/include/generated/zephyr/version.h COMMAND ${CMAKE_COMMAND} -DZEPHYR_BASE=${ZEPHYR_BASE} - -DOUT_FILE=${PROJECT_BINARY_DIR}/include/generated/version.h + -DOUT_FILE=${PROJECT_BINARY_DIR}/include/generated/zephyr/version.h -DVERSION_TYPE=KERNEL -DVERSION_FILE=${ZEPHYR_BASE}/VERSION -DKERNEL_VERSION_CUSTOMIZATION="$" @@ -552,13 +596,13 @@ add_custom_command( DEPENDS ${ZEPHYR_BASE}/VERSION ${git_dependency} COMMAND_EXPAND_LISTS ) -add_custom_target(version_h DEPENDS ${PROJECT_BINARY_DIR}/include/generated/version.h) +add_custom_target(version_h DEPENDS ${PROJECT_BINARY_DIR}/include/generated/zephyr/version.h) if(EXISTS ${APPLICATION_SOURCE_DIR}/VERSION) add_custom_command( - OUTPUT ${PROJECT_BINARY_DIR}/include/generated/app_version.h + OUTPUT ${PROJECT_BINARY_DIR}/include/generated/zephyr/app_version.h COMMAND ${CMAKE_COMMAND} -DZEPHYR_BASE=${ZEPHYR_BASE} - -DOUT_FILE=${PROJECT_BINARY_DIR}/include/generated/app_version.h + -DOUT_FILE=${PROJECT_BINARY_DIR}/include/generated/zephyr/app_version.h -DVERSION_TYPE=APP -DVERSION_FILE=${APPLICATION_SOURCE_DIR}/VERSION -DAPP_VERSION_CUSTOMIZATION="$" @@ -567,7 +611,9 @@ if(EXISTS ${APPLICATION_SOURCE_DIR}/VERSION) DEPENDS ${APPLICATION_SOURCE_DIR}/VERSION ${git_dependency} COMMAND_EXPAND_LISTS ) - add_custom_target(app_version_h DEPENDS ${PROJECT_BINARY_DIR}/include/generated/app_version.h) + add_custom_target( + app_version_h + DEPENDS ${PROJECT_BINARY_DIR}/include/generated/zephyr/app_version.h) add_dependencies(zephyr_interface app_version_h) endif() @@ -622,8 +668,8 @@ set(ZEPHYR_CURRENT_CMAKE_DIR) get_property(LIBC_LINK_LIBRARIES TARGET zephyr_interface PROPERTY LIBC_LINK_LIBRARIES) zephyr_link_libraries(${LIBC_LINK_LIBRARIES}) -set(syscall_list_h ${CMAKE_CURRENT_BINARY_DIR}/include/generated/syscall_list.h) -set(edk_syscall_list_h ${CMAKE_CURRENT_BINARY_DIR}/edk/include/generated/syscall_list.h) +set(syscall_list_h ${CMAKE_CURRENT_BINARY_DIR}/include/generated/zephyr/syscall_list.h) +set(edk_syscall_list_h ${CMAKE_CURRENT_BINARY_DIR}/edk/include/generated/zephyr/syscall_list.h) set(syscalls_json ${CMAKE_CURRENT_BINARY_DIR}/misc/generated/syscalls.json) set(struct_tags_json ${CMAKE_CURRENT_BINARY_DIR}/misc/generated/struct_tags.json) @@ -761,7 +807,7 @@ add_custom_target(${SYSCALL_LIST_H_TARGET} DEPENDS ${syscall_list_h} ${picolibc_ set_property(TARGET ${SYSCALL_LIST_H_TARGET} APPEND PROPERTY ADDITIONAL_CLEAN_FILES - ${CMAKE_CURRENT_BINARY_DIR}/include/generated/syscalls + ${CMAKE_CURRENT_BINARY_DIR}/include/generated/zephyr/syscalls ) add_custom_target(${PARSE_SYSCALLS_TARGET} @@ -781,19 +827,30 @@ if(CONFIG_TIMEOUT_64BIT) set(SYSCALL_SPLIT_TIMEOUT_ARG --split-type k_timeout_t --split-type k_ticks_t) endif() -add_custom_command(OUTPUT include/generated/syscall_dispatch.c ${syscall_list_h} - # Also, some files are written to include/generated/syscalls/ +# percepio/TraceRecorder/kernelports/Zephyr/scripts/tz_parse_syscalls.py hardcodes the path +# to the `syscall_list.h`, make a copy of the generated file so that percepio is able to build +if(CONFIG_LEGACY_GENERATED_INCLUDE_PATH) + set(LEGACY_SYSCALL_LIST_H_ARGS + ${CMAKE_COMMAND} -E copy + ${syscall_list_h} + ${CMAKE_CURRENT_BINARY_DIR}/include/generated/syscall_list.h) +endif() + +add_custom_command(OUTPUT include/generated/zephyr/syscall_dispatch.c ${syscall_list_h} + # Also, some files are written to include/generated/zephyr/syscalls/ COMMAND ${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/scripts/build/gen_syscalls.py --json-file ${syscalls_json} # Read this file - --base-output include/generated/syscalls # Write to this dir - --syscall-dispatch include/generated/syscall_dispatch.c # Write this file - --syscall-export-llext include/generated/syscall_export_llext.c + --base-output include/generated/zephyr/syscalls # Write to this dir + --syscall-dispatch include/generated/zephyr/syscall_dispatch.c # Write this file + --syscall-export-llext include/generated/zephyr/syscall_export_llext.c --syscall-list ${syscall_list_h} $<$:--gen-mrsh-files> ${SYSCALL_LONG_REGISTERS_ARG} ${SYSCALL_SPLIT_TIMEOUT_ARG} + COMMAND + ${LEGACY_SYSCALL_LIST_H_ARGS} WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} DEPENDS ${PARSE_SYSCALLS_TARGET} ) @@ -801,7 +858,7 @@ add_custom_command(OUTPUT include/generated/syscall_dispatch.c ${syscall_list_h} # This is passed into all calls to the gen_kobject_list.py script. set(gen_kobject_list_include_args --include-subsystem-list ${struct_tags_json}) -set(DRV_VALIDATION ${PROJECT_BINARY_DIR}/include/generated/driver-validation.h) +set(DRV_VALIDATION ${PROJECT_BINARY_DIR}/include/generated/zephyr/driver-validation.h) add_custom_command( OUTPUT ${DRV_VALIDATION} COMMAND @@ -834,7 +891,7 @@ add_dependencies(zephyr_generated_headers set(OFFSETS_LIB offsets) set(OFFSETS_C_PATH ${ARCH_DIR}/${ARCH}/core/offsets/offsets.c) -set(OFFSETS_H_PATH ${PROJECT_BINARY_DIR}/include/generated/offsets.h) +set(OFFSETS_H_PATH ${PROJECT_BINARY_DIR}/include/generated/zephyr/offsets.h) add_library( ${OFFSETS_LIB} OBJECT ${OFFSETS_C_PATH}) target_include_directories(${OFFSETS_LIB} PRIVATE @@ -1197,7 +1254,7 @@ if(CONFIG_USERSPACE) PUBLIC $ ) - set(KOBJECT_LINKER_HEADER_DATA "${PROJECT_BINARY_DIR}/include/generated/linker-kobject-prebuilt-data.h") + set(KOBJECT_LINKER_HEADER_DATA "${PROJECT_BINARY_DIR}/include/generated/zephyr/linker-kobject-prebuilt-data.h") add_custom_command( OUTPUT ${KOBJECT_LINKER_HEADER_DATA} @@ -1205,7 +1262,7 @@ if(CONFIG_USERSPACE) ${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/scripts/build/gen_kobject_placeholders.py --object $ - --outdir ${PROJECT_BINARY_DIR}/include/generated + --outdir ${PROJECT_BINARY_DIR}/include/generated/zephyr --datapct ${CONFIG_KOBJECT_DATA_AREA_RESERVE_EXTRA_PERCENT} --rodata ${CONFIG_KOBJECT_RODATA_AREA_EXTRA_BYTES} $<$:--verbose> @@ -1297,6 +1354,20 @@ if(CONFIG_GEN_ISR_TABLES) set_property(GLOBAL APPEND PROPERTY GENERATED_KERNEL_SOURCE_FILES isr_tables.c) endif() +if(CONFIG_SYMTAB) + add_custom_command( + OUTPUT symtab.c + COMMAND + ${PYTHON_EXECUTABLE} + ${ZEPHYR_BASE}/scripts/build/gen_symtab.py + -k $ + -o symtab.c + DEPENDS ${ZEPHYR_LINK_STAGE_EXECUTABLE} + COMMAND_EXPAND_LISTS + ) + set_property(GLOBAL APPEND PROPERTY GENERATED_KERNEL_SOURCE_FILES symtab.c) +endif() + if(CONFIG_USERSPACE) set(KOBJECT_HASH_LIST kobject_hash.gperf) set(KOBJECT_HASH_OUTPUT_SRC_PRE kobject_hash_preprocessed.c) @@ -1679,9 +1750,8 @@ if(CONFIG_BUILD_OUTPUT_BIN AND CONFIG_BUILD_OUTPUT_UF2) set(BYPRODUCT_KERNEL_UF2_NAME "${PROJECT_BINARY_DIR}/${KERNEL_UF2_NAME}" CACHE FILEPATH "Kernel uf2 file" FORCE) endif() +set(KERNEL_META_PATH ${PROJECT_BINARY_DIR}/${KERNEL_META_NAME} CACHE INTERNAL "") if(CONFIG_BUILD_OUTPUT_META) - set(KERNEL_META_PATH ${PROJECT_BINARY_DIR}/${KERNEL_META_NAME} CACHE INTERNAL "") - list(APPEND post_build_commands COMMAND ${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/scripts/zephyr_module.py @@ -1695,6 +1765,9 @@ if(CONFIG_BUILD_OUTPUT_META) post_build_byproducts ${KERNEL_META_PATH} ) +else(CONFIG_BUILD_OUTPUT_META) + # Prevent spdx to use invalid data + file(REMOVE ${KERNEL_META_PATH}) endif() # Cleanup intermediate files @@ -1855,6 +1928,20 @@ if(CONFIG_BUILD_OUTPUT_INFO_HEADER) ) endif() +if (CONFIG_LLEXT AND CONFIG_LLEXT_EXPORT_BUILTINS_BY_SLID) + #slidgen must be the first post-build command to be executed + #on the Zephyr ELF to ensure that all other commands, such as + #binary file generation, are operating on a preparated ELF. + list(PREPEND + post_build_commands + COMMAND ${PYTHON_EXECUTABLE} + ${ZEPHYR_BASE}/scripts/build/llext_prepare_exptab.py + --elf-file ${PROJECT_BINARY_DIR}/${KERNEL_ELF_NAME} + --slid-listing ${PROJECT_BINARY_DIR}/slid_listing.txt + ) + +endif() + if(NOT CMAKE_C_COMPILER_ID STREQUAL "ARMClang") set(check_init_priorities_input $,${BYPRODUCT_KERNEL_EXE_NAME},${BYPRODUCT_KERNEL_ELF_NAME}> @@ -1941,22 +2028,39 @@ elseif(CONFIG_LOG_MIPI_SYST_USE_CATALOG) endif() if(LOG_DICT_DB_NAME_ARG) - if (NOT CONFIG_LOG_DICTIONARY_DB_TARGET) - set(LOG_DICT_DB_ALL_TARGET ALL) - endif() - add_custom_command( - OUTPUT ${LOG_DICT_DB_NAME} - COMMAND + set(log_dict_gen_command ${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/scripts/logging/dictionary/database_gen.py ${KERNEL_ELF_NAME} ${LOG_DICT_DB_NAME_ARG}=${LOG_DICT_DB_NAME} - --build-header ${PROJECT_BINARY_DIR}/include/generated/version.h - WORKING_DIRECTORY ${PROJECT_BINARY_DIR} - COMMENT "Generating logging dictionary database: ${LOG_DICT_DB_NAME}" - DEPENDS ${logical_target_for_zephyr_elf} + --build-header ${PROJECT_BINARY_DIR}/include/generated/zephyr/version.h ) - add_custom_target(log_dict_db_gen ${LOG_DICT_DB_ALL_TARGET} DEPENDS ${LOG_DICT_DB_NAME}) + + if (NOT CONFIG_LOG_DICTIONARY_DB_TARGET) + # If not using a separate target for generating logging dictionary + # database, add the generation to post build command to make sure + # the database is actually being generated. + list(APPEND + post_build_commands + COMMAND ${CMAKE_COMMAND} -E echo "Generating logging dictionary database: ${LOG_DICT_DB_NAME}" + COMMAND ${log_dict_gen_command} + ) + list(APPEND + post_build_byproducts + ${LOG_DICT_DB_NAME} + ) + else() + # Seprate build target for generating logging dictionary database. + # This needs to be explicitly called/used to generate the database. + add_custom_command( + OUTPUT ${LOG_DICT_DB_NAME} + COMMAND ${log_dict_gen_command} + WORKING_DIRECTORY ${PROJECT_BINARY_DIR} + COMMENT "Generating logging dictionary database: ${LOG_DICT_DB_NAME}" + DEPENDS ${logical_target_for_zephyr_elf} + ) + add_custom_target(log_dict_db_gen DEPENDS ${LOG_DICT_DB_NAME}) + endif() endif() # Add post_build_commands to post-process the final .elf file produced by @@ -2069,12 +2173,15 @@ endif() set(llext_edk_file ${PROJECT_BINARY_DIR}/${CONFIG_LLEXT_EDK_NAME}.tar.xz) # TODO maybe generate flags for C CXX ASM +zephyr_get_compile_definitions_for_lang(C zephyr_defs) zephyr_get_compile_options_for_lang(C zephyr_flags) # Filter out non LLEXT and LLEXT_EDK flags - and add required ones -llext_filter_zephyr_flags(LLEXT_REMOVE_FLAGS ${zephyr_flags} llext_edk_cflags) -llext_filter_zephyr_flags(LLEXT_EDK_REMOVE_FLAGS ${llext_edk_cflags} llext_edk_cflags) +llext_filter_zephyr_flags(LLEXT_REMOVE_FLAGS ${zephyr_flags} llext_filt_flags) +llext_filter_zephyr_flags(LLEXT_EDK_REMOVE_FLAGS ${llext_filt_flags} llext_filt_flags) +set(llext_edk_cflags ${zephyr_defs} -DLL_EXTENSION_BUILD) +list(APPEND llext_edk_cflags ${llext_filt_flags}) list(APPEND llext_edk_cflags ${LLEXT_APPEND_FLAGS}) list(APPEND llext_edk_cflags ${LLEXT_EDK_APPEND_FLAGS}) @@ -2082,13 +2189,13 @@ add_custom_command( OUTPUT ${llext_edk_file} # Regenerate syscalls in case CONFIG_LLEXT_EDK_USERSPACE_ONLY COMMAND ${CMAKE_COMMAND} - -E make_directory edk/include/generated + -E make_directory edk/include/generated/zephyr COMMAND ${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/scripts/build/gen_syscalls.py --json-file ${syscalls_json} # Read this file - --base-output edk/include/generated/syscalls # Write to this dir - --syscall-dispatch edk/include/generated/syscall_dispatch.c # Write this file + --base-output edk/include/generated/zephyr/syscalls # Write to this dir + --syscall-dispatch edk/include/generated/zephyr/syscall_dispatch.c # Write this file --syscall-list ${edk_syscall_list_h} $<$:--userspace-only> ${SYSCALL_LONG_REGISTERS_ARG} @@ -2096,10 +2203,9 @@ add_custom_command( COMMAND ${CMAKE_COMMAND} -DPROJECT_BINARY_DIR=${PROJECT_BINARY_DIR} -DAPPLICATION_SOURCE_DIR=${APPLICATION_SOURCE_DIR} - -DINTERFACE_INCLUDE_DIRECTORIES="$,:>" + -DINTERFACE_INCLUDE_DIRECTORIES="$" -Dllext_edk_file=${llext_edk_file} - -DAUTOCONF_H=${AUTOCONF_H} - -Dllext_cflags="${llext_edk_cflags}" + -Dllext_edk_cflags="${llext_edk_cflags}" -Dllext_edk_name=${CONFIG_LLEXT_EDK_NAME} -DWEST_TOPDIR=${WEST_TOPDIR} -DZEPHYR_BASE=${ZEPHYR_BASE} diff --git a/CODEOWNERS b/CODEOWNERS index 84faf677d91..8ba6e3c5b78 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -27,8 +27,6 @@ /soc/arm/infineon_xmc/ @parthitce /soc/arm/silabs_exx32/efm32pg1b/ @rdmeneze /soc/arm/silabs_exx32/efr32mg21/ @l-alfred -/soc/arm/st_stm32/ @erwango -/soc/arm/st_stm32/*/power.c @FRASTM /soc/arm/st_stm32/stm32mp1/ @arnopo /soc/arm/st_stm32/stm32h7/*stm32h735* @benediktibk /soc/arm/st_stm32/stm32l4/*stm32l451* @benediktibk @@ -44,6 +42,7 @@ /soc/riscv/riscv-privileged/gd32vf103/ @soburi /soc/starfive/jh71xx/ @pfarwsi /soc/riscv/riscv-privileged/niosv/ @sweeaun +/boards/adafruit/feather_nrf52840/ @jacobw /boards/ene/ @ene-steven /boards/arm/96b_argonkey/ @avisconti /boards/arm/96b_avenger96/ @Mani-Sadhasivam @@ -56,8 +55,6 @@ /boards/arm/acn52832/ @sven-hm /boards/arm/arduino_mkrzero/ @soburi /boards/arm/bbc_microbit_v2/ @LingaoM -/boards/arm/bl5340_dvk/ @lairdjm -/boards/arm/bl65*/ @lairdjm /boards/arm/blackpill_f401ce/ @coderkalyan /boards/arm/blackpill_f411ce/ @coderkalyan /boards/arm/bt*10/ @greg-leach @@ -68,7 +65,6 @@ /boards/arm/cy8ckit_062s4/ @DaWei8823 /boards/arm/cy8ckit_062_wifi_bt/ @ifyall @npal-cy /boards/arm/cy8cproto_062_4343w/ @ifyall @npal-cy -/boards/arm/disco_l475_iot1/ @erwango /boards/arm/efm32pg_stk3401a/ @rdmeneze /boards/arm/faze/ @mbittan @simonguinot /boards/arm/frdm*/ @mmahadevan108 @dleach02 @@ -78,7 +74,6 @@ /boards/arm/ip_k66f/ @parthitce @lmajewski /boards/arm/legend/ @mbittan @simonguinot /boards/arm/lpcxpresso*/ @mmahadevan108 @dleach02 -/boards/arm/mg100/ @rerickson1 /boards/arm/mimx8mm_evk/ @Mani-Sadhasivam /boards/arm/mimx8mm_phyboard_polis @pefech /boards/arm/mimxrt*/ @mmahadevan108 @dleach02 @@ -86,10 +81,8 @@ /boards/arm/msp_exp432p401r_launchxl/ @Mani-Sadhasivam /boards/arm/npcx7m6fb_evb/ @MulinChao @ChiHuaL /boards/arm/nrf*/ @carlescufi @lemrey -/boards/arm/nucleo*/ @erwango @ABOSTM @FRASTM /boards/arm/nucleo_f401re/ @idlethread /boards/arm/nuvoton_pfm_m487/ @ssekar15 -/boards/arm/pinnacle_100_dvk/ @rerickson1 /boards/arm/qemu_cortex_a9/ @ibirnbaum /boards/arm/qemu_cortex_r*/ @stephanosio /boards/arm/qemu_cortex_m*/ @ioannisg @stephanosio @@ -107,14 +100,13 @@ /boards/arm/sensortile_box/ @avisconti /boards/arm/steval_fcu001v1/ @Navin-Sankar /boards/arm/stm32l1_disco/ @karlp -/boards/arm/stm32*_disco/ @erwango @ABOSTM @FRASTM /boards/arm/stm32h735g_disco/ @benediktibk /boards/arm/stm32f3_disco/ @ydamigos -/boards/arm/stm32*_eval/ @erwango @ABOSTM @FRASTM /boards/arm/rcar_*/ @aaillet /boards/arm/ubx_bmd345eval_nrf52840/ @Navin-Sankar @brec-u-blox /boards/arm/nrf5340_audio_dk_nrf5340 @koffes @alexsven @erikrobstad @rick1082 @gWacey /boards/arm/stm32_min_dev/ @sidcha +/boards/ezurio/* @rerickson1 /boards/riscv/rv32m1_vega/ @dleach02 /boards/riscv/adp_xc7k_ae350/ @cwshu @kevinwang821020 @jimmyzhe /boards/riscv/longan_nano/ @soburi @@ -152,9 +144,7 @@ /drivers/*/*sam4l* @nandojve /drivers/*/*cc13xx_cc26xx* @bwitherspoon /drivers/*/*gd32* @nandojve -/drivers/*/*litex* @mateusz-holenko @kgugala @pgielda /drivers/*/*mcux* @mmahadevan108 @dleach02 -/drivers/*/*stm32* @erwango @ABOSTM @FRASTM /drivers/*/*native_posix* @aescolar @daor-oti /drivers/*/*lpc11u6x* @mbittan @simonguinot /drivers/*/*npcx* @MulinChao @ChiHuaL @@ -199,6 +189,7 @@ /drivers/dai/intel/ssp/ @kv2019i @marcinszkudlinski @abonislawski /drivers/dai/intel/dmic/ @marcinszkudlinski @abonislawski /drivers/dai/intel/alh/ @abonislawski +/drivers/dma/dma_dw_axi.c @pbalsundar /drivers/dma/*dw* @tbursztyka /drivers/dma/*dw_common* @abonislawski /drivers/dma/*sam0* @Sizurka @@ -212,7 +203,6 @@ /drivers/entropy/*b91* @andy-liu-telink /drivers/entropy/*bt_hci* @JordanYates /drivers/entropy/*rv32m1* @dleach02 -/drivers/entropy/*litex* @mateusz-holenko @kgugala @pgielda /drivers/ethernet/*dwmac* @npitre /drivers/ethernet/*stm32* @Nukersson @lochej /drivers/ethernet/*w5500* @parthitce @@ -221,6 +211,8 @@ /drivers/ethernet/*adin2111* @GeorgeCGV /drivers/ethernet/*oa_tc6* @lmajewski /drivers/ethernet/*lan865x* @lmajewski +/drivers/ethernet/dwc_xgmac @Smale-12048867 +/drivers/ethernet/dwc_xgmac/dwc_xgmac @Smale-12048867 /drivers/ethernet/phy/ @rlubos @tbursztyka @arvinf @jukkar /drivers/ethernet/phy/*adin2111* @GeorgeCGV /drivers/mdio/*adin2111* @GeorgeCGV @@ -234,7 +226,6 @@ /drivers/gpio/*b91* @andy-liu-telink /drivers/gpio/*lmp90xxx* @henrikbrixandersen /drivers/gpio/*nct38xx* @MulinChao @ChiHuaL -/drivers/gpio/*stm32* @erwango /drivers/gpio/*eos_s3* @fkokosinski @kgugala /drivers/gpio/*rcar* @aaillet /drivers/gpio/*esp32* @sylvioalves @@ -258,13 +249,12 @@ /drivers/i2c/i2c_test.c @mbolivar-ampere /drivers/i2c/*rcar* @aaillet /drivers/i2c/*kb1200* @ene-steven -/drivers/i2s/*litex* @mateusz-holenko @kgugala @pgielda /drivers/i2s/i2s_ll_stm32* @avisconti /drivers/i2s/*nrfx* @anangl /drivers/i3c/i3c_cdns.c @XenuIsWatching /drivers/ieee802154/ @rlubos @tbursztyka @jukkar @fgrandel /drivers/ieee802154/*b91* @andy-liu-telink -/drivers/ieee802154/ieee802154_nrf5* @jciupis +/drivers/ieee802154/ieee802154_nrf5* @ankuns /drivers/ieee802154/ieee802154_rf2xx* @tbursztyka @nandojve /drivers/ieee802154/ieee802154_cc13xx* @bwitherspoon @cfriedt @vaishnavachath /drivers/interrupt_controller/ @dcpleung @nashif @@ -334,13 +324,13 @@ /drivers/sensor/qdec_stm32/ @valeriosetti /drivers/sensor/rpi_pico_temp/ @soburi /drivers/sensor/st*/ @avisconti +/drivers/sensor/veaa_x_3/ @jeppenodgaard @MaureenHelm /drivers/sensor/ene_tack_kb1200/ @ene-steven /drivers/serial/*b91* @andy-liu-telink /drivers/serial/uart_altera_jtag.c @nashif @gohshunjing /drivers/serial/uart_altera.c @gohshunjing /drivers/serial/*ns16550* @dcpleung @nashif @gdengi /drivers/serial/*nrfx* @anangl -/drivers/serial/uart_liteuart.c @mateusz-holenko @kgugala @pgielda /drivers/serial/Kconfig.mcux_iuart @Mani-Sadhasivam /drivers/serial/uart_mcux_iuart.c @Mani-Sadhasivam /drivers/serial/Kconfig.rtt @carlescufi @pkral78 @@ -360,7 +350,6 @@ /drivers/serial/uart_ite_it8xxx2.c @GTLin08 /drivers/serial/*intel_lw* @shilinte /drivers/serial/*kb1200* @ene-steven -/drivers/disk/sdmmc_sdhc.h @JunYangNXP /drivers/disk/sdmmc_stm32.c @anthonybrandon /drivers/ptp_clock/ @tbursztyka @jukkar /drivers/spi/*b91* @andy-liu-telink @@ -377,13 +366,11 @@ /drivers/timer/*xlnx_psttc* @wjliang @stephanosio /drivers/timer/*cc13xx_cc26xx_rtc* @vanti /drivers/timer/*cavs* @dcpleung -/drivers/timer/*stm32_lptim* @FRASTM /drivers/timer/*leon_gptimer* @julius-barendt /drivers/timer/*mips_cp0* @frantony /drivers/timer/*rcar_cmt* @aaillet /drivers/timer/*esp32_sys* @uLipe /drivers/timer/*sam0_rtc* @bendiscz -/drivers/timer/*arcv2* @ruuddw /drivers/timer/*xtensa* @dcpleung /drivers/timer/*rv32m1_lptmr* @mbolivar /drivers/timer/*nrf_rtc* @anangl @@ -411,7 +398,6 @@ /drivers/wifi/eswifi/ @loicpoulain @nandojve /drivers/wifi/winc1500/ @kludentwo /drivers/virtualization/ @tbursztyka -/dts/arc/ @abrodkin @ruuddw @iriszzw @evgeniy-paltsev /dts/arm/acsip/ @NorthernDean /dts/arm/aspeed/ @aspeeddylan /dts/arm/atmel/ @galak @nandojve @@ -427,7 +413,6 @@ /dts/arm64/renesas/ @lorc @xakep-amatop /dts/arm/quicklogic/ @fkokosinski @kgugala /dts/arm/seeed_studio/ @str4t0m -/dts/arm/st/ @erwango /dts/arm/st/h7/*stm32h735* @benediktibk /dts/arm/st/l4/*stm32l451* @benediktibk /dts/arm/ti/cc13?2* @bwitherspoon @@ -450,7 +435,6 @@ /dts/riscv/ite/ @ite /dts/riscv/microchip/microchip-miv.dtsi @galak /dts/riscv/openisa/rv32m1* @dleach02 -/dts/riscv/riscv32-litex-vexriscv.dtsi @mateusz-holenko @kgugala @pgielda /dts/riscv/starfive/ @rajnesh-kanwal @pfarwsi /dts/riscv/andes/andes_v5* @cwshu @kevinwang821020 @jimmyzhe /dts/riscv/niosv/ @sweeaun @@ -482,11 +466,8 @@ /dts/bindings/*/nxp*s32* @manuargue /dts/bindings/*/openisa* @dleach02 /dts/bindings/*/raspberrypi*pico* @yonsch -/dts/bindings/*/st* @erwango /dts/bindings/sensor/ams* @alexanderwachter /dts/bindings/*/sifive* @mateusz-holenko @kgugala @pgielda -/dts/bindings/*/litex* @mateusz-holenko @kgugala @pgielda -/dts/bindings/*/vexriscv* @mateusz-holenko @kgugala @pgielda /dts/bindings/*/andes* @cwshu @kevinwang821020 @jimmyzhe /dts/bindings/*/neorv32* @henrikbrixandersen /dts/bindings/*/*lan91c111* @sgrrzhf diff --git a/Kconfig.constants b/Kconfig.constants new file mode 100644 index 00000000000..980b1da193a --- /dev/null +++ b/Kconfig.constants @@ -0,0 +1,19 @@ +# Constant variables to be used across Kconfig options + +# Copyright (c) 2024 basalte bv +# SPDX-License-Identifier: Apache-2.0 + +INT8_MIN := -128 +INT16_MIN := -32768 +INT32_MIN := -2147483648 +INT64_MIN := -9223372036854775808 + +INT8_MAX := 127 +INT16_MAX := 32767 +INT32_MAX := 2147483647 +INT64_MAX := 9223372036854775807 + +UINT8_MAX := 255 +UINT16_MAX := 65535 +UINT32_MAX := 4294967295 +UINT64_MAX := 18446744073709551615 diff --git a/Kconfig.zephyr b/Kconfig.zephyr index 904999f9f66..f97819896d9 100644 --- a/Kconfig.zephyr +++ b/Kconfig.zephyr @@ -5,6 +5,8 @@ # Copyright (c) 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 +source "Kconfig.constants" + osource "${APPLICATION_SOURCE_DIR}/VERSION" # Include Kconfig.defconfig files first so that they can override defaults and @@ -258,6 +260,20 @@ config LINKER_USE_PINNED_SECTION Requires that pinned sections exist in the architecture, SoC, board or custom linker script. +config LINKER_USE_ONDEMAND_SECTION + bool "Use Evictable Linker Section" + depends on DEMAND_MAPPING + depends on !LINKER_USE_PINNED_SECTION + depends on !ARCH_MAPS_ALL_RAM + help + If enabled, the symbols which may be evicted from memory + will be put into a linker section reserved for on-demand symbols. + During boot, the corresponding memory will be mapped as paged out. + This is conceptually the opposite of CONFIG_LINKER_USE_PINNED_SECTION. + + Requires that on-demand sections exist in the architecture, SoC, + board or custom linker script. + config LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT bool "Generic sections are present at boot" if DEMAND_PAGING && LINKER_USE_PINNED_SECTION default y @@ -273,7 +289,7 @@ config LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT config LINKER_LAST_SECTION_ID bool "Last section identifier" - default y + default y if !ARM64 depends on ARM || ARM64 || RISCV help If enabled, the last section will contain an identifier. @@ -478,6 +494,7 @@ choice COMPILER_OPTIMIZATIONS prompt "Optimization level" default NO_OPTIMIZATIONS if COVERAGE default DEBUG_OPTIMIZATIONS if DEBUG + default SIZE_OPTIMIZATIONS_AGGRESSIVE if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "llvm" default SIZE_OPTIMIZATIONS help Note that these flags shall only control the compiler @@ -490,6 +507,12 @@ config SIZE_OPTIMIZATIONS Compiler optimizations will be set to -Os independently of other options. +config SIZE_OPTIMIZATIONS_AGGRESSIVE + bool "Aggressively optimize for size" + help + Compiler optimizations wil be set to -Oz independently of other + options. + config SPEED_OPTIMIZATIONS bool "Optimize for speed" help @@ -940,6 +963,8 @@ config DEPRECATED help Symbol that must be selected by a feature or module if it is considered to be deprecated. + When adding this to an option, remember to follow the instructions in + https://docs.zephyrproject.org/latest/develop/api/api_lifecycle.html#deprecated config WARN_DEPRECATED bool @@ -1065,3 +1090,20 @@ config BOOTLOADER_BOSSA_ADAFRUIT_UF2 endchoice endmenu + +menu "Compatibility" + +config LEGACY_GENERATED_INCLUDE_PATH + bool "Legacy include path for generated headers" + default y + help + Allow applications and libraries to use the Zephyr legacy include + path for the generated headers which does not use the `zephyr/` prefix. + + From now on, i.e., the preferred way to include the `version.h` header is to + use , this Kconfig is currently enabled by default so that + user applications won't immediately fail to compile. + + This Kconfig will be deprecated and eventually removed in the future releases. + +endmenu diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index c24eb2e290c..cc7cb9a1411 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -119,6 +119,8 @@ ACPI: - lib/acpi/ - include/zephyr/acpi/ - tests/lib/acpi/ + - dts/bindings/acpi/ + - include/zephyr/dt-bindings/acpi/ labels: - "area: ACPI" tests: @@ -128,14 +130,17 @@ ARC arch: status: maintained maintainers: - ruuddw + - evgeniy-paltsev collaborators: - abrodkin - - evgeniy-paltsev files: - arch/arc/ - include/zephyr/arch/arc/ + - drivers/timer/*arcv2* + - drivers/interrupt_controller/*arcv2* - tests/arch/arc/ - - dts/arc/synopsys/ + - dts/arc/ + - dts/bindings/arc/ - doc/hardware/arch/arc-support-status.rst labels: - "area: ARC" @@ -199,6 +204,8 @@ ARM Platforms: - soc/arm/designstart/ - soc/arm/fvp_aemv8*/ - dts/arm/armv*.dtsi + - dts/bindings/arm/arm*.yaml + - drivers/interrupt_controller/intc_gic* labels: - "platform: ARM" @@ -237,10 +244,11 @@ MIPS arch: - arch.mips Ambiq Platforms: - status: odd fixes + status: maintained + maintainers: + - AlessandroLuo collaborators: - aaronyegx - - AlessandroLuo - RichardSWheatley files: - soc/ambiq/ @@ -293,47 +301,6 @@ Binary Descriptors: tests: - bindesc -Bluetooth: - status: maintained - maintainers: - - jhedberg - collaborators: - - hermabe - - Vudentz - - Thalley - - asbjornsabo - - sjanc - files: - - doc/connectivity/bluetooth/ - - include/zephyr/bluetooth/ - - samples/bluetooth/ - - subsys/bluetooth/ - - subsys/bluetooth/common/ - - tests/bluetooth/ - - tests/bsim/bluetooth/ - files-exclude: - - include/zephyr/bluetooth/mesh/ - - subsys/bluetooth/controller/ - - subsys/bluetooth/host/ - - subsys/bluetooth/mesh/ - - samples/bluetooth/mesh/ - - subsys/bluetooth/audio/ - - include/zephyr/bluetooth/audio/ - - tests/bsim/bluetooth/audio/ - - tests/bsim/bluetooth/host/ - - tests/bsim/bluetooth/ll/ - - tests/bluetooth/controller/ - - tests/bluetooth/host*/ - - tests/bluetooth/mesh_*/ - - tests/bluetooth/mesh/ - - tests/bluetooth/audio/ - - tests/bsim/bluetooth/mesh/ - - tests/bluetooth/shell/audio* - labels: - - "area: Bluetooth" - tests: - - bluetooth - Bluetooth HCI: status: maintained maintainers: @@ -350,6 +317,8 @@ Bluetooth HCI: - include/zephyr/drivers/bluetooth/ - drivers/bluetooth/ - samples/bluetooth/hci_*/ + - tests/bsim/bluetooth/hci_uart/ + - dts/bindings/bluetooth/ labels: - "area: Bluetooth Host" - "area: Bluetooth" @@ -369,7 +338,16 @@ Bluetooth controller: - wopu-ot - erbr-ot files: + - doc/connectivity/bluetooth/bluetooth-ctlr-arch.rst + - doc/connectivity/bluetooth/img/ctlr* + - doc/connectivity/bluetooth/api/controller.rst + - include/zephyr/bluetooth/controller.h + - subsys/bluetooth/common/ - subsys/bluetooth/controller/ + - subsys/bluetooth/crypto/ + - subsys/bluetooth/shell/ll.c + - subsys/bluetooth/shell/ll.h + - subsys/bluetooth/shell/ticker.c - tests/bluetooth/controller/ - tests/bsim/bluetooth/ll/ labels: @@ -390,11 +368,60 @@ Bluetooth Host: - sjanc - theob-pro files: + - doc/connectivity/bluetooth/ + - include/zephyr/bluetooth/ + - samples/bluetooth/ + - subsys/bluetooth/common/ + - subsys/bluetooth/crypto/ - subsys/bluetooth/host/ + - subsys/bluetooth/lib/ - subsys/bluetooth/services/ - subsys/bluetooth/shell/ - - tests/bluetooth/host*/ - - tests/bsim/bluetooth/host/ + - subsys/bluetooth/CMakeLists.txt + - subsys/bluetooth/Kconfig* + - tests/bluetooth/ + - tests/bsim/bluetooth/ + files-exclude: + - subsys/bluetooth/host/classic/ + - include/zephyr/bluetooth/audio/ + - include/zephyr/bluetooth/classic/ + - include/zephyr/bluetooth/mesh/ + - include/zephyr/bluetooth/iso.h + - include/zephyr/bluetooth/controller.h + - include/zephyr/bluetooth/mesh.h + - doc/connectivity/bluetooth/bluetooth-ctlr-arch.rst + - doc/connectivity/bluetooth/autopts/ + - doc/connectivity/bluetooth/img/ctlr* + - doc/connectivity/bluetooth/api/audio/ + - doc/connectivity/bluetooth/api/mesh/ + - doc/connectivity/bluetooth/api/shell/iso.rst + - doc/connectivity/bluetooth/api/controller.rst + - samples/bluetooth/bap*/ + - samples/bluetooth/cap*/ + - samples/bluetooth/hap*/ + - samples/bluetooth/hci_*/ + - samples/bluetooth/pbp*/ + - samples/bluetooth/tmap*/ + - samples/bluetooth/iso_*/ + - samples/bluetooth/mesh*/ + - subsys/bluetooth/shell/bredr.c + - subsys/bluetooth/shell/iso.c + - subsys/bluetooth/shell/ll.c + - subsys/bluetooth/shell/ll.h + - subsys/bluetooth/shell/ticker.c + - subsys/bluetooth/Kconfig.iso + - subsys/bluetooth/host/iso.c + - subsys/bluetooth/host/iso_internal.h + - tests/bluetooth/audio/ + - tests/bluetooth/controller/ + - tests/bluetooth/mesh*/ + - tests/bluetooth/qualification/ + - tests/bluetooth/tester/ + - tests/bsim/bluetooth/audio/ + - tests/bsim/bluetooth/audio_samples/ + - tests/bsim/bluetooth/hci_uart/ + - tests/bsim/bluetooth/ll/ + - tests/bsim/bluetooth/mesh/ labels: - "area: Bluetooth Host" - "area: Bluetooth" @@ -411,12 +438,15 @@ Bluetooth Mesh: - akredalen - HaavardRei - omkar3141 + - KyraLengfeld files: - - subsys/bluetooth/mesh/ + - doc/connectivity/bluetooth/api/mesh/ - include/zephyr/bluetooth/mesh/ + - include/zephyr/bluetooth/mesh.h + - samples/bluetooth/mesh*/ + - subsys/bluetooth/mesh/ - tests/bluetooth/mesh*/ - tests/bsim/bluetooth/mesh/ - - samples/bluetooth/mesh/ labels: - "area: Bluetooth Mesh" - "area: Bluetooth" @@ -437,19 +467,23 @@ Bluetooth Audio: - kruithofa - larsgk - pin-zephyr + - niym-ot + - jthm-ot files: - subsys/bluetooth/audio/ - include/zephyr/bluetooth/audio/ - tests/bluetooth/audio/ - tests/bsim/bluetooth/audio/ + - tests/bsim/bluetooth/audio_samples/ - tests/bluetooth/shell/audio.conf - tests/bluetooth/tester/overlay-le-audio.conf + - tests/bluetooth/tester/src/audio/ - doc/connectivity/bluetooth/api/audio/ - - samples/bluetooth/broadcast_audio*/ + - samples/bluetooth/bap*/ + - samples/bluetooth/cap*/ - samples/bluetooth/hap*/ - - samples/bluetooth/public_broadcast*/ + - samples/bluetooth/pbp*/ - samples/bluetooth/tmap*/ - - samples/bluetooth/unicast_audio*/ labels: - "area: Bluetooth Audio" - "area: Bluetooth" @@ -464,10 +498,50 @@ Bluetooth Classic: - jhedberg - sjanc files: + - subsys/bluetooth/common/ - subsys/bluetooth/host/classic/ + - subsys/bluetooth/shell/bredr.c - include/zephyr/bluetooth/classic/ labels: - "area: Bluetooth Classic" + - "area: Bluetooth" + tests: + - bluetooth + +Bluetooth ISO: + status: maintained + maintainers: + - Thalley + collaborators: + - jhedberg + files: + - include/zephyr/bluetooth/iso.h + - doc/connectivity/bluetooth/api/shell/iso.rst + - samples/bluetooth/iso_*/ + - subsys/bluetooth/shell/iso.c + - subsys/bluetooth/Kconfig.iso + - subsys/bluetooth/host/iso.c + - subsys/bluetooth/host/iso_internal.h + labels: + - "area: Bluetooth ISO" + - "area: Bluetooth" + tests: + - bluetooth + +Bluetooth Qualification: + status: maintained + maintainers: + - sjanc + collaborators: + - Thalley + - jhedberg + files: + - doc/connectivity/bluetooth/autopts/ + - tests/bluetooth/qualification/ + - tests/bluetooth/tester/ + labels: + - "area: Bluetooth Qualification" + - "area: Bluetooth" tests: - bluetooth @@ -590,6 +664,22 @@ CMSIS API layer: - portability.cmsis_rtos_v1 - portability.cmsis_rtos_v2 +DAP: + status: maintained + maintainers: + - jfischer-no + collaborators: + - maxd-nordic + files: + - include/zephyr/drivers/swdp.h + - drivers/dp/ + - subsys/dap/ + - samples/subsys/dap/ + description: >- + Debug Access Port controller + labels: + - "area: dap" + DSP subsystem: status: maintained maintainers: @@ -646,6 +736,7 @@ Coding Guidelines: - nashif - carlescufi - jfischer-no + - simhein files: - .checkpatch.conf - .clang-format @@ -668,8 +759,8 @@ Coding Guidelines: - "area: Coding Guidelines" Common Architecture Interface: - status: odd fixes - collaborators: + status: maintained + maintainers: - dcpleung - nashif files: @@ -713,6 +804,32 @@ Debug: tests: - debug +"Debug: Profiling: Perf": + status: odd fixes + files: + - doc/services/profiling/perf.rst + - samples/subsys/profiling/perf/ + - scripts/profiling/stackcollapse.py + - subsys/profiling/perf/ + labels: + - "area: Profiling / Perf" + tests: + - debug.profiling.perf + +"Debug: Symtab": + status: maintained + maintainers: + - ycsin + files: + - include/zephyr/debug/symtab.h + - subsys/debug/symtab/ + - tests/subsys/debug/symtab/ + - scripts/build/gen_symtab.py + labels: + - "area: Symtab" + tests: + - debug.symtab + Demand Paging: status: maintained maintainers: @@ -731,8 +848,8 @@ Device Driver Model: status: maintained maintainers: - gmarull - collaborators: - tbursztyka + collaborators: - dcpleung - nashif files: @@ -763,11 +880,12 @@ DFU: - dfu Devicetree: - status: maintained - maintainers: - - galak + status: odd fixes collaborators: - decsny + - galak + files-regex: + - dts/bindings/.*zephyr.* files: - scripts/dts/ - dts/common/ @@ -775,7 +893,11 @@ Devicetree: - doc/build/dts/ - include/zephyr/devicetree/ - scripts/kconfig/kconfigfunctions.py + - doc/build/kconfig/preprocessor-functions.rst - include/zephyr/devicetree.h + - include/zephyr/dt-bindings/dt-util.h + - dts/binding-template.yaml + - dts/bindings/base/ files-exclude: - dts/common/nordic/ labels: @@ -783,19 +905,6 @@ Devicetree: tests: - libraries.devicetree -Devicetree Bindings: - status: maintained - maintainers: - - galak - collaborators: - - decsny - files: - - dts/bindings/ - - include/zephyr/dt-bindings/ - - dts/binding-template.yaml - labels: - - "area: Devicetree Binding" - Disk: status: maintained maintainers: @@ -812,6 +921,9 @@ Disk: - tests/subsys/sd/ - tests/drivers/disk/ - include/zephyr/sd/ + - dts/bindings/sd/ + - dts/bindings/mmc/ + - dts/bindings/disk/ labels: - "area: Disk Access" tests: @@ -825,15 +937,20 @@ Display drivers: files: - drivers/display/ - dts/bindings/display/ + - include/zephyr/dt-bindings/display/ - include/zephyr/drivers/display.h - include/zephyr/display/ - include/zephyr/drivers/display.h - subsys/fb/ - samples/subsys/display/ + - tests/subsys/display/ - doc/hardware/peripherals/display/ - tests/drivers/*/display/ labels: - "area: Display" + tests: + - display.cfb + - drivers.display Documentation: status: maintained @@ -852,18 +969,19 @@ Documentation: - doc/project/ - doc/releases/ - doc/security/ + - doc/safety/ - README.rst - doc/substitutions.txt - doc/images/Zephyr-Kite-in-tree.png - doc/index-tex.rst - doc/index.rst - - doc/known-warnings.txt - doc/templates/sample.tmpl - doc/templates/board.tmpl - boards/index.rst files-exclude: - doc/releases/migration-guide-* - doc/releases/release-notes-* + - doc/develop/test/ labels: - "area: Documentation" @@ -871,10 +989,10 @@ Documentation Infrastructure: status: maintained maintainers: - gmarull + - kartben collaborators: - carlescufi - nashif - - kartben files: - doc/_*/ - doc/CMakeLists.txt @@ -887,8 +1005,8 @@ Documentation Infrastructure: Release Notes: status: maintained maintainers: - - nashif - - aescolar + - dkalowsk + - mmahadevan108 collaborators: - kartben files: @@ -912,6 +1030,7 @@ Release Notes: - doc/hardware/peripherals/adc.rst - tests/drivers/build_all/adc/ - include/zephyr/dt-bindings/adc/ + - dts/bindings/adc/ labels: - "area: ADC" tests: @@ -922,7 +1041,6 @@ Release Notes: collaborators: - lyakh - lgirdwood - - marc-hb - kv2019i files: - drivers/audio/ @@ -988,6 +1106,7 @@ Release Notes: - samples/modules/canopennode/ - samples/net/sockets/can/ - samples/subsys/canbus/ + - scripts/west_commands/runners/canopen_program.py - subsys/canbus/ - subsys/net/l2/canbus/ - tests/drivers/build_all/can/ @@ -1005,7 +1124,7 @@ Release Notes: maintainers: - rriveramcrus collaborators: - - GRobertZieba + - RobertZ2011 files: - drivers/charger/ - dts/bindings/charger/ @@ -1026,6 +1145,7 @@ Release Notes: files: - drivers/clock_control/ - dts/bindings/clock/ + - include/zephyr/dt-bindings/clock/ - include/zephyr/drivers/clock_control.h - include/zephyr/dt-bindings/clock/ - tests/drivers/clock_control/ @@ -1089,6 +1209,7 @@ Release Notes: - include/zephyr/crypto/ - samples/drivers/crypto/ - tests/crypto/ + - doc/services/crypto/ labels: - "area: Crypto / RNG" tests: @@ -1101,6 +1222,8 @@ Release Notes: files: - drivers/dac/ - include/zephyr/drivers/dac.h + - dts/bindings/dac/ + - include/zephyr/dt-bindings/dac/ - tests/drivers/dac/ - samples/drivers/dac/ - doc/hardware/peripherals/dac.rst @@ -1124,6 +1247,8 @@ Release Notes: - drivers/dai/ - doc/hardware/peripherals/audio/dai.rst - include/zephyr/drivers/dai.h + - include/zephyr/dt-bindings/dai/ + - dts/bindings/dai/ labels: - "area: DAI" @@ -1148,6 +1273,8 @@ Release Notes: - drivers/dma/ - tests/drivers/dma/ - include/zephyr/drivers/dma/ + - dts/bindings/dma/ + - include/zephyr/dt-bindings/dma/ - doc/hardware/peripherals/dma.rst - include/zephyr/drivers/dma.h - include/zephyr/dt-bindings/dma/ @@ -1184,7 +1311,7 @@ Release Notes: - samples/drivers/eeprom/ - tests/drivers/eeprom/ - tests/drivers/*/eeprom/ - - doc/hardware/peripherals/eeprom.rst + - doc/hardware/peripherals/eeprom/ labels: - "area: EEPROM" tests: @@ -1194,6 +1321,8 @@ Release Notes: status: maintained maintainers: - ceolin + collaborators: + - tomi-font files: - drivers/entropy/ - include/zephyr/drivers/entropy.h @@ -1231,6 +1360,7 @@ Release Notes: collaborators: - decsny - lmajewski + - pdgendt files: - drivers/ethernet/ - include/zephyr/dt-bindings/ethernet/ @@ -1250,6 +1380,7 @@ Release Notes: files: - drivers/flash/ - dts/bindings/flash_controller/ + - include/zephyr/dt-bindings/flash_controller/ - include/zephyr/drivers/flash.h - samples/drivers/flash_shell/ - samples/drivers/soc_flash_nrf/ @@ -1305,6 +1436,7 @@ Release Notes: files: - doc/hardware/peripherals/gpio.rst - drivers/gpio/ + - dts/bindings/gpio/ - include/zephyr/drivers/gpio/ - include/zephyr/drivers/gpio.h - include/zephyr/dt-bindings/gpio/ @@ -1318,7 +1450,7 @@ Release Notes: "Drivers: GNSS": status: maintained maintainers: - - bjarki-trackunit + - bjarki-andreasen collaborators: - tomi-font - fabiobaltieri @@ -1327,6 +1459,8 @@ Release Notes: - drivers/gnss/ - include/zephyr/drivers/gnss.h - include/zephyr/drivers/gnss/ + - dts/bindings/gnss/ + - include/zephyr/dt-bindings/gnss/ - tests/drivers/build_all/gnss/ - tests/drivers/gnss/ labels: @@ -1334,6 +1468,22 @@ Release Notes: tests: - drivers.gnss +"Drivers: Haptics": + status: maintained + maintainers: + - rriveramcrus + files: + - drivers/haptics/ + - dts/bindings/haptics/ + - include/zephyr/drivers/haptics.h + - doc/hardware/peripherals/haptics.rst + - tests/drivers/build_all/haptics/ + - samples/drivers/haptics/ + labels: + - "area: Haptics" + tests: + - drivers.haptics + "Drivers: HW Info": status: maintained maintainers: @@ -1418,7 +1568,7 @@ Release Notes: - fgrandel collaborators: - rlubos - - jciupis + - ankuns - cfriedt - jukkar files: @@ -1452,6 +1602,8 @@ Release Notes: - drivers/memc/ - samples/drivers/memc/ - tests/drivers/memc/ + - include/zephyr/dt-bindings/memory-controller/ + - dts/bindings/memory-controllers/ labels: - "area: MEMC" tests: @@ -1467,6 +1619,7 @@ Release Notes: - drivers/mdio/ - include/zephyr/drivers/mdio.h - tests/drivers/build_all/mdio/ + - dts/bindings/mdio/ labels: - "area: MDIO" tests: @@ -1487,6 +1640,26 @@ Release Notes: tests: - drivers.mipi_dsi +"Drivers: MSPI": + status: maintained + maintainers: + - swift-tk + files: + - drivers/mspi/ + - drivers/memc/*mspi* + - drivers/flash/*mspi* + - include/zephyr/drivers/mspi.h + - include/zephyr/drivers/mspi/ + - samples/drivers/mspi/ + - tests/drivers/mspi/ + - doc/hardware/peripherals/mspi.rst + - dts/bindings/mspi/ + - dts/bindings/mtd/mspi* + labels: + - "area: MSPI" + tests: + - drivers.mspi + "Drivers: Reset": status: odd fixes collaborators: @@ -1494,6 +1667,8 @@ Release Notes: files: - drivers/reset/ - include/zephyr/drivers/reset.h + - dts/bindings/reset/ + - include/zephyr/dt-bindings/reset/ "Interrupt Handling": status: odd fixes @@ -1559,10 +1734,12 @@ Release Notes: - drivers/led/ - include/zephyr/drivers/led/ - include/zephyr/drivers/led.h - - samples/drivers/led_*/ + - samples/drivers/led/ - tests/drivers/led/ - doc/hardware/peripherals/led.rst - tests/drivers/build_all/led/ + - dts/bindings/led/ + - include/zephyr/dt-bindings/led/ labels: - "area: LED" tests: @@ -1571,9 +1748,9 @@ Release Notes: "Drivers: LED Strip": status: maintained maintainers: - - mbolivar-ampere - simonguinot collaborators: + - mbolivar-ampere - soburi - thedjnK files: @@ -1619,10 +1796,10 @@ Release Notes: "Drivers: Regulators": status: maintained maintainers: - - aasinclair + - gmarull collaborators: - danieldegrasse - - gmarull + - aasinclair files: - drivers/regulator/ - include/zephyr/drivers/regulator/ @@ -1631,6 +1808,7 @@ Release Notes: - tests/drivers/regulator/ - tests/drivers/build_all/regulator/ - doc/hardware/peripherals/regulators.rst + - dts/bindings/regulator/ labels: - "area: Regulators" tests: @@ -1646,6 +1824,7 @@ Release Notes: - include/zephyr/drivers/retained_mem.h - tests/drivers/retained_mem/ - doc/hardware/peripherals/retained_mem.rst + - dts/bindings/retained_mem/ labels: - "area: Retained Memory" tests: @@ -1654,7 +1833,7 @@ Release Notes: "Drivers: RTC": status: maintained maintainers: - - bjarki-trackunit + - bjarki-andreasen files: - drivers/rtc/ - include/zephyr/drivers/rtc/ @@ -1662,6 +1841,7 @@ Release Notes: - doc/hardware/peripherals/rtc.rst - include/zephyr/drivers/rtc.h - tests/drivers/build_all/rtc/ + - dts/bindings/rtc/ labels: - "area: RTC" tests: @@ -1675,6 +1855,8 @@ Release Notes: - drivers/pcie/ - include/zephyr/drivers/pcie/ - doc/hardware/peripherals/pcie.rst + - dts/bindings/pcie/ + - include/zephyr/dt-bindings/pcie/ labels: - "area: PCI" @@ -1689,6 +1871,7 @@ Release Notes: - include/zephyr/drivers/peci.h - samples/drivers/peci/ - doc/hardware/peripherals/peci.rst + - dts/bindings/peci/ labels: - "area: PECI" tests: @@ -1746,6 +1929,7 @@ Release Notes: - include/zephyr/drivers/pm_cpu_ops/ - include/zephyr/drivers/pm_cpu_ops.h - include/zephyr/arch/arm64/arm-smccc.h + - dts/bindings/pm_cpu_ops/ labels: - "area: PM CPU ops" @@ -1758,6 +1942,7 @@ Release Notes: files: - drivers/pwm/ - dts/bindings/pwm/ + - include/zephyr/dt-bindings/pwm/ - tests/drivers/pwm/ - include/zephyr/*/pwms.h - doc/hardware/peripherals/pwm.rst @@ -1814,6 +1999,7 @@ Release Notes: - yperess - tristan-google - ubieda + - jeppenodgaard files: - drivers/sensor/ - include/zephyr/drivers/sensor.h @@ -1823,7 +2009,7 @@ Release Notes: - dts/bindings/sensor/ - include/zephyr/drivers/sensor/ - include/zephyr/dt-bindings/sensor/ - - doc/hardware/peripherals/sensor.rst + - doc/hardware/peripherals/sensor/ - tests/drivers/build_all/sensor/ labels: - "area: Sensors" @@ -1856,12 +2042,29 @@ Release Notes: - drivers/spi/ - include/zephyr/drivers/spi.h - tests/drivers/spi/ + - dts/bindings/spi/ + - include/zephyr/dt-bindings/spi/ - doc/hardware/peripherals/spi.rst labels: - "area: SPI" tests: - drivers.spi +"Drivers: Stepper": + status: maintained + maintainers: + - jilaypandya + files: + - drivers/stepper/ + - include/zephyr/drivers/stepper.h + - dts/bindings/stepper/ + - doc/hardware/peripherals/stepper.rst + - tests/drivers/build_all/stepper/ + labels: + - "area: Stepper" + tests: + - drivers.stepper + "Drivers: System timer": status: maintained maintainers: @@ -1871,6 +2074,8 @@ Release Notes: files: - drivers/timer/ - include/zephyr/drivers/timer/ + - dts/bindings/timer/ + - include/zephyr/dt-bindings/timer/ labels: - "area: Timer" @@ -1878,12 +2083,15 @@ Release Notes: status: odd fixes collaborators: - loicpoulain + - josuah files: - drivers/video/ - include/zephyr/drivers/video.h - include/zephyr/drivers/video-controls.h - doc/hardware/peripherals/video.rst - tests/drivers/*/video/ + - dts/bindings/video/ + - samples/drivers/video/ labels: - "area: Video" tests: @@ -1936,6 +2144,7 @@ Release Notes: - krish2718 files: - drivers/wifi/ + - dts/bindings/wifi/ labels: - "area: Wi-Fi" @@ -1951,6 +2160,29 @@ Release Notes: labels: - "area: Wi-Fi" +"Drivers: Wi-Fi as nRF Wi-Fi": + status: maintained + maintainers: + - krish2718 + - jukkar + collaborators: + - sachinthegreen + files: + - drivers/wifi/nrfwifi/ + - dts/bindings/wifi/nordic,nrf70.yaml + - dts/bindings/wifi/nordic,nrf70-qspi.yaml + - dts/bindings/wifi/nordic,nrf70-spi.yaml + - dts/bindings/wifi/nordic,nrf70-coex.yaml + - dts/bindings/wifi/nordic,nrf7002-qspi.yaml + - dts/bindings/wifi/nordic,nrf7002-spi.yaml + - dts/bindings/wifi/nordic,nrf7000-qspi.yaml + - dts/bindings/wifi/nordic,nrf7000-spi.yaml + - dts/bindings/wifi/nordic,nrf7001-qspi.yaml + - dts/bindings/wifi/nordic,nrf7001-spi.yaml + - boards/shields/nrf7002ek/ + labels: + - "area: Wi-Fi" + "Drivers: Memory Management": status: maintained maintainers: @@ -1974,6 +2206,7 @@ Release Notes: files: - drivers/mipi_dbi/ - dts/bindings/mipi-dbi/ + - include/zephyr/dt-bindings/mipi_dbi/ labels: - "area: Display Controller" @@ -2021,6 +2254,7 @@ Xen Platform: - arch/arm64/core/xen/ - soc/xen/ - boards/xen/ + - dts/bindings/xen/ labels: - "area: Xen Platform" @@ -2036,6 +2270,7 @@ Filesystems: - samples/subsys/fs/ - subsys/fs/ - tests/subsys/fs/ + - dts/bindings/fs/ labels: - "area: File System" tests: @@ -2077,9 +2312,11 @@ Google Platforms: maintainers: - fabiobaltieri - keith-zephyr + collaborators: + - duda-patryk files: - boards/google/ - - samples/boards/google_*/ + - samples/boards/google/ Hash Utilities: status: maintained @@ -2134,6 +2371,8 @@ IPC: - subsys/ipc/ - tests/subsys/ipc/ - doc/services/ipc/ + - dts/bindings/ipc/ + - include/zephyr/dt-bindings/ipc_service/ description: >- Inter-Processor Communication labels: @@ -2300,21 +2539,22 @@ Memory Management: - tests/lib/mem_blocks/ - doc/services/mem_mgmt/ - include/zephyr/mem_mgmt/mem_attr.h + - include/zephyr/dt-bindings/memory-attr/ - tests/lib/mem_blocks_stats/ - tests/drivers/mm/ tests: - mem_mgmt -Laird Connectivity platforms: +Ezurio platforms: status: maintained maintainers: - rerickson1 collaborators: - greg-leach files: - - boards/lairdconnect/ + - boards/ezurio/ labels: - - "platform: Laird Connectivity" + - "platform: Ezurio" Linker Scripts: status: maintained @@ -2381,6 +2621,8 @@ LoRa and LoRaWAN: - include/zephyr/lorawan/ - subsys/lorawan/ - samples/subsys/lorawan/ + - include/zephyr/dt-bindings/lora/ + - dts/bindings/lora/ - doc/connectivity/lora_lorawan/index.rst labels: - "area: LoRa" @@ -2402,25 +2644,6 @@ MAINTAINERS file: description: >- Zephyr Maintainers File -Mbed TLS: - status: maintained - maintainers: - - d3zd3z - - ceolin - collaborators: - - ithinuel - files: - - tests/crypto/mbedtls/ - - doc/services/crypto/ - - tests/benchmarks/mbedtls/ - labels: - - "area: Crypto / RNG" - description: >- - Mbed TLS module implementing the PSA Crypto API and TLS. - tests: - - benchmark.crypto.mbedtls - - crypto.mbedtls - MCU Manager: status: maintained maintainers: @@ -2457,7 +2680,7 @@ Modbus: Modem: status: maintained maintainers: - - bjarki-trackunit + - bjarki-andreasen collaborators: - tomi-font files: @@ -2492,8 +2715,6 @@ hawkBit: status: maintained maintainers: - maass-hamburg - collaborators: - - ycsin files: - subsys/mgmt/hawkbit/ - include/zephyr/mgmt/hawkbit.h @@ -2566,9 +2787,11 @@ Networking: files-exclude: - doc/connectivity/networking/api/gptp.rst - doc/connectivity/networking/api/ieee802154.rst + - doc/connectivity/networking/api/ptp.rst - doc/connectivity/networking/api/wifi.rst - include/zephyr/net/gptp.h - include/zephyr/net/ieee802154*.h + - include/zephyr/net/ptp.h - include/zephyr/net/wifi*.h - include/zephyr/net/buf.h - include/zephyr/net/dhcpv4*.h @@ -2577,13 +2800,13 @@ Networking: - samples/net/lwm2m_client/ - samples/net/wifi/ - samples/net/dhcpv4_client/ - - subsys/net/buf*.c - subsys/net/l2/ethernet/gptp/ - subsys/net/l2/ieee802154/ - subsys/net/l2/wifi/ - subsys/net/lib/coap/ - subsys/net/lib/config/ieee802154* - subsys/net/lib/lwm2m/ + - subsys/net/lib/ptp/ - subsys/net/lib/tls_credentials/ - subsys/net/lib/dhcpv4/ - tests/net/dhcpv4/ @@ -2609,7 +2832,7 @@ Networking: tests: - net.socket -"Networking: Buffers": +"Networking Buffers": status: maintained maintainers: - jhedberg @@ -2618,13 +2841,15 @@ Networking: - tbursztyka - jukkar files: + - doc/services/net_buf/ - include/zephyr/net/buf.h - - subsys/net/buf*.c - - tests/net/buf/ + - include/zephyr/net_buf.h + - lib/net_buf/ + - tests/lib/net_buf/ labels: - "area: Networking Buffers" tests: - - net.buf + - libraries.net_buf "Networking: Connection Manager": status: maintained @@ -2739,6 +2964,20 @@ Networking: tests: - net.mqtt_sn +"Networking: PTP": + status: maintained + maintainers: + - awojasinski + files: + - doc/connectivity/networking/api/ptp.rst + - include/zephyr/net/ptp.h + - subsys/net/lib/ptp/ + - samples/net/ptp/ + labels: + - "area: Networking" + tests: + - sample.net.ptp + "Networking: Native IEEE 802.15.4": status: maintained maintainers: @@ -2839,7 +3078,13 @@ Open AMP: - carlocaione files: - lib/open-amp/ - + - samples/subsys/ipc/openamp/ + - samples/subsys/ipc/openamp_rsc_table/ + - samples/subsys/ipc/rpmsg_service/ + labels: + - "area: Open AMP" + tests: + - sample.ipc.openamp POSIX API layer: status: maintained @@ -2876,6 +3121,8 @@ Power management: - tests/subsys/pm/ - doc/services/pm/ - drivers/power_domain/ + - dts/bindings/power/ + - include/zephyr/dt-bindings/power/ labels: - "area: Power Management" tests: @@ -2904,6 +3151,8 @@ RISCV arch: - ycsin files: - arch/riscv/ + - boards/enjoydigital/litex_vexriscv/ + - boards/lowrisc/opentitan_earlgrey/ - boards/qemu/riscv*/ - boards/sifive/ - boards/sparkfun/red_v_things_plus/ @@ -2961,10 +3210,12 @@ Sensor Subsystem: - doc/services/sensing/ - subsys/sensing/ - samples/subsys/sensing/ + - tests/subsys/sensing/ labels: - "area: Sensor Subsystem" tests: - sample.sensing + - sensing.api Stats: status: odd fixes @@ -2981,7 +3232,6 @@ Twister: collaborators: - PerMac - hakehuang - - gopiotr - golowanow - gchwier - LukaszMrugala @@ -3077,11 +3327,13 @@ State machine framework: - sambhurst collaborators: - keith-zephyr + - glenn-andrews files: - doc/services/smf/ - include/zephyr/smf.h - lib/smf/ - tests/lib/smf/ + - samples/subsys/smf/ labels: - "area: State Machine Framework" tests: @@ -3092,20 +3344,25 @@ ADI Platforms: maintainers: - MaureenHelm collaborators: + - ozersa + - ttmut - galak - microbuilder files: - boards/adi/ - - drivers/*/max* + - boards/shields/pmod_acl/ + - drivers/*/*max* - drivers/*/*max*/ - drivers/dac/dac_ltc* - drivers/ethernet/eth_adin* - drivers/mdio/mdio_adin* - drivers/regulator/regulator_adp5360* - drivers/sensor/adi/ + - dts/arm/adi/ - dts/bindings/*/adi,* - dts/bindings/*/lltc,* - dts/bindings/*/maxim,* + - soc/adi/ labels: - "platform: ADI" @@ -3119,11 +3376,11 @@ Broadcom Platforms: GD32 Platforms: status: maintained maintainers: - - cameled - nandojve collaborators: - gmarull - soburi + - cameled files: - boards/gd/ - drivers/*/*gd32* @@ -3141,9 +3398,9 @@ Synopsys Platforms: status: maintained maintainers: - ruuddw + - evgeniy-paltsev collaborators: - abrodkin - - evgeniy-paltsev files: - soc/snps/ - boards/snps/ @@ -3153,6 +3410,8 @@ Synopsys Platforms: - scripts/west_commands/tests/test_mdb.py - scripts/west_commands/runners/nsim.py - cmake/emu/nsim.cmake + - drivers/serial/uart_hostlink.c + - drivers/serial/Kconfig.hostlink labels: - "platform: Synopsys" @@ -3195,6 +3454,19 @@ Nuvoton Numicro Numaker Platforms: labels: - "platform: Nuvoton Numicro Numaker" +Nuvoton NPCM Platforms: + status: maintained + maintainers: + - maxdog988 + - warp5tw + - jc849 + files: + - soc/nuvoton/npcm/ + - boards/nuvoton/npcm*/ + - dts/arm/nuvoton/ + labels: + - "platform: Nuvoton NPCM" + Raspberry Pi Pico Platforms: status: maintained maintainers: @@ -3214,8 +3486,13 @@ Raspberry Pi Pico Platforms: labels: - "platform: Raspberry Pi Pico" -SiLabs Platforms: - status: odd fixes +Silabs Platforms: + status: maintained + maintainers: + - jhedberg + collaborators: + - jerome-pouiller + - asmellby files: - soc/silabs/ - boards/silabs/ @@ -3223,7 +3500,28 @@ SiLabs Platforms: - dts/bindings/*/silabs* - drivers/*/*_gecko* labels: - - "platform: SiLabs" + - "platform: Silabs" + +Silabs SiM3U Platforms: + status: maintained + maintainers: + - rettichschnidi + collaborators: + - M1cha + - asmellby + - jerome-pouiller + - jhedberg + files: + - boards/silabs/dev_kits/sim3u1xx_dk/ + - drivers/*/*_si32* + - drivers/*/Kconfig.si32 + - dts/arm/silabs/sim3u* + - dts/bindings/*/*silabs,si32* + - soc/silabs/silabs_sim3/ + labels: + - "platform: Silabs SiM3U" + description: >- + SiM3U SoCs, dts files, and related drivers. Boards based on SiM3U SoCs. Intel Platforms (X86): status: maintained @@ -3256,7 +3554,6 @@ Intel Platforms (Xtensa): - andyross - lyakh - lgirdwood - - marc-hb - kv2019i - ceolin - tmleman @@ -3269,7 +3566,7 @@ Intel Platforms (Xtensa): - soc/intel/intel_adsp/ - dts/xtensa/intel/ - tests/boards/intel_adsp/ - - samples/boards/intel_adsp/ + - samples/boards/intel/adsp/ - dts/bindings/*/intel,adsp* - scripts/west_commands/runners/intel_adsp.py labels: @@ -3312,12 +3609,16 @@ NXP Drivers: status: maintained maintainers: - dleach02 - collaborators: - mmahadevan108 + collaborators: - danieldegrasse - decsny - manuargue - dbaluta + - MarkWangChinese + files-regex: + - ^drivers/.*nxp.* + - ^drivers/.*mcux.* files: - drivers/*/*imx* - drivers/*/*lpc*.c @@ -3329,6 +3630,8 @@ NXP Drivers: - drivers/misc/*/nxp* - include/zephyr/dt-bindings/*/*nxp* - include/zephyr/dt-bindings/*/*mcux* + - include/zephyr/dt-bindings/inputmux/ + - include/zephyr/dt-bindings/rdc/ - include/zephyr/drivers/*/*nxp* - include/zephyr/drivers/*/*mcux* - arch/arm/core/mpu/nxp_mpu.c @@ -3343,8 +3646,8 @@ NXP Platforms (MCU): status: maintained maintainers: - dleach02 - collaborators: - mmahadevan108 + collaborators: - danieldegrasse - DerekSnell - yvanderv @@ -3389,7 +3692,7 @@ NXP Platforms (S32): - drivers/misc/*nxp_s32*/ - dts/bindings/*/nxp,s32* - dts/arm/nxp/*s32* - - samples/boards/nxp_s32/ + - samples/boards/nxp/s32/ - include/zephyr/dt-bindings/*/nxp-s32* - include/zephyr/dt-bindings/*/nxp_s32* - include/zephyr/drivers/*/*nxp_s32* @@ -3449,6 +3752,20 @@ Microchip MEC Platforms: labels: - "platform: Microchip MEC" +Microchip RISC-V Platforms: + status: maintained + maintainers: + - fkokosinski + - kgugala + - tgorochowik + files: + - boards/microchip/m2gl025_miv/ + - boards/microchip/mpfs_icicle/ + - dts/riscv/microchip/ + - soc/microchip/miv/ + labels: + - "platform: Microchip RISC-V" + Microchip SAM Platforms: status: maintained maintainers: @@ -3482,7 +3799,7 @@ nRF Platforms: - drivers/*/*nrf*.c - drivers/*/*nordic*/ - soc/nordic/ - - samples/boards/nrf/ + - samples/boards/nordic/ - dts/*/nordic/ - dts/bindings/*/nordic,* - tests/drivers/*/*nrf*/ @@ -3511,6 +3828,8 @@ Renesas SmartBond Platforms: - ioannis-karachalios - andrzej-kaczmarek - blauret + collaborators: + - ydamigos files: - boards/renesas/da14*/ - drivers/*/*smartbond* @@ -3528,15 +3847,20 @@ Renesas RA Platforms: status: maintained maintainers: - soburi + - KhiemNguyenT + collaborators: + - duynguyenxa + - thaoluonguw files: - boards/arduino/uno_r4/ + - boards/renesas/*ra*/ - drivers/*/*renesas_ra* - drivers/pinctrl/renesas/ra/ - dts/arm/renesas/ra/ - dts/bindings/*/*renesas,ra* - soc/renesas/ra/ labels: - - "platforms: Renesas RA" + - "platform: Renesas RA" description: >- Renesas RA SOCs, dts files, and related drivers. Boards based on Renesas RA SoCs. @@ -3586,10 +3910,11 @@ STM32 Platforms: maintainers: - erwango collaborators: - - ajarmouni-st - FRASTM - gautierg-st - GeorgeCGV + - marwaiehm-st + - mathieuchopstm files: - boards/st/ - drivers/*/*stm32*.c @@ -3599,7 +3924,7 @@ STM32 Platforms: - dts/arm/st/ - dts/bindings/*/*stm32* - soc/st/stm32/ - - samples/boards/stm32/ + - samples/boards/st/ labels: - "platform: STM32" description: >- @@ -3614,6 +3939,8 @@ Espressif Platforms: - LucasTambor - marekmatej - uLipe + - raffarost + - wmrsouza files: - drivers/*/*esp32*.c - boards/espressif/ @@ -3621,7 +3948,7 @@ Espressif Platforms: - dts/xtensa/espressif/ - dts/riscv/espressif/ - dts/bindings/*/*esp32* - - samples/boards/esp32*/ + - samples/boards/espressif/ - tests/boards/espressif_esp32/ - drivers/*/*esp32*/ labels: @@ -3643,7 +3970,7 @@ ITE Platforms: - drivers/sensor/ite/ - drivers/*/*it8xxx2*.c - drivers/*/*_ite_* - - dts/bindings/*/*ite* + - dts/bindings/*/ite* - dts/riscv/ite/ - soc/ite/ labels: @@ -3731,6 +4058,28 @@ Infineon Platforms: Infineon SOCs, dts files and related drivers. Infineon Proto, Pioneer, Eval and Relax boards. +LiteX Platforms: + status: maintained + maintainers: + - tgorochowik + - kgugala + - fkokosinski + collaborators: + - mateusz-holenko + - maass-hamburg + files: + - boards/enjoydigital/litex_vexriscv/ + - drivers/*/*litex* + - drivers/*/Kconfig.litex + - dts/bindings/*/litex* + - dts/riscv/riscv32-litex-vexriscv.dtsi + - include/zephyr/drivers/*/*litex* + - samples/boards/enjoydigital/litex/ + - samples/drivers/*litex/ + - soc/litex/ + labels: + - "platform: LiteX" + Panasonic Platforms: status: maintained maintainers: @@ -3746,6 +4095,7 @@ RTIO: - teburd collaborators: - yperess + - ubieda files: - samples/subsys/rtio/ - include/zephyr/rtio/ @@ -3836,23 +4186,6 @@ TDK Sensors: tests: - sample.drivers.misc.timeaware_gpio -TF-M Integration: - status: maintained - maintainers: - - d3zd3z - collaborators: - - Vge0rge - - ithinuel - files: - - samples/tfm_integration/ - - modules/trusted-firmware-m/ - - doc/services/tfm/ - labels: - - "area: TF-M" - tests: - - tfm - - "Toolchain Integration": status: maintained maintainers: @@ -3877,6 +4210,7 @@ TF-M Integration: files: - cmake/*/arcmwdt/ - include/zephyr/toolchain/mwdt.h + - include/zephyr/linker/linker-tool-mwdt.h - lib/libc/arcmwdt/* labels: - "area: Toolchains" @@ -3931,6 +4265,7 @@ USB: files: - drivers/usb/ - dts/bindings/usb/ + - include/zephyr/dt-bindings/usb/ - include/zephyr/*/usb/ - include/zephyr/usb/ - samples/subsys/usb/ @@ -3939,7 +4274,6 @@ USB: - tests/drivers/usb/ - tests/drivers/udc/ - doc/connectivity/usb/ - - scripts/generate_usb_vif/ labels: - "area: USB" tests: @@ -3955,12 +4289,14 @@ USB-C: files: - drivers/usb_c/ - dts/bindings/usb-c/ + - include/zephyr/dt-bindings/usb-c/ - include/zephyr/*/usb_c/ - include/zephyr/usb_c/ - samples/subsys/usb_c/ - subsys/usb/usb_c/ - doc/connectivity/usb/pd/ - doc/hardware/peripherals/usbc_vbus.rst + - scripts/generate_usb_vif/ labels: - "area: USB-C" tests: @@ -4012,12 +4348,12 @@ VFS: - filesystem West: - status: maintained - maintainers: - - mbolivar-ampere + status: odd fixes collaborators: + - mbolivar-ampere - carlescufi - swinslow + - pdgendt files: - scripts/west-commands.yml - scripts/west_commands/ @@ -4160,7 +4496,7 @@ West: files: - modules/cmsis/ labels: - - "area: ARM" + - "area: CMSIS-Core" "West project: cmsis-dsp": status: maintained @@ -4204,6 +4540,17 @@ West: labels: - "area: Storage" +"West project: hal_adi": + status: maintained + maintainers: + - MaureenHelm + collaborators: + - ozersa + - ttmut + files: [] + labels: + - "platform: ADI" + "West project: hal_altera": status: odd fixes collaborators: @@ -4267,7 +4614,7 @@ West: - drivers/misc/ethos_u/ - modules/hal_ethos_u/ labels: - - "area: ARM" + - "platform: ARM" "West project: hal_gigadevice": status: maintained @@ -4315,6 +4662,11 @@ West: collaborators: - hubertmis - nordic-krch + - krish2718 + - sachinthegreen + - udaynordic + - rajb9 + - srkanordic files: - modules/hal_nordic/ labels: @@ -4333,8 +4685,8 @@ West: status: maintained maintainers: - dleach02 - collaborators: - mmahadevan108 + collaborators: - danieldegrasse - manuargue - PetervdPerk-NXP @@ -4372,6 +4724,10 @@ West: collaborators: - blauret - andrzej-kaczmarek + - ydamigos + - soburi + - duynguyenxa + - thaoluonguw files: [] labels: - "platform: Renesas" @@ -4386,15 +4742,20 @@ West: - "platform: Raspberry Pi Pico" "West project: hal_silabs": - status: odd fixes + status: maintained + maintainers: + - jhedberg collaborators: + - jerome-pouiller + - asmellby - sateeshkotapati - yonsch - mnkp + - rettichschnidi files: - modules/Kconfig.silabs labels: - - "platform: SiLabs" + - "platform: Silabs" "West project: hal_st": status: maintained @@ -4411,9 +4772,8 @@ West: - erwango collaborators: - FRASTM - - ABOSTM - gautierg-st - - Desvauxm-st + - marwaiehm-st files: - modules/Kconfig.stm32 labels: @@ -4516,15 +4876,17 @@ West: files: - modules/lvgl/ - tests/lib/gui/lvgl/ + - include/zephyr/dt-bindings/lvgl/ labels: - "area: LVGL" "West project: lz4": status: odd fixes collaborators: - - Navin-Sankar + - parthitce files: - modules/lz4/ + - samples/modules/compression/lz4/ labels: - "area: Compression" @@ -4535,10 +4897,17 @@ West: - ceolin collaborators: - ithinuel + - valeriosetti + - tomi-font files: - modules/mbedtls/ + - tests/crypto/mbedtls/ + - tests/benchmarks/mbedtls/ labels: - - "area: Crypto / RNG" + - "area: mbedTLS / PSA Crypto" + tests: + - benchmark.crypto.mbedtls + - crypto.mbedtls "West project: mcuboot": status: maintained @@ -4549,7 +4918,7 @@ West: - nordicjm files: - modules/Kconfig.mcuboot - - tests/boot/test_mcuboot/ + - tests/boot/ labels: - "area: MCUBoot" @@ -4658,7 +5027,6 @@ West: - nashif - lyakh - lgirdwood - - marc-hb files: - modules/Kconfig.sof labels: @@ -4702,10 +5070,16 @@ West: collaborators: - Vge0rge - ithinuel + - valeriosetti + - tomi-font files: - modules/trusted-firmware-m/ + - samples/tfm_integration/ + - doc/services/tfm/ labels: - "area: TF-M" + tests: + - trusted-firmware-m "West project: tf-m-tests": status: maintained @@ -4833,6 +5207,7 @@ Continuous Integration: files: - .github/ - scripts/ci/ + - scripts/make_bugs_pickle.py - .checkpatch.conf - scripts/gitlint/ - scripts/set_assignees.py @@ -4854,7 +5229,7 @@ Test Framework (Ztest): - tests/unit/util/ - tests/subsys/testsuite/ - samples/subsys/testsuite/ - - doc/develop/test/ztest.rst + - doc/develop/test/ labels: - "area: Testsuite" tests: @@ -4888,6 +5263,8 @@ Random: status: maintained maintainers: - ceolin + collaborators: + - tomi-font files: - subsys/random/ - include/zephyr/random/ @@ -4896,7 +5273,7 @@ Random: # This area is to be converted to a subarea Testing with Renode: - status: maintained + status: odd fixes collaborators: - mateusz-holenko - fkokosinski @@ -4936,6 +5313,6 @@ zbus: - subsys/llext/ - doc/services/llext/ labels: - - "area: Linkable Loadable Extensions" + - "area: llext" tests: - llext diff --git a/README.rst b/README.rst index 45a3998194d..2b44d5ed4a5 100644 --- a/README.rst +++ b/README.rst @@ -10,12 +10,15 @@

- - - + + + + + + + + + The Zephyr Project is a scalable real-time operating system (RTOS) supporting diff --git a/SDK_VERSION b/SDK_VERSION index e35e56114f4..74aaa3f38cf 100644 --- a/SDK_VERSION +++ b/SDK_VERSION @@ -1 +1 @@ -0.16.5-1 +0.16.8 diff --git a/VERSION b/VERSION index 11cab989b0b..83bbbb1d942 100644 --- a/VERSION +++ b/VERSION @@ -1,5 +1,5 @@ VERSION_MAJOR = 3 -VERSION_MINOR = 6 +VERSION_MINOR = 7 PATCHLEVEL = 99 VERSION_TWEAK = 0 EXTRAVERSION = diff --git a/arch/Kconfig b/arch/Kconfig index 03432871bd0..da35a1b2751 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -24,6 +24,7 @@ config ARC imply XIP select ARCH_HAS_THREAD_LOCAL_STORAGE select ARCH_SUPPORTS_ROM_START + select ARCH_HAS_DIRECTED_IPIS help ARC architecture @@ -31,6 +32,7 @@ config ARM bool select ARCH_IS_SET select ARCH_SUPPORTS_COREDUMP if CPU_CORTEX_M + select ARCH_SUPPORTS_COREDUMP_THREADS if CPU_CORTEX_M # FIXME: current state of the code for all ARM requires this, but # is really only necessary for Cortex-M with ARM MPU! select GEN_PRIV_STACKS @@ -50,6 +52,9 @@ config ARM64 select USE_SWITCH_SUPPORTED select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD select BARRIER_OPERATIONS_ARCH + select ARCH_HAS_DIRECTED_IPIS + select ARCH_HAS_DEMAND_PAGING + select ARCH_HAS_DEMAND_MAPPING help ARM64 (AArch64) architecture @@ -92,6 +97,7 @@ config X86 && !SOC_HAS_TIMING_FUNCTIONS select ARCH_HAS_STACK_CANARIES_TLS select ARCH_SUPPORTS_MEM_MAPPED_STACKS if X86_MMU && !DEMAND_PAGING + select ARCH_HAS_THREAD_PRIV_STACK_SPACE_GET if USERSPACE help x86 architecture @@ -108,15 +114,17 @@ config RISCV bool select ARCH_IS_SET select ARCH_SUPPORTS_COREDUMP - select ARCH_SUPPORTS_ROM_START if !SOC_SERIES_ESP32C3 + select ARCH_SUPPORTS_ROM_START if !SOC_FAMILY_ESPRESSIF_ESP32 + select ARCH_SUPPORTS_EMPTY_IRQ_SPURIOUS select ARCH_HAS_CODE_DATA_RELOCATION select ARCH_HAS_THREAD_LOCAL_STORAGE select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD select USE_SWITCH_SUPPORTED select USE_SWITCH select SCHED_IPI_SUPPORTED if SMP + select ARCH_HAS_DIRECTED_IPIS select BARRIER_OPERATIONS_BUILTIN - imply XIP + select ARCH_HAS_THREAD_PRIV_STACK_SPACE_GET if USERSPACE help RISCV architecture @@ -129,6 +137,9 @@ config XTENSA select ARCH_HAS_CODE_DATA_RELOCATION select ARCH_HAS_TIMING_FUNCTIONS select ARCH_MEM_DOMAIN_DATA if USERSPACE + select ARCH_HAS_DIRECTED_IPIS + select THREAD_STACK_INFO + select ARCH_HAS_THREAD_PRIV_STACK_SPACE_GET if USERSPACE help Xtensa architecture @@ -139,6 +150,7 @@ config ARCH_POSIX select ARCH_HAS_CUSTOM_SWAP_TO_MAIN select ARCH_HAS_CUSTOM_BUSY_WAIT select ARCH_HAS_THREAD_ABORT + select ARCH_HAS_THREAD_NAME_HOOK select NATIVE_BUILD select HAS_COVERAGE_SUPPORT select BARRIER_OPERATIONS_BUILTIN @@ -174,8 +186,9 @@ config BIG_ENDIAN Little-endian architecture is the default and should leave this option unselected. This option is selected by arch/$ARCH/Kconfig, soc/**/Kconfig, or boards/**/Kconfig and the user should generally avoid - modifying it. The option is used to select linker script OUTPUT_FORMAT - and command line option for gen_isr_tables.py. + modifying it. The option is used to select linker script OUTPUT_FORMAT, + the toolchain flags (TOOLCHAIN_C_FLAGS, TOOLCHAIN_LD_FLAGS), and command + line option for gen_isr_tables.py. config LITTLE_ENDIAN # Hidden Kconfig option representing the default little-endian architecture @@ -209,7 +222,7 @@ config SRAM_BASE_ADDRESS hex "SRAM Base Address" default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_SRAM)) help - The SRAM base address. The default value comes from from + The SRAM base address. The default value comes from /chosen/zephyr,sram in devicetree. The user should generally avoid changing it via menuconfig or in configuration files. @@ -400,6 +413,28 @@ config NOCACHE_MEMORY transfers when cache coherence issues are not optimal or can not be solved using cache maintenance operations. +config FRAME_POINTER + bool "Compile the kernel with frame pointers" + select OVERRIDE_FRAME_POINTER_DEFAULT + help + Select Y here to gain precise stack traces at the expense of slightly + increased size and decreased speed. + +config ARCH_STACKWALK + bool "Compile the stack walking function" + default y + depends on ARCH_HAS_STACKWALK + help + Select Y here to compile the `arch_stack_walk()` function + +config ARCH_STACKWALK_MAX_FRAMES + int "Max depth for stack walk function" + default 8 + depends on ARCH_STACKWALK + help + Depending on implementation, this can place a hard limit on the depths of the stack + for the stack walk function to examine. + menu "Interrupt Configuration" config ISR_TABLES_LOCAL_DECLARATION_SUPPORTED @@ -577,6 +612,14 @@ config SIMPLIFIED_EXCEPTION_CODES down to the generic K_ERR_CPU_EXCEPTION, which makes testing code much more portable. +config EMPTY_IRQ_SPURIOUS + bool "Create empty spurious interrupt handler" + depends on ARCH_SUPPORTS_EMPTY_IRQ_SPURIOUS + help + This option changes body of spurious interrupt handler. When enabled, + handler contains only an infinite while loop, when disabled, handler + contains the whole Zephyr fault handling procedure. + endmenu # Interrupt configuration config INIT_ARCH_HW_AT_BOOT @@ -633,12 +676,18 @@ config ARCH_HAS_NESTED_EXCEPTION_DETECTION config ARCH_SUPPORTS_COREDUMP bool +config ARCH_SUPPORTS_COREDUMP_THREADS + bool + config ARCH_SUPPORTS_ARCH_HW_INIT bool config ARCH_SUPPORTS_ROM_START bool +config ARCH_SUPPORTS_EMPTY_IRQ_SPURIOUS + bool + config ARCH_HAS_EXTRA_EXCEPTION_INFO bool @@ -668,6 +717,11 @@ config ARCH_SUPPORTS_MEM_MAPPED_STACKS help Select when the architecture supports memory mapped stacks. +config ARCH_HAS_THREAD_PRIV_STACK_SPACE_GET + bool + help + Select when the architecture implements arch_thread_priv_stack_space_get(). + # # Other architecture related options # @@ -733,6 +787,13 @@ config ARCH_HAS_DEMAND_PAGING This hidden configuration should be selected by the architecture if demand paging is supported. +config ARCH_HAS_DEMAND_MAPPING + bool + help + This hidden configuration should be selected by the architecture if + demand paging is supported and arch_mem_map() supports + K_MEM_MAP_UNPAGED. + config ARCH_HAS_RESERVED_PAGE_FRAMES bool help @@ -741,6 +802,13 @@ config ARCH_HAS_RESERVED_PAGE_FRAMES memory mappings. The architecture will need to implement arch_reserved_pages_update(). +config ARCH_HAS_DIRECTED_IPIS + bool + help + This hidden configuration should be selected by the architecture if + it has an implementation for arch_sched_directed_ipi() which allows + for IPIs to be directed to specific CPUs. + config CPU_HAS_DCACHE bool help @@ -776,7 +844,7 @@ config ARCH_MAPS_ALL_RAM virtual addresses elsewhere, this is limited to only management of the virtual address space. The kernel's page frame ontology will not consider this mapping at all; non-kernel pages will be considered free (unless marked - as reserved) and Z_PAGE_FRAME_MAPPED will not be set. + as reserved) and K_MEM_PAGE_FRAME_MAPPED will not be set. config DCLS bool "Processor is configured in DCLS mode" @@ -1041,9 +1109,28 @@ config TOOLCHAIN_HAS_BUILTIN_FFS help Hidden option to signal that toolchain has __builtin_ffs*(). -config ARCH_CPU_IDLE_CUSTOM - bool "Custom arch_cpu_idle implementation" - default n +config ARCH_HAS_CUSTOM_CPU_IDLE + bool help This options allows applications to override the default arch idle implementation with a custom one. + +config ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE + bool + help + This options allows applications to override the default arch idle implementation with + a custom one. + +config ARCH_HAS_CUSTOM_SWAP_TO_MAIN + bool + help + It's possible that an architecture port cannot use _Swap() to swap to + the _main() thread, but instead must do something custom. It must + enable this option in that case. + +config ARCH_HAS_CUSTOM_BUSY_WAIT + bool + help + It's possible that an architecture port cannot or does not want to use + the provided k_busy_wait(), but instead must do something custom. It must + enable this option in that case. diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index 8a3bd5b1b3c..a27b09659ac 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -18,6 +18,7 @@ config CPU_ARCEM config CPU_ARCHS bool select ATOMIC_OPERATIONS_BUILTIN + select BARRIER_OPERATIONS_BUILTIN help This option signifies the use of an ARC HS CPU @@ -373,7 +374,9 @@ config ARC_EXCEPTION_STACK_SIZE endmenu config ARC_EARLY_SOC_INIT - bool "Make early stage SoC-specific initialization" + bool "Make early stage SoC-specific initialization [DEPRECATED]" + select SOC_RESET_HOOK + select DEPRECATED help Call SoC per-core setup code on early stage initialization (before C runtime initialization). Setup code is called in form of diff --git a/arch/arc/core/cache.c b/arch/arc/core/cache.c index 8c2aab29fed..2688d5b03eb 100644 --- a/arch/arc/core/cache.c +++ b/arch/arc/core/cache.c @@ -227,4 +227,8 @@ static int init_dcache(void) return 0; } -SYS_INIT(init_dcache, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); + +void arch_cache_init(void) +{ + init_dcache(); +} diff --git a/arch/arc/core/cpu_idle.S b/arch/arc/core/cpu_idle.S index a5996a2ca4b..e0eaf4af2a1 100644 --- a/arch/arc/core/cpu_idle.S +++ b/arch/arc/core/cpu_idle.S @@ -26,6 +26,7 @@ SECTION_VAR(BSS, z_arc_cpu_sleep_mode) .align 4 .word 0 +#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_IDLE /* * @brief Put the CPU in low-power mode * @@ -48,7 +49,9 @@ SECTION_FUNC(TEXT, arch_cpu_idle) sleep r1 j_s [blink] nop +#endif +#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE /* * @brief Put the CPU in low-power mode, entered with IRQs locked * @@ -56,6 +59,7 @@ SECTION_FUNC(TEXT, arch_cpu_idle) * * void arch_cpu_atomic_idle(unsigned int key) */ + SECTION_FUNC(TEXT, arch_cpu_atomic_idle) #ifdef CONFIG_TRACING @@ -70,3 +74,4 @@ SECTION_FUNC(TEXT, arch_cpu_atomic_idle) sleep r1 j_s.d [blink] seti r0 +#endif diff --git a/arch/arc/core/fatal.c b/arch/arc/core/fatal.c index f193c0b09f1..512d1cc442c 100644 --- a/arch/arc/core/fatal.c +++ b/arch/arc/core/fatal.c @@ -23,7 +23,7 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); #ifdef CONFIG_EXCEPTION_DEBUG -static void dump_arc_esf(const z_arch_esf_t *esf) +static void dump_arc_esf(const struct arch_esf *esf) { ARC_EXCEPTION_DUMP(" r0: 0x%" PRIxPTR " r1: 0x%" PRIxPTR " r2: 0x%" PRIxPTR " r3: 0x%" PRIxPTR "", esf->r0, esf->r1, esf->r2, esf->r3); @@ -42,7 +42,7 @@ static void dump_arc_esf(const z_arch_esf_t *esf) } #endif -void z_arc_fatal_error(unsigned int reason, const z_arch_esf_t *esf) +void z_arc_fatal_error(unsigned int reason, const struct arch_esf *esf) { #ifdef CONFIG_EXCEPTION_DEBUG if (esf != NULL) { diff --git a/arch/arc/core/fault.c b/arch/arc/core/fault.c index 763ed7a2c73..6f9da3cd1e0 100644 --- a/arch/arc/core/fault.c +++ b/arch/arc/core/fault.c @@ -346,7 +346,7 @@ static void dump_exception_info(uint32_t vector, uint32_t cause, uint32_t parame * invokes the user provided routine k_sys_fatal_error_handler() which is * responsible for implementing the error handling policy. */ -void _Fault(z_arch_esf_t *esf, uint32_t old_sp) +void _Fault(struct arch_esf *esf, uint32_t old_sp) { uint32_t vector, cause, parameter; uint32_t exc_addr = z_arc_v2_aux_reg_read(_ARC_V2_EFA); diff --git a/arch/arc/core/irq_offload.c b/arch/arc/core/irq_offload.c index b658b8e353d..d1a3f900ca3 100644 --- a/arch/arc/core/irq_offload.c +++ b/arch/arc/core/irq_offload.c @@ -54,7 +54,7 @@ void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) } /* need to be executed on every core in the system */ -int arc_irq_offload_init(void) +void arch_irq_offload_init(void) { IRQ_CONNECT(IRQ_OFFLOAD_LINE, IRQ_OFFLOAD_PRIO, arc_irq_offload_handler, NULL, 0); @@ -64,8 +64,4 @@ int arc_irq_offload_init(void) * with generic irq_enable() but via z_arc_v2_irq_unit_int_enable(). */ z_arc_v2_irq_unit_int_enable(IRQ_OFFLOAD_LINE); - - return 0; } - -SYS_INIT(arc_irq_offload_init, POST_KERNEL, 0); diff --git a/arch/arc/core/isr_wrapper.S b/arch/arc/core/isr_wrapper.S index 3471e4d7349..4b486ed926d 100644 --- a/arch/arc/core/isr_wrapper.S +++ b/arch/arc/core/isr_wrapper.S @@ -26,7 +26,7 @@ GTEXT(_isr_wrapper) GTEXT(_isr_demux) #if defined(CONFIG_PM) -GTEXT(z_pm_save_idle_exit) +GTEXT(pm_system_resume) #endif /* @@ -253,7 +253,7 @@ rirq_path: st 0, [r1, _kernel_offset_to_idle] /* zero idle duration */ PUSHR blink - jl z_pm_save_idle_exit + jl pm_system_resume POPR blink _skip_pm_save_idle_exit: diff --git a/arch/arc/core/mpu/Kconfig b/arch/arc/core/mpu/Kconfig index 7078d88d534..2f288de25c7 100644 --- a/arch/arc/core/mpu/Kconfig +++ b/arch/arc/core/mpu/Kconfig @@ -35,5 +35,7 @@ config ARC_MPU select GEN_PRIV_STACKS if !(ARC_MPU_VER = 4 || ARC_MPU_VER = 8) select MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT if !(ARC_MPU_VER = 4 || ARC_MPU_VER = 8) select MPU_REQUIRES_NON_OVERLAPPING_REGIONS if (ARC_MPU_VER = 4 || ARC_MPU_VER = 8) + select ARCH_MEM_DOMAIN_SUPPORTS_ISOLATED_STACKS + select MEM_DOMAIN_ISOLATED_STACKS help Target has ARC MPU diff --git a/arch/arc/core/mpu/arc_mpu_common_internal.h b/arch/arc/core/mpu/arc_mpu_common_internal.h index a9ff5518b2f..15758ed15f6 100644 --- a/arch/arc/core/mpu/arc_mpu_common_internal.h +++ b/arch/arc/core/mpu/arc_mpu_common_internal.h @@ -238,7 +238,7 @@ int arc_core_mpu_buffer_validate(const void *addr, size_t size, int write) * This function provides the default configuration mechanism for the Memory * Protection Unit (MPU). */ -static int arc_mpu_init(void) +void arc_mpu_init(void) { uint32_t num_regions = get_num_regions(); @@ -246,7 +246,6 @@ static int arc_mpu_init(void) if (mpu_config.num_regions > num_regions) { __ASSERT(0, "Request to configure: %u regions (supported: %u)\n", mpu_config.num_regions, num_regions); - return -EINVAL; } /* Disable MPU */ @@ -278,10 +277,7 @@ static int arc_mpu_init(void) /* Enable MPU */ arc_core_mpu_enable(); - - return 0; } -SYS_INIT(arc_mpu_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); #endif /* ZEPHYR_ARCH_ARC_CORE_MPU_ARC_MPU_COMMON_INTERNAL_H_ */ diff --git a/arch/arc/core/mpu/arc_mpu_v2_internal.h b/arch/arc/core/mpu/arc_mpu_v2_internal.h index f59b1e9184c..a088df32d9b 100644 --- a/arch/arc/core/mpu/arc_mpu_v2_internal.h +++ b/arch/arc/core/mpu/arc_mpu_v2_internal.h @@ -118,7 +118,7 @@ static inline bool _is_enabled_region(uint32_t r_index) } /** - * This internal function check if the given buffer in in the region + * This internal function check if the given buffer is in the region */ static inline bool _is_in_region(uint32_t r_index, uint32_t start, uint32_t size) { diff --git a/arch/arc/core/mpu/arc_mpu_v4_internal.h b/arch/arc/core/mpu/arc_mpu_v4_internal.h index 3bf6fca6c43..1323f1ebda2 100644 --- a/arch/arc/core/mpu/arc_mpu_v4_internal.h +++ b/arch/arc/core/mpu/arc_mpu_v4_internal.h @@ -814,7 +814,7 @@ int arc_core_mpu_buffer_validate(const void *addr, size_t size, int write) * This function provides the default configuration mechanism for the Memory * Protection Unit (MPU). */ -static int arc_mpu_init(void) +void arc_mpu_init(void) { uint32_t num_regions; uint32_t i; @@ -826,7 +826,7 @@ static int arc_mpu_init(void) __ASSERT(0, "Request to configure: %u regions (supported: %u)\n", mpu_config.num_regions, num_regions); - return -EINVAL; + return; } static_regions_num = 0U; @@ -851,7 +851,7 @@ static int arc_mpu_init(void) MPU_DYNAMIC_REGION_AREAS_NUM) { LOG_ERR("not enough dynamic regions %d", dynamic_regions_num); - return -EINVAL; + return; } dyn_reg_info[dynamic_regions_num].index = i; @@ -886,10 +886,8 @@ static int arc_mpu_init(void) /* Enable MPU */ arc_core_mpu_enable(); - return 0; + return; } -SYS_INIT(arc_mpu_init, PRE_KERNEL_1, - CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); #endif /* ZEPHYR_ARCH_ARC_CORE_MPU_ARC_MPU_V4_INTERNAL_H_ */ diff --git a/arch/arc/core/mpu/arc_mpu_v6_internal.h b/arch/arc/core/mpu/arc_mpu_v6_internal.h index 1dbd50bdc84..3ee88d08320 100644 --- a/arch/arc/core/mpu/arc_mpu_v6_internal.h +++ b/arch/arc/core/mpu/arc_mpu_v6_internal.h @@ -156,7 +156,7 @@ static inline bool _is_enabled_region(uint32_t r_index) } /** - * This internal function check if the given buffer in in the region + * This internal function check if the given buffer is in the region */ static inline bool _is_in_region(uint32_t r_index, uint32_t start, uint32_t size) { diff --git a/arch/arc/core/prep_c.c b/arch/arc/core/prep_c.c index 0e4975cd3fc..bf3ab454a2c 100644 --- a/arch/arc/core/prep_c.c +++ b/arch/arc/core/prep_c.c @@ -23,6 +23,8 @@ #include #include #include +#include +#include /* XXX - keep for future use in full-featured cache APIs */ #if 0 @@ -113,6 +115,9 @@ static void dev_state_zero(void) #endif extern FUNC_NORETURN void z_cstart(void); +extern void arc_mpu_init(void); +extern void arc_secureshield_init(void); + /** * @brief Prepare to and run C code * @@ -121,6 +126,10 @@ extern FUNC_NORETURN void z_cstart(void); void z_prep_c(void) { +#if defined(CONFIG_SOC_PREP_HOOK) + soc_prep_hook(); +#endif + #ifdef CONFIG_ISA_ARCV3 arc_cluster_scm_enable(); #endif @@ -130,6 +139,15 @@ void z_prep_c(void) dev_state_zero(); #endif z_data_copy(); +#if CONFIG_ARCH_CACHE + arch_cache_init(); +#endif +#ifdef CONFIG_ARC_MPU + arc_mpu_init(); +#endif +#ifdef CONFIG_ARC_SECURE_FIRMWARE + arc_secureshield_init(); +#endif z_cstart(); CODE_UNREACHABLE; } diff --git a/arch/arc/core/reset.S b/arch/arc/core/reset.S index a2b038d387e..63fa6438ce4 100644 --- a/arch/arc/core/reset.S +++ b/arch/arc/core/reset.S @@ -16,8 +16,9 @@ #include #include #include -#ifdef CONFIG_ARC_EARLY_SOC_INIT - #include + +#if defined(CONFIG_SOC_RESET_HOOK) +GTEXT(soc_reset_hook) #endif GDATA(z_interrupt_stacks) @@ -112,8 +113,8 @@ done_icache_invalidate: done_dcache_invalidate: -#ifdef CONFIG_ARC_EARLY_SOC_INIT - soc_early_asm_init_percpu +#ifdef CONFIG_SOC_RESET_HOOK + bl soc_reset_hook #endif _dsp_extension_probe diff --git a/arch/arc/core/secureshield/arc_sjli.c b/arch/arc/core/secureshield/arc_sjli.c index 22deebc2718..e5b865445ee 100644 --- a/arch/arc/core/secureshield/arc_sjli.c +++ b/arch/arc/core/secureshield/arc_sjli.c @@ -48,7 +48,7 @@ static void sjli_table_init(void) /* * @brief initialization of secureshield related functions. */ -static int arc_secureshield_init(void) +void arc_secureshield_init(void) { sjli_table_init(); @@ -60,9 +60,4 @@ static int arc_secureshield_init(void) * */ __asm__ volatile("sflag 0x20"); - - return 0; } - -SYS_INIT(arc_secureshield_init, PRE_KERNEL_1, - CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); diff --git a/arch/arc/core/smp.c b/arch/arc/core/smp.c index 9f8ee38a4a1..e8463b7b53b 100644 --- a/arch/arc/core/smp.c +++ b/arch/arc/core/smp.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -130,21 +131,27 @@ static void sched_ipi_handler(const void *unused) z_sched_ipi(); } -/* arch implementation of sched_ipi */ -void arch_sched_ipi(void) +void arch_sched_directed_ipi(uint32_t cpu_bitmap) { - uint32_t i; + unsigned int i; + unsigned int num_cpus = arch_num_cpus(); - /* broadcast sched_ipi request to other cores + /* Send sched_ipi request to other cores * if the target is current core, hardware will ignore it */ - unsigned int num_cpus = arch_num_cpus(); for (i = 0U; i < num_cpus; i++) { - z_arc_connect_ici_generate(i); + if ((cpu_bitmap & BIT(i)) != 0) { + z_arc_connect_ici_generate(i); + } } } +void arch_sched_broadcast_ipi(void) +{ + arch_sched_directed_ipi(IPI_ALL_CPUS_MASK); +} + int arch_smp_init(void) { struct arc_connect_bcr bcr; @@ -188,5 +195,4 @@ int arch_smp_init(void) return 0; } -SYS_INIT(arch_smp_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); #endif diff --git a/arch/arc/include/arc_irq_offload.h b/arch/arc/include/arc_irq_offload.h index c38d0a24b68..243b4655652 100644 --- a/arch/arc/include/arc_irq_offload.h +++ b/arch/arc/include/arc_irq_offload.h @@ -9,11 +9,9 @@ #ifdef CONFIG_IRQ_OFFLOAD -int arc_irq_offload_init(const struct device *unused); - static inline void arc_irq_offload_init_smp(void) { - arc_irq_offload_init(NULL); + arch_irq_offload_init(); } #else diff --git a/arch/arc/include/kernel_arch_data.h b/arch/arc/include/kernel_arch_data.h index efe2bd7d1c6..b0dc733446b 100644 --- a/arch/arc/include/kernel_arch_data.h +++ b/arch/arc/include/kernel_arch_data.h @@ -36,7 +36,7 @@ extern "C" { #endif #ifdef CONFIG_ARC_HAS_SECURE -struct _irq_stack_frame { +struct arch_esf { #ifdef CONFIG_ARC_HAS_ZOL uintptr_t lp_end; uintptr_t lp_start; @@ -72,7 +72,7 @@ struct _irq_stack_frame { uintptr_t status32; }; #else -struct _irq_stack_frame { +struct arch_esf { uintptr_t r0; uintptr_t r1; uintptr_t r2; @@ -108,7 +108,7 @@ struct _irq_stack_frame { }; #endif -typedef struct _irq_stack_frame _isf_t; +typedef struct arch_esf _isf_t; diff --git a/arch/arc/include/kernel_arch_func.h b/arch/arc/include/kernel_arch_func.h index 1c46423cb4f..ca382a274f4 100644 --- a/arch/arc/include/kernel_arch_func.h +++ b/arch/arc/include/kernel_arch_func.h @@ -62,9 +62,7 @@ extern void z_arc_userspace_enter(k_thread_entry_t user_entry, void *p1, void *p2, void *p3, uint32_t stack, uint32_t size, struct k_thread *thread); -extern void z_arc_fatal_error(unsigned int reason, const z_arch_esf_t *esf); - -extern void arch_sched_ipi(void); +extern void z_arc_fatal_error(unsigned int reason, const struct arch_esf *esf); extern void z_arc_switch(void *switch_to, void **switched_from); diff --git a/arch/arc/include/offsets_short_arch.h b/arch/arc/include/offsets_short_arch.h index 5bf2c23fc3a..f461112ae79 100644 --- a/arch/arc/include/offsets_short_arch.h +++ b/arch/arc/include/offsets_short_arch.h @@ -7,7 +7,7 @@ #ifndef ZEPHYR_ARCH_ARC_INCLUDE_OFFSETS_SHORT_ARCH_H_ #define ZEPHYR_ARCH_ARC_INCLUDE_OFFSETS_SHORT_ARCH_H_ -#include +#include /* kernel */ diff --git a/arch/arm/CMakeLists.txt b/arch/arm/CMakeLists.txt index 5aa25f20396..48c78e8d88c 100644 --- a/arch/arm/CMakeLists.txt +++ b/arch/arm/CMakeLists.txt @@ -1,5 +1,9 @@ # SPDX-License-Identifier: Apache-2.0 -set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT elf32-littlearm) +if(CONFIG_BIG_ENDIAN) + set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT elf32-bigarm) +else() + set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT elf32-littlearm) +endif() add_subdirectory(core) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index bf68ec6faae..c28cf8d29f9 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -35,7 +35,7 @@ config ARM_CUSTOM_INTERRUPT_CONTROLLER assumes responsibility for handling the NVIC. config ROMSTART_RELOCATION_ROM - bool + bool "Relocate rom_start region" default n help Relocates the rom_start region containing the boot-vector data and @@ -66,7 +66,7 @@ config ROMSTART_RELOCATION_ROM if ROMSTART_RELOCATION_ROM config ROMSTART_REGION_ADDRESS - hex + hex "Base address of the rom_start region" default 0x00000000 help Start address of the rom_start region. @@ -85,7 +85,7 @@ if ROMSTART_RELOCATION_ROM $(dt_nodelabel_reg_addr_hex,ocram_s_sys) config ROMSTART_REGION_SIZE - hex + hex "Size of the rom_start region" default 1 help Size of the rom_start region in KB. diff --git a/arch/arm/core/Kconfig b/arch/arm/core/Kconfig index e446eb25c1d..2573ca2cac6 100644 --- a/arch/arm/core/Kconfig +++ b/arch/arm/core/Kconfig @@ -60,7 +60,7 @@ config CPU_AARCH32_CORTEX_A select USE_SWITCH_SUPPORTED # GDBSTUB has not yet been tested on Cortex M or R SoCs select ARCH_HAS_GDBSTUB - # GDB on ARM needs the etxra registers + # GDB on ARM needs the extra registers select EXTRA_EXCEPTION_INFO if GDBSTUB help This option signifies the use of a CPU of the Cortex-A family. @@ -166,11 +166,14 @@ config RUNTIME_NMI needed, enable this option and attach it via z_arm_nmi_set_handler(). config PLATFORM_SPECIFIC_INIT - bool "Platform (SOC) specific startup hook" + bool "Platform (SOC) specific startup hook [DEPRECATED]" + select DEPRECATED help The platform specific initialization code (z_arm_platform_init) is executed at the beginning of the startup code (__start). + This option is deprecated, use SOC_RESET_HOOK instead. + config FAULT_DUMP int "Fault dump level" default 2 diff --git a/arch/arm/core/cortex_a_r/Kconfig b/arch/arm/core/cortex_a_r/Kconfig index 3ec57cc408e..4095a277c61 100644 --- a/arch/arm/core/cortex_a_r/Kconfig +++ b/arch/arm/core/cortex_a_r/Kconfig @@ -131,6 +131,7 @@ config AARCH32_ARMV8_R bool select ATOMIC_OPERATIONS_BUILTIN select SCHED_IPI_SUPPORTED if SMP + select ARCH_HAS_DIRECTED_IPIS help This option signifies the use of an ARMv8-R AArch32 processor implementation. diff --git a/arch/arm/core/cortex_a_r/boot.h b/arch/arm/core/cortex_a_r/boot.h index 7eeba8b6ada..89306798ce4 100644 --- a/arch/arm/core/cortex_a_r/boot.h +++ b/arch/arm/core/cortex_a_r/boot.h @@ -26,5 +26,6 @@ extern void __start(void); #define BOOT_PARAM_UDF_SP_OFFSET 16 #define BOOT_PARAM_SVC_SP_OFFSET 20 #define BOOT_PARAM_SYS_SP_OFFSET 24 +#define BOOT_PARAM_VOTING_OFFSET 28 #endif /* _BOOT_H_ */ diff --git a/arch/arm/core/cortex_a_r/cache.c b/arch/arm/core/cortex_a_r/cache.c index 533666f0469..31cf27a08e6 100644 --- a/arch/arm/core/cortex_a_r/cache.c +++ b/arch/arm/core/cortex_a_r/cache.c @@ -217,3 +217,7 @@ int arch_icache_flush_and_invd_range(void *start_addr, size_t size) } #endif + +void arch_cache_init(void) +{ +} diff --git a/arch/arm/core/cortex_a_r/cpu_idle.S b/arch/arm/core/cortex_a_r/cpu_idle.S index 5c6ef3f12ed..044c0038239 100644 --- a/arch/arm/core/cortex_a_r/cpu_idle.S +++ b/arch/arm/core/cortex_a_r/cpu_idle.S @@ -49,6 +49,7 @@ _skip_\@: #endif /* CONFIG_ARM_ON_ENTER_CPU_IDLE_HOOK */ .endm +#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_IDLE SECTION_FUNC(TEXT, arch_cpu_idle) #ifdef CONFIG_TRACING push {r0, lr} @@ -68,6 +69,9 @@ SECTION_FUNC(TEXT, arch_cpu_idle) bx lr +#endif + +#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE SECTION_FUNC(TEXT, arch_cpu_atomic_idle) #ifdef CONFIG_TRACING push {r0, lr} @@ -93,3 +97,4 @@ SECTION_FUNC(TEXT, arch_cpu_atomic_idle) _irq_disabled: bx lr +#endif diff --git a/arch/arm/core/cortex_a_r/fault.c b/arch/arm/core/cortex_a_r/fault.c index a39efeb96e0..daf1d2345ca 100644 --- a/arch/arm/core/cortex_a_r/fault.c +++ b/arch/arm/core/cortex_a_r/fault.c @@ -147,8 +147,9 @@ bool z_arm_fault_undef_instruction_fp(void) * the FP was already enabled then this was an actual undefined * instruction. */ - if (__get_FPEXC() & FPEXC_EN) + if (__get_FPEXC() & FPEXC_EN) { return true; + } __set_FPEXC(FPEXC_EN); @@ -162,8 +163,9 @@ bool z_arm_fault_undef_instruction_fp(void) struct __fpu_sf *spill_esf = (struct __fpu_sf *)_current_cpu->fp_ctx; - if (spill_esf == NULL) + if (spill_esf == NULL) { return false; + } _current_cpu->fp_ctx = NULL; @@ -206,7 +208,7 @@ bool z_arm_fault_undef_instruction_fp(void) * * @return Returns true if the fault is fatal */ -bool z_arm_fault_undef_instruction(z_arch_esf_t *esf) +bool z_arm_fault_undef_instruction(struct arch_esf *esf) { #if defined(CONFIG_FPU_SHARING) /* @@ -243,7 +245,7 @@ bool z_arm_fault_undef_instruction(z_arch_esf_t *esf) * * @return Returns true if the fault is fatal */ -bool z_arm_fault_prefetch(z_arch_esf_t *esf) +bool z_arm_fault_prefetch(struct arch_esf *esf) { uint32_t reason = K_ERR_CPU_EXCEPTION; @@ -299,7 +301,7 @@ static const struct z_exc_handle exceptions[] = { * * @return true if error is recoverable, otherwise return false. */ -static bool memory_fault_recoverable(z_arch_esf_t *esf) +static bool memory_fault_recoverable(struct arch_esf *esf) { for (int i = 0; i < ARRAY_SIZE(exceptions); i++) { /* Mask out instruction mode */ @@ -321,7 +323,7 @@ static bool memory_fault_recoverable(z_arch_esf_t *esf) * * @return Returns true if the fault is fatal */ -bool z_arm_fault_data(z_arch_esf_t *esf) +bool z_arm_fault_data(struct arch_esf *esf) { uint32_t reason = K_ERR_CPU_EXCEPTION; diff --git a/arch/arm/core/cortex_a_r/irq_manage.c b/arch/arm/core/cortex_a_r/irq_manage.c index a381fad2a48..48c9ede3327 100644 --- a/arch/arm/core/cortex_a_r/irq_manage.c +++ b/arch/arm/core/cortex_a_r/irq_manage.c @@ -71,7 +71,7 @@ void z_arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags) } #endif /* !CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER */ -void z_arm_fatal_error(unsigned int reason, const z_arch_esf_t *esf); +void z_arm_fatal_error(unsigned int reason, const struct arch_esf *esf); /** * @@ -98,7 +98,7 @@ void _arch_isr_direct_pm(void) if (_kernel.idle) { _kernel.idle = 0; - z_pm_save_idle_exit(); + pm_system_resume(); } irq_unlock(key); diff --git a/arch/arm/core/cortex_a_r/isr_wrapper.S b/arch/arm/core/cortex_a_r/isr_wrapper.S index 0cd30e0a343..3dd678c4030 100644 --- a/arch/arm/core/cortex_a_r/isr_wrapper.S +++ b/arch/arm/core/cortex_a_r/isr_wrapper.S @@ -156,7 +156,7 @@ _vfp_not_enabled: * idle, this ensures that the calculation and programming of the * device for the next timer deadline is not interrupted. For * non-tickless idle, this ensures that the clearing of the kernel idle - * state is not interrupted. In each case, z_pm_save_idle_exit + * state is not interrupted. In each case, pm_system_resume * is called with interrupts disabled. */ @@ -170,7 +170,7 @@ _vfp_not_enabled: movs r1, #0 /* clear kernel idle state */ str r1, [r2, #_kernel_offset_to_idle] - bl z_pm_save_idle_exit + bl pm_system_resume _idle_state_cleared: #endif /* CONFIG_PM */ @@ -189,7 +189,7 @@ _idle_state_cleared: * * Note that interrupts are disabled up to this point on the ARM * architecture variants other than the Cortex-M. It is also important - * to note that that most interrupt controllers require that the nested + * to note that most interrupt controllers require that the nested * interrupts are handled after the active interrupt is acknowledged; * this is be done through the `get_active` interrupt controller * interface function. @@ -269,7 +269,7 @@ SECTION_FUNC(TEXT, _isr_wrapper) * idle, this ensures that the calculation and programming of the * device for the next timer deadline is not interrupted. For * non-tickless idle, this ensures that the clearing of the kernel idle - * state is not interrupted. In each case, z_pm_save_idle_exit + * state is not interrupted. In each case, pm_system_resume * is called with interrupts disabled. */ @@ -283,7 +283,7 @@ SECTION_FUNC(TEXT, _isr_wrapper) movs r1, #0 /* clear kernel idle state */ str r1, [r2, #_kernel_offset_to_idle] - bl z_pm_save_idle_exit + bl pm_system_resume _idle_state_cleared: #endif /* CONFIG_PM */ @@ -339,6 +339,15 @@ z_arm_cortex_ar_irq_done: str r0, [r2, #___cpu_t_nested_OFFSET] /* Do not context switch if exiting a nested interrupt */ cmp r0, #0 + /* Note that this function is only called from `z_arm_svc`, + * while handling irq_offload, with below modes set: + * ``` + * if (cpu interrupts are nested) + * mode=MODE_SYS + * else + * mode=MODE_IRQ + * ``` + */ bhi __EXIT_INT /* retrieve pointer to the current thread */ diff --git a/arch/arm/core/cortex_a_r/macro_priv.inc b/arch/arm/core/cortex_a_r/macro_priv.inc index e02433692f9..aafa87ca9b6 100644 --- a/arch/arm/core/cortex_a_r/macro_priv.inc +++ b/arch/arm/core/cortex_a_r/macro_priv.inc @@ -18,6 +18,27 @@ ubfx \rreg0, \rreg0, #0, #24 .endm +/* + * Get CPU logic id by looking up cpu_node_list + * returns + * reg0: MPID + * reg1: logic id (0 ~ CONFIG_MP_MAX_NUM_CPUS - 1) + * clobbers: reg0, reg1, reg2, reg3 + */ +.macro get_cpu_logic_id reg0, reg1, reg2, reg3 + get_cpu_id \reg0 + ldr \reg3, =cpu_node_list + mov \reg1, #0 +1: ldr \reg2, [\reg3, \reg1, lsl #2] + cmp \reg2, \reg0 + beq 2f + add \reg1, \reg1, #1 + cmp \reg1, #CONFIG_MP_MAX_NUM_CPUS + bne 1b + b . +2: +.endm + .macro get_cpu rreg0 /* * Get CPU pointer. @@ -33,8 +54,7 @@ */ srsdb sp!, #MODE_SYS cps #MODE_SYS - stmdb sp, {r0-r3, r12, lr}^ - sub sp, #24 + push {r0-r3, r12, lr} /* TODO: EXTRA_EXCEPTION_INFO */ mov r0, sp diff --git a/arch/arm/core/cortex_a_r/prep_c.c b/arch/arm/core/cortex_a_r/prep_c.c index e510d06ee95..74d0855a620 100644 --- a/arch/arm/core/cortex_a_r/prep_c.c +++ b/arch/arm/core/cortex_a_r/prep_c.c @@ -21,6 +21,8 @@ #include #include #include +#include +#include #if defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A) #include @@ -147,6 +149,9 @@ extern FUNC_NORETURN void z_cstart(void); */ void z_prep_c(void) { +#if defined(CONFIG_SOC_PREP_HOOK) + soc_prep_hook(); +#endif /* Initialize tpidruro with our struct _cpu instance address */ write_tpidruro((uintptr_t)&_kernel.cpus[0]); @@ -160,6 +165,9 @@ void z_prep_c(void) z_arm_init_stacks(); #endif z_arm_interrupt_init(); +#if CONFIG_ARCH_CACHE + arch_cache_init(); +#endif #ifdef CONFIG_ARM_MPU z_arm_mpu_init(); z_arm_configure_static_mpu_regions(); diff --git a/arch/arm/core/cortex_a_r/reset.S b/arch/arm/core/cortex_a_r/reset.S index 0b107fbf596..efb04d249ec 100644 --- a/arch/arm/core/cortex_a_r/reset.S +++ b/arch/arm/core/cortex_a_r/reset.S @@ -30,8 +30,8 @@ GDATA(z_arm_sys_stack) GDATA(z_arm_fiq_stack) GDATA(z_arm_abort_stack) GDATA(z_arm_undef_stack) -#if defined(CONFIG_PLATFORM_SPECIFIC_INIT) -GTEXT(z_arm_platform_init) +#if defined(CONFIG_SOC_RESET_HOOK) +GTEXT(soc_reset_hook) #endif /** @@ -200,23 +200,62 @@ EL1_Reset_Handler: #endif /* CONFIG_DCLS */ ldr r0, =arm_cpu_boot_params + #if CONFIG_MP_MAX_NUM_CPUS > 1 - get_cpu_id r1 + /* + * This code uses voting locks, like arch/arm64/core/reset.S, to determine primary CPU. + */ - ldrex r2, [r0, #BOOT_PARAM_MPID_OFFSET] - cmp r2, #-1 - bne 1f - strex r3, r1, [r0, #BOOT_PARAM_MPID_OFFSET] - cmp r3, #0 + /* + * Get the "logic" id defined by cpu_node_list statically for voting lock self-identify. + * It is worth noting that this is NOT the final logic id (arch_curr_cpu()->id) + */ + get_cpu_logic_id r1, r2, r3, r4 // r1: MPID, r2: logic id + + add r4, r0, #BOOT_PARAM_VOTING_OFFSET + + /* signal our desire to vote */ + mov r5, #1 + strb r5, [r4, r2] + ldr r3, [r0, #BOOT_PARAM_MPID_OFFSET] + cmn r3, #1 + beq 1f + + /* some core already won, release */ + mov r7, #0 + strb r7, [r4, r2] + b _secondary_core + + /* suggest current core then release */ +1: str r1, [r0, #BOOT_PARAM_MPID_OFFSET] + strb r7, [r4, r2] + dmb + + /* then wait until every core else is done voting */ + mov r5, #0 +2: ldrb r3, [r4, r5] + tst r3, #255 + /* wait */ + bne 2b + add r5, r5, #1 + cmp r5, #CONFIG_MP_MAX_NUM_CPUS + bne 2b + + /* check if current core won */ + dmb + ldr r3, [r0, #BOOT_PARAM_MPID_OFFSET] + cmp r3, r1 beq _primary_core + /* fallthrough secondary */ -1: - dmb ld + /* loop until our turn comes */ +_secondary_core: + dmb ldr r2, [r0, #BOOT_PARAM_MPID_OFFSET] cmp r1, r2 - bne 1b + bne _secondary_core - /* we can now move on */ + /* we can now load our stack pointer values and move on */ ldr r4, =arch_secondary_cpu_init ldr r5, [r0, #BOOT_PARAM_FIQ_SP_OFFSET] ldr r6, [r0, #BOOT_PARAM_IRQ_SP_OFFSET] @@ -266,9 +305,9 @@ _primary_core: msr CPSR_c, #(MODE_SYS | I_BIT | F_BIT) mov sp, r10 -#if defined(CONFIG_PLATFORM_SPECIFIC_INIT) +#if defined(CONFIG_SOC_RESET_HOOK) /* Execute platform-specific initialisation if applicable */ - bl z_arm_platform_init + bl soc_reset_hook #endif #if defined(CONFIG_WDOG_INIT) diff --git a/arch/arm/core/cortex_a_r/smp.c b/arch/arm/core/cortex_a_r/smp.c index 9e06730f913..6579cb4adde 100644 --- a/arch/arm/core/cortex_a_r/smp.c +++ b/arch/arm/core/cortex_a_r/smp.c @@ -7,6 +7,7 @@ #include #include #include +#include #include "boot.h" #include "zephyr/cache.h" #include "zephyr/kernel/thread_stack.h" @@ -50,6 +51,7 @@ struct boot_params { char *udf_sp; char *svc_sp; char *sys_sp; + uint8_t voting[CONFIG_MP_MAX_NUM_CPUS]; arch_cpustart_t fn; void *arg; int cpu_num; @@ -63,6 +65,7 @@ BUILD_ASSERT(offsetof(struct boot_params, abt_sp) == BOOT_PARAM_ABT_SP_OFFSET); BUILD_ASSERT(offsetof(struct boot_params, udf_sp) == BOOT_PARAM_UDF_SP_OFFSET); BUILD_ASSERT(offsetof(struct boot_params, svc_sp) == BOOT_PARAM_SVC_SP_OFFSET); BUILD_ASSERT(offsetof(struct boot_params, sys_sp) == BOOT_PARAM_SYS_SP_OFFSET); +BUILD_ASSERT(offsetof(struct boot_params, voting) == BOOT_PARAM_VOTING_OFFSET); volatile struct boot_params arm_cpu_boot_params = { .mpid = -1, @@ -74,7 +77,7 @@ volatile struct boot_params arm_cpu_boot_params = { .sys_sp = (char *)(z_arm_sys_stack + CONFIG_ARMV7_SYS_STACK_SIZE), }; -static const uint32_t cpu_node_list[] = { +const uint32_t cpu_node_list[] = { DT_FOREACH_CHILD_STATUS_OKAY_SEP(DT_PATH(cpus), DT_REG_ADDR, (,))}; /* cpu_map saves the maping of core id and mpid */ @@ -210,7 +213,7 @@ void arch_secondary_cpu_init(void) #ifdef CONFIG_SMP -static void broadcast_ipi(unsigned int ipi) +static void send_ipi(unsigned int ipi, uint32_t cpu_bitmap) { uint32_t mpidr = MPIDR_TO_CORE(GET_MPIDR()); @@ -220,6 +223,10 @@ static void broadcast_ipi(unsigned int ipi) unsigned int num_cpus = arch_num_cpus(); for (int i = 0; i < num_cpus; i++) { + if ((cpu_bitmap & BIT(i)) == 0) { + continue; + } + uint32_t target_mpidr = cpu_map[i]; uint8_t aff0; @@ -239,10 +246,14 @@ void sched_ipi_handler(const void *unused) z_sched_ipi(); } -/* arch implementation of sched_ipi */ -void arch_sched_ipi(void) +void arch_sched_broadcast_ipi(void) { - broadcast_ipi(SGI_SCHED_IPI); + send_ipi(SGI_SCHED_IPI, IPI_ALL_CPUS_MASK); +} + +void arch_sched_directed_ipi(uint32_t cpu_bitmap) +{ + send_ipi(SGI_SCHED_IPI, cpu_bitmap); } int arch_smp_init(void) @@ -259,6 +270,4 @@ int arch_smp_init(void) return 0; } -SYS_INIT(arch_smp_init, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); - #endif diff --git a/arch/arm/core/cortex_a_r/thread.c b/arch/arm/core/cortex_a_r/thread.c index d5ccab76877..b3bd91ce5c1 100644 --- a/arch/arm/core/cortex_a_r/thread.c +++ b/arch/arm/core/cortex_a_r/thread.c @@ -95,6 +95,10 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, iframe->a4 = (uint32_t)p3; iframe->xpsr = A_BIT | MODE_SYS; +#if defined(CONFIG_BIG_ENDIAN) + iframe->xpsr |= E_BIT; +#endif /* CONFIG_BIG_ENDIAN */ + #if defined(CONFIG_COMPILER_ISA_THUMB2) iframe->xpsr |= T_BIT; #endif /* CONFIG_COMPILER_ISA_THUMB2 */ diff --git a/arch/arm/core/cortex_a_r/vector_table.S b/arch/arm/core/cortex_a_r/vector_table.S index 8c1060e6122..e74b6a41c8d 100644 --- a/arch/arm/core/cortex_a_r/vector_table.S +++ b/arch/arm/core/cortex_a_r/vector_table.S @@ -41,6 +41,11 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table) GTEXT(z_arm_cortex_ar_exit_exc) SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_cortex_ar_exit_exc) + /* Note: + * This function is expected to be *always* called with + * processor mode set to MODE_SYS. + */ + /* decrement exception depth */ get_cpu r2 ldrb r1, [r2, #_cpu_offset_to_exc_depth] @@ -51,7 +56,6 @@ SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_cortex_ar_exit_exc) * Restore r0-r3, r12, lr, lr_und and spsr_und from the exception stack * and return to the current thread. */ - ldmia sp, {r0-r3, r12, lr}^ - add sp, #24 + pop {r0-r3, r12, lr} rfeia sp! #endif diff --git a/arch/arm/core/cortex_m/Kconfig b/arch/arm/core/cortex_m/Kconfig index e2a0fbb42da..c018574429a 100644 --- a/arch/arm/core/cortex_m/Kconfig +++ b/arch/arm/core/cortex_m/Kconfig @@ -73,6 +73,17 @@ config CPU_CORTEX_M55 help This option signifies the use of a Cortex-M55 CPU +config CPU_CORTEX_M85 + bool + select CPU_CORTEX_M + select ARMV8_1_M_MAINLINE + select ARMV8_M_SE if CPU_HAS_TEE + select ARMV7_M_ARMV8_M_FP if CPU_HAS_FPU + select CPU_HAS_DCACHE + select CPU_HAS_ICACHE + help + This option signifies the use of a Cortex-M85 CPU + config CPU_CORTEX_M7 bool select CPU_CORTEX_M @@ -319,7 +330,7 @@ config ZERO_LATENCY_IRQS config ZERO_LATENCY_LEVELS int "Number of interrupt priority levels reserved for zero latency" depends on ZERO_LATENCY_IRQS - range 1 255 + range 1 $(UINT8_MAX) help The amount of interrupt priority levels reserved for zero latency interrupts. Increase this value to reserve more than one priority diff --git a/arch/arm/core/cortex_m/cache.c b/arch/arm/core/cortex_m/cache.c index df746eb0474..a56996c8931 100644 --- a/arch/arm/core/cortex_m/cache.c +++ b/arch/arm/core/cortex_m/cache.c @@ -110,3 +110,7 @@ int arch_icache_flush_and_invd_range(void *start_addr, size_t size) { return -ENOTSUP; } + +void arch_cache_init(void) +{ +} diff --git a/arch/arm/core/cortex_m/coredump.c b/arch/arm/core/cortex_m/coredump.c index 2b4a86a1bb9..c688c91d981 100644 --- a/arch/arm/core/cortex_m/coredump.c +++ b/arch/arm/core/cortex_m/coredump.c @@ -41,7 +41,7 @@ struct arm_arch_block { */ static struct arm_arch_block arch_blk; -void arch_coredump_info_dump(const z_arch_esf_t *esf) +void arch_coredump_info_dump(const struct arch_esf *esf) { struct coredump_arch_hdr_t hdr = { .id = COREDUMP_ARCH_HDR_ID, diff --git a/arch/arm/core/cortex_m/cpu_idle.c b/arch/arm/core/cortex_m/cpu_idle.c index 4df091fbbd6..5f373a88c9d 100644 --- a/arch/arm/core/cortex_m/cpu_idle.c +++ b/arch/arm/core/cortex_m/cpu_idle.c @@ -53,6 +53,7 @@ void z_arm_cpu_idle_init(void) } while (false) #endif +#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_IDLE void arch_cpu_idle(void) { #if defined(CONFIG_TRACING) @@ -96,7 +97,9 @@ void arch_cpu_idle(void) __enable_irq(); __ISB(); } +#endif +#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE void arch_cpu_atomic_idle(unsigned int key) { #if defined(CONFIG_TRACING) @@ -135,3 +138,4 @@ void arch_cpu_atomic_idle(unsigned int key) __enable_irq(); #endif } +#endif diff --git a/arch/arm/core/cortex_m/debug.c b/arch/arm/core/cortex_m/debug.c index 8d83cd07f2f..61fb6814535 100644 --- a/arch/arm/core/cortex_m/debug.c +++ b/arch/arm/core/cortex_m/debug.c @@ -58,7 +58,7 @@ BUILD_ASSERT(!(CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE & (CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE - 1)), "the size of the partition must be power of 2"); -static int z_arm_debug_enable_null_pointer_detection(void) +int z_arm_debug_enable_null_pointer_detection(void) { z_arm_dwt_init(); @@ -118,7 +118,4 @@ static int z_arm_debug_enable_null_pointer_detection(void) return 0; } -SYS_INIT(z_arm_debug_enable_null_pointer_detection, PRE_KERNEL_1, - CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); - #endif /* CONFIG_NULL_POINTER_EXCEPTION_DETECTION_DWT */ diff --git a/arch/arm/core/cortex_m/fault.c b/arch/arm/core/cortex_m/fault.c index 5090381fa31..4cc01f87129 100644 --- a/arch/arm/core/cortex_m/fault.c +++ b/arch/arm/core/cortex_m/fault.c @@ -146,7 +146,7 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); */ #if (CONFIG_FAULT_DUMP == 1) -static void fault_show(const z_arch_esf_t *esf, int fault) +static void fault_show(const struct arch_esf *esf, int fault) { PR_EXC("Fault! EXC #%d", fault); @@ -165,7 +165,7 @@ static void fault_show(const z_arch_esf_t *esf, int fault) * * For Dump level 0, no information needs to be generated. */ -static void fault_show(const z_arch_esf_t *esf, int fault) +static void fault_show(const struct arch_esf *esf, int fault) { (void)esf; (void)fault; @@ -185,7 +185,7 @@ static const struct z_exc_handle exceptions[] = { * * @return true if error is recoverable, otherwise return false. */ -static bool memory_fault_recoverable(z_arch_esf_t *esf, bool synchronous) +static bool memory_fault_recoverable(struct arch_esf *esf, bool synchronous) { #ifdef CONFIG_USERSPACE for (int i = 0; i < ARRAY_SIZE(exceptions); i++) { @@ -228,7 +228,7 @@ uint32_t z_check_thread_stack_fail(const uint32_t fault_addr, * * @return error code to identify the fatal error reason */ -static uint32_t mem_manage_fault(z_arch_esf_t *esf, int from_hard_fault, +static uint32_t mem_manage_fault(struct arch_esf *esf, int from_hard_fault, bool *recoverable) { uint32_t reason = K_ERR_ARM_MEM_GENERIC; @@ -387,7 +387,7 @@ static uint32_t mem_manage_fault(z_arch_esf_t *esf, int from_hard_fault, * @return error code to identify the fatal error reason. * */ -static int bus_fault(z_arch_esf_t *esf, int from_hard_fault, bool *recoverable) +static int bus_fault(struct arch_esf *esf, int from_hard_fault, bool *recoverable) { uint32_t reason = K_ERR_ARM_BUS_GENERIC; @@ -549,7 +549,7 @@ static int bus_fault(z_arch_esf_t *esf, int from_hard_fault, bool *recoverable) * * @return error code to identify the fatal error reason */ -static uint32_t usage_fault(const z_arch_esf_t *esf) +static uint32_t usage_fault(const struct arch_esf *esf) { uint32_t reason = K_ERR_ARM_USAGE_GENERIC; @@ -612,7 +612,7 @@ static uint32_t usage_fault(const z_arch_esf_t *esf) * * @return error code to identify the fatal error reason */ -static uint32_t secure_fault(const z_arch_esf_t *esf) +static uint32_t secure_fault(const struct arch_esf *esf) { uint32_t reason = K_ERR_ARM_SECURE_GENERIC; @@ -661,7 +661,7 @@ static uint32_t secure_fault(const z_arch_esf_t *esf) * See z_arm_fault_dump() for example. * */ -static void debug_monitor(z_arch_esf_t *esf, bool *recoverable) +static void debug_monitor(struct arch_esf *esf, bool *recoverable) { *recoverable = false; @@ -687,7 +687,7 @@ static void debug_monitor(z_arch_esf_t *esf, bool *recoverable) #error Unknown ARM architecture #endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */ -static inline bool z_arm_is_synchronous_svc(z_arch_esf_t *esf) +static inline bool z_arm_is_synchronous_svc(struct arch_esf *esf) { uint16_t *ret_addr = (uint16_t *)esf->basic.pc; /* SVC is a 16-bit instruction. On a synchronous SVC @@ -762,7 +762,7 @@ static inline bool z_arm_is_pc_valid(uintptr_t pc) * * @return error code to identify the fatal error reason */ -static uint32_t hard_fault(z_arch_esf_t *esf, bool *recoverable) +static uint32_t hard_fault(struct arch_esf *esf, bool *recoverable) { uint32_t reason = K_ERR_CPU_EXCEPTION; @@ -829,7 +829,7 @@ static uint32_t hard_fault(z_arch_esf_t *esf, bool *recoverable) * See z_arm_fault_dump() for example. * */ -static void reserved_exception(const z_arch_esf_t *esf, int fault) +static void reserved_exception(const struct arch_esf *esf, int fault) { ARG_UNUSED(esf); @@ -839,7 +839,7 @@ static void reserved_exception(const z_arch_esf_t *esf, int fault) } /* Handler function for ARM fault conditions. */ -static uint32_t fault_handle(z_arch_esf_t *esf, int fault, bool *recoverable) +static uint32_t fault_handle(struct arch_esf *esf, int fault, bool *recoverable) { uint32_t reason = K_ERR_CPU_EXCEPTION; @@ -893,7 +893,7 @@ static uint32_t fault_handle(z_arch_esf_t *esf, int fault, bool *recoverable) * * @param secure_esf Pointer to the secure stack frame. */ -static void secure_stack_dump(const z_arch_esf_t *secure_esf) +static void secure_stack_dump(const struct arch_esf *secure_esf) { /* * In case a Non-Secure exception interrupted the Secure @@ -918,7 +918,7 @@ static void secure_stack_dump(const z_arch_esf_t *secure_esf) * Non-Secure exception entry. */ top_of_sec_stack += ADDITIONAL_STATE_CONTEXT_WORDS; - secure_esf = (const z_arch_esf_t *)top_of_sec_stack; + secure_esf = (const struct arch_esf *)top_of_sec_stack; sec_ret_addr = secure_esf->basic.pc; } else { /* Exception during Non-Secure function call. @@ -947,11 +947,11 @@ static void secure_stack_dump(const z_arch_esf_t *secure_esf) * * @return ESF pointer on success, otherwise return NULL */ -static inline z_arch_esf_t *get_esf(uint32_t msp, uint32_t psp, uint32_t exc_return, +static inline struct arch_esf *get_esf(uint32_t msp, uint32_t psp, uint32_t exc_return, bool *nested_exc) { bool alternative_state_exc = false; - z_arch_esf_t *ptr_esf = NULL; + struct arch_esf *ptr_esf = NULL; *nested_exc = false; @@ -979,14 +979,14 @@ static inline z_arch_esf_t *get_esf(uint32_t msp, uint32_t psp, uint32_t exc_ret alternative_state_exc = true; /* Dump the Secure stack before handling the actual fault. */ - z_arch_esf_t *secure_esf; + struct arch_esf *secure_esf; if (exc_return & EXC_RETURN_SPSEL_PROCESS) { /* Secure stack pointed by PSP */ - secure_esf = (z_arch_esf_t *)psp; + secure_esf = (struct arch_esf *)psp; } else { /* Secure stack pointed by MSP */ - secure_esf = (z_arch_esf_t *)msp; + secure_esf = (struct arch_esf *)msp; *nested_exc = true; } @@ -997,9 +997,9 @@ static inline z_arch_esf_t *get_esf(uint32_t msp, uint32_t psp, uint32_t exc_ret * and supply it to the fault handing function. */ if (exc_return & EXC_RETURN_MODE_THREAD) { - ptr_esf = (z_arch_esf_t *)__TZ_get_PSP_NS(); + ptr_esf = (struct arch_esf *)__TZ_get_PSP_NS(); } else { - ptr_esf = (z_arch_esf_t *)__TZ_get_MSP_NS(); + ptr_esf = (struct arch_esf *)__TZ_get_MSP_NS(); } } #elif defined(CONFIG_ARM_NONSECURE_FIRMWARE) @@ -1024,10 +1024,10 @@ static inline z_arch_esf_t *get_esf(uint32_t msp, uint32_t psp, uint32_t exc_ret if (exc_return & EXC_RETURN_SPSEL_PROCESS) { /* Non-Secure stack frame on PSP */ - ptr_esf = (z_arch_esf_t *)psp; + ptr_esf = (struct arch_esf *)psp; } else { /* Non-Secure stack frame on MSP */ - ptr_esf = (z_arch_esf_t *)msp; + ptr_esf = (struct arch_esf *)msp; } } else { /* Exception entry occurred in Non-Secure stack. */ @@ -1046,11 +1046,11 @@ static inline z_arch_esf_t *get_esf(uint32_t msp, uint32_t psp, uint32_t exc_ret if (!alternative_state_exc) { if (exc_return & EXC_RETURN_MODE_THREAD) { /* Returning to thread mode */ - ptr_esf = (z_arch_esf_t *)psp; + ptr_esf = (struct arch_esf *)psp; } else { /* Returning to handler mode */ - ptr_esf = (z_arch_esf_t *)msp; + ptr_esf = (struct arch_esf *)msp; *nested_exc = true; } } @@ -1095,12 +1095,12 @@ void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return, uint32_t reason = K_ERR_CPU_EXCEPTION; int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk; bool recoverable, nested_exc; - z_arch_esf_t *esf; + struct arch_esf *esf; /* Create a stack-ed copy of the ESF to be used during * the fault handling process. */ - z_arch_esf_t esf_copy; + struct arch_esf esf_copy; /* Force unlock interrupts */ arch_irq_unlock(0); @@ -1123,13 +1123,13 @@ void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return, /* Copy ESF */ #if !defined(CONFIG_EXTRA_EXCEPTION_INFO) - memcpy(&esf_copy, esf, sizeof(z_arch_esf_t)); + memcpy(&esf_copy, esf, sizeof(struct arch_esf)); ARG_UNUSED(callee_regs); #else /* the extra exception info is not present in the original esf * so we only copy the fields before those. */ - memcpy(&esf_copy, esf, offsetof(z_arch_esf_t, extra_info)); + memcpy(&esf_copy, esf, offsetof(struct arch_esf, extra_info)); esf_copy.extra_info = (struct __extra_esf_info) { .callee = callee_regs, .exc_return = exc_return, @@ -1192,5 +1192,7 @@ void z_arm_fault_init(void) #endif /* CONFIG_BUILTIN_STACK_GUARD */ #ifdef CONFIG_TRAP_UNALIGNED_ACCESS SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#else + SCB->CCR &= ~SCB_CCR_UNALIGN_TRP_Msk; #endif /* CONFIG_TRAP_UNALIGNED_ACCESS */ } diff --git a/arch/arm/core/cortex_m/irq_manage.c b/arch/arm/core/cortex_m/irq_manage.c index 3940d5246d4..cc62386e8ac 100644 --- a/arch/arm/core/cortex_m/irq_manage.c +++ b/arch/arm/core/cortex_m/irq_manage.c @@ -94,7 +94,7 @@ void z_arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags) #endif /* !defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER) */ -void z_arm_fatal_error(unsigned int reason, const z_arch_esf_t *esf); +void z_arm_fatal_error(unsigned int reason, const struct arch_esf *esf); /** * @@ -122,7 +122,7 @@ void _arch_isr_direct_pm(void) #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) /* Lock all interrupts. irq_lock() will on this CPU only disable those * lower than BASEPRI, which is not what we want. See comments in - * arch/arm/core/isr_wrapper.S + * arch/arm/core/cortex_m/isr_wrapper.c */ __asm__ volatile("cpsid i" : : : "memory"); #else @@ -131,7 +131,7 @@ void _arch_isr_direct_pm(void) if (_kernel.idle) { _kernel.idle = 0; - z_pm_save_idle_exit(); + pm_system_resume(); } #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) diff --git a/arch/arm/core/cortex_m/isr_wrapper.c b/arch/arm/core/cortex_m/isr_wrapper.c index 6e6016508c6..46aac160c3b 100644 --- a/arch/arm/core/cortex_m/isr_wrapper.c +++ b/arch/arm/core/cortex_m/isr_wrapper.c @@ -42,7 +42,7 @@ void _isr_wrapper(void) * idle, this ensures that the calculation and programming of the * device for the next timer deadline is not interrupted. For * non-tickless idle, this ensures that the clearing of the kernel idle - * state is not interrupted. In each case, z_pm_save_idle_exit + * state is not interrupted. In each case, pm_system_resume * is called with interrupts disabled. */ @@ -59,7 +59,7 @@ void _isr_wrapper(void) if (_kernel.idle != 0) { /* clear kernel idle state */ _kernel.idle = 0; - z_pm_save_idle_exit(); + pm_system_resume(); } /* re-enable interrupts */ __enable_irq(); diff --git a/arch/arm/core/cortex_m/pm_s2ram.S b/arch/arm/core/cortex_m/pm_s2ram.S index 1e5bca04fe2..f9c82b4069b 100644 --- a/arch/arm/core/cortex_m/pm_s2ram.S +++ b/arch/arm/core/cortex_m/pm_s2ram.S @@ -27,6 +27,11 @@ SECTION_FUNC(TEXT, arch_pm_s2ram_suspend) * r0: address of the system_off function */ push {r4-r12, lr} + + /* Move system_off to protected register. */ + mov r4, r0 + + /* Store CPU context */ ldr r1, =_cpu_context mrs r2, msp @@ -71,7 +76,7 @@ SECTION_FUNC(TEXT, arch_pm_s2ram_suspend) * Call the system_off function passed as parameter. This should never * return. */ - blx r0 + blx r4 /* * The system_off function returns here only when the powering off was @@ -81,9 +86,10 @@ SECTION_FUNC(TEXT, arch_pm_s2ram_suspend) /* * Reset the marking of suspend to RAM, return is ignored. */ - push {r0} bl pm_s2ram_mark_check_and_clear - pop {r0} + + /* Move system_off back to r0 as return value */ + mov r0, r4 pop {r4-r12, lr} bx lr @@ -93,11 +99,14 @@ GTEXT(arch_pm_s2ram_resume) SECTION_FUNC(TEXT, arch_pm_s2ram_resume) /* * Check if reset occurred after suspending to RAM. + * Store LR to ensure we can continue boot when we are not suspended + * to RAM. In addition to LR, R0 is pushed too, to ensure "SP mod 8 = 0", + * as stated by ARM rule 6.2.1.2 for AAPCS32. */ - push {lr} + push {r0, lr} bl pm_s2ram_mark_check_and_clear cmp r0, #0x1 - pop {lr} + pop {r0, lr} beq resume bx lr diff --git a/arch/arm/core/cortex_m/prep_c.c b/arch/arm/core/cortex_m/prep_c.c index 422d45b57e1..10f78c44a25 100644 --- a/arch/arm/core/cortex_m/prep_c.c +++ b/arch/arm/core/cortex_m/prep_c.c @@ -20,6 +20,8 @@ #include #include #include +#include +#include #if defined(__GNUC__) /* @@ -181,6 +183,10 @@ extern FUNC_NORETURN void z_cstart(void); */ void z_prep_c(void) { +#if defined(CONFIG_SOC_PREP_HOOK) + soc_prep_hook(); +#endif + relocate_vector_table(); #if defined(CONFIG_CPU_HAS_FPU) z_arm_floating_point_init(); @@ -193,6 +199,13 @@ void z_prep_c(void) #else z_arm_interrupt_init(); #endif /* CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER */ +#if CONFIG_ARCH_CACHE + arch_cache_init(); +#endif + +#ifdef CONFIG_NULL_POINTER_EXCEPTION_DETECTION_DWT + z_arm_debug_enable_null_pointer_detection(); +#endif z_cstart(); CODE_UNREACHABLE; } diff --git a/arch/arm/core/cortex_m/reset.S b/arch/arm/core/cortex_m/reset.S index 332f1a60c10..bc75ccfceaa 100644 --- a/arch/arm/core/cortex_m/reset.S +++ b/arch/arm/core/cortex_m/reset.S @@ -24,8 +24,8 @@ GDATA(z_interrupt_stacks) #if defined(CONFIG_DEBUG_THREAD_INFO) GDATA(z_sys_post_kernel) #endif -#if defined(CONFIG_PLATFORM_SPECIFIC_INIT) -GTEXT(z_arm_platform_init) +#if defined(CONFIG_SOC_RESET_HOOK) +GTEXT(soc_reset_hook) #endif #if defined(CONFIG_INIT_ARCH_HW_AT_BOOT) GTEXT(z_arm_init_arch_hw_at_boot) @@ -93,8 +93,8 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start) bl arch_pm_s2ram_resume #endif /* CONFIG_PM_S2RAM */ -#if defined(CONFIG_PLATFORM_SPECIFIC_INIT) - bl z_arm_platform_init +#if defined(CONFIG_SOC_RESET_HOOK) + bl soc_reset_hook #endif #if defined(CONFIG_INIT_ARCH_HW_AT_BOOT) diff --git a/arch/arm/core/cortex_m/swap.c b/arch/arm/core/cortex_m/swap.c index b60f6acd675..027fb47a01f 100644 --- a/arch/arm/core/cortex_m/swap.c +++ b/arch/arm/core/cortex_m/swap.c @@ -96,11 +96,15 @@ uintptr_t z_arm_pendsv_c(uintptr_t exc_ret) /* restore mode */ IF_ENABLED(CONFIG_USERSPACE, ({ - CONTROL_Type ctrl = {.w = __get_CONTROL()}; - /* exit privileged state when returing to thread mode. */ - ctrl.b.nPRIV = 0; - __set_CONTROL(ctrl.w | current->arch.mode); - })); + CONTROL_Type ctrl = {.w = __get_CONTROL()}; + /* exit privileged state when returning to thread mode. */ + ctrl.b.nPRIV = 0; + /* __set_CONTROL inserts an ISB which is may not be necessary here + * (stack pointer may not be touched), but it's recommended to avoid + * executing pre-fetched instructions with the previous privilege. + */ + __set_CONTROL(ctrl.w | current->arch.mode); + })); return exc_ret; } diff --git a/arch/arm/core/cortex_m/thread.c b/arch/arm/core/cortex_m/thread.c index e9ab7292ab5..fa500032d3c 100644 --- a/arch/arm/core/cortex_m/thread.c +++ b/arch/arm/core/cortex_m/thread.c @@ -588,7 +588,7 @@ void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr, "bx r4\n" /* We don’t intend to return, so there is no need to link. */ : "+r" (_main) : "r" (stack_ptr) - : "r0", "r1", "r2", "r3", "r4"); + : "r0", "r1", "r2", "r3", "r4", "ip", "lr"); CODE_UNREACHABLE; } @@ -659,7 +659,7 @@ FUNC_NORETURN void z_arm_switch_to_main_no_multithreading( #ifdef CONFIG_BUILTIN_STACK_GUARD , [_psplim]"r" (psplim) #endif - : "r0", "r1", "r2", "r3" + : "r0", "r1", "r2", "ip", "lr" ); CODE_UNREACHABLE; /* LCOV_EXCL_LINE */ diff --git a/arch/arm/core/elf.c b/arch/arm/core/elf.c index 108c72728d5..5fdc5471a6b 100644 --- a/arch/arm/core/elf.c +++ b/arch/arm/core/elf.c @@ -12,6 +12,34 @@ LOG_MODULE_REGISTER(elf, CONFIG_LLEXT_LOG_LEVEL); +#define R_ARM_NONE 0 +#define R_ARM_PC24 1 +#define R_ARM_ABS32 2 +#define R_ARM_REL32 3 +#define R_ARM_COPY 20 +#define R_ARM_GLOB_DAT 21 +#define R_ARM_JUMP_SLOT 22 +#define R_ARM_RELATIVE 23 +#define R_ARM_CALL 28 +#define R_ARM_JUMP24 29 +#define R_ARM_TARGET1 38 +#define R_ARM_V4BX 40 +#define R_ARM_PREL31 42 +#define R_ARM_MOVW_ABS_NC 43 +#define R_ARM_MOVT_ABS 44 +#define R_ARM_MOVW_PREL_NC 45 +#define R_ARM_MOVT_PREL 46 +#define R_ARM_ALU_PC_G0_NC 57 +#define R_ARM_ALU_PC_G1_NC 59 +#define R_ARM_LDR_PC_G2 63 + +#define R_ARM_THM_CALL 10 +#define R_ARM_THM_JUMP24 30 +#define R_ARM_THM_MOVW_ABS_NC 47 +#define R_ARM_THM_MOVT_ABS 48 +#define R_ARM_THM_MOVW_PREL_NC 49 +#define R_ARM_THM_MOVT_PREL 50 + #define OPCODE2ARMMEM(x) ((uint32_t)(x)) #define OPCODE2THM16MEM(x) ((uint16_t)(x)) #define MEM2ARMOPCODE(x) OPCODE2ARMMEM(x) diff --git a/arch/arm/core/fatal.c b/arch/arm/core/fatal.c index 4364d48d45d..4532e238f05 100644 --- a/arch/arm/core/fatal.c +++ b/arch/arm/core/fatal.c @@ -18,7 +18,7 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); #ifdef CONFIG_EXCEPTION_DEBUG -static void esf_dump(const z_arch_esf_t *esf) +static void esf_dump(const struct arch_esf *esf) { LOG_ERR("r0/a1: 0x%08x r1/a2: 0x%08x r2/a3: 0x%08x", esf->basic.a1, esf->basic.a2, esf->basic.a3); @@ -66,7 +66,7 @@ static void esf_dump(const z_arch_esf_t *esf) } #endif /* CONFIG_EXCEPTION_DEBUG */ -void z_arm_fatal_error(unsigned int reason, const z_arch_esf_t *esf) +void z_arm_fatal_error(unsigned int reason, const struct arch_esf *esf) { #ifdef CONFIG_EXCEPTION_DEBUG if (esf != NULL) { @@ -102,7 +102,7 @@ void z_arm_fatal_error(unsigned int reason, const z_arch_esf_t *esf) * @param esf exception frame * @param callee_regs Callee-saved registers (R4-R11) */ -void z_do_kernel_oops(const z_arch_esf_t *esf, _callee_saved_t *callee_regs) +void z_do_kernel_oops(const struct arch_esf *esf, _callee_saved_t *callee_regs) { #if !(defined(CONFIG_EXTRA_EXCEPTION_INFO) && defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)) ARG_UNUSED(callee_regs); @@ -130,9 +130,9 @@ void z_do_kernel_oops(const z_arch_esf_t *esf, _callee_saved_t *callee_regs) #if !defined(CONFIG_EXTRA_EXCEPTION_INFO) z_arm_fatal_error(reason, esf); #else - z_arch_esf_t esf_copy; + struct arch_esf esf_copy; - memcpy(&esf_copy, esf, offsetof(z_arch_esf_t, extra_info)); + memcpy(&esf_copy, esf, offsetof(struct arch_esf, extra_info)); #if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) /* extra exception info is collected in callee_reg param * on CONFIG_ARMV7_M_ARMV8_M_MAINLINE @@ -156,7 +156,7 @@ void z_do_kernel_oops(const z_arch_esf_t *esf, _callee_saved_t *callee_regs) FUNC_NORETURN void arch_syscall_oops(void *ssf_ptr) { uint32_t *ssf_contents = ssf_ptr; - z_arch_esf_t oops_esf = { 0 }; + struct arch_esf oops_esf = { 0 }; /* TODO: Copy the rest of the register set out of ssf_ptr */ oops_esf.basic.pc = ssf_contents[3]; diff --git a/arch/arm/core/gdbstub.c b/arch/arm/core/gdbstub.c index 5386cfa619f..60d16b78c31 100644 --- a/arch/arm/core/gdbstub.c +++ b/arch/arm/core/gdbstub.c @@ -42,7 +42,7 @@ static int is_bkpt(unsigned int exc_cause) } /* Wrapper function to save and restore execution c */ -void z_gdb_entry(z_arch_esf_t *esf, unsigned int exc_cause) +void z_gdb_entry(struct arch_esf *esf, unsigned int exc_cause) { /* Disable the hardware breakpoint in case it was set */ __asm__ volatile("mcr p14, 0, %0, c0, c0, 5" ::"r"(0x0) :); diff --git a/arch/arm/core/irq_offload.c b/arch/arm/core/irq_offload.c index 5dc1feccf7a..65349de331b 100644 --- a/arch/arm/core/irq_offload.c +++ b/arch/arm/core/irq_offload.c @@ -42,3 +42,7 @@ void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) offload_routine = NULL; k_sched_unlock(); } + +void arch_irq_offload_init(void) +{ +} diff --git a/arch/arm/core/mpu/arm_mpu.c b/arch/arm/core/mpu/arm_mpu.c index fe5d86c822d..3f9cf095754 100644 --- a/arch/arm/core/mpu/arm_mpu.c +++ b/arch/arm/core/mpu/arm_mpu.c @@ -54,6 +54,7 @@ static uint8_t static_regions_num; #elif defined(CONFIG_CPU_CORTEX_M23) || \ defined(CONFIG_CPU_CORTEX_M33) || \ defined(CONFIG_CPU_CORTEX_M55) || \ + defined(CONFIG_CPU_CORTEX_M85) || \ defined(CONFIG_AARCH32_ARMV8_R) #include "arm_mpu_v8_internal.h" #else diff --git a/arch/arm/core/mpu/arm_mpu_v8_internal.h b/arch/arm/core/mpu/arm_mpu_v8_internal.h index 66a00a452a7..51ab093d17c 100644 --- a/arch/arm/core/mpu/arm_mpu_v8_internal.h +++ b/arch/arm/core/mpu/arm_mpu_v8_internal.h @@ -31,7 +31,7 @@ struct dynamic_region_info { */ static struct dynamic_region_info dyn_reg_info[MPU_DYNAMIC_REGION_AREAS_NUM]; #if defined(CONFIG_CPU_CORTEX_M23) || defined(CONFIG_CPU_CORTEX_M33) || \ - defined(CONFIG_CPU_CORTEX_M55) + defined(CONFIG_CPU_CORTEX_M55) || defined(CONFIG_CPU_CORTEX_M85) static inline void mpu_set_mair0(uint32_t mair0) { MPU->MAIR0 = mair0; diff --git a/arch/arm/include/cortex_a_r/exception.h b/arch/arm/include/cortex_a_r/exception.h index 7519016176c..6daa9c106ee 100644 --- a/arch/arm/include/cortex_a_r/exception.h +++ b/arch/arm/include/cortex_a_r/exception.h @@ -38,7 +38,7 @@ static ALWAYS_INLINE bool arch_is_in_isr(void) return (arch_curr_cpu()->nested != 0U); } -static ALWAYS_INLINE bool arch_is_in_nested_exception(const z_arch_esf_t *esf) +static ALWAYS_INLINE bool arch_is_in_nested_exception(const struct arch_esf *esf) { return (arch_curr_cpu()->arch.exc_depth > 1U) ? (true) : (false); } @@ -48,7 +48,7 @@ static ALWAYS_INLINE bool arch_is_in_nested_exception(const z_arch_esf_t *esf) * This function is used by privileged code to determine if the thread * associated with the stack frame is in user mode. */ -static ALWAYS_INLINE bool z_arm_preempted_thread_in_user_mode(const z_arch_esf_t *esf) +static ALWAYS_INLINE bool z_arm_preempted_thread_in_user_mode(const struct arch_esf *esf) { return ((esf->basic.xpsr & CPSR_M_Msk) == CPSR_M_USR); } diff --git a/arch/arm/include/cortex_a_r/kernel_arch_func.h b/arch/arm/include/cortex_a_r/kernel_arch_func.h index 88f631ff4b4..3486d7d4d4e 100644 --- a/arch/arm/include/cortex_a_r/kernel_arch_func.h +++ b/arch/arm/include/cortex_a_r/kernel_arch_func.h @@ -59,7 +59,7 @@ extern FUNC_NORETURN void z_arm_userspace_enter(k_thread_entry_t user_entry, uint32_t stack_end, uint32_t stack_start); -extern void z_arm_fatal_error(unsigned int reason, const z_arch_esf_t *esf); +extern void z_arm_fatal_error(unsigned int reason, const struct arch_esf *esf); #endif /* _ASMLANGUAGE */ diff --git a/arch/arm/include/cortex_m/exception.h b/arch/arm/include/cortex_m/exception.h index bf86abd77c7..89bdd4b83e9 100644 --- a/arch/arm/include/cortex_m/exception.h +++ b/arch/arm/include/cortex_m/exception.h @@ -68,7 +68,7 @@ static ALWAYS_INLINE bool arch_is_in_isr(void) * @return true if execution state was in handler mode, before * the current exception occurred, otherwise false. */ -static ALWAYS_INLINE bool arch_is_in_nested_exception(const z_arch_esf_t *esf) +static ALWAYS_INLINE bool arch_is_in_nested_exception(const struct arch_esf *esf) { return (esf->basic.xpsr & IPSR_ISR_Msk) ? (true) : (false); } @@ -80,7 +80,7 @@ static ALWAYS_INLINE bool arch_is_in_nested_exception(const z_arch_esf_t *esf) * @param esf the exception stack frame (unused) * @return true if the current thread was in unprivileged mode */ -static ALWAYS_INLINE bool z_arm_preempted_thread_in_user_mode(const z_arch_esf_t *esf) +static ALWAYS_INLINE bool z_arm_preempted_thread_in_user_mode(const struct arch_esf *esf) { return z_arm_thread_is_in_user_mode(); } diff --git a/arch/arm/include/cortex_m/kernel_arch_func.h b/arch/arm/include/cortex_m/kernel_arch_func.h index 77619c9d6c4..132c056c910 100644 --- a/arch/arm/include/cortex_m/kernel_arch_func.h +++ b/arch/arm/include/cortex_m/kernel_arch_func.h @@ -76,7 +76,7 @@ extern FUNC_NORETURN void z_arm_userspace_enter(k_thread_entry_t user_entry, uint32_t stack_end, uint32_t stack_start); -extern void z_arm_fatal_error(unsigned int reason, const z_arch_esf_t *esf); +extern void z_arm_fatal_error(unsigned int reason, const struct arch_esf *esf); #endif /* _ASMLANGUAGE */ diff --git a/arch/arm/include/kernel_arch_data.h b/arch/arm/include/kernel_arch_data.h index 5ad19db8f84..9b4ca04f66c 100644 --- a/arch/arm/include/kernel_arch_data.h +++ b/arch/arm/include/kernel_arch_data.h @@ -42,7 +42,7 @@ extern "C" { #endif -typedef struct __esf _esf_t; +typedef struct arch_esf _esf_t; typedef struct __basic_sf _basic_sf_t; #if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING) typedef struct __fpu_sf _fpu_sf_t; diff --git a/arch/arm/include/offsets_short_arch.h b/arch/arm/include/offsets_short_arch.h index 4ceb1fc3f7a..ea6af4db92d 100644 --- a/arch/arm/include/offsets_short_arch.h +++ b/arch/arm/include/offsets_short_arch.h @@ -7,7 +7,7 @@ #ifndef ZEPHYR_ARCH_ARM_INCLUDE_OFFSETS_SHORT_ARCH_H_ #define ZEPHYR_ARCH_ARM_INCLUDE_OFFSETS_SHORT_ARCH_H_ -#include +#include /* kernel */ diff --git a/arch/arm64/core/CMakeLists.txt b/arch/arm64/core/CMakeLists.txt index 05e4be8c0ea..9112e55f302 100644 --- a/arch/arm64/core/CMakeLists.txt +++ b/arch/arm64/core/CMakeLists.txt @@ -4,10 +4,12 @@ zephyr_library() zephyr_library_sources( cpu_idle.S + early_mem_funcs.S fatal.c irq_init.c irq_manage.c prep_c.c + reboot.c reset.S reset.c switch.S @@ -27,6 +29,7 @@ if(${SRAM_LENGTH} GREATER 11 OR ${KERNEL_VM_LENGTH} GREATER 11) zephyr_cc_option(-mcmodel=large) endif() +zephyr_library_sources_ifdef(CONFIG_LLEXT elf.c) zephyr_library_sources_ifdef(CONFIG_FPU_SHARING fpu.c fpu.S) zephyr_library_sources_ifdef(CONFIG_ARM_MMU mmu.c mmu.S) zephyr_library_sources_ifdef(CONFIG_ARM_MPU cortex_r/arm_mpu.c) @@ -43,7 +46,7 @@ if ((CONFIG_MP_MAX_NUM_CPUS GREATER 1) OR (CONFIG_SMP)) endif () zephyr_cc_option_ifdef(CONFIG_USERSPACE -mno-outline-atomics) -zephyr_cc_option_ifdef(CONFIG_ARM64_ENABLE_FRAME_POINTER -mno-omit-leaf-frame-pointer) +zephyr_cc_option_ifdef(CONFIG_FRAME_POINTER -mno-omit-leaf-frame-pointer) # GCC may generate ldp/stp instructions with the Advanced SIMD Qn registers for # consecutive 32-byte loads and stores. Saving and restoring the Advanced SIMD diff --git a/arch/arm64/core/Kconfig b/arch/arm64/core/Kconfig index 8f09d49a04c..29f2cb6105b 100644 --- a/arch/arm64/core/Kconfig +++ b/arch/arm64/core/Kconfig @@ -145,13 +145,30 @@ config ARM64_SAFE_EXCEPTION_STACK config ARM64_ENABLE_FRAME_POINTER bool - default y depends on OVERRIDE_FRAME_POINTER_DEFAULT && !OMIT_FRAME_POINTER + depends on !FRAME_POINTER + select DEPRECATED help + Deprecated. Use CONFIG_FRAME_POINTER instead. Hidden option to simplify access to OVERRIDE_FRAME_POINTER_DEFAULT and OMIT_FRAME_POINTER. It is automatically enabled when the frame pointer unwinding is enabled. +config ARM64_EXCEPTION_STACK_TRACE + bool + default y + depends on FRAME_POINTER + help + Internal config to enable runtime stack traces on fatal exceptions. + +config ARCH_HAS_STACKWALK + bool + default y + depends on FRAME_POINTER + help + Internal config to indicate that the arch_stack_walk() API is implemented + and it can be enabled. + config ARM64_SAFE_EXCEPTION_STACK_SIZE int "The stack size of the safe exception stack" default 4096 diff --git a/arch/arm64/core/coredump.c b/arch/arm64/core/coredump.c index 399cf85e3d0..0176b61612e 100644 --- a/arch/arm64/core/coredump.c +++ b/arch/arm64/core/coredump.c @@ -13,7 +13,7 @@ #define ARCH_HDR_VER 1 /* Structure to store the architecture registers passed arch_coredump_info_dump - * As callee saved registers are not provided in z_arch_esf_t structure in Zephyr + * As callee saved registers are not provided in struct arch_esf structure in Zephyr * we just need 22 registers. */ struct arm64_arch_block { @@ -50,7 +50,7 @@ struct arm64_arch_block { */ static struct arm64_arch_block arch_blk; -void arch_coredump_info_dump(const z_arch_esf_t *esf) +void arch_coredump_info_dump(const struct arch_esf *esf) { /* Target architecture information header */ /* Information just relevant to the python parser */ @@ -69,7 +69,7 @@ void arch_coredump_info_dump(const z_arch_esf_t *esf) /* * Copies the thread registers to a memory block that will be printed out - * The thread registers are already provided by structure z_arch_esf_t + * The thread registers are already provided by structure struct arch_esf */ arch_blk.r.x0 = esf->x0; arch_blk.r.x1 = esf->x1; diff --git a/arch/arm64/core/cpu_idle.S b/arch/arm64/core/cpu_idle.S index e01881ed58d..7681e212054 100644 --- a/arch/arm64/core/cpu_idle.S +++ b/arch/arm64/core/cpu_idle.S @@ -13,7 +13,7 @@ #include _ASM_FILE_PROLOGUE - +#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_IDLE GTEXT(arch_cpu_idle) SECTION_FUNC(TEXT, arch_cpu_idle) #ifdef CONFIG_TRACING @@ -25,7 +25,9 @@ SECTION_FUNC(TEXT, arch_cpu_idle) wfi msr daifclr, #(DAIFCLR_IRQ_BIT) ret +#endif +#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE GTEXT(arch_cpu_atomic_idle) SECTION_FUNC(TEXT, arch_cpu_atomic_idle) #ifdef CONFIG_TRACING @@ -41,3 +43,5 @@ SECTION_FUNC(TEXT, arch_cpu_atomic_idle) msr daifclr, #(DAIFCLR_IRQ_BIT) _irq_disabled: ret + +#endif diff --git a/arch/arm64/core/early_mem_funcs.S b/arch/arm64/core/early_mem_funcs.S new file mode 100644 index 00000000000..383cdec7901 --- /dev/null +++ b/arch/arm64/core/early_mem_funcs.S @@ -0,0 +1,83 @@ +/* + * Copyright (c) BayLibre SAS + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +_ASM_FILE_PROLOGUE + +/* + * These simple memset and memcpy alternatives are necessary as the optimized + * ones depend on the MMU to be active (see commit c5b898743a20). + * + * Furthermore, we can't implement those in C as the compiler is just too + * smart for its own good and replaces our simple loops into direct calls + * to memset or memcpy on its own. + */ + +/* void z_early_memset(void *dst, int c, size_t n) */ +GTEXT(z_early_memset) +SECTION_FUNC(TEXT, z_early_memset) + + /* is dst pointer 8-bytes aligned? */ + tst x0, #0x7 + b.ne 2f + + /* at least 8 bytes to set? */ + cmp x2, #8 + b.lo 2f + + /* spread the byte value across whole 64 bits */ + and x8, x1, #0xff + mov x9, #0x0101010101010101 + mul x8, x8, x9 + +1: /* 8 bytes at a time */ + sub x2, x2, #8 + cmp x2, #7 + str x8, [x0], #8 + b.hi 1b + +2: /* at least one byte to set? */ + cbz x2, 4f + +3: /* one byte at a time */ + subs x2, x2, #1 + strb w8, [x0], #1 + b.ne 3b + +4: ret + +/* void z_early_memcpy(void *dst, const void *src, size_t n) */ +GTEXT(z_early_memcpy) +SECTION_FUNC(TEXT, z_early_memcpy) + + /* are dst and src pointers 8-bytes aligned? */ + orr x8, x1, x0 + tst x8, #0x7 + b.ne 2f + + /* at least 8 bytes to copy? */ + cmp x2, #8 + b.lo 2f + +1: /* 8 bytes at a time */ + ldr x8, [x1], #8 + sub x2, x2, #8 + cmp x2, #7 + str x8, [x0], #8 + b.hi 1b + +2: /* at least one byte to copy? */ + cbz x2, 4f + +3: /* one byte at a time */ + ldrb w8, [x1], #1 + subs x2, x2, #1 + strb w8, [x0], #1 + b.ne 3b + +4: ret diff --git a/arch/arm64/core/elf.c b/arch/arm64/core/elf.c new file mode 100644 index 00000000000..66e9f21fc06 --- /dev/null +++ b/arch/arm64/core/elf.c @@ -0,0 +1,515 @@ +/* + * Copyright (c) 2024 BayLibre SAS + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(elf, CONFIG_LLEXT_LOG_LEVEL); + +#define R_ARM_NONE 0 +#define R_AARCH64_NONE 256 + +/* Static data relocations */ +#define R_AARCH64_ABS64 257 +#define R_AARCH64_ABS32 258 +#define R_AARCH64_ABS16 259 +#define R_AARCH64_PREL64 260 +#define R_AARCH64_PREL32 261 +#define R_AARCH64_PREL16 262 + +/* Static relocations */ +#define R_AARCH64_MOVW_UABS_G0 263 +#define R_AARCH64_MOVW_UABS_G0_NC 264 +#define R_AARCH64_MOVW_UABS_G1 265 +#define R_AARCH64_MOVW_UABS_G1_NC 266 +#define R_AARCH64_MOVW_UABS_G2 267 +#define R_AARCH64_MOVW_UABS_G2_NC 268 +#define R_AARCH64_MOVW_UABS_G3 269 +#define R_AARCH64_MOVW_SABS_G0 270 +#define R_AARCH64_MOVW_SABS_G1 271 +#define R_AARCH64_MOVW_SABS_G2 272 +#define R_AARCH64_MOVW_PREL_G0 287 +#define R_AARCH64_MOVW_PREL_G0_NC 288 +#define R_AARCH64_MOVW_PREL_G1 289 +#define R_AARCH64_MOVW_PREL_G1_NC 290 +#define R_AARCH64_MOVW_PREL_G2 291 +#define R_AARCH64_MOVW_PREL_G2_NC 292 +#define R_AARCH64_MOVW_PREL_G3 293 + +#define R_AARCH64_LD_PREL_LO19 273 +#define R_AARCH64_ADR_PREL_LO21 274 +#define R_AARCH64_ADR_PREL_PG_HI21 275 +#define R_AARCH64_ADR_PREL_PG_HI21_NC 276 +#define R_AARCH64_ADD_ABS_LO12_NC 277 +#define R_AARCH64_LDST8_ABS_LO12_NC 278 +#define R_AARCH64_TSTBR14 279 +#define R_AARCH64_CONDBR19 280 +#define R_AARCH64_JUMP26 282 +#define R_AARCH64_CALL26 283 +#define R_AARCH64_LDST16_ABS_LO12_NC 284 +#define R_AARCH64_LDST32_ABS_LO12_NC 285 +#define R_AARCH64_LDST64_ABS_LO12_NC 286 +#define R_AARCH64_LDST128_ABS_LO12_NC 299 + +/* Masks for immediate values */ +#define AARCH64_MASK_IMM12 BIT_MASK(12) +#define AARCH64_MASK_IMM14 BIT_MASK(14) +#define AARCH64_MASK_IMM16 BIT_MASK(16) +#define AARCH64_MASK_IMM19 BIT_MASK(19) +#define AARCH64_MASK_IMM26 BIT_MASK(26) + +/* MOV instruction helper symbols */ +#define AARCH64_MASK_MOV_OPCODE BIT_MASK(8) +#define AARCH64_SHIFT_MOV_OPCODE (23) +#define AARCH64_SHIFT_MOV_IMM16 (5) +#define AARCH64_OPCODE_MOVN (0b00100101) +#define AARCH64_OPCODE_MOVZ (0b10100101) + +/* ADR instruction helper symbols */ +#define AARCH64_MASK_ADR_IMMLO BIT_MASK(2) +#define AARCH64_MASK_ADR_IMMHI BIT_MASK(19) +#define AARCH64_SHIFT_ADR_IMMLO (29) +#define AARCH64_SHIFT_ADR_IMMHI (5) +#define AARCH64_ADR_IMMLO_BITS (2) + +#define AARCH64_PAGE(expr) ((expr) & ~0xFFF) + +enum aarch64_reloc_type { + AARCH64_RELOC_TYPE_NONE, + AARCH64_RELOC_TYPE_ABS, + AARCH64_RELOC_TYPE_PREL, + AARCH64_RELOC_TYPE_PAGE, +}; + +/** + * @brief Function computing a relocation (X in AArch64 ELF). + * + * @param[in] reloc_type Type of relocation operation. + * @param[in] loc Address of an opcode to rewrite (P in AArch64 ELF). + * @param[in] sym_base_addr Address of the symbol referenced by relocation (S in AArch64 ELF). + * @param[in] addend Addend from RELA relocation. + * + * @return Result of the relocation operation (X in AArch64 ELF) + */ +static uint64_t reloc(enum aarch64_reloc_type reloc_type, uintptr_t loc, uintptr_t sym_base_addr, + int64_t addend) +{ + switch (reloc_type) { + case AARCH64_RELOC_TYPE_ABS: + return sym_base_addr + addend; + case AARCH64_RELOC_TYPE_PREL: + return sym_base_addr + addend - loc; + case AARCH64_RELOC_TYPE_PAGE: + return AARCH64_PAGE(sym_base_addr + addend) - AARCH64_PAGE(loc); + case AARCH64_RELOC_TYPE_NONE: + return 0; + } + + CODE_UNREACHABLE; +} + +/** + * @brief Handler for static data relocations. + * + * @param[in] rel Relocation data provided by ELF + * @param[in] reloc_type Type of relocation operation. + * @param[in] loc Address of an opcode to rewrite (P in AArch64 ELF). + * @param[in] sym_base_addr Address of the symbol referenced by relocation (S in AArch64 ELF). + * + * @retval -ERANGE Relocation value overflow + * @retval 0 Successful relocation + */ +static int data_reloc_handler(elf_rela_t *rel, elf_word reloc_type, uintptr_t loc, + uintptr_t sym_base_addr) +{ + int64_t x; + + switch (reloc_type) { + case R_AARCH64_ABS64: + *(int64_t *)loc = reloc(AARCH64_RELOC_TYPE_ABS, loc, sym_base_addr, rel->r_addend); + break; + + case R_AARCH64_ABS32: + x = reloc(AARCH64_RELOC_TYPE_ABS, loc, sym_base_addr, rel->r_addend); + if (x < 0 || x > UINT32_MAX) { + return -ERANGE; + } + *(uint32_t *)loc = (uint32_t)x; + break; + + case R_AARCH64_ABS16: + x = reloc(AARCH64_RELOC_TYPE_ABS, loc, sym_base_addr, rel->r_addend); + if (x < 0 || x > UINT16_MAX) { + return -ERANGE; + } + *(uint16_t *)loc = (uint16_t)x; + break; + + case R_AARCH64_PREL64: + *(int64_t *)loc = reloc(AARCH64_RELOC_TYPE_PREL, loc, sym_base_addr, rel->r_addend); + break; + + case R_AARCH64_PREL32: + x = reloc(AARCH64_RELOC_TYPE_PREL, loc, sym_base_addr, rel->r_addend); + if (x < INT32_MIN || x > INT32_MAX) { + return -ERANGE; + } + *(int32_t *)loc = (int32_t)x; + break; + + case R_AARCH64_PREL16: + x = reloc(AARCH64_RELOC_TYPE_PREL, loc, sym_base_addr, rel->r_addend); + if (x < INT16_MIN || x > INT16_MAX) { + return -ERANGE; + } + *(int16_t *)loc = (int16_t)x; + break; + + default: + CODE_UNREACHABLE; + } + + return 0; +} + +/** + * @brief Handler for relocations using MOV* instructions. + * + * @param[in] rel Relocation data provided by ELF + * @param[in] reloc_type Type of relocation operation. + * @param[in] loc Address of an opcode to rewrite (P in AArch64 ELF). + * @param[in] sym_base_addr Address of the symbol referenced by relocation (S in AArch64 ELF). + * + * @retval -ERANGE Relocation value overflow + * @retval 0 Successful relocation + */ +static int movw_reloc_handler(elf_rela_t *rel, elf_word reloc_type, uintptr_t loc, + uintptr_t sym_base_addr) +{ + int64_t x; + uint32_t imm; + int lsb = 0; /* LSB of X to be used */ + bool is_movnz = false; + enum aarch64_reloc_type type = AARCH64_RELOC_TYPE_ABS; + uint32_t opcode = sys_le32_to_cpu(*(uint32_t *)loc); + + switch (reloc_type) { + case R_AARCH64_MOVW_SABS_G0: + is_movnz = true; + case R_AARCH64_MOVW_UABS_G0_NC: + case R_AARCH64_MOVW_UABS_G0: + break; + + case R_AARCH64_MOVW_SABS_G1: + is_movnz = true; + case R_AARCH64_MOVW_UABS_G1_NC: + case R_AARCH64_MOVW_UABS_G1: + lsb = 16; + break; + + case R_AARCH64_MOVW_SABS_G2: + is_movnz = true; + case R_AARCH64_MOVW_UABS_G2_NC: + case R_AARCH64_MOVW_UABS_G2: + lsb = 32; + break; + + case R_AARCH64_MOVW_UABS_G3: + lsb = 48; + break; + + case R_AARCH64_MOVW_PREL_G0: + is_movnz = true; + case R_AARCH64_MOVW_PREL_G0_NC: + type = AARCH64_RELOC_TYPE_PREL; + break; + + case R_AARCH64_MOVW_PREL_G1: + is_movnz = true; + case R_AARCH64_MOVW_PREL_G1_NC: + type = AARCH64_RELOC_TYPE_PREL; + lsb = 16; + break; + + case R_AARCH64_MOVW_PREL_G2: + is_movnz = true; + case R_AARCH64_MOVW_PREL_G2_NC: + type = AARCH64_RELOC_TYPE_PREL; + lsb = 32; + break; + + case R_AARCH64_MOVW_PREL_G3: + is_movnz = true; + type = AARCH64_RELOC_TYPE_PREL; + lsb = 48; + break; + + default: + CODE_UNREACHABLE; + } + + x = reloc(type, loc, sym_base_addr, rel->r_addend); + imm = x >> lsb; + + /* Manipulate opcode for signed relocations. Result depends on sign of immediate value. */ + if (is_movnz) { + opcode &= ~(AARCH64_MASK_MOV_OPCODE << AARCH64_SHIFT_MOV_OPCODE); + + if (x >= 0) { + opcode |= (AARCH64_OPCODE_MOVN << AARCH64_SHIFT_MOV_OPCODE); + } else { + opcode |= (AARCH64_OPCODE_MOVZ << AARCH64_SHIFT_MOV_OPCODE); + /* Need to invert immediate value for MOVZ. */ + imm = ~imm; + } + } + + opcode &= ~(AARCH64_MASK_IMM16 << AARCH64_SHIFT_MOV_IMM16); + opcode |= (imm & AARCH64_MASK_IMM16) << AARCH64_SHIFT_MOV_IMM16; + + *(uint32_t *)loc = sys_cpu_to_le32(opcode); + + if (imm > UINT16_MAX) { + return -ERANGE; + } + + return 0; +} + +/** + * @brief Handler for static relocations except these related to MOV* instructions. + * + * @param[in] rel Relocation data provided by ELF + * @param[in] reloc_type Type of relocation operation. + * @param[in] loc Address of an opcode to rewrite (P in AArch64 ELF). + * @param[in] sym_base_addr Address of the symbol referenced by relocation (S in AArch64 ELF). + * + * @retval -ERANGE Relocation value overflow + * @retval 0 Successful relocation + */ +static int imm_reloc_handler(elf_rela_t *rel, elf_word reloc_type, uintptr_t loc, + uintptr_t sym_base_addr) +{ + int lsb = 2; /* LSB of X to be used */ + int len; /* bit length of immediate value */ + int shift = 10; /* shift of the immediate in instruction encoding */ + uint64_t imm; + uint32_t bitmask = AARCH64_MASK_IMM12; + int64_t x; + bool is_adr = false; + enum aarch64_reloc_type type = AARCH64_RELOC_TYPE_ABS; + uint32_t opcode = sys_le32_to_cpu(*(uint32_t *)loc); + + switch (reloc_type) { + case R_AARCH64_ADD_ABS_LO12_NC: + case R_AARCH64_LDST8_ABS_LO12_NC: + lsb = 0; + len = 12; + break; + + case R_AARCH64_LDST16_ABS_LO12_NC: + lsb = 1; + len = 11; + break; + + case R_AARCH64_LDST32_ABS_LO12_NC: + len = 10; + break; + + case R_AARCH64_LDST64_ABS_LO12_NC: + lsb = 3; + len = 9; + break; + + case R_AARCH64_LDST128_ABS_LO12_NC: + lsb = 4; + len = 8; + break; + + case R_AARCH64_LD_PREL_LO19: + case R_AARCH64_CONDBR19: + type = AARCH64_RELOC_TYPE_PREL; + bitmask = AARCH64_MASK_IMM19; + shift = 5; + len = 19; + break; + + case R_AARCH64_ADR_PREL_LO21: + type = AARCH64_RELOC_TYPE_PREL; + is_adr = true; + lsb = 0; + len = 21; + break; + + case R_AARCH64_TSTBR14: + type = AARCH64_RELOC_TYPE_PREL; + bitmask = AARCH64_MASK_IMM14; + shift = 5; + len = 14; + break; + + case R_AARCH64_ADR_PREL_PG_HI21_NC: + case R_AARCH64_ADR_PREL_PG_HI21: + type = AARCH64_RELOC_TYPE_PAGE; + is_adr = true; + lsb = 12; + len = 21; + break; + + case R_AARCH64_CALL26: + case R_AARCH64_JUMP26: + type = AARCH64_RELOC_TYPE_PREL; + bitmask = AARCH64_MASK_IMM26; + shift = 0; + len = 26; + break; + + default: + CODE_UNREACHABLE; + } + + x = reloc(type, loc, sym_base_addr, rel->r_addend); + x >>= lsb; + + imm = x & BIT_MASK(len); + + /* ADR instruction has immediate value split into two fields. */ + if (is_adr) { + uint32_t immlo, immhi; + + immlo = (imm & AARCH64_MASK_ADR_IMMLO) << AARCH64_SHIFT_ADR_IMMLO; + imm >>= AARCH64_ADR_IMMLO_BITS; + immhi = (imm & AARCH64_MASK_ADR_IMMHI) << AARCH64_SHIFT_ADR_IMMHI; + imm = immlo | immhi; + + shift = 0; + bitmask = ((AARCH64_MASK_ADR_IMMLO << AARCH64_SHIFT_ADR_IMMLO) | + (AARCH64_MASK_ADR_IMMHI << AARCH64_SHIFT_ADR_IMMHI)); + } + + opcode &= ~(bitmask << shift); + opcode |= (imm & bitmask) << shift; + + *(uint32_t *)loc = sys_cpu_to_le32(opcode); + + /* Mask X sign bit and upper bits. */ + x = (int64_t)(x & ~BIT_MASK(len - 1)) >> (len - 1); + + /* Incrementing X will either overflow and set it to 0 or + * set it 1. Any other case indicates that there was an overflow in relocation. + */ + if ((int64_t)x++ > 1) { + return -ERANGE; + } + + return 0; +} + +/** + * @brief Architecture specific function for relocating partially linked (static) elf + * + * Elf files contain a series of relocations described in a section. These relocation + * instructions are architecture specific and each architecture supporting extensions + * must implement this. + * + * The relocation codes for arm64 are well documented + * https://github.com/ARM-software/abi-aa/blob/main/aaelf64/aaelf64.rst#relocation + * + * @param[in] rel Relocation data provided by ELF + * @param[in] loc Address of an opcode to rewrite (P in AArch64 ELF) + * @param[in] sym_base_addr Address of the symbol referenced by relocation (S in AArch64 ELF) + * @param[in] sym_name Name of symbol referenced by relocation + * @param[in] load_bias `.text` load address + * @retval 0 Success + * @retval -ENOTSUP Unsupported relocation + * @retval -ENOEXEC Invalid relocation + */ +int arch_elf_relocate(elf_rela_t *rel, uintptr_t loc, uintptr_t sym_base_addr, const char *sym_name, + uintptr_t load_bias) +{ + int ret = 0; + bool overflow_check = true; + elf_word reloc_type = ELF_R_TYPE(rel->r_info); + + switch (reloc_type) { + case R_ARM_NONE: + case R_AARCH64_NONE: + overflow_check = false; + break; + + case R_AARCH64_ABS64: + case R_AARCH64_PREL64: + overflow_check = false; + case R_AARCH64_ABS16: + case R_AARCH64_ABS32: + case R_AARCH64_PREL16: + case R_AARCH64_PREL32: + ret = data_reloc_handler(rel, reloc_type, loc, sym_base_addr); + break; + + case R_AARCH64_MOVW_UABS_G0_NC: + case R_AARCH64_MOVW_UABS_G1_NC: + case R_AARCH64_MOVW_UABS_G2_NC: + case R_AARCH64_MOVW_UABS_G3: + case R_AARCH64_MOVW_PREL_G0_NC: + case R_AARCH64_MOVW_PREL_G1_NC: + case R_AARCH64_MOVW_PREL_G2_NC: + case R_AARCH64_MOVW_PREL_G3: + overflow_check = false; + case R_AARCH64_MOVW_UABS_G0: + case R_AARCH64_MOVW_UABS_G1: + case R_AARCH64_MOVW_UABS_G2: + case R_AARCH64_MOVW_SABS_G0: + case R_AARCH64_MOVW_SABS_G1: + case R_AARCH64_MOVW_SABS_G2: + case R_AARCH64_MOVW_PREL_G0: + case R_AARCH64_MOVW_PREL_G1: + case R_AARCH64_MOVW_PREL_G2: + ret = movw_reloc_handler(rel, reloc_type, loc, sym_base_addr); + break; + + case R_AARCH64_ADD_ABS_LO12_NC: + case R_AARCH64_LDST8_ABS_LO12_NC: + case R_AARCH64_LDST16_ABS_LO12_NC: + case R_AARCH64_LDST32_ABS_LO12_NC: + case R_AARCH64_LDST64_ABS_LO12_NC: + case R_AARCH64_LDST128_ABS_LO12_NC: + overflow_check = false; + case R_AARCH64_LD_PREL_LO19: + case R_AARCH64_ADR_PREL_LO21: + case R_AARCH64_TSTBR14: + case R_AARCH64_CONDBR19: + ret = imm_reloc_handler(rel, reloc_type, loc, sym_base_addr); + break; + + case R_AARCH64_ADR_PREL_PG_HI21_NC: + overflow_check = false; + case R_AARCH64_ADR_PREL_PG_HI21: + ret = imm_reloc_handler(rel, reloc_type, loc, sym_base_addr); + break; + + case R_AARCH64_CALL26: + case R_AARCH64_JUMP26: + ret = imm_reloc_handler(rel, reloc_type, loc, sym_base_addr); + /* TODO Handle case when address exceeds +/- 128MB */ + break; + + default: + LOG_ERR("unknown relocation: %llu\n", reloc_type); + return -ENOEXEC; + } + + if (overflow_check && ret == -ERANGE) { + LOG_ERR("sym '%s': relocation out of range (%#lx -> %#lx)\n", sym_name, loc, + sym_base_addr); + return -ENOEXEC; + } + + return 0; +} diff --git a/arch/arm64/core/fatal.c b/arch/arm64/core/fatal.c index 84ff767508e..7955b6f7d6d 100644 --- a/arch/arm64/core/fatal.c +++ b/arch/arm64/core/fatal.c @@ -13,6 +13,7 @@ * exceptions */ +#include #include #include #include @@ -20,6 +21,8 @@ #include #include +#include "paging.h" + LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); #ifdef CONFIG_ARM64_SAFE_EXCEPTION_STACK @@ -180,7 +183,7 @@ static void dump_esr(uint64_t esr, bool *dump_far) LOG_ERR(" ISS: 0x%llx", GET_ESR_ISS(esr)); } -static void esf_dump(const z_arch_esf_t *esf) +static void esf_dump(const struct arch_esf *esf) { LOG_ERR("x0: 0x%016llx x1: 0x%016llx", esf->x0, esf->x1); LOG_ERR("x2: 0x%016llx x3: 0x%016llx", esf->x2, esf->x3); @@ -193,9 +196,13 @@ static void esf_dump(const z_arch_esf_t *esf) LOG_ERR("x16: 0x%016llx x17: 0x%016llx", esf->x16, esf->x17); LOG_ERR("x18: 0x%016llx lr: 0x%016llx", esf->x18, esf->lr); } +#endif /* CONFIG_EXCEPTION_DEBUG */ -#ifdef CONFIG_ARM64_ENABLE_FRAME_POINTER -static void esf_unwind(const z_arch_esf_t *esf) +#ifdef CONFIG_ARCH_STACKWALK +typedef bool (*arm64_stacktrace_cb)(void *cookie, unsigned long addr, void *fp); + +static void walk_stackframe(arm64_stacktrace_cb cb, void *cookie, const struct arch_esf *esf, + int max_frames) { /* * For GCC: @@ -217,25 +224,64 @@ static void esf_unwind(const z_arch_esf_t *esf) * + +-----------------+ */ - uint64_t *fp = (uint64_t *) esf->fp; - unsigned int count = 0; + uint64_t *fp; uint64_t lr; - LOG_ERR(""); - while (fp != NULL) { + if (esf != NULL) { + fp = (uint64_t *) esf->fp; + } else { + return; + } + + for (int i = 0; (fp != NULL) && (i < max_frames); i++) { lr = fp[1]; - LOG_ERR("backtrace %2d: fp: 0x%016llx lr: 0x%016llx", - count++, (uint64_t) fp, lr); + if (!cb(cookie, lr, fp)) { + break; + } fp = (uint64_t *) fp[0]; } - LOG_ERR(""); } -#endif -#endif /* CONFIG_EXCEPTION_DEBUG */ +void arch_stack_walk(stack_trace_callback_fn callback_fn, void *cookie, + const struct k_thread *thread, const struct arch_esf *esf) +{ + ARG_UNUSED(thread); + + walk_stackframe((arm64_stacktrace_cb)callback_fn, cookie, esf, + CONFIG_ARCH_STACKWALK_MAX_FRAMES); +} +#endif /* CONFIG_ARCH_STACKWALK */ + +#ifdef CONFIG_EXCEPTION_STACK_TRACE +static bool print_trace_address(void *arg, unsigned long lr, void *fp) +{ + int *i = arg; +#ifdef CONFIG_SYMTAB + uint32_t offset = 0; + const char *name = symtab_find_symbol_name(lr, &offset); + + LOG_ERR(" %d: fp: 0x%016llx lr: 0x%016lx [%s+0x%x]", (*i)++, (uint64_t)fp, lr, name, + offset); +#else + LOG_ERR(" %d: fp: 0x%016llx lr: 0x%016lx", (*i)++, (uint64_t)fp, lr); +#endif /* CONFIG_SYMTAB */ + + return true; +} + +static void esf_unwind(const struct arch_esf *esf) +{ + int i = 0; + + LOG_ERR(""); + LOG_ERR("call trace:"); + walk_stackframe(print_trace_address, &i, esf, CONFIG_ARCH_STACKWALK_MAX_FRAMES); + LOG_ERR(""); +} +#endif /* CONFIG_EXCEPTION_STACK_TRACE */ #ifdef CONFIG_ARM64_STACK_PROTECTION -static bool z_arm64_stack_corruption_check(z_arch_esf_t *esf, uint64_t esr, uint64_t far) +static bool z_arm64_stack_corruption_check(struct arch_esf *esf, uint64_t esr, uint64_t far) { uint64_t sp, sp_limit, guard_start; /* 0x25 means data abort from current EL */ @@ -275,11 +321,12 @@ static bool z_arm64_stack_corruption_check(z_arch_esf_t *esf, uint64_t esr, uint } #endif -static bool is_recoverable(z_arch_esf_t *esf, uint64_t esr, uint64_t far, +static bool is_recoverable(struct arch_esf *esf, uint64_t esr, uint64_t far, uint64_t elr) { - if (!esf) + if (!esf) { return false; + } #ifdef CONFIG_USERSPACE for (int i = 0; i < ARRAY_SIZE(exceptions); i++) { @@ -297,7 +344,7 @@ static bool is_recoverable(z_arch_esf_t *esf, uint64_t esr, uint64_t far, return false; } -void z_arm64_fatal_error(unsigned int reason, z_arch_esf_t *esf) +void z_arm64_fatal_error(unsigned int reason, struct arch_esf *esf) { uint64_t esr = 0; uint64_t elr = 0; @@ -328,6 +375,12 @@ void z_arm64_fatal_error(unsigned int reason, z_arch_esf_t *esf) } #endif + if (IS_ENABLED(CONFIG_DEMAND_PAGING) && + reason != K_ERR_STACK_CHK_FAIL && + z_arm64_do_demand_paging(esf, esr, far)) { + return; + } + if (GET_EL(el) != MODE_EL0) { #ifdef CONFIG_EXCEPTION_DEBUG bool dump_far = false; @@ -336,8 +389,9 @@ void z_arm64_fatal_error(unsigned int reason, z_arch_esf_t *esf) dump_esr(esr, &dump_far); - if (dump_far) + if (dump_far) { LOG_ERR("FAR_ELn: 0x%016llx", far); + } LOG_ERR("TPIDRRO: 0x%016llx", read_tpidrro_el0()); #endif /* CONFIG_EXCEPTION_DEBUG */ @@ -354,9 +408,9 @@ void z_arm64_fatal_error(unsigned int reason, z_arch_esf_t *esf) esf_dump(esf); } -#ifdef CONFIG_ARM64_ENABLE_FRAME_POINTER +#ifdef CONFIG_EXCEPTION_STACK_TRACE esf_unwind(esf); -#endif /* CONFIG_ARM64_ENABLE_FRAME_POINTER */ +#endif /* CONFIG_EXCEPTION_STACK_TRACE */ #endif /* CONFIG_EXCEPTION_DEBUG */ z_fatal_error(reason, esf); @@ -370,7 +424,7 @@ void z_arm64_fatal_error(unsigned int reason, z_arch_esf_t *esf) * * @param esf exception frame */ -void z_arm64_do_kernel_oops(z_arch_esf_t *esf) +void z_arm64_do_kernel_oops(struct arch_esf *esf) { /* x8 holds the exception reason */ unsigned int reason = esf->x8; diff --git a/arch/arm64/core/fpu.c b/arch/arm64/core/fpu.c index 0133eed2dca..a585165b943 100644 --- a/arch/arm64/core/fpu.c +++ b/arch/arm64/core/fpu.c @@ -159,7 +159,7 @@ void z_arm64_fpu_enter_exc(void) * simulate them and leave the FPU access disabled. This also avoids the * need for disabling interrupts in syscalls and IRQ handlers as well. */ -static bool simulate_str_q_insn(z_arch_esf_t *esf) +static bool simulate_str_q_insn(struct arch_esf *esf) { /* * Support only the "FP in exception" cases for now. @@ -221,7 +221,7 @@ static bool simulate_str_q_insn(z_arch_esf_t *esf) * don't get interrupted that is. To ensure that we mask interrupts to * the triggering exception context. */ -void z_arm64_fpu_trap(z_arch_esf_t *esf) +void z_arm64_fpu_trap(struct arch_esf *esf) { __ASSERT(read_daif() & DAIF_IRQ_BIT, "must be called with IRQs disabled"); diff --git a/arch/arm64/core/irq_manage.c b/arch/arm64/core/irq_manage.c index 4e96ce77bfa..6344d1e3696 100644 --- a/arch/arm64/core/irq_manage.c +++ b/arch/arm64/core/irq_manage.c @@ -18,7 +18,7 @@ #include #include -void z_arm64_fatal_error(unsigned int reason, z_arch_esf_t *esf); +void z_arm64_fatal_error(unsigned int reason, struct arch_esf *esf); #if !defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER) /* diff --git a/arch/arm64/core/irq_offload.c b/arch/arm64/core/irq_offload.c index 1d5e3c829b8..4488e26849c 100644 --- a/arch/arm64/core/irq_offload.c +++ b/arch/arm64/core/irq_offload.c @@ -23,3 +23,7 @@ void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) : [svid] "i" (_SVC_CALL_IRQ_OFFLOAD), "r" (x0), "r" (x1)); } + +void arch_irq_offload_init(void) +{ +} diff --git a/arch/arm64/core/mmu.c b/arch/arm64/core/mmu.c index 2260d22c101..a914916d605 100644 --- a/arch/arm64/core/mmu.c +++ b/arch/arm64/core/mmu.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -21,16 +22,22 @@ #include #include #include +#include #include "mmu.h" +#include "paging.h" LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); static uint64_t xlat_tables[CONFIG_MAX_XLAT_TABLES * Ln_XLAT_NUM_ENTRIES] __aligned(Ln_XLAT_NUM_ENTRIES * sizeof(uint64_t)); -static uint16_t xlat_use_count[CONFIG_MAX_XLAT_TABLES]; +static int xlat_use_count[CONFIG_MAX_XLAT_TABLES]; static struct k_spinlock xlat_lock; +/* Usage count value range */ +#define XLAT_PTE_COUNT_MASK GENMASK(15, 0) +#define XLAT_REF_COUNT_UNIT BIT(16) + /* Returns a reference to a free table */ static uint64_t *new_table(void) { @@ -39,9 +46,9 @@ static uint64_t *new_table(void) /* Look for a free table. */ for (i = 0U; i < CONFIG_MAX_XLAT_TABLES; i++) { - if (xlat_use_count[i] == 0U) { + if (xlat_use_count[i] == 0) { table = &xlat_tables[i * Ln_XLAT_NUM_ENTRIES]; - xlat_use_count[i] = 1U; + xlat_use_count[i] = XLAT_REF_COUNT_UNIT; MMU_DEBUG("allocating table [%d]%p\n", i, table); return table; } @@ -59,33 +66,88 @@ static inline unsigned int table_index(uint64_t *pte) return i; } -/* Makes a table free for reuse. */ -static void free_table(uint64_t *table) +/* Adjusts usage count and returns current count. */ +static int table_usage(uint64_t *table, int adjustment) { unsigned int i = table_index(table); + int prev_count = xlat_use_count[i]; + int new_count = prev_count + adjustment; - MMU_DEBUG("freeing table [%d]%p\n", i, table); - __ASSERT(xlat_use_count[i] == 1U, "table still in use"); - xlat_use_count[i] = 0U; + /* be reasonable not to always create a debug flood */ + if ((IS_ENABLED(DUMP_PTE) && adjustment != 0) || new_count == 0) { + MMU_DEBUG("table [%d]%p: usage %#x -> %#x\n", i, table, prev_count, new_count); + } + + __ASSERT(new_count >= 0, + "table use count underflow"); + __ASSERT(new_count == 0 || new_count >= XLAT_REF_COUNT_UNIT, + "table in use with no reference to it"); + __ASSERT((new_count & XLAT_PTE_COUNT_MASK) <= Ln_XLAT_NUM_ENTRIES, + "table PTE count overflow"); + + xlat_use_count[i] = new_count; + return new_count; } -/* Adjusts usage count and returns current count. */ -static int table_usage(uint64_t *table, int adjustment) +static inline void inc_table_ref(uint64_t *table) { - unsigned int i = table_index(table); + table_usage(table, XLAT_REF_COUNT_UNIT); +} - xlat_use_count[i] += adjustment; - __ASSERT(xlat_use_count[i] > 0, "usage count underflow"); - return xlat_use_count[i]; +static inline void dec_table_ref(uint64_t *table) +{ + int ref_unit = XLAT_REF_COUNT_UNIT; + + table_usage(table, -ref_unit); } static inline bool is_table_unused(uint64_t *table) { - return table_usage(table, 0) == 1; + return (table_usage(table, 0) & XLAT_PTE_COUNT_MASK) == 0; +} + +static inline bool is_table_single_referenced(uint64_t *table) +{ + return table_usage(table, 0) < (2 * XLAT_REF_COUNT_UNIT); +} + +#ifdef CONFIG_TEST +/* Hooks to let test code peek at table states */ + +int arm64_mmu_nb_free_tables(void) +{ + int count = 0; + + for (int i = 0; i < CONFIG_MAX_XLAT_TABLES; i++) { + if (xlat_use_count[i] == 0) { + count++; + } + } + + return count; } +int arm64_mmu_tables_total_usage(void) +{ + int count = 0; + + for (int i = 0; i < CONFIG_MAX_XLAT_TABLES; i++) { + count += xlat_use_count[i]; + } + + return count; +} + +#endif /* CONFIG_TEST */ + static inline bool is_free_desc(uint64_t desc) { + return desc == 0; +} + +static inline bool is_inval_desc(uint64_t desc) +{ + /* invalid descriptors aren't necessarily free */ return (desc & PTE_DESC_TYPE_MASK) == PTE_INVALID_DESC; } @@ -102,15 +164,15 @@ static inline bool is_block_desc(uint64_t desc) static inline uint64_t *pte_desc_table(uint64_t desc) { - uint64_t address = desc & GENMASK(47, PAGE_SIZE_SHIFT); + uint64_t address = desc & PTE_PHYSADDR_MASK; + /* tables use a 1:1 physical:virtual mapping */ return (uint64_t *)address; } static inline bool is_desc_block_aligned(uint64_t desc, unsigned int level_size) { - uint64_t mask = GENMASK(47, PAGE_SIZE_SHIFT); - bool aligned = !((desc & mask) & (level_size - 1)); + bool aligned = (desc & PTE_PHYSADDR_MASK & (level_size - 1)) == 0; if (!aligned) { MMU_DEBUG("misaligned desc 0x%016llx for block size 0x%x\n", @@ -123,7 +185,7 @@ static inline bool is_desc_block_aligned(uint64_t desc, unsigned int level_size) static inline bool is_desc_superset(uint64_t desc1, uint64_t desc2, unsigned int level) { - uint64_t mask = DESC_ATTRS_MASK | GENMASK(47, LEVEL_TO_VA_SIZE_SHIFT(level)); + uint64_t mask = DESC_ATTRS_MASK | GENMASK64(47, LEVEL_TO_VA_SIZE_SHIFT(level)); return (desc1 & mask) == (desc2 & mask); } @@ -139,6 +201,8 @@ static void debug_show_pte(uint64_t *pte, unsigned int level) return; } + MMU_DEBUG("0x%016llx ", *pte); + if (is_table_desc(*pte, level)) { uint64_t *table = pte_desc_table(*pte); @@ -148,8 +212,10 @@ static void debug_show_pte(uint64_t *pte, unsigned int level) if (is_block_desc(*pte)) { MMU_DEBUG("[Block] "); - } else { + } else if (!is_inval_desc(*pte)) { MMU_DEBUG("[Page] "); + } else { + MMU_DEBUG("[paged-out] "); } uint8_t mem_type = (*pte >> 2) & MT_TYPE_MASK; @@ -161,6 +227,7 @@ static void debug_show_pte(uint64_t *pte, unsigned int level) MMU_DEBUG((*pte & PTE_BLOCK_DESC_AP_ELx) ? "-ELx" : "-ELh"); MMU_DEBUG((*pte & PTE_BLOCK_DESC_PXN) ? "-PXN" : "-PX"); MMU_DEBUG((*pte & PTE_BLOCK_DESC_UXN) ? "-UXN" : "-UX"); + MMU_DEBUG((*pte & PTE_SW_WRITABLE) ? "-WRITABLE" : ""); MMU_DEBUG("\n"); } #else @@ -176,8 +243,15 @@ static void set_pte_table_desc(uint64_t *pte, uint64_t *table, unsigned int leve static void set_pte_block_desc(uint64_t *pte, uint64_t desc, unsigned int level) { - if (desc) { - desc |= (level == XLAT_LAST_LEVEL) ? PTE_PAGE_DESC : PTE_BLOCK_DESC; + if (level != XLAT_LAST_LEVEL) { + desc |= PTE_BLOCK_DESC; + } else if (!IS_ENABLED(CONFIG_DEMAND_PAGING) || (desc & PTE_BLOCK_DESC_AF) != 0) { + desc |= PTE_PAGE_DESC; + } else { + /* + * Demand paging configured and AF unset: leave the descriptor + * type to "invalid" as in arch_mem_page_out(). + */ } *pte = desc; debug_show_pte(pte, level); @@ -225,20 +299,17 @@ static uint64_t *expand_to_table(uint64_t *pte, unsigned int level) /* Link the new table in place of the pte it replaces */ set_pte_table_desc(pte, table, level); - table_usage(table, 1); return table; } -static int set_mapping(struct arm_mmu_ptables *ptables, - uintptr_t virt, size_t size, +static int set_mapping(uint64_t *top_table, uintptr_t virt, size_t size, uint64_t desc, bool may_overwrite) { - uint64_t *pte, *ptes[XLAT_LAST_LEVEL + 1]; + uint64_t *table = top_table; + uint64_t *pte; uint64_t level_size; - uint64_t *table = ptables->base_xlat_table; unsigned int level = BASE_XLAT_LEVEL; - int ret = 0; while (size) { __ASSERT(level <= XLAT_LAST_LEVEL, @@ -246,7 +317,6 @@ static int set_mapping(struct arm_mmu_ptables *ptables, /* Locate PTE for given virtual address and page table level */ pte = &table[XLAT_TABLE_VA_IDX(virt, level)]; - ptes[level] = pte; if (is_table_desc(*pte, level)) { /* Move to the next translation table level */ @@ -260,8 +330,7 @@ static int set_mapping(struct arm_mmu_ptables *ptables, LOG_ERR("entry already in use: " "level %d pte %p *pte 0x%016llx", level, pte, *pte); - ret = -EBUSY; - break; + return -EBUSY; } level_size = 1ULL << LEVEL_TO_VA_SIZE_SHIFT(level); @@ -280,8 +349,7 @@ static int set_mapping(struct arm_mmu_ptables *ptables, /* Range doesn't fit, create subtable */ table = expand_to_table(pte, level); if (!table) { - ret = -ENOMEM; - break; + return -ENOMEM; } level++; continue; @@ -291,32 +359,57 @@ static int set_mapping(struct arm_mmu_ptables *ptables, if (is_free_desc(*pte)) { table_usage(pte, 1); } - if (!desc) { - table_usage(pte, -1); - } - /* Create (or erase) block/page descriptor */ + /* Create block/page descriptor */ set_pte_block_desc(pte, desc, level); - /* recursively free unused tables if any */ - while (level != BASE_XLAT_LEVEL && - is_table_unused(pte)) { - free_table(pte); - pte = ptes[--level]; - set_pte_block_desc(pte, 0, level); - table_usage(pte, -1); - } - move_on: virt += level_size; - desc += desc ? level_size : 0; + desc += level_size; size -= level_size; /* Range is mapped, start again for next range */ - table = ptables->base_xlat_table; + table = top_table; level = BASE_XLAT_LEVEL; } - return ret; + return 0; +} + +static void del_mapping(uint64_t *table, uintptr_t virt, size_t size, + unsigned int level) +{ + size_t step, level_size = 1ULL << LEVEL_TO_VA_SIZE_SHIFT(level); + uint64_t *pte, *subtable; + + for ( ; size; virt += step, size -= step) { + step = level_size - (virt & (level_size - 1)); + if (step > size) { + step = size; + } + pte = &table[XLAT_TABLE_VA_IDX(virt, level)]; + + if (is_free_desc(*pte)) { + continue; + } + + if (step != level_size && is_block_desc(*pte)) { + /* need to split this block mapping */ + expand_to_table(pte, level); + } + + if (is_table_desc(*pte, level)) { + subtable = pte_desc_table(*pte); + del_mapping(subtable, virt, step, level + 1); + if (!is_table_unused(subtable)) { + continue; + } + dec_table_ref(subtable); + } + + /* free this entry */ + *pte = 0; + table_usage(pte, -1); + } } #ifdef CONFIG_USERSPACE @@ -324,7 +417,7 @@ static int set_mapping(struct arm_mmu_ptables *ptables, static uint64_t *dup_table(uint64_t *src_table, unsigned int level) { uint64_t *dst_table = new_table(); - int i; + int i, usage_count = 0; if (!dst_table) { return NULL; @@ -347,13 +440,14 @@ static uint64_t *dup_table(uint64_t *src_table, unsigned int level) } dst_table[i] = src_table[i]; - if (is_table_desc(src_table[i], level)) { - table_usage(pte_desc_table(src_table[i]), 1); + if (is_table_desc(dst_table[i], level)) { + inc_table_ref(pte_desc_table(dst_table[i])); } if (!is_free_desc(dst_table[i])) { - table_usage(dst_table, 1); + usage_count++; } } + table_usage(dst_table, usage_count); return dst_table; } @@ -388,8 +482,7 @@ static int privatize_table(uint64_t *dst_table, uint64_t *src_table, return -ENOMEM; } set_pte_table_desc(&dst_table[i], dst_subtable, level); - table_usage(dst_subtable, 1); - table_usage(src_subtable, -1); + dec_table_ref(src_subtable); } ret = privatize_table(dst_subtable, src_subtable, @@ -433,18 +526,23 @@ static int privatize_page_range(struct arm_mmu_ptables *dst_pt, static void discard_table(uint64_t *table, unsigned int level) { unsigned int i; + int free_count = 0; for (i = 0U; i < Ln_XLAT_NUM_ENTRIES; i++) { if (is_table_desc(table[i], level)) { - table_usage(pte_desc_table(table[i]), -1); - discard_table(pte_desc_table(table[i]), level + 1); + uint64_t *subtable = pte_desc_table(table[i]); + + if (is_table_single_referenced(subtable)) { + discard_table(subtable, level + 1); + } + dec_table_ref(subtable); } if (!is_free_desc(table[i])) { table[i] = 0U; - table_usage(table, -1); + free_count++; } } - free_table(table); + table_usage(table, -free_count); } static int globalize_table(uint64_t *dst_table, uint64_t *src_table, @@ -466,6 +564,20 @@ static int globalize_table(uint64_t *dst_table, uint64_t *src_table, continue; } + if (is_free_desc(src_table[i]) && + is_table_desc(dst_table[i], level)) { + uint64_t *subtable = pte_desc_table(dst_table[i]); + + del_mapping(subtable, virt, step, level + 1); + if (is_table_unused(subtable)) { + /* unreference the empty table */ + dst_table[i] = 0; + table_usage(dst_table, -1); + dec_table_ref(subtable); + } + continue; + } + if (step != level_size) { /* boundary falls in the middle of this pte */ __ASSERT(is_table_desc(src_table[i], level), @@ -497,15 +609,15 @@ static int globalize_table(uint64_t *dst_table, uint64_t *src_table, table_usage(dst_table, -1); } if (is_table_desc(src_table[i], level)) { - table_usage(pte_desc_table(src_table[i]), 1); + inc_table_ref(pte_desc_table(src_table[i])); } dst_table[i] = src_table[i]; debug_show_pte(&dst_table[i], level); if (old_table) { /* we can discard the whole branch */ - table_usage(old_table, -1); discard_table(old_table, level + 1); + dec_table_ref(old_table); } } @@ -563,6 +675,8 @@ static uint64_t get_region_desc(uint32_t attrs) /* AP bits for Data access permission */ desc |= (attrs & MT_RW) ? PTE_BLOCK_DESC_AP_RW : PTE_BLOCK_DESC_AP_RO; + desc |= (IS_ENABLED(CONFIG_DEMAND_PAGING) && (attrs & MT_RW)) ? + PTE_SW_WRITABLE : 0; /* Mirror permissions to EL0 */ desc |= (attrs & MT_RW_AP_ELx) ? @@ -570,6 +684,11 @@ static uint64_t get_region_desc(uint32_t attrs) /* the access flag */ desc |= PTE_BLOCK_DESC_AF; + if (IS_ENABLED(CONFIG_DEMAND_PAGING) && (attrs & MT_PAGED_OUT) != 0) { + /* set it up for demand paging like arch_mem_page_out() */ + desc &= ~PTE_BLOCK_DESC_AF; + desc |= PTE_BLOCK_DESC_AP_RO; + } /* memory attribute index field */ mem_type = MT_TYPE(attrs); @@ -592,17 +711,20 @@ static uint64_t get_region_desc(uint32_t attrs) case MT_NORMAL_NC: case MT_NORMAL: /* Make Normal RW memory as execute never */ - if ((attrs & MT_RW) || (attrs & MT_P_EXECUTE_NEVER)) + if ((attrs & MT_RW) || (attrs & MT_P_EXECUTE_NEVER)) { desc |= PTE_BLOCK_DESC_PXN; + } if (((attrs & MT_RW) && (attrs & MT_RW_AP_ELx)) || - (attrs & MT_U_EXECUTE_NEVER)) + (attrs & MT_U_EXECUTE_NEVER)) { desc |= PTE_BLOCK_DESC_UXN; + } - if (mem_type == MT_NORMAL) + if (mem_type == MT_NORMAL) { desc |= PTE_BLOCK_DESC_INNER_SHARE; - else + } else { desc |= PTE_BLOCK_DESC_OUTER_SHARE; + } } /* non-Global bit */ @@ -625,7 +747,7 @@ static int __add_map(struct arm_mmu_ptables *ptables, const char *name, __ASSERT(((virt | phys | size) & (CONFIG_MMU_PAGE_SIZE - 1)) == 0, "address/size are not page aligned\n"); desc |= phys; - return set_mapping(ptables, virt, size, desc, may_overwrite); + return set_mapping(ptables->base_xlat_table, virt, size, desc, may_overwrite); } static int add_map(struct arm_mmu_ptables *ptables, const char *name, @@ -640,20 +762,18 @@ static int add_map(struct arm_mmu_ptables *ptables, const char *name, return ret; } -static int remove_map(struct arm_mmu_ptables *ptables, const char *name, - uintptr_t virt, size_t size) +static void remove_map(struct arm_mmu_ptables *ptables, const char *name, + uintptr_t virt, size_t size) { k_spinlock_key_t key; - int ret; MMU_DEBUG("unmmap [%s]: virt %lx size %lx\n", name, virt, size); __ASSERT(((virt | size) & (CONFIG_MMU_PAGE_SIZE - 1)) == 0, "address/size are not page aligned\n"); key = k_spin_lock(&xlat_lock); - ret = set_mapping(ptables, virt, size, 0, true); + del_mapping(ptables->base_xlat_table, virt, size, BASE_XLAT_LEVEL); k_spin_unlock(&xlat_lock, key); - return ret; } static void invalidate_tlb_all(void) @@ -663,6 +783,12 @@ static void invalidate_tlb_all(void) : : : "memory"); } +static inline void invalidate_tlb_page(uintptr_t virt) +{ + /* to be refined */ + invalidate_tlb_all(); +} + /* zephyr execution regions with appropriate attributes */ struct arm_mmu_flat_range { @@ -752,8 +878,9 @@ static void setup_page_tables(struct arm_mmu_ptables *ptables) uintptr_t max_va = 0, max_pa = 0; MMU_DEBUG("xlat tables:\n"); - for (index = 0U; index < CONFIG_MAX_XLAT_TABLES; index++) + for (index = 0U; index < CONFIG_MAX_XLAT_TABLES; index++) { MMU_DEBUG("%d: %p\n", index, xlat_tables + index * Ln_XLAT_NUM_ENTRIES); + } for (index = 0U; index < mmu_config.num_regions; index++) { region = &mmu_config.mmu_regions[index]; @@ -892,7 +1019,7 @@ void z_arm64_mm_init(bool is_primary_core) enable_mmu_el1(&kernel_ptables, flags); } -static void sync_domains(uintptr_t virt, size_t size) +static void sync_domains(uintptr_t virt, size_t size, const char *name) { #ifdef CONFIG_USERSPACE sys_snode_t *node; @@ -906,7 +1033,7 @@ static void sync_domains(uintptr_t virt, size_t size) domain = CONTAINER_OF(node, struct arch_mem_domain, node); domain_ptables = &domain->ptables; ret = globalize_page_range(domain_ptables, &kernel_ptables, - virt, size, "generic"); + virt, size, name); if (ret) { LOG_ERR("globalize_page_range() returned %d", ret); } @@ -975,6 +1102,10 @@ static int __arch_mem_map(void *virt, uintptr_t phys, size_t size, uint32_t flag entry_flags |= MT_RW_AP_ELx; } + if (IS_ENABLED(CONFIG_DEMAND_PAGING) && (flags & K_MEM_MAP_UNPAGED) != 0) { + entry_flags |= MT_PAGED_OUT; + } + return add_map(ptables, "generic", phys, (uintptr_t)virt, size, entry_flags); } @@ -988,7 +1119,7 @@ void arch_mem_map(void *virt, uintptr_t phys, size_t size, uint32_t flags) } else { uint32_t mem_flags = flags & K_MEM_CACHE_MASK; - sync_domains((uintptr_t)virt, size); + sync_domains((uintptr_t)virt, size, "mem_map"); invalidate_tlb_all(); switch (mem_flags) { @@ -1005,14 +1136,9 @@ void arch_mem_map(void *virt, uintptr_t phys, size_t size, uint32_t flags) void arch_mem_unmap(void *addr, size_t size) { - int ret = remove_map(&kernel_ptables, "generic", (uintptr_t)addr, size); - - if (ret) { - LOG_ERR("remove_map() returned %d", ret); - } else { - sync_domains((uintptr_t)addr, size); - invalidate_tlb_all(); - } + remove_map(&kernel_ptables, "generic", (uintptr_t)addr, size); + sync_domains((uintptr_t)addr, size, "mem_unmap"); + invalidate_tlb_all(); } int arch_page_phys_get(void *virt, uintptr_t *phys) @@ -1031,7 +1157,7 @@ int arch_page_phys_get(void *virt, uintptr_t *phys) } if (phys) { - *phys = par & GENMASK(47, 12); + *phys = par & GENMASK64(47, 12); } return 0; } @@ -1230,6 +1356,7 @@ static void z_arm64_swap_ptables(struct k_thread *incoming) return; /* Already the right tables */ } + MMU_DEBUG("TTBR0 switch from %#llx to %#llx\n", curr_ttbr0, new_ttbr0); z_arm64_set_ttbr0(new_ttbr0); if (get_asid(curr_ttbr0) == get_asid(new_ttbr0)) { @@ -1241,8 +1368,9 @@ void z_arm64_thread_mem_domains_init(struct k_thread *incoming) { struct arm_mmu_ptables *ptables; - if ((incoming->base.user_options & K_USER) == 0) + if ((incoming->base.user_options & K_USER) == 0) { return; + } ptables = incoming->arch.ptables; @@ -1258,3 +1386,311 @@ void z_arm64_swap_mem_domains(struct k_thread *incoming) } #endif /* CONFIG_USERSPACE */ + +#ifdef CONFIG_DEMAND_PAGING + +static uint64_t *get_pte_location(struct arm_mmu_ptables *ptables, + uintptr_t virt) +{ + uint64_t *pte; + uint64_t *table = ptables->base_xlat_table; + unsigned int level = BASE_XLAT_LEVEL; + + for (;;) { + pte = &table[XLAT_TABLE_VA_IDX(virt, level)]; + if (level == XLAT_LAST_LEVEL) { + return pte; + } + + if (is_table_desc(*pte, level)) { + level++; + table = pte_desc_table(*pte); + continue; + } + + /* anything else is unexpected */ + return NULL; + } +} + +void arch_mem_page_out(void *addr, uintptr_t location) +{ + uintptr_t virt = (uintptr_t)addr; + uint64_t *pte = get_pte_location(&kernel_ptables, virt); + uint64_t desc; + + __ASSERT(pte != NULL, ""); + desc = *pte; + + /* mark the entry invalid to the hardware */ + desc &= ~PTE_DESC_TYPE_MASK; + desc |= PTE_INVALID_DESC; + + /* store the location token in place of the physical address */ + __ASSERT((location & ~PTE_PHYSADDR_MASK) == 0, ""); + desc &= ~PTE_PHYSADDR_MASK; + desc |= location; + + /* + * The location token may be 0. Make sure the whole descriptor + * doesn't end up being zero as this would be seen as a free entry. + */ + desc |= PTE_BLOCK_DESC_AP_RO; + + *pte = desc; + MMU_DEBUG("page_out: virt=%#lx location=%#lx\n", virt, location); + debug_show_pte(pte, XLAT_LAST_LEVEL); + + sync_domains(virt, CONFIG_MMU_PAGE_SIZE, "page_out"); + invalidate_tlb_page(virt); +} + +void arch_mem_page_in(void *addr, uintptr_t phys) +{ + uintptr_t virt = (uintptr_t)addr; + uint64_t *pte = get_pte_location(&kernel_ptables, virt); + uint64_t desc; + + __ASSERT((phys & ~PTE_PHYSADDR_MASK) == 0, ""); + + __ASSERT(pte != NULL, ""); + desc = *pte; + __ASSERT(!is_free_desc(desc), ""); + + /* mark the entry valid again to the hardware */ + desc &= ~PTE_DESC_TYPE_MASK; + desc |= PTE_PAGE_DESC; + + /* store the physical address */ + desc &= ~PTE_PHYSADDR_MASK; + desc |= phys; + + /* mark as clean */ + desc |= PTE_BLOCK_DESC_AP_RO; + + /* and make it initially unaccessible to track unaccessed pages */ + desc &= ~PTE_BLOCK_DESC_AF; + + *pte = desc; + MMU_DEBUG("page_in: virt=%#lx phys=%#lx\n", virt, phys); + debug_show_pte(pte, XLAT_LAST_LEVEL); + + sync_domains(virt, CONFIG_MMU_PAGE_SIZE, "page_in"); + invalidate_tlb_page(virt); +} + +enum arch_page_location arch_page_location_get(void *addr, uintptr_t *location) +{ + uintptr_t virt = (uintptr_t)addr; + uint64_t *pte = get_pte_location(&kernel_ptables, virt); + uint64_t desc; + enum arch_page_location status; + + if (!pte) { + return ARCH_PAGE_LOCATION_BAD; + } + desc = *pte; + if (is_free_desc(desc)) { + return ARCH_PAGE_LOCATION_BAD; + } + + switch (desc & PTE_DESC_TYPE_MASK) { + case PTE_PAGE_DESC: + status = ARCH_PAGE_LOCATION_PAGED_IN; + break; + case PTE_INVALID_DESC: + status = ARCH_PAGE_LOCATION_PAGED_OUT; + break; + default: + return ARCH_PAGE_LOCATION_BAD; + } + + *location = desc & PTE_PHYSADDR_MASK; + return status; +} + +uintptr_t arch_page_info_get(void *addr, uintptr_t *phys, bool clear_accessed) +{ + uintptr_t virt = (uintptr_t)addr; + uint64_t *pte = get_pte_location(&kernel_ptables, virt); + uint64_t desc; + uintptr_t status = 0; + + if (!pte) { + return ARCH_DATA_PAGE_NOT_MAPPED; + } + desc = *pte; + if (is_free_desc(desc)) { + return ARCH_DATA_PAGE_NOT_MAPPED; + } + + switch (desc & PTE_DESC_TYPE_MASK) { + case PTE_PAGE_DESC: + status |= ARCH_DATA_PAGE_LOADED; + break; + case PTE_INVALID_DESC: + /* page not loaded */ + break; + default: + return ARCH_DATA_PAGE_NOT_MAPPED; + } + + if (phys) { + *phys = desc & PTE_PHYSADDR_MASK; + } + + if ((status & ARCH_DATA_PAGE_LOADED) == 0) { + return status; + } + + if ((desc & PTE_BLOCK_DESC_AF) != 0) { + status |= ARCH_DATA_PAGE_ACCESSED; + } + + if ((desc & PTE_BLOCK_DESC_AP_RO) == 0) { + status |= ARCH_DATA_PAGE_DIRTY; + } + + if (clear_accessed) { + desc &= ~PTE_BLOCK_DESC_AF; + *pte = desc; + MMU_DEBUG("page_info: virt=%#lx (clearing AF)\n", virt); + debug_show_pte(pte, XLAT_LAST_LEVEL); + sync_domains(virt, CONFIG_MMU_PAGE_SIZE, "unaccessible"); + invalidate_tlb_page(virt); + } + + return status; +} + +#define MT_SCRATCH (MT_NORMAL | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE) + +void arch_mem_scratch(uintptr_t phys) +{ + uintptr_t virt = (uintptr_t)K_MEM_SCRATCH_PAGE; + size_t size = CONFIG_MMU_PAGE_SIZE; + int ret = add_map(&kernel_ptables, "scratch", phys, virt, size, MT_SCRATCH); + + if (ret) { + LOG_ERR("add_map() returned %d", ret); + } else { + sync_domains(virt, size, "scratch"); + invalidate_tlb_page(virt); + } +} + +static bool do_mem_page_fault(struct arch_esf *esf, uintptr_t virt) +{ + /* + * The k_mem_page_fault() code expects to be called with IRQs enabled + * if the fault happened in a context where IRQs were enabled. + */ + if (arch_irq_unlocked(esf->spsr)) { + enable_irq(); + } + + bool ok = k_mem_page_fault((void *)virt); + + disable_irq(); + return ok; +} + +/* Called from the fault handler. Returns true if the fault is resolved. */ +bool z_arm64_do_demand_paging(struct arch_esf *esf, uint64_t esr, uint64_t far) +{ + uintptr_t virt = far; + uint64_t *pte, desc; + uintptr_t phys; + + /* filter relevant exceptions */ + switch (GET_ESR_EC(esr)) { + case 0x21: /* insn abort from current EL */ + case 0x25: /* data abort from current EL */ + break; + default: + return false; + } + + /* make sure the fault happened in the expected range */ + if (!IN_RANGE(virt, + (uintptr_t)K_MEM_VIRT_RAM_START, + ((uintptr_t)K_MEM_VIRT_RAM_END - 1))) { + return false; + } + + virt = ROUND_DOWN(virt, CONFIG_MMU_PAGE_SIZE); + + pte = get_pte_location(&kernel_ptables, virt); + if (!pte) { + /* page mapping doesn't exist, let the core code do its thing */ + return do_mem_page_fault(esf, virt); + } + desc = *pte; + if ((desc & PTE_DESC_TYPE_MASK) != PTE_PAGE_DESC) { + /* page is not loaded/mapped */ + return do_mem_page_fault(esf, virt); + } + + /* + * From this point, we expect only 2 cases: + * + * 1) the Access Flag was not set so we set it marking the page + * as accessed; + * + * 2) the page was read-only and a write occurred so we clear the + * RO flag marking the page dirty. + * + * We bail out on anything else. + * + * Fault status codes for Data aborts (DFSC): + * 0b0010LL Access flag fault + * 0b0011LL Permission fault + */ + uint32_t dfsc = GET_ESR_ISS(esr) & GENMASK(5, 0); + bool write = (GET_ESR_ISS(esr) & BIT(6)) != 0; /* WnR */ + + if (dfsc == (0b001000 | XLAT_LAST_LEVEL) && + (desc & PTE_BLOCK_DESC_AF) == 0) { + /* page is being accessed: set the access flag */ + desc |= PTE_BLOCK_DESC_AF; + if (write) { + if ((desc & PTE_SW_WRITABLE) == 0) { + /* we don't actually have write permission */ + return false; + } + /* + * Let's avoid another fault immediately after + * returning by making the page read-write right away + * effectively marking it "dirty" as well. + */ + desc &= ~PTE_BLOCK_DESC_AP_RO; + } + *pte = desc; + sync_domains(virt, CONFIG_MMU_PAGE_SIZE, "accessed"); + /* no TLB inval needed after setting AF */ + + /* tell the eviction algorithm about it */ + phys = desc & PTE_PHYSADDR_MASK; + k_mem_paging_eviction_accessed(phys); + return true; + } + + if (dfsc == (0b001100 | XLAT_LAST_LEVEL) && write && + (desc & PTE_BLOCK_DESC_AP_RO) != 0 && + (desc & PTE_SW_WRITABLE) != 0) { + /* make it "dirty" i.e. read-write */ + desc &= ~PTE_BLOCK_DESC_AP_RO; + *pte = desc; + sync_domains(virt, CONFIG_MMU_PAGE_SIZE, "dirtied"); + invalidate_tlb_page(virt); + + /* this also counts as an access refresh */ + phys = desc & PTE_PHYSADDR_MASK; + k_mem_paging_eviction_accessed(phys); + return true; + } + + return false; +} + +#endif /* CONFIG_DEMAND_PAGING */ diff --git a/arch/arm64/core/mmu.h b/arch/arm64/core/mmu.h index fa43a1fc9f6..47be42db635 100644 --- a/arch/arm64/core/mmu.h +++ b/arch/arm64/core/mmu.h @@ -93,3 +93,88 @@ #define DESC_ATTRS_LOWER_MASK GENMASK(11, 2) #define DESC_ATTRS_MASK (DESC_ATTRS_UPPER_MASK | DESC_ATTRS_LOWER_MASK) + +/* + * PTE descriptor can be Block descriptor or Table descriptor + * or Page descriptor. + */ +#define PTE_DESC_TYPE_MASK 3ULL +#define PTE_BLOCK_DESC 1ULL +#define PTE_TABLE_DESC 3ULL +#define PTE_PAGE_DESC 3ULL +#define PTE_INVALID_DESC 0ULL + +/* + * Block and Page descriptor attributes fields + */ +#define PTE_BLOCK_DESC_MEMTYPE(x) (x << 2) +#define PTE_BLOCK_DESC_NS (1ULL << 5) +#define PTE_BLOCK_DESC_AP_ELx (1ULL << 6) +#define PTE_BLOCK_DESC_AP_EL_HIGHER (0ULL << 6) +#define PTE_BLOCK_DESC_AP_RO (1ULL << 7) +#define PTE_BLOCK_DESC_AP_RW (0ULL << 7) +#define PTE_BLOCK_DESC_NON_SHARE (0ULL << 8) +#define PTE_BLOCK_DESC_OUTER_SHARE (2ULL << 8) +#define PTE_BLOCK_DESC_INNER_SHARE (3ULL << 8) +#define PTE_BLOCK_DESC_AF (1ULL << 10) +#define PTE_BLOCK_DESC_NG (1ULL << 11) +#define PTE_BLOCK_DESC_PXN (1ULL << 53) +#define PTE_BLOCK_DESC_UXN (1ULL << 54) + +/* + * Descriptor physical address field bits + */ +#define PTE_PHYSADDR_MASK GENMASK64(47, PAGE_SIZE_SHIFT) + +/* + * Descriptor bits 58 to 55 are defined as "Reserved for Software Use". + * + * When using demand paging, RW memory is marked RO to trap the first write + * for dirty page tracking. Bit 55 indicates if memory is actually writable. + */ +#define PTE_SW_WRITABLE (1ULL << 55) + +/* + * TCR definitions. + */ +#define TCR_EL1_IPS_SHIFT 32U +#define TCR_EL2_PS_SHIFT 16U +#define TCR_EL3_PS_SHIFT 16U + +#define TCR_T0SZ_SHIFT 0U +#define TCR_T0SZ(x) ((64 - (x)) << TCR_T0SZ_SHIFT) + +#define TCR_IRGN_NC (0ULL << 8) +#define TCR_IRGN_WBWA (1ULL << 8) +#define TCR_IRGN_WT (2ULL << 8) +#define TCR_IRGN_WBNWA (3ULL << 8) +#define TCR_IRGN_MASK (3ULL << 8) +#define TCR_ORGN_NC (0ULL << 10) +#define TCR_ORGN_WBWA (1ULL << 10) +#define TCR_ORGN_WT (2ULL << 10) +#define TCR_ORGN_WBNWA (3ULL << 10) +#define TCR_ORGN_MASK (3ULL << 10) +#define TCR_SHARED_NON (0ULL << 12) +#define TCR_SHARED_OUTER (2ULL << 12) +#define TCR_SHARED_INNER (3ULL << 12) +#define TCR_TG0_4K (0ULL << 14) +#define TCR_TG0_64K (1ULL << 14) +#define TCR_TG0_16K (2ULL << 14) +#define TCR_EPD1_DISABLE (1ULL << 23) +#define TCR_TG1_16K (1ULL << 30) +#define TCR_TG1_4K (2ULL << 30) +#define TCR_TG1_64K (3ULL << 30) + +#define TCR_PS_BITS_4GB 0x0ULL +#define TCR_PS_BITS_64GB 0x1ULL +#define TCR_PS_BITS_1TB 0x2ULL +#define TCR_PS_BITS_4TB 0x3ULL +#define TCR_PS_BITS_16TB 0x4ULL +#define TCR_PS_BITS_256TB 0x5ULL + +/* + * ARM guarantees at least 8 ASID bits. + * We may have more available, but do not make use of them for the time being. + */ +#define VM_ASID_BITS 8 +#define TTBR_ASID_SHIFT 48 diff --git a/arch/arm64/core/offsets/offsets.c b/arch/arm64/core/offsets/offsets.c index 4268692c498..772f0df3a8d 100644 --- a/arch/arm64/core/offsets/offsets.c +++ b/arch/arm64/core/offsets/offsets.c @@ -40,7 +40,7 @@ GEN_NAMED_OFFSET_SYM(_callee_saved_t, x27, x27_x28); GEN_NAMED_OFFSET_SYM(_callee_saved_t, x29, x29_sp_el0); GEN_NAMED_OFFSET_SYM(_callee_saved_t, sp_elx, sp_elx_lr); -#ifdef CONFIG_ARM64_ENABLE_FRAME_POINTER +#ifdef CONFIG_FRAME_POINTER GEN_NAMED_OFFSET_SYM(_esf_t, fp, fp); #endif diff --git a/arch/arm64/core/paging.h b/arch/arm64/core/paging.h new file mode 100644 index 00000000000..85e3ef7d33f --- /dev/null +++ b/arch/arm64/core/paging.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2024 BayLibre SAS + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef Z_ARM64_PAGING_H +#define Z_ARM64_PAGING_H + +bool z_arm64_do_demand_paging(struct arch_esf *esf, uint64_t esr, uint64_t far); + +#endif /* Z_ARM64_PAGING_H */ diff --git a/arch/arm64/core/prep_c.c b/arch/arm64/core/prep_c.c index bfd3b7c1eaa..11c7d2b112b 100644 --- a/arch/arm64/core/prep_c.c +++ b/arch/arm64/core/prep_c.c @@ -16,34 +16,13 @@ #include #include +#include +#include extern void z_arm64_mm_init(bool is_primary_core); __weak void z_arm64_mm_init(bool is_primary_core) { } -/* - * These simple memset/memcpy alternatives are necessary as the optimized - * ones depend on the MMU to be active (see commit c5b898743a20). - */ -void z_early_memset(void *dst, int c, size_t n) -{ - uint8_t *d = dst; - - while (n--) { - *d++ = c; - } -} - -void z_early_memcpy(void *dst, const void *src, size_t n) -{ - uint8_t *d = dst; - const uint8_t *s = src; - - while (n--) { - *d++ = *s++; - } -} - /** * * @brief Prepare to and run C code @@ -53,6 +32,10 @@ void z_early_memcpy(void *dst, const void *src, size_t n) */ void z_prep_c(void) { +#if defined(CONFIG_SOC_PREP_HOOK) + soc_prep_hook(); +#endif + /* Initialize tpidrro_el0 with our struct _cpu instance address */ write_tpidrro_el0((uintptr_t)&_kernel.cpus[0]); @@ -75,6 +58,9 @@ extern FUNC_NORETURN void arch_secondary_cpu_init(void); void z_arm64_secondary_prep_c(void) { arch_secondary_cpu_init(); +#if CONFIG_ARCH_CACHE + arch_cache_init(); +#endif CODE_UNREACHABLE; } diff --git a/arch/arm64/core/reboot.c b/arch/arm64/core/reboot.c new file mode 100644 index 00000000000..064b44f93bf --- /dev/null +++ b/arch/arm64/core/reboot.c @@ -0,0 +1,35 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); + +#ifdef CONFIG_PM_CPU_OPS_PSCI +void __weak sys_arch_reboot(int type) +{ + unsigned char reset_type; + + if (type == SYS_REBOOT_COLD) { + reset_type = SYS_COLD_RESET; + } else if (type == SYS_REBOOT_WARM) { + reset_type = SYS_WARM_RESET; + } else { + LOG_ERR("Invalid reboot type"); + return; + } + pm_system_reset(reset_type); +} +#else +void __weak sys_arch_reboot(int type) +{ + LOG_WRN("%s is not implemented", __func__); + ARG_UNUSED(type); +} +#endif diff --git a/arch/arm64/core/reset.S b/arch/arm64/core/reset.S index 5e406bea132..a01139ad700 100644 --- a/arch/arm64/core/reset.S +++ b/arch/arm64/core/reset.S @@ -7,7 +7,7 @@ #include #include #include -#include +#include #include "boot.h" #include "macro_priv.inc" diff --git a/arch/arm64/core/smp.c b/arch/arm64/core/smp.c index 8777c400766..bbb7f963431 100644 --- a/arch/arm64/core/smp.c +++ b/arch/arm64/core/smp.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -180,7 +181,7 @@ void arch_secondary_cpu_init(int cpu_num) #ifdef CONFIG_SMP -static void broadcast_ipi(unsigned int ipi) +static void send_ipi(unsigned int ipi, uint32_t cpu_bitmap) { uint64_t mpidr = MPIDR_TO_CORE(GET_MPIDR()); @@ -190,6 +191,10 @@ static void broadcast_ipi(unsigned int ipi) unsigned int num_cpus = arch_num_cpus(); for (int i = 0; i < num_cpus; i++) { + if ((cpu_bitmap & BIT(i)) == 0) { + continue; + } + uint64_t target_mpidr = cpu_map[i]; uint8_t aff0; @@ -209,10 +214,14 @@ void sched_ipi_handler(const void *unused) z_sched_ipi(); } -/* arch implementation of sched_ipi */ -void arch_sched_ipi(void) +void arch_sched_broadcast_ipi(void) +{ + send_ipi(SGI_SCHED_IPI, IPI_ALL_CPUS_MASK); +} + +void arch_sched_directed_ipi(uint32_t cpu_bitmap) { - broadcast_ipi(SGI_SCHED_IPI); + send_ipi(SGI_SCHED_IPI, cpu_bitmap); } #ifdef CONFIG_USERSPACE @@ -232,7 +241,7 @@ void mem_cfg_ipi_handler(const void *unused) void z_arm64_mem_cfg_ipi(void) { - broadcast_ipi(SGI_MMCFG_IPI); + send_ipi(SGI_MMCFG_IPI, IPI_ALL_CPUS_MASK); } #endif @@ -302,6 +311,5 @@ int arch_smp_init(void) return 0; } -SYS_INIT(arch_smp_init, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); #endif diff --git a/arch/arm64/core/thread.c b/arch/arm64/core/thread.c index a0269501c19..18f49945eda 100644 --- a/arch/arm64/core/thread.c +++ b/arch/arm64/core/thread.c @@ -87,7 +87,7 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, void *p1, void *p2, void *p3) { extern void z_arm64_exit_exc(void); - z_arch_esf_t *pInitCtx; + struct arch_esf *pInitCtx; /* * Clean the thread->arch to avoid unexpected behavior because the @@ -102,7 +102,7 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, * dropping into EL0. */ - pInitCtx = Z_STACK_PTR_TO_FRAME(struct __esf, stack_ptr); + pInitCtx = Z_STACK_PTR_TO_FRAME(struct arch_esf, stack_ptr); pInitCtx->x0 = (uint64_t)entry; pInitCtx->x1 = (uint64_t)p1; diff --git a/arch/arm64/core/vector_table.S b/arch/arm64/core/vector_table.S index 1a1b649d4f2..632304b7029 100644 --- a/arch/arm64/core/vector_table.S +++ b/arch/arm64/core/vector_table.S @@ -10,7 +10,7 @@ #include #include -#include +#include #include #include #include @@ -72,7 +72,7 @@ _ASM_FILE_PROLOGUE .endif #endif -#ifdef CONFIG_ARM64_ENABLE_FRAME_POINTER +#ifdef CONFIG_FRAME_POINTER str x29, [sp, ___esf_t_fp_OFFSET] #endif @@ -339,7 +339,7 @@ SECTION_FUNC(TEXT, z_arm64_exit_exc) ldp x16, x17, [sp, ___esf_t_x16_x17_OFFSET] ldp x18, lr, [sp, ___esf_t_x18_lr_OFFSET] -#ifdef CONFIG_ARM64_ENABLE_FRAME_POINTER +#ifdef CONFIG_FRAME_POINTER ldr x29, [sp, ___esf_t_fp_OFFSET] #endif diff --git a/arch/arm64/core/xen/CMakeLists.txt b/arch/arm64/core/xen/CMakeLists.txt index b0b573b7b9b..cbedb1204e1 100644 --- a/arch/arm64/core/xen/CMakeLists.txt +++ b/arch/arm64/core/xen/CMakeLists.txt @@ -4,8 +4,5 @@ # Needed to separate definitions in common Xen headers zephyr_compile_options($<$:-D__ASSEMBLY__>) -# Xen interface version used in headers for correct definition -zephyr_compile_options(-D__XEN_INTERFACE_VERSION__=0x00040e00) - zephyr_library_sources(hypercall.S) zephyr_library_sources(enlighten.c) diff --git a/arch/arm64/core/xen/Kconfig b/arch/arm64/core/xen/Kconfig index a4bb0be77e9..f860f9f1d4f 100644 --- a/arch/arm64/core/xen/Kconfig +++ b/arch/arm64/core/xen/Kconfig @@ -25,3 +25,11 @@ config XEN_DOM0LESS help Configures Zephyr as DomU, that can be started on Dom0less setup. + +config XEN_INTERFACE_VERSION + hex "Xen interface version" + default 0x00040e00 + depends on XEN + help + Xen interface version to use. This is the version of the + interface that Zephyr will use to communicate with the hypervisor. diff --git a/arch/arm64/core/xen/enlighten.c b/arch/arm64/core/xen/enlighten.c index 164947a09ff..91bf014b762 100644 --- a/arch/arm64/core/xen/enlighten.c +++ b/arch/arm64/core/xen/enlighten.c @@ -42,7 +42,7 @@ static int xen_map_shared_info(const shared_info_t *shared_page) return HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp); } -static int xen_enlighten_init(void) +int xen_enlighten_init(void) { int ret = 0; shared_info_t *info = (shared_info_t *) shared_info_buf; @@ -66,5 +66,3 @@ static int xen_enlighten_init(void) return 0; } - -SYS_INIT(xen_enlighten_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); diff --git a/arch/arm64/include/kernel_arch_data.h b/arch/arm64/include/kernel_arch_data.h index ec781fc902d..8b607c1dbf4 100644 --- a/arch/arm64/include/kernel_arch_data.h +++ b/arch/arm64/include/kernel_arch_data.h @@ -36,7 +36,7 @@ extern "C" { #endif -typedef struct __esf _esf_t; +typedef struct arch_esf _esf_t; typedef struct __basic_sf _basic_sf_t; #ifdef __cplusplus diff --git a/arch/arm64/include/kernel_arch_func.h b/arch/arm64/include/kernel_arch_func.h index a5c3d59d87a..d2c346be1f0 100644 --- a/arch/arm64/include/kernel_arch_func.h +++ b/arch/arm64/include/kernel_arch_func.h @@ -28,8 +28,13 @@ extern "C" { #ifndef _ASMLANGUAGE +extern void xen_enlighten_init(void); + static ALWAYS_INLINE void arch_kernel_init(void) { +#ifdef CONFIG_XEN + xen_enlighten_init(); +#endif } static inline void arch_switch(void *switch_to, void **switched_from) @@ -43,7 +48,7 @@ static inline void arch_switch(void *switch_to, void **switched_from) z_arm64_context_switch(new, old); } -extern void z_arm64_fatal_error(unsigned int reason, z_arch_esf_t *esf); +extern void z_arm64_fatal_error(unsigned int reason, struct arch_esf *esf); extern void z_arm64_set_ttbr0(uint64_t ttbr0); extern void z_arm64_mem_cfg_ipi(void); diff --git a/arch/arm64/include/offsets_short_arch.h b/arch/arm64/include/offsets_short_arch.h index abd93bba7ba..11dd5f64256 100644 --- a/arch/arm64/include/offsets_short_arch.h +++ b/arch/arm64/include/offsets_short_arch.h @@ -7,7 +7,7 @@ #ifndef ZEPHYR_ARCH_ARM64_INCLUDE_OFFSETS_SHORT_ARCH_H_ #define ZEPHYR_ARCH_ARM64_INCLUDE_OFFSETS_SHORT_ARCH_H_ -#include +#include #define _thread_offset_to_exception_depth \ (___thread_t_arch_OFFSET + ___thread_arch_t_exception_depth_OFFSET) diff --git a/arch/common/CMakeLists.txt b/arch/common/CMakeLists.txt index 78fc6396ed6..48685151ab1 100644 --- a/arch/common/CMakeLists.txt +++ b/arch/common/CMakeLists.txt @@ -17,11 +17,18 @@ if(CONFIG_GEN_ISR_TABLES) ) endif() +zephyr_library_sources_ifdef( + CONFIG_ISR_TABLE_SHELL + isr_tables_shell.c +) + zephyr_library_sources_ifdef( CONFIG_MULTI_LEVEL_INTERRUPTS multilevel_irq.c ) +zephyr_library_sources_ifdef(CONFIG_LEGACY_MULTI_LEVEL_TABLE_GENERATION multilevel_irq_legacy.c) + zephyr_library_sources_ifdef(CONFIG_SHARED_INTERRUPTS shared_irq.c) if(NOT CONFIG_ARCH_HAS_TIMING_FUNCTIONS AND diff --git a/arch/common/Kconfig b/arch/common/Kconfig index aabc599a4d5..2dcf2f5791b 100644 --- a/arch/common/Kconfig +++ b/arch/common/Kconfig @@ -15,3 +15,25 @@ config SEMIHOST https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc This option is compatible with hardware and with QEMU, through the (automatic) use of the -semihosting-config switch when invoking it. + +config LEGACY_MULTI_LEVEL_TABLE_GENERATION + bool "Auto generates the multi-level interrupt LUT (deprecated)" + default y + select DEPRECATED + depends on MULTI_LEVEL_INTERRUPTS + depends on !PLIC + depends on !NXP_IRQSTEER + depends on !RV32M1_INTMUX + depends on !CAVS_ICTL + depends on !DW_ICTL_ACE + depends on !DW_ICTL + help + A make-shift Kconfig to continue generating the multi-level interrupt LUT + with the legacy way using DT macros. + +config ISR_TABLE_SHELL + bool "Shell command to dump the ISR tables" + depends on GEN_SW_ISR_TABLE + depends on SHELL + help + This option enables a shell command to dump the ISR tables. diff --git a/arch/common/isr_tables.c b/arch/common/isr_tables.c index 050597b7b1d..183f80738fe 100644 --- a/arch/common/isr_tables.c +++ b/arch/common/isr_tables.c @@ -15,11 +15,11 @@ struct int_list_header { uint32_t table_size; uint32_t offset; -#if IS_ENABLED(CONFIG_ISR_TABLES_LOCAL_DECLARATION) +#if defined(CONFIG_ISR_TABLES_LOCAL_DECLARATION) uint32_t swi_table_entry_size; uint32_t shared_isr_table_entry_size; uint32_t shared_isr_client_num_offset; -#endif /* IS_ENABLED(CONFIG_ISR_TABLES_LOCAL_DECLARATION) */ +#endif /* defined(CONFIG_ISR_TABLES_LOCAL_DECLARATION) */ }; /* These values are not included in the resulting binary, but instead form the @@ -29,13 +29,13 @@ struct int_list_header { Z_GENERIC_SECTION(.irq_info) __used struct int_list_header _iheader = { .table_size = IRQ_TABLE_SIZE, .offset = CONFIG_GEN_IRQ_START_VECTOR, -#if IS_ENABLED(CONFIG_ISR_TABLES_LOCAL_DECLARATION) +#if defined(CONFIG_ISR_TABLES_LOCAL_DECLARATION) .swi_table_entry_size = sizeof(struct _isr_table_entry), -#if IS_ENABLED(CONFIG_SHARED_INTERRUPTS) +#if defined(CONFIG_SHARED_INTERRUPTS) .shared_isr_table_entry_size = sizeof(struct z_shared_isr_table_entry), .shared_isr_client_num_offset = offsetof(struct z_shared_isr_table_entry, client_num), -#endif /* IS_ENABLED(CONFIG_SHARED_INTERRUPTS) */ -#endif /* IS_ENABLED(CONFIG_ISR_TABLES_LOCAL_DECLARATION) */ +#endif /* defined(CONFIG_SHARED_INTERRUPTS) */ +#endif /* defined(CONFIG_ISR_TABLES_LOCAL_DECLARATION) */ }; /* These are placeholder tables. They will be replaced by the real tables @@ -90,7 +90,7 @@ uintptr_t __irq_vector_table _irq_vector_table[IRQ_TABLE_SIZE] = { #ifdef CONFIG_GEN_SW_ISR_TABLE struct _isr_table_entry __sw_isr_table _sw_isr_table[IRQ_TABLE_SIZE] = { [0 ...(IRQ_TABLE_SIZE - 1)] = {(const void *)0x42, - (void *)&z_irq_spurious}, + &z_irq_spurious}, }; #endif diff --git a/arch/common/isr_tables_shell.c b/arch/common/isr_tables_shell.c new file mode 100644 index 00000000000..232878f2b29 --- /dev/null +++ b/arch/common/isr_tables_shell.c @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2024 Meta Platforms. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +static void dump_isr_table_entry(const struct shell *sh, int idx, struct _isr_table_entry *entry) +{ + + if ((entry->isr == z_irq_spurious) || (entry->isr == NULL)) { + return; + } +#ifdef CONFIG_SYMTAB + const char *name = symtab_find_symbol_name((uintptr_t)entry->isr, NULL); + + shell_print(sh, "%4d: %s(%p)", idx, name, entry->arg); +#else + shell_print(sh, "%4d: %p(%p)", idx, entry->isr, entry->arg); +#endif /* CONFIG_SYMTAB */ +} + +static int cmd_sw_isr_table(const struct shell *sh, size_t argc, char **argv) +{ + shell_print(sh, "_sw_isr_table[%d]\n", IRQ_TABLE_SIZE); + + for (int idx = 0; idx < IRQ_TABLE_SIZE; idx++) { + dump_isr_table_entry(sh, idx, &_sw_isr_table[idx]); + } + + return 0; +} + +#ifdef CONFIG_SHARED_INTERRUPTS +static int cmd_shared_sw_isr_table(const struct shell *sh, size_t argc, char **argv) +{ + shell_print(sh, "z_shared_sw_isr_table[%d][%d]\n", IRQ_TABLE_SIZE, + CONFIG_SHARED_IRQ_MAX_NUM_CLIENTS); + + for (int idx = 0; idx < IRQ_TABLE_SIZE; idx++) { + for (int c = 0; c < z_shared_sw_isr_table[idx].client_num; c++) { + dump_isr_table_entry(sh, idx, &z_shared_sw_isr_table[idx].clients[c]); + } + } + + return 0; +} +#endif /* CONFIG_SHARED_INTERRUPTS */ + +SHELL_STATIC_SUBCMD_SET_CREATE(isr_table_cmds, + SHELL_CMD_ARG(sw_isr_table, NULL, + "Dump _sw_isr_table.\n" + "Usage: isr_table sw_isr_table", + cmd_sw_isr_table, 1, 0), +#ifdef CONFIG_SHARED_INTERRUPTS + SHELL_CMD_ARG(shared_sw_isr_table, NULL, + "Dump z_shared_sw_isr_table.\n" + "Usage: isr_table shared_sw_isr_table", + cmd_shared_sw_isr_table, 1, 0), +#endif /* CONFIG_SHARED_INTERRUPTS */ + SHELL_SUBCMD_SET_END); + +SHELL_CMD_ARG_REGISTER(isr_table, &isr_table_cmds, "ISR tables shell command", + NULL, 0, 0); diff --git a/arch/common/multilevel_irq.c b/arch/common/multilevel_irq.c index 53f8e03a4d8..55bd3b277f0 100644 --- a/arch/common/multilevel_irq.c +++ b/arch/common/multilevel_irq.c @@ -11,172 +11,85 @@ #include #include -BUILD_ASSERT((CONFIG_NUM_2ND_LEVEL_AGGREGATORS * CONFIG_MAX_IRQ_PER_AGGREGATOR) <= - BIT(CONFIG_2ND_LEVEL_INTERRUPT_BITS), +BUILD_ASSERT(CONFIG_MAX_IRQ_PER_AGGREGATOR < BIT(CONFIG_2ND_LEVEL_INTERRUPT_BITS), "L2 bits not enough to cover the number of L2 IRQs"); - -/* - * Insert code if the node_id is an interrupt controller - */ -#define Z_IF_DT_IS_INTC(node_id, code) \ - IF_ENABLED(DT_NODE_HAS_PROP(node_id, interrupt_controller), (code)) - -/* - * Expands to node_id if its IRQN is equal to `_irq`, nothing otherwise - * This only works for `_irq` between 0 & 4095, see `IS_EQ` - */ -#define Z_IF_DT_INTC_IRQN_EQ(node_id, _irq) IF_ENABLED(IS_EQ(DT_IRQ(node_id, irq), _irq), (node_id)) - -/* - * Expands to node_id if it's an interrupt controller & its IRQN is `irq`, or nothing otherwise - */ -#define Z_DT_INTC_GET_IRQN(node_id, _irq) \ - Z_IF_DT_IS_INTC(node_id, Z_IF_DT_INTC_IRQN_EQ(node_id, _irq)) - -/** - * Loop through child of "/soc" and get root interrupt controllers with `_irq` as IRQN, - * this assumes only one device has the IRQN - * @param _irq irq number - * @return node_id(s) that has the `_irq` number, or empty if none of them has the `_irq` - */ -#define INTC_DT_IRQN_GET(_irq) \ - DT_FOREACH_CHILD_STATUS_OKAY_VARGS(DT_PATH(soc), Z_DT_INTC_GET_IRQN, _irq) - -/* If can't find any matching interrupt controller, fills with `NULL` */ -#define INTC_DEVICE_INIT(node_id) .dev = DEVICE_DT_GET_OR_NULL(node_id), - -#define INIT_IRQ_PARENT_OFFSET(d, i, o) { \ - INTC_DEVICE_INIT(d) \ - .irq = i, \ - .offset = o, \ -} - -#define IRQ_INDEX_TO_OFFSET(i, base) (base + i * CONFIG_MAX_IRQ_PER_AGGREGATOR) - -#define CAT_2ND_LVL_LIST(i, base) \ - INIT_IRQ_PARENT_OFFSET(INTC_DT_IRQN_GET(CONFIG_2ND_LVL_INTR_0##i##_OFFSET), \ - CONFIG_2ND_LVL_INTR_0##i##_OFFSET, IRQ_INDEX_TO_OFFSET(i, base)) -const struct _irq_parent_entry _lvl2_irq_list[CONFIG_NUM_2ND_LEVEL_AGGREGATORS] - = { LISTIFY(CONFIG_NUM_2ND_LEVEL_AGGREGATORS, CAT_2ND_LVL_LIST, (,), - CONFIG_2ND_LVL_ISR_TBL_OFFSET) }; - #ifdef CONFIG_3RD_LEVEL_INTERRUPTS - -BUILD_ASSERT((CONFIG_NUM_3RD_LEVEL_AGGREGATORS * CONFIG_MAX_IRQ_PER_AGGREGATOR) <= - BIT(CONFIG_3RD_LEVEL_INTERRUPT_BITS), +BUILD_ASSERT(CONFIG_MAX_IRQ_PER_AGGREGATOR < BIT(CONFIG_3RD_LEVEL_INTERRUPT_BITS), "L3 bits not enough to cover the number of L3 IRQs"); - -#define CAT_3RD_LVL_LIST(i, base) \ - INIT_IRQ_PARENT_OFFSET(INTC_DT_IRQN_GET(CONFIG_3RD_LVL_INTR_0##i##_OFFSET), \ - CONFIG_3RD_LVL_INTR_0##i##_OFFSET, IRQ_INDEX_TO_OFFSET(i, base)) - -const struct _irq_parent_entry _lvl3_irq_list[CONFIG_NUM_3RD_LEVEL_AGGREGATORS] - = { LISTIFY(CONFIG_NUM_3RD_LEVEL_AGGREGATORS, CAT_3RD_LVL_LIST, (,), - CONFIG_3RD_LVL_ISR_TBL_OFFSET) }; - #endif /* CONFIG_3RD_LEVEL_INTERRUPTS */ -static const struct _irq_parent_entry *get_parent_entry(unsigned int parent_irq, - const struct _irq_parent_entry list[], - unsigned int length) +/** + * @brief Get the aggregator that's responsible for the given irq + * + * @param irq IRQ number to query + * + * @return Aggregator entry, NULL if irq is level 1 or not found. + */ +static const struct _irq_parent_entry *get_intc_entry_for_irq(unsigned int irq) { - unsigned int i; - const struct _irq_parent_entry *entry = NULL; + const unsigned int level = irq_get_level(irq); - for (i = 0U; i < length; ++i) { - if (list[i].irq == parent_irq) { - entry = &list[i]; - break; - } + /* 1st level aggregator is not registered */ + if (level == 1) { + return NULL; } - __ASSERT(i != length, "Invalid argument: %i", parent_irq); + const unsigned int intc_irq = irq_get_intc_irq(irq); + + /* Find an aggregator entry that matches the level & intc_irq */ + STRUCT_SECTION_FOREACH_ALTERNATE(intc_table, _irq_parent_entry, intc) { + if ((intc->level == level) && (intc->irq == intc_irq)) { + return intc; + } + } - return entry; + return NULL; } const struct device *z_get_sw_isr_device_from_irq(unsigned int irq) { - const struct device *dev = NULL; - unsigned int level, parent_irq; - const struct _irq_parent_entry *entry = NULL; - - level = irq_get_level(irq); + const struct _irq_parent_entry *intc = get_intc_entry_for_irq(irq); - if (level == 2U) { - parent_irq = irq_parent_level_2(irq); - entry = get_parent_entry(parent_irq, - _lvl2_irq_list, - CONFIG_NUM_2ND_LEVEL_AGGREGATORS); - } -#ifdef CONFIG_3RD_LEVEL_INTERRUPTS - else if (level == 3U) { - parent_irq = irq_parent_level_3(irq); - entry = get_parent_entry(parent_irq, - _lvl3_irq_list, - CONFIG_NUM_3RD_LEVEL_AGGREGATORS); - } -#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */ - dev = entry != NULL ? entry->dev : NULL; + __ASSERT(intc != NULL, "can't find an aggregator to handle irq(%X)", irq); - return dev; + return intc != NULL ? intc->dev : NULL; } unsigned int z_get_sw_isr_irq_from_device(const struct device *dev) { - for (size_t i = 0U; i < CONFIG_NUM_2ND_LEVEL_AGGREGATORS; ++i) { - if (_lvl2_irq_list[i].dev == dev) { - return _lvl2_irq_list[i].irq; + /* Get the IRQN for the aggregator */ + STRUCT_SECTION_FOREACH_ALTERNATE(intc_table, _irq_parent_entry, intc) { + if (intc->dev == dev) { + return intc->irq; } } -#ifdef CONFIG_3RD_LEVEL_INTERRUPTS - for (size_t i = 0U; i < CONFIG_NUM_3RD_LEVEL_AGGREGATORS; ++i) { - if (_lvl3_irq_list[i].dev == dev) { - return _lvl3_irq_list[i].irq; - } - } -#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */ + __ASSERT(false, "dev(%p) not found", dev); return 0; } unsigned int z_get_sw_isr_table_idx(unsigned int irq) { - unsigned int table_idx, level, parent_irq, local_irq, parent_offset; - const struct _irq_parent_entry *entry = NULL; - - level = irq_get_level(irq); + unsigned int table_idx, local_irq; + const struct _irq_parent_entry *intc = get_intc_entry_for_irq(irq); + const unsigned int level = irq_get_level(irq); - if (level == 2U) { - local_irq = irq_from_level_2(irq); + if (intc != NULL) { + local_irq = irq_from_level(irq, level); __ASSERT_NO_MSG(local_irq < CONFIG_MAX_IRQ_PER_AGGREGATOR); - parent_irq = irq_parent_level_2(irq); - entry = get_parent_entry(parent_irq, - _lvl2_irq_list, - CONFIG_NUM_2ND_LEVEL_AGGREGATORS); - parent_offset = entry != NULL ? entry->offset : 0U; - table_idx = parent_offset + local_irq; - } -#ifdef CONFIG_3RD_LEVEL_INTERRUPTS - else if (level == 3U) { - local_irq = irq_from_level_3(irq); - __ASSERT_NO_MSG(local_irq < CONFIG_MAX_IRQ_PER_AGGREGATOR); - parent_irq = irq_parent_level_3(irq); - entry = get_parent_entry(parent_irq, - _lvl3_irq_list, - CONFIG_NUM_3RD_LEVEL_AGGREGATORS); - parent_offset = entry != NULL ? entry->offset : 0U; - table_idx = parent_offset + local_irq; - } -#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */ - else { + + table_idx = intc->offset + local_irq; + } else { + /* irq level must be 1 if no intc entry */ + __ASSERT(level == 1, "can't find an aggregator to handle irq(%X)", irq); table_idx = irq; } table_idx -= CONFIG_GEN_IRQ_START_VECTOR; - __ASSERT_NO_MSG(table_idx < IRQ_TABLE_SIZE); + __ASSERT(table_idx < IRQ_TABLE_SIZE, "table_idx(%d) < IRQ_TABLE_SIZE(%d)", table_idx, + IRQ_TABLE_SIZE); return table_idx; } diff --git a/arch/common/multilevel_irq_legacy.c b/arch/common/multilevel_irq_legacy.c new file mode 100644 index 00000000000..dd4fe68b5ac --- /dev/null +++ b/arch/common/multilevel_irq_legacy.c @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2018 Intel Corporation. + * Copyright (c) 2024 Meta. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/** + * @file + * @brief This file houses the deprecated legacy macros-generated multi-level interrupt lookup + * table code, compiled when `CONFIG_LEGACY_MULTI_LEVEL_TABLE_GENERATION` is enabled. + */ + +/* + * Insert code if the node_id is an interrupt controller + */ +#define Z_IF_DT_IS_INTC(node_id, code) \ + IF_ENABLED(DT_NODE_HAS_PROP(node_id, interrupt_controller), (code)) + +/* + * Expands to node_id if its IRQN is equal to `_irq`, nothing otherwise + * This only works for `_irq` between 0 & 4095, see `IS_EQ` + */ +#define Z_IF_DT_INTC_IRQN_EQ(node_id, _irq) IF_ENABLED(IS_EQ(DT_IRQ(node_id, irq), _irq), (node_id)) + +/* + * Expands to node_id if it's an interrupt controller & its IRQN is `irq`, or nothing otherwise + */ +#define Z_DT_INTC_GET_IRQN(node_id, _irq) \ + Z_IF_DT_IS_INTC(node_id, Z_IF_DT_INTC_IRQN_EQ(node_id, _irq)) + +/** + * Loop through child of "/soc" and get root interrupt controllers with `_irq` as IRQN, + * this assumes only one device has the IRQN + * @param _irq irq number + * @return node_id(s) that has the `_irq` number, or empty if none of them has the `_irq` + */ +#define INTC_DT_IRQN_GET(_irq) \ + DT_FOREACH_CHILD_STATUS_OKAY_VARGS(DT_PATH(soc), Z_DT_INTC_GET_IRQN, _irq) + +#define INIT_IRQ_PARENT_OFFSET_2ND(n, d, i, o) \ + IRQ_PARENT_ENTRY_DEFINE(intc_l2_##n, DEVICE_DT_GET_OR_NULL(d), i, o, 2) + +#define IRQ_INDEX_TO_OFFSET(i, base) (base + i * CONFIG_MAX_IRQ_PER_AGGREGATOR) + +#define CAT_2ND_LVL_LIST(i, base) \ + INIT_IRQ_PARENT_OFFSET_2ND(i, INTC_DT_IRQN_GET(CONFIG_2ND_LVL_INTR_0##i##_OFFSET), \ + CONFIG_2ND_LVL_INTR_0##i##_OFFSET, \ + IRQ_INDEX_TO_OFFSET(i, base)) + +LISTIFY(CONFIG_NUM_2ND_LEVEL_AGGREGATORS, CAT_2ND_LVL_LIST, (;), CONFIG_2ND_LVL_ISR_TBL_OFFSET); + +#ifdef CONFIG_3RD_LEVEL_INTERRUPTS + +BUILD_ASSERT((CONFIG_NUM_3RD_LEVEL_AGGREGATORS * CONFIG_MAX_IRQ_PER_AGGREGATOR) <= + BIT(CONFIG_3RD_LEVEL_INTERRUPT_BITS), + "L3 bits not enough to cover the number of L3 IRQs"); + +#define INIT_IRQ_PARENT_OFFSET_3RD(n, d, i, o) \ + IRQ_PARENT_ENTRY_DEFINE(intc_l3_##n, DEVICE_DT_GET_OR_NULL(d), i, o, 3) + +#define CAT_3RD_LVL_LIST(i, base) \ + INIT_IRQ_PARENT_OFFSET_3RD(i, INTC_DT_IRQN_GET(CONFIG_3RD_LVL_INTR_0##i##_OFFSET), \ + CONFIG_3RD_LVL_INTR_0##i##_OFFSET, \ + IRQ_INDEX_TO_OFFSET(i, base)) + +LISTIFY(CONFIG_NUM_3RD_LEVEL_AGGREGATORS, CAT_3RD_LVL_LIST, (;), CONFIG_3RD_LVL_ISR_TBL_OFFSET); + +#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */ diff --git a/arch/common/nocache.ld b/arch/common/nocache.ld index a4e500e8b17..24e81cdefcf 100644 --- a/arch/common/nocache.ld +++ b/arch/common/nocache.ld @@ -7,6 +7,12 @@ /* Copied from linker.ld */ +#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_nocache_ram), okay) +#define NOCACHE_REGION LINKER_DT_NODE_REGION_NAME_TOKEN(DT_CHOSEN(zephyr_nocache_ram)) +#else +#define NOCACHE_REGION RAMABLE_REGION +#endif + /* Non-cached region of RAM */ SECTION_DATA_PROLOGUE(_NOCACHE_SECTION_NAME,(NOLOAD),) { @@ -27,5 +33,5 @@ SECTION_DATA_PROLOGUE(_NOCACHE_SECTION_NAME,(NOLOAD),) MPU_ALIGN(_nocache_ram_size); #endif _nocache_ram_end = .; -} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) +} GROUP_DATA_LINK_IN(NOCACHE_REGION, NOCACHE_REGION) _nocache_ram_size = _nocache_ram_end - _nocache_ram_start; diff --git a/arch/common/shared_irq.c b/arch/common/shared_irq.c index b4226ba7205..56c8d0cbc7d 100644 --- a/arch/common/shared_irq.c +++ b/arch/common/shared_irq.c @@ -92,8 +92,8 @@ void z_isr_install(unsigned int irq, void (*routine)(const void *), for (i = 0; i < shared_entry->client_num; i++) { client = &shared_entry->clients[i]; - __ASSERT(client->isr != routine && client->arg != param, - "trying to register duplicate ISR/arg pair"); + __ASSERT((client->isr == routine && client->arg == param) == false, + "ISR/arg combination is already registered"); } shared_entry->clients[shared_entry->client_num].isr = routine; diff --git a/arch/mips/core/cpu_idle.c b/arch/mips/core/cpu_idle.c index d91a6b3ce4b..fd6621284a5 100644 --- a/arch/mips/core/cpu_idle.c +++ b/arch/mips/core/cpu_idle.c @@ -19,12 +19,16 @@ static ALWAYS_INLINE void mips_idle(unsigned int key) __asm__ volatile("wait"); } +#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_IDLE void arch_cpu_idle(void) { mips_idle(1); } +#endif +#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE void arch_cpu_atomic_idle(unsigned int key) { mips_idle(key); } +#endif diff --git a/arch/mips/core/fatal.c b/arch/mips/core/fatal.c index 16011241666..a53e5bb0f5e 100644 --- a/arch/mips/core/fatal.c +++ b/arch/mips/core/fatal.c @@ -9,7 +9,7 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); FUNC_NORETURN void z_mips_fatal_error(unsigned int reason, - const z_arch_esf_t *esf) + const struct arch_esf *esf) { #ifdef CONFIG_EXCEPTION_DEBUG if (esf != NULL) { @@ -84,7 +84,7 @@ static char *cause_str(unsigned long cause) } } -void _Fault(z_arch_esf_t *esf) +void _Fault(struct arch_esf *esf) { unsigned long cause; diff --git a/arch/mips/core/irq_offload.c b/arch/mips/core/irq_offload.c index 2a62ae071e0..5c85ada4d61 100644 --- a/arch/mips/core/irq_offload.c +++ b/arch/mips/core/irq_offload.c @@ -48,3 +48,7 @@ void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) irq_unlock(key); } + +void arch_irq_offload_init(void) +{ +} diff --git a/arch/mips/core/isr.S b/arch/mips/core/isr.S index 44babb2149b..86d05d19833 100644 --- a/arch/mips/core/isr.S +++ b/arch/mips/core/isr.S @@ -14,7 +14,7 @@ #include #include -#define ESF_O(FIELD) __z_arch_esf_t_##FIELD##_OFFSET +#define ESF_O(FIELD) __struct_arch_esf_##FIELD##_OFFSET #define THREAD_O(FIELD) _thread_offset_to_##FIELD /* Convenience macros for loading/storing register states. */ @@ -58,12 +58,12 @@ op v1, ESF_O(v1)(sp) ; #define STORE_CALLER_SAVED() \ - addi sp, sp, -__z_arch_esf_t_SIZEOF ;\ + addi sp, sp, -__struct_arch_esf_SIZEOF ;\ DO_CALLER_SAVED(OP_STOREREG) ; #define LOAD_CALLER_SAVED() \ DO_CALLER_SAVED(OP_LOADREG) ;\ - addi sp, sp, __z_arch_esf_t_SIZEOF ; + addi sp, sp, __struct_arch_esf_SIZEOF ; /* imports */ GTEXT(_Fault) diff --git a/arch/mips/core/offsets/offsets.c b/arch/mips/core/offsets/offsets.c index 24b477e9558..c70ce3c39fc 100644 --- a/arch/mips/core/offsets/offsets.c +++ b/arch/mips/core/offsets/offsets.c @@ -23,32 +23,32 @@ GEN_OFFSET_SYM(_callee_saved_t, s6); GEN_OFFSET_SYM(_callee_saved_t, s7); GEN_OFFSET_SYM(_callee_saved_t, s8); -GEN_OFFSET_SYM(z_arch_esf_t, ra); -GEN_OFFSET_SYM(z_arch_esf_t, gp); -GEN_OFFSET_SYM(z_arch_esf_t, t0); -GEN_OFFSET_SYM(z_arch_esf_t, t1); -GEN_OFFSET_SYM(z_arch_esf_t, t2); -GEN_OFFSET_SYM(z_arch_esf_t, t3); -GEN_OFFSET_SYM(z_arch_esf_t, t4); -GEN_OFFSET_SYM(z_arch_esf_t, t5); -GEN_OFFSET_SYM(z_arch_esf_t, t6); -GEN_OFFSET_SYM(z_arch_esf_t, t7); -GEN_OFFSET_SYM(z_arch_esf_t, t8); -GEN_OFFSET_SYM(z_arch_esf_t, t9); -GEN_OFFSET_SYM(z_arch_esf_t, a0); -GEN_OFFSET_SYM(z_arch_esf_t, a1); -GEN_OFFSET_SYM(z_arch_esf_t, a2); -GEN_OFFSET_SYM(z_arch_esf_t, a3); -GEN_OFFSET_SYM(z_arch_esf_t, v0); -GEN_OFFSET_SYM(z_arch_esf_t, v1); -GEN_OFFSET_SYM(z_arch_esf_t, at); -GEN_OFFSET_SYM(z_arch_esf_t, epc); -GEN_OFFSET_SYM(z_arch_esf_t, badvaddr); -GEN_OFFSET_SYM(z_arch_esf_t, hi); -GEN_OFFSET_SYM(z_arch_esf_t, lo); -GEN_OFFSET_SYM(z_arch_esf_t, status); -GEN_OFFSET_SYM(z_arch_esf_t, cause); +GEN_OFFSET_STRUCT(arch_esf, ra); +GEN_OFFSET_STRUCT(arch_esf, gp); +GEN_OFFSET_STRUCT(arch_esf, t0); +GEN_OFFSET_STRUCT(arch_esf, t1); +GEN_OFFSET_STRUCT(arch_esf, t2); +GEN_OFFSET_STRUCT(arch_esf, t3); +GEN_OFFSET_STRUCT(arch_esf, t4); +GEN_OFFSET_STRUCT(arch_esf, t5); +GEN_OFFSET_STRUCT(arch_esf, t6); +GEN_OFFSET_STRUCT(arch_esf, t7); +GEN_OFFSET_STRUCT(arch_esf, t8); +GEN_OFFSET_STRUCT(arch_esf, t9); +GEN_OFFSET_STRUCT(arch_esf, a0); +GEN_OFFSET_STRUCT(arch_esf, a1); +GEN_OFFSET_STRUCT(arch_esf, a2); +GEN_OFFSET_STRUCT(arch_esf, a3); +GEN_OFFSET_STRUCT(arch_esf, v0); +GEN_OFFSET_STRUCT(arch_esf, v1); +GEN_OFFSET_STRUCT(arch_esf, at); +GEN_OFFSET_STRUCT(arch_esf, epc); +GEN_OFFSET_STRUCT(arch_esf, badvaddr); +GEN_OFFSET_STRUCT(arch_esf, hi); +GEN_OFFSET_STRUCT(arch_esf, lo); +GEN_OFFSET_STRUCT(arch_esf, status); +GEN_OFFSET_STRUCT(arch_esf, cause); -GEN_ABSOLUTE_SYM(__z_arch_esf_t_SIZEOF, STACK_ROUND_UP(sizeof(z_arch_esf_t))); +GEN_ABSOLUTE_SYM(__struct_arch_esf_SIZEOF, STACK_ROUND_UP(sizeof(struct arch_esf))); GEN_ABS_SYM_END diff --git a/arch/mips/core/prep_c.c b/arch/mips/core/prep_c.c index 19673273b8a..0247f90df62 100644 --- a/arch/mips/core/prep_c.c +++ b/arch/mips/core/prep_c.c @@ -11,6 +11,8 @@ #include #include +#include +#include static void interrupt_init(void) { @@ -44,9 +46,15 @@ static void interrupt_init(void) void z_prep_c(void) { +#if defined(CONFIG_SOC_PREP_HOOK) + soc_prep_hook(); +#endif z_bss_zero(); interrupt_init(); +#if CONFIG_ARCH_CACHE + arch_cache_init(); +#endif z_cstart(); CODE_UNREACHABLE; diff --git a/arch/mips/core/thread.c b/arch/mips/core/thread.c index e551674d521..7966ff462f5 100644 --- a/arch/mips/core/thread.c +++ b/arch/mips/core/thread.c @@ -19,11 +19,11 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, char *stack_ptr, k_thread_entry_t entry, void *p1, void *p2, void *p3) { - struct __esf *stack_init; + struct arch_esf *stack_init; /* Initial stack frame for thread */ - stack_init = (struct __esf *)Z_STACK_PTR_ALIGN( - Z_STACK_PTR_TO_FRAME(struct __esf, stack_ptr) + stack_init = (struct arch_esf *)Z_STACK_PTR_ALIGN( + Z_STACK_PTR_TO_FRAME(struct arch_esf, stack_ptr) ); /* Setup the initial stack frame */ diff --git a/arch/mips/include/kernel_arch_func.h b/arch/mips/include/kernel_arch_func.h index ad89f75dd7f..b01cc1a4c65 100644 --- a/arch/mips/include/kernel_arch_func.h +++ b/arch/mips/include/kernel_arch_func.h @@ -35,7 +35,7 @@ arch_thread_return_value_set(struct k_thread *thread, unsigned int value) } FUNC_NORETURN void z_mips_fatal_error(unsigned int reason, - const z_arch_esf_t *esf); + const struct arch_esf *esf); static inline bool arch_is_in_isr(void) { diff --git a/arch/mips/include/offsets_short_arch.h b/arch/mips/include/offsets_short_arch.h index bd64deef114..8440f0ff701 100644 --- a/arch/mips/include/offsets_short_arch.h +++ b/arch/mips/include/offsets_short_arch.h @@ -9,7 +9,7 @@ #ifndef ZEPHYR_ARCH_MIPS_INCLUDE_OFFSETS_SHORT_ARCH_H_ #define ZEPHYR_ARCH_MIPS_INCLUDE_OFFSETS_SHORT_ARCH_H_ -#include +#include #define _thread_offset_to_sp \ (___thread_t_callee_saved_OFFSET + ___callee_saved_t_sp_OFFSET) diff --git a/arch/nios2/core/cpu_idle.c b/arch/nios2/core/cpu_idle.c index ecdea13f5e4..b201ecfa84e 100644 --- a/arch/nios2/core/cpu_idle.c +++ b/arch/nios2/core/cpu_idle.c @@ -7,6 +7,7 @@ #include #include +#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_IDLE void arch_cpu_idle(void) { /* Do nothing but unconditionally unlock interrupts and return to the @@ -14,7 +15,9 @@ void arch_cpu_idle(void) */ irq_unlock(NIOS2_STATUS_PIE_MSK); } +#endif +#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE void arch_cpu_atomic_idle(unsigned int key) { /* Do nothing but restore IRQ state. This CPU does not have any @@ -22,3 +25,4 @@ void arch_cpu_atomic_idle(unsigned int key) */ irq_unlock(key); } +#endif diff --git a/arch/nios2/core/exception.S b/arch/nios2/core/exception.S index 6b003262bb0..ab2d3463dd4 100644 --- a/arch/nios2/core/exception.S +++ b/arch/nios2/core/exception.S @@ -35,35 +35,35 @@ GTEXT(_offload_routine) */ SECTION_FUNC(exception.entry, _exception) /* Reserve thread stack space for saving context */ - subi sp, sp, __z_arch_esf_t_SIZEOF + subi sp, sp, __struct_arch_esf_SIZEOF /* Preserve all caller-saved registers onto the thread's stack */ - stw ra, __z_arch_esf_t_ra_OFFSET(sp) - stw r1, __z_arch_esf_t_r1_OFFSET(sp) - stw r2, __z_arch_esf_t_r2_OFFSET(sp) - stw r3, __z_arch_esf_t_r3_OFFSET(sp) - stw r4, __z_arch_esf_t_r4_OFFSET(sp) - stw r5, __z_arch_esf_t_r5_OFFSET(sp) - stw r6, __z_arch_esf_t_r6_OFFSET(sp) - stw r7, __z_arch_esf_t_r7_OFFSET(sp) - stw r8, __z_arch_esf_t_r8_OFFSET(sp) - stw r9, __z_arch_esf_t_r9_OFFSET(sp) - stw r10, __z_arch_esf_t_r10_OFFSET(sp) - stw r11, __z_arch_esf_t_r11_OFFSET(sp) - stw r12, __z_arch_esf_t_r12_OFFSET(sp) - stw r13, __z_arch_esf_t_r13_OFFSET(sp) - stw r14, __z_arch_esf_t_r14_OFFSET(sp) - stw r15, __z_arch_esf_t_r15_OFFSET(sp) + stw ra, __struct_arch_esf_ra_OFFSET(sp) + stw r1, __struct_arch_esf_r1_OFFSET(sp) + stw r2, __struct_arch_esf_r2_OFFSET(sp) + stw r3, __struct_arch_esf_r3_OFFSET(sp) + stw r4, __struct_arch_esf_r4_OFFSET(sp) + stw r5, __struct_arch_esf_r5_OFFSET(sp) + stw r6, __struct_arch_esf_r6_OFFSET(sp) + stw r7, __struct_arch_esf_r7_OFFSET(sp) + stw r8, __struct_arch_esf_r8_OFFSET(sp) + stw r9, __struct_arch_esf_r9_OFFSET(sp) + stw r10, __struct_arch_esf_r10_OFFSET(sp) + stw r11, __struct_arch_esf_r11_OFFSET(sp) + stw r12, __struct_arch_esf_r12_OFFSET(sp) + stw r13, __struct_arch_esf_r13_OFFSET(sp) + stw r14, __struct_arch_esf_r14_OFFSET(sp) + stw r15, __struct_arch_esf_r15_OFFSET(sp) /* Store value of estatus control register */ rdctl et, estatus - stw et, __z_arch_esf_t_estatus_OFFSET(sp) + stw et, __struct_arch_esf_estatus_OFFSET(sp) /* ea-4 is the address of the instruction when the exception happened, * put this in the stack frame as well */ addi r15, ea, -4 - stw r15, __z_arch_esf_t_instr_OFFSET(sp) + stw r15, __struct_arch_esf_instr_OFFSET(sp) /* Figure out whether we are here because of an interrupt or an * exception. If an interrupt, switch stacks and enter IRQ handling @@ -157,7 +157,7 @@ not_interrupt: * * We earlier put ea - 4 in the stack frame, replace it with just ea */ - stw ea, __z_arch_esf_t_instr_OFFSET(sp) + stw ea, __struct_arch_esf_instr_OFFSET(sp) #ifdef CONFIG_IRQ_OFFLOAD /* Check the contents of _offload_routine. If non-NULL, jump into @@ -193,35 +193,35 @@ _exception_exit: * and return to the interrupted context */ /* Return address from the exception */ - ldw ea, __z_arch_esf_t_instr_OFFSET(sp) + ldw ea, __struct_arch_esf_instr_OFFSET(sp) /* Restore estatus * XXX is this right??? */ - ldw r5, __z_arch_esf_t_estatus_OFFSET(sp) + ldw r5, __struct_arch_esf_estatus_OFFSET(sp) wrctl estatus, r5 /* Restore caller-saved registers */ - ldw ra, __z_arch_esf_t_ra_OFFSET(sp) - ldw r1, __z_arch_esf_t_r1_OFFSET(sp) - ldw r2, __z_arch_esf_t_r2_OFFSET(sp) - ldw r3, __z_arch_esf_t_r3_OFFSET(sp) - ldw r4, __z_arch_esf_t_r4_OFFSET(sp) - ldw r5, __z_arch_esf_t_r5_OFFSET(sp) - ldw r6, __z_arch_esf_t_r6_OFFSET(sp) - ldw r7, __z_arch_esf_t_r7_OFFSET(sp) - ldw r8, __z_arch_esf_t_r8_OFFSET(sp) - ldw r9, __z_arch_esf_t_r9_OFFSET(sp) - ldw r10, __z_arch_esf_t_r10_OFFSET(sp) - ldw r11, __z_arch_esf_t_r11_OFFSET(sp) - ldw r12, __z_arch_esf_t_r12_OFFSET(sp) - ldw r13, __z_arch_esf_t_r13_OFFSET(sp) - ldw r14, __z_arch_esf_t_r14_OFFSET(sp) - ldw r15, __z_arch_esf_t_r15_OFFSET(sp) + ldw ra, __struct_arch_esf_ra_OFFSET(sp) + ldw r1, __struct_arch_esf_r1_OFFSET(sp) + ldw r2, __struct_arch_esf_r2_OFFSET(sp) + ldw r3, __struct_arch_esf_r3_OFFSET(sp) + ldw r4, __struct_arch_esf_r4_OFFSET(sp) + ldw r5, __struct_arch_esf_r5_OFFSET(sp) + ldw r6, __struct_arch_esf_r6_OFFSET(sp) + ldw r7, __struct_arch_esf_r7_OFFSET(sp) + ldw r8, __struct_arch_esf_r8_OFFSET(sp) + ldw r9, __struct_arch_esf_r9_OFFSET(sp) + ldw r10, __struct_arch_esf_r10_OFFSET(sp) + ldw r11, __struct_arch_esf_r11_OFFSET(sp) + ldw r12, __struct_arch_esf_r12_OFFSET(sp) + ldw r13, __struct_arch_esf_r13_OFFSET(sp) + ldw r14, __struct_arch_esf_r14_OFFSET(sp) + ldw r15, __struct_arch_esf_r15_OFFSET(sp) /* Put the stack pointer back where it was when we entered * exception state */ - addi sp, sp, __z_arch_esf_t_SIZEOF + addi sp, sp, __struct_arch_esf_SIZEOF /* All done, copy estatus into status and transfer to ea */ eret diff --git a/arch/nios2/core/fatal.c b/arch/nios2/core/fatal.c index ac64b5bc309..b531bb41e17 100644 --- a/arch/nios2/core/fatal.c +++ b/arch/nios2/core/fatal.c @@ -12,7 +12,7 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); FUNC_NORETURN void z_nios2_fatal_error(unsigned int reason, - const z_arch_esf_t *esf) + const struct arch_esf *esf) { #if CONFIG_EXCEPTION_DEBUG if (esf != NULL) { @@ -102,7 +102,7 @@ static char *cause_str(uint32_t cause_code) } #endif -FUNC_NORETURN void _Fault(const z_arch_esf_t *esf) +FUNC_NORETURN void _Fault(const struct arch_esf *esf) { #if defined(CONFIG_PRINTK) || defined(CONFIG_LOG) /* Unfortunately, completely unavailable on Nios II/e cores */ diff --git a/arch/nios2/core/irq_offload.c b/arch/nios2/core/irq_offload.c index d33882f9f02..0c918896be9 100644 --- a/arch/nios2/core/irq_offload.c +++ b/arch/nios2/core/irq_offload.c @@ -41,3 +41,7 @@ void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) irq_unlock(key); } + +void arch_irq_offload_init(void) +{ +} diff --git a/arch/nios2/core/offsets/offsets.c b/arch/nios2/core/offsets/offsets.c index 8f3b3f748c1..9d381d87446 100644 --- a/arch/nios2/core/offsets/offsets.c +++ b/arch/nios2/core/offsets/offsets.c @@ -44,24 +44,24 @@ GEN_OFFSET_SYM(_callee_saved_t, sp); GEN_OFFSET_SYM(_callee_saved_t, key); GEN_OFFSET_SYM(_callee_saved_t, retval); -GEN_OFFSET_SYM(z_arch_esf_t, ra); -GEN_OFFSET_SYM(z_arch_esf_t, r1); -GEN_OFFSET_SYM(z_arch_esf_t, r2); -GEN_OFFSET_SYM(z_arch_esf_t, r3); -GEN_OFFSET_SYM(z_arch_esf_t, r4); -GEN_OFFSET_SYM(z_arch_esf_t, r5); -GEN_OFFSET_SYM(z_arch_esf_t, r6); -GEN_OFFSET_SYM(z_arch_esf_t, r7); -GEN_OFFSET_SYM(z_arch_esf_t, r8); -GEN_OFFSET_SYM(z_arch_esf_t, r9); -GEN_OFFSET_SYM(z_arch_esf_t, r10); -GEN_OFFSET_SYM(z_arch_esf_t, r11); -GEN_OFFSET_SYM(z_arch_esf_t, r12); -GEN_OFFSET_SYM(z_arch_esf_t, r13); -GEN_OFFSET_SYM(z_arch_esf_t, r14); -GEN_OFFSET_SYM(z_arch_esf_t, r15); -GEN_OFFSET_SYM(z_arch_esf_t, estatus); -GEN_OFFSET_SYM(z_arch_esf_t, instr); -GEN_ABSOLUTE_SYM(__z_arch_esf_t_SIZEOF, sizeof(z_arch_esf_t)); +GEN_OFFSET_STRUCT(arch_esf, ra); +GEN_OFFSET_STRUCT(arch_esf, r1); +GEN_OFFSET_STRUCT(arch_esf, r2); +GEN_OFFSET_STRUCT(arch_esf, r3); +GEN_OFFSET_STRUCT(arch_esf, r4); +GEN_OFFSET_STRUCT(arch_esf, r5); +GEN_OFFSET_STRUCT(arch_esf, r6); +GEN_OFFSET_STRUCT(arch_esf, r7); +GEN_OFFSET_STRUCT(arch_esf, r8); +GEN_OFFSET_STRUCT(arch_esf, r9); +GEN_OFFSET_STRUCT(arch_esf, r10); +GEN_OFFSET_STRUCT(arch_esf, r11); +GEN_OFFSET_STRUCT(arch_esf, r12); +GEN_OFFSET_STRUCT(arch_esf, r13); +GEN_OFFSET_STRUCT(arch_esf, r14); +GEN_OFFSET_STRUCT(arch_esf, r15); +GEN_OFFSET_STRUCT(arch_esf, estatus); +GEN_OFFSET_STRUCT(arch_esf, instr); +GEN_ABSOLUTE_SYM(__struct_arch_esf_SIZEOF, sizeof(struct arch_esf)); GEN_ABS_SYM_END diff --git a/arch/nios2/core/prep_c.c b/arch/nios2/core/prep_c.c index 74a3454af48..c5996205956 100644 --- a/arch/nios2/core/prep_c.c +++ b/arch/nios2/core/prep_c.c @@ -21,6 +21,8 @@ #include #include #include +#include +#include /** * @brief Prepare to and run C code @@ -30,6 +32,10 @@ void z_prep_c(void) { +#if defined(CONFIG_SOC_PREP_HOOK) + soc_prep_hook(); +#endif + z_bss_zero(); z_data_copy(); /* In most XIP scenarios we copy the exception code into RAM, so need @@ -44,6 +50,9 @@ void z_prep_c(void) */ z_nios2_dcache_flush_all(); #endif +#endif +#if CONFIG_ARCH_CACHE + arch_cache_init(); #endif z_cstart(); CODE_UNREACHABLE; diff --git a/arch/nios2/include/kernel_arch_func.h b/arch/nios2/include/kernel_arch_func.h index 2f2030c1c73..2df268a1c62 100644 --- a/arch/nios2/include/kernel_arch_func.h +++ b/arch/nios2/include/kernel_arch_func.h @@ -39,7 +39,7 @@ arch_thread_return_value_set(struct k_thread *thread, unsigned int value) } FUNC_NORETURN void z_nios2_fatal_error(unsigned int reason, - const z_arch_esf_t *esf); + const struct arch_esf *esf); static inline bool arch_is_in_isr(void) { diff --git a/arch/nios2/include/offsets_short_arch.h b/arch/nios2/include/offsets_short_arch.h index b3f60972c3b..3b961e1fcb9 100644 --- a/arch/nios2/include/offsets_short_arch.h +++ b/arch/nios2/include/offsets_short_arch.h @@ -7,7 +7,7 @@ #ifndef ZEPHYR_ARCH_NIOS2_INCLUDE_OFFSETS_SHORT_ARCH_H_ #define ZEPHYR_ARCH_NIOS2_INCLUDE_OFFSETS_SHORT_ARCH_H_ -#include +#include /* kernel */ diff --git a/arch/posix/core/CMakeLists.txt b/arch/posix/core/CMakeLists.txt index 12ec5261635..8c46147bc0a 100644 --- a/arch/posix/core/CMakeLists.txt +++ b/arch/posix/core/CMakeLists.txt @@ -21,10 +21,12 @@ endif() if(CONFIG_NATIVE_APPLICATION) zephyr_include_directories( nsi_compat/ + ${ZEPHYR_BASE}/scripts/native_simulator/common/src/include/ ) zephyr_library_sources( - posix_core.c + posix_core_nsi.c nsi_compat/nsi_compat.c + ${ZEPHYR_BASE}/scripts/native_simulator/common/src/nct.c ${ZEPHYR_BASE}/scripts/native_simulator/common/src/nce.c ${ZEPHYR_BASE}/scripts/native_simulator/common/src/nsi_host_trampolines.c ) diff --git a/arch/posix/core/irq.c b/arch/posix/core/irq.c index 11d99e782b1..a1d3568c154 100644 --- a/arch/posix/core/irq.c +++ b/arch/posix/core/irq.c @@ -14,6 +14,10 @@ void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) { posix_irq_offload(routine, parameter); } + +void arch_irq_offload_init(void) +{ +} #endif void arch_irq_enable(unsigned int irq) diff --git a/arch/posix/core/nsi_compat/nce_if.h b/arch/posix/core/nsi_compat/nce_if.h deleted file mode 100644 index be5772a2b73..00000000000 --- a/arch/posix/core/nsi_compat/nce_if.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (c) 2023 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef NSI_COMMON_SRC_INCL_NCE_IF_H -#define NSI_COMMON_SRC_INCL_NCE_IF_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Native simulator CPU start/stop emulation module interface */ - -void *nce_init(void); -void nce_terminate(void *this); -void nce_boot_cpu(void *this, void (*start_routine)(void)); -void nce_halt_cpu(void *this); -void nce_wake_cpu(void *this); -int nce_is_cpu_running(void *this); - -#ifdef __cplusplus -} -#endif - -#endif /* NSI_COMMON_SRC_INCL_NCE_IF_H */ diff --git a/arch/posix/core/nsi_compat/nsi_host_trampolines.h b/arch/posix/core/nsi_compat/nsi_host_trampolines.h deleted file mode 100644 index f0a2e06c1ca..00000000000 --- a/arch/posix/core/nsi_compat/nsi_host_trampolines.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2023 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - * - * Note: This is a provisional header which exists to allow - * old POSIX arch based boards (i.e. native_posix) to provide access - * to the host C library as if the native simulator trampolines - * existed. - * - * Boards based on the native simulator do NOT use this file - */ - -#ifndef ARCH_POSIX_CORE_NSI_COMPAT_NSI_HOST_TRAMPOLINES_H -#define ARCH_POSIX_CORE_NSI_COMPAT_NSI_HOST_TRAMPOLINES_H - -#include "../scripts/native_simulator/common/src/include/nsi_host_trampolines.h" - -#endif /* ARCH_POSIX_CORE_NSI_COMPAT_NSI_HOST_TRAMPOLINES_H */ diff --git a/arch/posix/core/nsi_compat/nsi_safe_call.h b/arch/posix/core/nsi_compat/nsi_safe_call.h deleted file mode 100644 index 6227cb187ae..00000000000 --- a/arch/posix/core/nsi_compat/nsi_safe_call.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2023 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ARCH_POSIX_CORE_NSI_SAFE_CALLL_H -#define ARCH_POSIX_CORE_NSI_SAFE_CALLL_H - -#include "nsi_tracing.h" -#include "posix_arch_internal.h" - -#define NSI_SAFE_CALL PC_SAFE_CALL - -#endif /* ARCH_POSIX_CORE_NSI_SAFE_CALLL_H */ diff --git a/arch/posix/core/nsi_compat/nsi_tracing.h b/arch/posix/core/nsi_compat/nsi_tracing.h deleted file mode 100644 index 854873bf3c8..00000000000 --- a/arch/posix/core/nsi_compat/nsi_tracing.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2023 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ARCH_POSIX_CORE_NSI_TRACING_H -#define ARCH_POSIX_CORE_NSI_TRACING_H - -#ifdef __cplusplus -extern "C" { -#endif - -void nsi_print_error_and_exit(const char *format, ...); -void nsi_print_warning(const char *format, ...); -void nsi_print_trace(const char *format, ...); - -#ifdef __cplusplus -} -#endif - -#endif /* ARCH_POSIX_CORE_NSI_TRACING_H */ diff --git a/arch/posix/core/posix_core.c b/arch/posix/core/posix_core.c deleted file mode 100644 index 89310f11d94..00000000000 --- a/arch/posix/core/posix_core.c +++ /dev/null @@ -1,539 +0,0 @@ -/* - * Copyright (c) 2017 Oticon A/S - * Copyright (c) 2023 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * Here is where things actually happen for the POSIX arch - * - * We isolate all functions here, to ensure they can be compiled as - * independently as possible to the remainder of Zephyr to avoid name clashes - * as Zephyr does provide functions with the same names as the POSIX threads - * functions - */ -/** - * Principle of operation: - * - * The Zephyr OS and its app run as a set of native pthreads. - * The Zephyr OS only sees one of this thread executing at a time. - * Which is running is controlled using {cond|mtx}_threads and - * currently_allowed_thread. - * - * The main part of the execution of each thread will occur in a fully - * synchronous and deterministic manner, and only when commanded by the Zephyr - * kernel. - * But the creation of a thread will spawn a new pthread whose start - * is asynchronous to the rest, until synchronized in posix_wait_until_allowed() - * below. - * Similarly aborting and canceling threads execute a tail in a quite - * asynchronous manner. - * - * This implementation is meant to be portable in between POSIX systems. - * A table (threads_table) is used to abstract the native pthreads. - * And index in this table is used to identify threads in the IF to the kernel. - * - */ - -#include -#include -#include -#include - -#include "posix_core.h" -#include "posix_arch_internal.h" - -#define PREFIX "POSIX arch core: " -#define ERPREFIX PREFIX"error on " -#define NO_MEM_ERR PREFIX"Can't allocate memory\n" - -#define PC_ENABLE_CANCEL 0 /* See Note.c1 */ -#define PC_ALLOC_CHUNK_SIZE 64 -#define PC_REUSE_ABORTED_ENTRIES 0 -/* tests/kernel/threads/scheduling/schedule_api fails when setting - * PC_REUSE_ABORTED_ENTRIES => don't set it by now - */ - -static int threads_table_size; -struct threads_table_el { - enum {NOTUSED = 0, USED, ABORTING, ABORTED, FAILED} state; - bool running; /* Is this the currently running thread */ - pthread_t thread; /* Actual pthread_t as returned by native kernel */ - int thead_cnt; /* For debugging: Unique, consecutive, thread number */ - /* Pointer to the status kept in the Zephyr thread stack */ - posix_thread_status_t *t_status; -}; - -static struct threads_table_el *threads_table; - -static int thread_create_count; /* For debugging. Thread creation counter */ - -/* - * Conditional variable to block/awake all threads during swaps() - * (we only need 1 mutex and 1 cond variable for all threads) - */ -static pthread_cond_t cond_threads = PTHREAD_COND_INITIALIZER; -/* Mutex for the conditional variable posix_core_cond_threads */ -static pthread_mutex_t mtx_threads = PTHREAD_MUTEX_INITIALIZER; -/* Token which tells which process is allowed to run now */ -static int currently_allowed_thread; - -static bool terminate; /* Are we terminating the program == cleaning up */ - -static void posix_wait_until_allowed(int this_th_nbr); -static void *posix_thread_starter(void *arg); -static void posix_preexit_cleanup(void); -extern void posix_arch_thread_entry(void *pa_thread_status); - -/** - * Helper function, run by a thread is being aborted - */ -static void abort_tail(int this_th_nbr) -{ - PC_DEBUG("Thread [%i] %i: %s: Aborting (exiting) (rel mut)\n", - threads_table[this_th_nbr].thead_cnt, - this_th_nbr, - __func__); - - threads_table[this_th_nbr].running = false; - threads_table[this_th_nbr].state = ABORTED; - posix_preexit_cleanup(); - pthread_exit(NULL); -} - -/** - * Helper function to block this thread until it is allowed again - * (somebody calls posix_let_run() with this thread number - * - * Note that we go out of this function (the while loop below) - * with the mutex locked by this particular thread. - * In normal circumstances, the mutex is only unlocked internally in - * pthread_cond_wait() while waiting for cond_threads to be signaled - */ -static void posix_wait_until_allowed(int this_th_nbr) -{ - threads_table[this_th_nbr].running = false; - - PC_DEBUG("Thread [%i] %i: %s: Waiting to be allowed to run (rel mut)\n", - threads_table[this_th_nbr].thead_cnt, - this_th_nbr, - __func__); - - while (this_th_nbr != currently_allowed_thread) { - pthread_cond_wait(&cond_threads, &mtx_threads); - - if (threads_table && - (threads_table[this_th_nbr].state == ABORTING)) { - abort_tail(this_th_nbr); - } - } - - threads_table[this_th_nbr].running = true; - - PC_DEBUG("Thread [%i] %i: %s(): I'm allowed to run! (hav mut)\n", - threads_table[this_th_nbr].thead_cnt, - this_th_nbr, - __func__); -} - - -/** - * Helper function to let the thread run - * Note: posix_let_run() can only be called with the mutex locked - */ -static void posix_let_run(int next_allowed_th) -{ - PC_DEBUG("%s: We let thread [%i] %i run\n", - __func__, - threads_table[next_allowed_th].thead_cnt, - next_allowed_th); - - - currently_allowed_thread = next_allowed_th; - - /* - * We let all threads know one is able to run now (it may even be us - * again if fancied) - * Note that as we hold the mutex, they are going to be blocked until - * we reach our own posix_wait_until_allowed() while loop - */ - PC_SAFE_CALL(pthread_cond_broadcast(&cond_threads)); -} - - -static void posix_preexit_cleanup(void) -{ - /* - * Release the mutex so the next allowed thread can run - */ - PC_SAFE_CALL(pthread_mutex_unlock(&mtx_threads)); - - /* We detach ourselves so nobody needs to join to us */ - pthread_detach(pthread_self()); -} - - -/** - * Let the ready thread run and block this thread until it is allowed again - * - * called from arch_swap() which does the picking from the kernel structures - */ -void posix_swap(int next_allowed_thread_nbr, int this_th_nbr) -{ - posix_let_run(next_allowed_thread_nbr); - - if (threads_table[this_th_nbr].state == ABORTING) { - PC_DEBUG("Thread [%i] %i: %s: Aborting curr.\n", - threads_table[this_th_nbr].thead_cnt, - this_th_nbr, - __func__); - abort_tail(this_th_nbr); - } else { - posix_wait_until_allowed(this_th_nbr); - } -} - -/** - * Let the ready thread (main) run, and exit this thread (init) - * - * Called from arch_switch_to_main_thread() which does the picking from the - * kernel structures - * - * Note that we could have just done a swap(), but that would have left the - * init thread lingering. Instead here we exit the init thread after enabling - * the new one - */ -void posix_main_thread_start(int next_allowed_thread_nbr) -{ - posix_let_run(next_allowed_thread_nbr); - PC_DEBUG("%s: Init thread dying now (rel mut)\n", - __func__); - posix_preexit_cleanup(); - pthread_exit(NULL); -} - -/** - * Handler called when any thread is cancelled or exits - */ -static void posix_cleanup_handler(void *arg) -{ - /* - * If we are not terminating, this is just an aborted thread, - * and the mutex was already released - * Otherwise, release the mutex so other threads which may be - * caught waiting for it could terminate - */ - - if (!terminate) { - return; - } - -#if POSIX_ARCH_DEBUG_PRINTS - posix_thread_status_t *ptr = (posix_thread_status_t *) arg; - - PC_DEBUG("Thread %i: %s: Canceling (rel mut)\n", - ptr->thread_idx, - __func__); -#endif - - - PC_SAFE_CALL(pthread_mutex_unlock(&mtx_threads)); - - /* We detach ourselves so nobody needs to join to us */ - pthread_detach(pthread_self()); -} - -/** - * Helper function to start a Zephyr thread as a POSIX thread: - * It will block the thread until a arch_swap() is called for it - * - * Spawned from posix_new_thread() below - */ -static void *posix_thread_starter(void *arg) -{ - int thread_idx = (intptr_t)arg; - - PC_DEBUG("Thread [%i] %i: %s: Starting\n", - threads_table[thread_idx].thead_cnt, - thread_idx, - __func__); - - /* - * We block until all other running threads reach the while loop - * in posix_wait_until_allowed() and they release the mutex - */ - PC_SAFE_CALL(pthread_mutex_lock(&mtx_threads)); - - /* - * The program may have been finished before this thread ever got to run - */ - /* LCOV_EXCL_START */ /* See Note1 */ - if (!threads_table) { - posix_cleanup_handler(arg); - pthread_exit(NULL); - } - /* LCOV_EXCL_STOP */ - - pthread_cleanup_push(posix_cleanup_handler, arg); - - PC_DEBUG("Thread [%i] %i: %s: After start mutex (hav mut)\n", - threads_table[thread_idx].thead_cnt, - thread_idx, - __func__); - - /* - * The thread would try to execute immediately, so we block it - * until allowed - */ - posix_wait_until_allowed(thread_idx); - - posix_thread_status_t *ptr = threads_table[thread_idx].t_status; - - posix_arch_thread_entry(ptr); - - /* - * We only reach this point if the thread actually returns which should - * not happen. But we handle it gracefully just in case - */ - /* LCOV_EXCL_START */ - posix_print_trace(PREFIX"Thread [%i] %i [%lu] ended!?!\n", - threads_table[thread_idx].thead_cnt, - thread_idx, - pthread_self()); - - - threads_table[thread_idx].running = false; - threads_table[thread_idx].state = FAILED; - - pthread_cleanup_pop(1); - - return NULL; - /* LCOV_EXCL_STOP */ -} - -/** - * Return the first free entry index in the threads table - */ -static int ttable_get_empty_slot(void) -{ - - for (int i = 0; i < threads_table_size; i++) { - if ((threads_table[i].state == NOTUSED) - || (PC_REUSE_ABORTED_ENTRIES - && (threads_table[i].state == ABORTED))) { - return i; - } - } - - /* - * else, we run out table without finding an index - * => we expand the table - */ - - threads_table = realloc(threads_table, - (threads_table_size + PC_ALLOC_CHUNK_SIZE) - * sizeof(struct threads_table_el)); - if (threads_table == NULL) { /* LCOV_EXCL_BR_LINE */ - posix_print_error_and_exit(NO_MEM_ERR); /* LCOV_EXCL_LINE */ - } - - /* Clear new piece of table */ - (void)memset(&threads_table[threads_table_size], 0, - PC_ALLOC_CHUNK_SIZE * sizeof(struct threads_table_el)); - - threads_table_size += PC_ALLOC_CHUNK_SIZE; - - /* The first newly created entry is good: */ - return threads_table_size - PC_ALLOC_CHUNK_SIZE; -} - -/** - * Called from arch_new_thread(), - * Create a new POSIX thread for the new Zephyr thread. - * arch_new_thread() picks from the kernel structures what it is that we need - * to call with what parameters - */ -int posix_new_thread(void *ptr) -{ - int t_slot; - - t_slot = ttable_get_empty_slot(); - threads_table[t_slot].state = USED; - threads_table[t_slot].running = false; - threads_table[t_slot].thead_cnt = thread_create_count++; - threads_table[t_slot].t_status = ptr; - - /* - * Note: If you are here due to a valgrind reported memory leak in - * pthread_create() please use the provided valgrind.supp suppression file. - */ - PC_SAFE_CALL(pthread_create(&threads_table[t_slot].thread, - NULL, - posix_thread_starter, - (void *)(intptr_t)t_slot)); - - PC_DEBUG("%s created thread [%i] %i [%lu]\n", - __func__, - threads_table[t_slot].thead_cnt, - t_slot, - threads_table[t_slot].thread); - - return t_slot; -} - -/* - * Initialize the posix architecture - * - * Prepare whatever needs to be prepared to be able to start threads - */ -void posix_arch_init(void) -{ - thread_create_count = 0; - - currently_allowed_thread = -1; - - threads_table = calloc(PC_ALLOC_CHUNK_SIZE, - sizeof(struct threads_table_el)); - if (threads_table == NULL) { /* LCOV_EXCL_BR_LINE */ - posix_print_error_and_exit(NO_MEM_ERR); /* LCOV_EXCL_LINE */ - } - - threads_table_size = PC_ALLOC_CHUNK_SIZE; - - - PC_SAFE_CALL(pthread_mutex_lock(&mtx_threads)); -} - -/* - * Free any allocated memory by the posix core and clean up. - * Note that this function cannot be called from a SW thread - * (the CPU is assumed halted. Otherwise we will cancel ourselves) - * - * This function cannot guarantee the threads will be cancelled before the HW - * thread exists. The only way to do that, would be to wait for each of them in - * a join (without detaching them, but that could lead to locks in some - * convoluted cases. As a call to this function can come from an ASSERT or other - * error termination, we better do not assume things are working fine. - * => we prefer the supposed memory leak report from valgrind, and ensure we - * will not hang - */ -void posix_arch_clean_up(void) -{ - - if (!threads_table) { /* LCOV_EXCL_BR_LINE */ - return; /* LCOV_EXCL_LINE */ - } - - terminate = true; - -#if (PC_ENABLE_CANCEL) - for (int i = 0; i < threads_table_size; i++) { - if (threads_table[i].state != USED) { - continue; - } - - /* LCOV_EXCL_START */ - if (pthread_cancel(threads_table[i].thread)) { - posix_print_warning( - PREFIX"cleanup: could not stop thread %i\n", - i); - } - /* LCOV_EXCL_STOP */ - } -#endif - - free(threads_table); - threads_table = NULL; -} - -void posix_abort_thread(int thread_idx) -{ - if (thread_idx == currently_allowed_thread) { - PC_DEBUG("Thread [%i] %i: %s Marked myself " - "as aborting\n", - threads_table[thread_idx].thead_cnt, - thread_idx, - __func__); - } else { - if (threads_table[thread_idx].state != USED) { /* LCOV_EXCL_BR_LINE */ - /* The thread may have been already aborted before */ - return; /* LCOV_EXCL_LINE */ - } - - PC_DEBUG("Aborting not scheduled thread [%i] %i\n", - threads_table[thread_idx].thead_cnt, - thread_idx); - } - - threads_table[thread_idx].state = ABORTING; - /* - * Note: the native thread will linger in RAM until it catches the - * mutex or awakes on the condition. - * Note that even if we would pthread_cancel() the thread here, that - * would be the case, but with a pthread_cancel() the mutex state would - * be uncontrolled - */ - -} - -int posix_arch_get_unique_thread_id(int thread_idx) -{ - return threads_table[thread_idx].thead_cnt; -} - -/* - * Notes about coverage: - * - * Note1: - * - * This condition will only be triggered in very unlikely cases - * (once every few full regression runs). - * It is therefore excluded from the coverage report to avoid confusing - * developers. - * - * Background: This arch creates a pthread as soon as the Zephyr kernel creates - * a Zephyr thread. A pthread creation is an asynchronous process handled by the - * host kernel. - * - * This architecture normally keeps only 1 thread executing at a time. - * But part of the pre-initialization during creation of a new thread - * and some cleanup at the tail of the thread termination are executed - * in parallel to other threads. - * That is, the execution of those code paths is a bit indeterministic. - * - * Only when the Zephyr kernel attempts to swap to a new thread does this - * architecture need to wait until its pthread is ready and initialized - * (has reached posix_wait_until_allowed()) - * - * In some cases (tests) threads are created which are never actually needed - * (typically the idle thread). That means the test may finish before this - * thread's underlying pthread has reached posix_wait_until_allowed(). - * - * In this unlikely cases the initialization or cleanup of the thread follows - * non-typical code paths. - * This code paths are there to ensure things work always, no matter - * the load of the host. Without them, very rare & mysterious segfault crashes - * would occur. - * But as they are very atypical and only triggered with some host loads, - * they will be covered in the coverage reports only rarely. - * - * Note2: - * - * Some other code will never or only very rarely trigger and is therefore - * excluded with LCOV_EXCL_LINE - * - * - * Notes about (memory) cleanup: - * - * Note.c1: - * - * In some very rare cases in very loaded machines, a race in the glibc pthread_cancel() - * seems to be triggered. - * In this, the cancelled thread cleanup overtakes the pthread_cancel() code, and frees the - * pthread structure before pthread_cancel() has finished, resulting in a dereference into already - * free'd memory, and therefore a segfault. - * Calling pthread_cancel() during cleanup is not required beyond preventing a valgrind - * memory leak report (all threads will be canceled immediately on exit). - * Therefore we do not do this, to avoid this very rare crashes. - */ diff --git a/arch/posix/core/posix_core_nsi.c b/arch/posix/core/posix_core_nsi.c index 496ce12a3bf..39ed2de0ea6 100644 --- a/arch/posix/core/posix_core_nsi.c +++ b/arch/posix/core/posix_core_nsi.c @@ -57,3 +57,8 @@ int posix_arch_get_unique_thread_id(int thread_idx) { return nct_get_unique_thread_id(te_state, thread_idx); } + +int posix_arch_thread_name_set(int thread_idx, const char *str) +{ + return nct_thread_name_set(te_state, thread_idx, str); +} diff --git a/arch/posix/core/swap.c b/arch/posix/core/swap.c index 67ca4c5bb9b..d4ec5e50b5e 100644 --- a/arch/posix/core/swap.c +++ b/arch/posix/core/swap.c @@ -112,7 +112,7 @@ void posix_irq_check_idle_exit(void) { if (_kernel.idle) { _kernel.idle = 0; - z_pm_save_idle_exit(); + pm_system_resume(); } } #endif diff --git a/arch/posix/core/thread.c b/arch/posix/core/thread.c index cc7fc355554..4e443e2283b 100644 --- a/arch/posix/core/thread.c +++ b/arch/posix/core/thread.c @@ -13,6 +13,7 @@ * architecture */ +#include #include #include #include @@ -54,6 +55,40 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, thread_status->thread_idx = posix_new_thread((void *)thread_status); } +int arch_thread_name_set(struct k_thread *thread, const char *str) +{ +#define MAX_HOST_THREAD_NAME 16 + + int ret; + int thread_index; + posix_thread_status_t *thread_status; + char th_name[MAX_HOST_THREAD_NAME]; + + thread_status = thread->callee_saved.thread_status; + if (!thread_status) { + return -EAGAIN; + } + + thread_index = thread_status->thread_idx; + + if (!str) { + return -EAGAIN; + } + + snprintf(th_name, MAX_HOST_THREAD_NAME, + #if (CONFIG_NATIVE_SIMULATOR_NUMBER_MCUS > 1) + STRINGIFY(CONFIG_NATIVE_SIMULATOR_MCU_N) ":" + #endif + "%s", str); + + ret = posix_arch_thread_name_set(thread_index, th_name); + if (ret) { + return -EAGAIN; + } + + return 0; +} + void posix_arch_thread_entry(void *pa_thread_status) { posix_thread_status_t *ptr = pa_thread_status; diff --git a/arch/posix/include/offsets_short_arch.h b/arch/posix/include/offsets_short_arch.h index b33414b3f6e..5281d68e092 100644 --- a/arch/posix/include/offsets_short_arch.h +++ b/arch/posix/include/offsets_short_arch.h @@ -7,7 +7,7 @@ #ifndef ZEPHYR_ARCH_POSIX_INCLUDE_OFFSETS_SHORT_ARCH_H_ #define ZEPHYR_ARCH_POSIX_INCLUDE_OFFSETS_SHORT_ARCH_H_ -#include +#include /* kernel */ diff --git a/arch/posix/include/posix_core.h b/arch/posix/include/posix_core.h index c16d17afbd9..983f80a3abd 100644 --- a/arch/posix/include/posix_core.h +++ b/arch/posix/include/posix_core.h @@ -47,6 +47,7 @@ void posix_main_thread_start(int next_allowed_thread_nbr); int posix_new_thread(void *payload); void posix_abort_thread(int thread_idx); int posix_arch_get_unique_thread_id(int thread_idx); +int posix_arch_thread_name_set(int thread_idx, const char *str); #ifndef POSIX_ARCH_DEBUG_PRINTS #define POSIX_ARCH_DEBUG_PRINTS 0 diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 1c4d547b29c..575c9871c13 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -30,7 +30,6 @@ config RISCV_GP config RISCV_ALWAYS_SWITCH_THROUGH_ECALL bool "Do not use mret outside a trap handler context" depends on MULTITHREADING - depends on !RISCV_PMP help Use mret instruction only when in a trap handler. This is for RISC-V implementations that require every mret to be @@ -38,30 +37,14 @@ config RISCV_ALWAYS_SWITCH_THROUGH_ECALL and most people should say n here to minimize context switching overhead. -config RISCV_ENABLE_FRAME_POINTER - bool - default y - depends on OVERRIDE_FRAME_POINTER_DEFAULT && !OMIT_FRAME_POINTER - help - Hidden option to simplify access to OVERRIDE_FRAME_POINTER_DEFAULT - and OMIT_FRAME_POINTER. It is automatically enabled when the frame - pointer unwinding is enabled. - -config RISCV_EXCEPTION_STACK_TRACE - bool - default y - depends on EXCEPTION_STACK_TRACE - imply THREAD_STACK_INFO - help - Internal config to enable runtime stack traces on fatal exceptions. - menu "RISCV Processor Options" config INCLUDE_RESET_VECTOR - bool "Include Reset vector" + bool "Jumps to __initialize directly" help - Include the reset vector stub, which initializes the stack and - prepares for running C code. + Select 'y' here to use the Zephyr provided default implementation that + jumps to `__initialize` directly. Otherwise a SOC needs to provide its + custom `__reset` routine. config RISCV_PRIVILEGED bool @@ -98,7 +81,7 @@ config RISCV_SOC_HAS_ISR_STACKING guarded by !_ASMLANGUAGE. The ESF should be defined to account for the hardware stacked registers in the proper order as they are saved on the stack by the hardware, and the registers saved by the - software macros. The structure must be called '__esf'. + software macros. The structure must be called 'struct arch_esf'. config RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING bool @@ -255,6 +238,14 @@ config RISCV_HART_MASK i.e. 128, 129, ..(0x80, 8x81, ..), this can be configured to 63 (0x7f) such that we can extract the bits that start from 0. +config EXTRA_EXCEPTION_INFO + bool "Collect extra exception info" + depends on EXCEPTION_DEBUG + help + This option enables the collection of extra information, such as + register state, when a fault occurs. This information can be useful + to collect for post-mortem analysis and debug of issues. + config RISCV_PMP bool "RISC-V PMP Support" select THREAD_STACK_INFO @@ -379,6 +370,7 @@ config ARCH_IRQ_VECTOR_TABLE_ALIGN config RISCV_TRAP_HANDLER_ALIGNMENT int "Alignment of RISC-V trap handler in bytes" + default 64 if RISCV_HAS_CLIC default 4 help This value configures the alignment of RISC-V trap handling @@ -392,6 +384,14 @@ config GEN_IRQ_VECTOR_TABLE config ARCH_HAS_SINGLE_THREAD_SUPPORT default y if !SMP +config ARCH_HAS_STACKWALK + bool + default y + imply THREAD_STACK_INFO + help + Internal config to indicate that the arch_stack_walk() API is implemented + and it can be enabled. + rsource "Kconfig.isa" endmenu diff --git a/arch/riscv/core/CMakeLists.txt b/arch/riscv/core/CMakeLists.txt index 7ffcffd65c8..3e97d36d7f8 100644 --- a/arch/riscv/core/CMakeLists.txt +++ b/arch/riscv/core/CMakeLists.txt @@ -6,7 +6,6 @@ zephyr_library_sources( cpu_idle.c fatal.c irq_manage.c - isr.S prep_c.c reboot.c reset.S @@ -21,9 +20,10 @@ endif () zephyr_library_sources_ifdef(CONFIG_FPU_SHARING fpu.c fpu.S) zephyr_library_sources_ifdef(CONFIG_DEBUG_COREDUMP coredump.c) zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c) +zephyr_library_sources_ifdef(CONFIG_GEN_SW_ISR_TABLE isr.S) zephyr_library_sources_ifdef(CONFIG_RISCV_PMP pmp.c pmp.S) zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE tls.c) zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S) zephyr_library_sources_ifdef(CONFIG_SEMIHOST semihost.c) -zephyr_library_sources_ifdef(CONFIG_RISCV_EXCEPTION_STACK_TRACE stacktrace.c) +zephyr_library_sources_ifdef(CONFIG_ARCH_STACKWALK stacktrace.c) zephyr_linker_sources(ROM_START SORT_KEY 0x0vectors vector_table.ld) diff --git a/arch/riscv/core/coredump.c b/arch/riscv/core/coredump.c index f232816433a..70d7a9976d4 100644 --- a/arch/riscv/core/coredump.c +++ b/arch/riscv/core/coredump.c @@ -67,7 +67,7 @@ struct riscv_arch_block { */ static struct riscv_arch_block arch_blk; -void arch_coredump_info_dump(const z_arch_esf_t *esf) +void arch_coredump_info_dump(const struct arch_esf *esf) { struct coredump_arch_hdr_t hdr = { .id = COREDUMP_ARCH_HDR_ID, diff --git a/arch/riscv/core/cpu_idle.c b/arch/riscv/core/cpu_idle.c index 1d47680cef2..413b911a53e 100644 --- a/arch/riscv/core/cpu_idle.c +++ b/arch/riscv/core/cpu_idle.c @@ -7,16 +7,20 @@ #include #include -void __weak arch_cpu_idle(void) +#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_IDLE +void arch_cpu_idle(void) { sys_trace_idle(); __asm__ volatile("wfi"); irq_unlock(MSTATUS_IEN); } +#endif -void __weak arch_cpu_atomic_idle(unsigned int key) +#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE +void arch_cpu_atomic_idle(unsigned int key) { sys_trace_idle(); __asm__ volatile("wfi"); irq_unlock(key); } +#endif diff --git a/arch/riscv/core/fatal.c b/arch/riscv/core/fatal.c index 8efffd37371..d5cbd2f4dc1 100644 --- a/arch/riscv/core/fatal.c +++ b/arch/riscv/core/fatal.c @@ -29,15 +29,15 @@ static const struct z_exc_handle exceptions[] = { #endif /* Stack trace function */ -void z_riscv_unwind_stack(const z_arch_esf_t *esf); +void z_riscv_unwind_stack(const struct arch_esf *esf, const _callee_saved_t *csf); -uintptr_t z_riscv_get_sp_before_exc(const z_arch_esf_t *esf) +uintptr_t z_riscv_get_sp_before_exc(const struct arch_esf *esf) { /* * Kernel stack pointer prior this exception i.e. before * storing the exception stack frame. */ - uintptr_t sp = (uintptr_t)esf + sizeof(z_arch_esf_t); + uintptr_t sp = (uintptr_t)esf + sizeof(struct arch_esf); #ifdef CONFIG_USERSPACE if ((esf->mstatus & MSTATUS_MPP) == PRV_U) { @@ -52,15 +52,55 @@ uintptr_t z_riscv_get_sp_before_exc(const z_arch_esf_t *esf) return sp; } +const char *z_riscv_mcause_str(unsigned long cause) +{ + static const char *const mcause_str[17] = { + [0] = "Instruction address misaligned", + [1] = "Instruction Access fault", + [2] = "Illegal instruction", + [3] = "Breakpoint", + [4] = "Load address misaligned", + [5] = "Load access fault", + [6] = "Store/AMO address misaligned", + [7] = "Store/AMO access fault", + [8] = "Environment call from U-mode", + [9] = "Environment call from S-mode", + [10] = "unknown", + [11] = "Environment call from M-mode", + [12] = "Instruction page fault", + [13] = "Load page fault", + [14] = "unknown", + [15] = "Store/AMO page fault", + [16] = "unknown", + }; + + return mcause_str[MIN(cause, ARRAY_SIZE(mcause_str) - 1)]; +} + FUNC_NORETURN void z_riscv_fatal_error(unsigned int reason, - const z_arch_esf_t *esf) + const struct arch_esf *esf) { z_riscv_fatal_error_csf(reason, esf, NULL); } -FUNC_NORETURN void z_riscv_fatal_error_csf(unsigned int reason, const z_arch_esf_t *esf, +FUNC_NORETURN void z_riscv_fatal_error_csf(unsigned int reason, const struct arch_esf *esf, const _callee_saved_t *csf) { + unsigned long mcause; + + __asm__ volatile("csrr %0, mcause" : "=r" (mcause)); + + mcause &= CONFIG_RISCV_MCAUSE_EXCEPTION_MASK; + LOG_ERR(""); + LOG_ERR(" mcause: %ld, %s", mcause, z_riscv_mcause_str(mcause)); + +#ifndef CONFIG_SOC_OPENISA_RV32M1 + unsigned long mtval; + + __asm__ volatile("csrr %0, mtval" : "=r" (mtval)); + LOG_ERR(" mtval: %lx", mtval); +#endif /* CONFIG_SOC_OPENISA_RV32M1 */ + #ifdef CONFIG_EXCEPTION_DEBUG if (esf != NULL) { LOG_ERR(" a0: " PR_REG " t0: " PR_REG, esf->a0, esf->t0); @@ -98,60 +138,24 @@ FUNC_NORETURN void z_riscv_fatal_error_csf(unsigned int reason, const z_arch_esf #endif /* CONFIG_RISCV_ISA_RV32E */ LOG_ERR(""); } +#endif /* CONFIG_EXCEPTION_DEBUG */ - if (IS_ENABLED(CONFIG_RISCV_EXCEPTION_STACK_TRACE)) { - z_riscv_unwind_stack(esf); - } +#ifdef CONFIG_EXCEPTION_STACK_TRACE + z_riscv_unwind_stack(esf, csf); +#endif /* CONFIG_EXCEPTION_STACK_TRACE */ -#endif /* CONFIG_EXCEPTION_DEBUG */ z_fatal_error(reason, esf); CODE_UNREACHABLE; } -static char *cause_str(unsigned long cause) -{ - switch (cause) { - case 0: - return "Instruction address misaligned"; - case 1: - return "Instruction Access fault"; - case 2: - return "Illegal instruction"; - case 3: - return "Breakpoint"; - case 4: - return "Load address misaligned"; - case 5: - return "Load access fault"; - case 6: - return "Store/AMO address misaligned"; - case 7: - return "Store/AMO access fault"; - case 8: - return "Environment call from U-mode"; - case 9: - return "Environment call from S-mode"; - case 11: - return "Environment call from M-mode"; - case 12: - return "Instruction page fault"; - case 13: - return "Load page fault"; - case 15: - return "Store/AMO page fault"; - default: - return "unknown"; - } -} - -static bool bad_stack_pointer(z_arch_esf_t *esf) +static bool bad_stack_pointer(struct arch_esf *esf) { #ifdef CONFIG_PMP_STACK_GUARD /* * Check if the kernel stack pointer prior this exception (before * storing the exception stack frame) was in the stack guard area. */ - uintptr_t sp = (uintptr_t)esf + sizeof(z_arch_esf_t); + uintptr_t sp = (uintptr_t)esf + sizeof(struct arch_esf); #ifdef CONFIG_USERSPACE if (_current->arch.priv_stack_start != 0 && @@ -189,7 +193,7 @@ static bool bad_stack_pointer(z_arch_esf_t *esf) return false; } -void _Fault(z_arch_esf_t *esf) +void _Fault(struct arch_esf *esf) { #ifdef CONFIG_USERSPACE /* @@ -207,25 +211,16 @@ void _Fault(z_arch_esf_t *esf) } #endif /* CONFIG_USERSPACE */ - unsigned long mcause; - - __asm__ volatile("csrr %0, mcause" : "=r" (mcause)); - -#ifndef CONFIG_SOC_OPENISA_RV32M1 - unsigned long mtval; - __asm__ volatile("csrr %0, mtval" : "=r" (mtval)); -#endif - - mcause &= CONFIG_RISCV_MCAUSE_EXCEPTION_MASK; - LOG_ERR(""); - LOG_ERR(" mcause: %ld, %s", mcause, cause_str(mcause)); -#ifndef CONFIG_SOC_OPENISA_RV32M1 - LOG_ERR(" mtval: %lx", mtval); -#endif - unsigned int reason = K_ERR_CPU_EXCEPTION; if (bad_stack_pointer(esf)) { +#ifdef CONFIG_PMP_STACK_GUARD + /* + * Remove the thread's PMP setting to prevent triggering a stack + * overflow error again due to the previous configuration. + */ + z_riscv_pmp_stackguard_disable(); +#endif /* CONFIG_PMP_STACK_GUARD */ reason = K_ERR_STACK_CHK_FAIL; } @@ -241,7 +236,7 @@ FUNC_NORETURN void arch_syscall_oops(void *ssf_ptr) void z_impl_user_fault(unsigned int reason) { - z_arch_esf_t *oops_esf = _current->syscall_frame; + struct arch_esf *oops_esf = _current->syscall_frame; if (((_current->base.user_options & K_USER) != 0) && reason != K_ERR_STACK_CHK_FAIL) { @@ -255,6 +250,6 @@ static void z_vrfy_user_fault(unsigned int reason) z_impl_user_fault(reason); } -#include +#include #endif /* CONFIG_USERSPACE */ diff --git a/arch/riscv/core/fpu.S b/arch/riscv/core/fpu.S index 2708d11fec1..981bd576cb7 100644 --- a/arch/riscv/core/fpu.S +++ b/arch/riscv/core/fpu.S @@ -7,7 +7,7 @@ #include #include -#include +#include #ifdef CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION #define LOAD fld diff --git a/arch/riscv/core/fpu.c b/arch/riscv/core/fpu.c index da5d07b3146..318e97e0002 100644 --- a/arch/riscv/core/fpu.c +++ b/arch/riscv/core/fpu.c @@ -204,7 +204,7 @@ void z_riscv_fpu_enter_exc(void) * Note that the exception depth count was not incremented before this call * as no further exceptions are expected before returning to normal mode. */ -void z_riscv_fpu_trap(z_arch_esf_t *esf) +void z_riscv_fpu_trap(struct arch_esf *esf) { __ASSERT((esf->mstatus & MSTATUS_FS) == 0 && (csr_read(mstatus) & MSTATUS_FS) == 0, @@ -293,7 +293,7 @@ static bool fpu_access_allowed(unsigned int exc_update_level) * This is called on every exception exit except for z_riscv_fpu_trap(). * In that case the exception level of interest is 1 (soon to be 0). */ -void z_riscv_fpu_exit_exc(z_arch_esf_t *esf) +void z_riscv_fpu_exit_exc(struct arch_esf *esf) { if (fpu_access_allowed(1)) { esf->mstatus &= ~MSTATUS_FS; diff --git a/arch/riscv/core/irq_manage.c b/arch/riscv/core/irq_manage.c index 358b07534be..8ba7b615b42 100644 --- a/arch/riscv/core/irq_manage.c +++ b/arch/riscv/core/irq_manage.c @@ -19,6 +19,12 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); FUNC_NORETURN void z_irq_spurious(const void *unused) { +#ifdef CONFIG_EMPTY_IRQ_SPURIOUS + while (1) { + } + + CODE_UNREACHABLE; +#else unsigned long mcause; ARG_UNUSED(unused); @@ -37,6 +43,7 @@ FUNC_NORETURN void z_irq_spurious(const void *unused) } #endif z_riscv_fatal_error(K_ERR_SPURIOUS_IRQ, NULL); +#endif /* CONFIG_EMPTY_IRQ_SPURIOUS */ } #ifdef CONFIG_DYNAMIC_INTERRUPTS diff --git a/arch/riscv/core/irq_offload.c b/arch/riscv/core/irq_offload.c index d325bc2dcd6..73d4b04c2a1 100644 --- a/arch/riscv/core/irq_offload.c +++ b/arch/riscv/core/irq_offload.c @@ -11,3 +11,7 @@ void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) { arch_syscall_invoke2((uintptr_t)routine, (uintptr_t)parameter, RV_ECALL_IRQ_OFFLOAD); } + +void arch_irq_offload_init(void) +{ +} diff --git a/arch/riscv/core/isr.S b/arch/riscv/core/isr.S index e9a3d523127..7e885da93a4 100644 --- a/arch/riscv/core/isr.S +++ b/arch/riscv/core/isr.S @@ -24,22 +24,22 @@ /* Convenience macro for loading/storing register states. */ #define DO_CALLER_SAVED(op) \ - RV_E( op t0, __z_arch_esf_t_t0_OFFSET(sp) );\ - RV_E( op t1, __z_arch_esf_t_t1_OFFSET(sp) );\ - RV_E( op t2, __z_arch_esf_t_t2_OFFSET(sp) );\ - RV_I( op t3, __z_arch_esf_t_t3_OFFSET(sp) );\ - RV_I( op t4, __z_arch_esf_t_t4_OFFSET(sp) );\ - RV_I( op t5, __z_arch_esf_t_t5_OFFSET(sp) );\ - RV_I( op t6, __z_arch_esf_t_t6_OFFSET(sp) );\ - RV_E( op a0, __z_arch_esf_t_a0_OFFSET(sp) );\ - RV_E( op a1, __z_arch_esf_t_a1_OFFSET(sp) );\ - RV_E( op a2, __z_arch_esf_t_a2_OFFSET(sp) );\ - RV_E( op a3, __z_arch_esf_t_a3_OFFSET(sp) );\ - RV_E( op a4, __z_arch_esf_t_a4_OFFSET(sp) );\ - RV_E( op a5, __z_arch_esf_t_a5_OFFSET(sp) );\ - RV_I( op a6, __z_arch_esf_t_a6_OFFSET(sp) );\ - RV_I( op a7, __z_arch_esf_t_a7_OFFSET(sp) );\ - RV_E( op ra, __z_arch_esf_t_ra_OFFSET(sp) ) + RV_E( op t0, __struct_arch_esf_t0_OFFSET(sp) );\ + RV_E( op t1, __struct_arch_esf_t1_OFFSET(sp) );\ + RV_E( op t2, __struct_arch_esf_t2_OFFSET(sp) );\ + RV_I( op t3, __struct_arch_esf_t3_OFFSET(sp) );\ + RV_I( op t4, __struct_arch_esf_t4_OFFSET(sp) );\ + RV_I( op t5, __struct_arch_esf_t5_OFFSET(sp) );\ + RV_I( op t6, __struct_arch_esf_t6_OFFSET(sp) );\ + RV_E( op a0, __struct_arch_esf_a0_OFFSET(sp) );\ + RV_E( op a1, __struct_arch_esf_a1_OFFSET(sp) );\ + RV_E( op a2, __struct_arch_esf_a2_OFFSET(sp) );\ + RV_E( op a3, __struct_arch_esf_a3_OFFSET(sp) );\ + RV_E( op a4, __struct_arch_esf_a4_OFFSET(sp) );\ + RV_E( op a5, __struct_arch_esf_a5_OFFSET(sp) );\ + RV_I( op a6, __struct_arch_esf_a6_OFFSET(sp) );\ + RV_I( op a7, __struct_arch_esf_a7_OFFSET(sp) );\ + RV_E( op ra, __struct_arch_esf_ra_OFFSET(sp) ) #ifdef CONFIG_EXCEPTION_DEBUG /* Convenience macro for storing callee saved register [s0 - s11] states. */ @@ -157,7 +157,7 @@ SECTION_FUNC(exception.entry, _isr_wrapper) /* Save user stack value. Coming from user space, we know this * can't overflow the privileged stack. The esf will be allocated * later but it is safe to store our saved user sp here. */ - sr t0, (-__z_arch_esf_t_SIZEOF + __z_arch_esf_t_sp_OFFSET)(sp) + sr t0, (-__struct_arch_esf_SIZEOF + __struct_arch_esf_sp_OFFSET)(sp) /* Make sure tls pointer is sane */ lr t0, ___cpu_t_current_OFFSET(s0) @@ -180,21 +180,21 @@ SECTION_FUNC(exception.entry, _isr_wrapper) SOC_ISR_SW_STACKING #else /* Save caller-saved registers on current thread stack. */ - addi sp, sp, -__z_arch_esf_t_SIZEOF + addi sp, sp, -__struct_arch_esf_SIZEOF DO_CALLER_SAVED(sr) ; #endif /* CONFIG_RISCV_SOC_HAS_ISR_STACKING */ /* Save s0 in the esf and load it with &_current_cpu. */ - sr s0, __z_arch_esf_t_s0_OFFSET(sp) + sr s0, __struct_arch_esf_s0_OFFSET(sp) get_current_cpu s0 /* Save MEPC register */ csrr t0, mepc - sr t0, __z_arch_esf_t_mepc_OFFSET(sp) + sr t0, __struct_arch_esf_mepc_OFFSET(sp) /* Save MSTATUS register */ csrr t2, mstatus - sr t2, __z_arch_esf_t_mstatus_OFFSET(sp) + sr t2, __struct_arch_esf_mstatus_OFFSET(sp) #if defined(CONFIG_FPU_SHARING) /* determine if FPU access was disabled */ @@ -301,7 +301,7 @@ no_fp: /* increment _current->arch.exception_depth */ #ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE /* Handle context saving at SOC level. */ - addi a0, sp, __z_arch_esf_t_soc_context_OFFSET + addi a0, sp, __struct_arch_esf_soc_context_OFFSET jal ra, __soc_save_context #endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */ @@ -347,11 +347,26 @@ no_fp: /* increment _current->arch.exception_depth */ */ li t1, RISCV_EXC_ECALLU beq t0, t1, is_user_syscall + +#ifdef CONFIG_PMP_STACK_GUARD + /* + * Determine if we come from user space. If so, reconfigure the PMP for + * kernel mode stack guard. + */ + csrr t0, mstatus + li t1, MSTATUS_MPP + and t0, t0, t1 + bnez t0, 1f + lr a0, ___cpu_t_current_OFFSET(s0) + call z_riscv_pmp_stackguard_enable +1: +#endif /* CONFIG_PMP_STACK_GUARD */ + #endif /* CONFIG_USERSPACE */ /* * Call _Fault to handle exception. - * Stack pointer is pointing to a z_arch_esf_t structure, pass it + * Stack pointer is pointing to a struct_arch_esf structure, pass it * to _Fault (via register a0). * If _Fault shall return, set return address to * no_reschedule to restore stack. @@ -370,9 +385,9 @@ is_kernel_syscall: * It's safe to always increment by 4, even with compressed * instructions, because the ecall instruction is always 4 bytes. */ - lr t0, __z_arch_esf_t_mepc_OFFSET(sp) + lr t0, __struct_arch_esf_mepc_OFFSET(sp) addi t0, t0, 4 - sr t0, __z_arch_esf_t_mepc_OFFSET(sp) + sr t0, __struct_arch_esf_mepc_OFFSET(sp) #ifdef CONFIG_PMP_STACK_GUARD /* Re-activate PMP for m-mode */ @@ -383,7 +398,7 @@ is_kernel_syscall: #endif /* Determine what to do. Operation code is in t0. */ - lr t0, __z_arch_esf_t_t0_OFFSET(sp) + lr t0, __struct_arch_esf_t0_OFFSET(sp) .if RV_ECALL_RUNTIME_EXCEPT != 0; .err; .endif beqz t0, do_fault @@ -396,8 +411,24 @@ is_kernel_syscall: #ifdef CONFIG_RISCV_ALWAYS_SWITCH_THROUGH_ECALL li t1, RV_ECALL_SCHEDULE bne t0, t1, skip_schedule - lr a0, __z_arch_esf_t_a0_OFFSET(sp) - lr a1, __z_arch_esf_t_a1_OFFSET(sp) + lr a0, __struct_arch_esf_a0_OFFSET(sp) + lr a1, __struct_arch_esf_a1_OFFSET(sp) + +#ifdef CONFIG_FPU_SHARING + /* + * When an ECALL is used for a context-switch, the current thread has + * been updated to the next thread. + * Add the exception_depth back to the previous thread. + */ + lb t1, _thread_offset_to_exception_depth(a0) + add t1, t1, -1 + sb t1, _thread_offset_to_exception_depth(a0) + + lb t1, _thread_offset_to_exception_depth(a1) + add t1, t1, 1 + sb t1, _thread_offset_to_exception_depth(a1) +#endif + j reschedule skip_schedule: #endif @@ -408,7 +439,7 @@ skip_schedule: do_fault: /* Handle RV_ECALL_RUNTIME_EXCEPT. Retrieve reason in a0, esf in A1. */ - lr a0, __z_arch_esf_t_a0_OFFSET(sp) + lr a0, __struct_arch_esf_a0_OFFSET(sp) 1: mv a1, sp #ifdef CONFIG_EXCEPTION_DEBUG @@ -419,10 +450,15 @@ do_fault: STORE_CALLEE_SAVED() ; mv a2, sp +#ifdef CONFIG_EXTRA_EXCEPTION_INFO + /* Store csf's addr into esf (a1 still holds the pointer to the esf at this point) */ + sr a2 __struct_arch_esf_csf_OFFSET(a1) +#endif /* CONFIG_EXTRA_EXCEPTION_INFO */ + tail z_riscv_fatal_error_csf #else tail z_riscv_fatal_error -#endif +#endif /* CONFIG_EXCEPTION_DEBUG */ #if defined(CONFIG_IRQ_OFFLOAD) do_irq_offload: @@ -431,8 +467,8 @@ do_irq_offload: * Routine pointer is in saved a0, argument in saved a1 * so we load them with a1/a0 (reversed). */ - lr a1, __z_arch_esf_t_a0_OFFSET(sp) - lr a0, __z_arch_esf_t_a1_OFFSET(sp) + lr a1, __struct_arch_esf_a0_OFFSET(sp) + lr a0, __struct_arch_esf_a1_OFFSET(sp) /* Increment _current_cpu->nested */ lw t1, ___cpu_t_nested_OFFSET(s0) @@ -474,18 +510,18 @@ is_user_syscall: * Same as for is_kernel_syscall: increment saved MEPC by 4 to * prevent triggering the same ecall again upon exiting the ISR. */ - lr t1, __z_arch_esf_t_mepc_OFFSET(sp) + lr t1, __struct_arch_esf_mepc_OFFSET(sp) addi t1, t1, 4 - sr t1, __z_arch_esf_t_mepc_OFFSET(sp) + sr t1, __struct_arch_esf_mepc_OFFSET(sp) /* Restore argument registers from user stack */ - lr a0, __z_arch_esf_t_a0_OFFSET(sp) - lr a1, __z_arch_esf_t_a1_OFFSET(sp) - lr a2, __z_arch_esf_t_a2_OFFSET(sp) - lr a3, __z_arch_esf_t_a3_OFFSET(sp) - lr a4, __z_arch_esf_t_a4_OFFSET(sp) - lr a5, __z_arch_esf_t_a5_OFFSET(sp) - lr t0, __z_arch_esf_t_t0_OFFSET(sp) + lr a0, __struct_arch_esf_a0_OFFSET(sp) + lr a1, __struct_arch_esf_a1_OFFSET(sp) + lr a2, __struct_arch_esf_a2_OFFSET(sp) + lr a3, __struct_arch_esf_a3_OFFSET(sp) + lr a4, __struct_arch_esf_a4_OFFSET(sp) + lr a5, __struct_arch_esf_a5_OFFSET(sp) + lr t0, __struct_arch_esf_t0_OFFSET(sp) #if defined(CONFIG_RISCV_ISA_RV32E) /* Stack alignment for RV32E is 4 bytes */ addi sp, sp, -4 @@ -519,7 +555,7 @@ valid_syscall_id: #endif /* CONFIG_RISCV_ISA_RV32E */ /* Update a0 (return value) on the stack */ - sr a0, __z_arch_esf_t_a0_OFFSET(sp) + sr a0, __struct_arch_esf_a0_OFFSET(sp) /* Disable IRQs again before leaving */ csrc mstatus, MSTATUS_IEN @@ -534,7 +570,7 @@ is_interrupt: * If we came from userspace then we need to reconfigure the * PMP for kernel mode stack guard. */ - lr t0, __z_arch_esf_t_mstatus_OFFSET(sp) + lr t0, __struct_arch_esf_mstatus_OFFSET(sp) li t1, MSTATUS_MPP and t0, t0, t1 bnez t0, 1f @@ -665,7 +701,7 @@ no_reschedule: #ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE /* Restore context at SOC level */ - addi a0, sp, __z_arch_esf_t_soc_context_OFFSET + addi a0, sp, __struct_arch_esf_soc_context_OFFSET jal ra, __soc_restore_context #endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */ @@ -683,8 +719,8 @@ fp_trap_exit: #endif /* Restore MEPC and MSTATUS registers */ - lr t0, __z_arch_esf_t_mepc_OFFSET(sp) - lr t2, __z_arch_esf_t_mstatus_OFFSET(sp) + lr t0, __struct_arch_esf_mepc_OFFSET(sp) + lr t2, __struct_arch_esf_mstatus_OFFSET(sp) csrw mepc, t0 csrw mstatus, t2 @@ -711,7 +747,7 @@ fp_trap_exit: sb t1, %tprel_lo(is_user_mode)(t0) /* preserve stack pointer for next exception entry */ - add t0, sp, __z_arch_esf_t_SIZEOF + add t0, sp, __struct_arch_esf_SIZEOF sr t0, _curr_cpu_arch_user_exc_sp(s0) j 2f @@ -720,13 +756,13 @@ fp_trap_exit: * We are returning to kernel mode. Store the stack pointer to * be re-loaded further down. */ - addi t0, sp, __z_arch_esf_t_SIZEOF - sr t0, __z_arch_esf_t_sp_OFFSET(sp) + addi t0, sp, __struct_arch_esf_SIZEOF + sr t0, __struct_arch_esf_sp_OFFSET(sp) 2: #endif /* Restore s0 (it is no longer ours) */ - lr s0, __z_arch_esf_t_s0_OFFSET(sp) + lr s0, __struct_arch_esf_s0_OFFSET(sp) #ifdef CONFIG_RISCV_SOC_HAS_ISR_STACKING SOC_ISR_SW_UNSTACKING @@ -736,10 +772,10 @@ fp_trap_exit: #ifdef CONFIG_USERSPACE /* retrieve saved stack pointer */ - lr sp, __z_arch_esf_t_sp_OFFSET(sp) + lr sp, __struct_arch_esf_sp_OFFSET(sp) #else /* remove esf from the stack */ - addi sp, sp, __z_arch_esf_t_SIZEOF + addi sp, sp, __struct_arch_esf_SIZEOF #endif #endif /* CONFIG_RISCV_SOC_HAS_ISR_STACKING */ diff --git a/arch/riscv/core/offsets/offsets.c b/arch/riscv/core/offsets/offsets.c index 9bc9306c2e9..99eba096824 100644 --- a/arch/riscv/core/offsets/offsets.c +++ b/arch/riscv/core/offsets/offsets.c @@ -13,6 +13,7 @@ * structures. */ +#include #include #include #include @@ -88,43 +89,47 @@ GEN_OFFSET_SYM(_thread_arch_t, exception_depth); #endif /* CONFIG_FPU_SHARING */ /* esf member offsets */ -GEN_OFFSET_SYM(z_arch_esf_t, ra); -GEN_OFFSET_SYM(z_arch_esf_t, t0); -GEN_OFFSET_SYM(z_arch_esf_t, t1); -GEN_OFFSET_SYM(z_arch_esf_t, t2); -GEN_OFFSET_SYM(z_arch_esf_t, a0); -GEN_OFFSET_SYM(z_arch_esf_t, a1); -GEN_OFFSET_SYM(z_arch_esf_t, a2); -GEN_OFFSET_SYM(z_arch_esf_t, a3); -GEN_OFFSET_SYM(z_arch_esf_t, a4); -GEN_OFFSET_SYM(z_arch_esf_t, a5); +GEN_OFFSET_STRUCT(arch_esf, ra); +GEN_OFFSET_STRUCT(arch_esf, t0); +GEN_OFFSET_STRUCT(arch_esf, t1); +GEN_OFFSET_STRUCT(arch_esf, t2); +GEN_OFFSET_STRUCT(arch_esf, a0); +GEN_OFFSET_STRUCT(arch_esf, a1); +GEN_OFFSET_STRUCT(arch_esf, a2); +GEN_OFFSET_STRUCT(arch_esf, a3); +GEN_OFFSET_STRUCT(arch_esf, a4); +GEN_OFFSET_STRUCT(arch_esf, a5); #if !defined(CONFIG_RISCV_ISA_RV32E) -GEN_OFFSET_SYM(z_arch_esf_t, t3); -GEN_OFFSET_SYM(z_arch_esf_t, t4); -GEN_OFFSET_SYM(z_arch_esf_t, t5); -GEN_OFFSET_SYM(z_arch_esf_t, t6); -GEN_OFFSET_SYM(z_arch_esf_t, a6); -GEN_OFFSET_SYM(z_arch_esf_t, a7); +GEN_OFFSET_STRUCT(arch_esf, t3); +GEN_OFFSET_STRUCT(arch_esf, t4); +GEN_OFFSET_STRUCT(arch_esf, t5); +GEN_OFFSET_STRUCT(arch_esf, t6); +GEN_OFFSET_STRUCT(arch_esf, a6); +GEN_OFFSET_STRUCT(arch_esf, a7); #endif /* !CONFIG_RISCV_ISA_RV32E */ -GEN_OFFSET_SYM(z_arch_esf_t, mepc); -GEN_OFFSET_SYM(z_arch_esf_t, mstatus); +GEN_OFFSET_STRUCT(arch_esf, mepc); +GEN_OFFSET_STRUCT(arch_esf, mstatus); -GEN_OFFSET_SYM(z_arch_esf_t, s0); +GEN_OFFSET_STRUCT(arch_esf, s0); #ifdef CONFIG_USERSPACE -GEN_OFFSET_SYM(z_arch_esf_t, sp); +GEN_OFFSET_STRUCT(arch_esf, sp); #endif +#ifdef CONFIG_EXTRA_EXCEPTION_INFO +GEN_OFFSET_STRUCT(arch_esf, csf); +#endif /* CONFIG_EXTRA_EXCEPTION_INFO */ + #if defined(CONFIG_RISCV_SOC_CONTEXT_SAVE) -GEN_OFFSET_SYM(z_arch_esf_t, soc_context); +GEN_OFFSET_STRUCT(arch_esf, soc_context); #endif #if defined(CONFIG_RISCV_SOC_OFFSETS) GEN_SOC_OFFSET_SYMS(); #endif -GEN_ABSOLUTE_SYM(__z_arch_esf_t_SIZEOF, sizeof(z_arch_esf_t)); +GEN_ABSOLUTE_SYM(__struct_arch_esf_SIZEOF, sizeof(struct arch_esf)); #ifdef CONFIG_EXCEPTION_DEBUG GEN_ABSOLUTE_SYM(__callee_saved_t_SIZEOF, ROUND_UP(sizeof(_callee_saved_t), ARCH_STACK_PTR_ALIGN)); diff --git a/arch/riscv/core/pmp.c b/arch/riscv/core/pmp.c index 50b5dd58f5d..e41eb8d4bb0 100644 --- a/arch/riscv/core/pmp.c +++ b/arch/riscv/core/pmp.c @@ -204,6 +204,34 @@ static bool set_pmp_entry(unsigned int *index_p, uint8_t perm, return ok; } +static inline bool set_pmp_mprv_catchall(unsigned int *index_p, + unsigned long *pmp_addr, unsigned long *pmp_cfg, + unsigned int index_limit) +{ + /* + * We'll be using MPRV. Make a fallback entry with everything + * accessible as if no PMP entries were matched which is otherwise + * the default behavior for m-mode without MPRV. + */ + bool ok = set_pmp_entry(index_p, PMP_R | PMP_W | PMP_X, + 0, 0, pmp_addr, pmp_cfg, index_limit); + +#ifdef CONFIG_QEMU_TARGET + if (ok) { + /* + * Workaround: The above produced 0x1fffffff which is correct. + * But there is a QEMU bug that prevents it from interpreting + * this value correctly. Hardcode the special case used by + * QEMU to bypass this bug for now. The QEMU fix is here: + * https://lists.gnu.org/archive/html/qemu-devel/2022-04/msg00961.html + */ + pmp_addr[*index_p - 1] = -1L; + } +#endif + + return ok; +} + /** * @brief Write a range of PMP entries to corresponding PMP registers * @@ -320,8 +348,8 @@ static unsigned int global_pmp_end_index; */ void z_riscv_pmp_init(void) { - unsigned long pmp_addr[4]; - unsigned long pmp_cfg[1]; + unsigned long pmp_addr[5]; + unsigned long pmp_cfg[2]; unsigned int index = 0; /* The read-only area is always there for every mode */ @@ -351,10 +379,28 @@ void z_riscv_pmp_init(void) (uintptr_t)z_interrupt_stacks[_current_cpu->id], Z_RISCV_STACK_GUARD_SIZE, pmp_addr, pmp_cfg, ARRAY_SIZE(pmp_addr)); -#endif + /* + * This early, the kernel init code uses the IRQ stack and we want to + * safeguard it as soon as possible. But we need a temporary default + * "catch all" PMP entry for MPRV to work. Later on, this entry will + * be set for each thread by z_riscv_pmp_stackguard_prepare(). + */ + set_pmp_mprv_catchall(&index, pmp_addr, pmp_cfg, ARRAY_SIZE(pmp_addr)); + + /* Write those entries to PMP regs. */ write_pmp_entries(0, index, true, pmp_addr, pmp_cfg, ARRAY_SIZE(pmp_addr)); + /* Activate our non-locked PMP entries for m-mode */ + csr_set(mstatus, MSTATUS_MPRV); + + /* And forget about that last entry as we won't need it later */ + index--; +#else + /* Write those entries to PMP regs. */ + write_pmp_entries(0, index, true, pmp_addr, pmp_cfg, ARRAY_SIZE(pmp_addr)); +#endif + #ifdef CONFIG_SMP #ifdef CONFIG_PMP_STACK_GUARD /* @@ -373,6 +419,7 @@ void z_riscv_pmp_init(void) } #endif + __ASSERT(index <= PMPCFG_STRIDE, "provision for one global word only"); global_pmp_cfg[0] = pmp_cfg[0]; global_pmp_last_addr = pmp_addr[index - 1]; global_pmp_end_index = index; @@ -429,24 +476,7 @@ void z_riscv_pmp_stackguard_prepare(struct k_thread *thread) set_pmp_entry(&index, PMP_NONE, stack_bottom, Z_RISCV_STACK_GUARD_SIZE, PMP_M_MODE(thread)); - - /* - * We'll be using MPRV. Make a fallback entry with everything - * accessible as if no PMP entries were matched which is otherwise - * the default behavior for m-mode without MPRV. - */ - set_pmp_entry(&index, PMP_R | PMP_W | PMP_X, - 0, 0, PMP_M_MODE(thread)); -#ifdef CONFIG_QEMU_TARGET - /* - * Workaround: The above produced 0x1fffffff which is correct. - * But there is a QEMU bug that prevents it from interpreting this - * value correctly. Hardcode the special case used by QEMU to - * bypass this bug for now. The QEMU fix is here: - * https://lists.gnu.org/archive/html/qemu-devel/2022-04/msg00961.html - */ - thread->arch.m_mode_pmpaddr_regs[index-1] = -1L; -#endif + set_pmp_mprv_catchall(&index, PMP_M_MODE(thread)); /* remember how many entries we use */ thread->arch.m_mode_pmp_end_index = index; @@ -481,6 +511,37 @@ void z_riscv_pmp_stackguard_enable(struct k_thread *thread) csr_set(mstatus, MSTATUS_MPRV); } +/** + * @brief Remove PMP stackguard content to actual PMP registers + */ +void z_riscv_pmp_stackguard_disable(void) +{ + + unsigned long pmp_addr[PMP_M_MODE_SLOTS]; + unsigned long pmp_cfg[PMP_M_MODE_SLOTS / sizeof(unsigned long)]; + unsigned int index = global_pmp_end_index; + + /* Retrieve the pmpaddr value matching the last global PMP slot. */ + pmp_addr[global_pmp_end_index - 1] = global_pmp_last_addr; + + /* Disable (non-locked) PMP entries for m-mode while we update them. */ + csr_clear(mstatus, MSTATUS_MPRV); + + /* + * Set a temporary default "catch all" PMP entry for MPRV to work, + * except for the global locked entries. + */ + set_pmp_mprv_catchall(&index, pmp_addr, pmp_cfg, ARRAY_SIZE(pmp_addr)); + + /* Write "catch all" entry and clear unlocked entries to PMP regs. */ + write_pmp_entries(global_pmp_end_index, index, + true, pmp_addr, pmp_cfg, ARRAY_SIZE(pmp_addr)); + + if (PMP_DEBUG_DUMP) { + dump_pmp_regs("catch all register dump"); + } +} + #endif /* CONFIG_PMP_STACK_GUARD */ #ifdef CONFIG_USERSPACE diff --git a/arch/riscv/core/prep_c.c b/arch/riscv/core/prep_c.c index b0fdd3a0569..e74a570cb66 100644 --- a/arch/riscv/core/prep_c.c +++ b/arch/riscv/core/prep_c.c @@ -19,6 +19,8 @@ #include #include #include +#include +#include #if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT) void soc_interrupt_init(void); @@ -33,10 +35,17 @@ void soc_interrupt_init(void); void z_prep_c(void) { +#if defined(CONFIG_SOC_PREP_HOOK) + soc_prep_hook(); +#endif + z_bss_zero(); z_data_copy(); #if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT) soc_interrupt_init(); +#endif +#if CONFIG_ARCH_CACHE + arch_cache_init(); #endif z_cstart(); CODE_UNREACHABLE; diff --git a/arch/riscv/core/reset.S b/arch/riscv/core/reset.S index e9424e7a8e2..af96cb9757e 100644 --- a/arch/riscv/core/reset.S +++ b/arch/riscv/core/reset.S @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include "asm_macros.inc" /* exports */ @@ -62,7 +62,8 @@ boot_first_core: #ifdef CONFIG_INIT_STACKS /* Pre-populate all bytes in z_interrupt_stacks with 0xAA */ la t0, z_interrupt_stacks - li t1, __z_interrupt_stack_SIZEOF + /* Total size of all cores' IRQ stack */ + li t1, __z_interrupt_all_stacks_SIZEOF add t1, t1, t0 /* Populate z_interrupt_stacks with 0xaaaaaaaa */ @@ -71,7 +72,7 @@ aa_loop: sw t2, 0x00(t0) addi t0, t0, 4 blt t0, t1, aa_loop -#endif +#endif /* CONFIG_INIT_STACKS */ /* * Initially, setup stack pointer to diff --git a/arch/riscv/core/smp.c b/arch/riscv/core/smp.c index 68147f8880a..4ef287c4a7a 100644 --- a/arch/riscv/core/smp.c +++ b/arch/riscv/core/smp.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -86,14 +87,15 @@ static atomic_val_t cpu_pending_ipi[CONFIG_MP_MAX_NUM_CPUS]; #define IPI_SCHED 0 #define IPI_FPU_FLUSH 1 -void arch_sched_ipi(void) +void arch_sched_directed_ipi(uint32_t cpu_bitmap) { unsigned int key = arch_irq_lock(); unsigned int id = _current_cpu->id; unsigned int num_cpus = arch_num_cpus(); for (unsigned int i = 0; i < num_cpus; i++) { - if (i != id && _kernel.cpus[i].arch.online) { + if ((i != id) && _kernel.cpus[i].arch.online && + ((cpu_bitmap & BIT(i)) != 0)) { atomic_set_bit(&cpu_pending_ipi[i], IPI_SCHED); MSIP(_kernel.cpus[i].arch.hartid) = 1; } @@ -102,6 +104,11 @@ void arch_sched_ipi(void) arch_irq_unlock(key); } +void arch_sched_broadcast_ipi(void) +{ + arch_sched_directed_ipi(IPI_ALL_CPUS_MASK); +} + #ifdef CONFIG_FPU_SHARING void arch_flush_fpu_ipi(unsigned int cpu) { @@ -165,5 +172,4 @@ int arch_smp_init(void) return 0; } -SYS_INIT(arch_smp_init, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); #endif /* CONFIG_SMP */ diff --git a/arch/riscv/core/stacktrace.c b/arch/riscv/core/stacktrace.c index a85dcfbd82d..361e152f00c 100644 --- a/arch/riscv/core/stacktrace.c +++ b/arch/riscv/core/stacktrace.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include #include #include #include @@ -11,51 +12,80 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); -uintptr_t z_riscv_get_sp_before_exc(const z_arch_esf_t *esf); +uintptr_t z_riscv_get_sp_before_exc(const struct arch_esf *esf); -#if __riscv_xlen == 32 - #define PR_REG "%08" PRIxPTR -#elif __riscv_xlen == 64 - #define PR_REG "%016" PRIxPTR -#endif +typedef bool (*riscv_stacktrace_cb)(void *cookie, unsigned long addr, unsigned long sfp); -#define MAX_STACK_FRAMES 8 +#define MAX_STACK_FRAMES CONFIG_ARCH_STACKWALK_MAX_FRAMES struct stackframe { uintptr_t fp; uintptr_t ra; }; -static bool in_stack_bound(uintptr_t addr) +typedef bool (*stack_verify_fn)(uintptr_t, const struct k_thread *const, const struct arch_esf *); + +static inline bool in_irq_stack_bound(uintptr_t addr, uint8_t cpu_id) +{ + uintptr_t start, end; + + start = (uintptr_t)K_KERNEL_STACK_BUFFER(z_interrupt_stacks[cpu_id]); + end = start + CONFIG_ISR_STACK_SIZE; + + return (addr >= start) && (addr < end); +} + +static inline bool in_kernel_thread_stack_bound(uintptr_t addr, const struct k_thread *const thread) { #ifdef CONFIG_THREAD_STACK_INFO uintptr_t start, end; - if (_current == NULL || arch_is_in_isr()) { - /* We were servicing an interrupt */ - int cpu_id; + start = thread->stack_info.start; + end = Z_STACK_PTR_ALIGN(thread->stack_info.start + thread->stack_info.size); -#ifdef CONFIG_SMP - cpu_id = arch_curr_cpu()->id; + return (addr >= start) && (addr < end); #else - cpu_id = 0; + ARG_UNUSED(addr); + ARG_UNUSED(thread); + /* Return false as we can't check if the addr is in the thread stack without stack info */ + return false; #endif +} - start = (uintptr_t)K_KERNEL_STACK_BUFFER(z_interrupt_stacks[cpu_id]); - end = start + CONFIG_ISR_STACK_SIZE; #ifdef CONFIG_USERSPACE - /* TODO: handle user threads */ -#endif +static inline bool in_user_thread_stack_bound(uintptr_t addr, const struct k_thread *const thread) +{ + uintptr_t start, end; + + /* See: zephyr/include/zephyr/arch/riscv/arch.h */ + if (IS_ENABLED(CONFIG_PMP_POWER_OF_TWO_ALIGNMENT)) { + start = thread->arch.priv_stack_start + Z_RISCV_STACK_GUARD_SIZE; } else { - start = _current->stack_info.start; - end = Z_STACK_PTR_ALIGN(_current->stack_info.start + _current->stack_info.size); + start = thread->stack_info.start - CONFIG_PRIVILEGED_STACK_SIZE; } + end = Z_STACK_PTR_ALIGN(thread->arch.priv_stack_start + K_KERNEL_STACK_RESERVED + + CONFIG_PRIVILEGED_STACK_SIZE); return (addr >= start) && (addr < end); -#else - ARG_UNUSED(addr); - return true; -#endif /* CONFIG_THREAD_STACK_INFO */ +} +#endif /* CONFIG_USERSPACE */ + +static bool in_stack_bound(uintptr_t addr, const struct k_thread *const thread, + const struct arch_esf *esf) +{ + ARG_UNUSED(esf); + + if (!IS_ALIGNED(addr, sizeof(uintptr_t))) { + return false; + } + +#ifdef CONFIG_USERSPACE + if ((thread->base.user_options & K_USER) != 0) { + return in_user_thread_stack_bound(addr, thread); + } +#endif /* CONFIG_USERSPACE */ + + return in_kernel_thread_stack_bound(addr, thread); } static inline bool in_text_region(uintptr_t addr) @@ -65,62 +95,192 @@ static inline bool in_text_region(uintptr_t addr) return (addr >= (uintptr_t)&__text_region_start) && (addr < (uintptr_t)&__text_region_end); } -#ifdef CONFIG_RISCV_ENABLE_FRAME_POINTER -void z_riscv_unwind_stack(const z_arch_esf_t *esf) +#ifdef CONFIG_FRAME_POINTER +static void walk_stackframe(riscv_stacktrace_cb cb, void *cookie, const struct k_thread *thread, + const struct arch_esf *esf, stack_verify_fn vrfy, + const _callee_saved_t *csf) { - uintptr_t fp = esf->s0; + uintptr_t fp, last_fp = 0; uintptr_t ra; struct stackframe *frame; - if (esf == NULL) { - return; + if (esf != NULL) { + /* Unwind the provided exception stack frame */ + fp = esf->s0; + ra = esf->mepc; + } else if ((csf == NULL) || (csf == &_current->callee_saved)) { + /* Unwind current thread (default case when nothing is provided ) */ + fp = (uintptr_t)__builtin_frame_address(0); + ra = (uintptr_t)walk_stackframe; + } else { + /* Unwind the provided thread */ + fp = csf->s0; + ra = csf->ra; } - LOG_ERR("call trace:"); + for (int i = 0; (i < MAX_STACK_FRAMES) && vrfy(fp, thread, esf) && (fp > last_fp); i++) { + if (in_text_region(ra) && !cb(cookie, ra, fp)) { + break; + } + last_fp = fp; - for (int i = 0; (i < MAX_STACK_FRAMES) && (fp != 0U) && in_stack_bound(fp);) { + /* Unwind to the previous frame */ frame = (struct stackframe *)fp - 1; - ra = frame->ra; - if (in_text_region(ra)) { - LOG_ERR(" %2d: fp: " PR_REG " ra: " PR_REG, i, fp, ra); - /* - * Increment the iterator only if `ra` is within the text region to get the - * most out of it + + if ((i == 0) && (esf != NULL)) { + /* Print `esf->ra` if we are at the top of the stack */ + if (in_text_region(esf->ra) && !cb(cookie, esf->ra, fp)) { + break; + } + /** + * For the first stack frame, the `ra` is not stored in the frame if the + * preempted function doesn't call any other function, we can observe: + * + * .-------------. + * frame[0]->fp ---> | frame[0] fp | + * :-------------: + * frame[0]->ra ---> | frame[1] fp | + * | frame[1] ra | + * :~~~~~~~~~~~~~: + * | frame[N] fp | + * + * Instead of: + * + * .-------------. + * frame[0]->fp ---> | frame[0] fp | + * frame[0]->ra ---> | frame[1] ra | + * :-------------: + * | frame[1] fp | + * | frame[1] ra | + * :~~~~~~~~~~~~~: + * | frame[N] fp | + * + * Check if `frame->ra` actually points to a `fp`, and adjust accordingly */ - i++; + if (vrfy(frame->ra, thread, esf)) { + fp = frame->ra; + frame = (struct stackframe *)fp; + } } + fp = frame->fp; + ra = frame->ra; } - - LOG_ERR(""); } -#else /* !CONFIG_RISCV_ENABLE_FRAME_POINTER */ -void z_riscv_unwind_stack(const z_arch_esf_t *esf) +#else /* !CONFIG_FRAME_POINTER */ +register uintptr_t current_stack_pointer __asm__("sp"); +static void walk_stackframe(riscv_stacktrace_cb cb, void *cookie, const struct k_thread *thread, + const struct arch_esf *esf, stack_verify_fn vrfy, + const _callee_saved_t *csf) { - uintptr_t sp = z_riscv_get_sp_before_exc(esf); + uintptr_t sp; uintptr_t ra; - uintptr_t *ksp = (uintptr_t *)sp; + uintptr_t *ksp, last_ksp = 0; - if (esf == NULL) { - return; + if (esf != NULL) { + /* Unwind the provided exception stack frame */ + sp = z_riscv_get_sp_before_exc(esf); + ra = esf->mepc; + } else if ((csf == NULL) || (csf == &_current->callee_saved)) { + /* Unwind current thread (default case when nothing is provided ) */ + sp = current_stack_pointer; + ra = (uintptr_t)walk_stackframe; + } else { + /* Unwind the provided thread */ + sp = csf->sp; + ra = csf->ra; } - LOG_ERR("call trace:"); - - for (int i = 0; - (i < MAX_STACK_FRAMES) && ((uintptr_t)ksp != 0U) && in_stack_bound((uintptr_t)ksp); - ksp++) { - ra = *ksp; + ksp = (uintptr_t *)sp; + for (int i = 0; (i < MAX_STACK_FRAMES) && vrfy((uintptr_t)ksp, thread, esf) && + ((uintptr_t)ksp > last_ksp);) { if (in_text_region(ra)) { - LOG_ERR(" %2d: sp: " PR_REG " ra: " PR_REG, i, (uintptr_t)ksp, ra); + if (!cb(cookie, ra, POINTER_TO_UINT(ksp))) { + break; + } /* * Increment the iterator only if `ra` is within the text region to get the * most out of it */ i++; } + last_ksp = (uintptr_t)ksp; + /* Unwind to the previous frame */ + ra = ((struct arch_esf *)ksp++)->ra; + } +} +#endif /* CONFIG_FRAME_POINTER */ + +void arch_stack_walk(stack_trace_callback_fn callback_fn, void *cookie, + const struct k_thread *thread, const struct arch_esf *esf) +{ + if (thread == NULL) { + /* In case `thread` is NULL, default that to `_current` and try to unwind */ + thread = _current; + } + + walk_stackframe((riscv_stacktrace_cb)callback_fn, cookie, thread, esf, in_stack_bound, + &thread->callee_saved); +} + +#ifdef CONFIG_EXCEPTION_STACK_TRACE +static bool in_fatal_stack_bound(uintptr_t addr, const struct k_thread *const thread, + const struct arch_esf *esf) +{ + if (!IS_ALIGNED(addr, sizeof(uintptr_t))) { + return false; + } + + if ((thread == NULL) || arch_is_in_isr()) { + /* We were servicing an interrupt */ + uint8_t cpu_id = IS_ENABLED(CONFIG_SMP) ? arch_curr_cpu()->id : 0U; + + return in_irq_stack_bound(addr, cpu_id); } + return in_stack_bound(addr, thread, esf); +} + +#if __riscv_xlen == 32 +#define PR_REG "%08" PRIxPTR +#elif __riscv_xlen == 64 +#define PR_REG "%016" PRIxPTR +#endif + +#ifdef CONFIG_FRAME_POINTER +#define SFP "fp" +#else +#define SFP "sp" +#endif /* CONFIG_FRAME_POINTER */ + +#ifdef CONFIG_SYMTAB +#define LOG_STACK_TRACE(idx, sfp, ra, name, offset) \ + LOG_ERR(" %2d: " SFP ": " PR_REG " ra: " PR_REG " [%s+0x%x]", idx, sfp, ra, name, \ + offset) +#else +#define LOG_STACK_TRACE(idx, sfp, ra, name, offset) \ + LOG_ERR(" %2d: " SFP ": " PR_REG " ra: " PR_REG, idx, sfp, ra) +#endif /* CONFIG_SYMTAB */ + +static bool print_trace_address(void *arg, unsigned long ra, unsigned long sfp) +{ + int *i = arg; +#ifdef CONFIG_SYMTAB + uint32_t offset = 0; + const char *name = symtab_find_symbol_name(ra, &offset); +#endif /* CONFIG_SYMTAB */ + + LOG_STACK_TRACE((*i)++, sfp, ra, name, offset); + + return true; +} + +void z_riscv_unwind_stack(const struct arch_esf *esf, const _callee_saved_t *csf) +{ + int i = 0; + + LOG_ERR("call trace:"); + walk_stackframe(print_trace_address, &i, _current, esf, in_fatal_stack_bound, csf); LOG_ERR(""); } -#endif /* CONFIG_RISCV_ENABLE_FRAME_POINTER */ +#endif /* CONFIG_EXCEPTION_STACK_TRACE */ diff --git a/arch/riscv/core/thread.c b/arch/riscv/core/thread.c index de739f02895..59adbc42e46 100644 --- a/arch/riscv/core/thread.c +++ b/arch/riscv/core/thread.c @@ -23,15 +23,15 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, void *p1, void *p2, void *p3) { extern void z_riscv_thread_start(void); - struct __esf *stack_init; + struct arch_esf *stack_init; #ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE const struct soc_esf soc_esf_init = {SOC_ESF_INIT}; #endif /* Initial stack frame for thread */ - stack_init = (struct __esf *)Z_STACK_PTR_ALIGN( - Z_STACK_PTR_TO_FRAME(struct __esf, stack_ptr) + stack_init = (struct arch_esf *)Z_STACK_PTR_ALIGN( + Z_STACK_PTR_TO_FRAME(struct arch_esf, stack_ptr) ); /* Setup the initial stack frame */ @@ -144,6 +144,12 @@ FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry, K_KERNEL_STACK_RESERVED + CONFIG_PRIVILEGED_STACK_SIZE); +#ifdef CONFIG_INIT_STACKS + /* Initialize the privileged stack */ + (void)memset((void *)_current->arch.priv_stack_start, 0xaa, + Z_STACK_PTR_ALIGN(K_KERNEL_STACK_RESERVED + CONFIG_PRIVILEGED_STACK_SIZE)); +#endif /* CONFIG_INIT_STACKS */ + top_of_user_stack = Z_STACK_PTR_ALIGN( _current->stack_info.start + _current->stack_info.size - @@ -189,6 +195,18 @@ FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry, CODE_UNREACHABLE; } +int arch_thread_priv_stack_space_get(const struct k_thread *thread, size_t *stack_size, + size_t *unused_ptr) +{ + if ((thread->base.user_options & K_USER) != K_USER) { + return -EINVAL; + } + + *stack_size = Z_STACK_PTR_ALIGN(K_KERNEL_STACK_RESERVED + CONFIG_PRIVILEGED_STACK_SIZE); + + return z_stack_space_get((void *)thread->arch.priv_stack_start, *stack_size, unused_ptr); +} + #endif /* CONFIG_USERSPACE */ #ifndef CONFIG_MULTITHREADING diff --git a/arch/riscv/include/kernel_arch_func.h b/arch/riscv/include/kernel_arch_func.h index bdfc0527b95..c5ed6ff3f7f 100644 --- a/arch/riscv/include/kernel_arch_func.h +++ b/arch/riscv/include/kernel_arch_func.h @@ -71,9 +71,9 @@ arch_switch(void *switch_to, void **switched_from) /* Thin wrapper around z_riscv_fatal_error_csf */ FUNC_NORETURN void z_riscv_fatal_error(unsigned int reason, - const z_arch_esf_t *esf); + const struct arch_esf *esf); -FUNC_NORETURN void z_riscv_fatal_error_csf(unsigned int reason, const z_arch_esf_t *esf, +FUNC_NORETURN void z_riscv_fatal_error_csf(unsigned int reason, const struct arch_esf *esf, const _callee_saved_t *csf); static inline bool arch_is_in_isr(void) diff --git a/arch/riscv/include/offsets_short_arch.h b/arch/riscv/include/offsets_short_arch.h index 3d3a878f16e..27c01a77461 100644 --- a/arch/riscv/include/offsets_short_arch.h +++ b/arch/riscv/include/offsets_short_arch.h @@ -7,7 +7,7 @@ #ifndef ZEPHYR_ARCH_RISCV_INCLUDE_OFFSETS_SHORT_ARCH_H_ #define ZEPHYR_ARCH_RISCV_INCLUDE_OFFSETS_SHORT_ARCH_H_ -#include +#include #define _thread_offset_to_sp \ (___thread_t_callee_saved_OFFSET + ___callee_saved_t_sp_OFFSET) diff --git a/arch/riscv/include/pmp.h b/arch/riscv/include/pmp.h index 20877f14fd2..ca4f37f3a2a 100644 --- a/arch/riscv/include/pmp.h +++ b/arch/riscv/include/pmp.h @@ -10,6 +10,7 @@ void z_riscv_pmp_init(void); void z_riscv_pmp_stackguard_prepare(struct k_thread *thread); void z_riscv_pmp_stackguard_enable(struct k_thread *thread); +void z_riscv_pmp_stackguard_disable(void); void z_riscv_pmp_usermode_init(struct k_thread *thread); void z_riscv_pmp_usermode_prepare(struct k_thread *thread); void z_riscv_pmp_usermode_enable(struct k_thread *thread); diff --git a/arch/sparc/core/fatal.c b/arch/sparc/core/fatal.c index 55100606b92..40fd9d16792 100644 --- a/arch/sparc/core/fatal.c +++ b/arch/sparc/core/fatal.c @@ -122,7 +122,7 @@ static const struct { { .tt = 0x0A, .desc = "tag_overflow", }, }; -static void print_trap_type(const z_arch_esf_t *esf) +static void print_trap_type(const struct arch_esf *esf) { const int tt = (esf->tbr & TBR_TT) >> TBR_TT_BIT; const char *desc = "unknown"; @@ -142,7 +142,7 @@ static void print_trap_type(const z_arch_esf_t *esf) LOG_ERR("tt = 0x%02X, %s", tt, desc); } -static void print_integer_registers(const z_arch_esf_t *esf) +static void print_integer_registers(const struct arch_esf *esf) { const struct savearea *flushed = (struct savearea *) esf->out[6]; @@ -159,7 +159,7 @@ static void print_integer_registers(const z_arch_esf_t *esf) } } -static void print_special_registers(const z_arch_esf_t *esf) +static void print_special_registers(const struct arch_esf *esf) { LOG_ERR( "psr: %08x wim: %08x tbr: %08x y: %08x", @@ -168,7 +168,7 @@ static void print_special_registers(const z_arch_esf_t *esf) LOG_ERR(" pc: %08x npc: %08x", esf->pc, esf->npc); } -static void print_backtrace(const z_arch_esf_t *esf) +static void print_backtrace(const struct arch_esf *esf) { const int MAX_LOGLINES = 40; const struct savearea *s = (struct savearea *) esf->out[6]; @@ -190,7 +190,7 @@ static void print_backtrace(const z_arch_esf_t *esf) } } -static void print_all(const z_arch_esf_t *esf) +static void print_all(const struct arch_esf *esf) { LOG_ERR(""); print_trap_type(esf); @@ -205,7 +205,7 @@ static void print_all(const z_arch_esf_t *esf) #endif /* CONFIG_EXCEPTION_DEBUG */ FUNC_NORETURN void z_sparc_fatal_error(unsigned int reason, - const z_arch_esf_t *esf) + const struct arch_esf *esf) { #if CONFIG_EXCEPTION_DEBUG if (esf != NULL) { diff --git a/arch/sparc/core/fault_trap.S b/arch/sparc/core/fault_trap.S index c1a8977ba23..53b3d9f0b98 100644 --- a/arch/sparc/core/fault_trap.S +++ b/arch/sparc/core/fault_trap.S @@ -72,7 +72,7 @@ SECTION_FUNC(TEXT, __sparc_trap_except_reason) mov %l5, %g3 /* Allocate an ABI stack frame and exception stack frame */ - sub %fp, 96 + __z_arch_esf_t_SIZEOF, %sp + sub %fp, 96 + __struct_arch_esf_SIZEOF, %sp /* * %fp: %sp of interrupted task * %sp: %sp of interrupted task - ABI_frame - esf @@ -81,19 +81,19 @@ SECTION_FUNC(TEXT, __sparc_trap_except_reason) mov %l7, %o0 /* Fill in the content of the exception stack frame */ #if defined(CONFIG_EXTRA_EXCEPTION_INFO) - std %i0, [%sp + 96 + __z_arch_esf_t_out_OFFSET + 0x00] - std %i2, [%sp + 96 + __z_arch_esf_t_out_OFFSET + 0x08] - std %i4, [%sp + 96 + __z_arch_esf_t_out_OFFSET + 0x10] - std %i6, [%sp + 96 + __z_arch_esf_t_out_OFFSET + 0x18] - std %g0, [%sp + 96 + __z_arch_esf_t_global_OFFSET + 0x00] - std %g2, [%sp + 96 + __z_arch_esf_t_global_OFFSET + 0x08] - std %g4, [%sp + 96 + __z_arch_esf_t_global_OFFSET + 0x10] - std %g6, [%sp + 96 + __z_arch_esf_t_global_OFFSET + 0x18] + std %i0, [%sp + 96 + __struct_arch_esf_out_OFFSET + 0x00] + std %i2, [%sp + 96 + __struct_arch_esf_out_OFFSET + 0x08] + std %i4, [%sp + 96 + __struct_arch_esf_out_OFFSET + 0x10] + std %i6, [%sp + 96 + __struct_arch_esf_out_OFFSET + 0x18] + std %g0, [%sp + 96 + __struct_arch_esf_global_OFFSET + 0x00] + std %g2, [%sp + 96 + __struct_arch_esf_global_OFFSET + 0x08] + std %g4, [%sp + 96 + __struct_arch_esf_global_OFFSET + 0x10] + std %g6, [%sp + 96 + __struct_arch_esf_global_OFFSET + 0x18] #endif - std %l0, [%sp + 96 + __z_arch_esf_t_psr_OFFSET] /* psr pc */ - std %l2, [%sp + 96 + __z_arch_esf_t_npc_OFFSET] /* npc wim */ + std %l0, [%sp + 96 + __struct_arch_esf_psr_OFFSET] /* psr pc */ + std %l2, [%sp + 96 + __struct_arch_esf_npc_OFFSET] /* npc wim */ rd %y, %l7 - std %l6, [%sp + 96 + __z_arch_esf_t_tbr_OFFSET] /* tbr y */ + std %l6, [%sp + 96 + __struct_arch_esf_tbr_OFFSET] /* tbr y */ /* Enable traps, raise PIL to mask all maskable interrupts. */ or %l0, PSR_PIL, %o2 diff --git a/arch/sparc/core/irq_offload.c b/arch/sparc/core/irq_offload.c index cd5acc08ba2..f36e957084b 100644 --- a/arch/sparc/core/irq_offload.c +++ b/arch/sparc/core/irq_offload.c @@ -39,3 +39,7 @@ void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) irq_unlock(key); } + +void arch_irq_offload_init(void) +{ +} diff --git a/arch/sparc/core/offsets/offsets.c b/arch/sparc/core/offsets/offsets.c index 3796117ac09..023ef7452c4 100644 --- a/arch/sparc/core/offsets/offsets.c +++ b/arch/sparc/core/offsets/offsets.c @@ -31,11 +31,11 @@ GEN_OFFSET_SYM(_callee_saved_t, i6); GEN_OFFSET_SYM(_callee_saved_t, o6); /* esf member offsets */ -GEN_OFFSET_SYM(z_arch_esf_t, out); -GEN_OFFSET_SYM(z_arch_esf_t, global); -GEN_OFFSET_SYM(z_arch_esf_t, npc); -GEN_OFFSET_SYM(z_arch_esf_t, psr); -GEN_OFFSET_SYM(z_arch_esf_t, tbr); -GEN_ABSOLUTE_SYM(__z_arch_esf_t_SIZEOF, STACK_ROUND_UP(sizeof(z_arch_esf_t))); +GEN_OFFSET_STRUCT(arch_esf, out); +GEN_OFFSET_STRUCT(arch_esf, global); +GEN_OFFSET_STRUCT(arch_esf, npc); +GEN_OFFSET_STRUCT(arch_esf, psr); +GEN_OFFSET_STRUCT(arch_esf, tbr); +GEN_ABSOLUTE_SYM(__struct_arch_esf_SIZEOF, sizeof(struct arch_esf)); GEN_ABS_SYM_END diff --git a/arch/sparc/core/prep_c.c b/arch/sparc/core/prep_c.c index 9ad3955a190..5b4a440a63c 100644 --- a/arch/sparc/core/prep_c.c +++ b/arch/sparc/core/prep_c.c @@ -10,6 +10,8 @@ */ #include +#include +#include /** * @brief Prepare to and run C code @@ -19,7 +21,13 @@ void z_prep_c(void) { +#if defined(CONFIG_SOC_PREP_HOOK) + soc_prep_hook(); +#endif z_data_copy(); +#if CONFIG_ARCH_CACHE + arch_cache_init(); +#endif z_cstart(); CODE_UNREACHABLE; } diff --git a/arch/sparc/include/kernel_arch_func.h b/arch/sparc/include/kernel_arch_func.h index 41f48ccc44a..8b79b130ad6 100644 --- a/arch/sparc/include/kernel_arch_func.h +++ b/arch/sparc/include/kernel_arch_func.h @@ -43,7 +43,7 @@ static inline void arch_switch(void *switch_to, void **switched_from) } FUNC_NORETURN void z_sparc_fatal_error(unsigned int reason, - const z_arch_esf_t *esf); + const struct arch_esf *esf); static inline bool arch_is_in_isr(void) { diff --git a/arch/sparc/include/offsets_short_arch.h b/arch/sparc/include/offsets_short_arch.h index c53f2b3705b..0f9272f332b 100644 --- a/arch/sparc/include/offsets_short_arch.h +++ b/arch/sparc/include/offsets_short_arch.h @@ -7,7 +7,7 @@ #ifndef ZEPHYR_ARCH_SPARC_INCLUDE_OFFSETS_SHORT_ARCH_H_ #define ZEPHYR_ARCH_SPARC_INCLUDE_OFFSETS_SHORT_ARCH_H_ -#include +#include #define _thread_offset_to_y \ (___thread_t_callee_saved_OFFSET + ___callee_saved_t_y_OFFSET) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 487d6e94bd9..52ef70a0d13 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -205,7 +205,7 @@ config MAX_IRQ_LINES config IRQ_OFFLOAD_VECTOR int "IDT vector to use for IRQ offload" default 33 - range 32 255 + range 32 $(UINT8_MAX) depends on IRQ_OFFLOAD config PIC_DISABLE diff --git a/arch/x86/core/Kconfig.ia32 b/arch/x86/core/Kconfig.ia32 index d789c87eb80..75a3c2bbb7c 100644 --- a/arch/x86/core/Kconfig.ia32 +++ b/arch/x86/core/Kconfig.ia32 @@ -163,12 +163,15 @@ config X86_DYNAMIC_IRQ_STUBS endmenu -config X86_EXCEPTION_STACK_TRACE +config ARCH_HAS_STACKWALK bool default y - depends on EXCEPTION_STACK_TRACE + select DEBUG_INFO + select THREAD_STACK_INFO + depends on !OMIT_FRAME_POINTER help - Internal config to enable runtime stack traces on fatal exceptions. + Internal config to indicate that the arch_stack_walk() API is implemented + and it can be enabled. config X86_USE_THREAD_LOCAL_STORAGE bool diff --git a/arch/x86/core/Kconfig.intel64 b/arch/x86/core/Kconfig.intel64 index 2e6e7ebd00a..7b5359a7ecd 100644 --- a/arch/x86/core/Kconfig.intel64 +++ b/arch/x86/core/Kconfig.intel64 @@ -29,24 +29,27 @@ config X86_EXCEPTION_STACK_SIZE support limited call-tree depth and must fit into the low core, so they are typically smaller than the ISR stacks. -config X86_EXCEPTION_STACK_TRACE +config ARCH_HAS_STACKWALK bool default y - depends on EXCEPTION_STACK_TRACE + select DEBUG_INFO + select THREAD_STACK_INFO + depends on !OMIT_FRAME_POINTER depends on NO_OPTIMIZATIONS help - Internal config to enable runtime stack traces on fatal exceptions. + Internal config to indicate that the arch_stack_walk() API is implemented + and it can be enabled. config SCHED_IPI_VECTOR int "IDT vector to use for scheduler IPI" default 34 - range 33 255 + range 33 $(UINT8_MAX) depends on SMP config TLB_IPI_VECTOR int "IDT vector to use for TLB shootdown IPI" default 35 - range 33 255 + range 33 $(UINT8_MAX) depends on SMP # We should really only have to provide one of the following two values, diff --git a/arch/x86/core/cache.c b/arch/x86/core/cache.c index e80cb6d1dbf..476632115c1 100644 --- a/arch/x86/core/cache.c +++ b/arch/x86/core/cache.c @@ -119,3 +119,7 @@ int arch_dcache_flush_and_invd_range(void *start_addr, size_t size) { return arch_dcache_flush_range(start_addr, size); } + +void arch_cache_init(void) +{ +} diff --git a/arch/x86/core/common.S b/arch/x86/core/common.S index 1f390df42fb..07c0de8c8dc 100644 --- a/arch/x86/core/common.S +++ b/arch/x86/core/common.S @@ -22,9 +22,35 @@ */ cmpl $MULTIBOOT_EAX_MAGIC, %eax + +#ifndef CONFIG_DYNAMIC_BOOTARGS je 1f xorl %ebx, %ebx 1: +#else + movl $multiboot_cmdline, %edi + je setup_copy_cmdline + xorl %ebx, %ebx + jmp end_cmdline + +setup_copy_cmdline: + testl $MULTIBOOT_INFO_FLAGS_CMDLINE, __multiboot_info_t_flags_OFFSET(%ebx) + jz end_cmdline + + movl $multiboot_cmdline + CONFIG_BOOTARGS_ARGS_BUFFER_SIZE - 1, %edx + movl __multiboot_info_t_cmdline_OFFSET(%ebx), %esi +copy_cmdline: + cmpl %esi, %edx + je end_cmdline + cmpb $0, (%esi) + je end_cmdline + + movsb + jmp copy_cmdline +end_cmdline: + movb $0, (%edi) +#endif + #endif #ifdef CONFIG_PIC_DISABLE diff --git a/arch/x86/core/cpuhalt.c b/arch/x86/core/cpuhalt.c index 77c727bd3f9..b3f53a243e0 100644 --- a/arch/x86/core/cpuhalt.c +++ b/arch/x86/core/cpuhalt.c @@ -7,6 +7,7 @@ #include #include +#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_IDLE __pinned_func void arch_cpu_idle(void) { @@ -15,7 +16,9 @@ void arch_cpu_idle(void) "sti\n\t" "hlt\n\t"); } +#endif +#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE __pinned_func void arch_cpu_atomic_idle(unsigned int key) { @@ -42,3 +45,4 @@ void arch_cpu_atomic_idle(unsigned int key) __asm__ volatile("cli"); } } +#endif diff --git a/arch/x86/core/efi.c b/arch/x86/core/efi.c index 425b0dcde86..64faeb9efa5 100644 --- a/arch/x86/core/efi.c +++ b/arch/x86/core/efi.c @@ -18,6 +18,10 @@ static uint64_t __aligned(64) efi_stack[1024]; struct efi_boot_arg *efi; +#ifdef CONFIG_DYNAMIC_BOOTARGS +__pinned_noinit char efi_bootargs[CONFIG_BOOTARGS_ARGS_BUFFER_SIZE]; +#endif + void *efi_get_acpi_rsdp(void) { if (efi == NULL) { @@ -33,8 +37,8 @@ void efi_init(struct efi_boot_arg *efi_arg) return; } - z_phys_map((uint8_t **)&efi, (uintptr_t)efi_arg, - sizeof(struct efi_boot_arg), 0); + k_mem_map_phys_bare((uint8_t **)&efi, (uintptr_t)efi_arg, + sizeof(struct efi_boot_arg), 0); } /* EFI thunk. Not a lot of code, but lots of context: @@ -169,3 +173,10 @@ int arch_printk_char_out(int c) return efi_console_putchar(c); } #endif + +#ifdef CONFIG_DYNAMIC_BOOTARGS +const char *get_bootargs(void) +{ + return efi_bootargs; +} +#endif /* CONFIG_DYNAMIC_BOOTARGS */ diff --git a/arch/x86/core/fatal.c b/arch/x86/core/fatal.c index 370386d4af9..d43499a08d2 100644 --- a/arch/x86/core/fatal.c +++ b/arch/x86/core/fatal.c @@ -35,7 +35,7 @@ FUNC_NORETURN void arch_system_halt(unsigned int reason) #ifdef CONFIG_THREAD_STACK_INFO -static inline uintptr_t esf_get_sp(const z_arch_esf_t *esf) +static inline uintptr_t esf_get_sp(const struct arch_esf *esf) { #ifdef CONFIG_X86_64 return esf->rsp; @@ -84,7 +84,7 @@ bool z_x86_check_stack_bounds(uintptr_t addr, size_t size, uint16_t cs) return (addr <= start) || (addr + size > end); } -#endif +#endif /* CONFIG_THREAD_STACK_INFO */ #ifdef CONFIG_THREAD_STACK_MEM_MAPPED /** @@ -120,40 +120,37 @@ bool z_x86_check_guard_page(uintptr_t addr) } #endif /* CONFIG_THREAD_STACK_MEM_MAPPED */ -#ifdef CONFIG_EXCEPTION_DEBUG - -static inline uintptr_t esf_get_code(const z_arch_esf_t *esf) -{ -#ifdef CONFIG_X86_64 - return esf->code; -#else - return esf->errorCode; -#endif -} - -#if defined(CONFIG_X86_EXCEPTION_STACK_TRACE) +#if defined(CONFIG_ARCH_STACKWALK) struct stack_frame { uintptr_t next; uintptr_t ret_addr; -#ifndef CONFIG_X86_64 - uintptr_t args; -#endif }; -#define MAX_STACK_FRAMES 8 - -__pinned_func -static void unwind_stack(uintptr_t base_ptr, uint16_t cs) +__pinned_func static void walk_stackframe(stack_trace_callback_fn cb, void *cookie, + const struct arch_esf *esf, int max_frames) { + uintptr_t base_ptr; + uint16_t cs; struct stack_frame *frame; int i; + if (esf != NULL) { +#ifdef CONFIG_X86_64 + base_ptr = esf->rbp; +#else /* x86 32-bit */ + base_ptr = esf->ebp; +#endif /* CONFIG_X86_64 */ + cs = esf->cs; + } else { + return; + } + if (base_ptr == 0U) { LOG_ERR("NULL base ptr"); return; } - for (i = 0; i < MAX_STACK_FRAMES; i++) { + for (i = 0; i < max_frames; i++) { if (base_ptr % sizeof(base_ptr) != 0U) { LOG_ERR("unaligned frame ptr"); return; @@ -178,17 +175,58 @@ static void unwind_stack(uintptr_t base_ptr, uint16_t cs) if (frame->ret_addr == 0U) { break; } + + if (!cb(cookie, frame->ret_addr)) { + break; + } + + base_ptr = frame->next; + } +} + +void arch_stack_walk(stack_trace_callback_fn callback_fn, void *cookie, + const struct k_thread *thread, const struct arch_esf *esf) +{ + ARG_UNUSED(thread); + + walk_stackframe(callback_fn, cookie, esf, + CONFIG_ARCH_STACKWALK_MAX_FRAMES); +} +#endif /* CONFIG_ARCH_STACKWALK */ + +#if defined(CONFIG_EXCEPTION_STACK_TRACE) +static bool print_trace_address(void *arg, unsigned long addr) +{ + int *i = arg; + #ifdef CONFIG_X86_64 - LOG_ERR(" 0x%016lx", frame->ret_addr); + LOG_ERR(" %d: 0x%016lx", (*i)++, addr); #else - LOG_ERR(" 0x%08lx (0x%lx)", frame->ret_addr, frame->args); + LOG_ERR(" %d: 0x%08lx", (*i)++, addr); #endif - base_ptr = frame->next; - } + + return true; } -#endif /* CONFIG_X86_EXCEPTION_STACK_TRACE */ -static inline uintptr_t get_cr3(const z_arch_esf_t *esf) +static ALWAYS_INLINE void unwind_stack(const struct arch_esf *esf) +{ + int i = 0; + + walk_stackframe(print_trace_address, &i, esf, CONFIG_ARCH_STACKWALK_MAX_FRAMES); +} +#endif /* CONFIG_EXCEPTION_STACK_TRACE */ + +#ifdef CONFIG_EXCEPTION_DEBUG +static inline uintptr_t esf_get_code(const struct arch_esf *esf) +{ +#ifdef CONFIG_X86_64 + return esf->code; +#else + return esf->errorCode; +#endif +} + +static inline uintptr_t get_cr3(const struct arch_esf *esf) { #if defined(CONFIG_USERSPACE) && defined(CONFIG_X86_KPTI) /* If the interrupted thread was in user mode, we did a page table @@ -206,14 +244,14 @@ static inline uintptr_t get_cr3(const z_arch_esf_t *esf) return z_x86_cr3_get(); } -static inline pentry_t *get_ptables(const z_arch_esf_t *esf) +static inline pentry_t *get_ptables(const struct arch_esf *esf) { - return z_mem_virt_addr(get_cr3(esf)); + return k_mem_virt_addr(get_cr3(esf)); } #ifdef CONFIG_X86_64 __pinned_func -static void dump_regs(const z_arch_esf_t *esf) +static void dump_regs(const struct arch_esf *esf) { LOG_ERR("RAX: 0x%016lx RBX: 0x%016lx RCX: 0x%016lx RDX: 0x%016lx", esf->rax, esf->rbx, esf->rcx, esf->rdx); @@ -226,17 +264,11 @@ static void dump_regs(const z_arch_esf_t *esf) LOG_ERR("RSP: 0x%016lx RFLAGS: 0x%016lx CS: 0x%04lx CR3: 0x%016lx", esf->rsp, esf->rflags, esf->cs & 0xFFFFU, get_cr3(esf)); -#ifdef CONFIG_X86_EXCEPTION_STACK_TRACE - LOG_ERR("call trace:"); -#endif LOG_ERR("RIP: 0x%016lx", esf->rip); -#ifdef CONFIG_X86_EXCEPTION_STACK_TRACE - unwind_stack(esf->rbp, esf->cs); -#endif } #else /* 32-bit */ __pinned_func -static void dump_regs(const z_arch_esf_t *esf) +static void dump_regs(const struct arch_esf *esf) { LOG_ERR("EAX: 0x%08x, EBX: 0x%08x, ECX: 0x%08x, EDX: 0x%08x", esf->eax, esf->ebx, esf->ecx, esf->edx); @@ -245,13 +277,7 @@ static void dump_regs(const z_arch_esf_t *esf) LOG_ERR("EFLAGS: 0x%08x CS: 0x%04x CR3: 0x%08lx", esf->eflags, esf->cs & 0xFFFFU, get_cr3(esf)); -#ifdef CONFIG_X86_EXCEPTION_STACK_TRACE - LOG_ERR("call trace:"); -#endif LOG_ERR("EIP: 0x%08x", esf->eip); -#ifdef CONFIG_X86_EXCEPTION_STACK_TRACE - unwind_stack(esf->ebp, esf->cs); -#endif } #endif /* CONFIG_X86_64 */ @@ -327,7 +353,7 @@ static void log_exception(uintptr_t vector, uintptr_t code) } __pinned_func -static void dump_page_fault(z_arch_esf_t *esf) +static void dump_page_fault(struct arch_esf *esf) { uintptr_t err; void *cr2; @@ -362,12 +388,16 @@ static void dump_page_fault(z_arch_esf_t *esf) __pinned_func FUNC_NORETURN void z_x86_fatal_error(unsigned int reason, - const z_arch_esf_t *esf) + const struct arch_esf *esf) { if (esf != NULL) { #ifdef CONFIG_EXCEPTION_DEBUG dump_regs(esf); #endif +#ifdef CONFIG_EXCEPTION_STACK_TRACE + LOG_ERR("call trace:"); + unwind_stack(esf); +#endif /* CONFIG_EXCEPTION_STACK_TRACE */ #if defined(CONFIG_ASSERT) && defined(CONFIG_X86_64) if (esf->rip == 0xb9) { /* See implementation of __resume in locore.S. This is @@ -385,7 +415,7 @@ FUNC_NORETURN void z_x86_fatal_error(unsigned int reason, __pinned_func FUNC_NORETURN void z_x86_unhandled_cpu_exception(uintptr_t vector, - const z_arch_esf_t *esf) + const struct arch_esf *esf) { #ifdef CONFIG_EXCEPTION_DEBUG log_exception(vector, esf_get_code(esf)); @@ -404,7 +434,7 @@ static const struct z_exc_handle exceptions[] = { #endif __pinned_func -void z_x86_page_fault_handler(z_arch_esf_t *esf) +void z_x86_page_fault_handler(struct arch_esf *esf) { #ifdef CONFIG_DEMAND_PAGING if ((esf->errorCode & PF_P) == 0) { @@ -434,7 +464,7 @@ void z_x86_page_fault_handler(z_arch_esf_t *esf) } else #else { - was_valid_access = z_page_fault(virt); + was_valid_access = k_mem_page_fault(virt); } #endif /* CONFIG_X86_KPTI */ if (was_valid_access) { @@ -488,7 +518,7 @@ void z_x86_page_fault_handler(z_arch_esf_t *esf) } __pinned_func -void z_x86_do_kernel_oops(const z_arch_esf_t *esf) +void z_x86_do_kernel_oops(const struct arch_esf *esf) { uintptr_t reason; diff --git a/arch/x86/core/ia32/coredump.c b/arch/x86/core/ia32/coredump.c index b49373aab77..fb7d0fcfd8c 100644 --- a/arch/x86/core/ia32/coredump.c +++ b/arch/x86/core/ia32/coredump.c @@ -34,7 +34,7 @@ struct x86_arch_block { */ static struct x86_arch_block arch_blk; -void arch_coredump_info_dump(const z_arch_esf_t *esf) +void arch_coredump_info_dump(const struct arch_esf *esf) { struct coredump_arch_hdr_t hdr = { .id = COREDUMP_ARCH_HDR_ID, diff --git a/arch/x86/core/ia32/crt0.S b/arch/x86/core/ia32/crt0.S index 32513a95790..0c7ea821280 100644 --- a/arch/x86/core/ia32/crt0.S +++ b/arch/x86/core/ia32/crt0.S @@ -60,7 +60,7 @@ * Until we enable these page tables, only physical memory addresses * work. */ - movl $Z_MEM_PHYS_ADDR(z_x86_kernel_ptables), %eax + movl $K_MEM_PHYS_ADDR(z_x86_kernel_ptables), %eax movl %eax, %cr3 #ifdef CONFIG_X86_PAE @@ -89,7 +89,7 @@ orl $(CR0_PG | CR0_WP), %eax movl %eax, %cr0 -#ifdef Z_VM_KERNEL +#ifdef K_MEM_IS_VM_KERNEL /* Jump to a virtual address, which works because the identity and * virtual mappings both are to the same physical address. */ @@ -98,7 +98,7 @@ vm_enter: /* We are now executing in virtual memory. We'll un-map the identity * mappings later once we are in the C domain */ -#endif /* Z_VM_KERNEL */ +#endif /* K_MEM_IS_VM_KERNEL */ #endif /* CONFIG_X86_MMU */ .endm @@ -126,7 +126,7 @@ SECTION_FUNC(BOOT_TEXT, __start) */ #if CONFIG_SET_GDT /* load 32-bit operand size GDT */ - lgdt Z_MEM_PHYS_ADDR(_gdt_rom) + lgdt K_MEM_PHYS_ADDR(_gdt_rom) /* If we set our own GDT, update the segment registers as well. */ @@ -138,7 +138,7 @@ SECTION_FUNC(BOOT_TEXT, __start) movw %ax, %fs /* Zero FS */ movw %ax, %gs /* Zero GS */ - ljmp $CODE_SEG, $Z_MEM_PHYS_ADDR(__csSet) /* set CS = 0x08 */ + ljmp $CODE_SEG, $K_MEM_PHYS_ADDR(__csSet) /* set CS = 0x08 */ __csSet: #endif /* CONFIG_SET_GDT */ @@ -180,7 +180,8 @@ __csSet: andl $~0x400, %eax /* CR4[OSXMMEXCPT] = 0 */ movl %eax, %cr4 /* move EAX to CR4 */ - ldmxcsr Z_MEM_PHYS_ADDR(_sse_mxcsr_default_value) /* initialize SSE control/status reg */ + /* initialize SSE control/status reg */ + ldmxcsr K_MEM_PHYS_ADDR(_sse_mxcsr_default_value) #endif /* CONFIG_X86_SSE */ @@ -199,7 +200,7 @@ __csSet: */ #ifdef CONFIG_INIT_STACKS movl $0xAAAAAAAA, %eax - leal Z_MEM_PHYS_ADDR(z_interrupt_stacks), %edi + leal K_MEM_PHYS_ADDR(z_interrupt_stacks), %edi #ifdef CONFIG_X86_STACK_PROTECTION addl $4096, %edi #endif @@ -208,7 +209,7 @@ __csSet: rep stosl #endif - movl $Z_MEM_PHYS_ADDR(z_interrupt_stacks), %esp + movl $K_MEM_PHYS_ADDR(z_interrupt_stacks), %esp #ifdef CONFIG_X86_STACK_PROTECTION /* In this configuration, all stacks, including IRQ stack, are declared * with a 4K non-present guard page preceding the stack buffer @@ -243,7 +244,7 @@ __csSet: ltr %ax #endif -#ifdef Z_VM_KERNEL +#ifdef K_MEM_IS_VM_KERNEL /* Need to reset the stack to virtual address after * page table is loaded. */ @@ -254,7 +255,7 @@ __csSet: #else addl $CONFIG_ISR_STACK_SIZE, %esp #endif -#endif /* Z_VM_KERNEL */ +#endif /* K_MEM_IS_VM_KERNEL */ #ifdef CONFIG_THREAD_LOCAL_STORAGE pushl %esp @@ -272,7 +273,7 @@ __csSet: /* Don't clear BSS if the section is not present * in memory at boot. Or else it would cause page * faults. Zeroing BSS will be done later once the - * the paging mechanism has been initialized. + * paging mechanism has been initialized. */ call z_bss_zero #endif @@ -347,9 +348,9 @@ _gdt: * descriptor here */ /* Limit on GDT */ - .word Z_MEM_PHYS_ADDR(_gdt_rom_end) - Z_MEM_PHYS_ADDR(_gdt_rom) - 1 + .word K_MEM_PHYS_ADDR(_gdt_rom_end) - K_MEM_PHYS_ADDR(_gdt_rom) - 1 /* table address: _gdt_rom */ - .long Z_MEM_PHYS_ADDR(_gdt_rom) + .long K_MEM_PHYS_ADDR(_gdt_rom) .word 0x0000 /* Entry 1 (selector=0x0008): Code descriptor: DPL0 */ diff --git a/arch/x86/core/ia32/excstub.S b/arch/x86/core/ia32/excstub.S index 9c5f3f03191..6c0a13a37cd 100644 --- a/arch/x86/core/ia32/excstub.S +++ b/arch/x86/core/ia32/excstub.S @@ -161,12 +161,12 @@ SECTION_FUNC(PINNED_TEXT, _exception_enter) /* ESP is still pointing to the ESF at this point */ - testl $0x200, __z_arch_esf_t_eflags_OFFSET(%esp) + testl $0x200, __struct_arch_esf_eflags_OFFSET(%esp) je allDone sti allDone: - pushl %esp /* push z_arch_esf_t * parameter */ + pushl %esp /* push struct_arch_esf * parameter */ call *%ecx /* call exception handler */ addl $0x4, %esp diff --git a/arch/x86/core/ia32/fatal.c b/arch/x86/core/ia32/fatal.c index 597f21a01ad..3ae8a6b67da 100644 --- a/arch/x86/core/ia32/fatal.c +++ b/arch/x86/core/ia32/fatal.c @@ -27,10 +27,10 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); unsigned int z_x86_exception_vector; #endif -__weak void z_debug_fatal_hook(const z_arch_esf_t *esf) { ARG_UNUSED(esf); } +__weak void z_debug_fatal_hook(const struct arch_esf *esf) { ARG_UNUSED(esf); } __pinned_func -void z_x86_spurious_irq(const z_arch_esf_t *esf) +void z_x86_spurious_irq(const struct arch_esf *esf) { int vector = z_irq_controller_isr_vector_get(); @@ -46,7 +46,7 @@ void arch_syscall_oops(void *ssf) { struct _x86_syscall_stack_frame *ssf_ptr = (struct _x86_syscall_stack_frame *)ssf; - z_arch_esf_t oops = { + struct arch_esf oops = { .eip = ssf_ptr->eip, .cs = ssf_ptr->cs, .eflags = ssf_ptr->eflags @@ -66,7 +66,7 @@ NANO_CPU_INT_REGISTER(_kernel_oops_handler, NANO_SOFT_IRQ, #if CONFIG_EXCEPTION_DEBUG __pinned_func FUNC_NORETURN static void generic_exc_handle(unsigned int vector, - const z_arch_esf_t *pEsf) + const struct arch_esf *pEsf) { #ifdef CONFIG_DEBUG_COREDUMP z_x86_exception_vector = vector; @@ -77,7 +77,7 @@ FUNC_NORETURN static void generic_exc_handle(unsigned int vector, #define _EXC_FUNC(vector) \ __pinned_func \ -FUNC_NORETURN __used static void handle_exc_##vector(const z_arch_esf_t *pEsf) \ +FUNC_NORETURN __used static void handle_exc_##vector(const struct arch_esf *pEsf) \ { \ generic_exc_handle(vector, pEsf); \ } @@ -120,7 +120,7 @@ EXC_FUNC_NOCODE(IV_MACHINE_CHECK, 0); _EXCEPTION_CONNECT_CODE(z_x86_page_fault_handler, IV_PAGE_FAULT, 0); #ifdef CONFIG_X86_ENABLE_TSS -static __pinned_noinit volatile z_arch_esf_t _df_esf; +static __pinned_noinit volatile struct arch_esf _df_esf; /* Very tiny stack; just enough for the bogus error code pushed by the CPU * and a frame pointer push by the compiler. All df_handler_top does is @@ -156,7 +156,7 @@ struct task_state_segment _df_tss = { .ss = DATA_SEG, .eip = (uint32_t)df_handler_top, .cr3 = (uint32_t) - Z_MEM_PHYS_ADDR(POINTER_TO_UINT(&z_x86_kernel_ptables[0])) + K_MEM_PHYS_ADDR(POINTER_TO_UINT(&z_x86_kernel_ptables[0])) }; __pinned_func @@ -182,14 +182,14 @@ static __used void df_handler_bottom(void) reason = K_ERR_STACK_CHK_FAIL; } #endif - z_x86_fatal_error(reason, (z_arch_esf_t *)&_df_esf); + z_x86_fatal_error(reason, (struct arch_esf *)&_df_esf); } __pinned_func static FUNC_NORETURN __used void df_handler_top(void) { /* State of the system when the double-fault forced a task switch - * will be in _main_tss. Set up a z_arch_esf_t and copy system state into + * will be in _main_tss. Set up a struct arch_esf and copy system state into * it */ _df_esf.esp = _main_tss.esp; @@ -213,7 +213,7 @@ static FUNC_NORETURN __used void df_handler_top(void) _main_tss.es = DATA_SEG; _main_tss.ss = DATA_SEG; _main_tss.eip = (uint32_t)df_handler_bottom; - _main_tss.cr3 = z_mem_phys_addr(z_x86_kernel_ptables); + _main_tss.cr3 = k_mem_phys_addr(z_x86_kernel_ptables); _main_tss.eflags = 0U; /* NT bit is set in EFLAGS so we will task switch back to _main_tss diff --git a/arch/x86/core/ia32/float.c b/arch/x86/core/ia32/float.c index a33a40a0a78..c89bf7accd5 100644 --- a/arch/x86/core/ia32/float.c +++ b/arch/x86/core/ia32/float.c @@ -302,7 +302,7 @@ int z_float_disable(struct k_thread *thread) * instruction is executed while CR0[TS]=1. The handler then enables the * current thread to use all supported floating point registers. */ -void _FpNotAvailableExcHandler(z_arch_esf_t *pEsf) +void _FpNotAvailableExcHandler(struct arch_esf *pEsf) { ARG_UNUSED(pEsf); diff --git a/arch/x86/core/ia32/gdbstub.c b/arch/x86/core/ia32/gdbstub.c index 692ea78baf4..252f15d79ff 100644 --- a/arch/x86/core/ia32/gdbstub.c +++ b/arch/x86/core/ia32/gdbstub.c @@ -78,7 +78,7 @@ static unsigned int get_exception(unsigned int vector) /* * Debug exception handler. */ -static void z_gdb_interrupt(unsigned int vector, z_arch_esf_t *esf) +static void z_gdb_interrupt(unsigned int vector, struct arch_esf *esf) { debug_ctx.exception = get_exception(vector); @@ -212,7 +212,7 @@ size_t arch_gdb_reg_writeone(struct gdb_ctx *ctx, uint8_t *hex, size_t hexlen, return ret; } -static __used void z_gdb_debug_isr(z_arch_esf_t *esf) +static __used void z_gdb_debug_isr(struct arch_esf *esf) { #ifdef CONFIG_GDBSTUB_TRACE printk("gdbstub:enter %s (IV_DEBUG)\n", __func__); @@ -225,7 +225,7 @@ static __used void z_gdb_debug_isr(z_arch_esf_t *esf) #endif } -static __used void z_gdb_break_isr(z_arch_esf_t *esf) +static __used void z_gdb_break_isr(struct arch_esf *esf) { #ifdef CONFIG_GDBSTUB_TRACE printk("gdbstub:enter %s (IV_BREAKPOINT)\n", __func__); diff --git a/arch/x86/core/ia32/intstub.S b/arch/x86/core/ia32/intstub.S index 0dc08c67c24..dd454670dd8 100644 --- a/arch/x86/core/ia32/intstub.S +++ b/arch/x86/core/ia32/intstub.S @@ -33,7 +33,7 @@ GTEXT(arch_swap) #ifdef CONFIG_PM - GTEXT(z_pm_save_idle_exit) + GTEXT(pm_system_resume) #endif /** @@ -112,11 +112,12 @@ SECTION_FUNC(PINNED_TEXT, _interrupt_enter) * EAX = isr_param, EDX = isr */ - /* Push EDI as we will use it for scratch space. + /* Push EBP as we will use it for scratch space. + * Also it helps in stack unwinding * Rest of the callee-saved regs get saved by invocation of C * functions (isr handler, arch_swap(), etc) */ - pushl %edi + pushl %ebp /* load %ecx with &_kernel */ @@ -131,17 +132,17 @@ SECTION_FUNC(PINNED_TEXT, _interrupt_enter) jne alreadyOnIntStack /* - * switch to base of the interrupt stack: save esp in edi, then load + * switch to base of the interrupt stack: save esp in ebp, then load * irq_stack pointer */ - movl %esp, %edi + movl %esp, %ebp movl _kernel_offset_to_irq_stack(%ecx), %esp /* save thread's stack pointer onto base of interrupt stack */ - pushl %edi /* Save stack pointer */ + pushl %ebp /* Save stack pointer */ #ifdef CONFIG_PM cmpl $0, _kernel_offset_to_idle(%ecx) @@ -265,7 +266,7 @@ alreadyOnIntStack: #endif /* CONFIG_LAZY_FPU_SHARING */ /* Restore volatile registers and return to the interrupted thread */ - popl %edi + popl %ebp popl %ecx popl %edx popl %eax @@ -298,7 +299,7 @@ noReschedule: */ nestedInterrupt: - popl %edi + popl %ebp popl %ecx /* pop volatile registers in reverse order */ popl %edx popl %eax @@ -314,13 +315,13 @@ handle_idle: movl $0, _kernel_offset_to_idle(%ecx) /* - * Beware that a timer driver's z_pm_save_idle_exit() implementation might + * Beware that a timer driver's pm_system_resume() implementation might * expect that interrupts are disabled when invoked. This ensures that * the calculation and programming of the device for the next timer * deadline is not interrupted. */ - call z_pm_save_idle_exit + call pm_system_resume popl %edx popl %eax jmp alreadyOnIntStack diff --git a/arch/x86/core/ia32/irq_offload.c b/arch/x86/core/ia32/irq_offload.c index 71e8363ece3..c7d68b34370 100644 --- a/arch/x86/core/ia32/irq_offload.c +++ b/arch/x86/core/ia32/irq_offload.c @@ -47,3 +47,7 @@ void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) irq_unlock(key); } + +void arch_irq_offload_init(void) +{ +} diff --git a/arch/x86/core/ia32/userspace.S b/arch/x86/core/ia32/userspace.S index bf21a0cc1a2..a4ad4c69fb8 100644 --- a/arch/x86/core/ia32/userspace.S +++ b/arch/x86/core/ia32/userspace.S @@ -51,7 +51,7 @@ SECTION_FUNC(PINNED_TEXT, z_x86_trampoline_to_kernel) pushl %edi /* Switch to kernel page table */ - movl $Z_MEM_PHYS_ADDR(z_x86_kernel_ptables), %esi + movl $K_MEM_PHYS_ADDR(z_x86_kernel_ptables), %esi movl %esi, %cr3 /* Save old trampoline stack pointer in %edi */ @@ -156,7 +156,7 @@ SECTION_FUNC(TEXT, z_x86_syscall_entry_stub) pushl %edi /* Switch to kernel page table */ - movl $Z_MEM_PHYS_ADDR(z_x86_kernel_ptables), %esi + movl $K_MEM_PHYS_ADDR(z_x86_kernel_ptables), %esi movl %esi, %cr3 /* Save old trampoline stack pointer in %edi */ diff --git a/arch/x86/core/intel64/coredump.c b/arch/x86/core/intel64/coredump.c index f1c1a15eaff..65a9306ca07 100644 --- a/arch/x86/core/intel64/coredump.c +++ b/arch/x86/core/intel64/coredump.c @@ -46,7 +46,7 @@ struct x86_64_arch_block { */ static struct x86_64_arch_block arch_blk; -void arch_coredump_info_dump(const z_arch_esf_t *esf) +void arch_coredump_info_dump(const struct arch_esf *esf) { struct coredump_arch_hdr_t hdr = { .id = COREDUMP_ARCH_HDR_ID, diff --git a/arch/x86/core/intel64/fatal.c b/arch/x86/core/intel64/fatal.c index 9dd97614dc1..9eed95bfaa3 100644 --- a/arch/x86/core/intel64/fatal.c +++ b/arch/x86/core/intel64/fatal.c @@ -13,14 +13,14 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); /* NMI handlers should override weak implementation * return true if NMI is handled, false otherwise */ -__weak bool z_x86_do_kernel_nmi(const z_arch_esf_t *esf) +__weak bool z_x86_do_kernel_nmi(const struct arch_esf *esf) { ARG_UNUSED(esf); return false; } -void z_x86_exception(z_arch_esf_t *esf) +void z_x86_exception(struct arch_esf *esf) { switch (esf->vector) { case Z_X86_OOPS_VECTOR: diff --git a/arch/x86/core/intel64/irq.c b/arch/x86/core/intel64/irq.c index f8e251b8046..51410646dba 100644 --- a/arch/x86/core/intel64/irq.c +++ b/arch/x86/core/intel64/irq.c @@ -100,8 +100,8 @@ void z_x86_irq_connect_on_vector(unsigned int irq, */ int arch_irq_connect_dynamic(unsigned int irq, unsigned int priority, - void (*func)(const void *arg), - const void *arg, uint32_t flags) + void (*routine)(const void *parameter), + const void *parameter, uint32_t flags) { uint32_t key; int vector; @@ -124,7 +124,7 @@ int arch_irq_connect_dynamic(unsigned int irq, unsigned int priority, #endif /* CONFIG_INTEL_VTD_ICTL */ z_irq_controller_irq_config(vector, irq, flags); - z_x86_irq_connect_on_vector(irq, vector, func, arg); + z_x86_irq_connect_on_vector(irq, vector, routine, parameter); } irq_unlock(key); diff --git a/arch/x86/core/intel64/irq_offload.c b/arch/x86/core/intel64/irq_offload.c index 0146321f7d9..03ae8a9439b 100644 --- a/arch/x86/core/intel64/irq_offload.c +++ b/arch/x86/core/intel64/irq_offload.c @@ -9,6 +9,7 @@ */ #include +#include #include #include @@ -17,12 +18,33 @@ extern void (*x86_irq_funcs[NR_IRQ_VECTORS])(const void *arg); extern const void *x86_irq_args[NR_IRQ_VECTORS]; +static void (*irq_offload_funcs[CONFIG_MP_NUM_CPUS])(const void *arg); +static const void *irq_offload_args[CONFIG_MP_NUM_CPUS]; + +static void dispatcher(const void *arg) +{ + uint8_t cpu_id = _current_cpu->id; + + if (irq_offload_funcs[cpu_id] != NULL) { + irq_offload_funcs[cpu_id](irq_offload_args[cpu_id]); + } +} void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) { - x86_irq_funcs[CONFIG_IRQ_OFFLOAD_VECTOR - IV_IRQS] = routine; - x86_irq_args[CONFIG_IRQ_OFFLOAD_VECTOR - IV_IRQS] = parameter; + int key = arch_irq_lock(); + uint8_t cpu_id = _current_cpu->id; + + irq_offload_funcs[cpu_id] = routine; + irq_offload_args[cpu_id] = parameter; + __asm__ volatile("int %0" : : "i" (CONFIG_IRQ_OFFLOAD_VECTOR) : "memory"); - x86_irq_funcs[CONFIG_IRQ_OFFLOAD_VECTOR - IV_IRQS] = NULL; + + arch_irq_unlock(key); +} + +void arch_irq_offload_init(void) +{ + x86_irq_funcs[CONFIG_IRQ_OFFLOAD_VECTOR - IV_IRQS] = dispatcher; } diff --git a/arch/x86/core/intel64/locore.S b/arch/x86/core/intel64/locore.S index 68f89c90398..108d9f15d37 100644 --- a/arch/x86/core/intel64/locore.S +++ b/arch/x86/core/intel64/locore.S @@ -44,7 +44,7 @@ /* Page tables created at build time by gen_mmu.py * NOTE: Presumes phys=virt */ - movl $Z_MEM_PHYS_ADDR(z_x86_kernel_ptables), %eax + movl $K_MEM_PHYS_ADDR(z_x86_kernel_ptables), %eax movl %eax, %cr3 set_efer @@ -66,7 +66,7 @@ clts /* NOTE: Presumes phys=virt */ - movq $Z_MEM_PHYS_ADDR(z_x86_kernel_ptables), %rax + movq $K_MEM_PHYS_ADDR(z_x86_kernel_ptables), %rax movq %rax, %cr3 set_efer diff --git a/arch/x86/core/intel64/smp.c b/arch/x86/core/intel64/smp.c index a73ba9c8f38..1e0aeb3e443 100644 --- a/arch/x86/core/intel64/smp.c +++ b/arch/x86/core/intel64/smp.c @@ -34,9 +34,7 @@ int arch_smp_init(void) * it is not clear exactly how/where/why to abstract this, as it * assumes the use of a local APIC (but there's no other mechanism). */ -void arch_sched_ipi(void) +void arch_sched_broadcast_ipi(void) { z_loapic_ipi(0, LOAPIC_ICR_IPI_OTHERS, CONFIG_SCHED_IPI_VECTOR); } - -SYS_INIT(arch_smp_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); diff --git a/arch/x86/core/intel64/userspace.S b/arch/x86/core/intel64/userspace.S index ab09381c7af..d3610c300cb 100644 --- a/arch/x86/core/intel64/userspace.S +++ b/arch/x86/core/intel64/userspace.S @@ -87,7 +87,7 @@ z_x86_syscall_entry_stub: pushq %rax /* NOTE: Presumes phys=virt */ - movq $Z_MEM_PHYS_ADDR(z_x86_kernel_ptables), %rax + movq $K_MEM_PHYS_ADDR(z_x86_kernel_ptables), %rax movq %rax, %cr3 popq %rax movq $0, -8(%rsp) /* Delete stashed RAX data */ diff --git a/arch/x86/core/legacy_bios.c b/arch/x86/core/legacy_bios.c index 6a7159a9b1c..6245a6175c5 100644 --- a/arch/x86/core/legacy_bios.c +++ b/arch/x86/core/legacy_bios.c @@ -17,18 +17,18 @@ static uintptr_t bios_search_rsdp_buff(uintptr_t search_phy_add, uint32_t search { uint64_t *search_buff; - z_phys_map((uint8_t **)&search_buff, search_phy_add, search_length, 0); + k_mem_map_phys_bare((uint8_t **)&search_buff, search_phy_add, search_length, 0); if (!search_buff) { return 0; } for (int i = 0; i < search_length / 8u; i++) { if (search_buff[i] == RSDP_SIGNATURE) { - z_phys_unmap((uint8_t *)search_buff, search_length); + k_mem_unmap_phys_bare((uint8_t *)search_buff, search_length); return (search_phy_add + (i * 8u)); } } - z_phys_unmap((uint8_t *)search_buff, search_length); + k_mem_unmap_phys_bare((uint8_t *)search_buff, search_length); return 0; } @@ -38,10 +38,10 @@ void *bios_acpi_rsdp_get(void) uint8_t *bios_ext_data, *zero_page_base; uintptr_t search_phy_add, rsdp_phy_add; - z_phys_map(&zero_page_base, 0, DATA_SIZE_K(4u), 0); + k_mem_map_phys_bare(&zero_page_base, 0, DATA_SIZE_K(4u), 0); bios_ext_data = EBDA_ADD + zero_page_base; search_phy_add = (uintptr_t)((*(uint16_t *)bios_ext_data) << 4u); - z_phys_unmap(zero_page_base, DATA_SIZE_K(4u)); + k_mem_unmap_phys_bare(zero_page_base, DATA_SIZE_K(4u)); if ((search_phy_add >= BIOS_EXT_DATA_LOW) && (search_phy_add < BIOS_EXT_DATA_HIGH)) { rsdp_phy_add = bios_search_rsdp_buff(search_phy_add, DATA_SIZE_K(1u)); diff --git a/arch/x86/core/multiboot.c b/arch/x86/core/multiboot.c index 2dab56128d1..b6112b75f82 100644 --- a/arch/x86/core/multiboot.c +++ b/arch/x86/core/multiboot.c @@ -11,6 +11,15 @@ struct multiboot_info multiboot_info; +#ifdef CONFIG_DYNAMIC_BOOTARGS +__pinned_noinit char multiboot_cmdline[CONFIG_BOOTARGS_ARGS_BUFFER_SIZE]; + +const char *get_bootargs(void) +{ + return multiboot_cmdline; +} +#endif /* CONFIG_DYNAMIC_BOOTARGS */ + /* * called very early in the boot process to fetch data out of the multiboot * info struct. we need to grab the relevant data before any dynamic memory @@ -41,8 +50,8 @@ void z_multiboot_init(struct multiboot_info *info_pa) */ info = info_pa; #else - z_phys_map((uint8_t **)&info, POINTER_TO_UINT(info_pa), - sizeof(*info_pa), K_MEM_CACHE_NONE); + k_mem_map_phys_bare((uint8_t **)&info, POINTER_TO_UINT(info_pa), + sizeof(*info_pa), K_MEM_CACHE_NONE); #endif /* CONFIG_ARCH_MAPS_ALL_RAM */ if (info == NULL) { @@ -70,8 +79,8 @@ void z_multiboot_init(struct multiboot_info *info_pa) #else uint8_t *address_va; - z_phys_map(&address_va, info->mmap_addr, info->mmap_length, - K_MEM_CACHE_NONE); + k_mem_map_phys_bare(&address_va, info->mmap_addr, info->mmap_length, + K_MEM_CACHE_NONE); address = POINTER_TO_UINT(address_va); #endif /* CONFIG_ARCH_MAPS_ALL_RAM */ diff --git a/arch/x86/core/offsets/ia32_offsets.c b/arch/x86/core/offsets/ia32_offsets.c index 61a7f25bb2a..2dfbb5c38ef 100644 --- a/arch/x86/core/offsets/ia32_offsets.c +++ b/arch/x86/core/offsets/ia32_offsets.c @@ -52,7 +52,6 @@ GEN_ABSOLUTE_SYM(_K_THREAD_NO_FLOAT_SIZEOF, GEN_OFFSET_SYM(_callee_saved_t, esp); -/* z_arch_esf_t structure member offsets */ - -GEN_OFFSET_SYM(z_arch_esf_t, eflags); +/* struct arch_esf structure member offsets */ +GEN_OFFSET_STRUCT(arch_esf, eflags); #endif /* _X86_OFFSETS_INC_ */ diff --git a/arch/x86/core/offsets/offsets.c b/arch/x86/core/offsets/offsets.c index 53b432e74cb..2e6b323fa7c 100644 --- a/arch/x86/core/offsets/offsets.c +++ b/arch/x86/core/offsets/offsets.c @@ -14,9 +14,18 @@ #include "ia32_offsets.c" #endif +#ifdef CONFIG_MULTIBOOT_INFO +#include +#endif + GEN_OFFSET_SYM(x86_boot_arg_t, boot_type); GEN_OFFSET_SYM(x86_boot_arg_t, arg); GEN_OFFSET_SYM(_thread_arch_t, flags); +#ifdef CONFIG_MULTIBOOT_INFO +GEN_OFFSET_SYM(multiboot_info_t, flags); +GEN_OFFSET_SYM(multiboot_info_t, cmdline); +#endif + GEN_ABS_SYM_END diff --git a/arch/x86/core/prep_c.c b/arch/x86/core/prep_c.c index d9b62b0b711..96c76f6af26 100644 --- a/arch/x86/core/prep_c.c +++ b/arch/x86/core/prep_c.c @@ -9,6 +9,8 @@ #include #include #include +#include +#include extern FUNC_NORETURN void z_cstart(void); extern void x86_64_irq_init(void); @@ -17,6 +19,10 @@ extern void x86_64_irq_init(void); __pinned_data x86_boot_arg_t x86_cpu_boot_arg; #endif + + +extern int spec_ctrl_init(void); + /* Early global initialization functions, C domain. This runs only on the first * CPU for SMP systems. */ @@ -25,6 +31,9 @@ FUNC_NORETURN void z_prep_c(void *arg) { x86_boot_arg_t *cpu_arg = arg; +#if defined(CONFIG_SOC_PREP_HOOK) + soc_prep_hook(); +#endif _kernel.cpus[0].nested = 0; #ifdef CONFIG_MMU @@ -72,9 +81,11 @@ FUNC_NORETURN void z_prep_c(void *arg) z_x86_set_stack_guard(z_interrupt_stacks[i]); } #endif - -#if defined(CONFIG_SMP) - arch_smp_init(); +#if CONFIG_ARCH_CACHE + arch_cache_init(); +#endif +#if defined(CONFIG_X86_DISABLE_SSBD) || defined(CONFIG_X86_ENABLE_EXTENDED_IBRS) + spec_ctrl_init(); #endif z_cstart(); diff --git a/arch/x86/core/spec_ctrl.c b/arch/x86/core/spec_ctrl.c index 50daa74bd1a..f5358e596ee 100644 --- a/arch/x86/core/spec_ctrl.c +++ b/arch/x86/core/spec_ctrl.c @@ -17,7 +17,7 @@ */ #if defined(CONFIG_X86_DISABLE_SSBD) || defined(CONFIG_X86_ENABLE_EXTENDED_IBRS) -static int spec_ctrl_init(void) +int spec_ctrl_init(void) { uint32_t enable_bits = 0U; @@ -43,5 +43,4 @@ static int spec_ctrl_init(void) return 0; } -SYS_INIT(spec_ctrl_init, PRE_KERNEL_1, 0); #endif /* CONFIG_X86_DISABLE_SSBD || CONFIG_X86_ENABLE_EXTENDED_IBRS */ diff --git a/arch/x86/core/userspace.c b/arch/x86/core/userspace.c index dbe40b2bda0..436bc18edb7 100644 --- a/arch/x86/core/userspace.c +++ b/arch/x86/core/userspace.c @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + #include #include #include @@ -70,15 +72,18 @@ void *z_x86_userspace_prepare_thread(struct k_thread *thread) { void *initial_entry; - struct z_x86_thread_stack_header *header = + if (z_stack_is_user_capable(thread->stack_obj)) { + struct z_x86_thread_stack_header *header = #ifdef CONFIG_THREAD_STACK_MEM_MAPPED - (struct z_x86_thread_stack_header *)thread->stack_info.mapped.addr; + (struct z_x86_thread_stack_header *)thread->stack_info.mapped.addr; #else - (struct z_x86_thread_stack_header *)thread->stack_obj; + (struct z_x86_thread_stack_header *)thread->stack_obj; #endif /* CONFIG_THREAD_STACK_MEM_MAPPED */ - thread->arch.psp = - header->privilege_stack + sizeof(header->privilege_stack); + thread->arch.psp = header->privilege_stack + sizeof(header->privilege_stack); + } else { + thread->arch.psp = NULL; + } #ifndef CONFIG_X86_COMMON_PAGE_TABLE /* Important this gets cleared, so that arch_mem_domain_* APIs @@ -90,6 +95,28 @@ void *z_x86_userspace_prepare_thread(struct k_thread *thread) if ((thread->base.user_options & K_USER) != 0U) { initial_entry = arch_user_mode_enter; + +#ifdef CONFIG_INIT_STACKS + /* setup_thread_stack() does not initialize the architecture specific + * privileged stack. So we need to do it manually here as this function + * is called by arch_new_thread() via z_setup_new_thread() after + * setup_thread_stack() but before thread starts running. + * + * Note that only user threads have privileged stacks and kernel + * only threads do not. + * + * Also note that this needs to be done before calling + * z_x86_userspace_enter() where it clears the user stack. + * That function requires using the privileged stack for + * code execution so we cannot clear that at the same time. + */ + struct z_x86_thread_stack_header *hdr_stack_obj = + (struct z_x86_thread_stack_header *)thread->stack_obj; + + (void)memset(&hdr_stack_obj->privilege_stack[0], 0xaa, + sizeof(hdr_stack_obj->privilege_stack)); +#endif + } else { initial_entry = z_thread_entry; } @@ -158,3 +185,19 @@ FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry, _current->stack_info.start); CODE_UNREACHABLE; } + +int arch_thread_priv_stack_space_get(const struct k_thread *thread, size_t *stack_size, + size_t *unused_ptr) +{ + struct z_x86_thread_stack_header *hdr_stack_obj; + + if ((thread->base.user_options & K_USER) != K_USER) { + return -EINVAL; + } + + hdr_stack_obj = (struct z_x86_thread_stack_header *)thread->stack_obj; + + return z_stack_space_get(&hdr_stack_obj->privilege_stack[0], + sizeof(hdr_stack_obj->privilege_stack), + unused_ptr); +} diff --git a/arch/x86/core/x86_mmu.c b/arch/x86/core/x86_mmu.c index 7bfa2088a41..566dd2cdfd4 100644 --- a/arch/x86/core/x86_mmu.c +++ b/arch/x86/core/x86_mmu.c @@ -313,7 +313,7 @@ static inline uintptr_t get_entry_phys(pentry_t entry, int level) __pinned_func static inline pentry_t *next_table(pentry_t entry, int level) { - return z_mem_virt_addr(get_entry_phys(entry, level)); + return k_mem_virt_addr(get_entry_phys(entry, level)); } /* Number of table entries at this level */ @@ -416,12 +416,12 @@ void z_x86_tlb_ipi(const void *arg) * if KPTI is turned on */ ptables_phys = z_x86_cr3_get(); - __ASSERT(ptables_phys == z_mem_phys_addr(&z_x86_kernel_ptables), ""); + __ASSERT(ptables_phys == k_mem_phys_addr(&z_x86_kernel_ptables), ""); #else /* We might have been moved to another memory domain, so always invoke * z_x86_thread_page_tables_get() instead of using current CR3 value. */ - ptables_phys = z_mem_phys_addr(z_x86_thread_page_tables_get(_current)); + ptables_phys = k_mem_phys_addr(z_x86_thread_page_tables_get(_current)); #endif /* * In the future, we can consider making this smarter, such as @@ -593,7 +593,7 @@ static void print_entries(pentry_t entries_array[], uint8_t *base, int level, if (phys == virt) { /* Identity mappings */ COLOR(YELLOW); - } else if (phys + Z_MEM_VM_OFFSET == virt) { + } else if (phys + K_MEM_VIRT_OFFSET == virt) { /* Permanent RAM mappings */ COLOR(GREEN); } else { @@ -661,7 +661,7 @@ static void dump_ptables(pentry_t *table, uint8_t *base, int level) #endif printk("%s at %p (0x%" PRIxPTR "): ", info->name, table, - z_mem_phys_addr(table)); + k_mem_phys_addr(table)); if (level == 0) { printk("entire address space\n"); } else { @@ -826,7 +826,7 @@ static inline pentry_t pte_finalize_value(pentry_t val, bool user_table, { #ifdef CONFIG_X86_KPTI static const uintptr_t shared_phys_addr = - Z_MEM_PHYS_ADDR(POINTER_TO_UINT(&z_shared_kernel_page_start)); + K_MEM_PHYS_ADDR(POINTER_TO_UINT(&z_shared_kernel_page_start)); if (user_table && (val & MMU_US) == 0 && (val & MMU_P) != 0 && get_entry_phys(val, level) != shared_phys_addr) { @@ -1307,7 +1307,7 @@ void arch_mem_unmap(void *addr, size_t size) ARG_UNUSED(ret); } -#ifdef Z_VM_KERNEL +#ifdef K_MEM_IS_VM_KERNEL __boot_func static void identity_map_remove(uint32_t level) { @@ -1346,7 +1346,7 @@ static void identity_map_remove(uint32_t level) __boot_func void z_x86_mmu_init(void) { -#ifdef Z_VM_KERNEL +#ifdef K_MEM_IS_VM_KERNEL /* We booted with physical address space being identity mapped. * As we are now executing in virtual address space, * the identity map is no longer needed. So remove them. @@ -1720,7 +1720,7 @@ static int copy_page_table(pentry_t *dst, pentry_t *src, int level) * cast needed for PAE case where sizeof(void *) and * sizeof(pentry_t) are not the same. */ - dst[i] = ((pentry_t)z_mem_phys_addr(child_dst) | + dst[i] = ((pentry_t)k_mem_phys_addr(child_dst) | INT_FLAGS); ret = copy_page_table(child_dst, @@ -1924,11 +1924,11 @@ int arch_mem_domain_thread_add(struct k_thread *thread) * z_x86_current_stack_perms() */ if (is_migration) { - old_ptables = z_mem_virt_addr(thread->arch.ptables); + old_ptables = k_mem_virt_addr(thread->arch.ptables); set_stack_perms(thread, domain->arch.ptables); } - thread->arch.ptables = z_mem_phys_addr(domain->arch.ptables); + thread->arch.ptables = k_mem_phys_addr(domain->arch.ptables); LOG_DBG("set thread %p page tables to 0x%" PRIxPTR, thread, thread->arch.ptables); @@ -2004,11 +2004,12 @@ static void mark_addr_page_reserved(uintptr_t addr, size_t len) uintptr_t end = ROUND_UP(addr + len, CONFIG_MMU_PAGE_SIZE); for (; pos < end; pos += CONFIG_MMU_PAGE_SIZE) { - if (!z_is_page_frame(pos)) { + if (!k_mem_is_page_frame(pos)) { continue; } - z_page_frame_set(z_phys_to_page_frame(pos), Z_PAGE_FRAME_RESERVED); + k_mem_page_frame_set(k_mem_phys_to_page_frame(pos), + K_MEM_PAGE_FRAME_RESERVED); } } @@ -2112,7 +2113,7 @@ void arch_mem_page_in(void *addr, uintptr_t phys) __pinned_func void arch_mem_scratch(uintptr_t phys) { - page_map_set(z_x86_page_tables_get(), Z_SCRATCH_PAGE, + page_map_set(z_x86_page_tables_get(), K_MEM_SCRATCH_PAGE, phys | MMU_P | MMU_RW | MMU_XD, NULL, MASK_ALL, OPTION_FLUSH); } @@ -2230,7 +2231,7 @@ bool z_x86_kpti_is_access_ok(void *addr, pentry_t *ptables) /* Might as well also check if it's un-mapped, normally we don't * fetch the PTE from the page tables until we are inside - * z_page_fault() and call arch_page_fault_status_get() + * k_mem_page_fault() and call arch_page_fault_status_get() */ if (level != PTE_LEVEL || pte == 0 || is_flipped_pte(pte)) { return false; diff --git a/arch/x86/ia32.cmake b/arch/x86/ia32.cmake index ee2c7a7f01e..5bf5018a32a 100644 --- a/arch/x86/ia32.cmake +++ b/arch/x86/ia32.cmake @@ -126,7 +126,7 @@ add_bin_file_to_the_next_link(gen_idt_output irq_int_vector_map) add_bin_file_to_the_next_link(gen_idt_output irq_vectors_alloc) if(CONFIG_GDT_DYNAMIC) - # Use gen_gdt.py and objcopy to generate gdt.o from from the elf + # Use gen_gdt.py and objcopy to generate gdt.o from the elf # file ${ZEPHYR_PREBUILT_EXECUTABLE}, creating the temp file gdt.bin along the # way. # diff --git a/arch/x86/include/ia32/exception.h b/arch/x86/include/ia32/exception.h index 27119709c2a..1b0ce9ee3b5 100644 --- a/arch/x86/include/ia32/exception.h +++ b/arch/x86/include/ia32/exception.h @@ -62,7 +62,7 @@ * Assign an exception handler to a particular vector in the IDT. * * @param handler A handler function of the prototype - * void handler(const z_arch_esf_t *esf) + * void handler(const struct arch_esf *esf) * @param vector Vector index in the IDT */ #define _EXCEPTION_CONNECT_NOCODE(handler, vector, dpl) \ @@ -75,7 +75,7 @@ * The error code will be accessible in esf->errorCode * * @param handler A handler function of the prototype - * void handler(const z_arch_esf_t *esf) + * void handler(const struct arch_esf *esf) * @param vector Vector index in the IDT */ #define _EXCEPTION_CONNECT_CODE(handler, vector, dpl) \ diff --git a/arch/x86/include/ia32/offsets_short_arch.h b/arch/x86/include/ia32/offsets_short_arch.h index 2033a5585f7..cb5cdb218f0 100644 --- a/arch/x86/include/ia32/offsets_short_arch.h +++ b/arch/x86/include/ia32/offsets_short_arch.h @@ -7,7 +7,7 @@ #ifndef ZEPHYR_ARCH_X86_INCLUDE_IA32_OFFSETS_SHORT_ARCH_H_ #define ZEPHYR_ARCH_X86_INCLUDE_IA32_OFFSETS_SHORT_ARCH_H_ -#include +#include /* kernel */ diff --git a/arch/x86/include/intel64/kernel_arch_func.h b/arch/x86/include/intel64/kernel_arch_func.h index a749a9b9af1..abf022fe5fd 100644 --- a/arch/x86/include/intel64/kernel_arch_func.h +++ b/arch/x86/include/intel64/kernel_arch_func.h @@ -36,7 +36,7 @@ void x86_sse_init(struct k_thread *thread); void z_x86_syscall_entry_stub(void); -bool z_x86_do_kernel_nmi(const z_arch_esf_t *esf); +bool z_x86_do_kernel_nmi(const struct arch_esf *esf); #endif /* _ASMLANGUAGE */ diff --git a/arch/x86/include/intel64/offsets_short_arch.h b/arch/x86/include/intel64/offsets_short_arch.h index 4252ac687db..1ffabc899c2 100644 --- a/arch/x86/include/intel64/offsets_short_arch.h +++ b/arch/x86/include/intel64/offsets_short_arch.h @@ -6,7 +6,7 @@ #ifndef ZEPHYR_ARCH_X86_INCLUDE_INTEL64_OFFSETS_SHORT_ARCH_H_ #define ZEPHYR_ARCH_X86_INCLUDE_INTEL64_OFFSETS_SHORT_ARCH_H_ -#include +#include #define _thread_offset_to_rsp \ (___thread_t_callee_saved_OFFSET + ___callee_saved_t_rsp_OFFSET) diff --git a/arch/x86/include/kernel_arch_func.h b/arch/x86/include/kernel_arch_func.h index 00b411978ec..9bc7cfe4212 100644 --- a/arch/x86/include/kernel_arch_func.h +++ b/arch/x86/include/kernel_arch_func.h @@ -49,16 +49,16 @@ void z_x86_early_serial_init(void); * interesting info and call z_x86_fatal_error() */ FUNC_NORETURN void z_x86_unhandled_cpu_exception(uintptr_t vector, - const z_arch_esf_t *esf); + const struct arch_esf *esf); /* Called upon unrecoverable error; dump registers and transfer control to * kernel via z_fatal_error() */ FUNC_NORETURN void z_x86_fatal_error(unsigned int reason, - const z_arch_esf_t *esf); + const struct arch_esf *esf); /* Common handling for page fault exceptions */ -void z_x86_page_fault_handler(z_arch_esf_t *esf); +void z_x86_page_fault_handler(struct arch_esf *esf); #ifdef CONFIG_THREAD_STACK_INFO /** @@ -90,7 +90,7 @@ void *z_x86_userspace_prepare_thread(struct k_thread *thread); #endif /* CONFIG_USERSPACE */ -void z_x86_do_kernel_oops(const z_arch_esf_t *esf); +void z_x86_do_kernel_oops(const struct arch_esf *esf); /* * Find a free IRQ vector at the specified priority, or return -1 if none left. diff --git a/arch/x86/include/x86_mmu.h b/arch/x86/include/x86_mmu.h index 31c8526cb7a..ed6bb59b37c 100644 --- a/arch/x86/include/x86_mmu.h +++ b/arch/x86/include/x86_mmu.h @@ -182,7 +182,7 @@ static inline uintptr_t z_x86_cr3_get(void) /* Return the virtual address of the page tables installed in this CPU in CR3 */ static inline pentry_t *z_x86_page_tables_get(void) { - return z_mem_virt_addr(z_x86_cr3_get()); + return k_mem_virt_addr(z_x86_cr3_get()); } /* Return cr2 value, which contains the page fault linear address. @@ -215,7 +215,7 @@ static inline pentry_t *z_x86_thread_page_tables_get(struct k_thread *thread) * the kernel's page tables and not the page tables associated * with their memory domain. */ - return z_mem_virt_addr(thread->arch.ptables); + return k_mem_virt_addr(thread->arch.ptables); } #else ARG_UNUSED(thread); diff --git a/arch/x86/zefi/efi.h b/arch/x86/zefi/efi.h index 9be17c53e14..d0773177132 100644 --- a/arch/x86/zefi/efi.h +++ b/arch/x86/zefi/efi.h @@ -10,6 +10,7 @@ #ifndef _ASMLANGUAGE #include +#include #define __abi __attribute__((ms_abi)) @@ -618,6 +619,24 @@ struct efi_system_table { struct efi_configuration_table *ConfigurationTable; }; +#ifdef CONFIG_DYNAMIC_BOOTARGS +struct efi_loaded_image_protocol { + uint32_t Revision; + void *ParentHandle; + struct efi_system_table *SystemTable; + void *DeviceHandle; + void *FilePath; + void *Reserved; + uint32_t LoadOptionsSize; + void *LoadOptions; + void *ImageBase; + uint64_t ImageSize; + enum efi_memory_type ImageCodeType; + enum efi_memory_type ImageDataType; + efi_unload_image_t Unload; +}; +#endif /* CONFIG_DYNAMIC_BOOTARGS */ + #endif /* _ASMLANGUAGE */ #endif /* ZEPHYR_INCLUDE_ARCH_X86_EFI_H_ */ diff --git a/arch/x86/zefi/zefi.c b/arch/x86/zefi/zefi.c index 56d0701e79b..66a54b538b1 100644 --- a/arch/x86/zefi/zefi.c +++ b/arch/x86/zefi/zefi.c @@ -32,6 +32,14 @@ .Data4 = { 0xbc, 0x22, 0x00, 0x80, 0xc7, 0x3c, 0x88, 0x81 }, \ } +#define EFI_LOADED_IMAGE_PROTOCOL_GUID \ + { \ + .Data1 = 0x5b1b31a1, \ + .Data2 = 0x9562, \ + .Data3 = 0x11d2, \ + .Data4 = { 0x8e, 0x3f, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b } \ + } + /* The linker places this dummy last in the data memory. We can't use * traditional linker address symbols because we're relocatable; the * linker doesn't know what the runtime address will be. The compiler @@ -135,7 +143,9 @@ static void disable_hpet(void) */ uintptr_t __abi efi_entry(void *img_handle, struct efi_system_table *sys_tab) { +#ifndef CONFIG_DYNAMIC_BOOTARGS (void)img_handle; +#endif /* CONFIG_DYNAMIC_BOOTARGS */ efi = sys_tab; z_putchar = efi_putchar; @@ -180,6 +190,30 @@ uintptr_t __abi efi_entry(void *img_handle, struct efi_system_table *sys_tab) } } +#ifdef CONFIG_DYNAMIC_BOOTARGS + char *dst_bootargs = (char *)zefi_bootargs; + struct efi_loaded_image_protocol *loaded_image; + efi_guid_t loaded_image_protocol = EFI_LOADED_IMAGE_PROTOCOL_GUID; + efi_status_t loaded_image_status = sys_tab->BootServices->HandleProtocol( + img_handle, + &loaded_image_protocol, + (void **)&loaded_image + ); + + if (loaded_image_status == EFI_SUCCESS) { + uint16_t *src_bootargs = (uint16_t *)loaded_image->LoadOptions; + + while (*src_bootargs != '\0' && + dst_bootargs + 1 < + (char *)zefi_bootargs + CONFIG_BOOTARGS_ARGS_BUFFER_SIZE) { + *dst_bootargs++ = *src_bootargs++ & 0x7f; + } + *dst_bootargs = '\0'; + } else { + *dst_bootargs = '\0'; + } +#endif /* CONFIG_DYNAMIC_BOOTARGS */ + unsigned char *code = (void *)zefi_entry; efi_arg.efi_systab = efi; diff --git a/arch/x86/zefi/zefi.py b/arch/x86/zefi/zefi.py index 99c188ecd08..2f9c3482bb4 100755 --- a/arch/x86/zefi/zefi.py +++ b/arch/x86/zefi/zefi.py @@ -8,6 +8,9 @@ import argparse ENTRY_SYM = "__start64" +BOOTARGS_SYM = "efi_bootargs" + +args = None def verbose(msg): if args.verbose: @@ -93,6 +96,9 @@ def build_elf(elf_file, include_dirs): cf.write("static uintptr_t zefi_entry = 0x%xUL;\n" % (entry_addr)) + if symtab.get_symbol_by_name(BOOTARGS_SYM): + cf.write("static uintptr_t zefi_bootargs = 0x%xUL;\n" % (symtab.get_symbol_by_name(BOOTARGS_SYM)[0].entry.st_value)) + cf.close() verbose("Metadata header generated.") diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 82a44f820c5..8722c879e8b 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -103,6 +103,13 @@ config XTENSA_NUM_SPIN_RELAX_NOPS Specify the number of NOPs in Xtensa specific arch_spin_relax(). +config XTENSA_BREAK_ON_UNRECOVERABLE_EXCEPTIONS + bool "Use BREAK instruction on unrecoverable exceptions" + help + Use BREAK instruction when unrecoverable exceptions are + encountered. This requires a debugger attached to catch + the BREAK. + menu "Xtensa HiFi Options" config XTENSA_CPU_HAS_HIFI @@ -150,6 +157,12 @@ endif # XTENSA_CPU_HAS_HIFI endmenu # Xtensa HiFi Options +config XTENSA_INTERRUPT_NONPREEMPTABLE + bool "Xtensa exceptions and interrupts cannot be pre-empted" + help + Allow use of medium and high priority interrupts without + pre-empting low priority interrupts and exceptions. + if CPU_HAS_MMU config XTENSA_MMU diff --git a/arch/xtensa/core/CMakeLists.txt b/arch/xtensa/core/CMakeLists.txt index 4c2ce8173ca..d03e3641b42 100644 --- a/arch/xtensa/core/CMakeLists.txt +++ b/arch/xtensa/core/CMakeLists.txt @@ -12,6 +12,7 @@ zephyr_library_sources( irq_manage.c thread.c vector_handlers.c + prep_c.c ) zephyr_library_sources_ifdef(CONFIG_XTENSA_USE_CORE_CRT1 crt1.S) @@ -48,7 +49,7 @@ add_subdirectory(startup) # are the official places where we find core-isa.h. (Also that we # undefine __XCC_ because that compiler actually trips an error trying # to build this file to protect against mismatched versions.) -set(CORE_ISA_DM ${CMAKE_BINARY_DIR}/zephyr/include/generated/core-isa-dM.h) +set(CORE_ISA_DM ${CMAKE_BINARY_DIR}/zephyr/include/generated/zephyr/core-isa-dM.h) set(CORE_ISA_IN ${CMAKE_BINARY_DIR}/zephyr/include/generated/core-isa-dM.c) file(WRITE ${CORE_ISA_IN} "#include \n") add_custom_command(OUTPUT ${CORE_ISA_DM} @@ -73,7 +74,7 @@ else() endif() # Generates a list of device-specific scratch register choices -set(ZSR_H ${CMAKE_BINARY_DIR}/zephyr/include/generated/zsr.h) +set(ZSR_H ${CMAKE_BINARY_DIR}/zephyr/include/generated/zephyr/zsr.h) add_custom_command(OUTPUT ${ZSR_H} DEPENDS ${CORE_ISA_DM} COMMAND ${PYTHON_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/gen_zsr.py $<$:--mmu> diff --git a/arch/xtensa/core/README_MMU.txt b/arch/xtensa/core/README_MMU.txt index 499a251cdf2..4332ffdbd43 100644 --- a/arch/xtensa/core/README_MMU.txt +++ b/arch/xtensa/core/README_MMU.txt @@ -254,7 +254,7 @@ of access variability. But it also means that the TLB entries end up being stored twice in the same CPU, wasting transistors that could presumably store other useful data. -But it it also important to note that the L1 data cache on Xtensa is +But it is also important to note that the L1 data cache on Xtensa is incoherent! The cache being used for refill reflects the last access on the current CPU only, and not of the underlying memory being mapped. Page table changes in the data cache of one CPU will be diff --git a/arch/xtensa/core/coredump.c b/arch/xtensa/core/coredump.c index a2eec620774..0ee1f8992a6 100644 --- a/arch/xtensa/core/coredump.c +++ b/arch/xtensa/core/coredump.c @@ -7,7 +7,7 @@ #include #include #include -#include +#include #define ARCH_HDR_VER 1 #define XTENSA_BLOCK_HDR_VER 2 @@ -91,7 +91,7 @@ struct xtensa_arch_block { */ static struct xtensa_arch_block arch_blk; -void arch_coredump_info_dump(const z_arch_esf_t *esf) +void arch_coredump_info_dump(const struct arch_esf *esf) { struct coredump_arch_hdr_t hdr = { .id = COREDUMP_ARCH_HDR_ID, diff --git a/arch/xtensa/core/cpu_idle.c b/arch/xtensa/core/cpu_idle.c index dae79f023ff..48ddc58cb0a 100644 --- a/arch/xtensa/core/cpu_idle.c +++ b/arch/xtensa/core/cpu_idle.c @@ -6,7 +6,7 @@ #include #include -#ifndef CONFIG_ARCH_CPU_IDLE_CUSTOM +#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_IDLE void arch_cpu_idle(void) { sys_trace_idle(); @@ -14,6 +14,7 @@ void arch_cpu_idle(void) } #endif +#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE void arch_cpu_atomic_idle(unsigned int key) { sys_trace_idle(); @@ -21,3 +22,4 @@ void arch_cpu_atomic_idle(unsigned int key) "wsr.ps %0\n\t" "rsync" :: "a"(key)); } +#endif diff --git a/arch/xtensa/core/crt1.S b/arch/xtensa/core/crt1.S index c616b0889d7..5e3bf9e8a2c 100644 --- a/arch/xtensa/core/crt1.S +++ b/arch/xtensa/core/crt1.S @@ -4,7 +4,7 @@ */ /* - * Control arrives here at _start from the reset vector or from crt0-app.S. + * Control arrives here at _start from the reset vector. */ #include @@ -22,7 +22,7 @@ */ .global __start -.type z_cstart, @function +.type z_prep_c, @function /* Macros to abstract away ABI differences */ @@ -52,7 +52,7 @@ _start: /* * _start is typically NOT at the beginning of the text segment -- * it is always called from either the reset vector (__start) or other - * code that does equivalent initialization (such as crt0-app.S). + * code that does equivalent initialization. * * Assumptions on entry to _start: * - low (level-one) and medium priority interrupts are disabled @@ -189,6 +189,6 @@ _start: #endif /* !XCHAL_HAVE_BOOTLOADER */ /* Enter C domain, never returns from here */ - CALL z_cstart + CALL z_prep_c .size _start, . - _start diff --git a/arch/xtensa/core/debug_helpers_asm.S b/arch/xtensa/core/debug_helpers_asm.S index 3dacc1a4587..6ed5ced8c61 100644 --- a/arch/xtensa/core/debug_helpers_asm.S +++ b/arch/xtensa/core/debug_helpers_asm.S @@ -10,7 +10,7 @@ #include #include -#include +#include .section .iram1, "ax" .align 4 diff --git a/arch/xtensa/core/fatal.c b/arch/xtensa/core/fatal.c index 6ec5549f2e4..41a7a8d1409 100644 --- a/arch/xtensa/core/fatal.c +++ b/arch/xtensa/core/fatal.c @@ -84,10 +84,10 @@ char *xtensa_exccause(unsigned int cause_code) #endif } -void xtensa_fatal_error(unsigned int reason, const z_arch_esf_t *esf) +void xtensa_fatal_error(unsigned int reason, const struct arch_esf *esf) { #ifdef CONFIG_EXCEPTION_DEBUG - if (esf) { + if (esf != NULL) { /* Don't want to get elbowed by xtensa_switch * in between printing registers and dumping them; * corrupts backtrace @@ -154,6 +154,6 @@ static void z_vrfy_xtensa_user_fault(unsigned int reason) z_impl_xtensa_user_fault(reason); } -#include +#include #endif /* CONFIG_USERSPACE */ diff --git a/arch/xtensa/core/gdbstub.c b/arch/xtensa/core/gdbstub.c index 4df72f0d355..0ebc9cc68cc 100644 --- a/arch/xtensa/core/gdbstub.c +++ b/arch/xtensa/core/gdbstub.c @@ -422,7 +422,7 @@ static unsigned int get_gdb_exception_reason(unsigned int reason) * @param ctx GDB context * @param stack Pointer to the stack frame */ -static void copy_to_ctx(struct gdb_ctx *ctx, const z_arch_esf_t *stack) +static void copy_to_ctx(struct gdb_ctx *ctx, const struct arch_esf *stack) { struct xtensa_register *reg; int idx, num_laddr_regs; @@ -513,7 +513,7 @@ static void copy_to_ctx(struct gdb_ctx *ctx, const z_arch_esf_t *stack) * @param ctx GDB context * @param stack Pointer to the stack frame */ -static void restore_from_ctx(struct gdb_ctx *ctx, const z_arch_esf_t *stack) +static void restore_from_ctx(struct gdb_ctx *ctx, const struct arch_esf *stack) { struct xtensa_register *reg; int idx, num_laddr_regs; @@ -913,7 +913,7 @@ int arch_gdb_remove_breakpoint(struct gdb_ctx *ctx, uint8_t type, return ret; } -void z_gdb_isr(z_arch_esf_t *esf) +void z_gdb_isr(struct arch_esf *esf) { uint32_t reg; diff --git a/arch/xtensa/core/gen_zsr.py b/arch/xtensa/core/gen_zsr.py index 26797a7fe57..6d9a228303f 100755 --- a/arch/xtensa/core/gen_zsr.py +++ b/arch/xtensa/core/gen_zsr.py @@ -31,7 +31,7 @@ def parse_args(): NEEDED = ["A0SAVE", "CPU"] if args.mmu: - NEEDED += ["MMU_0", "MMU_1", "DBLEXC"] + NEEDED += ["DBLEXC", "DEPC_SAVE", "EXCCAUSE_SAVE"] if args.coherence: NEEDED += ["FLUSH"] diff --git a/arch/xtensa/core/irq_offload.c b/arch/xtensa/core/irq_offload.c index ad35ef4cd0e..0e83520c809 100644 --- a/arch/xtensa/core/irq_offload.c +++ b/arch/xtensa/core/irq_offload.c @@ -5,7 +5,7 @@ #include #include -#include +#include #include static struct { @@ -37,3 +37,7 @@ void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) :: "r"(intenable), "r"(BIT(ZSR_IRQ_OFFLOAD_INT))); arch_irq_unlock(key); } + +void arch_irq_offload_init(void) +{ +} diff --git a/arch/xtensa/core/mpu.c b/arch/xtensa/core/mpu.c index 76036b32c70..09385323dc7 100644 --- a/arch/xtensa/core/mpu.c +++ b/arch/xtensa/core/mpu.c @@ -33,6 +33,9 @@ extern char _heap_start[]; /** MPU foreground map for kernel mode. */ static struct xtensa_mpu_map xtensa_mpu_map_fg_kernel; +/** Make sure write to the MPU region is atomic. */ +static struct k_spinlock xtensa_mpu_lock; + /* * Additional information about the MPU maps: foreground and background * maps. @@ -443,6 +446,8 @@ static int mpu_map_region_add(struct xtensa_mpu_map *map, xtensa_mpu_entry_set(entry_slot_s, start_addr, true, access_rights, memory_type); + first_enabled_idx = XTENSA_MPU_NUM_ENTRIES - 1; + goto end; } else { /* * Populate the last two entries to indicate @@ -459,6 +464,8 @@ static int mpu_map_region_add(struct xtensa_mpu_map *map, xtensa_mpu_entry_set(entry_slot_e, end_addr, false, XTENSA_MPU_ACCESS_P_NA_U_NA, CONFIG_XTENSA_MPU_DEFAULT_MEM_TYPE); + first_enabled_idx = XTENSA_MPU_NUM_ENTRIES - 2; + goto end; } ret = 0; @@ -595,6 +602,7 @@ static int mpu_map_region_add(struct xtensa_mpu_map *map, xtensa_mpu_entry_attributes_set(&entries[idx], access_rights, memory_type); } +end: if (first_idx != NULL) { *first_idx = first_enabled_idx; } @@ -624,6 +632,9 @@ void xtensa_mpu_map_write(struct xtensa_mpu_map *map) #endif { int entry; + k_spinlock_key_t key; + + key = k_spin_lock(&xtensa_mpu_lock); #ifdef CONFIG_USERSPACE struct xtensa_mpu_map *map = thread->arch.mpu_map; @@ -647,6 +658,8 @@ void xtensa_mpu_map_write(struct xtensa_mpu_map *map) __asm__ volatile("wptlb %0, %1\n\t" : : "a"(map->entries[entry].at), "a"(map->entries[entry].as)); } + + k_spin_unlock(&xtensa_mpu_lock, key); } /** @@ -760,6 +773,7 @@ int arch_mem_domain_partition_remove(struct k_mem_domain *domain, { int ret; uint32_t perm; + struct k_thread *cur_thread; struct xtensa_mpu_map *map = &domain->arch.mpu_map; struct k_mem_partition *partition = &domain->partitions[partition_id]; uintptr_t end_addr = partition->start + partition->size; @@ -828,6 +842,15 @@ int arch_mem_domain_partition_remove(struct k_mem_domain *domain, CONFIG_XTENSA_MPU_DEFAULT_MEM_TYPE, NULL); + /* + * Need to update hardware MPU regions if we are removing + * partition from the domain of the current running thread. + */ + cur_thread = _current_cpu->current; + if (cur_thread->mem_domain_info.mem_domain == domain) { + xtensa_mpu_map_write(cur_thread); + } + out: return ret; } @@ -836,6 +859,7 @@ int arch_mem_domain_partition_add(struct k_mem_domain *domain, uint32_t partition_id) { int ret; + struct k_thread *cur_thread; struct xtensa_mpu_map *map = &domain->arch.mpu_map; struct k_mem_partition *partition = &domain->partitions[partition_id]; uintptr_t end_addr = partition->start + partition->size; @@ -850,6 +874,20 @@ int arch_mem_domain_partition_add(struct k_mem_domain *domain, CONFIG_XTENSA_MPU_DEFAULT_MEM_TYPE, NULL); + /* + * Need to update hardware MPU regions if we are removing + * partition from the domain of the current running thread. + * + * Note that this function can be called with dummy thread + * at boot so we need to avoid writing MPU regions to + * hardware. + */ + cur_thread = _current_cpu->current; + if (((cur_thread->base.thread_state & _THREAD_DUMMY) != _THREAD_DUMMY) && + (cur_thread->mem_domain_info.mem_domain == domain)) { + xtensa_mpu_map_write(cur_thread); + } + out: return ret; } @@ -984,6 +1022,14 @@ int arch_buffer_validate(const void *addr, size_t size, int write) offset += XCHAL_MPU_ALIGN) { uint32_t probed = xtensa_pptlb_probe(aligned_addr + offset); + if ((probed & XTENSA_MPU_PROBE_VALID_ENTRY_MASK) == 0U) { + /* There is no foreground or background entry associated + * with the region. + */ + ret = -EPERM; + goto out; + } + uint8_t access_rights = (probed & XTENSA_MPU_PPTLB_ACCESS_RIGHTS_MASK) >> XTENSA_MPU_PPTLB_ACCESS_RIGHTS_SHIFT; @@ -1032,6 +1078,95 @@ int arch_buffer_validate(const void *addr, size_t size, int write) return ret; } +bool xtensa_mem_kernel_has_access(void *addr, size_t size, int write) +{ + uintptr_t aligned_addr; + size_t aligned_size, addr_offset; + bool ret = true; + + /* addr/size arbitrary, fix this up into an aligned region */ + aligned_addr = ROUND_DOWN((uintptr_t)addr, XCHAL_MPU_ALIGN); + addr_offset = (uintptr_t)addr - aligned_addr; + aligned_size = ROUND_UP(size + addr_offset, XCHAL_MPU_ALIGN); + + for (size_t offset = 0; offset < aligned_size; + offset += XCHAL_MPU_ALIGN) { + uint32_t probed = xtensa_pptlb_probe(aligned_addr + offset); + + if ((probed & XTENSA_MPU_PROBE_VALID_ENTRY_MASK) == 0U) { + /* There is no foreground or background entry associated + * with the region. + */ + ret = false; + goto out; + } + + uint8_t access_rights = (probed & XTENSA_MPU_PPTLB_ACCESS_RIGHTS_MASK) + >> XTENSA_MPU_PPTLB_ACCESS_RIGHTS_SHIFT; + + + if (write != 0) { + /* Need to check write permission. */ + switch (access_rights) { + case XTENSA_MPU_ACCESS_P_RW_U_NA: + __fallthrough; + case XTENSA_MPU_ACCESS_P_RWX_U_NA: + __fallthrough; + case XTENSA_MPU_ACCESS_P_WO_U_WO: + __fallthrough; + case XTENSA_MPU_ACCESS_P_RW_U_RWX: + __fallthrough; + case XTENSA_MPU_ACCESS_P_RW_U_RO: + __fallthrough; + case XTENSA_MPU_ACCESS_P_RWX_U_RX: + __fallthrough; + case XTENSA_MPU_ACCESS_P_RW_U_RW: + __fallthrough; + case XTENSA_MPU_ACCESS_P_RWX_U_RWX: + /* These permissions are okay. */ + break; + default: + ret = false; + goto out; + } + } else { + /* Only check read permission. */ + switch (access_rights) { + case XTENSA_MPU_ACCESS_P_RO_U_NA: + __fallthrough; + case XTENSA_MPU_ACCESS_P_RX_U_NA: + __fallthrough; + case XTENSA_MPU_ACCESS_P_RW_U_NA: + __fallthrough; + case XTENSA_MPU_ACCESS_P_RWX_U_NA: + __fallthrough; + case XTENSA_MPU_ACCESS_P_RW_U_RWX: + __fallthrough; + case XTENSA_MPU_ACCESS_P_RW_U_RO: + __fallthrough; + case XTENSA_MPU_ACCESS_P_RWX_U_RX: + __fallthrough; + case XTENSA_MPU_ACCESS_P_RO_U_RO: + __fallthrough; + case XTENSA_MPU_ACCESS_P_RX_U_RX: + __fallthrough; + case XTENSA_MPU_ACCESS_P_RW_U_RW: + __fallthrough; + case XTENSA_MPU_ACCESS_P_RWX_U_RWX: + /* These permissions are okay. */ + break; + default: + ret = false; + goto out; + } + } + } + +out: + return ret; +} + + void xtensa_user_stack_perms(struct k_thread *thread) { int ret; diff --git a/arch/xtensa/core/prep_c.c b/arch/xtensa/core/prep_c.c new file mode 100644 index 00000000000..990915c5a46 --- /dev/null +++ b/arch/xtensa/core/prep_c.c @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2024 Intel Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#include + +extern FUNC_NORETURN void z_cstart(void); + +/* defined by the SoC in case of CONFIG_SOC_HAS_RUNTIME_NUM_CPUS=y */ +extern void soc_num_cpus_init(void); + +/** + * + * @brief Prepare to and run C code + * + * This routine prepares for the execution of and runs C code. + * + */ +void z_prep_c(void) +{ +#if defined(CONFIG_SOC_PREP_HOOK) + soc_prep_hook(); +#endif +#if CONFIG_SOC_HAS_RUNTIME_NUM_CPUS + soc_num_cpus_init(); +#endif + + _cpu_t *cpu0 = &_kernel.cpus[0]; + +#ifdef CONFIG_KERNEL_COHERENCE + /* Make sure we don't have live data for unexpected cached + * regions due to boot firmware + */ + sys_cache_data_flush_and_invd_all(); + + /* Our cache top stash location might have junk in it from a + * pre-boot environment. Must be zero or valid! + */ + XTENSA_WSR(ZSR_FLUSH_STR, 0); +#endif + + cpu0->nested = 0; + + /* The asm2 scheme keeps the kernel pointer in a scratch SR + * (see zsr.h for generation specifics) for easy access. That + * saves 4 bytes of immediate value to store the address when + * compared to the legacy scheme. But in SMP this record is a + * per-CPU thing and having it stored in a SR already is a big + * win. + */ + XTENSA_WSR(ZSR_CPU_STR, cpu0); + +#ifdef CONFIG_INIT_STACKS + char *stack_start = K_KERNEL_STACK_BUFFER(z_interrupt_stacks[0]); + size_t stack_sz = K_KERNEL_STACK_SIZEOF(z_interrupt_stacks[0]); + char *stack_end = stack_start + stack_sz; + + uint32_t sp; + + __asm__ volatile("mov %0, sp" : "=a"(sp)); + + /* Only clear the interrupt stack if the current stack pointer + * is not within the interrupt stack. Or else we would be + * wiping the in-use stack. + */ + if (((uintptr_t)sp < (uintptr_t)stack_start) || + ((uintptr_t)sp >= (uintptr_t)stack_end)) { + memset(stack_start, 0xAA, stack_sz); + } +#endif +#if CONFIG_ARCH_CACHE + arch_cache_init(); +#endif + +#ifdef CONFIG_XTENSA_MMU + xtensa_mmu_init(); +#endif + +#ifdef CONFIG_XTENSA_MPU + xtensa_mpu_init(); +#endif + z_cstart(); + CODE_UNREACHABLE; +} diff --git a/arch/xtensa/core/ptables.c b/arch/xtensa/core/ptables.c index f44e17ad6a9..c02ecc64b0d 100644 --- a/arch/xtensa/core/ptables.c +++ b/arch/xtensa/core/ptables.c @@ -267,6 +267,12 @@ static void map_memory(const uint32_t start, const uint32_t end, static void xtensa_init_page_tables(void) { volatile uint8_t entry; + static bool already_inited; + + if (already_inited) { + return; + } + already_inited = true; init_page_table(xtensa_kernel_ptables, XTENSA_L1_PAGE_TABLE_ENTRIES); atomic_set_bit(l1_page_table_track, 0); @@ -305,18 +311,35 @@ __weak void arch_xtensa_mmu_post_init(bool is_core0) void xtensa_mmu_init(void) { - if (_current_cpu->id == 0) { - /* This is normally done via arch_kernel_init() inside z_cstart(). - * However, before that is called, we go through the sys_init of - * INIT_LEVEL_EARLY, which is going to result in TLB misses. - * So setup whatever necessary so the exception handler can work - * properly. - */ - xtensa_init_page_tables(); - } + xtensa_init_page_tables(); xtensa_init_paging(xtensa_kernel_ptables); + /* + * This is used to determine whether we are faulting inside double + * exception if this is not zero. Sometimes SoC starts with this not + * being set to zero. So clear it during boot. + */ + XTENSA_WSR(ZSR_DEPC_SAVE_STR, 0); + + arch_xtensa_mmu_post_init(_current_cpu->id == 0); +} + +void xtensa_mmu_reinit(void) +{ + /* First initialize the hardware */ + xtensa_init_paging(xtensa_kernel_ptables); + +#ifdef CONFIG_USERSPACE + struct k_thread *thread = _current_cpu->current; + struct arch_mem_domain *domain = + &(thread->mem_domain_info.mem_domain->arch); + + + /* Set the page table for current context */ + xtensa_set_paging(domain->asid, domain->ptables); +#endif /* CONFIG_USERSPACE */ + arch_xtensa_mmu_post_init(_current_cpu->id == 0); } @@ -335,7 +358,7 @@ __weak void arch_reserved_pages_update(void) for (page = CONFIG_SRAM_BASE_ADDRESS, idx = 0; page < (uintptr_t)z_mapped_start; page += CONFIG_MMU_PAGE_SIZE, idx++) { - z_page_frame_set(&z_page_frames[idx], Z_PAGE_FRAME_RESERVED); + k_mem_page_frame_set(&k_mem_page_frames[idx], K_MEM_PAGE_FRAME_RESERVED); } } #endif /* CONFIG_ARCH_HAS_RESERVED_PAGE_FRAMES */ @@ -1058,15 +1081,13 @@ static bool page_validate(uint32_t *ptables, uint32_t page, uint8_t ring, bool w return true; } -int arch_buffer_validate(const void *addr, size_t size, int write) +static int mem_buffer_validate(const void *addr, size_t size, int write, int ring) { int ret = 0; uint8_t *virt; size_t aligned_size; const struct k_thread *thread = _current; uint32_t *ptables = thread_page_tables_get(thread); - uint8_t ring = ((thread->base.user_options & K_USER) != 0) ? - XTENSA_MMU_USER_RING : XTENSA_MMU_KERNEL_RING; /* addr/size arbitrary, fix this up into an aligned region */ k_mem_region_align((uintptr_t *)&virt, &aligned_size, @@ -1083,6 +1104,16 @@ int arch_buffer_validate(const void *addr, size_t size, int write) return ret; } +bool xtensa_mem_kernel_has_access(void *addr, size_t size, int write) +{ + return mem_buffer_validate(addr, size, write, XTENSA_MMU_KERNEL_RING) == 0; +} + +int arch_buffer_validate(const void *addr, size_t size, int write) +{ + return mem_buffer_validate(addr, size, write, XTENSA_MMU_USER_RING); +} + void xtensa_swap_update_page_tables(struct k_thread *incoming) { uint32_t *ptables = incoming->arch.ptables; diff --git a/arch/xtensa/core/smp.c b/arch/xtensa/core/smp.c index ffd08ab805c..71d8150025b 100644 --- a/arch/xtensa/core/smp.c +++ b/arch/xtensa/core/smp.c @@ -19,3 +19,13 @@ void arch_spin_relax(void) #undef NOP1 } #endif /* CONFIG_XTENSA_MORE_SPIN_RELAX_NOPS */ + + +/** + * init for multi-core/smp is done on the SoC level. Add this here for + * compatibility with other SMP systems. + */ +int arch_smp_init(void) +{ + return 0; +} diff --git a/arch/xtensa/core/syscall_helper.c b/arch/xtensa/core/syscall_helper.c index da2a5551c9a..24feda91c80 100644 --- a/arch/xtensa/core/syscall_helper.c +++ b/arch/xtensa/core/syscall_helper.c @@ -4,8 +4,13 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + #include +#include +#include + #ifdef CONFIG_XTENSA_SYSCALL_USE_HELPER uintptr_t xtensa_syscall_helper(uintptr_t arg1, uintptr_t arg2, uintptr_t arg3, uintptr_t arg4, @@ -47,3 +52,41 @@ bool xtensa_is_user_context(void) return ret != 0; } #endif /* XCHAL_HAVE_THREADPTR */ + +size_t arch_user_string_nlen(const char *s, size_t maxsize, int *err_arg) +{ + /* Check if we can actually read the whole length. + * + * arch_user_string_nlen() is supposed to naively go through + * the string passed from user thread, and relies on page faults + * to catch inaccessible strings, such that user thread can pass + * a string that is shorter than the max length this function + * caller expects. So at least we want to make sure kernel has + * access to the whole length, aka. memory being mapped. + * Note that arch_user_string_nlen() should never result in + * thread termination due to page faults, and must always + * return to the caller with err_arg set or cleared. + * For MMU systems, unmapped memory will result in a DTLB miss + * and that might trigger an infinite DTLB miss storm if + * the corresponding L2 page table never exists in the first + * place (which would result in DTLB misses through L1 page + * table), until some other exceptions occur to break + * the cycle. + * For MPU systems, this would simply results in access errors + * and the exception handler will terminate the thread. + */ + if (!xtensa_mem_kernel_has_access((void *)s, maxsize, 0)) { + /* + * API says we need to set err_arg to -1 if there are + * any errors. + */ + *err_arg = -1; + + return 0; + } + + /* No error and we can proceed to getting the string length. */ + *err_arg = 0; + + return strnlen(s, maxsize); +} diff --git a/arch/xtensa/core/thread.c b/arch/xtensa/core/thread.c index 4ba0150f705..f59c8274994 100644 --- a/arch/xtensa/core/thread.c +++ b/arch/xtensa/core/thread.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include #include #include @@ -72,6 +73,18 @@ static void *init_stack(struct k_thread *thread, int *stack_top, frame->bsa.ps = PS_WOE | PS_UM | PS_CALLINC(1); #ifdef CONFIG_USERSPACE if ((thread->base.user_options & K_USER) == K_USER) { +#ifdef CONFIG_INIT_STACKS + /* setup_thread_stack() does not initialize the architecture specific + * privileged stack. So we need to do it manually here as this function + * is called by arch_new_thread() via z_setup_new_thread() after + * setup_thread_stack() but before thread starts running. + * + * Note that only user threads have privileged stacks and kernel + * only threads do not. + */ + (void)memset(&header->privilege_stack[0], 0xaa, sizeof(header->privilege_stack)); +#endif + frame->bsa.pc = (uintptr_t)arch_user_mode_enter; } else { frame->bsa.pc = (uintptr_t)z_thread_entry; @@ -158,4 +171,20 @@ FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry, CODE_UNREACHABLE; } + +int arch_thread_priv_stack_space_get(const struct k_thread *thread, size_t *stack_size, + size_t *unused_ptr) +{ + struct xtensa_thread_stack_header *hdr_stack_obj; + + if ((thread->base.user_options & K_USER) != K_USER) { + return -EINVAL; + } + + hdr_stack_obj = (struct xtensa_thread_stack_header *)thread->stack_obj; + + return z_stack_space_get(&hdr_stack_obj->privilege_stack[0], + sizeof(hdr_stack_obj->privilege_stack), + unused_ptr); +} #endif /* CONFIG_USERSPACE */ diff --git a/arch/xtensa/core/userspace.S b/arch/xtensa/core/userspace.S index 1578e3be971..3db5d8cea8d 100644 --- a/arch/xtensa/core/userspace.S +++ b/arch/xtensa/core/userspace.S @@ -5,10 +5,10 @@ */ #include -#include +#include #include #include -#include +#include #include @@ -352,45 +352,3 @@ xtensa_userspace_enter: movi a0, 0 rfi 2 - -/* - * size_t arch_user_string_nlen(const char *s, size_t maxsize, int *err_arg) - */ -.global arch_user_string_nlen -.type arch_user_string_nlen, @function -.align 4 -arch_user_string_nlen: - entry a1, 32 - - /* error value, set to -1. */ - movi a5, -1 - s32i a5, a4, 0 - - /* length count */ - xor a5, a5, a5 - - /* This code might page fault */ -strlen_loop: -.global xtensa_user_string_nlen_fault_start -xtensa_user_string_nlen_fault_start: - l8ui a6, a2, 0 /* Current char */ - -.global xtensa_user_string_nlen_fault_end -xtensa_user_string_nlen_fault_end: - beqz a6, strlen_done - addi a5, a5, 1 - addi a2, a2, 1 - beq a5, a3, strlen_done - j strlen_loop - -strlen_done: - /* Set return value */ - mov a2, a5 - - /* Set error value to 0 since we succeeded */ - movi a5, 0x0 - s32i a5, a4, 0 - -.global xtensa_user_string_nlen_fixup -xtensa_user_string_nlen_fixup: - retw diff --git a/arch/xtensa/core/vector_handlers.c b/arch/xtensa/core/vector_handlers.c index f0b0a9175ff..fa58b9c2133 100644 --- a/arch/xtensa/core/vector_handlers.c +++ b/arch/xtensa/core/vector_handlers.c @@ -12,8 +12,8 @@ #include #include #include -#include -#include +#include +#include #include #ifdef CONFIG_XTENSA_GEN_HANDLERS @@ -22,28 +22,136 @@ #include <_soc_inthandlers.h> #endif +#include #include +#include LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); extern char xtensa_arch_except_epc[]; extern char xtensa_arch_kernel_oops_epc[]; +bool xtensa_is_outside_stack_bounds(uintptr_t addr, size_t sz, uint32_t ps) +{ + uintptr_t start, end; + struct k_thread *thread = _current; + bool was_in_isr, invalid; + + /* Without userspace, there is no privileged stack so the thread stack + * is the whole stack (minus reserved area). So there is no need to + * check for PS == UINT32_MAX for special treatment. + */ + ARG_UNUSED(ps); + + /* Since both level 1 interrupts and exceptions go through + * the same interrupt vector, both of them increase the nested + * counter in the CPU struct. The architecture vector handler + * moves execution to the interrupt stack when nested goes from + * zero to one. Afterwards, any nested interrupts/exceptions will + * continue running in interrupt stack. Therefore, only when + * nested > 1, then it was running in the interrupt stack, and + * we should check bounds against the interrupt stack. + */ + was_in_isr = arch_curr_cpu()->nested > 1; + + if ((thread == NULL) || was_in_isr) { + /* We were servicing an interrupt or in early boot environment + * and are supposed to be on the interrupt stack. + */ + int cpu_id; + +#ifdef CONFIG_SMP + cpu_id = arch_curr_cpu()->id; +#else + cpu_id = 0; +#endif + + start = (uintptr_t)K_KERNEL_STACK_BUFFER(z_interrupt_stacks[cpu_id]); + end = start + CONFIG_ISR_STACK_SIZE; #ifdef CONFIG_USERSPACE -Z_EXC_DECLARE(xtensa_user_string_nlen); + } else if (ps == UINT32_MAX) { + /* Since the stashed PS is inside struct pointed by frame->ptr_to_bsa, + * we need to verify that both frame and frame->ptr_to_bsa are valid + * pointer within the thread stack. Also without PS, we have no idea + * whether we were in kernel mode (using privileged stack) or user + * mode (normal thread stack). So we need to check the whole stack + * area. + * + * And... we cannot account for reserved area since we have no idea + * which to use: ARCH_KERNEL_STACK_RESERVED or ARCH_THREAD_STACK_RESERVED + * as we don't know whether we were in kernel or user mode. + */ + start = (uintptr_t)thread->stack_obj; + end = Z_STACK_PTR_ALIGN(thread->stack_info.start + thread->stack_info.size); + } else if (((ps & PS_RING_MASK) == 0U) && + ((thread->base.user_options & K_USER) == K_USER)) { + /* Check if this is a user thread, and that it was running in + * kernel mode. If so, we must have been doing a syscall, so + * check with privileged stack bounds. + */ + start = thread->stack_info.start - CONFIG_PRIVILEGED_STACK_SIZE; + end = thread->stack_info.start; +#endif + } else { + start = thread->stack_info.start; + end = Z_STACK_PTR_ALIGN(thread->stack_info.start + thread->stack_info.size); + } -static const struct z_exc_handle exceptions[] = { - Z_EXC_HANDLE(xtensa_user_string_nlen) -}; -#endif /* CONFIG_USERSPACE */ + invalid = (addr <= start) || ((addr + sz) >= end); + + return invalid; +} -void xtensa_dump_stack(const z_arch_esf_t *stack) +bool xtensa_is_frame_pointer_valid(_xtensa_irq_stack_frame_raw_t *frame) +{ + _xtensa_irq_bsa_t *bsa; + + /* Check if the pointer to the frame is within stack bounds. If not, there is no + * need to test if the BSA (base save area) pointer is also valid as it is + * possibly invalid. + */ + if (xtensa_is_outside_stack_bounds((uintptr_t)frame, sizeof(*frame), UINT32_MAX)) { + return false; + } + + /* Need to test if the BSA area is also within stack bounds. The information + * contained within the BSA is only valid if within stack bounds. + */ + bsa = frame->ptr_to_bsa; + if (xtensa_is_outside_stack_bounds((uintptr_t)bsa, sizeof(*bsa), UINT32_MAX)) { + return false; + } + +#ifdef CONFIG_USERSPACE + /* With usespace, we have privileged stack and normal thread stack within + * one stack object. So we need to further test whether the frame pointer + * resides in the correct stack based on kernel/user mode. + */ + if (xtensa_is_outside_stack_bounds((uintptr_t)frame, sizeof(*frame), bsa->ps)) { + return false; + } +#endif + + return true; +} + +void xtensa_dump_stack(const void *stack) { _xtensa_irq_stack_frame_raw_t *frame = (void *)stack; - _xtensa_irq_bsa_t *bsa = frame->ptr_to_bsa; + _xtensa_irq_bsa_t *bsa; uintptr_t num_high_regs; int reg_blks_remaining; + /* Don't dump stack if the stack pointer is invalid as any frame elements + * obtained via de-referencing the frame pointer are probably also invalid. + * Or worse, cause another access violation. + */ + if (!xtensa_is_frame_pointer_valid(frame)) { + return; + } + + bsa = frame->ptr_to_bsa; + /* Calculate number of high registers. */ num_high_regs = (uint8_t *)bsa - (uint8_t *)frame + sizeof(void *); num_high_regs /= sizeof(uintptr_t); @@ -116,15 +224,30 @@ static void print_fatal_exception(void *print_stack, int cause, uint32_t ps, vaddr; _xtensa_irq_bsa_t *bsa = (void *)*(int **)print_stack; - ps = bsa->ps; - pc = (void *)bsa->pc; - __asm__ volatile("rsr.excvaddr %0" : "=r"(vaddr)); - LOG_ERR(" ** FATAL EXCEPTION%s", (is_dblexc ? " (DOUBLE)" : "")); + if (is_dblexc) { + LOG_ERR(" ** FATAL EXCEPTION (DOUBLE)"); + } else { + LOG_ERR(" ** FATAL EXCEPTION"); + } + LOG_ERR(" ** CPU %d EXCCAUSE %d (%s)", arch_curr_cpu()->id, cause, xtensa_exccause(cause)); + + /* Don't print information if the BSA area is invalid as any elements + * obtained via de-referencing the pointer are probably also invalid. + * Or worse, cause another access violation. + */ + if (xtensa_is_outside_stack_bounds((uintptr_t)bsa, sizeof(*bsa), UINT32_MAX)) { + LOG_ERR(" ** VADDR %p Invalid SP %p", (void *)vaddr, print_stack); + return; + } + + ps = bsa->ps; + pc = (void *)bsa->pc; + LOG_ERR(" ** PC %p VADDR %p", pc, (void *)vaddr); if (is_dblexc) { @@ -218,9 +341,10 @@ static inline DEF_INT_C_HANDLER(1) * different because exceptions and interrupts land at the same * vector; other interrupt levels have their own vectors. */ -void *xtensa_excint1_c(int *interrupted_stack) +void *xtensa_excint1_c(void *esf) { - int cause; + int cause, reason; + int *interrupted_stack = &((struct arch_esf *)esf)->dummy; _xtensa_irq_bsa_t *bsa = (void *)*(int **)interrupted_stack; bool is_fatal_error = false; bool is_dblexc = false; @@ -228,19 +352,24 @@ void *xtensa_excint1_c(int *interrupted_stack) void *pc, *print_stack = (void *)interrupted_stack; uint32_t depc = 0; - __asm__ volatile("rsr.exccause %0" : "=r"(cause)); - #ifdef CONFIG_XTENSA_MMU - __asm__ volatile("rsr.depc %0" : "=r"(depc)); + depc = XTENSA_RSR(ZSR_DEPC_SAVE_STR); + cause = XTENSA_RSR(ZSR_EXCCAUSE_SAVE_STR); is_dblexc = (depc != 0U); +#else /* CONFIG_XTENSA_MMU */ + __asm__ volatile("rsr.exccause %0" : "=r"(cause)); #endif /* CONFIG_XTENSA_MMU */ switch (cause) { case EXCCAUSE_LEVEL1_INTERRUPT: +#ifdef CONFIG_XTENSA_MMU if (!is_dblexc) { return xtensa_int1_c(interrupted_stack); } +#else + return xtensa_int1_c(interrupted_stack); +#endif /* CONFIG_XTENSA_MMU */ break; #ifndef CONFIG_USERSPACE /* Syscalls are handled earlier in assembly if MMU is enabled. @@ -260,26 +389,17 @@ void *xtensa_excint1_c(int *interrupted_stack) break; #endif /* !CONFIG_USERSPACE */ default: - ps = bsa->ps; - pc = (void *)bsa->pc; - -#ifdef CONFIG_USERSPACE - /* If the faulting address is from one of the known - * exceptions that should not be fatal, return to - * the fixup address. - */ - for (int i = 0; i < ARRAY_SIZE(exceptions); i++) { - if ((pc >= exceptions[i].start) && - (pc < exceptions[i].end)) { - bsa->pc = (uintptr_t)exceptions[i].fixup; + reason = K_ERR_CPU_EXCEPTION; - goto fixup_out; - } + /* If the BSA area is invalid, we cannot trust anything coming out of it. */ + if (xtensa_is_outside_stack_bounds((uintptr_t)bsa, sizeof(*bsa), UINT32_MAX)) { + goto skip_checks; } -#endif /* CONFIG_USERSPACE */ + + ps = bsa->ps; + pc = (void *)bsa->pc; /* Default for exception */ - int reason = K_ERR_CPU_EXCEPTION; is_fatal_error = true; /* We need to distinguish between an ill in xtensa_arch_except, @@ -313,6 +433,7 @@ void *xtensa_excint1_c(int *interrupted_stack) } } +skip_checks: if (reason != K_ERR_KERNEL_OOPS) { print_fatal_exception(print_stack, cause, is_dblexc, depc); } @@ -369,15 +490,11 @@ void *xtensa_excint1_c(int *interrupted_stack) _current_cpu->nested = 1; } -#if defined(CONFIG_XTENSA_MMU) || defined(CONFIG_XTENSA_MPU) -#ifdef CONFIG_USERSPACE -fixup_out: -#endif +#if defined(CONFIG_XTENSA_MMU) if (is_dblexc) { - __asm__ volatile("wsr.depc %0" : : "r"(0)); + XTENSA_WSR(ZSR_DEPC_SAVE_STR, 0); } -#endif /* CONFIG_XTENSA_MMU || CONFIG_XTENSA_MPU */ - +#endif /* CONFIG_XTENSA_MMU */ return return_to(interrupted_stack); } @@ -385,7 +502,7 @@ void *xtensa_excint1_c(int *interrupted_stack) #if defined(CONFIG_GDBSTUB) void *xtensa_debugint_c(int *interrupted_stack) { - extern void z_gdb_isr(z_arch_esf_t *esf); + extern void z_gdb_isr(struct arch_esf *esf); z_gdb_isr((void *)interrupted_stack); diff --git a/arch/xtensa/core/window_vectors.S b/arch/xtensa/core/window_vectors.S index 90eba495bde..6c4e8c44803 100644 --- a/arch/xtensa/core/window_vectors.S +++ b/arch/xtensa/core/window_vectors.S @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ #include -#include +#include /* WINDOW OVERFLOW AND UNDERFLOW EXCEPTION VECTORS AND ALLOCA EXCEPTION * HANDLER diff --git a/arch/xtensa/core/xtensa_asm2_util.S b/arch/xtensa/core/xtensa_asm2_util.S index dad8f199359..11b18013033 100644 --- a/arch/xtensa/core/xtensa_asm2_util.S +++ b/arch/xtensa/core/xtensa_asm2_util.S @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ #include -#include -#include +#include +#include #if defined(CONFIG_SIMULATOR_XTENSA) || defined(XT_SIMULATOR) #include @@ -489,13 +489,29 @@ _DoubleExceptionVector: addi a0, a0, -EXCCAUSE_DTLB_MISS beqz a0, _handle_tlb_miss_dblexc + /* Need to stash the DEPC for used by the C handler. + * If we encounter any DTLB misses when PS.EXCM is set, + * this vector will be used and the DEPC register will + * have the new address instead of the one resulted in + * double exception. + */ + rsr.depc a0 + wsr a0, ZSR_DEPC_SAVE + rsr a0, ZSR_DBLEXC j _Level1Vector -#else -#if defined(CONFIG_SIMULATOR_XTENSA) || defined(XT_SIMULATOR) -1: +_TripleFault: +#endif /* CONFIG_XTENSA_MMU */ + +#if XCHAL_HAVE_DEBUG && defined(CONFIG_XTENSA_BREAK_ON_UNRECOVERABLE_EXCEPTIONS) + /* Signals an unhandled double exception, and unrecoverable exceptions. + * Definitely needs debugger to be attached to the hardware or simulator + * to catch this. + */ + break 1, 4 +#elif defined(CONFIG_SIMULATOR_XTENSA) || defined(XT_SIMULATOR) /* Tell simulator to stop executing here, instead of trying to do * an infinite loop (see below). Greatly help with using tracing in * simulator so that traces will not have infinite iterations of @@ -504,14 +520,9 @@ _DoubleExceptionVector: movi a3, 1 movi a2, SYS_exit simcall -#elif XCHAL_HAVE_DEBUG -/* Signals an unhandled double exception */ -1: break 1, 4 -#else -1: #endif +1: j 1b -#endif /* CONFIG_XTENSA_MMU */ #ifdef CONFIG_XTENSA_MMU _handle_tlb_miss_dblexc: diff --git a/arch/xtensa/core/xtensa_backtrace.c b/arch/xtensa/core/xtensa_backtrace.c index 8570fa5dbd6..145d52ce58d 100644 --- a/arch/xtensa/core/xtensa_backtrace.c +++ b/arch/xtensa/core/xtensa_backtrace.c @@ -14,6 +14,10 @@ #elif defined(CONFIG_SOC_XTENSA_DC233C) #include "backtrace_helpers.h" #endif + +#include +#include + static int mask, cause; static inline uint32_t xtensa_cpu_process_stack_pc(uint32_t pc) @@ -36,15 +40,25 @@ static inline uint32_t xtensa_cpu_process_stack_pc(uint32_t pc) static inline bool xtensa_stack_ptr_is_sane(uint32_t sp) { + bool valid; + #if defined(CONFIG_SOC_SERIES_ESP32) - return esp_stack_ptr_is_sane(sp); + valid = esp_stack_ptr_is_sane(sp); #elif defined(CONFIG_SOC_FAMILY_INTEL_ADSP) - return intel_adsp_ptr_is_sane(sp); -#elif defined(CONFIG_SOC_XTENSA_DC233C) - return xtensa_dc233c_stack_ptr_is_sane(sp); + valid = intel_adsp_ptr_is_sane(sp); #else -#warning "xtensa_stack_ptr_is_sane is not defined for this platform" + /* Platform does not have additional requirements on + * whether stack pointer is valid. So use the generic + * test below. + */ + valid = true; #endif + + if (valid) { + valid = !xtensa_is_outside_stack_bounds(sp, 0, UINT32_MAX); + } + + return valid; } static inline bool xtensa_ptr_executable(const void *p) @@ -62,6 +76,13 @@ static inline bool xtensa_ptr_executable(const void *p) bool xtensa_backtrace_get_next_frame(struct xtensa_backtrace_frame_t *frame) { + /* Do not continue backtrace when we encounter an invalid stack + * frame pointer. + */ + if (xtensa_is_outside_stack_bounds((uintptr_t)frame->sp, 0, UINT32_MAX)) { + return false; + } + /* Use frame(i-1)'s BS area located below frame(i)'s * sp to get frame(i-1)'s sp and frame(i-2)'s pc */ @@ -91,14 +112,27 @@ int xtensa_backtrace_print(int depth, int *interrupted_stack) return -1; } + _xtensa_irq_stack_frame_raw_t *frame = (void *)interrupted_stack; + _xtensa_irq_bsa_t *bsa; + + /* Don't dump stack if the stack pointer is invalid as + * any frame elements obtained via de-referencing the + * frame pointer are probably also invalid. Or worse, + * cause another access violation. + */ + if (!xtensa_is_frame_pointer_valid(frame)) { + return -1; + } + + bsa = frame->ptr_to_bsa; + cause = bsa->exccause; + /* Initialize stk_frame with first frame of stack */ struct xtensa_backtrace_frame_t stk_frame; xtensa_backtrace_get_start(&(stk_frame.pc), &(stk_frame.sp), &(stk_frame.next_pc), interrupted_stack); - __asm__ volatile("l32i a4, a3, 0"); - __asm__ volatile("l32i a4, a4, 4"); - __asm__ volatile("mov %0, a4" : "=r"(cause)); + if (cause != EXCCAUSE_INSTR_PROHIBITED) { mask = stk_frame.pc & 0xc0000000; } diff --git a/arch/xtensa/core/xtensa_hifi.S b/arch/xtensa/core/xtensa_hifi.S index 3c311acab0f..dff714cce18 100644 --- a/arch/xtensa/core/xtensa_hifi.S +++ b/arch/xtensa/core/xtensa_hifi.S @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include #include #include diff --git a/arch/xtensa/include/kernel_arch_func.h b/arch/xtensa/include/kernel_arch_func.h index 48599f0e769..4b5bac74ead 100644 --- a/arch/xtensa/include/kernel_arch_func.h +++ b/arch/xtensa/include/kernel_arch_func.h @@ -14,7 +14,7 @@ #include #include #include -#include +#include #ifdef __cplusplus extern "C" { @@ -25,57 +25,7 @@ K_KERNEL_STACK_ARRAY_DECLARE(z_interrupt_stacks, CONFIG_MP_MAX_NUM_CPUS, static ALWAYS_INLINE void arch_kernel_init(void) { - _cpu_t *cpu0 = &_kernel.cpus[0]; -#ifdef CONFIG_KERNEL_COHERENCE - /* Make sure we don't have live data for unexpected cached - * regions due to boot firmware - */ - sys_cache_data_flush_and_invd_all(); - - /* Our cache top stash location might have junk in it from a - * pre-boot environment. Must be zero or valid! - */ - XTENSA_WSR(ZSR_FLUSH_STR, 0); -#endif - - cpu0->nested = 0; - - /* The asm2 scheme keeps the kernel pointer in a scratch SR - * (see zsr.h for generation specifics) for easy access. That - * saves 4 bytes of immediate value to store the address when - * compared to the legacy scheme. But in SMP this record is a - * per-CPU thing and having it stored in a SR already is a big - * win. - */ - XTENSA_WSR(ZSR_CPU_STR, cpu0); - -#ifdef CONFIG_INIT_STACKS - char *stack_start = K_KERNEL_STACK_BUFFER(z_interrupt_stacks[0]); - size_t stack_sz = K_KERNEL_STACK_SIZEOF(z_interrupt_stacks[0]); - char *stack_end = stack_start + stack_sz; - - uint32_t sp; - - __asm__ volatile("mov %0, sp" : "=a"(sp)); - - /* Only clear the interrupt stack if the current stack pointer - * is not within the interrupt stack. Or else we would be - * wiping the in-use stack. - */ - if (((uintptr_t)sp < (uintptr_t)stack_start) || - ((uintptr_t)sp >= (uintptr_t)stack_end)) { - memset(stack_start, 0xAA, stack_sz); - } -#endif - -#ifdef CONFIG_XTENSA_MMU - xtensa_mmu_init(); -#endif - -#ifdef CONFIG_XTENSA_MPU - xtensa_mpu_init(); -#endif } void xtensa_switch(void *switch_to, void **switched_from); diff --git a/arch/xtensa/include/xtensa_asm2_context.h b/arch/xtensa/include/xtensa_asm2_context.h index f06dff077d4..d5593d7adbc 100644 --- a/arch/xtensa/include/xtensa_asm2_context.h +++ b/arch/xtensa/include/xtensa_asm2_context.h @@ -6,6 +6,10 @@ #ifndef ZEPHYR_ARCH_XTENSA_INCLUDE_XTENSA_ASM2_CONTEXT_H_ #define ZEPHYR_ARCH_XTENSA_INCLUDE_XTENSA_ASM2_CONTEXT_H_ +#if defined(__XT_CLANG__) +#include +#endif + #include #include #include diff --git a/arch/xtensa/include/xtensa_asm2_s.h b/arch/xtensa/include/xtensa_asm2_s.h index dddf7bb309c..150df82c35c 100644 --- a/arch/xtensa/include/xtensa_asm2_s.h +++ b/arch/xtensa/include/xtensa_asm2_s.h @@ -7,10 +7,10 @@ #ifndef ZEPHYR_ARCH_XTENSA_INCLUDE_XTENSA_ASM2_S_H #define ZEPHYR_ARCH_XTENSA_INCLUDE_XTENSA_ASM2_S_H -#include +#include #include "xtensa_asm2_context.h" -#include +#include /* Assembler header! This file contains macros designed to be included * only by the assembler. @@ -430,6 +430,22 @@ _xstack_returned_\@: wur.THREADPTR a0 #endif /* XCHAL_HAVE_THREADPTR && CONFIG_USERSPACE */ +#ifdef CONFIG_XTENSA_INTERRUPT_NONPREEMPTABLE + + /* Setting the interrupt mask to the max non-debug level + * to prevent lower priority interrupts being preempted by + * high level interrupts until processing of that lower level + * interrupt has completed. + */ + rsr.ps a0 + movi a3, ~(PS_INTLEVEL_MASK) + and a0, a0, a3 + movi a3, PS_INTLEVEL(ZSR_RFI_LEVEL) + or a0, a0, a3 + wsr.ps a0 + +#else + /* There's a gotcha with level 1 handlers: the INTLEVEL field * gets left at zero and not set like high priority interrupts * do. That works fine for exceptions, but for L1 interrupts, @@ -450,7 +466,9 @@ _xstack_returned_\@: movi a3, PS_INTLEVEL(1) or a0, a0, a3 wsr.ps a0 + _not_l1: +#endif /* CONFIG_XTENSA_INTERRUPT_NONPREEMPTABLE */ /* Setting up the cross stack call below has states where the * resulting frames are invalid/non-reentrant, so we can't @@ -604,6 +622,59 @@ _Level\LVL\()VectorHelper : .global _Level\LVL\()Vector _Level\LVL\()Vector: #endif + +#ifdef CONFIG_XTENSA_MMU +.if \LVL == 1 + /* If there are any TLB misses during interrupt handling, + * the user/kernel/double exception vector will be triggered + * to handle these misses. This results in DEPC and EXCCAUSE + * being overwritten, and then execution returned back to + * this site of TLB misses. When it gets to the C handler, + * it will not see the original cause. So stash + * the EXCCAUSE here so C handler can see the original cause. + * + * For double exception, DEPC in saved in earlier vector + * code. + */ + wsr a0, ZSR_EXCCAUSE_SAVE + + esync + + rsr a0, ZSR_DEPC_SAVE + beqz a0, _not_triple_fault + + /* If stashed DEPC is not zero, we have started servicing + * a double exception and yet we are here because there is + * another exception (through user/kernel if PS.EXCM is + * cleared, or through double if PS.EXCM is set). This can + * be considered triple fault. Although there is no triple + * faults on Xtensa. Once PS.EXCM is set, it keeps going + * through double exception vector for any new exceptions. + * However, our exception code needs to unmask PS.EXCM to + * enable register window operations. So after that, any + * new exceptions will go through the kernel or user vectors + * depending on PS.UM. If there is continuous faults, it may + * keep ping-ponging between double and kernel/user exception + * vectors that may never get resolved. Since we stash DEPC + * during double exception, and the stashed one is only cleared + * once the double exception has been processed, we can use + * the stashed DEPC value to detect if the next exception could + * be considered a triple fault. If such a case exists, simply + * jump to an infinite loop, or quit the simulator, or invoke + * debugger. + */ + rsr a0, ZSR_EXCCAUSE_SAVE + j _TripleFault + +_not_triple_fault: + rsr.exccause a0 + + xsr a0, ZSR_EXCCAUSE_SAVE + + esync +.endif +#endif + addi a1, a1, -___xtensa_irq_bsa_t_SIZEOF s32i a0, a1, ___xtensa_irq_bsa_t_a0_OFFSET s32i a2, a1, ___xtensa_irq_bsa_t_a2_OFFSET diff --git a/arch/xtensa/include/xtensa_internal.h b/arch/xtensa/include/xtensa_internal.h index 60b512ab571..29e08e1fe43 100644 --- a/arch/xtensa/include/xtensa_internal.h +++ b/arch/xtensa/include/xtensa_internal.h @@ -25,7 +25,7 @@ * * @param stack Pointer to stack frame. */ -void xtensa_dump_stack(const z_arch_esf_t *stack); +void xtensa_dump_stack(const void *stack); /** * @brief Get string description from an exception code. @@ -43,7 +43,7 @@ char *xtensa_exccause(unsigned int cause_code); * @param esf Exception context, with details and partial or full register * state when the error occurred. May in some cases be NULL. */ -void xtensa_fatal_error(unsigned int reason, const z_arch_esf_t *esf); +void xtensa_fatal_error(unsigned int reason, const struct arch_esf *esf); /** * @brief Perform a one-way transition from supervisor to user mode. @@ -55,6 +55,25 @@ void xtensa_userspace_enter(k_thread_entry_t user_entry, uintptr_t stack_end, uintptr_t stack_start); +/** + * @brief Check if kernel threads have access to a memory region. + * + * Given a memory region, return whether the current memory management + * hardware configuration would allow kernel threads to read/write + * that region. + * + * This is mainly used to make sure kernel has access to avoid relying + * on page fault to detect invalid mappings. + * + * @param addr Start address of the buffer + * @param size Size of the buffer + * @param write If non-zero, additionally check if the area is writable. + * Otherwise, just check if the memory can be read. + * + * @return False if the permissions don't match. + */ +bool xtensa_mem_kernel_has_access(void *addr, size_t size, int write); + /** * @} */ diff --git a/arch/xtensa/include/xtensa_mpu_priv.h b/arch/xtensa/include/xtensa_mpu_priv.h index 69df1b1037a..32bfb009d34 100644 --- a/arch/xtensa/include/xtensa_mpu_priv.h +++ b/arch/xtensa/include/xtensa_mpu_priv.h @@ -69,6 +69,16 @@ #define XTENSA_MPU_ENTRY_REG_MEMORY_TYPE_MASK \ (0x1FFU << XTENSA_MPU_ENTRY_REG_MEMORY_TYPE_SHIFT) +/** Bit mask for foreground entry returned by probing. */ +#define XTENSA_MPU_PROBE_IS_FG_ENTRY_MASK BIT(31) + +/** Bit mask for background entry returned by probing. */ +#define XTENSA_MPU_PROBE_IS_BG_ENTRY_MASK BIT(30) + +/** Bit mask used to determine if entry is valid returned by probing. */ +#define XTENSA_MPU_PROBE_VALID_ENTRY_MASK \ + (XTENSA_MPU_PROBE_IS_FG_ENTRY_MASK | XTENSA_MPU_PROBE_IS_BG_ENTRY_MASK) + /** * @} */ diff --git a/arch/xtensa/include/xtensa_stack.h b/arch/xtensa/include/xtensa_stack.h new file mode 100644 index 00000000000..71e046d7cbd --- /dev/null +++ b/arch/xtensa/include/xtensa_stack.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_ARCH_XTENSA_XTENSA_STACK_H_ +#define ZEPHYR_ARCH_XTENSA_XTENSA_STACK_H_ + +#include +#include +#include + +#include + +/** + * @defgroup xtensa_stack_internal_apis Xtensa Stack related Internal APIs + * @ingroup xtensa_stack_apis + * @{ + */ + +/** + * @brief Check if memory region is within correct stack boundaries. + * + * Check if the memory region [@a addr, (@a addr + @a sz)) is within + * correct stack boundaries: + * - Interrupt stack if servicing interrupts. + * - Privileged stack if in kernel mode doing syscalls. + * - Thread stack otherwise. + * + * @note When @ps == UINT32_MAX, it checks the whole range of stack + * object because we cannot get PS via frame pointer yet. + * + * @param addr Beginning address of memory region to check. + * @param sz Size of memory region to check. Can be zero. + * @param ps PS register value of interrupted context. Use UINT32_MAX if + * PS cannot be determined at time of call. + * + * @return True if memory region is outside stack bounds, false otherwise. + */ +bool xtensa_is_outside_stack_bounds(uintptr_t addr, size_t sz, uint32_t ps); + +/** + * @brief Check if frame pointer is within correct stack boundaries. + * + * Check if the frame pointer and its associated BSA (base save area) are + * within correct stack boundaries. Use @ref xtensa_is_outside_stack_bounds + * to determine validity. + * + * @param frame Frame Pointer. Cannot be NULL. + */ +bool xtensa_is_frame_pointer_valid(_xtensa_irq_stack_frame_raw_t *frame); + +/** + * @} + */ + +#endif /* ZEPHYR_ARCH_XTENSA_XTENSA_STACK_H_ */ diff --git a/boards/01space/esp32c3_042_oled/Kconfig.defconfig b/boards/01space/esp32c3_042_oled/Kconfig.defconfig new file mode 100644 index 00000000000..4171bb04bc2 --- /dev/null +++ b/boards/01space/esp32c3_042_oled/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright 2022 Google LLC +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 diff --git a/boards/01space/esp32c3_042_oled/Kconfig.esp32c3_042_oled b/boards/01space/esp32c3_042_oled/Kconfig.esp32c3_042_oled new file mode 100644 index 00000000000..8b0fbf42eab --- /dev/null +++ b/boards/01space/esp32c3_042_oled/Kconfig.esp32c3_042_oled @@ -0,0 +1,5 @@ +# Copyright 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32C3_042_OLED + select SOC_ESP32C3_FX4 diff --git a/boards/01space/esp32c3_042_oled/Kconfig.sysbuild b/boards/01space/esp32c3_042_oled/Kconfig.sysbuild new file mode 100644 index 00000000000..3a2d17ac5cf --- /dev/null +++ b/boards/01space/esp32c3_042_oled/Kconfig.sysbuild @@ -0,0 +1,10 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice BOOT_SIGNATURE_TYPE + default BOOT_SIGNATURE_TYPE_NONE +endchoice diff --git a/boards/01space/esp32c3_042_oled/board.cmake b/boards/01space/esp32c3_042_oled/board.cmake new file mode 100644 index 00000000000..2f04d1fe886 --- /dev/null +++ b/boards/01space/esp32c3_042_oled/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/01space/esp32c3_042_oled/board.yml b/boards/01space/esp32c3_042_oled/board.yml new file mode 100644 index 00000000000..40b7b0f5816 --- /dev/null +++ b/boards/01space/esp32c3_042_oled/board.yml @@ -0,0 +1,5 @@ +board: + name: esp32c3_042_oled + vendor: 01space + socs: + - name: esp32c3 diff --git a/boards/01space/esp32c3_042_oled/doc/img/esp32c3_042_oled.webp b/boards/01space/esp32c3_042_oled/doc/img/esp32c3_042_oled.webp new file mode 100644 index 00000000000..74abd1fd467 Binary files /dev/null and b/boards/01space/esp32c3_042_oled/doc/img/esp32c3_042_oled.webp differ diff --git a/boards/01space/esp32c3_042_oled/doc/img/esp32c3_042_oled_pinout.webp b/boards/01space/esp32c3_042_oled/doc/img/esp32c3_042_oled_pinout.webp new file mode 100644 index 00000000000..161e4c0680e Binary files /dev/null and b/boards/01space/esp32c3_042_oled/doc/img/esp32c3_042_oled_pinout.webp differ diff --git a/boards/01space/esp32c3_042_oled/doc/index.rst b/boards/01space/esp32c3_042_oled/doc/index.rst new file mode 100644 index 00000000000..b8f3cbe7bc9 --- /dev/null +++ b/boards/01space/esp32c3_042_oled/doc/index.rst @@ -0,0 +1,172 @@ +.. _01space_esp32c3_042_oled: + +ESP32C3 0.42 OLED +################# + +Overview +******** + +ESP32C3 0.42 OLED is a mini development board based on the `Espressif ESP32-C3`_ +RISC-V WiFi/Bluetooth dual-mode chip. + +For more details see the `01space ESP32C3 0.42 OLED`_ Github repo. + +.. figure:: img/esp32c3_042_oled.webp + :align: center + :alt: 01space ESP32C3 0.42 OLED + + 01space ESP32C3 0.42 OLED + +Hardware +******** + +This board is based on the ESP32-C3-FH4 with WiFi and BLE support. +It features: + +* RISC-V SoC @ 160MHz with 4MB flash and 400kB RAM +* WS2812B RGB serial LED +* 0.42-inch OLED over I2C +* Qwiic I2C connector +* One pushbutton +* Onboard ceramic chip antenna +* On-chip USB-UART converter + +.. note:: + + The RGB led is not supported on this Zephyr board yet. + +.. note:: + + The ESP32-C3 does not have native USB, it has an on-chip USB-serial converter + instead. + +Supported Features +================== + +The 01space ESP32C3 0.42 OLED board configuration supports the following hardware features: + ++-----------+------------+------------------+ +| Interface | Controller | Driver/Component | ++===========+============+==================+ +| PMP | on-chip | arch/riscv | ++-----------+------------+------------------+ +| INTMTRX | on-chip | intc_esp32c3 | ++-----------+------------+------------------+ +| PINMUX | on-chip | pinctrl_esp32 | ++-----------+------------+------------------+ +| USB UART | on-chip | serial_esp32_usb | ++-----------+------------+------------------+ +| GPIO | on-chip | gpio_esp32 | ++-----------+------------+------------------+ +| UART | on-chip | uart_esp32 | ++-----------+------------+------------------+ +| I2C | on-chip | i2c_esp32 | ++-----------+------------+------------------+ +| SPI | on-chip | spi_esp32_spim | ++-----------+------------+------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+------------------+ +| DISPLAY | off-chip | display | ++-----------+------------+------------------+ + +Connections and IOs +=================== + +See the following image: + +.. figure:: img/esp32c3_042_oled_pinout.webp + :align: center + :alt: 01space ESP32C3 0.42 OLED Pinout + + 01space ESP32C3 0.42 OLED Pinout + +It also features a 0.42 inch OLED display, driven by a SSD1306-compatible chip. +It is connected over I2C: SDA on GPIO5, SCL on GPIO6. + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs. Run the command below to +retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Programming and Debugging +************************* + +Standalone application +====================== + +The board can be loaded using a single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: + + This mode does not provide any security features nor OTA updates. + +Use the following command to build a sample hello_world application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32c3_042_oled + :goals: build + +Sysbuild +======== + +:ref:`sysbuild` makes it possible to build and flash all necessary images needed to +bootstrap the board. + +By default, the ESP32 sysbuild configuration creates bootloader (MCUboot) and +application images. + +To build the sample application using sysbuild, use this command: + +.. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/hello_world + :board: esp32c3_042_oled + :goals: build + :west-args: --sysbuild + :compact: + +Flashing +======== + +For the :code:`Hello, world!` application, follow the instructions below. +Assuming the board is connected to ``/dev/ttyACM0`` on Linux. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32c3_042_oled + :goals: flash + :flash-args: --esp-device /dev/ttyACM0 + +Since the Zephyr console is by default on the ``usb_serial`` device, we use +the espressif monitor utility to connect to the console. + +.. code-block:: console + + $ west espressif monitor -p /dev/ttyACM0 + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! esp32c3_042_oled + +References +********** + +.. target-notes:: + +.. _`Espressif ESP32-C3`: https://www.espressif.com/en/products/socs/esp32-c3 +.. _`01space ESP32C3 0.42 OLED`: https://github.com/01Space/ESP32-C3-0.42LCD diff --git a/boards/01space/esp32c3_042_oled/esp32c3_042_oled-pinctrl.dtsi b/boards/01space/esp32c3_042_oled/esp32c3_042_oled-pinctrl.dtsi new file mode 100644 index 00000000000..dec47fbcd44 --- /dev/null +++ b/boards/01space/esp32c3_042_oled/esp32c3_042_oled-pinctrl.dtsi @@ -0,0 +1,43 @@ +/* + * Copyright 2022 Google LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + uart1_default: uart1_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + spim2_default: spim2_default { + group1 { + pinmux = , + ; + }; + group2 { + pinmux = ; + output-low; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; +}; diff --git a/boards/01space/esp32c3_042_oled/esp32c3_042_oled.dts b/boards/01space/esp32c3_042_oled/esp32c3_042_oled.dts new file mode 100644 index 00000000000..c7680c0b152 --- /dev/null +++ b/boards/01space/esp32c3_042_oled/esp32c3_042_oled.dts @@ -0,0 +1,140 @@ +/* + * Copyright 2022 Google LLC + * Copyright 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "esp32c3_042_oled-pinctrl.dtsi" + +/ { + model = "01space ESP32C3 0.42 OLED"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &usb_serial; + zephyr,shell-uart = &usb_serial; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,canbus = &twai; + zephyr,bt-hci = &esp32_bt_hci; + zephyr,display = &eastrising_72x40; + }; + + aliases { + i2c-0 = &i2c0; + watchdog0 = &wdt0; + }; + + /* WS2812B LED connected to GPIO2 */ +}; + +/* Have to use uart1 as some tests are hardcoded for that DTS node :/ */ +&uart1 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + + eastrising_72x40: ssd1306@3c { + compatible = "solomon,ssd1306fb"; + reg = <0x3c>; + + width = <72>; + height = <40>; + + segment-offset = <28>; + page-offset = <0>; + display-offset = <0>; + multiplex-ratio = <0x27>; + prechargep = <0x22>; + ready-time-ms = <10>; + segment-remap; + com-invdir; + use-internal-iref; + }; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&usb_serial { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&wifi { + status = "okay"; +}; + +&esp32_bt_hci { + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x0000F000>; + read-only; + }; + + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/01space/esp32c3_042_oled/esp32c3_042_oled.yaml b/boards/01space/esp32c3_042_oled/esp32c3_042_oled.yaml new file mode 100644 index 00000000000..4f9e9c93778 --- /dev/null +++ b/boards/01space/esp32c3_042_oled/esp32c3_042_oled.yaml @@ -0,0 +1,18 @@ +identifier: esp32c3_042_oled +name: ESP32C3 0.42 OLED +type: mcu +arch: riscv +toolchain: + - zephyr +supported: + - display + - gpio + - i2c + - spi + - uart + - watchdog +testing: + ignore_tags: + - net + - bluetooth +vendor: 01space diff --git a/boards/01space/esp32c3_042_oled/esp32c3_042_oled_defconfig b/boards/01space/esp32c3_042_oled/esp32c3_042_oled_defconfig new file mode 100644 index 00000000000..ef633ce56a1 --- /dev/null +++ b/boards/01space/esp32c3_042_oled/esp32c3_042_oled_defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y diff --git a/boards/01space/esp32c3_042_oled/support/openocd.cfg b/boards/01space/esp32c3_042_oled/support/openocd.cfg new file mode 100644 index 00000000000..7421637880c --- /dev/null +++ b/boards/01space/esp32c3_042_oled/support/openocd.cfg @@ -0,0 +1,6 @@ +set ESP_RTOS none + +source [find interface/esp_usb_jtag.cfg] + +source [find target/esp32c3.cfg] +adapter speed 5000 diff --git a/boards/01space/index.rst b/boards/01space/index.rst new file mode 100644 index 00000000000..322a0f31840 --- /dev/null +++ b/boards/01space/index.rst @@ -0,0 +1,10 @@ +.. _boards-01space: + +01space +####### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/96boards/aerocore2/96b_aerocore2_defconfig b/boards/96boards/aerocore2/96b_aerocore2_defconfig index 490ce68a742..e753aa8269c 100644 --- a/boards/96boards/aerocore2/96b_aerocore2_defconfig +++ b/boards/96boards/aerocore2/96b_aerocore2_defconfig @@ -15,9 +15,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/96boards/aerocore2/doc/index.rst b/boards/96boards/aerocore2/doc/index.rst index ca12b694950..489433e09f3 100644 --- a/boards/96boards/aerocore2/doc/index.rst +++ b/boards/96boards/aerocore2/doc/index.rst @@ -311,7 +311,7 @@ You should see following confirmation on your Linux host: usb 1-2.1: SerialNumber: 3574364C3034 Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/96boards/argonkey/96b_argonkey_defconfig b/boards/96boards/argonkey/96b_argonkey_defconfig index 82ee7285d52..3fe5e4f9882 100644 --- a/boards/96boards/argonkey/96b_argonkey_defconfig +++ b/boards/96boards/argonkey/96b_argonkey_defconfig @@ -12,12 +12,6 @@ CONFIG_SERIAL=y # enable GPIO CONFIG_GPIO=y -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - # console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/96boards/argonkey/doc/index.rst b/boards/96boards/argonkey/doc/index.rst index 810ab2e5781..f5cc913f390 100644 --- a/boards/96boards/argonkey/doc/index.rst +++ b/boards/96boards/argonkey/doc/index.rst @@ -145,7 +145,7 @@ Programming and Debugging Building ======== -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/96boards/avenger96/96b_avenger96_defconfig b/boards/96boards/avenger96/96b_avenger96_defconfig index 11db7ac995f..e3edeecca13 100644 --- a/boards/96boards/avenger96/96b_avenger96_defconfig +++ b/boards/96boards/avenger96/96b_avenger96_defconfig @@ -11,9 +11,6 @@ CONFIG_GPIO=y CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y -# clock configuration -CONFIG_CLOCK_CONTROL=y - # console (remote proc console by default) CONFIG_CONSOLE=y CONFIG_RAM_CONSOLE=y @@ -21,6 +18,3 @@ CONFIG_RAM_CONSOLE_BUFFER_SIZE=1024 # uart console (overrides remote proc console) CONFIG_UART_CONSOLE=n - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/96boards/carbon/96b_carbon_stm32f401xe_defconfig b/boards/96boards/carbon/96b_carbon_stm32f401xe_defconfig index c729b83e3d0..51eadcb4809 100644 --- a/boards/96boards/carbon/96b_carbon_stm32f401xe_defconfig +++ b/boards/96boards/carbon/96b_carbon_stm32f401xe_defconfig @@ -14,9 +14,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/96boards/carbon/doc/stm32f401xe.rst b/boards/96boards/carbon/doc/stm32f401xe.rst index 222c6056a38..c493c0a7fd6 100644 --- a/boards/96boards/carbon/doc/stm32f401xe.rst +++ b/boards/96boards/carbon/doc/stm32f401xe.rst @@ -299,7 +299,7 @@ You should see following confirmation on your Linux host: usb 1-2.1: SerialNumber: 3574364C3034 Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -347,7 +347,7 @@ in general, see :ref:`build_an_application`. :board: 96b_carbon/stm32f401xe :goals: build flash -#. Refer to the instructions in :ref:`peripheral_hr` for how +#. Refer to the instructions in :zephyr:code-sample:`ble_peripheral_hr` for how to verify functionality. Congratulations! Your 96Boards Carbon now has Bluetooth diff --git a/boards/96boards/meerkat96/Kconfig.defconfig b/boards/96boards/meerkat96/Kconfig.defconfig deleted file mode 100644 index a401b7ecb89..00000000000 --- a/boards/96boards/meerkat96/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# 96Boards Meerkat96 board - -# Copyright (c) 2019, Linaro Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_96B_MEERKAT96 - -if !XIP -config FLASH_SIZE - default 0 -config FLASH_BASE_ADDRESS - default 0 -endif - -endif # BOARD_96B_MEERKAT96 diff --git a/boards/96boards/neonkey/96b_neonkey_defconfig b/boards/96boards/neonkey/96b_neonkey_defconfig index 82ee7285d52..3fe5e4f9882 100644 --- a/boards/96boards/neonkey/96b_neonkey_defconfig +++ b/boards/96boards/neonkey/96b_neonkey_defconfig @@ -12,12 +12,6 @@ CONFIG_SERIAL=y # enable GPIO CONFIG_GPIO=y -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - # console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/96boards/neonkey/doc/index.rst b/boards/96boards/neonkey/doc/index.rst index 96308784941..df9fb1619c1 100644 --- a/boards/96boards/neonkey/doc/index.rst +++ b/boards/96boards/neonkey/doc/index.rst @@ -135,7 +135,7 @@ Programming and Debugging Building ======== -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/96boards/nitrogen/doc/index.rst b/boards/96boards/nitrogen/doc/index.rst index 952f11237bf..df3d0236ca5 100644 --- a/boards/96boards/nitrogen/doc/index.rst +++ b/boards/96boards/nitrogen/doc/index.rst @@ -273,7 +273,7 @@ and install a more recent version of pyOCD. Flashing an Application to 96Boards Nitrogen ============================================ -Here is an example for the :ref:`hello_world` application. This +Here is an example for the :zephyr:code-sample:`hello_world` application. This requires installing the :ref:`pyocd-debug-host-tools`. .. zephyr-app-commands:: @@ -302,7 +302,7 @@ Debugging with GDB ================== You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. This also requires pyOCD. +:zephyr:code-sample:`hello_world` application. This also requires pyOCD. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez_defconfig b/boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez_defconfig index c729b83e3d0..51eadcb4809 100644 --- a/boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez_defconfig +++ b/boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez_defconfig @@ -14,9 +14,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/96boards/stm32_sensor_mez/doc/index.rst b/boards/96boards/stm32_sensor_mez/doc/index.rst index 350d4720a80..1539a8148a1 100644 --- a/boards/96boards/stm32_sensor_mez/doc/index.rst +++ b/boards/96boards/stm32_sensor_mez/doc/index.rst @@ -181,7 +181,7 @@ Programming and Debugging Building ======== -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -198,7 +198,7 @@ included in the Zephyr SDK. Flashing an application to 96Boards STM32 Sensor Mezzanine ---------------------------------------------------------- -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your 96Boards STM32 Sensor Mezzanine board. @@ -224,7 +224,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/96boards/wistrio/96b_wistrio_defconfig b/boards/96boards/wistrio/96b_wistrio_defconfig index 23d51e28afa..3f228374bc9 100644 --- a/boards/96boards/wistrio/96b_wistrio_defconfig +++ b/boards/96boards/wistrio/96b_wistrio_defconfig @@ -10,12 +10,6 @@ CONFIG_SERIAL=y # enable GPIO CONFIG_GPIO=y -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - # console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/96boards/wistrio/doc/96b_wistrio.rst b/boards/96boards/wistrio/doc/96b_wistrio.rst index 14f93e6bae1..8db31fcf6cb 100644 --- a/boards/96boards/wistrio/doc/96b_wistrio.rst +++ b/boards/96boards/wistrio/doc/96b_wistrio.rst @@ -148,7 +148,7 @@ More detailed information on activating the ROM bootloader can be found in Chapter 29 of Application note `AN2606`_. The ROM bootloader supports flashing via UART, and I2C protocols. -Here is an example for building and flashing the :ref:`hello_world` application using `stm32flash`_ command line utility: +Here is an example for building and flashing the :zephyr:code-sample:`hello_world` application using `stm32flash`_ command line utility: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/CMakeLists.txt b/boards/CMakeLists.txt index 02e9e158bb8..41a6c6e6010 100644 --- a/boards/CMakeLists.txt +++ b/boards/CMakeLists.txt @@ -17,3 +17,5 @@ if(EXISTS ${BOARD_DIR}/CMakeLists.txt) add_subdirectory(${BOARD_DIR} ${build_dir}) endif() + +add_subdirectory(shields) diff --git a/boards/Kconfig b/boards/Kconfig index 0e981cce1ce..8f186b32caf 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -37,6 +37,8 @@ config BOARD_DEPRECATED_RELEASE the Zephyr release that the board configuration will be removed. When set, any build for that board will generate a clearly visible deprecation warning. + When adding this to a BOARD, remember to follow the instructions in + https://docs.zephyrproject.org/latest/develop/api/api_lifecycle.html#deprecated config QEMU_TARGET bool diff --git a/boards/acrn/acrn/doc/index.rst b/boards/acrn/acrn/doc/index.rst index 9251284106d..5cf24a37232 100644 --- a/boards/acrn/acrn/doc/index.rst +++ b/boards/acrn/acrn/doc/index.rst @@ -5,8 +5,8 @@ Zephyr's is capable of running as a guest under the x86 ACRN hypervisor (see https://projectacrn.org/). The process for getting this to work is somewhat involved, however. -ACRN hypervisor supports a hybrid scenario where Zephyr runs in a so- -called "pre-launched" mode. This means Zephyr will access the ACRN +ACRN hypervisor supports a hybrid scenario where Zephyr runs in a so-called +"pre-launched" mode. This means Zephyr will access the ACRN hypervisor directly without involving the SOS VM. This is the most practical user scenario in the real world because Zephyr's real-time and safety capability can be assured without influence from other diff --git a/boards/actinius/icarus/actinius_icarus_common.dtsi b/boards/actinius/icarus/actinius_icarus_common.dtsi index ab0839205bf..39616df663f 100644 --- a/boards/actinius/icarus/actinius_icarus_common.dtsi +++ b/boards/actinius/icarus/actinius_icarus_common.dtsi @@ -166,62 +166,8 @@ pinctrl-names = "default", "sleep"; }; -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x10000>; - }; - slot0_partition: partition@10000 { - label = "image-0"; - }; - slot0_ns_partition: partition@50000 { - label = "image-0-nonsecure"; - }; - slot1_partition: partition@80000 { - label = "image-1"; - }; - slot1_ns_partition: partition@c0000 { - label = "image-1-nonsecure"; - }; - scratch_partition: partition@f0000 { - label = "image-scratch"; - reg = <0x000f0000 0xa000>; - }; - storage_partition: partition@fa000 { - label = "storage"; - reg = <0x000fa000 0x00006000>; - }; - }; -}; - -/ { - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_s: image_s@20000000 { - /* Secure image memory */ - }; - - sram0_modem: image_modem@20016000 { - /* Modem (shared) memory */ - }; - - sram0_ns: image_ns@20020000 { - /* Non-Secure image memory */ - }; - }; -}; - /* Include file with mappings and aliases for feather compatibility */ #include "feather_connector.dtsi" -/* Include partition configuration file */ -#include "actinius_icarus_partition_conf.dtsi" +/* Include default memory partition configuration file */ +#include diff --git a/boards/actinius/icarus/actinius_icarus_common_2_0_0.dtsi b/boards/actinius/icarus/actinius_icarus_common_2_0_0.dtsi index 9c63a8de335..802437900a8 100644 --- a/boards/actinius/icarus/actinius_icarus_common_2_0_0.dtsi +++ b/boards/actinius/icarus/actinius_icarus_common_2_0_0.dtsi @@ -39,10 +39,6 @@ }; / { - aliases { - spi-flash0 = &w25q64; - }; - charger_enable: charger-enable { compatible = "actinius-charger-enable"; gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; diff --git a/boards/actinius/icarus/actinius_icarus_partition_conf.dtsi b/boards/actinius/icarus/actinius_icarus_partition_conf.dtsi deleted file mode 100644 index 10025e29d02..00000000000 --- a/boards/actinius/icarus/actinius_icarus_partition_conf.dtsi +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2019-2022 Actinius - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* - * Default Flash planning for actinius_icarus. - * - * Zephyr build for nRF9160 with ARM TrustZone-M support, - * implies building Secure and Non-Secure Zephyr images. - * - * Secure image will be placed, by default, in flash0 - * (or in slot0, if MCUboot is present). - * Secure image will use sram0 for system memory. - * - * Non-Secure image will be placed in slot0_ns, and use - * sram0_ns for system memory. - * - * Note that the Secure image only requires knowledge of - * the beginning of the Non-Secure image (not its size). - */ - -&slot0_partition { - reg = <0x00010000 0x40000>; -}; - -&slot0_ns_partition { - reg = <0x00050000 0x30000>; -}; - -&slot1_partition { - reg = <0x00080000 0x40000>; -}; - -&slot1_ns_partition { - reg = <0x000c0000 0x30000>; -}; - -/* Default SRAM planning when building for nRF9160 with - * ARM TrustZone-M support - * - Lowest 88 kB SRAM allocated to Secure image (sram0_s). - * - 40 kB SRAM reserved for and used by the modem library - * (sram0_modem). This memory is Non-Secure. - * - Upper 128 kB allocated to Non-Secure image (sram0_ns). - */ - -&sram0_s { - reg = <0x20000000 DT_SIZE_K(88)>; -}; - -&sram0_modem { - reg = <0x20016000 DT_SIZE_K(40)>; -}; - -&sram0_ns { - reg = <0x20020000 DT_SIZE_K(128)>; -}; diff --git a/boards/actinius/icarus_bee/actinius_icarus_bee_common.dtsi b/boards/actinius/icarus_bee/actinius_icarus_bee_common.dtsi index 0bc57cd205a..4d302d006fb 100644 --- a/boards/actinius/icarus_bee/actinius_icarus_bee_common.dtsi +++ b/boards/actinius/icarus_bee/actinius_icarus_bee_common.dtsi @@ -79,7 +79,6 @@ mcuboot-button0 = &button0; mcuboot-led0 = &blue_led; watchdog0 = &wdt0; - spi-flash0 = &w25q64; accel0 = &lis2dh12_accel; }; @@ -157,59 +156,5 @@ pinctrl-names = "default", "sleep"; }; -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x10000>; - }; - slot0_partition: partition@10000 { - label = "image-0"; - }; - slot0_ns_partition: partition@50000 { - label = "image-0-nonsecure"; - }; - slot1_partition: partition@80000 { - label = "image-1"; - }; - slot1_ns_partition: partition@c0000 { - label = "image-1-nonsecure"; - }; - scratch_partition: partition@f0000 { - label = "image-scratch"; - reg = <0x000f0000 0xa000>; - }; - storage_partition: partition@fa000 { - label = "storage"; - reg = <0x000fa000 0x00006000>; - }; - }; -}; - -/ { - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_s: image_s@20000000 { - /* Secure image memory */ - }; - - sram0_modem: image_modem@20016000 { - /* Modem (shared) memory */ - }; - - sram0_ns: image_ns@20020000 { - /* Non-Secure image memory */ - }; - }; -}; - -/* Include partition configuration file */ -#include "actinius_icarus_bee_partition_conf.dtsi" +/* Include default memory partition configuration file */ +#include diff --git a/boards/actinius/icarus_bee/actinius_icarus_bee_partition_conf.dtsi b/boards/actinius/icarus_bee/actinius_icarus_bee_partition_conf.dtsi deleted file mode 100644 index 7f0713fab2f..00000000000 --- a/boards/actinius/icarus_bee/actinius_icarus_bee_partition_conf.dtsi +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2021-2022 Actinius - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* - * Default Flash planning for actinius_icarus_bee. - * - * Zephyr build for nRF9160 with ARM TrustZone-M support, - * implies building Secure and Non-Secure Zephyr images. - * - * Secure image will be placed, by default, in flash0 - * (or in slot0, if MCUboot is present). - * Secure image will use sram0 for system memory. - * - * Non-Secure image will be placed in slot0_ns, and use - * sram0_ns for system memory. - * - * Note that the Secure image only requires knowledge of - * the beginning of the Non-Secure image (not its size). - */ - -&slot0_partition { - reg = <0x00010000 0x40000>; -}; - -&slot0_ns_partition { - reg = <0x00050000 0x30000>; -}; - -&slot1_partition { - reg = <0x00080000 0x40000>; -}; - -&slot1_ns_partition { - reg = <0x000c0000 0x30000>; -}; - -/* Default SRAM planning when building for nRF9160 with - * ARM TrustZone-M support - * - Lowest 88 kB SRAM allocated to Secure image (sram0_s). - * - 40 kB SRAM reserved for and used by the modem library - * (sram0_modem). This memory is Non-Secure. - * - Upper 128 kB allocated to Non-Secure image (sram0_ns). - */ - -&sram0_s { - reg = <0x20000000 DT_SIZE_K(88)>; -}; - -&sram0_modem { - reg = <0x20016000 DT_SIZE_K(40)>; -}; - -&sram0_ns { - reg = <0x20020000 DT_SIZE_K(128)>; -}; diff --git a/boards/actinius/icarus_som/actinius_icarus_som_common.dtsi b/boards/actinius/icarus_som/actinius_icarus_som_common.dtsi index 46f5f5ab95d..605b2bdd3e7 100644 --- a/boards/actinius/icarus_som/actinius_icarus_som_common.dtsi +++ b/boards/actinius/icarus_som/actinius_icarus_som_common.dtsi @@ -65,59 +65,5 @@ }; }; -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x10000>; - }; - slot0_partition: partition@10000 { - label = "image-0"; - }; - slot0_ns_partition: partition@50000 { - label = "image-0-nonsecure"; - }; - slot1_partition: partition@80000 { - label = "image-1"; - }; - slot1_ns_partition: partition@c0000 { - label = "image-1-nonsecure"; - }; - scratch_partition: partition@f0000 { - label = "image-scratch"; - reg = <0x000f0000 0xa000>; - }; - storage_partition: partition@fa000 { - label = "storage"; - reg = <0x000fa000 0x00006000>; - }; - }; -}; - -/ { - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_s: image_s@20000000 { - /* Secure image memory */ - }; - - sram0_modem: image_modem@20016000 { - /* Modem (shared) memory */ - }; - - sram0_ns: image_ns@20020000 { - /* Non-Secure image memory */ - }; - }; -}; - -/* Include partition configuration file */ -#include "actinius_icarus_som_partition_conf.dtsi" +/* Include default memory partition configuration file */ +#include diff --git a/boards/actinius/icarus_som/actinius_icarus_som_partition_conf.dtsi b/boards/actinius/icarus_som/actinius_icarus_som_partition_conf.dtsi deleted file mode 100644 index 69340365b03..00000000000 --- a/boards/actinius/icarus_som/actinius_icarus_som_partition_conf.dtsi +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2021-2022 Actinius - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* - * Default Flash planning for actinius_icarus_som. - * - * Zephyr build for nRF9160 with ARM TrustZone-M support, - * implies building Secure and Non-Secure Zephyr images. - * - * Secure image will be placed, by default, in flash0 - * (or in slot0, if MCUboot is present). - * Secure image will use sram0 for system memory. - * - * Non-Secure image will be placed in slot0_ns, and use - * sram0_ns for system memory. - * - * Note that the Secure image only requires knowledge of - * the beginning of the Non-Secure image (not its size). - */ - -&slot0_partition { - reg = <0x00010000 0x40000>; -}; - -&slot0_ns_partition { - reg = <0x00050000 0x30000>; -}; - -&slot1_partition { - reg = <0x00080000 0x40000>; -}; - -&slot1_ns_partition { - reg = <0x000c0000 0x30000>; -}; - -/* Default SRAM planning when building for nRF9160 with - * ARM TrustZone-M support - * - Lowest 88 kB SRAM allocated to Secure image (sram0_s). - * - 40 kB SRAM reserved for and used by the modem library - * (sram0_modem). This memory is Non-Secure. - * - Upper 128 kB allocated to Non-Secure image (sram0_ns). - */ - -&sram0_s { - reg = <0x20000000 DT_SIZE_K(88)>; -}; - -&sram0_modem { - reg = <0x20016000 DT_SIZE_K(40)>; -}; - -&sram0_ns { - reg = <0x20020000 DT_SIZE_K(128)>; -}; diff --git a/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_common-pinctrl.dtsi b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_common-pinctrl.dtsi index a43e5e2b2c5..17ca10ef713 100644 --- a/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_common-pinctrl.dtsi +++ b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_common-pinctrl.dtsi @@ -68,7 +68,7 @@ }; }; - pwm0_default: pwm0_default { + pwm0_default: pwm0_default { group1 { psels = ; nordic,invert; diff --git a/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_common.dtsi b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_common.dtsi index 317b0d153b7..f084595540f 100644 --- a/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_common.dtsi +++ b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_common.dtsi @@ -55,7 +55,6 @@ mcuboot-led0 = &blue_led; watchdog0 = &wdt0; accel0 = &lis2dh12_accel; - spi-flash0 = &w25q64; led-strip = &neopixel_led; }; @@ -156,62 +155,8 @@ neopixel_spi: &spi1 { pinctrl-names = "default", "sleep"; }; -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x10000>; - }; - slot0_partition: partition@10000 { - label = "image-0"; - }; - slot0_ns_partition: partition@50000 { - label = "image-0-nonsecure"; - }; - slot1_partition: partition@80000 { - label = "image-1"; - }; - slot1_ns_partition: partition@c0000 { - label = "image-1-nonsecure"; - }; - scratch_partition: partition@f0000 { - label = "image-scratch"; - reg = <0x000f0000 0xa000>; - }; - storage_partition: partition@fa000 { - label = "storage"; - reg = <0x000fa000 0x00006000>; - }; - }; -}; - -/ { - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_s: image_s@20000000 { - /* Secure image memory */ - }; - - sram0_modem: image_modem@20016000 { - /* Modem (shared) memory */ - }; - - sram0_ns: image_ns@20020000 { - /* Non-Secure image memory */ - }; - }; -}; - /* Include file with mappings and aliases for arduino compatibility */ #include "arduino_connector.dtsi" -/* Include partition configuration file */ -#include "actinius_icarus_som_dk_partition_conf.dtsi" +/* Include default memory partition configuration file */ +#include diff --git a/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_partition_conf.dtsi b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_partition_conf.dtsi deleted file mode 100644 index 0d581732694..00000000000 --- a/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_partition_conf.dtsi +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2022 Actinius - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* - * Default Flash planning for actinius_icarus_som_dk. - * - * Zephyr build for nRF9160 with ARM TrustZone-M support, - * implies building Secure and Non-Secure Zephyr images. - * - * Secure image will be placed, by default, in flash0 - * (or in slot0, if MCUboot is present). - * Secure image will use sram0 for system memory. - * - * Non-Secure image will be placed in slot0_ns, and use - * sram0_ns for system memory. - * - * Note that the Secure image only requires knowledge of - * the beginning of the Non-Secure image (not its size). - */ - -&slot0_partition { - reg = <0x00010000 0x40000>; -}; - -&slot0_ns_partition { - reg = <0x00050000 0x30000>; -}; - -&slot1_partition { - reg = <0x00080000 0x40000>; -}; - -&slot1_ns_partition { - reg = <0x000c0000 0x30000>; -}; - -/* Default SRAM planning when building for nRF9160 with - * ARM TrustZone-M support - * - Lowest 88 kB SRAM allocated to Secure image (sram0_s). - * - 40 kB SRAM reserved for and used by the modem library - * (sram0_modem). This memory is Non-Secure. - * - Upper 128 kB allocated to Non-Secure image (sram0_ns). - */ - -&sram0_s { - reg = <0x20000000 DT_SIZE_K(88)>; -}; - -&sram0_modem { - reg = <0x20016000 DT_SIZE_K(40)>; -}; - -&sram0_ns { - reg = <0x20020000 DT_SIZE_K(128)>; -}; diff --git a/boards/adafruit/feather/Kconfig b/boards/adafruit/feather/Kconfig deleted file mode 100644 index e266540aa87..00000000000 --- a/boards/adafruit/feather/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Adafruit Feather nRF52840 Express board configuration - -# Copyright (c) 2020 Tobias Svehagen -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_ADAFRUIT_FEATHER diff --git a/boards/adafruit/feather/Kconfig.adafruit_feather b/boards/adafruit/feather/Kconfig.adafruit_feather deleted file mode 100644 index ed952670ce1..00000000000 --- a/boards/adafruit/feather/Kconfig.adafruit_feather +++ /dev/null @@ -1,7 +0,0 @@ -# Adafruit Feather nRF52840 Express board configuration - -# Copyright (c) 2020 Tobias Svehagen -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ADAFRUIT_FEATHER - select SOC_NRF52840_QIAA diff --git a/boards/adafruit/feather/Kconfig.defconfig b/boards/adafruit/feather/Kconfig.defconfig deleted file mode 100644 index 3ae6f23be55..00000000000 --- a/boards/adafruit/feather/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Adafruit Feather nRF52840 Express board configuration - -# Copyright (c) 2020 Tobias Svehagen -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ADAFRUIT_FEATHER - -config BT_CTLR - default BT - -endif # BOARD_ADAFRUIT_FEATHER diff --git a/boards/adafruit/feather/adafruit_feather_nrf52840.dts b/boards/adafruit/feather/adafruit_feather_nrf52840.dts deleted file mode 100644 index 2333e5becbe..00000000000 --- a/boards/adafruit/feather/adafruit_feather_nrf52840.dts +++ /dev/null @@ -1,176 +0,0 @@ -/* - * Copyright (c) 2020 Tobias Svehagen - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "feather_connector.dtsi" -#include "adafruit_feather_nrf52840-pinctrl.dtsi" -#include - -/ { - model = "Adafruit Feather nRF52840 Express"; - compatible = "adafruit,feather-nrf52840"; - - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,uart-mcumgr = &uart0; - zephyr,bt-mon-uart = &uart0; - zephyr,bt-c2h-uart = &uart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - zephyr,ieee802154 = &ieee802154; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpio1 15 0>; - label = "Red LED"; - }; - led1: led_1 { - gpios = <&gpio1 10 0>; - label = "Blue LED"; - }; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - gpios = <&gpio1 2 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button switch"; - zephyr,code = ; - }; - }; - - vbatt { - compatible = "voltage-divider"; - io-channels = <&adc 5>; - output-ohms = <100000>; - full-ohms = <(100000 + 100000)>; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0; - led1 = &led1; - sw0 = &button0; - watchdog0 = &wdt0; - spi-flash0 = &gd25q16; - }; -}; - -&adc { - status = "okay"; -}; - -&uicr { - gpio-as-nreset; -}; - -&gpiote { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&uart0 { - compatible = "nordic,nrf-uart"; - current-speed = <115200>; - status = "okay"; - pinctrl-0 = <&uart0_default>; - pinctrl-1 = <&uart0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&i2c0 { - compatible = "nordic,nrf-twi"; - status = "okay"; - pinctrl-0 = <&i2c0_default>; - pinctrl-1 = <&i2c0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&spi1 { - compatible = "nordic,nrf-spi"; - status = "okay"; - pinctrl-0 = <&spi1_default>; - pinctrl-1 = <&spi1_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&qspi { - status = "okay"; - pinctrl-0 = <&qspi_default>; - pinctrl-1 = <&qspi_sleep>; - pinctrl-names = "default", "sleep"; - gd25q16: gd25q16@0 { - compatible = "nordic,qspi-nor"; - reg = <0>; - writeoc = "pp4o"; - readoc = "read4io"; - sck-frequency = <16000000>; - jedec-id = [c8 40 15]; - size = <16777216>; - has-dpd; - t-enter-dpd = <20000>; - t-exit-dpd = <20000>; - quad-enable-requirements = "S2B1v1"; - }; -}; - -&ieee802154 { - status = "okay"; -}; - -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000C000>; - }; - slot0_partition: partition@c000 { - label = "image-0"; - reg = <0x0000C000 0x00067000>; - }; - slot1_partition: partition@73000 { - label = "image-1"; - reg = <0x00073000 0x00067000>; - }; - scratch_partition: partition@da000 { - label = "image-scratch"; - reg = <0x000da000 0x0001e000>; - }; - - /* - * The flash starting at 0x000f8000 and ending at - * 0x000fffff is reserved for use by the application. - */ - - /* Storage partition will be used by FCB/NFFS/NVS if enabled. */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; - -zephyr_udc0: &usbd { - compatible = "nordic,nrf-usbd"; - status = "okay"; -}; diff --git a/boards/adafruit/feather/adafruit_feather_nrf52840_defconfig b/boards/adafruit/feather/adafruit_feather_nrf52840_defconfig deleted file mode 100644 index 7167aca850a..00000000000 --- a/boards/adafruit/feather/adafruit_feather_nrf52840_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Enable MPU -CONFIG_ARM_MPU=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/adafruit/feather/board.cmake b/boards/adafruit/feather/board.cmake deleted file mode 100644 index c351ecd3a0b..00000000000 --- a/boards/adafruit/feather/board.cmake +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000") -board_runner_args(pyocd "--target=nrf52840" "--frequency=4000000") -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/blackmagicprobe.board.cmake) diff --git a/boards/adafruit/feather/board.yml b/boards/adafruit/feather/board.yml deleted file mode 100644 index f4ae7ce2d19..00000000000 --- a/boards/adafruit/feather/board.yml +++ /dev/null @@ -1,5 +0,0 @@ -board: - name: adafruit_feather - vendor: adafruit - socs: - - name: nrf52840 diff --git a/boards/adafruit/feather/doc/index.rst b/boards/adafruit/feather/doc/index.rst deleted file mode 100644 index 241f11e7305..00000000000 --- a/boards/adafruit/feather/doc/index.rst +++ /dev/null @@ -1,146 +0,0 @@ -.. _adafruit_feather_nrf52840: - -Adafruit Feather nRF52840 Express -################################# - -Overview -******** - -The Adafruit Feather nRF52840 provides support for the Nordic Semiconductor -nRF52840 ARM Cortex-M4F CPU and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/adafruit_feather_nrf52840.jpg - :align: center - :alt: Adafruit Feather nRF52840 Express - -Hardware -******** - -- nRF52840 ARM Cortex-M4F processor at 64 MHz -- 1 MB flash memory and 256 KB of SRAM -- Battery connector and charger for 3.7 V lithium polymer batteries -- Charging indicator LED -- 2 User LEDs -- 1 NeoPixel LED -- Reset button -- SWD connector - -Supported Features -================== - -The Adafruit Feather nRF52840 board configuration supports the -following hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| SPI | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. - -Connections and IOs -=================== - -The `Adafruit Feather nRF52840 Express Learn site`_ has detailed -information about the board including `pinouts`_ and the `schematic`_. - -LED ---- - -* LED0 (red) = P1.15 -* LED1 (blue) = P1.10 - -Push buttons ------------- - -* SWITCH = P1.02 -* RESET = P0.18 - -Programming and Debugging -************************* - -Applications for the ``adafruit_feather/nrf52840`` board configuration -can be built and flashed in the usual way (see :ref:`build_an_application` -and :ref:`application_run` for more details). - -Flashing -======== - -Flashing Zephyr onto the ``adafruit_feather_nrf52480`` board requires -an external programmer. The programmer is attached to the SWD header. - -Build the Zephyr kernel and the :zephyr:code-sample:`blinky` sample application. - - .. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: adafruit_feather/nrf52840 - :goals: build - :compact: - -Flash the image. - - .. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: adafruit_feather/nrf52840 - :goals: flash - :compact: - -You should see the red LED blink. - -References -********** - -.. target-notes:: - -.. _Adafruit Feather nRF52840 Express Learn site: - https://learn.adafruit.com/introducing-the-adafruit-nrf52840-feather/ - -.. _pinouts: - https://learn.adafruit.com/introducing-the-adafruit-nrf52840-feather/pinouts - -.. _schematic: - https://learn.adafruit.com/introducing-the-adafruit-nrf52840-feather/downloads diff --git a/boards/adafruit/feather_m0_basic_proto/doc/index.rst b/boards/adafruit/feather_m0_basic_proto/doc/index.rst index a9dc7f0c229..04206783b15 100644 --- a/boards/adafruit/feather_m0_basic_proto/doc/index.rst +++ b/boards/adafruit/feather_m0_basic_proto/doc/index.rst @@ -110,7 +110,7 @@ the reset button twice. Flashing ======== -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/adafruit/feather_m0_basic_proto/feather_connector.dtsi b/boards/adafruit/feather_m0_basic_proto/feather_connector.dtsi index 842da758f9b..f3f4d1e222a 100644 --- a/boards/adafruit/feather_m0_basic_proto/feather_connector.dtsi +++ b/boards/adafruit/feather_m0_basic_proto/feather_connector.dtsi @@ -5,4 +5,35 @@ * SPDX-License-Identifier: Apache-2.0 */ +/ { + feather_header: connector { + compatible = "adafruit-feather-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &porta 2 0>, /* A0 */ + <1 0 &portb 8 0>, /* A1 */ + <2 0 &portb 9 0>, /* A2 */ + <3 0 &porta 4 0>, /* A3 */ + <4 0 &porta 5 0>, /* A4 */ + <5 0 &portb 2 0>, /* A5 */ + <6 0 &portb 11 0>, /* SCK */ + <7 0 &portb 10 0>, /* MOSI */ + <8 0 &porta 12 0>, /* MISO */ + <9 0 &porta 11 0>, /* RX / D0 */ + <10 0 &porta 10 0>, /* TX / D1 */ + <11 0 &porta 13 0>, /* GND (NC) */ + <12 0 &porta 22 0>, /* SDA */ + <13 0 &porta 23 0>, /* SCL */ + <14 0 &porta 15 0>, /* D5 */ + <15 0 &porta 20 0>, /* D6 */ + <16 0 &porta 7 0>, /* D9 */ + <17 0 &porta 18 0>, /* D10 */ + <18 0 &porta 16 0>, /* D11 */ + <19 0 &porta 19 0>, /* D12 */ + <20 0 &porta 17 0>; /* D13 */ + }; +}; + feather_i2c: &sercom3 {}; +feather_spi: &sercom4 {}; diff --git a/boards/adafruit/feather_m0_lora/doc/index.rst b/boards/adafruit/feather_m0_lora/doc/index.rst index 3303c6e480c..b75f73d6fdc 100644 --- a/boards/adafruit/feather_m0_lora/doc/index.rst +++ b/boards/adafruit/feather_m0_lora/doc/index.rst @@ -119,7 +119,7 @@ the reset button twice. Flashing ======== -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/adafruit/feather_nrf52840/Kconfig.adafruit_feather_nrf52840 b/boards/adafruit/feather_nrf52840/Kconfig.adafruit_feather_nrf52840 new file mode 100644 index 00000000000..7364e9c0d70 --- /dev/null +++ b/boards/adafruit/feather_nrf52840/Kconfig.adafruit_feather_nrf52840 @@ -0,0 +1,8 @@ +# Adafruit Feather nRF52840 Express board configuration + +# Copyright (c) 2020 Tobias Svehagen +# Copyright (c) 2024 Jacob Winther +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_FEATHER_NRF52840 + select SOC_NRF52840_QIAA diff --git a/boards/adafruit/feather_nrf52840/Kconfig.defconfig b/boards/adafruit/feather_nrf52840/Kconfig.defconfig new file mode 100644 index 00000000000..5e42fcfb8aa --- /dev/null +++ b/boards/adafruit/feather_nrf52840/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Adafruit Feather nRF52840 Express board configuration + +# Copyright (c) 2020 Tobias Svehagen +# Copyright (c) 2024 Jacob Winther +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ADAFRUIT_FEATHER_NRF52840 + +config BT_CTLR + default BT + +endif # BOARD_ADAFRUIT_FEATHER_NRF52840 diff --git a/boards/adafruit/feather/adafruit_feather_nrf52840-pinctrl.dtsi b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840-pinctrl.dtsi similarity index 100% rename from boards/adafruit/feather/adafruit_feather_nrf52840-pinctrl.dtsi rename to boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840-pinctrl.dtsi diff --git a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840.dts b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840.dts new file mode 100644 index 00000000000..9d8ef1b15e5 --- /dev/null +++ b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840.dts @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2020 Tobias Svehagen + * Copyright (c) 2024 Jacob Winther + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include "adafruit_feather_nrf52840_common.dtsi" +#include + +/ { + model = "Adafruit Feather nRF52840 Express"; + compatible = "adafruit,feather-nrf52840"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,uart-mcumgr = &uart0; + zephyr,bt-mon-uart = &uart0; + zephyr,bt-c2h-uart = &uart0; + }; + + leds { + led0: led_0 { + gpios = <&gpio1 15 0>; + }; + }; +}; diff --git a/boards/adafruit/feather/adafruit_feather_nrf52840.yaml b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840.yaml similarity index 82% rename from boards/adafruit/feather/adafruit_feather_nrf52840.yaml rename to boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840.yaml index 487c78377a1..761f378dcaa 100644 --- a/boards/adafruit/feather/adafruit_feather_nrf52840.yaml +++ b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840.yaml @@ -1,4 +1,4 @@ -identifier: adafruit_feather/nrf52840 +identifier: adafruit_feather_nrf52840/nrf52840 name: Adafruit Feather nRF52840 Express type: mcu arch: arm @@ -9,7 +9,6 @@ toolchain: supported: - adc - usb_device - - usb_cdc - ble - watchdog - counter diff --git a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_common.dtsi b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_common.dtsi new file mode 100644 index 00000000000..9c952a50f3b --- /dev/null +++ b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_common.dtsi @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2020 Tobias Svehagen + * Copyright (c) 2024 Jacob Winther + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "feather_connector.dtsi" +#include "adafruit_feather_nrf52840-pinctrl.dtsi" +#include + +/ { + + chosen { + zephyr,ieee802154 = &ieee802154; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + label = "Red LED"; + }; + led1: led_1 { + gpios = <&gpio1 10 0>; + label = "Blue LED"; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio1 2 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch"; + zephyr,code = ; + }; + }; + + vbatt { + compatible = "voltage-divider"; + io-channels = <&adc 5>; + output-ohms = <100000>; + full-ohms = <(100000 + 100000)>; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + led1 = &led1; + sw0 = &button0; + watchdog0 = &wdt0; + }; +}; + +®1 { + regulator-initial-mode = ; +}; + +&adc { + status = "okay"; +}; + +&uicr { + gpio-as-nreset; +}; + +&gpiote { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&uart0 { + compatible = "nordic,nrf-uart"; + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&i2c0 { + compatible = "nordic,nrf-twi"; + status = "okay"; + pinctrl-0 = <&i2c0_default>; + pinctrl-1 = <&i2c0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&spi1 { + compatible = "nordic,nrf-spi"; + status = "okay"; + pinctrl-0 = <&spi1_default>; + pinctrl-1 = <&spi1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&qspi { + status = "okay"; + pinctrl-0 = <&qspi_default>; + pinctrl-1 = <&qspi_sleep>; + pinctrl-names = "default", "sleep"; + gd25q16: gd25q16@0 { + compatible = "nordic,qspi-nor"; + reg = <0>; + writeoc = "pp4o"; + readoc = "read4io"; + sck-frequency = <16000000>; + jedec-id = [ c8 40 15 ]; + size = <16777216>; + has-dpd; + t-enter-dpd = <20000>; + t-exit-dpd = <20000>; + quad-enable-requirements = "S2B1v1"; + }; +}; + +&ieee802154 { + status = "okay"; +}; + +zephyr_udc0: &usbd { + compatible = "nordic,nrf-usbd"; + status = "okay"; +}; diff --git a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_defconfig b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_defconfig new file mode 100644 index 00000000000..2225f146d9b --- /dev/null +++ b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_flash_uf2.dtsi b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_flash_uf2.dtsi new file mode 100644 index 00000000000..805b853ce31 --- /dev/null +++ b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_flash_uf2.dtsi @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2024 Jacob Winther + * + * SPDX-License-Identifier: Apache-2.0 + * + * Default flash layout for nrf52840 using UF2 + */ + +/ { + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &code_partition; + }; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* To enable flashing with UF2 bootloader, we + * must reserve a partition for SoftDevice. + * See https://learn.adafruit.com/ + * introducing-the-adafruit-nrf52840-feather?view=all#hathach-memory-map + */ + reserved_partition_0: partition@0 { + label = "SoftDevice"; + read-only; + reg = <0x000000000 DT_SIZE_K(152)>; + }; + code_partition: partition@26000 { + label = "Application"; + reg = <0x00026000 DT_SIZE_K(796)>; + }; + + /* + * The flash starting at 0x000ed000 and ending at + * 0x000f4000 is reserved for use by the application. + */ + storage_partition: partition@ed000 { + label = "storage"; + reg = <0x0000ed000 DT_SIZE_K(28)>; + }; + + boot_partition: partition@f4000 { + label = "UF2"; + read-only; + reg = <0x000f4000 DT_SIZE_K(48)>; + }; + }; +}; diff --git a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense.dts b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense.dts new file mode 100644 index 00000000000..764ebbfefbb --- /dev/null +++ b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense.dts @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2024 Jacob Winther + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include "adafruit_feather_nrf52840_common.dtsi" +#include + +/ { + model = "Adafruit Feather nRF52840 Sense"; + compatible = "adafruit,feather-nrf52840-sense-uf2"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,uart-mcumgr = &uart0; + zephyr,bt-mon-uart = &uart0; + zephyr,bt-c2h-uart = &uart0; + }; + + leds { + led0: led_0 { + gpios = <&gpio1 9 0>; + }; + }; +}; + +&i2c0 { + SHT3XD: sht3xd@44 { + compatible = "sensirion,sht3xd"; + reg = <0x44>; + }; +}; diff --git a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense.yaml b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense.yaml new file mode 100644 index 00000000000..276870f44d3 --- /dev/null +++ b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense.yaml @@ -0,0 +1,19 @@ +identifier: adafruit_feather_nrf52840/nrf52840/sense +name: Adafruit Feather nRF52840 Sense +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - adc + - usb_device + - usb_cdc + - ble + - watchdog + - counter + - feather_serial + - feather_i2c + - feather_spi +vendor: adafruit diff --git a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense_defconfig b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense_defconfig new file mode 100644 index 00000000000..fb20a748810 --- /dev/null +++ b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense_defconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# 32kHz clock source +CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y +CONFIG_CLOCK_CONTROL_NRF_K32SRC_500PPM=y diff --git a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense_uf2.dts b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense_uf2.dts new file mode 100644 index 00000000000..0ad7ee1e960 --- /dev/null +++ b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense_uf2.dts @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2020 Tobias Svehagen + * Copyright (c) 2024 Jacob Winther + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include "adafruit_feather_nrf52840_common.dtsi" +#include "adafruit_feather_nrf52840_flash_uf2.dtsi" + +/ { + model = "Adafruit Feather nRF52840 Sense"; + compatible = "adafruit,feather-nrf52840-sense-uf2"; + + chosen { + zephyr,console = &cdc_acm_uart0; + zephyr,shell-uart = &cdc_acm_uart0; + zephyr,uart-mcumgr = &cdc_acm_uart0; + zephyr,bt-mon-uart = &cdc_acm_uart0; + zephyr,bt-c2h-uart = &cdc_acm_uart0; + }; + + leds { + led0: led_0 { + gpios = <&gpio1 9 0>; + }; + }; +}; + +&i2c0 { + SHT3XD: sht3xd@44 { + compatible = "sensirion,sht3xd"; + reg = <0x44>; + }; +}; + +zephyr_udc0: &usbd { + cdc_acm_uart0: cdc_acm_uart0 { + compatible = "zephyr,cdc-acm-uart"; + }; +}; diff --git a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense_uf2.yaml b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense_uf2.yaml new file mode 100644 index 00000000000..08eb1eaa7f1 --- /dev/null +++ b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense_uf2.yaml @@ -0,0 +1,19 @@ +identifier: adafruit_feather_nrf52840/nrf52840/sense/uf2 +name: Adafruit Feather nRF52840 Sense UF2 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - adc + - usb_device + - usb_cdc + - ble + - watchdog + - counter + - feather_serial + - feather_i2c + - feather_spi +vendor: adafruit diff --git a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense_uf2_defconfig b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense_uf2_defconfig new file mode 100644 index 00000000000..18c22c337d0 --- /dev/null +++ b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense_uf2_defconfig @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# 32kHz clock source +CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y +CONFIG_CLOCK_CONTROL_NRF_K32SRC_500PPM=y + +# Logger cannot use itself to log +CONFIG_USB_CDC_ACM_LOG_LEVEL_OFF=y + +# Enable USB +CONFIG_USB_DEVICE_STACK=y + +# Build UF2 by default, supported by the Adafruit nRF52 Bootloader +CONFIG_BUILD_OUTPUT_UF2=y diff --git a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_uf2.dts b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_uf2.dts new file mode 100644 index 00000000000..33f2d3e598c --- /dev/null +++ b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_uf2.dts @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2024 Jacob Winther + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include "adafruit_feather_nrf52840_common.dtsi" +#include "adafruit_feather_nrf52840_flash_uf2.dtsi" + +/ { + model = "Adafruit Feather nRF52840 Express"; + compatible = "adafruit,feather-nrf52840-uf2"; + + chosen { + zephyr,console = &cdc_acm_uart0; + zephyr,shell-uart = &cdc_acm_uart0; + zephyr,uart-mcumgr = &cdc_acm_uart0; + zephyr,bt-mon-uart = &cdc_acm_uart0; + zephyr,bt-c2h-uart = &cdc_acm_uart0; + }; + + leds { + led0: led_0 { + gpios = <&gpio1 15 0>; + }; + }; +}; + +zephyr_udc0: &usbd { + cdc_acm_uart0: cdc_acm_uart0 { + compatible = "zephyr,cdc-acm-uart"; + }; +}; diff --git a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_uf2.yaml b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_uf2.yaml new file mode 100644 index 00000000000..ebb7a399f0c --- /dev/null +++ b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_uf2.yaml @@ -0,0 +1,18 @@ +identifier: adafruit_feather_nrf52840/nrf52840/uf2 +name: Adafruit Feather nRF52840 Express UF2 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - adc + - usb_device + - ble + - watchdog + - counter + - feather_serial + - feather_i2c + - feather_spi +vendor: adafruit diff --git a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_uf2_defconfig b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_uf2_defconfig new file mode 100644 index 00000000000..f6ec2097646 --- /dev/null +++ b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_uf2_defconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Logger cannot use itself to log +CONFIG_USB_CDC_ACM_LOG_LEVEL_OFF=y + +# Enable USB +CONFIG_USB_DEVICE_STACK=y + +# Build UF2 by default, supported by the Adafruit nRF52 Bootloader +CONFIG_BUILD_OUTPUT_UF2=y diff --git a/boards/adafruit/feather_nrf52840/board.cmake b/boards/adafruit/feather_nrf52840/board.cmake new file mode 100644 index 00000000000..7ea8d064fbb --- /dev/null +++ b/boards/adafruit/feather_nrf52840/board.cmake @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000") +board_runner_args(pyocd "--target=nrf52840" "--frequency=4000000") +if(CONFIG_BUILD_OUTPUT_UF2) + include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake) +endif() +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/blackmagicprobe.board.cmake) diff --git a/boards/adafruit/feather_nrf52840/board.yml b/boards/adafruit/feather_nrf52840/board.yml new file mode 100644 index 00000000000..5841c2f4bf0 --- /dev/null +++ b/boards/adafruit/feather_nrf52840/board.yml @@ -0,0 +1,10 @@ +board: + name: adafruit_feather_nrf52840 + vendor: adafruit + socs: + - name: nrf52840 + variants: + - name: uf2 + - name: sense + variants: + - name: uf2 diff --git a/boards/adafruit/feather/doc/img/adafruit_feather_nrf52840.jpg b/boards/adafruit/feather_nrf52840/doc/img/adafruit_feather_nrf52840_express.jpg similarity index 100% rename from boards/adafruit/feather/doc/img/adafruit_feather_nrf52840.jpg rename to boards/adafruit/feather_nrf52840/doc/img/adafruit_feather_nrf52840_express.jpg diff --git a/boards/adafruit/feather_nrf52840/doc/img/adafruit_feather_nrf52840_sense.jpg b/boards/adafruit/feather_nrf52840/doc/img/adafruit_feather_nrf52840_sense.jpg new file mode 100644 index 00000000000..c2bd1da9cba Binary files /dev/null and b/boards/adafruit/feather_nrf52840/doc/img/adafruit_feather_nrf52840_sense.jpg differ diff --git a/boards/adafruit/feather_nrf52840/doc/index.rst b/boards/adafruit/feather_nrf52840/doc/index.rst new file mode 100644 index 00000000000..7ab630978d4 --- /dev/null +++ b/boards/adafruit/feather_nrf52840/doc/index.rst @@ -0,0 +1,254 @@ +.. _adafruit_feather_nrf52840: + +Adafruit Feather nRF52840 (Express, Sense) +########################################## + +Overview +******** + +The Adafruit Feather nRF52840 provides support for the Nordic Semiconductor +nRF52840 ARM Cortex-M4F CPU and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. tabs:: + + .. group-tab:: Express + + .. figure:: img/adafruit_feather_nrf52840_express.jpg + :align: center + :alt: Adafruit Feather nRF52840 Express + + .. group-tab:: Sense + + .. figure:: img/adafruit_feather_nrf52840_sense.jpg + :align: center + :alt: Adafruit Feather nRF52840 Sense + +Hardware +******** + +- nRF52840 ARM Cortex-M4F processor at 64 MHz +- 1 MB flash memory and 256 KB of SRAM +- Battery connector and charger for 3.7 V lithium polymer batteries +- Charging indicator LED +- 2 User LEDs +- 1 NeoPixel LED +- Reset button +- SWD connector (Express only) +- SWD solder pads on bottom of PCB (Sense only) +- LSM6DS33 Accel/Gyro (Sense only) +- LIS3MDL magnetometer (Sense only) +- APDS9960 Proximity, Light, Color, and Gesture Sensor (Sense only) +- MP34DT01-M PDM Microphone sound sensor (Sense only) +- SHT3X Humidity sensor (Sense only) +- BMP280 temperature and barometric pressure/altitude (Sense only) + +Supported Features +================== + +The Adafruit Feather nRF52840 board configuration supports the +following hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| SPI | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Connections and IOs +=================== + +.. tabs:: + + .. group-tab:: Express + + The `Adafruit Feather nRF52840 Express Learn site`_ has + detailed information about the board including + `pinouts (Express)`_ and the `schematic (Express)`_. + + .. group-tab:: Sense + + The `Adafruit Feather nRF52840 Sense Learn site`_ has + detailed information about the board including + `pinouts (Sense)`_ and the `schematic (Sense)`_. + +LED +--- + +* LED0 (red) = P1.15 (Express) +* LED0 (red) = P1.9 (Sense) +* LED1 (blue) = P1.10 + +Push buttons +------------ + +* SWITCH = P1.02 +* RESET = P0.18 + +Programming and Debugging +************************* + +Flashing +======== + +Flashing Zephyr onto both the Feather nRF52840 Express and Sense is possible +using the SWD headers. Only the Express board has an SWD connector however. + +Both the Feather nRF52840 Express and Sense ship with the `Adafruit nRF52 Bootloader`_ +which supports flashing using `UF2`_. This allows easy flashing of new images, +but does not support debugging the device. + +#. Build the Zephyr kernel and the :zephyr:code-sample:`blinky` sample application. + +.. tabs:: + + .. group-tab:: Express + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: adafruit_feather_nrf52840 + :goals: build + :compact: + + .. group-tab:: Express UF2 + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: adafruit_feather_nrf52840/nrf52840/uf2 + :goals: build + :compact: + + .. group-tab:: Sense + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: adafruit_feather_nrf52840/nrf52840/sense + :goals: build + :compact: + + .. group-tab:: Sense UF2 + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: adafruit_feather_nrf52840/nrf52840/sense/uf2 + :goals: build + :compact: + +#. If using UF2, connect the board to your host computer using USB. + +#. Tap the reset button twice quickly to enter bootloader mode. + A mass storage device named ``FTHR840BOOT`` for (Express) or + ``FTHRSNSBOOT`` (Sense) should appear on the host. Ensure this is + mounted. + +#. Flash the image. + +.. tabs:: + + .. group-tab:: Express + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: adafruit_feather_nrf52840 + :goals: flash + :compact: + + .. group-tab:: Express UF2 + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: adafruit_feather_nrf52840/nrf52840/uf2 + :goals: flash + :compact: + + + .. group-tab:: Sense + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: adafruit_feather_nrf52840/nrf52840/sense + :goals: flash + :compact: + + .. group-tab:: Sense UF2 + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: adafruit_feather_nrf52840/nrf52840/sense/uf2 + :goals: flash + :compact: + +#. You should see the red LED blink. + +References +********** + +.. target-notes:: + +.. _Adafruit Feather nRF52840 Express Learn site: + https://learn.adafruit.com/introducing-the-adafruit-nrf52840-feather/ + +.. _pinouts (Express): + https://learn.adafruit.com/introducing-the-adafruit-nrf52840-feather/pinouts + +.. _schematic (Express): + https://learn.adafruit.com/introducing-the-adafruit-nrf52840-feather/downloads + +.. _Adafruit Feather nRF52840 Sense Learn site: + https://learn.adafruit.com/adafruit-feather-sense + +.. _pinouts (Sense): + https://learn.adafruit.com/adafruit-feather-sense/pinouts + +.. _schematic (Sense): + https://learn.adafruit.com/adafruit-feather-sense/downloads + +.. _Adafruit nRF52 Bootloader: + https://github.com/adafruit/Adafruit_nRF52_Bootloader + +.. _UF2: + https://github.com/microsoft/uf2 diff --git a/boards/adafruit/feather/feather_connector.dtsi b/boards/adafruit/feather_nrf52840/feather_connector.dtsi similarity index 100% rename from boards/adafruit/feather/feather_connector.dtsi rename to boards/adafruit/feather_nrf52840/feather_connector.dtsi diff --git a/boards/adafruit/feather/pre_dt_board.cmake b/boards/adafruit/feather_nrf52840/pre_dt_board.cmake similarity index 100% rename from boards/adafruit/feather/pre_dt_board.cmake rename to boards/adafruit/feather_nrf52840/pre_dt_board.cmake diff --git a/boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405.dts b/boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405.dts index cc1cb702062..7995e359593 100644 --- a/boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405.dts +++ b/boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405.dts @@ -31,7 +31,6 @@ aliases { led0 = &led; - spi-flash0 = &gd25q16; }; }; diff --git a/boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405_defconfig b/boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405_defconfig index c729b83e3d0..51eadcb4809 100644 --- a/boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405_defconfig +++ b/boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405_defconfig @@ -14,9 +14,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/adafruit/grand_central_m4_express/doc/index.rst b/boards/adafruit/grand_central_m4_express/doc/index.rst index ec8ab08afdf..e9cf733843a 100644 --- a/boards/adafruit/grand_central_m4_express/doc/index.rst +++ b/boards/adafruit/grand_central_m4_express/doc/index.rst @@ -111,7 +111,7 @@ The bootloader can be entered by quickly tapping the reset button twice. Flashing ======== -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/adafruit/itsybitsy/Kconfig b/boards/adafruit/itsybitsy/Kconfig index e2c47273197..8aa3368ffd6 100644 --- a/boards/adafruit/itsybitsy/Kconfig +++ b/boards/adafruit/itsybitsy/Kconfig @@ -3,12 +3,6 @@ # Copyright (c) 2022 Embla Flatlandsmo # SPDX-License-Identifier: Apache-2.0 -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_ADAFRUIT_ITSYBITSY - config BOARD_SERIAL_BACKEND_CDC_ACM bool "USB CDC" default y diff --git a/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.dts b/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.dts index 45827a7bcec..087ddc17307 100644 --- a/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.dts +++ b/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.dts @@ -48,11 +48,14 @@ led0 = &led0; sw0 = &button0; watchdog0 = &wdt0; - spi-flash0 = &gd25q16; led-strip = &apa102; }; }; +®1 { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; diff --git a/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.yaml b/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.yaml index 3e571954bf1..9bf0ea72176 100644 --- a/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.yaml +++ b/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.yaml @@ -16,7 +16,6 @@ supported: - i2c - pwm - spi - - usb_cdc - usb_device - watchdog vendor: adafruit diff --git a/boards/adafruit/itsybitsy_m4_express/doc/index.rst b/boards/adafruit/itsybitsy_m4_express/doc/index.rst index a25df0bf2fa..ce3efb89b1f 100644 --- a/boards/adafruit/itsybitsy_m4_express/doc/index.rst +++ b/boards/adafruit/itsybitsy_m4_express/doc/index.rst @@ -122,7 +122,7 @@ will be entered automatically when you run :code:`west flash`. Flashing ======== -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/adafruit/itsybitsy_m4_express/support/openocd.cfg b/boards/adafruit/itsybitsy_m4_express/support/openocd.cfg index 096e396efc5..44234712259 100644 --- a/boards/adafruit/itsybitsy_m4_express/support/openocd.cfg +++ b/boards/adafruit/itsybitsy_m4_express/support/openocd.cfg @@ -7,7 +7,7 @@ source [find target/atsame5x.cfg] # TODO(http://openocd.zylin.com/#/c/5706/): lower the clock speed to workaround # an erase timeout. -adapter_khz 500 +adapter speed 500 reset_config srst_only $_TARGETNAME configure -event gdb-attach { diff --git a/boards/adafruit/kb2040/doc/index.rst b/boards/adafruit/kb2040/doc/index.rst index 09d5bfb0960..58b53aec815 100644 --- a/boards/adafruit/kb2040/doc/index.rst +++ b/boards/adafruit/kb2040/doc/index.rst @@ -117,7 +117,7 @@ Using UF2 Since it doesn't expose the SWD pins, you must flash the Adafruit KB2040 with a UF2 file. By default, building an app for this board will generate a -`build/zephyr/zephyr.uf2` file. If the KB2040 is powered on with the `BOOTSEL` +:file:`build/zephyr/zephyr.uf2` file. If the KB2040 is powered on with the ``BOOTSEL`` button pressed, it will appear on the host as a mass storage device. The UF2 file should be drag-and-dropped to the device, which will flash the KB2040. diff --git a/boards/adafruit/nrf52_adafruit_feather/Kconfig b/boards/adafruit/nrf52_adafruit_feather/Kconfig deleted file mode 100644 index a64bfcef152..00000000000 --- a/boards/adafruit/nrf52_adafruit_feather/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# nRF52 Adafruit Feather board configuration - -# Copyright (c) 2018 LEDCity AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_NRF52_ADAFRUIT_FEATHER diff --git a/boards/adafruit/nrf52_adafruit_feather/doc/index.rst b/boards/adafruit/nrf52_adafruit_feather/doc/index.rst index 0e7680e70b8..1fff89aaeab 100644 --- a/boards/adafruit/nrf52_adafruit_feather/doc/index.rst +++ b/boards/adafruit/nrf52_adafruit_feather/doc/index.rst @@ -118,10 +118,10 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/adafruit/nrf52_adafruit_feather/nrf52_adafruit_feather.dts b/boards/adafruit/nrf52_adafruit_feather/nrf52_adafruit_feather.dts index c29ca8000dc..f86b889fe3b 100644 --- a/boards/adafruit/nrf52_adafruit_feather/nrf52_adafruit_feather.dts +++ b/boards/adafruit/nrf52_adafruit_feather/nrf52_adafruit_feather.dts @@ -70,6 +70,10 @@ }; }; +® { + regulator-initial-mode = ; +}; + &uicr { gpio-as-nreset; }; diff --git a/boards/adafruit/qt_py_rp2040/doc/index.rst b/boards/adafruit/qt_py_rp2040/doc/index.rst index 19b5a832223..bf081c029b7 100644 --- a/boards/adafruit/qt_py_rp2040/doc/index.rst +++ b/boards/adafruit/qt_py_rp2040/doc/index.rst @@ -116,7 +116,7 @@ Using UF2 Since it doesn't expose the SWD pins, you must flash the Adafruit QT Py RP2040 with a UF2 file. By default, building an app for this board will generate a -`build/zephyr/zephyr.uf2` file. If the QT Py RP2040 is powered on with the `BOOTSEL` +:file:`build/zephyr/zephyr.uf2` file. If the QT Py RP2040 is powered on with the ``BOOTSEL`` button pressed, it will appear on the host as a mass storage device. The UF2 file should be drag-and-dropped to the device, which will flash the QT Py RP2040. diff --git a/boards/adafruit/trinket_m0/doc/index.rst b/boards/adafruit/trinket_m0/doc/index.rst index 4e23822b242..e02b829d7a0 100644 --- a/boards/adafruit/trinket_m0/doc/index.rst +++ b/boards/adafruit/trinket_m0/doc/index.rst @@ -114,7 +114,7 @@ will be entered automatically when you run :code:`west flash`. Flashing ======== -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/adi/apard32690/Kconfig.apard32690 b/boards/adi/apard32690/Kconfig.apard32690 new file mode 100644 index 00000000000..44ff6d5d858 --- /dev/null +++ b/boards/adi/apard32690/Kconfig.apard32690 @@ -0,0 +1,7 @@ +# MAX32690 board configuration + +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_APARD32690 + select SOC_MAX32690_M4 if BOARD_APARD32690_MAX32690_M4 diff --git a/boards/adi/apard32690/Kconfig.defconfig b/boards/adi/apard32690/Kconfig.defconfig new file mode 100644 index 00000000000..d6fb445a4ed --- /dev/null +++ b/boards/adi/apard32690/Kconfig.defconfig @@ -0,0 +1,20 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 +if BOARD_APARD32690 + +config MDIO_INIT_PRIORITY + default 81 + depends on MDIO + +config PHY_INIT_PRIORITY + default 82 + depends on NET_L2_ETHERNET && ETH_DRIVER + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_APARD32690 diff --git a/boards/adi/apard32690/apard32690_max32690_m4.dts b/boards/adi/apard32690/apard32690_max32690_m4.dts new file mode 100644 index 00000000000..793a717442b --- /dev/null +++ b/boards/adi/apard32690/apard32690_max32690_m4.dts @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include + +/ { + model = "Analog Devices AD-APARD32690-SL"; + compatible = "adi,apard32690"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + leds { + compatible = "gpio-leds"; + blue_led: blue_led { + gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + red_led: red_led { + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + label = "LED2"; + }; + green_led: green_led { + gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; + label = "LED3"; + }; + }; + + buttons { + compatible = "gpio-keys"; + usr_btn: usr_btn { + gpios = <&gpio1 27 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; + label = "S2"; + zephyr,code = ; + }; + }; + + aliases { + led0 = &blue_led; + led1 = &red_led; + led2 = &green_led; + sw0 = &usr_btn; + }; +}; + +&clk_ipo { + status = "okay"; +}; + +&clk_ibro { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&uart0 { + clock-source = ; + pinctrl-0 = <&uart0a_tx_p2_12 &uart0a_rx_p2_11>; + pinctrl-names = "default"; + current-speed = <115200>; + data-bits = <8>; + parity = "none"; + status = "okay"; +}; + +&trng { + status = "okay"; +}; + +arduino_serial: &uart1 { + clock-source = ; + pinctrl-0 = <&uart1a_tx_p2_16 &uart1a_rx_p2_14>; + pinctrl-names = "default"; + current-speed = <115200>; +}; + +arduino_spi: &spi1 { + pinctrl-0 = <&spi1a_miso_p1_28 &spi1a_mosi_p1_29 &spi1a_sck_p1_26 + &spi1a_ss0_p1_23>; + pinctrl-names = "default"; +}; + +&spi4a_miso_p1_2 { + power-source = ; +}; + +&spi4a_mosi_p1_1 { + power-source = ; +}; + +&spi4a_sck_p1_3 { + power-source = ; +}; + +&spi4a_ss0_p1_0 { + power-source = ; +}; + +pmod_spi: &spi4 { + pinctrl-0 = <&spi4a_miso_p1_2 &spi4a_mosi_p1_1 &spi4a_sck_p1_3 + &spi4a_ss0_p1_0>; + pinctrl-names = "default"; +}; + +&spi3a_miso_p0_20 { + power-source = ; +}; + +&spi3a_mosi_p0_21 { + power-source = ; +}; + +&spi3a_sck_p0_16 { + power-source = ; +}; + +&spi3a_ss0_p0_19 { + power-source = ; +}; + +&spi3 { + pinctrl-0 = <&spi3a_miso_p0_20 &spi3a_mosi_p0_21 &spi3a_sck_p0_16 + &spi3a_ss0_p0_19>; + pinctrl-names = "default"; + status = "okay"; + + adin1110: adin1110@0 { + compatible = "adi,adin1110"; + reg = <0x0>; + spi-max-frequency = ; + int-gpios = <&gpio0 17 (GPIO_ACTIVE_LOW | MAX32_GPIO_VSEL_VDDIOH)>; + reset-gpios = <&gpio0 15 (GPIO_ACTIVE_LOW | MAX32_GPIO_VSEL_VDDIOH)>; + status = "okay"; + + port1 { + local-mac-address = [ 00 E0 22 FE DA C9 ]; + }; + mdio { + compatible = "adi,adin2111-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@1 { + reg = <0x1>; + compatible = "adi,adin2111-phy"; + }; + }; + }; +}; diff --git a/boards/adi/apard32690/apard32690_max32690_m4.yaml b/boards/adi/apard32690/apard32690_max32690_m4.yaml new file mode 100644 index 00000000000..f3f842b66b2 --- /dev/null +++ b/boards/adi/apard32690/apard32690_max32690_m4.yaml @@ -0,0 +1,20 @@ +identifier: apard32690/max32690/m4 +name: apard32690 m4 +vendor: adi +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - arduino_serial + - arduino_spi + - pmod_spi + - gpio + - serial + - spi + - trng + - counter +ram: 1024 +flash: 3072 diff --git a/boards/adi/apard32690/apard32690_max32690_m4_defconfig b/boards/adi/apard32690/apard32690_max32690_m4_defconfig new file mode 100644 index 00000000000..a048ab2608f --- /dev/null +++ b/boards/adi/apard32690/apard32690_max32690_m4_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/adi/apard32690/board.cmake b/boards/adi/apard32690/board.cmake new file mode 100644 index 00000000000..409b85f0bc1 --- /dev/null +++ b/boards/adi/apard32690/board.cmake @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]") +board_runner_args(openocd --cmd-pre-init "source [find target/max32690.cfg]") +board_runner_args(jlink "--device=MAX32690" "--reset-after-load") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/adi/apard32690/board.yml b/boards/adi/apard32690/board.yml new file mode 100644 index 00000000000..269b5789345 --- /dev/null +++ b/boards/adi/apard32690/board.yml @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: apard32690 + vendor: adi + socs: + - name: max32690 diff --git a/boards/adi/apard32690/doc/img/apard32690_img.webp b/boards/adi/apard32690/doc/img/apard32690_img.webp new file mode 100644 index 00000000000..b5d53722309 Binary files /dev/null and b/boards/adi/apard32690/doc/img/apard32690_img.webp differ diff --git a/boards/adi/apard32690/doc/index.rst b/boards/adi/apard32690/doc/index.rst new file mode 100644 index 00000000000..192f0bba814 --- /dev/null +++ b/boards/adi/apard32690/doc/index.rst @@ -0,0 +1,220 @@ +.. _ad_apard32690_sl: + +AD-APARD32690-SL +################ + +Overview +******** +The AD-APARD32690-SL is a platform for prototyping intelligent, secure, and connected field devices. +It has an Arduino Mega-compatible form factor and two Pmod-compatible connectors. +The system includes the MAX32690 ARM Cortex-M4 with FPU-Based Microcontroller and Bluetooth LE 5.2. +The MCU is coupled with external RAM (2 x 512 Mb) and Flash (64 Mb) memories to meet the requirements +of the most demanding applications. The MAXQ1065 security coprocessor enables state of the art +security features such as for root-of-trust, mutual authentication, data confidentiality and +integrity, secure boot, and secure communications. +A 10 Mbps single-pair Ethernet link using the ADIN1110 10BASE-T1L MAC/PHY, enables remote +data acquisition and system configuration. The 10BASE-T1L interface also supports Single-pair +Power over Ethernet (SPoE) and be used for powering the system via an Arduino shield implementing +the required power circuitry. + +The Zephyr port is running on the MAX32690 MCU. + +.. image:: img/apard32690_img.webp + :align: center + :alt: AD-APARD32690-SL Front + +Hardware +******** + +- MAX32690 MCU: + + - Ultra-Efficient Microcontroller for Battery-Powered Applications + + - 120MHz Arm Cortex-M4 Processor with FPU + - 7.3728MHz and 60MHz Low-Power Oscillators + - External Crystal Support (32MHz required for BLE) + - 32.768kHz RTC Clock (Requires External Crystal) + - 8kHz Always-On Ultra-Low Power Oscillator + - 3MB Internal Flash, 1MB Internal SRAM (832kB ECC ON) + - TBDμW/MHz Executing from Cache at 1.1V + - 1.8V and 3.3V I/O with No Level Translators + - External Flash & SRAM Expansion Interfaces + + - Bluetooth 5.2 LE Radio + + - Dedicated, Ultra-Low-Power, 32-Bit RISC-V Coprocessor to Offload Timing-Critical Bluetooth Processing + - Fully Open-Source Bluetooth 5.2 Stack Available + - Supports AoA, AoD, LE Audio, and Mesh + - High-Throughput (2Mbps) Mode + - Long-Range (125kbps and 500kbps) Modes + - Rx Sensitivity: -97.5dBm; Tx Power: +4.5dBm + - Single-Ended Antenna Connection (50Ω) + + - Multiple Peripherals for System Control + + - 16-Channel DMA + - Up To Five Quad SPI Master (60MHz)/Slave (48MHz) + - Up To Four 1Mbaud UARTs with Flow Control + - Up To Two 1MHz I2C Master/Slave + - I2S Master/Slave + - Eight External Channel, 12-bit 1MSPS SAR ADC w/ on-die temperature sensor + - USB 2.0 Hi-Speed Device + - 16 Pulse Train Engines + - Up To Six 32-Bit Timers with 8mA High Drive + - Up To Two CAN 2.0 Controllers + - Up To Four Micro-Power Comparators + - 1-Wire Master + + - Security and Integrity + + - ChipDNA Physically Un-clonable Function (PUF) + - Modular Arithmetic Accelerator (MAA), True Random Number Generator (TRNG) + - Secure Nonvolatile Key Storage, SHA-256, AES-128/192/256 + - Secure Boot ROM + +- External devices connected to the APARD32690: + + - On-Board HyperRAM + - On-Board SPI Flash + - USB 2.0 Type-C interface to the MAX32690 + - SPI PMOD connector + - I2C PMOD connector + - SWD 10-Pin Header + - On-Board Bluetooth 5.2 LE Radio antenna + - MAXQ1065 Ultralow Power Cryptographic Controller with ChipDNA + - ADIN1110 Robust, Industrial, Low Power 10BASE-T1L Ethernet MAC-PHY + - U-Blox NINA-W102 802.11b/g/n module with dual-mode Bluetooth v4.2 + - On-Board 5V, 3.3V, 1.8V, and 1.1V voltage regulators + - 2-Pin external power supply terminal block (5V - 28V DC) + - Board Power Provided by either the USB Port or the 2-Pin connector + - Arduino Mega compatible header. + - Two general-purpose LEDs and one general purpose push button. + + +Supported Features +================== + +Below interfaces are supported by Zephyr on APARD32690. + ++-----------+------------+------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+------------------------------------+ +| CLOCK | on-chip | clock and reset control | ++-----------+------------+------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+------------------------------------+ +| ADIN1110 | spi | ADIN1110 10BASE-T1L mac/phy | ++-----------+------------+------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+------------------------------------+ +| Timer | on-chip | counter | ++-----------+------------+------------------------------------+ + + +Connections and IOs +=================== + ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| Name | Name | Settings | Description | ++===========+===============+===============+==================================================================================================+ +| P55 | SWD TX | | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects the SWD UART TX to the (UART) RX port of the U-Blox Nina W102. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects the SWD UART TX to the UART0 TX pin of the MAX32690. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| P50 | SWD RX | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects the SWD UART RX to the (UART) TX port of the U-Blox Nina W102. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects the SWD UART RX to the UART0 RX pin of the MAX32690. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| P51 | SWD POW | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects the SWD Vcc pin to 3.3V. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects the SWD Vcc pin to 1.8V. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| P38 | UART RX WIFI | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connect the U-Blox Nina W102 UART RX to the UART2A TX pin of the MAX32690 | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects the U-Blox Nina W102 UART RX from the UART2A TX pin | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| P58 | UART TX WIFI | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connect the U-Blox Nina W102 UART TX to the UART2A RX pin of the MAX32690. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects the U-Blox Nina W102 UART TX from the UART2A RX pin. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| S4 | SW1 | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | On | | | Pulls the ADIN1110's SWPD_EN pin to 3.3V through a resistor. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Off | | | Leaves the ADIN1110's SWPD_EN pin floating. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| S4 | SW2 | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | On | | | Pulls the ADIN1110's CFG0 pin to 3.3V through a resistor. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Off | | | Leaves the ADIN1110's CFG0 pin floating. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| S4 | SW3 | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | On | | | Pulls the ADIN1110's CFG1 pin to 3.3V through a resistor. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Off | | | Leaves the ADIN1110's CFG1 pin floating. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ + + +Programming and Debugging +************************* + +Flashing +======== + +The MAX32690 MCU can be flashed by connecting an external debug probe to the +SWD port. SWD debug can be accessed through the Cortex 10-pin connector, P9. +Logic levels are either 1.8V or 3.3V (based on P51 selection). + +Once the debug probe is connected to your host computer, then you can simply run the +``west flash`` command to write a firmware image into flash. + +.. note:: + + This board uses OpenOCD as the default debug interface. You can also use + a Segger J-Link with Segger's native tooling by overriding the runner, + appending ``--runner jlink`` to your ``west`` command(s). The J-Link should + be connected to the standard 2*5 pin debug connector (P9) using an + appropriate adapter board and cable. + +Debugging +========= + +Please refer to the `Flashing`_ section and run the ``west debug`` command +instead of ``west flash``. + +References +********** + +- `AD-APARD32690-SL web page`_ + +.. _AD-APARD32690-SL web page: + https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/ad-apard32690-sl.html diff --git a/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.dts b/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.dts index 171e57963bc..3b6934062e9 100644 --- a/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.dts +++ b/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.dts @@ -54,7 +54,6 @@ aliases { led0 = &green_led; watchdog0 = &iwdg; - spi-flash0 = &mx25r6435f; ambient-temp0 = &adt7420; }; diff --git a/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz_defconfig b/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz_defconfig index c19a47618d1..7da4b13427e 100644 --- a/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz_defconfig +++ b/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz_defconfig @@ -9,9 +9,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/adi/eval_adin1110ebz/doc/index.rst b/boards/adi/eval_adin1110ebz/doc/index.rst index 92b70f0c1c0..f39a04b7362 100644 --- a/boards/adi/eval_adin1110ebz/doc/index.rst +++ b/boards/adi/eval_adin1110ebz/doc/index.rst @@ -145,7 +145,7 @@ program to connect with your ADI board. For example: $ minicom -D /dev/serial/by-id/usb-ADI_EVAL-ADIN1110EBZ_AVAS_XXXXXX-if00-port0 where XXXXXX is the serial number of the connected device. -Then, build and flash in the usual way. Here is an example for the :ref:`hello_world` application. +Then, build and flash in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -161,7 +161,7 @@ You should see the following message on the console: Debugging ========= -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: diff --git a/boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz.dts b/boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz.dts index 83a3343ca35..3a990815857 100644 --- a/boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz.dts +++ b/boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz.dts @@ -48,7 +48,6 @@ aliases { led0 = &blue_led; watchdog0 = &iwdg; - spi-flash0 = &flash_ext; }; }; diff --git a/boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz_defconfig b/boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz_defconfig index c19a47618d1..7da4b13427e 100644 --- a/boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz_defconfig +++ b/boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz_defconfig @@ -9,9 +9,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/adi/eval_adin2111ebz/doc/index.rst b/boards/adi/eval_adin2111ebz/doc/index.rst index c88e6d520ed..ea0ce92be2a 100644 --- a/boards/adi/eval_adin2111ebz/doc/index.rst +++ b/boards/adi/eval_adin2111ebz/doc/index.rst @@ -146,7 +146,7 @@ program to connect with your ADI board. For example: $ minicom -D /dev/serial/by-id/usb-ADI_EVAL-ADIN2111EBZ_XXXXXX-12-if00-port0 where XXXXXX is the serial number of the connected device. -Then, build and flash in the usual way. Here is an example for the :ref:`hello_world` application. +Then, build and flash in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -162,7 +162,7 @@ You should see the following message on the console: Debugging ========= -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: diff --git a/boards/adi/max32655evkit/Kconfig.max32655evkit b/boards/adi/max32655evkit/Kconfig.max32655evkit new file mode 100644 index 00000000000..2eed6e48c60 --- /dev/null +++ b/boards/adi/max32655evkit/Kconfig.max32655evkit @@ -0,0 +1,7 @@ +# MAX32655EVKIT boards configuration + +# Copyright (c) 2023-2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MAX32655EVKIT + select SOC_MAX32655_M4 if BOARD_MAX32655EVKIT_MAX32655_M4 diff --git a/boards/adi/max32655evkit/board.cmake b/boards/adi/max32655evkit/board.cmake new file mode 100644 index 00000000000..965de9e4de2 --- /dev/null +++ b/boards/adi/max32655evkit/board.cmake @@ -0,0 +1,9 @@ +# Copyright (c) 2023-2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]") +board_runner_args(openocd --cmd-pre-init "source [find target/max32655.cfg]") +board_runner_args(jlink "--device=MAX32655" "--reset-after-load") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/adi/max32655evkit/board.yml b/boards/adi/max32655evkit/board.yml new file mode 100644 index 00000000000..4824c6fe8e5 --- /dev/null +++ b/boards/adi/max32655evkit/board.yml @@ -0,0 +1,8 @@ +# Copyright (c) 2023-2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: max32655evkit + vendor: adi + socs: + - name: max32655 diff --git a/boards/adi/max32655evkit/doc/img/max32655evkit_img1.jpg b/boards/adi/max32655evkit/doc/img/max32655evkit_img1.jpg new file mode 100644 index 00000000000..3b449c04349 Binary files /dev/null and b/boards/adi/max32655evkit/doc/img/max32655evkit_img1.jpg differ diff --git a/boards/adi/max32655evkit/doc/img/max32655evkit_img2.jpg b/boards/adi/max32655evkit/doc/img/max32655evkit_img2.jpg new file mode 100644 index 00000000000..12b6444e361 Binary files /dev/null and b/boards/adi/max32655evkit/doc/img/max32655evkit_img2.jpg differ diff --git a/boards/adi/max32655evkit/doc/index.rst b/boards/adi/max32655evkit/doc/index.rst new file mode 100644 index 00000000000..d052dba938a --- /dev/null +++ b/boards/adi/max32655evkit/doc/index.rst @@ -0,0 +1,191 @@ +.. _max32655_evkit: + +MAX32655EVKIT +############# + +Overview +******** +The MAX32655 evaluation kit (EV kit) provides a platform for evaluation capabilities +of the MAX32655 microcontroller, which is an advanced system-on-chip (SoC). +It features an Arm® Cortex®-M4F CPU for efficient computation of complex functions and +algorithms, integrated power management (SIMO), and the newest generation +Bluetooth® 5.0 Low Energy (Bluetooth LE), long-range radio for wearable and hearable device applications. + +The Zephyr port is running on the MAX32655 MCU. + +.. image:: img/max32655evkit_img1.jpg + :align: center + :alt: MAX32655 EVKIT Front + +.. image:: img/max32655evkit_img2.jpg + :align: center + :alt: MAX32655 Back + +Hardware +******** + +- MAX32655 MCU: + + - Ultra-Low-Power Wireless Microcontroller + - Internal 100MHz Oscillator + - Flexible Low-Power Modes with 7.3728MHz System Clock Option + - 512KB Flash and 128KB SRAM (Optional ECC on One 32KB SRAM Bank) + - 16KB Instruction Cache + - Bluetooth 5.2 LE Radio + - Dedicated, Ultra-Low-Power, 32-Bit RISC-V Coprocessor to Offload Timing-Critical Bluetooth Processing + - Fully Open-Source Bluetooth 5.2 Stack Available + - Supports AoA, AoD, LE Audio, and Mesh + - High-Throughput (2Mbps) Mode + - Long-Range (125kbps and 500kbps) Modes + - Rx Sensitivity: -97.5dBm; Tx Power: +4.5dBm + - Single-Ended Antenna Connection (50Ω) + - Power Management Maximizes Battery Life + - 2.0V to 3.6V Supply Voltage Range + - Integrated SIMO Power Regulator + - Dynamic Voltage Scaling (DVS) + - 23.8μA/MHz Active Current at 3.0V + - 4.4μA at 3.0V Retention Current for 32KB + - Selectable SRAM Retention + RTC in Low-Power Modes + - Multiple Peripherals for System Control + - Up to Two High-Speed SPI Master/Slave + - Up to Three High-Speed I2C Master/Slave (3.4Mbps) + - Up to Four UART, One I2S Master/Slave + - Up to 8-Input, 10-Bit Sigma-Delta ADC 7.8ksps + - Up to Four Micro-Power Comparators + - Timers: Up to Two Four 32-Bit, Two LP, TwoWatchdog Timers + - 1-Wire® Master + - Up to Four Pulse Train (PWM) Engines + - RTC with Wake-Up Timer + - Up to 52 GPIOs + - Security and Integrity​ + - Available Secure Boot + - TRNG Seed Generator + - AES 128/192/256 Hardware Acceleration Engine + +- External devices connected to the MAX32655 EVKIT: + + - Color TFT Display + - Audio Stereo Codec Interface + - Digital Microphone + - A 128Mb QSPI flash + +Supported Features +================== + +Below are the interfaces supported by Zephyr on MAX32655EVKIT. + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock and reset control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | dma controller | ++-----------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| Timer | on-chip | counter | ++-----------+------------+-------------------------------------+ + +Connections and IOs +=================== + ++-----------+---------------+-----------------------------------------------------------------------+ +| Name | Signal | Usage | ++===========+===============+=======================================================================+ +| JP1 | VREGI | Connect/Disconnect VREGIO power | ++-----------+---------------+-----------------------------------------------------------------------+ +| JP2 | P0_24 | Enable/Disable LED1 | ++-----------+---------------+-----------------------------------------------------------------------+ +| JP3 | P0_25 | Enable/Disable LED2 | ++-----------+---------------+-----------------------------------------------------------------------+ +| JP4 | P2_6/ P2_7 | Connect/Disconnect the USB to serial UART to GPIO P2_6 (LPUART_RX) | ++-----------+---------------+-----------------------------------------------------------------------+ +| JP5 | P2_7/ P0_1 | Connect/Disconnect the USB to serial UART to GPIO P2_7 (LPUART_TX) | ++-----------+---------------+-----------------------------------------------------------------------+ +| JP6 | P0_2 | Connect/Disconnect the USB to serial UART to GPIO P0_2 (UART0_CTS) | ++-----------+---------------+-----------------------------------------------------------------------+ +| JP7 | P0_3 | Connect/Disconnect he USB to serial UART to GPIO P0_3 (UART0_RTS) | ++-----------+---------------+-----------------------------------------------------------------------+ +| JP8 | VREGI | Select VDDIO_EN power source (3V3 or coin cell) | ++-----------+---------------+-----------------------------------------------------------------------+ +| JP9 | VDDIOH_EN | Select VDDIOH_EN power source 3V3/VREGI | ++-----------+---------------+-----------------------------------------------------------------------+ +| JP10 | VDDIOH | Connect/Disconnect VDDIOH power | ++-----------+---------------+-----------------------------------------------------------------------+ +| JP11 | VDDIO_EN | Select VDDIO_EN power source 1V8/VREGO_A | ++-----------+---------------+-----------------------------------------------------------------------+ +| JP12 | VDDIO | Connect/Disconnect VDDIO power | ++-----------+---------------+-----------------------------------------------------------------------+ +| JP13 | VDDA_EN | Select VDDA_EN power source 1V8/VREGO_A | ++-----------+---------------+-----------------------------------------------------------------------+ +| JP14 | VDDA | Connect/Disconnect VDDA power | ++-----------+---------------+-----------------------------------------------------------------------+ +| JP15 | VCOREA_EN | Select VCOREA_EN power source 1V1/VREGO_C | ++-----------+---------------+-----------------------------------------------------------------------+ +| JP16 | VCOREA | Connect/Disconnect VCOREA power | ++-----------+---------------+-----------------------------------------------------------------------+ +| JP17 | VCOREB_EN | Select VCOREB_EN power source 1V1/VREGO_B | ++-----------+---------------+-----------------------------------------------------------------------+ +| JP18 | VCOREB | Connect/Disconnect VCOREB power | ++-----------+---------------+-----------------------------------------------------------------------+ +| JP19 | BLE_LDO | Connect/Disconnect BLE_LDO power | ++-----------+---------------+-----------------------------------------------------------------------+ +| JP20 | VREF | Select VREF power source VDDIO/VDDIOH | ++-----------+---------------+-----------------------------------------------------------------------+ +| JP21 | I2C0_PU | Select I2C0_PU power source VDDIO/VDDIOH | ++-----------+---------------+-----------------------------------------------------------------------+ +| JP22 | I2C1_PU | Select I2C1_PU power source VDDIO/VDDIOH | ++-----------+---------------+-----------------------------------------------------------------------+ +| JP23 | BOARD RESET | Connect/Disconnect RV JTAG NRESET from the BOARD RESET circuitry | ++-----------+---------------+-----------------------------------------------------------------------+ + +Programming and Debugging +************************* + +Flashing +======== + +The MAX32655 MCU can be flashed by connecting an external debug probe to the +SWD port. SWD debug can be accessed through the Cortex 10-pin connector, JH3. +Logic levels are fixed to VDDIO (1.8V). + +Once the debug probe is connected to your host computer, then you can simply run the +``west flash`` command to write a firmware image into flash. + +.. note:: + + This board uses OpenOCD as the default debug interface. You can also use + a Segger J-Link with Segger's native tooling by overriding the runner, + appending ``--runner jlink`` to your ``west`` command(s). The J-Link should + be connected to the standard 2*5 pin debug connector (JW3) using an + appropriate adapter board and cable. + +Debugging +========= + +Please refer to the `Flashing`_ section and run the ``west debug`` command +instead of ``west flash``. + +References +********** + +- `MAX32655EVKIT web page`_ + +.. _MAX32655EVKIT web page: + https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/max32655evkit.html#eb-overview diff --git a/boards/adi/max32655evkit/max32655evkit_max32655_m4.dts b/boards/adi/max32655evkit/max32655evkit_max32655_m4.dts new file mode 100644 index 00000000000..eea6c9e6ab4 --- /dev/null +++ b/boards/adi/max32655evkit/max32655evkit_max32655_m4.dts @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2023-2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + + #include + #include + #include +#include +#include + +/ { + model = "Analog Devices MAX32655EVKIT"; + compatible = "adi,max32655evkit"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &sram2; + zephyr,flash = &flash0; + }; + + leds { + compatible = "gpio-leds"; + led1: led_1 { + gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; + label = "Red LED"; + }; + led2: led_2 { + gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + label = "Blue LED"; + }; + }; + + buttons { + compatible = "gpio-keys"; + pb1: pb1 { + gpios = <&gpio0 18 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW2"; + zephyr,code = ; + }; + pb2: pb2 { + gpios = <&gpio0 19 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW3"; + zephyr,code = ; + }; + pb_wakeup: pb_wakeup { + gpios = <&gpio3 1 (GPIO_PULL_UP | GPIO_ACTIVE_LOW + | MAX32_GPIO_VSEL_VDDIOH)>; + label = "Wakeup"; + zephyr,code = ; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led1; + led1 = &led2; + sw0 = &pb1; + sw1 = &pb2; + watchdog0 = &wdt0; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0a_tx_p0_1 &uart0a_rx_p0_0>; + pinctrl-names = "default"; + current-speed = <115200>; + data-bits = <8>; + parity = "none"; + status = "okay"; +}; + +&clk_ipo { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&trng { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-0 = <&i2c0_scl_p0_10 &i2c0_sda_p0_11>; + pinctrl-names = "default"; +}; + +&dma0 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + pinctrl-0 = <&spi0_mosi_p0_5 &spi0_miso_p0_6 &spi0_sck_p0_7 &spi0_ss0_p0_4>; + pinctrl-names = "default"; +}; diff --git a/boards/adi/max32655evkit/max32655evkit_max32655_m4.yaml b/boards/adi/max32655evkit/max32655evkit_max32655_m4.yaml new file mode 100644 index 00000000000..0a870489a22 --- /dev/null +++ b/boards/adi/max32655evkit/max32655evkit_max32655_m4.yaml @@ -0,0 +1,21 @@ +identifier: max32655evkit/max32655/m4 +name: max32655evkit m4 +vendor: adi +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - serial + - trng + - i2c + - dma + - watchdog + - spi + - adc + - counter +ram: 128 +flash: 512 diff --git a/boards/adi/max32655evkit/max32655evkit_max32655_m4_defconfig b/boards/adi/max32655evkit/max32655evkit_max32655_m4_defconfig new file mode 100644 index 00000000000..4fa0a464106 --- /dev/null +++ b/boards/adi/max32655evkit/max32655evkit_max32655_m4_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2023-2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/adi/max32655fthr/Kconfig.max32655fthr b/boards/adi/max32655fthr/Kconfig.max32655fthr new file mode 100644 index 00000000000..589209a2fb3 --- /dev/null +++ b/boards/adi/max32655fthr/Kconfig.max32655fthr @@ -0,0 +1,7 @@ +# MAX32655FTHR boards configuration + +# Copyright (c) 2023-2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MAX32655FTHR + select SOC_MAX32655_M4 if BOARD_MAX32655FTHR_MAX32655_M4 diff --git a/boards/adi/max32655fthr/board.cmake b/boards/adi/max32655fthr/board.cmake new file mode 100644 index 00000000000..d2353452cbe --- /dev/null +++ b/boards/adi/max32655fthr/board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2023-2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]") +board_runner_args(openocd --cmd-pre-init "source [find target/max32655.cfg]") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/adi/max32655fthr/board.yml b/boards/adi/max32655fthr/board.yml new file mode 100644 index 00000000000..087b51d8d95 --- /dev/null +++ b/boards/adi/max32655fthr/board.yml @@ -0,0 +1,8 @@ +# Copyright (c) 2023-2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: max32655fthr + vendor: adi + socs: + - name: max32655 diff --git a/boards/adi/max32655fthr/doc/img/max32655fthr_img1.jpg b/boards/adi/max32655fthr/doc/img/max32655fthr_img1.jpg new file mode 100644 index 00000000000..075a68e15fb Binary files /dev/null and b/boards/adi/max32655fthr/doc/img/max32655fthr_img1.jpg differ diff --git a/boards/adi/max32655fthr/doc/img/max32655fthr_img2.jpg b/boards/adi/max32655fthr/doc/img/max32655fthr_img2.jpg new file mode 100644 index 00000000000..9976dfd48c4 Binary files /dev/null and b/boards/adi/max32655fthr/doc/img/max32655fthr_img2.jpg differ diff --git a/boards/adi/max32655fthr/doc/img/max32655fthr_img3.jpg b/boards/adi/max32655fthr/doc/img/max32655fthr_img3.jpg new file mode 100644 index 00000000000..f523ef2aed2 Binary files /dev/null and b/boards/adi/max32655fthr/doc/img/max32655fthr_img3.jpg differ diff --git a/boards/adi/max32655fthr/doc/index.rst b/boards/adi/max32655fthr/doc/index.rst new file mode 100644 index 00000000000..3c9efcfb675 --- /dev/null +++ b/boards/adi/max32655fthr/doc/index.rst @@ -0,0 +1,207 @@ +.. _max32655_fthr: + +MAX32655FTHR +############ + +Overview +******** +The MAX32655FTHR is a rapid development platform to help engineers quickly implement +ultra low-power wireless solutions using MAX32655 Arm© Cortex®-M4F and Bluetooth® 5.2 Low Energy (LE). +The board also includes the MAX20303 PMIC for battery and power management. +The form factor is a small 0.9in x 2.6in dual-row header footprint that is compatible +with Adafruit Feather Wing peripheral expansion boards. The board includes a variety of peripherals, +such as a digital microphone, lowpower stereo audio CODEC, 128MB QSPI Flash, micro SD card connector, +RGB indicator LED, and pushbutton. +The MAX32655FTHR provides a power-optimized flexible platform for quick proof-of-concepts and +early software development to enhance time to market. Go to +https://www.analog.com/MAX32655FTHR to get started developing with this board. + + +The Zephyr port is running on the MAX32655 MCU. + +.. image:: img/max32655fthr_img1.jpg + :align: center + :alt: MAX32655FTHR Front + +.. image:: img/max32655fthr_img2.jpg + :align: center + :alt: MAX32655FTHR Front Modules + +.. image:: img/max32655fthr_img3.jpg + :align: center + :alt: MAX32655FTHR Back + +Hardware +******** + +- MAX32655 MCU: + + - Ultra-Low-Power Wireless Microcontroller + - Internal 100MHz Oscillator + - Flexible Low-Power Modes with 7.3728MHz System Clock Option + - 512KB Flash and 128KB SRAM (Optional ECC on One 32KB SRAM Bank) + - 16KB Instruction Cache + - Bluetooth 5.2 LE Radio + - Dedicated, Ultra-Low-Power, 32-Bit RISC-V Coprocessor to Offload Timing-Critical Bluetooth Processing + - Fully Open-Source Bluetooth 5.2 Stack Available + - Supports AoA, AoD, LE Audio, and Mesh + - High-Throughput (2Mbps) Mode + - Long-Range (125kbps and 500kbps) Modes + - Rx Sensitivity: -97.5dBm; Tx Power: +4.5dBm + - Single-Ended Antenna Connection (50Ω) + - Power Management Maximizes Battery Life + - 2.0V to 3.6V Supply Voltage Range + - Integrated SIMO Power Regulator + - Dynamic Voltage Scaling (DVS) + - 23.8μA/MHz Active Current at 3.0V + - 4.4μA at 3.0V Retention Current for 32KB + - Selectable SRAM Retention + RTC in Low-Power Modes + - Multiple Peripherals for System Control + - Up to Two High-Speed SPI Master/Slave + - Up to Three High-Speed I2C Master/Slave (3.4Mbps) + - Up to Four UART, One I2S Master/Slave + - Up to 8-Input, 10-Bit Sigma-Delta ADC 7.8ksps + - Up to Four Micro-Power Comparators + - Timers: Up to Two Four 32-Bit, Two LP, TwoWatchdog Timers + - 1-Wire® Master + - Up to Four Pulse Train (PWM) Engines + - RTC with Wake-Up Timer + - Up to 52 GPIOs + - Security and Integrity​ + - Available Secure Boot + - TRNG Seed Generator + - AES 128/192/256 Hardware Acceleration Engine + +- External devices connected to the MAX32655FTHR: + + - Audio Stereo Codec Interface + - Digital Microphone + - PMIC and Battery Charger + - A 128Mb QSPI flash + - Micro SDCard Interface + - RGB LEDs + - Push Buttons + +Supported Features +================== + +Below are the interfaces supported by Zephyr on MAX32655FTHR. + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock and reset control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | dma controller | ++-----------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| Timer | on-chip | counter | ++-----------+------------+-------------------------------------+ + +Push Buttons +************ +There are six pushbuttons on the MAX32655FTHR board + +SW1 +=== +PMIC Power Button, when the board is powered on state, pressing +this button for 12 seconds performs a hard powerdown. +When the board is in a powered-off state, pressing this button powers on the board. +This button can also be read by MAX32655 firmware, PMIC_PFN2 signal connected to Port 0.13 +is a buffered input of the button status. When the button is pressed, this signal goes to a logic-low +state. + +SW2 +=== +User-programmable function button connected to +MAX32655 Port 0.2 through a debouncer IC. + +SW3 +=== +User-programmable function button connected to +MAX32655 Port 0.3 through a debouncer IC. + +SW4 +=== +Wake-up button connected to MAX32655 Port 3.1. + +SW5 +=== +Resets the MAX32655 through RSTN input of the MAX32655. + +SW6 +=== +DAPLink adapter button. Keep this button +pressed while applying power to the board to +put the MAX32625 DAPLink adapter on board +to MAINTENANCE mode for DAPLink firmware +updates. + + +LEDs +**** +There are three RGB LEDs on the MAX32655FTHR board + +LED1 (D1) +========= +Connected to the MAX32655FTHR GPIO ports. +This LED can be controlled by user firmware. +Port 0.18: Red color +Port 0.19: Green color +Port 0.26: Blue color + +LED2 (D2) +========= +Connected to MAX20303 PMIC LEDx outputs. +These LEDs can be controlled through I2C commands. +They also can be configured as charge +status indicators by issuing I2C commands. + +LED3 (D3) +========= +DAPLink adapter MAX32625 status LED. +Controlled by the DAPLink adapter and cannot be +used as a user LED. + +Programming and Debugging +************************* + +Flashing +======== + +The MAX32625 microcontroller on the board is flashed with DAPLink firmware at the factory. +It allows debugging and flashing the MAX32655 Arm Core over USB. + +Once the USB cable is connected to your host computer, then you can simply run the +``west flash`` command to write a firmware image into flash. + +Debugging +========= + +Please refer to the `Flashing`_ section and run the ``west debug`` command +instead of ``west flash``. + +References +********** + +- `MAX32655FTHR web page`_ + +.. _MAX32655FTHR web page: + https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/max32655fthr.html diff --git a/boards/adi/max32655fthr/max32655fthr_max32655_m4.dts b/boards/adi/max32655fthr/max32655fthr_max32655_m4.dts new file mode 100644 index 00000000000..f5df5e5260a --- /dev/null +++ b/boards/adi/max32655fthr/max32655fthr_max32655_m4.dts @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2023-2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include + +/ { + model = "Analog Devices MAX32655FTHR"; + compatible = "adi,max32655fthr"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &sram2; + zephyr,flash = &flash0; + }; + + leds { + compatible = "gpio-leds"; + led1: led_1 { + gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; + label = "Red LED"; + }; + led2: led_2 { + gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; + label = "Blue LED"; + }; + led3: led_3 { + gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; + label = "Green LED"; + }; + }; + + buttons { + compatible = "gpio-keys"; + pb1: pb1 { + gpios = <&gpio0 2 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW2"; + zephyr,code = ; + }; + pb2: pb2 { + gpios = <&gpio0 3 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW3"; + zephyr,code = ; + }; + pb_wakeup: pb_wakeup { + gpios = <&gpio3 1 (GPIO_PULL_UP | GPIO_ACTIVE_LOW + | MAX32_GPIO_VSEL_VDDIOH)>; + label = "Wakeup"; + zephyr,code = ; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led1; + led1 = &led2; + led2 = &led3; + sw0 = &pb1; + sw1 = &pb2; + watchdog0 = &wdt0; + }; + + /* Used for accessing other pins */ + feather_header: feather_connector { + compatible = "adafruit-feather-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <12 0 &gpio0 31 0>, /* SDA */ + <13 0 &gpio0 30 0>, /* SCL */ + <14 0 &gpio1 9 0>, /* GPIO */ + <15 0 &gpio1 8 0>, /* GPIO */ + <16 0 &gpio0 20 0>, /* GPIO */ + <17 0 &gpio0 24 0>, /* GPIO */ + <18 0 &gpio0 25 0>, /* GPIO */ + <19 0 &gpio1 7 0>, /* GPIO */ + <20 0 &gpio1 6 0>, /* GPIO */ + /* 11 not connected */ + <10 0 &gpio2 7 0>, /* TX */ + <9 0 &gpio2 6 0>, /* RX */ + <8 0 &gpio0 22 0>, /* MISO */ + <7 0 &gpio0 21 0>, /* MOSI */ + <6 0 &gpio0 23 0>, /* SCK */ + <5 0 &gpio2 5 0>, /* AIN5 */ + <4 0 &gpio2 4 0>, /* AIN4 */ + <3 0 &gpio2 3 0>, /* AIN3 */ + <2 0 &gpio2 2 0>, /* AIN2 */ + <1 0 &gpio2 1 0>, /* AIN1 */ + <0 0 &gpio2 0 0>; /* AIN0 */ + }; +}; + +&uart0 { + pinctrl-0 = <&uart0a_tx_p0_1 &uart0a_rx_p0_0>; + pinctrl-names = "default"; + current-speed = <115200>; + data-bits = <8>; + parity = "none"; + status = "okay"; +}; + +&clk_ipo { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&trng { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + pinctrl-0 = <&i2c2_scl_p0_30 &i2c2_sda_p0_31>; + pinctrl-names = "default"; +}; + +&dma0 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; + pinctrl-0 = <&spi1_mosi_p0_21 &spi1_miso_p0_22 &spi1_sck_p0_23 &spi1_ss0_p0_20>; + pinctrl-names = "default"; +}; diff --git a/boards/adi/max32655fthr/max32655fthr_max32655_m4.yaml b/boards/adi/max32655fthr/max32655fthr_max32655_m4.yaml new file mode 100644 index 00000000000..e361e18e24f --- /dev/null +++ b/boards/adi/max32655fthr/max32655fthr_max32655_m4.yaml @@ -0,0 +1,21 @@ +identifier: max32655fthr/max32655/m4 +name: max32655fthr m4 +vendor: adi +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - serial + - trng + - i2c + - dma + - watchdog + - spi + - adc + - counter +ram: 128 +flash: 512 diff --git a/boards/adi/max32655fthr/max32655fthr_max32655_m4_defconfig b/boards/adi/max32655fthr/max32655fthr_max32655_m4_defconfig new file mode 100644 index 00000000000..4fa0a464106 --- /dev/null +++ b/boards/adi/max32655fthr/max32655fthr_max32655_m4_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2023-2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/adi/max32662evkit/Kconfig.max32662evkit b/boards/adi/max32662evkit/Kconfig.max32662evkit new file mode 100644 index 00000000000..341e421cd9c --- /dev/null +++ b/boards/adi/max32662evkit/Kconfig.max32662evkit @@ -0,0 +1,7 @@ +# MAX32662EVKIT boards configuration + +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MAX32662EVKIT + select SOC_MAX32662 diff --git a/boards/adi/max32662evkit/board.cmake b/boards/adi/max32662evkit/board.cmake new file mode 100644 index 00000000000..48ee0fa505f --- /dev/null +++ b/boards/adi/max32662evkit/board.cmake @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]") +board_runner_args(openocd --cmd-pre-init "source [find target/max32662.cfg]") +board_runner_args(jlink "--device=MAX32662" "--reset-after-load") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/adi/max32662evkit/board.yml b/boards/adi/max32662evkit/board.yml new file mode 100644 index 00000000000..628de9d7668 --- /dev/null +++ b/boards/adi/max32662evkit/board.yml @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: max32662evkit + vendor: adi + socs: + - name: max32662 diff --git a/boards/adi/max32662evkit/doc/img/max32662evkit.webp b/boards/adi/max32662evkit/doc/img/max32662evkit.webp new file mode 100644 index 00000000000..6757d84654f Binary files /dev/null and b/boards/adi/max32662evkit/doc/img/max32662evkit.webp differ diff --git a/boards/adi/max32662evkit/doc/index.rst b/boards/adi/max32662evkit/doc/index.rst new file mode 100644 index 00000000000..64718015706 --- /dev/null +++ b/boards/adi/max32662evkit/doc/index.rst @@ -0,0 +1,240 @@ +.. _max32662_evkit: + +MAX32662EVKIT +############# + +Overview +******** +The MAX32662 evaluation kit (EV kit) provides a platform for evaluating +the capabilities of the MAX32662 microcontroller, which is a cost-effective, +ultra-low power, highly integrated 32-bit microcontroller designed +for battery-powered edge devices. + +The Zephyr port is running on the MAX32662 MCU. + +.. image:: img/max32662evkit.webp + :align: center + :alt: MAX32662EVKIT + +Hardware +******** + +- MAX32662 MCU: + + - High-Efficiency Microcontroller for Low-Power High-Reliability Devices + + - 256KB Flash + - 80KB SRAM, Optionally Preserved in LowestPower BACKUP Mode + - 16KB Unified Cache + - Memory Protection Unit (MPU) + - Dual- or Single-Supply Operation: 1.7V to 3.6V + - Wide Operating Temperature: -40°C to +105°C + + - Flexible Clocking Schemes + + - Internal High-Speed 100MHz + - Internal Low-Power 7.3728MHz + - Ultra-Low-Power 80kHz + - 16MHz–32MHz (External Crystal Required) + - 32.768kHz (External Crystal Required) + - External Clock Inputs for CPU and Low-PowerTimer + + - Power Management Maximizes Uptime for Battery Applications + + - 50μA/MHz at 0.9V up to 12MHz (CoreMark®) inACTIVE Mode + - 44μA/MHz at 1.1V up to 100MHz (While(1)) inACTIVE Mode + - 2.15μA Full Memory Retention Current in BACKUPMode at VDDIO = 1.8V + - 2.4μA Full Memory Retention Current in BACKUPMode at VDDIO = 3.3V + - 350nA Ultra-Low-Power RTC + - Wakeup from Low-Power Timer + + - Optimal Peripheral Mix Provides Platform Scalability + + - Up to 21 General-Purpose I/O Pins + - 4-Channel, 12-Bit, 1Msps ADC + - Two SPI Controller/Target + - One I2S Controller/Target + - Two 4-Wire UART + - Two I2C Controller/Target + - One CAN 2.0B Controller + - 4-Channel Standard DMA Controller + - Three 32-Bit Timers + - One 32-Bit Low-Power Timer + - One Watchdog Timer + - CMOS-Level 32.768kHz Calibration Output + - AES-128/192/256 Hardware Accelerator + +- Benefits and Features of MAX32662EVKIT: + + - 3-Pin Terminal Block for CAN Bus 2.0B + - 128 x 128 (1.45in) Color TFT Display with SPI Interface + - Selectable On-Board High-Precision Voltage Reference + - USB 2.0 Micro-B to Serial UART + - All GPIOs Signals Accessed through 0.1in Headers + - Four Analog Inputs Accessed through 0.1in Header + - SWD 10-Pin Header + - Board Power Provided by USB Port + - On-Board LDO Regulators + - Individual Power Measurement on All IC Rails through Jumpers + - One General-Purpose LED + - One General-Purpose Pushbutton Switch + +Supported Features +================== + +Below interfaces are supported by Zephyr on MAX32662EVKIT. + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock and reset control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | dma controller | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| Timer | on-chip | counter | ++-----------+------------+-------------------------------------+ + +Connections and IOs +=================== + ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| Name | Name | Settings | Description | ++===========+===============+===============+==================================================================================================+ +| JP1 | VREF EN | | | +| | | +-----------+ | +-------------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects the external voltage reference to the VREF pin; must be enabled in the software. | | +| | | | | | | See the External Voltage Reference (VREF) section for additional information. | | +| | | +-----------+ | +-------------------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects the external voltage reference. | | +| | | +-----------+ | +-------------------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP2 | I2C1_SCL_PU | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects the pull-up to I2C1A_SCL (P0.6); sourced by V_AUX. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects the pull-up from I2C1A_SCL (P0.6); sourced by V_AUX. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP3 | N/A | N/A | Does not exist. | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP4 | I2C1_SDA_PU | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects the pull-up to I2C1A_SDA (P0.9); sourced by V_AUX. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Oepn | | | Disconnects the pull-up from I2C1A_SDA (P0.9); sourced by V_AUX. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP5 | LED0 EN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Enables LED0. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disables LED0. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP6 | CTS0A EN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects the USB-to-serial bridge to UART0A_CTS (P0.20). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects the USB-to-serial bridge from UART0A_CTS (P0.20). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP7 | RX0A EN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects the USB-to-serial bridge to UART0A_RX (P0.11). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects the USB-to-serial bridge from UART0A_RX (P0.11). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP8 | TX0A EN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects the USB-to-serial bridge to UART0A_TX (P0.10). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects the USB-to-serial bridge from UART0A_TX (P0.10). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP9 | RTS0A EN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects the USB-to-serial bridge to UART0A_RTS (P0.19). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects the USB-to-serial bridge from UART0A_RTS (P0.19). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP10 | VCORE EN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects 1V1 to VCORE. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects 1V1 from VCORE. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP11 | VDDIO/VDDASEL | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-1 | | | Connects 1V8 to V_AUX, VDDIO EN (JP12), and VDDA EN (JP13) jumpers. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects 3V3 to V_AUX, VDDIO EN (JP12), and VDDA EN (JP13) jumpers. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP12 | VDDIO EN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects the JP11 selected voltage to VDDIO. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects the voltage from VDDIO. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ + + +Programming and Debugging +************************* + +Flashing +======== + +An Arm® debug access port (DAP) provides an external interface for debugging during application +development. The DAP is a standard Arm CoreSight® serial wire debug port, uses a two-pin serial +interface (SWDCLK and SWDIO), and is accessed through 10-pin header (J3). Logic levels are set +to V_AUX (1V8 or 3V3), which is determined by the shunt placement on JP11. In addition, +the UART1A port can also be accessed through J3. + + +Once the debug probe is connected to your host computer, then you can simply run the +``west flash`` command to write a firmware image into flash. + +.. note:: + + This board uses OpenOCD as the default debug interface. You can also use + a Segger J-Link with Segger's native tooling by overriding the runner, + appending ``--runner jlink`` to your ``west`` command(s). The J-Link should + be connected to the standard 2*5 pin debug connector (J3) using an + appropriate adapter board and cable. + +Debugging +========= + +Please refer to the `Flashing`_ section and run the ``west debug`` command +instead of ``west flash``. + +References +********** + +- `MAX32662EVKIT web page`_ + +.. _MAX32662EVKIT web page: + https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/max32662evkit.html diff --git a/boards/adi/max32662evkit/max32662evkit.dts b/boards/adi/max32662evkit/max32662evkit.dts new file mode 100644 index 00000000000..e458a8d6904 --- /dev/null +++ b/boards/adi/max32662evkit/max32662evkit.dts @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include + +/ { + model = "Analog Devices MAX32662EVKIT"; + compatible = "adi,max32662evkit"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &sram2; + zephyr,flash = &flash0; + }; + + leds { + compatible = "gpio-leds"; + led1: led_1 { + gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + label = "Red LED"; + }; + }; + + buttons { + compatible = "gpio-keys"; + pb1: pb1 { + gpios = <&gpio0 6 (GPIO_PULL_UP | GPIO_ACTIVE_LOW + | MAX32_GPIO_VSEL_VDDIOH)>; + label = "SW3"; + zephyr,code = ; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led1; + sw0 = &pb1; + watchdog0 = &wdt0; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0a_tx_p0_10 &uart0a_rx_p0_11>; + pinctrl-names = "default"; + current-speed = <115200>; + data-bits = <8>; + parity = "none"; + status = "okay"; +}; + +&clk_ipo { + status = "okay"; +}; + +&dma0 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + pinctrl-0 = <&i2c1a_scl_p0_6 &i2c1a_sda_p0_9>; + pinctrl-names = "default"; +}; + +&trng { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + pinctrl-0 = <&spi0a_copi_p0_3 &spi0a_cito_p0_2 &spi0a_sck_p0_4 &spi0a_ts0_p0_5>; + pinctrl-names = "default"; +}; diff --git a/boards/adi/max32662evkit/max32662evkit.yaml b/boards/adi/max32662evkit/max32662evkit.yaml new file mode 100644 index 00000000000..f4577c7bcab --- /dev/null +++ b/boards/adi/max32662evkit/max32662evkit.yaml @@ -0,0 +1,21 @@ +identifier: max32662evkit +name: max32662evkit +vendor: adi +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - dma + - gpio + - i2c + - serial + - trng + - watchdog + - spi + - adc + - counter +ram: 80 +flash: 256 diff --git a/boards/adi/max32662evkit/max32662evkit_defconfig b/boards/adi/max32662evkit/max32662evkit_defconfig new file mode 100644 index 00000000000..a048ab2608f --- /dev/null +++ b/boards/adi/max32662evkit/max32662evkit_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/adi/max32666evkit/Kconfig.max32666evkit b/boards/adi/max32666evkit/Kconfig.max32666evkit new file mode 100644 index 00000000000..a648082e506 --- /dev/null +++ b/boards/adi/max32666evkit/Kconfig.max32666evkit @@ -0,0 +1,7 @@ +# MAX32666EVKIT boards configuration + +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MAX32666EVKIT + select SOC_MAX32666_CPU0 if BOARD_MAX32666EVKIT_MAX32666_CPU0 diff --git a/boards/adi/max32666evkit/board.cmake b/boards/adi/max32666evkit/board.cmake new file mode 100644 index 00000000000..80033d85bdc --- /dev/null +++ b/boards/adi/max32666evkit/board.cmake @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]") +board_runner_args(openocd --cmd-pre-init "source [find target/max32665.cfg]") +board_runner_args(jlink "--device=MAX32666" "--reset-after-load") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/adi/max32666evkit/board.yml b/boards/adi/max32666evkit/board.yml new file mode 100644 index 00000000000..5d1beff7716 --- /dev/null +++ b/boards/adi/max32666evkit/board.yml @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: max32666evkit + vendor: adi + socs: + - name: max32666 diff --git a/boards/adi/max32666evkit/doc/img/max32666evkit.webp b/boards/adi/max32666evkit/doc/img/max32666evkit.webp new file mode 100644 index 00000000000..6eed641e252 Binary files /dev/null and b/boards/adi/max32666evkit/doc/img/max32666evkit.webp differ diff --git a/boards/adi/max32666evkit/doc/index.rst b/boards/adi/max32666evkit/doc/index.rst new file mode 100644 index 00000000000..528a8026ca1 --- /dev/null +++ b/boards/adi/max32666evkit/doc/index.rst @@ -0,0 +1,323 @@ +.. _max32666evkit: + +MAX32666EVKIT +############# + +Overview +******** +The MAX32666EVKIT provides a platform for evaluating the capabilities of the MAX32665 and MAX32666 +high-efficiency Arm® microcontrollers and audio DSP for wearable and hearable device applications. + + +The Zephyr port is running on the MAX32666 MCU. + +.. image:: img/max32666evkit.webp + :align: center + :alt: MAX32666EVKIT Front + + +Hardware +******** + +- MAX32666 MCU: + + - High-Efficiency Microcontroller and Audio DSP for Wearable and Hearable Devices + + - Arm Cortex-M4 with FPU Up to 96MHz + - Optional Second Arm Cortex-M4 with FPU Optimized for Data Processing + - Low-Power 7.3728MHz System Clock Option + - 1MB Flash, Organized into Dual Banks 2 x 512KB + - 560KB (448KB ECC) SRAM; 3 x 16KB Cache + - Optional Error Correction Code (ECC-SEC-DED)for Cache, SRAM, and Internal Flash + + - Bluetooth 5 Low Energy Radio + + - 1Mbps and 2Mbps Data Throughput + - Long Range (125kbps and 500kbps) + - Advertising Extension + - Rx Sensitivity: -95dbm; Tx Power Up to +4.5dbm + - On-Chip Matching with Single-Ended Antenna Port + + - Power Management Maximizes Operating Time for Battery Applications + + - Integrated SIMO SMPS for Coin-Cell Operation + - Dynamic Voltage Scaling Minimizes Active Core Power Consumption + - 27.3μA/MHz at 3.3V Executing from Cache + - Selectable SRAM Retention in Low Power Modes with RTC Enabled + + - Multiple Peripherals for System Control + + - Three QSPI Master/Slave with Three Chip Selects Each + - Three 4-Wire UARTs + - Three I2C Master/Slave + - Up to 50 GPIO + - QSPI (SPIXF) with Real-Time Flash Decryption + - QSPI (SPIXR) RAM Interface Provides SRAMExpansion + - 8-Input 10-Bit Delta-Sigma ADC 7.8ksps + - USB 2.0 HS Engine with Internal Transceiver + - PDM Interface Supports Two Digital Microphones + - I2S with TDM + - Six 32-Bit Timers + - Two High-Speed Timers + - 1-Wire Master + - Sixteen Pulse Trains (PWM) + - Secure Digital Interface Supports SD3.0/SDIO3.0/eMMC4.51 + + - Secure Valuable IP/Data with Hardware Security + + - Trust Protection Unit (TPU) with MAA SupportsFast ECDSA and Modular Arithmetic + - AES128/192/256, DES, 3DES, Hardware Accelerator + - TRNG Seed Generator + - SHA-2 Accelerator•Secure Bootloader + +- Benefits and Features of MAX32666EVKIT: + + - Bluetooth SMA connector with a 2.4GHz Hinged Whip Antenna + - 1.28in 128 x 128 Monochrome TFT Display + - 64MB XIP Flash + - 1MB XIP RAM + - Stereo Audio Codec with Line-In and Line-Out 3.5mm Jacks + - Digital Audio Microphone + - USB 2.0 Micro B Interface + - USB 2.0 Micro B to Serial UARTs + - Micro SD Card Interface + - Select GPIOs Accessed Through a 0.1in Header + - Access to the 8 Analog Inputs Through a 0.1in Header + - Arm® or SWD JTAG 20-Pin Header + - 1-Wire RJ11 Port + - Can Be Solely Sourced by a Coin Cell Battery + - Board Power Provided by Either USB Port + - Individual Power Measurement on All IC Rails Through Jumpers + - On-Board 1.8V and 3.3V Regulators + - Two General-Purpose LEDs and Two General-Purpose Pushbutton Switches + + +Supported Features +================== + +Below interfaces are supported by Zephyr on MAX32666EVKIT. + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock and reset control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | dma controller | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| Timer | on-chip | counter | ++-----------+------------+-------------------------------------+ + + +Connections and IOs +=================== + + ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| Name | Name | Settings | Description | ++===========+===============+===============+==================================================================================================+ +| JP1 | I2C0_SCL/SDA | | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects I2C0 SCL and SDA 1.5K pullups from VDDIOH. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects I2C0 SCL and SDA 1.5K pullups to VDDIOH. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP2 | I2C1_SCL/SDA | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects I2C1 SCL and SDA 1.5K pullups from VDDIOH. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects I2C1 SCL and SDA 1.5K pullups to VDDIOH. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP3 | I2C2_SCL/SDA | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects I2C2 SCL and SDA 1.5K pullups from VDDIOH. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects I2C2 SCL and SDA 1.5K pullups to VDDIOH. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP4 | P1_14 | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects LED D2 from P1_14. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects LED D2 to P1_14. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP5 | P1_15 | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects LED D3 from P1_15. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects LED D3 to P1_15. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP6 | VBUS | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-1 | | | Connects VBUS to USB connector CN1 to supply board power. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects VBUS to USB connector CN2 to supply board power. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP7 | N/A | N/A | N/A | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP8 | N/A | N/A | N/A | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP9 | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | P0_20 | | | 2-1 | | | Connects the USB to serial UART to GPIO P0_20 (RX1). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | P0_28 | | | 2-3 | | | Connects the USB to serial UART to GPIO P0_28 (RX2). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP10 | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | P0_21 | | | 2-1 | | | Connects the USB to serial UART to GPIO P0_21 (TX1). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | P0_29 | | | 2-3 | | | Connects the USB to serial UART to GPIO P0_29 (TX2). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP11 | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | P0_22 | | | 2-1 | | | Connects the USB to serial UART to GPIO P0_22 (CTS1_N). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | P0_30 | | | 2-3 | | | Connects the USB to serial UART to GPIO P0_30 (CTS2_N). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP12 | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | P0_23 | | | 2-1 | | | Connects the USB to serial UART to GPIO P0_23 (RTS1_N). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | P0_31 | | | 2-3 | | | Connects the USB to serial UART to GPIO P0_31 (RTS2_N). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP13 | VREGI | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-1 | | | Connects VREGI to the coin cell battery. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects VREGI to 3V3. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP14 | VDDIOH | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects VDDIOH to VREGO_A | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 3-4 | | | Connects VDDIOH to 1V8. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 5-6 | | | Connects VDDIOH to 3V3. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP15 | VDDIOH | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VDDIOH. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects power to VDDIOH. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP16 | VDDB | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VDDB. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects power to VDDB. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP17 | VDDIO | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-1 | | | Connects VDDIO to VREGO_A. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects VDDIO to 1V8. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP18 | VDDIO | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VDDIO. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects power to VDDIO. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP19 | VDDA | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VDDA. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects power to VDDA. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP20 | VCORE_A | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VCORE_A. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects power to VCORE_A. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP21 | VCORE_B | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VCORE_B. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects power to VCORE_B. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP22 | VTXIN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VTXIN. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects power to VTXIN. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP23 | VRXIN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VRXIN. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects power to VRXIN. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ + + + +Programming and Debugging +************************* + +Flashing +======== + +The MAX32666 MCU can be flashed by connecting an external debug probe to the +SWD port. SWD debug can be accessed through the Cortex 10-pin connector, J6. +Logic levels are fixed to VDDIOH (1.8V or 3.3V). + +Once the debug probe is connected to your host computer, then you can simply run the +``west flash`` command to write a firmware image into flash. + +.. note:: + + This board uses OpenOCD as the default debug interface. You can also use + a Segger J-Link with Segger's native tooling by overriding the runner, + appending ``--runner jlink`` to your ``west`` command(s). The J-Link should + be connected to the standard 20-pin connector (J7) or a Cortex® 10-pin connector (J6). + +Debugging +========= + +Please refer to the `Flashing`_ section and run the ``west debug`` command +instead of ``west flash``. + +References +********** + +- `MAX32666EVKIT web page`_ + +.. _MAX32666EVKIT web page: + https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/MAX32666EVKIT.html diff --git a/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.dts b/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.dts new file mode 100644 index 00000000000..a87658da4e8 --- /dev/null +++ b/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.dts @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include + +/ { + model = "Analog Devices MAX32666EVKIT"; + compatible = "adi,max32666evkit"; + + chosen { + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,sram = &sram4; + zephyr,flash = &flash0; + }; + + leds { + compatible = "gpio-leds"; + led1: led_1 { + gpios = <&gpio1 14 (GPIO_ACTIVE_LOW | MAX32_GPIO_VSEL_VDDIOH)>; + label = "Red LED"; + }; + led2: led_2 { + gpios = <&gpio1 15 (GPIO_ACTIVE_LOW | MAX32_GPIO_VSEL_VDDIOH)>; + label = "Blue LED"; + }; + }; + + buttons { + compatible = "gpio-keys"; + pb1: pb1 { + gpios = <&gpio1 6 (GPIO_PULL_UP | GPIO_ACTIVE_LOW + | MAX32_GPIO_VSEL_VDDIOH)>; + label = "SW2"; + zephyr,code = ; + }; + pb2: pb2 { + gpios = <&gpio1 7 (GPIO_PULL_UP | GPIO_ACTIVE_LOW + | MAX32_GPIO_VSEL_VDDIOH)>; + label = "SW3"; + zephyr,code = ; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led1; + led1 = &led2; + sw0 = &pb1; + sw1 = &pb2; + watchdog0 = &wdt0; + }; +}; + +&uart1 { + pinctrl-0 = <&uart1_tx_p0_21 &uart1_rx_p0_20>; + pinctrl-names = "default"; + current-speed = <115200>; + data-bits = <8>; + parity = "none"; + status = "okay"; +}; + +&clk_ipo { + status = "okay"; +}; + +&dma0 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + pinctrl-0 = <&i2c1_scl_p0_14 &i2c1_sda_p0_15>; + pinctrl-names = "default"; +}; + +&i2c2 { + status = "okay"; + pinctrl-0 = <&i2c2_scl_p1_14 &i2c2_sda_p1_15>; + pinctrl-names = "default"; +}; + +&trng { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; diff --git a/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.yaml b/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.yaml new file mode 100644 index 00000000000..45320dd7307 --- /dev/null +++ b/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.yaml @@ -0,0 +1,20 @@ +identifier: max32666evkit/max32666/cpu0 +name: max32666evkit cpu0 +vendor: adi +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - dma + - i2c + - gpio + - serial + - trng + - watchdog + - adc + - counter +ram: 560 +flash: 1024 diff --git a/boards/adi/max32666evkit/max32666evkit_max32666_cpu0_defconfig b/boards/adi/max32666evkit/max32666evkit_max32666_cpu0_defconfig new file mode 100644 index 00000000000..fc547f746b1 --- /dev/null +++ b/boards/adi/max32666evkit/max32666evkit_max32666_cpu0_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# enable uart driver +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/adi/max32666fthr/Kconfig.max32666fthr b/boards/adi/max32666fthr/Kconfig.max32666fthr new file mode 100644 index 00000000000..ca6e313e6c1 --- /dev/null +++ b/boards/adi/max32666fthr/Kconfig.max32666fthr @@ -0,0 +1,7 @@ +# MAX32666FTHR boards configuration + +# Copyright (c) 2023-2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MAX32666FTHR + select SOC_MAX32666_CPU0 if BOARD_MAX32666FTHR_MAX32666_CPU0 diff --git a/boards/adi/max32666fthr/board.cmake b/boards/adi/max32666fthr/board.cmake new file mode 100644 index 00000000000..b2315d05907 --- /dev/null +++ b/boards/adi/max32666fthr/board.cmake @@ -0,0 +1,9 @@ +# Copyright (c) 2023-2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]") +board_runner_args(openocd --cmd-pre-init "source [find target/max32665.cfg]") +board_runner_args(jlink "--device=MAX32666" "--reset-after-load") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/adi/max32666fthr/board.yml b/boards/adi/max32666fthr/board.yml new file mode 100644 index 00000000000..a071afb909e --- /dev/null +++ b/boards/adi/max32666fthr/board.yml @@ -0,0 +1,8 @@ +# Copyright (c) 2023-2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: max32666fthr + vendor: adi + socs: + - name: max32666 diff --git a/boards/adi/max32666fthr/doc/img/max32666fthr_img1.jpg b/boards/adi/max32666fthr/doc/img/max32666fthr_img1.jpg new file mode 100644 index 00000000000..0e04eeb25eb Binary files /dev/null and b/boards/adi/max32666fthr/doc/img/max32666fthr_img1.jpg differ diff --git a/boards/adi/max32666fthr/doc/img/max32666fthr_img2.jpg b/boards/adi/max32666fthr/doc/img/max32666fthr_img2.jpg new file mode 100644 index 00000000000..84d109f9cc7 Binary files /dev/null and b/boards/adi/max32666fthr/doc/img/max32666fthr_img2.jpg differ diff --git a/boards/adi/max32666fthr/doc/index.rst b/boards/adi/max32666fthr/doc/index.rst new file mode 100644 index 00000000000..df762d373f5 --- /dev/null +++ b/boards/adi/max32666fthr/doc/index.rst @@ -0,0 +1,238 @@ +.. _max32666_fthr: + +MAX32666FTHR +############ + +Overview +******** +The MAX32666FTHR board is a rapid development platform to help engineers quickly implement battery +optimized Bluetooth® 5 solutions with the MAX32666 Arm® Cortex®-M4 processor with FPU. The board +also includes the MAX1555 1-Cell Li+ battery charger for battery management. The form factor is +a small 0.9in by 2.0in dualrow header footprint that is compatible with breadboards and +off-the-shelf peripheral expansion boards. The board also includes a variety of peripherals, +such as a micro SD card connector, 6-axis accelerometer/gyro, RGB indicator LED, and pushbutton. +This platform provides poweroptimized flexible for quick proof-of-concepts and early software +development to enhance time to market. + + +The Zephyr port is running on the MAX32666 MCU. + +.. image:: img/max32666fthr_img1.jpg + :align: center + :alt: MAX32666FTHR Front + +.. image:: img/max32666fthr_img1.jpg + :align: center + :alt: MAX32666FTHR Back + +Hardware +******** + +- MAX32666 MCU: + + - High-Efficiency Microcontroller and Audio DSP for Wearable and Hearable Devices + + - Arm Cortex-M4 with FPU Up to 96MHz + - Optional Second Arm Cortex-M4 with FPU Optimized for Data Processing + - Low-Power 7.3728MHz System Clock Option + - 1MB Flash, Organized into Dual Banks 2 x 512KB + - 560KB (448KB ECC) SRAM; 3 x 16KB Cache + - Optional Error Correction Code (ECC-SEC-DED)for Cache, SRAM, and Internal Flash + + - Bluetooth 5 Low Energy Radio + + - 1Mbps and 2Mbps Data Throughput + - Long Range (125kbps and 500kbps) + - Advertising Extension + - Rx Sensitivity: -95dbm; Tx Power Up to +4.5dbm + - On-Chip Matching with Single-Ended Antenna Port + + - Power Management Maximizes Operating Time for Battery Applications + + - Integrated SIMO SMPS for Coin-Cell Operation + - Dynamic Voltage Scaling Minimizes Active Core Power Consumption + - 27.3μA/MHz at 3.3V Executing from Cache + - Selectable SRAM Retention in Low Power Modes with RTC Enabled + + - Multiple Peripherals for System Control + + - Three QSPI Master/Slave with Three Chip Selects Each + - Three 4-Wire UARTs + - Three I2C Master/Slave + - Up to 50 GPIO + - QSPI (SPIXF) with Real-Time Flash Decryption + - QSPI (SPIXR) RAM Interface Provides SRAMExpansion + - 8-Input 10-Bit Delta-Sigma ADC 7.8ksps + - USB 2.0 HS Engine with Internal Transceiver + - PDM Interface Supports Two Digital Microphones + - I2S with TDM + - Six 32-Bit Timers + - Two High-Speed Timers + - 1-Wire Master + - Sixteen Pulse Trains (PWM) + - Secure Digital Interface Supports SD3.0/SDIO3.0/eMMC4.51 + + - Secure Valuable IP/Data with Hardware Security + + - Trust Protection Unit (TPU) with MAA SupportsFast ECDSA and Modular Arithmetic + - AES128/192/256, DES, 3DES, Hardware Accelerator + - TRNG Seed Generator + - SHA-2 Accelerator•Secure Bootloader + +- External devices connected to the MAX32666FTHR: + + - MAX1555 1-Cell Li+ Battery Charger + - Breadboard Compatible Headers + - 10-Pin Cortex Debug Header + - Micro USB Connector + - Micro SD Card Connector + - RGB Indicator LED and One General Purpose Push Button Switch + - 6-Axis Accelerometer/Gyro + - Bluetooth Surface Mount Antenna + + +Supported Features +================== + +Below interfaces are supported by Zephyr on MAX32666FTHR. + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock and reset control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | dma controller | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| Timer | on-chip | counter | ++-----------+------------+-------------------------------------+ + +Connections and IOs +=================== + +JH3 Pinout +********** + ++---------+----------+-------------------------------------------------------------------------------------------------+ +| Pin | Name | Description | ++=========+==========+=================================================================================================+ +| 1 | GND | Ground | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 2 | P0_9 | UART0 Tx | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 3 | P0_10 | UART0 Rx | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 4 | P0_26 | QSPI2 MISO | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 5 | P0_25 | QSPI2 MOSI | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 6 | P0_27 | QSPI2 SCK | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 7 | AIN_5 | ADC Analog Input. Alternatively, AIN2N or P0_21 | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 8 | AIN_4 | ADC Analog Input. Alternatively, AIN2P or P0_20 | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 9 | AIN_3 | ADC Analog Input. Alternatively, AIN1N or P0_19 | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 10 | AIN_2 | ADC Analog Input. Alternatively, AIN1P or P0_18 | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 11 | AIN_1 | ADC Analog Input. Alternatively, AIN0N or P0_17 | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 12 | AIN_0 | ADC Analog Input. Alternatively, AIN0P or P0_16 | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 13 | GND | Ground | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 14 | NC | No Connection | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 15 | 3V3 | 3.3V Output. Typically used to provide 3.3V to peripherals connected to the expansion headers | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 16 | RSTN | Master Reset Signal | ++---------+----------+-------------------------------------------------------------------------------------------------+ + + +JH4 Pinout +********** + ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| Pin | Name | Description | ++=========+==========+===========================================================================================================+ +| 1 | SYS | SYS switched connection to the Battery. This is the primary system power supply and | +| | | automatically switches between the battery voltage and the USB supply when available. | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| 2 | PWREN | Power Enable. This is connected to the ON pin of the MAX4995 LDO. It turns off the LDO if shorted to GND. | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| 3 | VBUS | USB VBUS Signal. This can be used as a 5V supply when connected to USB. This pin can also be used as | +| | | an input to power the board, but this should only be done when not using the USB connector since there is | +| | | no circuitry to prevent current from flowing back into the USB connector. | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| 4 | P0_12 | 1-Wire master signal | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| 5 | P0_3 | SPIXF SCK | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| 6 | P0_5 | SPIXF SDIO3 | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| 7 | P0_4 | SPIXF SDIO2 | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| 8 | P0_2 | SPIXF SDIO1/MISO | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| 9 | P0_1 | SPIXF SDIO0/MOSI | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| 10 | P0_0 | SPIXF SS0 | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| 11 | P0_6 | I2CM0 SCL. Pulled to MAX32666 VDDIOH, connected to BMI160. | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| 12 | P0_7 | I2CM0 SDA. Pulled to MAX32666 VDDIOH, connected to BMI160. | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ + + +Programming and Debugging +************************* + +Flashing +======== + +The MAX32666 MCU can be flashed by connecting an external debug probe to the SWD port. +SWD debug can be accessed through the Cortex 10-pin connector, JH2. +Logic levels are fixed to VDDIO (1.8V). + +Once the debug probe is connected to your host computer, then you can simply run the +``west flash`` command to write a firmware image into flash. + +.. note:: + + This board uses OpenOCD as the default debug interface. You can also use + a Segger J-Link with Segger's native tooling by overriding the runner, + appending ``--runner jlink`` to your ``west`` command(s). The J-Link should + be connected to the standard 2*5 pin debug connector (JH2) using an + appropriate adapter board and cable. + +Debugging +========= + +Please refer to the `Flashing`_ section and run the ``west debug`` command +instead of ``west flash``. + +References +********** + +- `MAX32666FTHR web page`_ + +.. _MAX32666FTHR web page: + https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/MAX32666FTHR.html diff --git a/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.dts b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.dts new file mode 100644 index 00000000000..95597c47266 --- /dev/null +++ b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.dts @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2023-2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include + +/ { + model = "Analog Devices MAX32666FTHR"; + compatible = "adi,max32666fthr"; + + chosen { + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,sram = &sram4; + zephyr,flash = &flash0; + }; + + leds { + compatible = "gpio-leds"; + led1: led_1 { + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + label = "Red LED"; + }; + led2: led_2 { + gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; + label = "Blue LED"; + }; + led3: led_3 { + gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; + label = "Green LED"; + }; + }; + + buttons { + compatible = "gpio-keys"; + pb1: pb1 { + gpios = <&gpio1 10 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW1"; + zephyr,code = ; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led1; + led1 = &led2; + led2 = &led3; + sw0 = &pb1; + watchdog0 = &wdt0; + }; + + /* Used for accessing other pins */ + feather_header: feather_connector { + compatible = "adafruit-feather-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <12 0 &gpio0 7 0>, /* SDA */ + <13 0 &gpio0 6 0>, /* SCL */ + <14 0 &gpio0 0 0>, /* GPIO */ + <15 0 &gpio0 1 0>, /* GPIO */ + <16 0 &gpio0 2 0>, /* GPIO */ + <17 0 &gpio0 4 0>, /* GPIO */ + <18 0 &gpio0 5 0>, /* GPIO */ + <19 0 &gpio0 3 0>, /* GPIO */ + <20 0 &gpio0 12 0>, /* OWM */ + /* 11 not connected */ + <10 0 &gpio0 9 0>, /* TX */ + <9 0 &gpio0 10 0>, /* RX */ + <8 0 &gpio0 26 0>, /* MISO */ + <7 0 &gpio0 25 0>, /* MOSI */ + <6 0 &gpio0 27 0>, /* SCK */ + <5 0 &gpio0 21 0>, /* AIN5 */ + <4 0 &gpio0 20 0>, /* AIN4 */ + <3 0 &gpio0 19 0>, /* AIN3 */ + <2 0 &gpio0 18 0>, /* AIN2 */ + <1 0 &gpio0 17 0>, /* AIN1 */ + <0 0 &gpio0 16 0>; /* AIN0 */ + }; +}; + +&uart1 { + pinctrl-0 = <&uart1_tx_p1_13 &uart1_rx_p1_12>; + pinctrl-names = "default"; + current-speed = <115200>; + data-bits = <8>; + parity = "none"; + status = "okay"; +}; + +&clk_ipo { + status = "okay"; +}; + +&dma0 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&trng { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; + pinctrl-0 = <&spi1_mosi_p0_17 &spi1_miso_p0_18 &spi1_sck_p0_19 &spi1_ss0_p0_16>; + pinctrl-names = "default"; +}; diff --git a/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.yaml b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.yaml new file mode 100644 index 00000000000..f70a32e68cf --- /dev/null +++ b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.yaml @@ -0,0 +1,21 @@ +identifier: max32666fthr/max32666/cpu0 +name: max32666fthr cpu0 +vendor: adi +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - dma + - i2c + - gpio + - serial + - trng + - watchdog + - spi + - adc + - counter +ram: 560 +flash: 1024 diff --git a/boards/adi/max32666fthr/max32666fthr_max32666_cpu0_defconfig b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0_defconfig new file mode 100644 index 00000000000..b0a3b911431 --- /dev/null +++ b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2023-2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# enable uart driver +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/adi/max32670evkit/Kconfig.max32670evkit b/boards/adi/max32670evkit/Kconfig.max32670evkit new file mode 100644 index 00000000000..2ae479bd856 --- /dev/null +++ b/boards/adi/max32670evkit/Kconfig.max32670evkit @@ -0,0 +1,7 @@ +# MAX32670EVKIT boards configuration + +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MAX32670EVKIT + select SOC_MAX32670 diff --git a/boards/adi/max32670evkit/board.cmake b/boards/adi/max32670evkit/board.cmake new file mode 100644 index 00000000000..fc69d3635f1 --- /dev/null +++ b/boards/adi/max32670evkit/board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]") +board_runner_args(openocd --cmd-pre-init "source [find target/max32670.cfg]") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/adi/max32670evkit/board.yml b/boards/adi/max32670evkit/board.yml new file mode 100644 index 00000000000..1d0aabb3954 --- /dev/null +++ b/boards/adi/max32670evkit/board.yml @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: max32670evkit + vendor: adi + socs: + - name: max32670 diff --git a/boards/adi/max32670evkit/doc/img/max32670evkit.webp b/boards/adi/max32670evkit/doc/img/max32670evkit.webp new file mode 100644 index 00000000000..9b5aa0a1f90 Binary files /dev/null and b/boards/adi/max32670evkit/doc/img/max32670evkit.webp differ diff --git a/boards/adi/max32670evkit/doc/index.rst b/boards/adi/max32670evkit/doc/index.rst new file mode 100644 index 00000000000..3a03283975e --- /dev/null +++ b/boards/adi/max32670evkit/doc/index.rst @@ -0,0 +1,205 @@ +.. _max32670_evkit: + +MAX32670EVKIT +############# + +Overview +******** +The MAX32670 evaluation kit (EV kit) provides a platform for evaluation capabilities +of the MAX32670. The MAX32670 is an ultra-low-power, cost-effective, highly reliable +32-bit microcontroller that enables designs with complex sensor processing without +compromising battery life. It combines a flexible and versatile power management unit +with the powerful Arm® Cortex®-M4 core with floating point unit (FPU). +The MAX32670 also offers legacy designs an easy and cost optimal upgradepath +from 8-bit or 16-bit microcontrollers. + +The Zephyr port is running on the MAX32670 MCU. + +.. image:: img/max32670evkit.webp + :align: center + :alt: MAX32670 EVKIT + +Hardware +******** + +- MAX32670 MCU: + + - High-Efficiency Microcontroller for Low-Power, High-Reliability Devices + + - Arm Cortex-M4 Core with FPU up to 100MHz + - 384KB Flash Memory with Error Correction + - 160KB SRAM (128KB with ECC Enabled),Optionally Preserved in Lowest Power Modes + - 16KB Unified Cache with ECC + + - UART Bootloader + + - Dual- or Single-Supply Operation + - Ultra-Low 0.9V to 1.1V VCORE Supply Voltage + - Internal LDO Operation from 1.7V to 3.6V SingleSupply + + - Wide Operating Temperature: -40°C to +105°C + + - Flexible Clocking Schemes + + - Internal High-Speed 100MHz Oscillator + - Internal Low-Power 7.3728MHz and Ultra-Low-Power 80kHz Oscillators + - 16MHz to 32MHz Oscillator (External CrystalRequired) + - 32.768kHz Oscillator (External Crystal Required) + - External Clock Input for the Core + - External Clock Input for the LPUART and LPTMR + + - Power Management Maximizes Uptime for Battery Applications + + - 44μA/MHz Active at 0.9V up to 12MHz + - 50μA/MHz Active at 1.1V up to 100MHz + - 2.6μA Full Memory Retention Power in BACKUPMode at VDD = 1.8V + - 350nA Ultra-Low-Power RTC at VDD = 1.8V + - Wake from LPUART or LPTMR + + - Optimal Peripheral Mix Provides Platform Scalability + + - Up to 31 General-Purpose I/O Pins + - Up to Three SPI Master/Slave (up to 50MHz) + - Up to Three 4-Wire UART + - One Low-Power UART (LPUART) + - Up to Three I2C Master/Slave 3.4Mbps High Speed + - 8-Channel Standard DMA Controller + - Up to Four 32-Bit Timers (TMR) + - Up to Two Low-Power 32-Bit Timers (LPTMR) + - Two Windowed Watchdog Timers + - One I2S Slave for Digital Audio Interface + + - Security and Integrity + + - Available Secure Boot + - AES 128/192/256 Hardware Acceleration Engine + - 32-Bit CRC Acceleration Engine + +- Benefits and Features of MAX32670EVKIT: + + - USB 2.0 Micro B to Serial UART Bridge + - UART0 and UART3 Interface is Selectable Through On-Board Jumpers + - On-Board MAX32625PICO-Based Debugger + - Boot Load Enable Circuitry + - SPI and I2C Signals Accessed Through 0.1in Headers + - GPIOs and Miscellaneous Signals Accessed Through 0.1in Headers + - Board Power Provided by USB Port + - On-Board SIMO Regulator and LDO for IC and Peripherals + - Individual Power Measurement on all IC Rails Through Jumpers + - Two General-Purpose LED and One GeneralPurpose Pushbutton Switch + +Supported Features +================== + +Below interfaces are supported by Zephyr on MAX32670EVKIT. + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock and reset control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | dma controller | ++-----------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| Timer | on-chip | counter | ++-----------+------------+-------------------------------------+ + +Connections and IOs +=================== + ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| Name | Name | Settings | Description | ++===========+===============+===============+==================================================================================================+ +| JP1 | P0_22 | | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects red LED from P0_22. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects red to P0_22. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP2 | P0_23 | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects green LED from P0_23. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects green LED to P0_23. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP3 | P0_20 | +-----------+ | +-------------------------------------------------------------------------------+ | +| | P0_26 | | 2-1 | | | Connects the USB to serial port P0_8 (UART0_RX). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects the USB to serial port P0_26 (LPUART0_RX). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP4 | P0_9 | +-----------+ | +-------------------------------------------------------------------------------+ | +| | P0_27 | | 2-1 | | | Connects the USB to serial port P0_9 (UART0_TX). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects the USB to serial port P0_27 (LPUART0_TX). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP5 | VDD | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power to VDD. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects power to VDD. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP6 | VCORE | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power to VCORE. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects power to VCORE. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP7 | SIMO RSEL2 | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Sets output 2 of the SIMO regulator to 0.9V. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 3-4 | | | Sets output 2 of the SIMO regulator to 1.0V. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 5-6 | | | Sets output 2 of the SIMO regulator to 1.1V. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ + +Programming and Debugging +************************* + +Flashing +======== + +The MAX32670 EVKIT integrates a MAX32625PICO based debugger for DAPLink functionality. + + +Once the debug probe is connected to your host computer, then you can simply run the +``west flash`` command to write a firmware image into flash. + +Debugging +========= + +Please refer to the `Flashing`_ section and run the ``west debug`` command +instead of ``west flash``. + +References +********** + +- `MAX32670EVKIT web page`_ + +.. _MAX32670EVKIT web page: + https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/max32670evkit.html diff --git a/boards/adi/max32670evkit/max32670evkit.dts b/boards/adi/max32670evkit/max32670evkit.dts new file mode 100644 index 00000000000..98c6076374b --- /dev/null +++ b/boards/adi/max32670evkit/max32670evkit.dts @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include + +/ { + model = "Analog Devices MAX32670EVKIT"; + compatible = "adi,max32670evkit"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &sram3; + zephyr,flash = &flash0; + }; + + leds { + compatible = "gpio-leds"; + led1: led_1 { + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + label = "Red LED"; + }; + led2: led_2 { + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; + label = "Blue LED"; + }; + }; + + buttons { + compatible = "gpio-keys"; + pb1: pb1 { + gpios = <&gpio0 21 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW2"; + zephyr,code = ; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led1; + led1 = &led2; + sw0 = &pb1; + watchdog0 = &wdt0; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0a_tx_p0_9 &uart0a_rx_p0_8>; + pinctrl-names = "default"; + current-speed = <115200>; + data-bits = <8>; + parity = "none"; + status = "okay"; +}; + +&clk_ipo { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&trng { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-0 = <&i2c0_scl_p0_6 &i2c0_sda_p0_7>; + pinctrl-names = "default"; +}; + +&dma0 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + pinctrl-0 = <&spi0_mosi_p0_3 &spi0_miso_p0_2 &spi0_sck_p0_4 &spi0_ss0_p0_5>; + pinctrl-names = "default"; +}; diff --git a/boards/adi/max32670evkit/max32670evkit.yaml b/boards/adi/max32670evkit/max32670evkit.yaml new file mode 100644 index 00000000000..f4550186628 --- /dev/null +++ b/boards/adi/max32670evkit/max32670evkit.yaml @@ -0,0 +1,20 @@ +identifier: max32670evkit +name: max32670evkit +vendor: adi +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - serial + - trng + - i2c + - dma + - watchdog + - spi + - counter +ram: 160 +flash: 384 diff --git a/boards/adi/max32670evkit/max32670evkit_defconfig b/boards/adi/max32670evkit/max32670evkit_defconfig new file mode 100644 index 00000000000..a048ab2608f --- /dev/null +++ b/boards/adi/max32670evkit/max32670evkit_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/adi/max32672evkit/Kconfig.defconfig b/boards/adi/max32672evkit/Kconfig.defconfig new file mode 100644 index 00000000000..cb74c0282e7 --- /dev/null +++ b/boards/adi/max32672evkit/Kconfig.defconfig @@ -0,0 +1,29 @@ +# MAX32672EVKIT boards configuration + +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MAX32672EVKIT + +if DISPLAY + +config MIPI_DBI_SPI_3WIRE + default y + +if LVGL + +config LV_Z_BITS_PER_PIXEL + default 16 + +choice LV_COLOR_DEPTH + default LV_COLOR_DEPTH_16 # 16 bit per pixel +endchoice + +config LV_COLOR_16_SWAP + default y + +endif # LVGL + +endif # DISPLAY + +endif # BOARD_MAX32672EVKIT diff --git a/boards/adi/max32672evkit/Kconfig.max32672evkit b/boards/adi/max32672evkit/Kconfig.max32672evkit new file mode 100644 index 00000000000..4b7207a0c90 --- /dev/null +++ b/boards/adi/max32672evkit/Kconfig.max32672evkit @@ -0,0 +1,7 @@ +# MAX32672EVKIT boards configuration + +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MAX32672EVKIT + select SOC_MAX32672 diff --git a/boards/adi/max32672evkit/board.cmake b/boards/adi/max32672evkit/board.cmake new file mode 100644 index 00000000000..454ec897d2a --- /dev/null +++ b/boards/adi/max32672evkit/board.cmake @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]") +board_runner_args(openocd --cmd-pre-init "source [find target/max32672.cfg]") +board_runner_args(jlink "--device=MAX32672" "--reset-after-load") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/adi/max32672evkit/board.yml b/boards/adi/max32672evkit/board.yml new file mode 100644 index 00000000000..5df99f681bf --- /dev/null +++ b/boards/adi/max32672evkit/board.yml @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: max32672evkit + vendor: adi + socs: + - name: max32672 diff --git a/boards/adi/max32672evkit/doc/img/max32672evkit.webp b/boards/adi/max32672evkit/doc/img/max32672evkit.webp new file mode 100644 index 00000000000..9b9e2245d38 Binary files /dev/null and b/boards/adi/max32672evkit/doc/img/max32672evkit.webp differ diff --git a/boards/adi/max32672evkit/doc/index.rst b/boards/adi/max32672evkit/doc/index.rst new file mode 100644 index 00000000000..2ad07382fc4 --- /dev/null +++ b/boards/adi/max32672evkit/doc/index.rst @@ -0,0 +1,355 @@ +.. _max32672_evkit: + +MAX32672EVKIT +############# + +Overview +******** +The MAX32672 evaluation kit (EV kit) provides a platform for evaluating the capabilities +of the MAX32672 microcontroller, which is a small, high-reliability, ultra-low power, +32-bit microcontroller. The MAX32672 is a secure and cost-effective solution +for motion/motor control, industrial sensors, and battery-powered medical devices and offers legacy +designs an easy, cost-optimal upgrade path from 8-bit or 16-bit microcontrollers. + +The Zephyr port is running on the MAX32672 MCU. + +.. image:: img/max32672evkit.webp + :align: center + :alt: MAX32672EVKIT + +Hardware +******** + +- MAX32672 MCU: + + - High-Efficiency Microcontroller for Low-Power High-Reliability Devices + + - Arm Cortex-M4 Processor with FPU up to 100MHz + - 1MB Dual-Bank Flash with Error Correction + - 200KB SRAM (160KB with ECC Enabled), Optionally Preserved in Lowest Power Modes + - EEPROM Emulation on Flash + - 16KB Unified Cache with ECC + - Resource Protection Unit (RPU) and MemoryProtection Unit (MPU) + - Dual- or Single-Supply Operation, 1.7V to 3.6V + - Wide Operating Temperature: -40°C to +105°C + + - Flexible Clocking Schemes + + - Internal High-Speed 100MHz Oscillator + - Internal Low-Power 7.3728MHz and Ultra-Low-Power 80kHz Oscillators + - 16MHz–32MHz Oscillator, 32.768kHz Oscillator(External Crystal Required) + - External Clock Input for CPU, LPUART, LPTMR + + - Power Management Maximizes Uptime for Battery Applications + + - 59.8μA/MHz ACTIVE at 0.9V up to 12MHz(CoreMark®) + - 56.6μA/MHz ACTIVE at 1.1V up to 100MHz(While(1)) + - 3.09μA Full Memory Retention Power in BACKUPMode at VDD = 1.8V + - 350nA Ultra-Low-Power RTC at + - Wake from LPUART or LPTMR + + - Optimal Peripheral Mix Provides Platform Scalability + + - Up to 42 General-Purpose I/O Pins + - Up to Three SPI Master/Slave (up to 50Mbps) + - Up to Three 4-Wire UART + - Up to Three I2C Master/Slave 3.4Mbps High Speed + - Up to Four 32-Bit Timers (TMR) + - Up to Two Low-Power 32-Bit Timers (LPTMR) + - One I2S Master/Slave for Digital Audio Interface + - 12-Channel, 12-Bit, 1Msps SAR ADC with On-DieTemperature Sensor + + - Security and Integrity + + - Optional ECDSA-Based Cryptographic SecureBootloader in ROM + - Secure Cryptographic Accelerator for Elliptic Curve + - AES-128/192/256 Hardware Acceleration Engine + +- Benefits and Features of MAX32672EVKIT: + + - Selectable, On-Board, High-Precision Voltage Reference + - 128 x 128 (1.45in) Color TFT Display with SPI Interface + - Breadboard-Compatible Headers + - USB 2.0 Micro B-to-Serial UARTs + - UART0 and LPUART0 Interface Is Selectable through On-Board Jumpers + - All GPIOs Signals Accessed through 0.1in Headers + - 12 Analog Inputs Accessed through 0.1in Headers with Optional Filtering + - 10-Pin Arm® Cortex® SWD Connector + - Board Power Provided by USB Port + - On-Board, 3.3V LDO Regulator + - Test Loops Provided to Supply Optional VCORE Power Externally + - Individual Power Measurement on All IC Rails through Jumpers + - Two General-Purpose LEDs and One General-Purpose Pushbutton Switch + +Supported Features +================== + +Below interfaces are supported by Zephyr on MAX32672EVKIT. + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock and reset control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | dma controller | ++-----------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| Timer | on-chip | counter | ++-----------+------------+-------------------------------------+ + + +Connections and IOs +=================== + ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| Name | Name | Settings | Description | ++===========+===============+===============+==================================================================================================+ +| JP1 | VREF | | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects on-board, high-precision voltage reference. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects on-board, high-precision voltage reference. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP2 | P0_22 | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects red LED D1 from P0_22. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects red LED D1 to P0_22. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP3 | P0_23 | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects green LED D2 from P0_23. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects green LED D2 to P0_23. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP4 | I2C0_SCL | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects 2.2K pullup sourced by 3V3 from I2C0_SCL. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects 2.2K pullup sourced by 3V3 to I2C0_SCL. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP5 | I2C0_SDA | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects 2.2K pullup sourced by 3V3 from I2C0_SDA. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects 2.2K pullup sourced by 3V3 to I2C0_SDA. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP6 | I2C1_SCL | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects 2.2K pullup sourced by 3V3 from I2C1_SCL. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects 2.2K pullup sourced by 3V3 to I2C1_SCL. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP7 | I2C1_SDA | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects 2.2K pullup sourced by 3V3 from I2C1_SDA. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects 2.2K pullup sourced by 3V3 to I2C1_SDA. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP8 | I2C2_SCL | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects 2.2K pullup sourced by 3V3 from I2C2_SCL. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects 2.2K pullup sourced by 3V3 to I2C2_SCL. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP9 | I2C2_SDA | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects 2.2K pullup sourced by 3V3 from I2C2_SDA. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects 2.2K pullup sourced by 3V3 to I2C2_SDA. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP10 | UART_RX | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-1 | | | Connects the USB serial bridge to UART0_RX (P0.8). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects the USB serial bridge to LUART0_RX (P0.26). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP11 | UART_TX | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-1 | | | Connects the USB serial bridge to UART0_TX (P0.9). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects the USB serial bridge to LUART0_TX (P0.27). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP12 | VDDA | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VDDA. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects power to VDDA. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP13 | VDD | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VDD. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects power to VDD. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP14 | VCORE | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VCORE from an external power supply through test loop TP6.| | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects power to VCORE from an external power supply through test loop TP6. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP15 | LDO DUT | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from 3.3V LDO. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects power to 3.3V LDO. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ + + +Detailed Description of Hardware +================================ + +Power Supply +************ + +The EV kit is powered by +5V, which is made available through VBUS on the Micro USB type-B +connector CN1. The blue VBUS LED (DS1) and the green 3.3V LED will illuminate +when the board is powered. + +Single- or Dual-Supply Operation +******************************** + +The EV kit is configured for single-supply operation. For dual-supply operation, +install a jumper on JP14 and connect an external supply to TP6 (VCORE_EXT) and ground. +Refer to the MAX32672 data sheet for acceptable voltage values. + +Current Monitoring +****************** + +Two pin headers provide convenient current monitoring points for VDDA EN (JP12), VDD EN (JP13), +and VCORE EN (JP14). JP14 is only used for current measurements when VCORE is supplied externally. + +Low-Power Mode Current Measurements +*********************************** + +To accurately achieve the low-power current values, the EV kit must be configured such that +no outside influence (such as a pullup, external clock, or debugger connector) causes +a current source or sink on that GPIO. For these measurements, the board will be needed to be +configured as follows: + +1. Remove jumpers JP2 through JP11. +2. Set SW2 to the DIS position and remove resistor R12. +3. Unplug the SWD connector. + +Clocking +******** + +The MAX32672 clocking is provided by an external 16MHz crystal (Y1). + +External Voltage Reference +************************** + +The external voltage reference input VREF for the ADC can be sourced externally by a high-precision +external reference source (the MAX6071). VREF (JP1) allows the external reference +to be disconnected so that VREF can be sourced internally by VDDA. + + +UART Interface +************** + +The EV kit provides a USB-to-UART bridge chip (the FTDI FT230XS-R). This bridge eliminates +the requirement for a physical RS-232 COM port. Instead, the IC’s UART access is through +the Micro USB type-B connector (CN1). The USB-to-UART bridge can be connected to the IC’s UART0 or +LPUART0 with jumpers JP10 (RX0) and JP11 (TX0). Virtual COM port drivers and guides for +installing Windows® drivers are available on the FTDI Chip website. + + +Boot Loader +*********** + +The boot loader is activated by the boot-load-enable slide switch (SW2). +This pulls P0_10 low and, upon a power cycle or reset, the device will enter boot loader mode. + +GPIO and Alternate Function Headers +*********************************** + +GPIO and alternate function signals from the MAX32672 +can be accessed through 0.1in-spaced headers J3 and J4. + + +Analog Headers +************** + +The 12 analog inputs can be accessed through 0.1inspaced headers JH1, JH2, and JH3. + + +I2C Pullups +*********** + +The I2C ports can independently pulled up to V_AUX (3.3V default) through JP4 (I2C0_CL_PU) and JP5 +(I2C0_DA_PU), JP6 (I2C1_CL_PU) and JP7 (I2C1_DA_PU), and JP8 (I2C2_CL_PU) and JP9 (I2C2_DA_PU). + +Programming and Debugging +************************* + +The IC can be reset by pushbutton SW1. + + +Programming and Debugging +************************* + +Flashing +======== + +SWD debug can be accessed through an Arm Cortex 10-pin connector (J5). +Logic levels are set to 3V3 by default, but they can be set to 1.8V if TP5 (VDD_VDDA_EXT) +is supplied externally. Be sure to remove jumper JP15 (LDO_DUT_EN) to disconnect the 3.3V +LDO if supplying VDD and VDDA externally. + +Once the debug probe is connected to your host computer, then you can simply run the +``west flash`` command to write a firmware image into flash. + +.. note:: + + This board uses OpenOCD as the default debug interface. You can also use + a Segger J-Link with Segger's native tooling by overriding the runner, + appending ``--runner jlink`` to your ``west`` command(s). The J-Link should + be connected to the standard 2*5 pin debug connector (JH2) using an + appropriate adapter board and cable. + +Debugging +========= + +Please refer to the `Flashing`_ section and run the ``west debug`` command +instead of ``west flash``. + +References +********** + +- `MAX32672EVKIT web page`_ + +.. _MAX32672EVKIT web page: + https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/max32672evkit.html diff --git a/boards/adi/max32672evkit/max32672evkit.dts b/boards/adi/max32672evkit/max32672evkit.dts new file mode 100644 index 00000000000..d1d97f78af2 --- /dev/null +++ b/boards/adi/max32672evkit/max32672evkit.dts @@ -0,0 +1,151 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include + +/ { + model = "Analog Devices MAX32672EVKIT"; + compatible = "adi,max32672evkit"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &sram3; + zephyr,flash = &flash0; + zephyr,display = &st7735; + }; + + leds { + compatible = "gpio-leds"; + led1: led_1 { + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + label = "Red LED"; + }; + led2: led_2 { + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; + label = "Green LED"; + }; + }; + + buttons { + compatible = "gpio-keys"; + pb1: pb1 { + gpios = <&gpio0 18 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW3"; + zephyr,code = ; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led1; + led1 = &led2; + sw0 = &pb1; + watchdog0 = &wdt0; + }; + + mipi_dbi { + compatible = "zephyr,mipi-dbi-spi"; + /* Enable D/C line for 4wire mode */ + /* dc-gpios = <&gpio0 19 (GPIO_ACTIVE_HIGH | MAX32_GPIO_VSEL_VDDIOH)>; */ + spi-dev = <&spi0>; + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + st7735: st7735@0 { + compatible = "sitronix,st7735r"; + mipi-max-frequency = ; + mipi-mode = ; + + reg = <0>; + width = <130>; + height = <132>; + x-offset = <0>; + y-offset = <0>; + madctl = <0xc0>; + colmod = <0x05>; + vmctr1 = <0x51>; + pwctr1 = [02 02]; + pwctr2 = [c5]; + pwctr3 = [0d 00]; + pwctr4 = [8d 1a]; + pwctr5 = [8d ee]; + frmctr1 = [02 35 36]; + frmctr2 = [02 35 36]; + frmctr3 = [02 35 36 02 35 36]; + gamctrp1 = [0a 1c 0c 14 33 2b 24 28 27 25 2c 39 00 05 03 0d]; + gamctrn1 = [0a 1c 0c 14 33 2b 24 28 27 25 2d 3a 00 05 03 0d]; + }; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0a_tx_p0_9 &uart0a_rx_p0_8>; + pinctrl-names = "default"; + current-speed = <115200>; + data-bits = <8>; + parity = "none"; + status = "okay"; +}; + +&clk_ipo { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&trng { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-0 = <&i2c0a_scl_p0_6 &i2c0a_sda_p0_7>; + pinctrl-names = "default"; +}; + +&dma0 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; + pinctrl-0 = <&spi1a_mosi_p0_15 &spi1a_miso_p0_14 &spi1a_sck_p0_16 &spi1a_ss0_p0_17>; + pinctrl-names = "default"; +}; + +&spi0a_mosi_p0_3 { + power-source=; +}; + +&spi0a_sck_p0_4 { + power-source=; +}; + +&spi0 { + status = "okay"; + pinctrl-0 = <&spi0a_mosi_p0_3 &spi0a_miso_p0_2 &spi0a_sck_p0_4>; + pinctrl-names = "default"; + cs-gpios = <&gpio0 5 (GPIO_ACTIVE_LOW | MAX32_VSEL_VDDIOH)>; +}; diff --git a/boards/adi/max32672evkit/max32672evkit.yaml b/boards/adi/max32672evkit/max32672evkit.yaml new file mode 100644 index 00000000000..276acbe28f8 --- /dev/null +++ b/boards/adi/max32672evkit/max32672evkit.yaml @@ -0,0 +1,21 @@ +identifier: max32672evkit +name: max32672evkit +vendor: adi +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - serial + - trng + - i2c + - dma + - watchdog + - spi + - adc + - counter +ram: 200 +flash: 1024 diff --git a/boards/adi/max32672evkit/max32672evkit_defconfig b/boards/adi/max32672evkit/max32672evkit_defconfig new file mode 100644 index 00000000000..a048ab2608f --- /dev/null +++ b/boards/adi/max32672evkit/max32672evkit_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/adi/max32672fthr/Kconfig.defconfig b/boards/adi/max32672fthr/Kconfig.defconfig new file mode 100644 index 00000000000..71aa092864b --- /dev/null +++ b/boards/adi/max32672fthr/Kconfig.defconfig @@ -0,0 +1,36 @@ +# MAX32672FTHR boards configuration + +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MAX32672FTHR + +if DISPLAY + +if LVGL + +# LVGL should allocate buffers equal to size of display +config LV_Z_VDB_SIZE + default 64 + +# Default Dot Per Inch. [px/inch] +# Used to initialize default sizes such as widgets sized, style paddings. +config LV_DPI_DEF + default 128 + +config LV_Z_BITS_PER_PIXEL + default 1 + +# Use offloaded render thread +config LV_Z_FLUSH_THREAD + default y + +choice LV_COLOR_DEPTH + default LV_COLOR_DEPTH_1 # 1 byte per pixel +endchoice + +endif # LVGL + +endif # DISPLAY + +endif # BOARD_MAX32672FTHR diff --git a/boards/adi/max32672fthr/Kconfig.max32672fthr b/boards/adi/max32672fthr/Kconfig.max32672fthr new file mode 100644 index 00000000000..71f33f5214a --- /dev/null +++ b/boards/adi/max32672fthr/Kconfig.max32672fthr @@ -0,0 +1,7 @@ +# MAX32672FTHR boards configuration + +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MAX32672FTHR + select SOC_MAX32672 diff --git a/boards/adi/max32672fthr/board.cmake b/boards/adi/max32672fthr/board.cmake new file mode 100644 index 00000000000..815111de6b7 --- /dev/null +++ b/boards/adi/max32672fthr/board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]") +board_runner_args(openocd --cmd-pre-init "source [find target/max32672.cfg]") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/adi/max32672fthr/board.yml b/boards/adi/max32672fthr/board.yml new file mode 100644 index 00000000000..c99d16ad4a1 --- /dev/null +++ b/boards/adi/max32672fthr/board.yml @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: max32672fthr + vendor: adi + socs: + - name: max32672 diff --git a/boards/adi/max32672fthr/doc/img/max32672fthr_img1.webp b/boards/adi/max32672fthr/doc/img/max32672fthr_img1.webp new file mode 100644 index 00000000000..9f0e49b247b Binary files /dev/null and b/boards/adi/max32672fthr/doc/img/max32672fthr_img1.webp differ diff --git a/boards/adi/max32672fthr/doc/img/max32672fthr_img2.webp b/boards/adi/max32672fthr/doc/img/max32672fthr_img2.webp new file mode 100644 index 00000000000..38f5e9db758 Binary files /dev/null and b/boards/adi/max32672fthr/doc/img/max32672fthr_img2.webp differ diff --git a/boards/adi/max32672fthr/doc/index.rst b/boards/adi/max32672fthr/doc/index.rst new file mode 100644 index 00000000000..d773c4ceb95 --- /dev/null +++ b/boards/adi/max32672fthr/doc/index.rst @@ -0,0 +1,220 @@ +.. _max32672_fthr: + +MAX32672FTHR +############ + +Overview +******** +The MAX32672FTHR is a rapid development platform that helps engineers quickly implement complex +sensor solutions using the MAX32672 Arm® Cortex®-M4. The board also includes the MAX8819 PMIC for +battery and power management. The form factor is a small, 0.9in by 2.6in, dual row header footprint +that is compatible with Adafruit® FeatherWing peripheral expansion boards. The board includes +an OLED display, a RGB indicator LED, and a user pushbutton. The MAX32672FTHR provides +a power-optimized flexible platform for quick proof-ofconcepts and early software development +to enhance time to market. + +The Zephyr port is running on the MAX32672 MCU. + +.. image:: img/max32672fthr_img1.webp + :align: center + :alt: MAX32672FTHR Front + +.. image:: img/max32672fthr_img2.webp + :align: center + :alt: MAX32672FTHR Back + +Hardware +******** + +- MAX32672 MCU: + + - High-Efficiency Microcontroller for Low-Power High-Reliability Devices + + - Arm Cortex-M4 Processor with FPU up to 100MHz + - 1MB Dual-Bank Flash with Error Correction + - 200KB SRAM (160KB with ECC Enabled), Optionally Preserved in Lowest Power Modes + - EEPROM Emulation on Flash + - 16KB Unified Cache with ECC + - Resource Protection Unit (RPU) and MemoryProtection Unit (MPU) + - Dual- or Single-Supply Operation, 1.7V to 3.6V + - Wide Operating Temperature: -40°C to +105°C + + - Flexible Clocking Schemes + + - Internal High-Speed 100MHz Oscillator + - Internal Low-Power 7.3728MHz and Ultra-Low-Power 80kHz Oscillators + - 16MHz–32MHz Oscillator, 32.768kHz Oscillator(External Crystal Required) + - External Clock Input for CPU, LPUART, LPTMR + + - Power Management Maximizes Uptime for Battery Applications + + - 59.8μA/MHz ACTIVE at 0.9V up to 12MHz(CoreMark®) + - 56.6μA/MHz ACTIVE at 1.1V up to 100MHz(While(1)) + - 3.09μA Full Memory Retention Power in BACKUPMode at VDD = 1.8V + - 350nA Ultra-Low-Power RTC at + - Wake from LPUART or LPTMR + + - Optimal Peripheral Mix Provides Platform Scalability + + - Up to 42 General-Purpose I/O Pins + - Up to Three SPI Master/Slave (up to 50Mbps) + - Up to Three 4-Wire UART + - Up to Three I2C Master/Slave 3.4Mbps High Speed + - Up to Four 32-Bit Timers (TMR) + - Up to Two Low-Power 32-Bit Timers (LPTMR) + - One I2S Master/Slave for Digital Audio Interface + - 12-Channel, 12-Bit, 1Msps SAR ADC with On-DieTemperature Sensor + + - Security and Integrity + + - Optional ECDSA-Based Cryptographic SecureBootloader in ROM + - Secure Cryptographic Accelerator for Elliptic Curve + - AES-128/192/256 Hardware Acceleration Engine + +- Benefits and Features of MAX32672FTHR: + + - MAX8819 PMIC with Integrated Charger + - On-Board DAPLink Debug and Programming Interface for Arm Cortex-M4 + - Breadboard-Compatible Headers + - Micro USB Connector + - RGB Indicator LED + - User Pushbutton + - OLED Display + - SWD Debugger + - Virtual UART Console + +Supported Features +================== + +Below interfaces are supported by Zephyr on MAX32672FTHR. + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock and reset control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | dma controller | ++-----------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| Timer | on-chip | counter | ++-----------+------------+-------------------------------------+ + + +Connections and IOs +=================== + +J9 Pinout +********** + ++---------+----------+-------------------------------------------------------------------------------------------------+ +| Pin | Name | Description | ++=========+==========+=================================================================================================+ +| 1 | RST | Master Reset Signal | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 2 | 3V3 | 3.3V Output. Typically used to provide 3.3V to peripherals connected to the expansion headers. | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 3 | 1V8 | 1.8V Output. Typically used to provide 1.8V to peripherals connected to the expansion headers. | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 4 | GND | Ground | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 5 | P0_11 | GPIO or Analog Input (AIN3 channel). | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 6 | P0_12 | GPIO or Analog Input (AIN4 channel). | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 7 | P0_13 | GPIO or Analog Input (AIN5 channel). | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 8 | P0_22 | GPIO or ADC_TRIG signal. | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 9 | P0_27 | GPIO or QERR signal. | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 10 | P0_26 | GPIO or QDIR signal. | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 11 | P0_16 | GPIO or SPI1 clock signal. | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 12 | P0_15 | GPIO or SPI1 MOSI signal. | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 13 | P0_14 | GPIO or SPI1 MISO signal. | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 14 | P0_28 | GPIO or UART1 Rx signal. | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 15 | P0_29 | GPIO or UART1 Tx signal. | ++---------+----------+-------------------------------------------------------------------------------------------------+ +| 16 | GND | Ground | ++---------+----------+-------------------------------------------------------------------------------------------------+ + + +J7 Pinout +********** + ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| Pin | Name | Description | ++=========+==========+===========================================================================================================+ +| 1 | SYS | SYS Switched Connection to the Battery. This is the primary system power supply and automatically | +| | | switches between the battery voltage and the USB supply when available. | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| 2 | PWR | In battery-powered mode, turns off the PMIC if shorted to ground. | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| 3 | VBUS | USB VBUS Signal. This can be used as a 5V supply when connected to USB. This pin can also be | +| | | used as an input to power the board. | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| 4 | P0_5 | GPIO or HFX_CLK_OUT signal. | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| 5 | P0_6 | GPIO or QEA signal. | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| 6 | P0_7 | GPIO or QEB signal. | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| 7 | P0_23 | GPIO or QEI signal. | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| 8 | P0_17 | GPIO or SPI1 slave select signal. | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| 9 | P0_24 | GPIO or QES signal. | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| 10 | P0_25 | GPIO or QMATCH signal. | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| 11 | P0_18 | GPIO or I2C2 SCL signal. | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ +| 12 | P0_19 | GPIO or I2C2 SDA signal. | ++---------+----------+-----------------------------------------------------------------------------------------------------------+ + +Programming and Debugging +************************* + +Flashing +======== + +The MAX32625 microcontroller on the board is flashed with DAPLink firmware at the factory. +It allows debugging and flashing the MAX32672 Arm Core over USB. + +Once the debug probe is connected to your host computer, then you can simply run the +``west flash`` command to write a firmware image into flash. + +Debugging +========= + +Please refer to the `Flashing`_ section and run the ``west debug`` command +instead of ``west flash``. + +References +********** + +- `MAX32672FTHR web page`_ + +.. _MAX32672FTHR web page: + https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/max32672fthr.html diff --git a/boards/adi/max32672fthr/max32672fthr.dts b/boards/adi/max32672fthr/max32672fthr.dts new file mode 100644 index 00000000000..b2287cf7708 --- /dev/null +++ b/boards/adi/max32672fthr/max32672fthr.dts @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include + +/ { + model = "Analog Devices MAX32672FTHR"; + compatible = "adi,max32672fthr"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &sram3; + zephyr,flash = &flash0; + zephyr,display = &ssd1306; + }; + + leds { + compatible = "gpio-leds"; + led1: led_1 { + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + label = "Red LED"; + }; + led2: led_2 { + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + label = "Green LED"; + }; + led3: led_3 { + gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; + label = "Blue LED"; + }; + }; + + buttons { + compatible = "gpio-keys"; + pb1: pb1 { + gpios = <&gpio0 10 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW2"; + zephyr,code = ; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led1; + led1 = &led2; + led2 = &led3; + sw0 = &pb1; + watchdog0 = &wdt0; + }; + + /* Used for accessing other pins */ + feather_header: feather_connector { + compatible = "adafruit-feather-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <12 0 &gpio0 19 0>, /* SDA */ + <13 0 &gpio0 18 0>, /* SCL */ + <14 0 &gpio0 25 0>, /* I2S LRCLK */ + <15 0 &gpio0 24 0>, /* I2S SDO */ + <16 0 &gpio0 17 0>, /* SPI1 SS */ + <17 0 &gpio0 23 0>, /* QEI */ + <18 0 &gpio0 7 0>, /* QEB */ + <19 0 &gpio0 6 0>, /* QEA */ + <20 0 &gpio0 5 0>, /* HFX CLK OUT */ + /* 11 not connected */ + <10 0 &gpio0 29 0>, /* TX */ + <9 0 &gpio0 28 0>, /* RX */ + <8 0 &gpio0 14 0>, /* MISO */ + <7 0 &gpio0 15 0>, /* MOSI */ + <6 0 &gpio0 16 0>, /* SCK */ + <5 0 &gpio0 26 0>, /* I2S BCLK */ + <4 0 &gpio0 27 0>, /* I2S SDI */ + <3 0 &gpio0 22 0>, /* ADC_TRG */ + <2 0 &gpio0 13 0>, /* AIN5 */ + <1 0 &gpio0 12 0>, /* AIN4 */ + <0 0 &gpio0 11 0>; /* AIN3 */ + }; +}; + +&uart0 { + pinctrl-0 = <&uart0a_tx_p0_9 &uart0a_rx_p0_8>; + pinctrl-names = "default"; + current-speed = <115200>; + data-bits = <8>; + parity = "none"; + status = "okay"; +}; + +&clk_ipo { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&trng { + status = "okay"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2a_scl_p0_18 &i2c2a_sda_p0_19>; + pinctrl-names = "default"; + clock-frequency = ; + status = "okay"; + + ssd1306: ssd1306@3d { + compatible = "solomon,ssd1306fb"; + reg = <0x3d>; + width = <128>; + height = <32>; + segment-offset = <0>; + page-offset = <0>; + display-offset = <0>; + multiplex-ratio = <31>; + segment-remap; + com-invdir; + com-sequential; + prechargep = <0x22>; + inversion-on; + }; +}; + +&dma0 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; + pinctrl-0 = <&spi1a_mosi_p0_15 &spi1a_miso_p0_14 &spi1a_sck_p0_16 &spi1a_ss0_p0_17>; + pinctrl-names = "default"; +}; diff --git a/boards/adi/max32672fthr/max32672fthr.yaml b/boards/adi/max32672fthr/max32672fthr.yaml new file mode 100644 index 00000000000..68ba3c8b8a6 --- /dev/null +++ b/boards/adi/max32672fthr/max32672fthr.yaml @@ -0,0 +1,21 @@ +identifier: max32672fthr +name: max32672fthr +vendor: adi +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - serial + - trng + - i2c + - dma + - watchdog + - spi + - adc + - counter +ram: 200 +flash: 1024 diff --git a/boards/adi/max32672fthr/max32672fthr_defconfig b/boards/adi/max32672fthr/max32672fthr_defconfig new file mode 100644 index 00000000000..a048ab2608f --- /dev/null +++ b/boards/adi/max32672fthr/max32672fthr_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/adi/max32675evkit/Kconfig.max32675evkit b/boards/adi/max32675evkit/Kconfig.max32675evkit new file mode 100644 index 00000000000..25732ef6631 --- /dev/null +++ b/boards/adi/max32675evkit/Kconfig.max32675evkit @@ -0,0 +1,7 @@ +# MAX32675EVKIT boards configuration + +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MAX32675EVKIT + select SOC_MAX32675 diff --git a/boards/adi/max32675evkit/board.cmake b/boards/adi/max32675evkit/board.cmake new file mode 100644 index 00000000000..42caa77e95b --- /dev/null +++ b/boards/adi/max32675evkit/board.cmake @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]") +board_runner_args(openocd --cmd-pre-init "source [find target/max32675.cfg]") +board_runner_args(jlink "--device=MAX32675" "--reset-after-load") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/adi/max32675evkit/board.yml b/boards/adi/max32675evkit/board.yml new file mode 100644 index 00000000000..d51c7284c7f --- /dev/null +++ b/boards/adi/max32675evkit/board.yml @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: max32675evkit + vendor: adi + socs: + - name: max32675 diff --git a/boards/adi/max32675evkit/doc/img/max32675evkit.webp b/boards/adi/max32675evkit/doc/img/max32675evkit.webp new file mode 100644 index 00000000000..c884836b2be Binary files /dev/null and b/boards/adi/max32675evkit/doc/img/max32675evkit.webp differ diff --git a/boards/adi/max32675evkit/doc/index.rst b/boards/adi/max32675evkit/doc/index.rst new file mode 100644 index 00000000000..c4cb514d591 --- /dev/null +++ b/boards/adi/max32675evkit/doc/index.rst @@ -0,0 +1,407 @@ +.. _max32675_evkit: + +MAX32675EVKIT +############# + +Overview +******** +The MAX32675 evaluation kit (EV kit) provides a platform for evaluation capabilities of +the MAX32675 microcontroller, which is a highly integrated, mixed-signal, ultralow-power +microcontroller designed for industrial and medical sensors. It contains an integrated, low-power +HART modem which enables the bidirectional transfer of digital data over a current loop, to/from +industrial sensors for configuration and diagnostics. + +The Zephyr port is running on the MAX32675 MCU. + +.. image:: img/max32675evkit.webp + :align: center + :alt: MAX32675EVKIT + +Hardware +******** + +- MAX32675 MCU: + + - Low-Power, High-Performance for IndustrialApplications + + - 100MHz Arm Cortex-M4 with FPU + - 384KB Internal Flash + - 160KB SRAM + - 128kB ECC Enabled + - 44.1μA/MHz ACTIVE Mode at 0.9V up to 12MHzCoremark® + - 64.5μA/MHz ACTIVE Mode at 1.1V up to 100MHzCoremark + - 2.84μA Full Memory Retention Current in BACKUPMode at VDDIO = 3.3V + - Ultra-Low-Power Analog Peripherals + + - Optimal Peripheral Mix Provides Platform Scalability + + - Two Sigma-Delta ADCs + - 12 Channels, Assignable to Either ADC + - Flexible Resolution and Sample Rates (24 Bits at 0.4ksps, 16 Bits at 4ksps) + - 12-Bit DAC + - On-Die Temperature Sensor + - SPI (M/S) + - Up to Two I2C + - Up to Two UARTs + - Up to 23 GPIOs + - Up to Five 32-Bit Timers + - Two Windowed Watchdog Timers + - 8-Channel Standard DMA Controller + - One I2S Slave for Digital Audio Interface + + - Robust Security and Reliability + + - TRNG Compliant to SP800-90B + - Secure Nonvolatile Key Storage and AES-128/192/256 + - Secure Bootloader to Protect IP/Firmware + - Wide, -40°C to +105°C Operating TemperatureRange + + +- Benefits and Features of MAX32675EVKIT: + + - HART Compatible Secondary Master with the Ability to Connect to Existing 4-20mA Current Loop and Communicate with HART Enabled Devices + - USB 2.0 Micro B to Serial UART + - Two On-Board, High-Precision Voltage References + - All GPIOs Signals Accessed Through 0.1in Headers + - Access to 4 Analog Inputs Through SMA Connectors Configured as Differential + - Access to 8 Analog Inputs Through 0.1in Headers Configured as Single-Ended + - DAC Output Accessed Through SMA Connector or Test Point + - 10-Pin SWD and Connector + - Board Power Provided by USB Port + - On-Board 1.0V, 1.8V, and 3.3V LDO Regulators + - Individual Power Measurement on all IC Rails Through Jumpers + - Two General-Purpose LEDs and Two General-Purpose Pushbutton Switches + +Supported Features +================== + +Below interfaces are supported by Zephyr on MAX32675EVKIT. + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock and reset control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | dma controller | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ + +Connections and IOs +=================== + ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| Name | Name | Settings | Description | ++===========+===============+===============+==================================================================================================+ +| JP1 | P1_9 | | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects red LED D1 from P1_9. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects red LED D1 to P1_9. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP2 | P1_10 | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects green LED D2 from P1_10. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects green LED D2 to P1_10. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP3 | I2C_SCLK | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects 3V3 from I2C_SCLK. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects 3V3 to I2C0_SCLK. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP4 | I2C_SDA | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects 3V3 to I2C_SDA. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects 3V3 to I2C_SDA. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP5 | UART0_RX | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects UART0_RX (P0.8) from the SWD connector. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects UART0_RX (P0.8) to the SWD connector. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP6 | UART0_TX | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disonnects UART0_TX (P0.9) from the SWD connector. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects UART0_TX (P0.9) to the SWD connector. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP7 | REF0N | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects REF0N from ground. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects REF0N to ground. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP8 | REF1N | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects REF1N from ground. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects REF1N to ground. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP9 | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | HART_IN | | | Open | | | Disconnects TX of USB - serial bridge from HART_IN (P0.15). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | HART_IN | | | 1-2 | | | Connects TX of USB - serial bridge to HART_IN (P0.15). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | HART_OUT | | | Open | | | Disconnects RX of USB - serial bridge from HART_OUT (P0.14). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | HART_OUT | | | 3-4 | | | Connects RX of USB - serial bridge to HART_OUT (P0.14). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | HART_RTS | | | Open | | | Disconnects RTS of USB - serial bridge from HART_RTS (P1.8). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | HART_RTS | | | 4-5 | | | Connects TX of USB - serial bridge to HART_RTS (P1.8). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | HART_OCD | | | Open | | | Disconnects RTS of USB - serial bridge from HART_OCD (P0.16). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | HART_OCD | | | 7-8 | | | Connects TX of USB - serial bridge to HART_OCD (P0.16). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP10 | SWD_CLK | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects boot load enable circuit from SWD_CLK (P0.1). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects boot load enable circuit to SWD_CLK (P0.1). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP11 | FSK_IN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects FSK_IN from HART analog circuitry. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects FSK_IN to HART analog circuitry. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP12 | FSK_OUT | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects FSK_OUT from HART analog circuitry. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects FSK_OUT to HART analog circuitry. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP13 | RCV_FSK | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects RCV_FSK from CC LOOP. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects RCV_FSK to CC LOOP. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP14 | RCV_FSK | +-----------+ | +--------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects RCV_FSK from XFMR LOOP. | | +| | | +-----------+ | +--------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects RCV_FSK to XFMR LOOP. | | +| | | +-----------+ | +--------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP15 | RLOAD | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects 249Ω resistor shunt from CC LOOP. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects 249Ω resistor shunt to CC LOOP. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP16 | N/A | N/A | N/A | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP17 | N/A | N/A | N/A | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP18 | N/A | N/A | N/A | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP19 | HART_RTS | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Enables HART_RTS optical transceiver. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Bypasses HART_RTS optical transceiver. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP20 | RLOAD | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects 249Ω resistor shunt from XFMR LOOP. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects 249Ω resistor shunt to XFMR LOOP. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP21 | VDDIO | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VDDIO. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects power to VDDIO. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP22 | VDDA | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VDDA. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects power to VDDA. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP23 | VDD18 | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VDD18. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects power to VDD18. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP24 | VCORE | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VCORE. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects power to VCORE. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP25 | REF0P | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-1 | | | Connects OB_VREF to REF0P. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects INT_VREF to REF0P. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP26 | REF1P | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-1 | | | Connects OB_VREF to REF1P. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects INT_VREF to REF1P. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ + + +Detailed Description of Hardware +================================ + +HART Interface +************** +The HART circuitry acts as a secondary master with the ability to connect to an existing 4mA–20mA +current loop and communicates with HART-enabled devices. Connection to a capacitance coupled loop +through JH8 and a transformer loop is through JH9. HART communication to the MAX32675 is through +the USB connector CN1. + +USB-to-HART Interface +********************* +The EV kit provides a USB-to-HART bridge chip, FTDI FT231. This bridge eliminates the requirement +for a physical RS-232 COM port. Instead, the IC’s HART access is through the Micro-USB type-B +connector, CN1. Virtual COM port drivers and guides for installing Windows® drivers are available +at the FTDI chip website. + +Power Supply +************ +The EV kit is powered by +5V that is made available through VBUS on the Micro-USB type-B +connector CN1. A blue LED (D5) illuminates when the board is powered. Green LEDs (D6), (D7), +and (D8) illuminate when the 3V3, 1V8, and 1V0 LDOs are powered, respectively. + +Current Monitoring +****************** +Two pin headers provide convenient current monitoring points for VDDIO EN (JP21), +VDDA EN (JP22), VDD18 EN (JP23), and VCORE (JP24). +To accurately achieve the low-power current values, the EVkit needs to be configured +such that no outside influence (i.e., pullups, external clock, debugger connector, etc.) +causes a current source or sink on that GPIO. + +Clocking +******** +The MAX32675 clocking is provided by an external 16MHz crystal (Y1). + +Voltage Reference +***************** +The differential reference inputs REF0 and REF1 can be sourced by an internal reference (INT_VREF) +or a higher precision external reference source, MAX6071. +This is selected by jumpers JP25 and JP26. + +UART Interface +************** +The EV kit provides a USB-to-UART bridge chip (the FTDI FT230XS-R). This bridge eliminates +the requirement for a physical RS-232 COM port. Instead, the IC’s UART access is through +the Micro USB type-B connector (CN1). The USB-to-UART bridge can be connected to the IC’s UART0 +or LPUART0 with jumpers JP10 (RX0) and JP11 (TX0). Virtual COM port drivers and guides for +installing Windows® drivers are available on the FTDI Chip website. + +Boot Loader +*********** +Boot load is activated by boot load enable slide switch SW5. + +GPIO and Alternate Function Headers +*********************************** +GPIO and alternate function signals from the MAX32675 can be accessed through 0.1in +spaced headers JH1, JH2, JH3, and JH4. + +Analog Input Access +******************* +Analog inputs (AIN0–AIN3) can be accessed differentially from SMA connectors J2 and J3 or +separately from TP10, TP12, TP15, and TP16, respectively. Analog inputs (AIN4–AIN11) can be +accessed through 0.1in spaced headers JH5 and JH6. + +I2C Pullups +*********** +The I2C port can independently pulled up to 3V3 through JP3 (I2C_SCL) and JP4 (I2C_SDA). + +Reset Pushbutton +**************** +The IC can be reset by pushbutton SW3. + +Indicator LEDs +************** +General-purpose indicators LED D1 (red) is connected to GPIO P1.9 and LED D2 (green) is connected +to GPIO P1.10. + +GPIO Pushbutton Switches +************************ +The two general-purpose pushbuttons (SW1 and SW2) are connected to GPIO P1.11 and P1.12, +respectively. If the pushbutton is pressed, the attached port pin is pulled low. + + +Programming and Debugging +************************* + +Flashing +======== + +SWD debug can be accessed through an Arm Cortex 10-pin connector (J5). +Logic levels are set to 3V3 by default, but they can be set to 1.8V if TP5 (VDD_VDDA_EXT) +is supplied externally. Be sure to remove jumper JP15 (LDO_DUT_EN) to disconnect +the 3.3V LDO if supplying VDD and VDDA externally. + +Once the debug probe is connected to your host computer, then you can simply run the +``west flash`` command to write a firmware image into flash. + +.. note:: + + This board uses OpenOCD as the default debug interface. You can also use + a Segger J-Link with Segger's native tooling by overriding the runner, + appending ``--runner jlink`` to your ``west`` command(s). The J-Link should + be connected to the standard 2*5 pin debug connector (JH2) using an + appropriate adapter board and cable. + +Debugging +========= + +Please refer to the `Flashing`_ section and run the ``west debug`` command +instead of ``west flash``. + +References +********** + +- `MAX32675EVKIT web page`_ + +.. _MAX32675EVKIT web page: + https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/max32675evkit.html diff --git a/boards/adi/max32675evkit/max32675evkit.dts b/boards/adi/max32675evkit/max32675evkit.dts new file mode 100644 index 00000000000..3c5bfccd8b5 --- /dev/null +++ b/boards/adi/max32675evkit/max32675evkit.dts @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include + +/ { + model = "Analog Devices MAX32675EVKIT"; + compatible = "adi,max32675evkit"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &sram3; + zephyr,flash = &flash0; + }; + + leds { + compatible = "gpio-leds"; + led1: led_1 { + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + label = "Red LED"; + }; + led2: led_2 { + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + label = "Green LED"; + }; + }; + + buttons { + compatible = "gpio-keys"; + pb1: pb1 { + gpios = <&gpio1 11 (GPIO_PULL_UP | GPIO_ACTIVE_LOW + | MAX32_GPIO_VSEL_VDDIOH)>; + label = "SW1"; + zephyr,code = ; + }; + pb2: pb2 { + gpios = <&gpio1 12 (GPIO_PULL_UP | GPIO_ACTIVE_LOW + | MAX32_GPIO_VSEL_VDDIOH)>; + label = "SW2"; + zephyr,code = ; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led1; + led1 = &led2; + sw0 = &pb1; + sw1 = &pb2; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0a_tx_p0_9 &uart0a_rx_p0_8>; + pinctrl-names = "default"; + current-speed = <115200>; + data-bits = <8>; + parity = "none"; + status = "okay"; +}; + +&clk_ipo { + status = "okay"; +}; + +&dma0 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + pinctrl-0 = <&i2c2a_scl_p0_18 &i2c2a_sda_p0_19>; + pinctrl-names = "default"; +}; + +&trng { + status = "okay"; +}; + +&spi1 { + status = "okay"; + pinctrl-0 = <&spi1a_mosi_p0_15 &spi1a_miso_p0_14 &spi1a_sck_p0_16 &spi1a_ss0_p0_17>; + pinctrl-names = "default"; +}; diff --git a/boards/adi/max32675evkit/max32675evkit.yaml b/boards/adi/max32675evkit/max32675evkit.yaml new file mode 100644 index 00000000000..b16eefcba45 --- /dev/null +++ b/boards/adi/max32675evkit/max32675evkit.yaml @@ -0,0 +1,18 @@ +identifier: max32675evkit +name: max32675evkit +vendor: adi +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - dma + - gpio + - i2c + - serial + - trng + - spi +ram: 160 +flash: 384 diff --git a/boards/adi/max32675evkit/max32675evkit_defconfig b/boards/adi/max32675evkit/max32675evkit_defconfig new file mode 100644 index 00000000000..a048ab2608f --- /dev/null +++ b/boards/adi/max32675evkit/max32675evkit_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/adi/max32680evkit/Kconfig.defconfig b/boards/adi/max32680evkit/Kconfig.defconfig new file mode 100644 index 00000000000..99702938eae --- /dev/null +++ b/boards/adi/max32680evkit/Kconfig.defconfig @@ -0,0 +1,29 @@ +# MAX32680EVKIT boards configuration + +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MAX32680EVKIT + +if DISPLAY + +config MIPI_DBI_SPI_3WIRE + default y + +if LVGL + +config LV_Z_BITS_PER_PIXEL + default 16 + +choice LV_COLOR_DEPTH + default LV_COLOR_DEPTH_16 # 16 bit per pixel +endchoice + +config LV_COLOR_16_SWAP + default y + +endif # LVGL + +endif # DISPLAY + +endif # BOARD_MAX32680EVKIT diff --git a/boards/adi/max32680evkit/Kconfig.max32680evkit b/boards/adi/max32680evkit/Kconfig.max32680evkit new file mode 100644 index 00000000000..ad5115590bd --- /dev/null +++ b/boards/adi/max32680evkit/Kconfig.max32680evkit @@ -0,0 +1,7 @@ +# MAX32680EVKIT boards configuration + +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MAX32680EVKIT + select SOC_MAX32680_M4 if BOARD_MAX32680EVKIT_MAX32680_M4 diff --git a/boards/adi/max32680evkit/board.cmake b/boards/adi/max32680evkit/board.cmake new file mode 100644 index 00000000000..bd318bb200d --- /dev/null +++ b/boards/adi/max32680evkit/board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]") +board_runner_args(openocd --cmd-pre-init "source [find target/max32680.cfg]") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/adi/max32680evkit/board.yml b/boards/adi/max32680evkit/board.yml new file mode 100644 index 00000000000..23b5102a97f --- /dev/null +++ b/boards/adi/max32680evkit/board.yml @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: max32680evkit + vendor: adi + socs: + - name: max32680 diff --git a/boards/adi/max32680evkit/doc/img/max32680evkit_img1.jpg b/boards/adi/max32680evkit/doc/img/max32680evkit_img1.jpg new file mode 100644 index 00000000000..c334dfe867e Binary files /dev/null and b/boards/adi/max32680evkit/doc/img/max32680evkit_img1.jpg differ diff --git a/boards/adi/max32680evkit/doc/index.rst b/boards/adi/max32680evkit/doc/index.rst new file mode 100644 index 00000000000..4663894d58a --- /dev/null +++ b/boards/adi/max32680evkit/doc/index.rst @@ -0,0 +1,348 @@ +.. _max32680_evkit: + +MAX32680EVKIT +############# + +Overview +******** + +The MAX32680 evaluation kit (EV kit) provides a platform +for evaluation capabilities of the MAX32680 microcontroller, +which is an advanced system-on-chip (SoC) +designed for industrial and medical sensors. Power regulation +and management is provided by a single-inductor +multiple-output (SIMO) buck regulator system and contains +the latest generation Bluetooth® 5.2 Low Energy +(LE) radio. + +The Zephyr port is running on the MAX32680 MCU. + +.. image:: img/max32680evkit_img1.jpg + :align: center + :alt: MAX32680 EVKIT + + +Hardware +******** + +- MAX32680 MCU: + + - Ultra-Low-Power Wireless Microcontroller + + - Internal 100MHz Oscillator + - 512KB Flash and 128KB SRAM, Optional ECC on One 32KB SRAM Bank + + - Bluetooth 5.2 LE Radio + + - Dedicated, Ultra-Low-Power, 32-Bit RISC-VCoprocessor to Offload + + Timing-Critical Bluetooth Processing + + - Fully Open-Source Bluetooth 5.2 Stack Available + - Supports AoA, AoD, LE Audio, and Mesh + - High-Throughput (2Mbps) Mode•Long-Range (125kbps and 500kbps) Modes + - Rx Sensitivity: -97.5dBm; Tx Power: +4.5dBm + - Single-Ended Antenna Connection (50Ω) + + - Smart Integration Reduces BOM, Cost, and PCB Size + + - Two 16-Bit to 24-Bit Sigma-Delta ADCs + - 12 Channels, Assignable to Either ADC + - Flexible Resolution and Sample Rates + - 24-Bits at 0.4ksps, 16-Bits at 4ksps + - Four External Input, 10-Bit Sigma-Delta ADC 7.8ksps + - 12-Bit DAC + - On-Die Temperature Sensor + - Digital Peripherals: Two SPI, Two I2C, up to FourUART, and up to 36 GPIOs + - Timers: Six 32-Bit Timers, Two Watchdog Timers,Two Pulse Trains, 1-Wire® Master + + - Power Management Maximizes Battery Life + + - 2.0V to 3.6V Supply Voltage Range + - Integrated SIMO Power Regulator + - Dynamic Voltage Scaling (DVS) + - 23.8μA/MHz ACTIVE Mode Current at 3.0VCoremark® + - 4.4μA at 3.0V Retention Current for 32KB SRAM + - Selectable SRAM Retention in Low-Power Modes + + - Robust Security and Reliability + + - TRNG + - Secure Nonvolatile Key Storage and AES-128/192/256 + - Secure Boot to Protect IP/Firmware + - Wide, -40°C to +85°C Operating Temperature + +- External devices connected to the MAX32680 EVKIT: + + - SMA Connector for Attaching an External Bluetooth Antenna + - 128 x 128 (1.45in) Color TFT Display with SPI Interface + - Two Selectable On-Board, High-Precision Voltage References + - USB 2.0 Micro B to Serial UARTs + - UART1 and LPUART0 Interface is Selectable Through On-Board Jumpers + - All GPIOs Signals Accessed Through 0.1in Headers + - Access to Four Analog Inputs Through SMA Connectors Configured as Differential + - Access to Eight Analog Inputs Through 0.1in Headers Configured as Single-End + - Optional Discrete Filter for the Twelve Analog Inputs + - DAC Accessed Through SMA Connector or Test Point + - 10-Pin SWD Connector + - 10-Pin RV JTAG Connector + - Board Power Provided by USB Port + - On-Board 3.3V LDO Regulator to Power MAX32680 Internal SIMO + - Test Loops Provided to Supply Optional VCORE Power Externally + - Individual Power Measurement on All IC Rails Through Jumpers + - Two General Purpose LEDs and Two General Purpose Pushbutton Switches + +Supported Features +================== + +Below interfaces are supported by Zephyr on MAX32680EVKIT. + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock and reset control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | dma controller | ++-----------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| Timer | on-chip | counter | ++-----------+------------+-------------------------------------+ + +Connections and IOs +=================== + ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| Name | Name | Settings | Description | ++===========+===============+===============+==================================================================================================+ +| JP1 | VREGI | | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects 3.3V power from the MAX32680 SIMO. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects 3.3V power to the MAX32680 SIMO. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP2 | REF0P | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-1 | | | Connects the external high-precision voltage refernce to REF0P. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects the internal voltage refernce to REF0P. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP3 | REF0N | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects REF0N from ground. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects REF0N to ground. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP4 | VDDIO_AUX | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects VDDIO_AUX from pull-ups and reference voltages. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects VDDIO_AUX to pull-ups and reference voltages. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP5 | VDDIOH | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Connects VREGO_A to VDDIOH. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects the 3.3V from the estrenal LDO to VDDIOH. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP6 | REF1P | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-1 | | | Connects the external high-precision voltage refernce to REF1P. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects the internal voltage refernce to REF1P. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP7 | REF1N | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects REF1N from ground. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects REF1N to ground. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP8 | I2C0_SDA | +-----------+ | +-------------------------------------------------------------------------------+ | +| | I2C0_SCL | | 2-1 | | | Connects I2C0 pullups to VDDIO_AUX (1.8V). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects I2C0 pullups to 3.3V. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP9 | I2C1_SDA | +-----------+ | +-------------------------------------------------------------------------------+ | +| | I2C1_SCL | | 2-1 | | | Connects I2C1 pullups to VDDIO_AUX (1.8V). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects I2C1 pullups to 3.3V. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP10 | P0_24 | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects red LED D1 from P0_24. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects red LED D1 to P0_24. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP11 | P0_25 | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects green LED D2 from P0_25. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects green LED D2 to P0_25. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP12 | FSK_IN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects FSK_IN from HART analog circuitry. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects FSK_IN to HART analog circuitry. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP13 | RCV_FSK | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects RCV_FSK from CC LOOP. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects RCV_FSK to CC LOOP. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP14 | FSK_OUT | +-----------+ | +--------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects FSK_OUT from HART analog circuitry. | | +| | | +-----------+ | +--------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects FSK_OUT to HART analog circuitry. | | +| | | +-----------+ | +--------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP15 | RCV_FSK | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects RCV_FSK from XFMR LOOP. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects RCV_FSK to XFMR LOOP. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP16 | RLOAD | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects 249 ohm resistor shunt from CC LOOP. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects 249 ohm resistor shunt to CC LOOP. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP17 | FSK AMP GAIN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Enables FSK variable amp gain. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Disables FSK variable amp gain. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP18 | AMP BYPASS | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-1 | | | Enables FSK amp. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Bypasses FSK amp. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP19 | FSK AMP GAIN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Enables FSK fixed amp gain. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Disables FSK fixed amp gain. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP20 | HART_RTS | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Enables HART_RTS optical transceiver. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Bypasses HART_RTS optical transceiver. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP21 | RLOAD | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects 249 ohm resistor shunt from XFMR LOOP. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Closed | | | Connects 249 ohm resistor shunt to XFMR LOOP. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP22 | UART0_RX | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-1 | | | Disconnects the USB - serial bridge from UART1_RX (P0.12). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects the USB - serial bridge to LPUART_RX (P2.6). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP23 | UART0_TX | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-1 | | | Disonnects the USB - serial bridge from UART1_TX (P0.13). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects the USB - serial bridge to LPUART_TX (P2.7). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP24 | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | HART_IN | | | Open | | | Disconnects TX of USB - serial bridge from HART_IN (P0.1) | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | HART_IN | | | 1-2 | | | Connects TX of USB - serial bridge to HART_IN (P0.1). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | HART_OUT | | | Open | | | Disconnects RX of USB - serial bridge from HART_OUT (P0.0). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | HART_OUT | | | 2-3 | | | Connects RX of USB - serial bridge to HART_OUT (P0.0). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | HART_RTS | | | Open | | | Disconnects RTS of USB - serial bridge from HART_RTS (P0.3). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | HART_RTS | | | 3-4 | | | Connects TX of USB - serial bridge to HART_RTS (P0.3). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | HART_OCD | | | Open | | | Disconnects RTS of USB - serial bridge from HART_OCD (P0.2). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | HART_OCD | | | 4-5 | | | Connects TX of USB - serial bridge to HART_OCD (P0.2). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP25 | RSTN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects DUT_3V3_RSTN from RSTN. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects DUT_3V3_RSTN to RSTN. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ + +Programming and Debugging +************************* + +Flashing +======== + +The MAX32680 MCU can be flashed by connecting an external debug probe to the +SWD port. SWD debug can be accessed through the Cortex 10-pin connector, JH10. +Logic levels are set to 1.8V (VDDIO_AUX). + +Once the debug probe is connected to your host computer, then you can simply run the +``west flash`` command to write a firmware image into flash. + +Debugging +========= + +Please refer to the `Flashing`_ section and run the ``west debug`` command +instead of ``west flash``. + +References +********** + +- `MAX32680EVKIT web page`_ + +.. _MAX32680EVKIT web page: + https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/max32680evkit.html#eb-overview diff --git a/boards/adi/max32680evkit/max32680evkit_max32680_m4.dts b/boards/adi/max32680evkit/max32680evkit_max32680_m4.dts new file mode 100644 index 00000000000..3e426960b0c --- /dev/null +++ b/boards/adi/max32680evkit/max32680evkit_max32680_m4.dts @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + + #include + #include + #include +#include +#include + +/ { + model = "Analog Devices MAX32680EVKIT"; + compatible = "adi,max32680evkit"; + + chosen { + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,sram = &sram2; + zephyr,flash = &flash0; + zephyr,display = &st7735; + }; + + leds { + compatible = "gpio-leds"; + led1: led_1 { + gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; + label = "Red LED"; + }; + led2: led_2 { + gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + label = "Blue LED"; + }; + }; + + buttons { + compatible = "gpio-keys"; + pb1: pb1 { + gpios = <&gpio0 26 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW1"; + zephyr,code = ; + }; + pb2: pb2 { + gpios = <&gpio0 27 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW2"; + zephyr,code = ; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led1; + led1 = &led2; + sw0 = &pb1; + sw1 = &pb2; + watchdog0 = &wdt0; + }; + + mipi_dbi { + compatible = "zephyr,mipi-dbi-spi"; + /* Enable D/C line for 4wire mode */ + /* dc-gpios = <&gpio1 7 (GPIO_ACTIVE_LOW | MAX32_GPIO_VSEL_VDDIOH)>; */ + spi-dev = <&spi0>; + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + st7735: st7735@0 { + compatible = "sitronix,st7735r"; + mipi-max-frequency = ; + mipi-mode = ; + + reg = <0>; + width = <130>; + height = <132>; + x-offset = <0>; + y-offset = <0>; + madctl = <0xc0>; + colmod = <0x05>; + vmctr1 = <0x51>; + pwctr1 = [02 02]; + pwctr2 = [c5]; + pwctr3 = [0d 00]; + pwctr4 = [8d 1a]; + pwctr5 = [8d ee]; + frmctr1 = [02 35 36]; + frmctr2 = [02 35 36]; + frmctr3 = [02 35 36 02 35 36]; + gamctrp1 = [0a 1c 0c 14 33 2b 24 28 27 25 2c 39 00 05 03 0d]; + gamctrn1 = [0a 1c 0c 14 33 2b 24 28 27 25 2d 3a 00 05 03 0d]; + }; + }; +}; + +&uart1 { + pinctrl-0 = <&uart1a_tx_p0_13 &uart1a_rx_p0_12>; + pinctrl-names = "default"; + current-speed = <115200>; + data-bits = <8>; + parity = "none"; + status = "okay"; +}; + +&clk_ipo { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&trng { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-0 = <&i2c0a_scl_p0_10 &i2c0a_sda_p0_11>; + pinctrl-names = "default"; +}; + +&i2c1 { + status = "okay"; + pinctrl-0 = <&i2c1a_scl_p0_16 &i2c1a_sda_p0_17>; + pinctrl-names = "default"; +}; + +&dma0 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + pinctrl-0 = <&spi0a_mosi_p0_5 &spi0a_miso_p0_6 &spi0a_sck_p0_7 &spi0a_ss0_p0_4>; + pinctrl-names = "default"; +}; + +&spi0a_mosi_p0_5 { + power-source=; +}; + +&spi0a_sck_p0_7 { + power-source=; +}; + +&spi0 { + status = "okay"; + pinctrl-0 = <&spi0a_mosi_p0_5 &spi0a_miso_p0_6 &spi0a_sck_p0_7>; + pinctrl-names = "default"; + cs-gpios = <&gpio0 4 (GPIO_ACTIVE_LOW | MAX32_VSEL_VDDIOH)>; +}; diff --git a/boards/adi/max32680evkit/max32680evkit_max32680_m4.yaml b/boards/adi/max32680evkit/max32680evkit_max32680_m4.yaml new file mode 100644 index 00000000000..604d3935222 --- /dev/null +++ b/boards/adi/max32680evkit/max32680evkit_max32680_m4.yaml @@ -0,0 +1,21 @@ +identifier: max32680evkit/max32680/m4 +name: max32680evkit m4 +vendor: adi +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - serial + - trng + - i2c + - dma + - watchdog + - spi + - adc + - counter +ram: 128 +flash: 512 diff --git a/boards/adi/max32680evkit/max32680evkit_max32680_m4_defconfig b/boards/adi/max32680evkit/max32680evkit_max32680_m4_defconfig new file mode 100644 index 00000000000..a048ab2608f --- /dev/null +++ b/boards/adi/max32680evkit/max32680evkit_max32680_m4_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/adi/max32690evkit/Kconfig.defconfig b/boards/adi/max32690evkit/Kconfig.defconfig new file mode 100644 index 00000000000..342cc0ca513 --- /dev/null +++ b/boards/adi/max32690evkit/Kconfig.defconfig @@ -0,0 +1,29 @@ +# MAX32690EVKIT boards configuration + +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MAX32690EVKIT + +if DISPLAY + +config MIPI_DBI_SPI_3WIRE + default y + +if LVGL + +config LV_Z_BITS_PER_PIXEL + default 16 + +choice LV_COLOR_DEPTH + default LV_COLOR_DEPTH_16 # 16 bit per pixel +endchoice + +config LV_COLOR_16_SWAP + default y + +endif # LVGL + +endif # DISPLAY + +endif # BOARD_MAX32690EVKIT diff --git a/boards/adi/max32690evkit/Kconfig.max32690evkit b/boards/adi/max32690evkit/Kconfig.max32690evkit new file mode 100644 index 00000000000..d475a30f4c8 --- /dev/null +++ b/boards/adi/max32690evkit/Kconfig.max32690evkit @@ -0,0 +1,7 @@ +# MAX32690 board configuration + +# Copyright (c) 2023-2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MAX32690EVKIT + select SOC_MAX32690_M4 if BOARD_MAX32690EVKIT_MAX32690_M4 diff --git a/boards/adi/max32690evkit/board.cmake b/boards/adi/max32690evkit/board.cmake new file mode 100644 index 00000000000..443c84cc5e8 --- /dev/null +++ b/boards/adi/max32690evkit/board.cmake @@ -0,0 +1,9 @@ +# Copyright (c) 2023-2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]") +board_runner_args(openocd --cmd-pre-init "source [find target/max32690.cfg]") +board_runner_args(jlink "--device=MAX32690" "--reset-after-load") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/adi/max32690evkit/board.yml b/boards/adi/max32690evkit/board.yml new file mode 100644 index 00000000000..53f531e193b --- /dev/null +++ b/boards/adi/max32690evkit/board.yml @@ -0,0 +1,8 @@ +# Copyright (c) 2023-2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: max32690evkit + vendor: adi + socs: + - name: max32690 diff --git a/boards/adi/max32690evkit/doc/img/max32690evkit_img1.jpg b/boards/adi/max32690evkit/doc/img/max32690evkit_img1.jpg new file mode 100644 index 00000000000..7ecfdcb3b26 Binary files /dev/null and b/boards/adi/max32690evkit/doc/img/max32690evkit_img1.jpg differ diff --git a/boards/adi/max32690evkit/doc/img/max32690evkit_img2.jpg b/boards/adi/max32690evkit/doc/img/max32690evkit_img2.jpg new file mode 100644 index 00000000000..24b665d288d Binary files /dev/null and b/boards/adi/max32690evkit/doc/img/max32690evkit_img2.jpg differ diff --git a/boards/adi/max32690evkit/doc/index.rst b/boards/adi/max32690evkit/doc/index.rst new file mode 100644 index 00000000000..5f4fe41e158 --- /dev/null +++ b/boards/adi/max32690evkit/doc/index.rst @@ -0,0 +1,306 @@ +.. _max32690_evkit: + +MAX32690EVKIT +############# + +Overview +******** +The MAX32690 evaluation kit (EV kit) provides a platform for evaluating the capabilities +of the MAX32690 microcontroller, which is an advanced system-on-chip (SoC). +It features an Arm® Cortex®-M4F CPU for efficient computation of complex functions and +algorithms, and the latest generation Bluetooth® 5 Low Energy (Bluetooth LE) radio designed +for wearable and hearable fitness devices, portable and wearable wireless medical devices, +industrial sensors/networks, internet of things (IoT), and asset tracking. + +The Zephyr port is running on the MAX32690 MCU. + +.. image:: img/max32690evkit_img1.jpg + :align: center + :alt: MAX32690 EVKIT Front + +.. image:: img/max32690evkit_img2.jpg + :align: center + :alt: MAX32690 Back + +Hardware +******** + +- MAX32690 MCU: + + - Ultra-Efficient Microcontroller for Battery-Powered Applications + + - 120MHz Arm Cortex-M4 Processor with FPU + - 7.3728MHz and 60MHz Low-Power Oscillators + - External Crystal Support (32MHz required for BLE) + - 32.768kHz RTC Clock (Requires External Crystal) + - 8kHz Always-On Ultra-Low Power Oscillator + - 3MB Internal Flash, 1MB Internal SRAM (832kB ECC ON) + - TBDμW/MHz Executing from Cache at 1.1V + - 1.8V and 3.3V I/O with No Level Translators + - External Flash & SRAM Expansion Interfaces + + - Bluetooth 5.2 LE Radio + + - Dedicated, Ultra-Low-Power, 32-Bit RISC-V Coprocessor to Offload Timing-Critical Bluetooth Processing + - Fully Open-Source Bluetooth 5.2 Stack Available + - Supports AoA, AoD, LE Audio, and Mesh + - High-Throughput (2Mbps) Mode + - Long-Range (125kbps and 500kbps) Modes + - Rx Sensitivity: -97.5dBm; Tx Power: +4.5dBm + - Single-Ended Antenna Connection (50Ω) + + - Multiple Peripherals for System Control + + - 16-Channel DMA + - Up To Five Quad SPI Master (60MHz)/Slave (48MHz) + - Up To Four 1Mbaud UARTs with Flow Control + - Up To Two 1MHz I2C Master/Slave + - I2S Master/Slave + - Eight External Channel, 12-bit 1MSPS SAR ADC w/ on-die temperature sensor + - USB 2.0 Hi-Speed Device + - 16 Pulse Train Engines + - Up To Six 32-Bit Timers with 8mA High Drive + - Up To Two CAN 2.0 Controllers + - Up To Four Micro-Power Comparators + - 1-Wire Master + + - Security and Integrity​ + + - ChipDNA Physically Un-clonable Function (PUF) + - Modular Arithmetic Accelerator (MAA), True Random Number Generator (TRNG) + - Secure Nonvolatile Key Storage, SHA-256, AES-128/192/256 + - Secure Boot ROM + +- External devices connected to the MAX32690EVKIT: + + - Bluetooth SMA Connector with a Hinged 2.4GHz Whip Antenna + - 3-Pin Terminal Block for CAN Bus 2.0 + - Selectable On-Board High-Precision Voltage Reference + - On-Board HyperRAM + - Stereo Audio Codec with Line-In and Line-Out 3.5mm Jacks + - 128 x 128 (1.45in) Color TFT Display + - USB 2.0 Micro-B Interface to the MAX32690 + - USB 2.0 Micro-B to Serial UART + - Board Power Provided by either USB Port + - Jumpers to Enable Optional Pull-Up Resistors on I2C port + - All GPIOs Signals Accessed through 0.1in Headers + - Three Analog Inputs Accessed through 0.1in Headers with Optional Filtering + - SWD 10-Pin Header + - On-Board 3.3V, 1.8V, and 1.1V LDO Regulators + - Individual Power Measurement on All IC Rails through Jumpers + - Two General-Purpose LEDs and One GeneralPurpose Push Button Switch + + +Supported Features +================== + +Below interfaces are supported by Zephyr on MAX32690EVKIT. + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock and reset control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++--------------------------------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | dma controller | ++-----------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| Timer | on-chip | counter | ++-----------+------------+-------------------------------------+ + + +Connections and IOs +=================== + ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| Name | Name | Settings | Description | ++===========+===============+===============+==================================================================================================+ +| JP1 | VREF | | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects external voltage reference to VREF pin, must be enabled in software. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects external voltage reference. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP2 | I2C0 PU | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-1 | | | Connects VDDIO (1V8) to I2C0 pull-up resistors. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects VDDIOH (3V3) to I2C0 pull-up resistors. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from I2C0 pull-up resistors. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP3 | I2C0_SDA_PU | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects pull-up to I2C0A_SDA (P2.7) sourced by I2C0 PU (JP2). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects pull-up from I2C0A_SDA (P2.7) sourced by I2C0 PU (JP2). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP4 | I2C0_SCL_PU | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects pull-up to I2C0A_SCL (P2.8) sourced by I2C0 PU (JP2). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects pull-up from I2C0A_SCL (P2.8) sourced by I2C0 PU (JP2). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP5 | LED0 EN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects red LED D1 to P0.14. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects red LED D1 from P0.14. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP6 | LED1 EN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects green LED D2 to P2.12. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects green LED D2 from P2.12. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP7 | RX EN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects the USB - serial bridge to UART2A_RX (P1.9). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects the USB - serial bridge from UART2A_RX (P1.9). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP8 | TX EN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects the USB - serial bridge to UART2A_TX (P1.10). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects the USB - serial bridge from UART2A_TX (P1.10). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP9 | P1_7 SEL | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-1 | | | Connects the USB - serial bridge to UART2A_CTS (P1.7). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects I2C2C_SDA (P1.7) to the codec. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP10 | P1_8 SEL | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-1 | | | Connects the USB - serial bridge to UART2A_RTS (P1.8). | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects I2C2C_SCL (P1.8) to the codec. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP11 | V_AUX SEL | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-1 | | | Connects V_AUX to 1V8. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects V_AUX to 3V3. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP12 | VDD3A EN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects 3V3 to VDD3A. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects 3V3 from VDD3A. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP13 | VDDIOH EN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects 3V3 to VDDIOH. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects 3V3 from VDDIOH. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP14 | VDDB EN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects a 3V3 LDO sourced by USB_VBUS (CN1) to VDDB. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects a 3V3 LDO sourced by USB_VBUS (CN1) from VDDB. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP15 | VDDA EN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects 1V8 to VDDA. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects 1V8 from VDDA. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP16 | VDDIO EN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects 1V8 to VDDIO. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects 1V8 from VDDIO. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP17 | VCORE EN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects 1V1 to VCORE. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects 1V1 from VCORE. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP18 | BLE LDO EN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects 1V4 to BLE_LDO. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects 1V4 from BLE_LDO. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JH6 | ANALOG PORT3 | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects LPUART0B_RX (P3.0) to the SWD connector. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 3-4 | | | Connects LPUART0B_TX (P3.1) to the SWD connector. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects LPUART0B_RX (P3.0) and LPUART0B_TX (P3.1) from the SWD connector. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ + +Programming and Debugging +************************* + +Flashing +======== + +The MAX32690 MCU can be flashed by connecting an external debug probe to the +SWD port. SWD debug can be accessed through the Cortex 10-pin connector, J3. +Logic levels are fixed to VDDIO (1.8V). + +Once the debug probe is connected to your host computer, then you can simply run the +``west flash`` command to write a firmware image into flash. + +.. note:: + + This board uses OpenOCD as the default debug interface. You can also use + a Segger J-Link with Segger's native tooling by overriding the runner, + appending ``--runner jlink`` to your ``west`` command(s). The J-Link should + be connected to the standard 2*5 pin debug connector (JW3) using an + appropriate adapter board and cable. + +Debugging +========= + +Please refer to the `Flashing`_ section and run the ``west debug`` command +instead of ``west flash``. + +References +********** + +- `MAX32690EVKIT web page`_ + +.. _MAX32690EVKIT web page: + https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/MAX32690EVKIT.html diff --git a/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts b/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts new file mode 100644 index 00000000000..85b9d251e07 --- /dev/null +++ b/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts @@ -0,0 +1,160 @@ +/* + * Copyright (c) 2023-2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include + +/ { + model = "Analog Devices MAX32690EVKIT"; + compatible = "adi,max32690evkit"; + + chosen { + zephyr,console = &uart2; + zephyr,shell-uart = &uart2; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,display = &st7735; + }; + + leds { + compatible = "gpio-leds"; + red_led: led_0 { + gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + label = "LED0"; + }; + green_led: led_1 { + gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + label = "LED1"; + }; + }; + + buttons { + compatible = "gpio-keys"; + pb0: pb0 { + gpios = <&gpio4 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW2"; + zephyr,code = ; + }; + }; + + aliases { + led0 = &red_led; + led1 = &green_led; + sw0 = &pb0; + watchdog0 = &wdt0; + }; + + mipi_dbi { + compatible = "zephyr,mipi-dbi-spi"; + spi-dev = <&spibb0>; + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + st7735: st7735@0 { + compatible = "sitronix,st7735r"; + mipi-max-frequency = ; + mipi-mode = ; + + reg = <0>; + width = <130>; + height = <132>; + x-offset = <0>; + y-offset = <0>; + madctl = <0xc0>; + colmod = <0x05>; + vmctr1 = <0x51>; + pwctr1 = [02 02]; + pwctr2 = [c5]; + pwctr3 = [0d 00]; + pwctr4 = [8d 1a]; + pwctr5 = [8d ee]; + frmctr1 = [02 35 36]; + frmctr2 = [02 35 36]; + frmctr3 = [02 35 36 02 35 36]; + gamctrp1 = [0a 1c 0c 14 33 2b 24 28 27 25 2c 39 00 05 03 0d]; + gamctrn1 = [0a 1c 0c 14 33 2b 24 28 27 25 2d 3a 00 05 03 0d]; + }; + }; + + spibb0: spibb0 { + compatible = "zephyr,spi-bitbang"; + status="okay"; + #address-cells = <1>; + #size-cells = <0>; + clk-gpios = <&gpio2 25 (GPIO_ACTIVE_HIGH | MAX32_GPIO_VSEL_VDDIOH)>; + mosi-gpios = <&gpio2 24 (GPIO_ACTIVE_HIGH | MAX32_GPIO_VSEL_VDDIOH)>; + cs-gpios = <&gpio2 11 (GPIO_ACTIVE_LOW | MAX32_GPIO_VSEL_VDDIOH)>; + }; +}; + +&clk_ipo { + status = "okay"; +}; + +&clk_ibro { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&uart2 { + clock-source = ; + pinctrl-0 = <&uart2a_tx_p1_10 &uart2a_rx_p1_9>; + pinctrl-names = "default"; + current-speed = <115200>; + data-bits = <8>; + parity = "none"; + status = "okay"; +}; + +&trng { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-0 = <&i2c0a_scl_p2_8 &i2c0a_sda_p2_7>; + pinctrl-names = "default"; +}; + +&dma0 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + pinctrl-0 = <&spi0b_mosi_p2_28 &spi0b_miso_p2_27 &spi0b_sck_p2_29 &spi0b_ss1_p2_26>; + pinctrl-names = "default"; +}; diff --git a/boards/adi/max32690evkit/max32690evkit_max32690_m4.yaml b/boards/adi/max32690evkit/max32690evkit_max32690_m4.yaml new file mode 100644 index 00000000000..bd7e017dd30 --- /dev/null +++ b/boards/adi/max32690evkit/max32690evkit_max32690_m4.yaml @@ -0,0 +1,21 @@ +identifier: max32690evkit/max32690/m4 +name: max32690evkit m4 +vendor: adi +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - serial + - spi + - i2c + - trng + - dma + - watchdog + - adc + - counter +ram: 1024 +flash: 3072 diff --git a/boards/adi/max32690evkit/max32690evkit_max32690_m4_defconfig b/boards/adi/max32690evkit/max32690evkit_max32690_m4_defconfig new file mode 100644 index 00000000000..4fa0a464106 --- /dev/null +++ b/boards/adi/max32690evkit/max32690evkit_max32690_m4_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2023-2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/adi/max32690fthr/Kconfig.max32690fthr b/boards/adi/max32690fthr/Kconfig.max32690fthr new file mode 100644 index 00000000000..95bc3a9904a --- /dev/null +++ b/boards/adi/max32690fthr/Kconfig.max32690fthr @@ -0,0 +1,7 @@ +# MAX32690 board configuration + +# Copyright (c) 2023-2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MAX32690FTHR + select SOC_MAX32690_M4 if BOARD_MAX32690FTHR_MAX32690_M4 diff --git a/boards/adi/max32690fthr/board.cmake b/boards/adi/max32690fthr/board.cmake new file mode 100644 index 00000000000..443c84cc5e8 --- /dev/null +++ b/boards/adi/max32690fthr/board.cmake @@ -0,0 +1,9 @@ +# Copyright (c) 2023-2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]") +board_runner_args(openocd --cmd-pre-init "source [find target/max32690.cfg]") +board_runner_args(jlink "--device=MAX32690" "--reset-after-load") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/adi/max32690fthr/board.yml b/boards/adi/max32690fthr/board.yml new file mode 100644 index 00000000000..328035bdccd --- /dev/null +++ b/boards/adi/max32690fthr/board.yml @@ -0,0 +1,8 @@ +# Copyright (c) 2023-2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: max32690fthr + vendor: adi + socs: + - name: max32690 diff --git a/boards/adi/max32690fthr/doc/index.rst b/boards/adi/max32690fthr/doc/index.rst new file mode 100644 index 00000000000..edb480f3898 --- /dev/null +++ b/boards/adi/max32690fthr/doc/index.rst @@ -0,0 +1,134 @@ +.. _max32690_fthr: + +MAX32690FTHR +############ + +Overview +******** + +The MAX32690FTHR is a rapid development platform to help engineers quickly +implement ultra low-power wireless solutions using MAX32690 Arm© Cortex®-M4F +and Bluetooth® 5.2 Low Energy (LE). The board also includes the MAX77654 PMIC +for battery and power management. The form factor is a small 0.9in x 2.6in +dual-row header footprint that is compatible with Adafruit Feather Wing +peripheral expansion boards. + +Hardware +******** + +- MAX32690 MCU: + + - Ultra-Efficient Microcontroller for Battery-Powered Applications + + - 120MHz Arm Cortex-M4 Processor with FPU + - 7.3728MHz and 60MHz Low-Power Oscillators + - External Crystal Support (32MHz required for BLE) + - 32.768kHz RTC Clock (Requires External Crystal) + - 8kHz Always-On Ultra-Low Power Oscillator + - 3MB Internal Flash, 1MB Internal SRAM (832kB ECC ON) + - 85 μW/MHz ACTIVE mode at 1.1V + - 1.8V and 3.3V I/O with No Level Translators + - External Flash & SRAM Expansion Interfaces + + - Bluetooth 5.2 LE Radio + + - Dedicated, Ultra-Low-Power, 32-Bit RISC-V Coprocessor to Offload + Timing-Critical Bluetooth Processing + - Fully Open-Source Bluetooth 5.2 Stack Available + - Supports AoA, AoD, LE Audio, and Mesh + - High-Throughput (2Mbps) Mode + - Long-Range (125kbps and 500kbps) Modes + - Rx Sensitivity: -97.5dBm; Tx Power: +4.5dBm + - Single-Ended Antenna Connection (50Ω) + + - Multiple Peripherals for System Control + + - 16-Channel DMA + - Up To Five Quad SPI Master (60MHz)/Slave (48MHz) + - Up To Four 1Mbaud UARTs with Flow Control + - Up To Two 1MHz I2C Master/Slave + - I2S Master/Slave + - Eight External Channel, 12-bit 1MSPS SAR ADC w/ on-die temperature sensor + - USB 2.0 Hi-Speed Device + - 16 Pulse Train Engines + - Up To Six 32-Bit Timers with 8mA High Drive + - Up To Two CAN 2.0 Controllers + - Up To Four Micro-Power Comparators + - 1-Wire Master + + - Security and Integrity​ + + - ChipDNA Physically Un-clonable Function (PUF) + - Modular Arithmetic Accelerator (MAA), True Random Number Generator (TRNG) + - Secure Nonvolatile Key Storage, SHA-256, AES-128/192/256 + - Secure Boot ROM + +Supported Features +================== + +Below interfaces are supported by Zephyr on MAX32690FTHR. + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock and reset control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++--------------------------------------------------------------+ + +Programming and Debugging +************************* + +Flashing +======== + +The MAX32690 MCU can be flashed by connecting an external debug probe to the +SWD port. SWD debug can be accessed through the Cortex 10-pin connector, J4. +Logic levels are fixed to VDDIO (1.8V). + +Once the debug probe is connected to your host computer, then you can run the +``west flash`` command to write a firmware image into flash. Here is an example +for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: max32690fthr/max32690/m4 + :goals: flash + +.. note:: + + This board uses OpenOCD as the default debug interface. You can also use a + Segger J-Link with Segger's native tooling by overriding the runner, + appending ``--runner jlink`` to your ``west`` command(s). The J-Link should + be connected to the standard 2*5 pin debug connector (J4) using an + appropriate adapter board and cable. + +Debugging +========= + +Once the debug probe is connected to your host computer, then you can run the +``west debug`` command to write a firmware image into flash and start a debug +session. Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: max32690fthr/max32690/m4 + :goals: debug + +References +********** + +- `MAX32690 product page`_ + +.. _MAX32690 product page: + https://www.analog.com/en/products/max32690.html diff --git a/boards/adi/max32690fthr/max32690fthr_max32690_m4.dts b/boards/adi/max32690fthr/max32690fthr_max32690_m4.dts new file mode 100644 index 00000000000..0ee5bb85f96 --- /dev/null +++ b/boards/adi/max32690fthr/max32690fthr_max32690_m4.dts @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2023-2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include + +/ { + model = "Analog Devices MAX32690FTHR"; + compatible = "adi,max32690fthr"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + leds { + compatible = "gpio-leds"; + red_led: led_0 { + gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + label = "LED0"; + }; + green_led: led_1 { + gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; + label = "LED1"; + }; + blue_led: led_2 { + gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; + label = "LED2"; + }; + }; + + buttons { + compatible = "gpio-keys"; + pb1: pb1 { + gpios = <&gpio1 14 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW3"; + zephyr,code = ; + }; + pb2: pb2 { + gpios = <&gpio1 15 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW4"; + zephyr,code = ; + }; + }; + + aliases { + led0 = &red_led; + led1 = &green_led; + led2 = &blue_led; + sw0 = &pb1; + sw1 = &pb2; + }; + + feather_header: feather_connector { + compatible = "adafruit-feather-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio3 0 0>, /* A0 */ + <1 0 &gpio3 1 0>, /* A1 */ + <2 0 &gpio3 4 0>, /* A2 */ + <3 0 &gpio0 9 0>, /* A3 */ + <4 0 &gpio0 10 0>, /* A4 */ + <5 0 &gpio0 7 0>, /* A5 */ + <6 0 &gpio2 29 0>, /* SCK */ + <7 0 &gpio2 28 0>, /* MOSI */ + <8 0 &gpio2 27 0>, /* MISO */ + <9 0 &gpio1 9 0>, /* RXD */ + <10 0 &gpio1 10 0>, /* TXD */ + /* 11 (D2) not connected */ + <12 0 &gpio2 7 0>, /* SDA */ + <13 0 &gpio2 8 0>, /* SCL */ + <14 0 &gpio1 7 0>, /* D5 */ + <15 0 &gpio1 8 0>, /* D6 */ + <16 0 &gpio2 26 0>, /* D9 */ + <17 0 &gpio0 23 0>, /* D10 */ + <18 0 &gpio1 12 0>, /* D11 */ + <19 0 &gpio1 11 0>, /* D12 */ + <20 0 &gpio0 8 0>; /* D13 */ + }; +}; + +&clk_ibro { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&uart0 { + clock-source = ; + pinctrl-0 = <&uart0a_tx_p2_12 &uart0a_rx_p2_11>; + pinctrl-names = "default"; + current-speed = <115200>; + data-bits = <8>; + parity = "none"; + status = "okay"; +}; + +feather_serial: &uart2 { + clock-source = ; + pinctrl-0 = <&uart2a_tx_p1_10 &uart2a_rx_p1_9>; + pinctrl-names = "default"; + current-speed = <115200>; + data-bits = <8>; + parity = "none"; + status = "okay"; +}; + +feather_i2c: &i2c0 { + status = "okay"; + pinctrl-0 = <&i2c0a_scl_p2_8 &i2c0a_sda_p2_7>; + pinctrl-names = "default"; +}; + +feather_spi: &spi0 { + status = "okay"; + pinctrl-0 = <&spi0b_mosi_p2_28 &spi0b_miso_p2_27 &spi0b_sck_p2_29>; + pinctrl-names = "default"; +}; diff --git a/boards/adi/max32690fthr/max32690fthr_max32690_m4.yaml b/boards/adi/max32690fthr/max32690fthr_max32690_m4.yaml new file mode 100644 index 00000000000..bbf1af6853f --- /dev/null +++ b/boards/adi/max32690fthr/max32690fthr_max32690_m4.yaml @@ -0,0 +1,19 @@ +identifier: max32690fthr/max32690/m4 +name: max32690fthr m4 +vendor: adi +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - serial + - i2c + - spi + - feather_serial + - feather_i2c + - feather_spi +ram: 1024 +flash: 3072 diff --git a/boards/adi/max32690fthr/max32690fthr_max32690_m4_defconfig b/boards/adi/max32690fthr/max32690fthr_max32690_m4_defconfig new file mode 100644 index 00000000000..4fa0a464106 --- /dev/null +++ b/boards/adi/max32690fthr/max32690fthr_max32690_m4_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2023-2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/adi/sdp_k1/adi_sdp_k1_defconfig b/boards/adi/sdp_k1/adi_sdp_k1_defconfig index c729b83e3d0..51eadcb4809 100644 --- a/boards/adi/sdp_k1/adi_sdp_k1_defconfig +++ b/boards/adi/sdp_k1/adi_sdp_k1_defconfig @@ -14,9 +14,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/adi/sdp_k1/doc/index.rst b/boards/adi/sdp_k1/doc/index.rst index 1f6f918e0a6..0b23797da6b 100644 --- a/boards/adi/sdp_k1/doc/index.rst +++ b/boards/adi/sdp_k1/doc/index.rst @@ -151,7 +151,7 @@ Run a serial host program to connect with your board: $ minicom -D /dev/serial/by-id/usb-ARM_DAPLink_CMSIS-DAP_<...> -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/alientek/pandora_stm32l475/doc/index.rst b/boards/alientek/pandora_stm32l475/doc/index.rst index cee292e1e56..082c814914a 100644 --- a/boards/alientek/pandora_stm32l475/doc/index.rst +++ b/boards/alientek/pandora_stm32l475/doc/index.rst @@ -182,7 +182,7 @@ board. For example: $ minicom -D /dev/ttyACM0 Then, build and flash in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -199,7 +199,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/alientek/pandora_stm32l475/pandora_stm32l475.dts b/boards/alientek/pandora_stm32l475/pandora_stm32l475.dts index 1c28f6c8176..567e88a0152 100644 --- a/boards/alientek/pandora_stm32l475/pandora_stm32l475.dts +++ b/boards/alientek/pandora_stm32l475/pandora_stm32l475.dts @@ -27,8 +27,6 @@ zephyr,shell-uart = &usart1; zephyr,sram = &sram0; zephyr,flash = &flash0; - - spi-flash0 = &w25q128jv; }; leds { diff --git a/boards/alientek/pandora_stm32l475/pandora_stm32l475_defconfig b/boards/alientek/pandora_stm32l475/pandora_stm32l475_defconfig index 82ee7285d52..3fe5e4f9882 100644 --- a/boards/alientek/pandora_stm32l475/pandora_stm32l475_defconfig +++ b/boards/alientek/pandora_stm32l475/pandora_stm32l475_defconfig @@ -12,12 +12,6 @@ CONFIG_SERIAL=y # enable GPIO CONFIG_GPIO=y -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - # console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/altr/max10/doc/index.rst b/boards/altr/max10/doc/index.rst index ca66d77a0a7..0ff861b4f83 100644 --- a/boards/altr/max10/doc/index.rst +++ b/boards/altr/max10/doc/index.rst @@ -147,7 +147,7 @@ Flashing Kernel into UFM ------------------------ The usual ``flash`` target will work with the ``altera_max10`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -172,7 +172,7 @@ directly into RAM and then boot it from the __start symbol. In order for this to work, your entire kernel must be located in RAM. Make sure the following config options are disabled: -.. code-block:: console +.. code-block:: cfg CONFIG_XIP=n CONFIG_INCLUDE_RESET_VECTOR=n @@ -265,7 +265,7 @@ In order for this to work, execute-in-place must be disabled, since the GDB 'load' command can only put text and data in RAM. Ensure this is in your configuration: -.. code-block:: console +.. code-block:: cfg CONFIG_XIP=n diff --git a/boards/ambiq/apollo3_evb/apollo3_evb-pinctrl.dtsi b/boards/ambiq/apollo3_evb/apollo3_evb-pinctrl.dtsi index cfba01ba4de..7fbd368813b 100644 --- a/boards/ambiq/apollo3_evb/apollo3_evb-pinctrl.dtsi +++ b/boards/ambiq/apollo3_evb/apollo3_evb-pinctrl.dtsi @@ -5,6 +5,7 @@ */ #include +#include "apollo3_evb_connector.dtsi" &pinctrl { uart0_default: uart0_default { @@ -69,66 +70,37 @@ group1 { pinmux = , , ; }; - group2 { - pinmux = ; - drive-push-pull; - ambiq,iom-nce-module = <0>; - ambiq,iom-num = <0>; - }; }; spi1_default: spi1_default { group1 { pinmux = , , ; }; - group2 { - pinmux = ; - drive-push-pull; - ambiq,iom-nce-module = <1>; - ambiq,iom-num = <1>; - }; }; spi2_default: spi2_default { group1 { pinmux = , , ; }; - group2 { - pinmux = ; - drive-push-pull; - ambiq,iom-nce-module = <3>; - ambiq,iom-num = <2>; - }; }; spi3_default: spi3_default { group1 { pinmux = , , ; }; - group2 { - pinmux = ; - drive-push-pull; - ambiq,iom-nce-module = <0>; - ambiq,iom-num = <3>; - }; }; spi4_default: spi4_default { group1 { pinmux = , , ; }; - group2 { - pinmux = ; - drive-push-pull; - ambiq,iom-nce-module = <1>; - ambiq,iom-num = <4>; - }; }; spi5_default: spi5_default { group1 { pinmux = , , ; }; - group2 { - pinmux = ; - drive-push-pull; - ambiq,iom-nce-module = <0>; - ambiq,iom-num = <5>; + }; + + adc0_default: adc0_default{ + group1 { + pinmux = , ; + drive-strength = "0.1"; }; }; @@ -148,4 +120,15 @@ ambiq,iom-num = <6>; }; }; + + bleif_default: bleif_default{ + group1 { + pinmux = , + , + , + , + , + ; + }; + }; }; diff --git a/boards/ambiq/apollo3_evb/apollo3_evb.dts b/boards/ambiq/apollo3_evb/apollo3_evb.dts index 9f1cac0b309..a47b97f1696 100644 --- a/boards/ambiq/apollo3_evb/apollo3_evb.dts +++ b/boards/ambiq/apollo3_evb/apollo3_evb.dts @@ -15,6 +15,7 @@ zephyr,shell-uart = &uart0; zephyr,uart-pipe = &uart0; zephyr,flash-controller = &flash; + zephyr,bt_hci = &bt_hci_apollo; }; aliases { @@ -84,6 +85,12 @@ }; }; +&bleif { + pinctrl-0 = <&bleif_default>; + pinctrl-names = "default"; + status = "okay"; +}; + &uart0 { current-speed = <115200>; pinctrl-0 = <&uart0_default>; @@ -95,6 +102,15 @@ status = "okay"; }; +&spi0 { + compatible = "ambiq,spi"; + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; + cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>; + clock-frequency = ; + status = "okay"; +}; + &i2c3 { compatible = "ambiq,i2c"; pinctrl-0 = <&i2c3_default>; @@ -103,6 +119,45 @@ status = "okay"; }; +&counter0 { + status = "okay"; +}; + +&counter1 { + status = "okay"; +}; + +&counter2 { + status = "okay"; +}; + +&counter3 { + status = "okay"; +}; + +&counter4 { + status = "okay"; +}; + +&counter5 { + status = "okay"; +}; + +&counter6 { + status = "okay"; +}; + +&counter7 { + status = "okay"; +}; + +&adc0 { + compatible = "ambiq,adc"; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + &gpio0_31 { status = "okay"; }; diff --git a/boards/ambiq/apollo3_evb/apollo3_evb.yaml b/boards/ambiq/apollo3_evb/apollo3_evb.yaml index f55c135f1d4..048f2ed0a72 100644 --- a/boards/ambiq/apollo3_evb/apollo3_evb.yaml +++ b/boards/ambiq/apollo3_evb/apollo3_evb.yaml @@ -9,8 +9,11 @@ toolchain: - gnuarmemb supported: - uart + - adc - watchdog + - counter - gpio + - spi - i2c testing: ignore_tags: diff --git a/boards/ambiq/apollo3_evb/apollo3_evb_connector.dtsi b/boards/ambiq/apollo3_evb/apollo3_evb_connector.dtsi new file mode 100644 index 00000000000..77e22c5bbb5 --- /dev/null +++ b/boards/ambiq/apollo3_evb/apollo3_evb_connector.dtsi @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2024 Ambiq + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + ambiq_header: connector { + compatible = "ambiq-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffff80>; + gpio-map-pass-thru = <0 0x7f>; + gpio-map = <0 0 &gpio0_31 0 0>, /* IOS_SPI_SCK, IOS_I2C_SCL */ + <1 0 &gpio0_31 1 0>, /* IOS_SPI_MOSI, IOS_I2C_SDA */ + <2 0 &gpio0_31 2 0>, /* IOS_SPI_MISO */ + <3 0 &gpio0_31 3 0>, /* IOS_CE */ + <4 0 &gpio0_31 4 0>, /* IOS_INT */ + <5 0 &gpio0_31 5 0>, /* IOM0_SPI_SCK, IOM0_I2C_SCL */ + <6 0 &gpio0_31 6 0>, /* IOM0_SPI_MISO, IOM0_I2C_SDA */ + <7 0 &gpio0_31 7 0>, /* IOM0_SPI_MOSI */ + <8 0 &gpio0_31 8 0>, /* IOM1_SPI_SCK, IOM1_I2C_SCL */ + <9 0 &gpio0_31 9 0>, /* IOM1_SPI_MISO, IOM1_I2C_SDA */ + <10 0 &gpio0_31 10 0>, /* LED0, IOM1_SPI_MOSI */ + <11 0 &gpio0_31 11 0>, /* DISP_RESET */ + <12 0 &gpio0_31 12 0>, /* MSPI0_CE0 */ + <13 0 &gpio0_31 13 0>, /* IOM0_CS */ + <14 0 &gpio0_31 14 0>, /* LED3 */ + <15 0 &gpio0_31 15 0>, /* LED2 */ + <16 0 &gpio0_31 16 0>, /* BUTTON0 */ + <17 0 &gpio0_31 17 0>, /* LED4 */ + <18 0 &gpio0_31 18 0>, /* BUTTON1 */ + <19 0 &gpio0_31 19 0>, /* BUTTON2 */ + <20 0 &gpio0_31 20 0>, /* SWDCK */ + <21 0 &gpio0_31 21 0>, /* SWDIO */ + <22 0 &gpio0_31 22 0>, /* MSPI0_D0, UART0_TX */ + <23 0 &gpio0_31 23 0>, /* MSPI0_D3, UART0_RX */ + <24 0 &gpio0_31 24 0>, /* MSPI0_SCK */ + <25 0 &gpio0_31 25 0>, /* IOM2_MISO_SCK, IOM2_I2C_SDA */ + <26 0 &gpio0_31 26 0>, /* MSPI0_D1 */ + <27 0 &gpio0_31 27 0>, /* IOM2_SPI_SCK, IOM2_I2C_SCL*/ + <28 0 &gpio0_31 28 0>, /* MSPI0_CE0 */ + <29 0 &gpio0_31 29 0>, /* IOM3_CS */ + <30 0 &gpio0_31 30 0>, /* LED1 */ + <31 0 &gpio0_31 31 0>, /* DISP_3V3_EN */ + <32 0 &gpio32_63 0 0>, /* BLEIF_MOSI */ + <33 0 &gpio32_63 1 0>, /* BLEIF_CSN */ + <34 0 &gpio32_63 2 0>, /* IOM1_CS */ + <35 0 &gpio32_63 3 0>, /* BLEIF_STATUS */ + <36 0 &gpio32_63 4 0>, /* PDM_DATA */ + <37 0 &gpio32_63 5 0>, /* PDM_CLK */ + <38 0 &gpio32_63 6 0>, /* DISP_TE */ + <39 0 &gpio32_63 7 0>, /* DISP_PWR_EN */ + <40 0 &gpio32_63 8 0>, /* IOM4_SPI_MISO, IOM4_I2C_SDA */ + <41 0 &gpio32_63 9 0>, /* SWO */ + <42 0 &gpio32_63 10 0>, /* IOM3_I2C_SCL */ + <43 0 &gpio32_63 11 0>, /* IOM3_I2C_SDA */ + <44 0 &gpio32_63 12 0>, /* IOM4_SPI_MOSI */ + <45 0 &gpio32_63 13 0>, /* DISP_2V8_EN */ + <46 0 &gpio32_63 14 0>, /* ACC_INT */ + <47 0 &gpio32_63 15 0>, /* IOM5_SPI_MOSI */ + <48 0 &gpio32_63 16 0>, /* IOM5_I2C_SCL */ + <49 0 &gpio32_63 17 0>; /* IOM5_I2C_SDA */ + }; +}; + +ambiq_spi0: &spi0 {}; +ambiq_i2c3: &i2c3 {}; diff --git a/boards/ambiq/apollo3_evb/doc/index.rst b/boards/ambiq/apollo3_evb/doc/index.rst index 12990d0c9fe..570e1d54d45 100644 --- a/boards/ambiq/apollo3_evb/doc/index.rst +++ b/boards/ambiq/apollo3_evb/doc/index.rst @@ -60,7 +60,7 @@ Flashing an application ----------------------- Connect your device to your host computer using the JLINK USB port. -The sample application :ref:`hello_world` is used for this example. +The sample application :zephyr:code-sample:`hello_world` is used for this example. Build the Zephyr kernel and application, then flash it to the device: .. zephyr-app-commands:: @@ -69,7 +69,7 @@ Build the Zephyr kernel and application, then flash it to the device: :goals: flash .. note:: - `west flash` requires `SEGGER J-Link software`_ and `pylink`_ Python module + ``west flash`` requires `SEGGER J-Link software`_ and `pylink`_ Python module to be installed on you host computer. Open a serial terminal (minicom, putty, etc.) with the following settings: diff --git a/boards/ambiq/apollo3p_evb/apollo3p_evb-pinctrl.dtsi b/boards/ambiq/apollo3p_evb/apollo3p_evb-pinctrl.dtsi index 5619b134ee9..b026ba7722f 100644 --- a/boards/ambiq/apollo3p_evb/apollo3p_evb-pinctrl.dtsi +++ b/boards/ambiq/apollo3p_evb/apollo3p_evb-pinctrl.dtsi @@ -5,6 +5,7 @@ */ #include +#include "apollo3p_evb_connector.dtsi" &pinctrl { uart0_default: uart0_default { @@ -69,72 +70,37 @@ group1 { pinmux = , , ; }; - group2 { - pinmux = ; - drive-push-pull; - ambiq,iom-mspi = <1>; - ambiq,iom-nce-module = <0>; - ambiq,iom-num = <0>; - }; }; spi1_default: spi1_default { group1 { pinmux = , , ; }; - group2 { - pinmux = ; - drive-push-pull; - ambiq,iom-mspi = <1>; - ambiq,iom-nce-module = <1>; - ambiq,iom-num = <1>; - }; }; spi2_default: spi2_default { group1 { pinmux = , , ; }; - group2 { - pinmux = ; - drive-push-pull; - ambiq,iom-mspi = <1>; - ambiq,iom-nce-module = <3>; - ambiq,iom-num = <2>; - }; }; spi3_default: spi3_default { group1 { pinmux = , , ; }; - group2 { - pinmux = ; - drive-push-pull; - ambiq,iom-mspi = <1>; - ambiq,iom-nce-module = <0>; - ambiq,iom-num = <3>; - }; }; spi4_default: spi4_default { group1 { pinmux = , , ; }; - group2 { - pinmux = ; - drive-push-pull; - ambiq,iom-mspi = <1>; - ambiq,iom-nce-module = <1>; - ambiq,iom-num = <4>; - }; }; spi5_default: spi5_default { group1 { pinmux = , , ; }; - group2 { - pinmux = ; - drive-push-pull; - ambiq,iom-mspi = <1>; - ambiq,iom-nce-module = <0>; - ambiq,iom-num = <5>; + }; + + adc0_default: adc0_default{ + group1 { + pinmux = , ; + drive-strength = "0.1"; }; }; @@ -193,4 +159,15 @@ ambiq,iom-num = <2>; }; }; + + bleif_default: bleif_default{ + group1 { + pinmux = , + , + , + , + , + ; + }; + }; }; diff --git a/boards/ambiq/apollo3p_evb/apollo3p_evb.dts b/boards/ambiq/apollo3p_evb/apollo3p_evb.dts index 02acc1bed57..75d61cbf2a3 100644 --- a/boards/ambiq/apollo3p_evb/apollo3p_evb.dts +++ b/boards/ambiq/apollo3p_evb/apollo3p_evb.dts @@ -15,6 +15,7 @@ zephyr,shell-uart = &uart0; zephyr,uart-pipe = &uart0; zephyr,flash-controller = &flash; + zephyr,bt_hci = &bt_hci_apollo; }; aliases { @@ -84,6 +85,12 @@ }; }; +&bleif { + pinctrl-0 = <&bleif_default>; + pinctrl-names = "default"; + status = "okay"; +}; + &uart0 { current-speed = <115200>; pinctrl-0 = <&uart0_default>; @@ -95,6 +102,15 @@ status = "okay"; }; +&spi0 { + compatible = "ambiq,spi"; + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; + cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>; + clock-frequency = ; + status = "okay"; +}; + &i2c3 { compatible = "ambiq,i2c"; pinctrl-0 = <&i2c3_default>; @@ -103,6 +119,45 @@ status = "okay"; }; +&counter0 { + status = "okay"; +}; + +&counter1 { + status = "okay"; +}; + +&counter2 { + status = "okay"; +}; + +&counter3 { + status = "okay"; +}; + +&counter4 { + status = "okay"; +}; + +&counter5 { + status = "okay"; +}; + +&counter6 { + status = "okay"; +}; + +&counter7 { + status = "okay"; +}; + +&adc0 { + compatible = "ambiq,adc"; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + &gpio0_31 { status = "okay"; }; diff --git a/boards/ambiq/apollo3p_evb/apollo3p_evb.yaml b/boards/ambiq/apollo3p_evb/apollo3p_evb.yaml index 0ed3fe2929d..2a490611cae 100644 --- a/boards/ambiq/apollo3p_evb/apollo3p_evb.yaml +++ b/boards/ambiq/apollo3p_evb/apollo3p_evb.yaml @@ -9,9 +9,13 @@ toolchain: - gnuarmemb supported: - uart + - adc - watchdog + - counter - gpio + - spi - i2c + - mspi testing: ignore_tags: - net diff --git a/boards/ambiq/apollo3p_evb/apollo3p_evb_connector.dtsi b/boards/ambiq/apollo3p_evb/apollo3p_evb_connector.dtsi new file mode 100644 index 00000000000..fc85edb4a63 --- /dev/null +++ b/boards/ambiq/apollo3p_evb/apollo3p_evb_connector.dtsi @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2024 Ambiq + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + ambiq_header: connector { + compatible = "ambiq-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffff80>; + gpio-map-pass-thru = <0 0x7f>; + gpio-map = <0 0 &gpio0_31 0 0>, /* IOS_SPI_SCK, IOS_I2C_SCL */ + <1 0 &gpio0_31 1 0>, /* IOS_SPI_MOSI, IOS_I2C_SDA */ + <2 0 &gpio0_31 2 0>, /* IOS_SPI_MISO */ + <3 0 &gpio0_31 3 0>, /* IOS_CE */ + <4 0 &gpio0_31 4 0>, /* IOS_INT */ + <5 0 &gpio0_31 5 0>, /* IOM0_SPI_SCK, IOM0_I2C_SCL */ + <6 0 &gpio0_31 6 0>, /* IOM0_SPI_MISO, IOM0_I2C_SDA */ + <7 0 &gpio0_31 7 0>, /* IOM0_SPI_MOSI */ + <8 0 &gpio0_31 8 0>, /* IOM1_SPI_SCK, IOM1_I2C_SCL */ + <9 0 &gpio0_31 9 0>, /* IOM1_SPI_MISO, IOM1_I2C_SDA */ + <10 0 &gpio0_31 10 0>, /* LED0, IOM1_SPI_MOSI */ + <11 0 &gpio0_31 11 0>, /* DISP_RESET */ + <12 0 &gpio0_31 12 0>, /* MSPI0_CE0 */ + <13 0 &gpio0_31 13 0>, /* IOM0_CS */ + <14 0 &gpio0_31 14 0>, /* LED3 */ + <15 0 &gpio0_31 15 0>, /* LED2 */ + <16 0 &gpio0_31 16 0>, /* BUTTON0 */ + <17 0 &gpio0_31 17 0>, /* LED4 */ + <18 0 &gpio0_31 18 0>, /* BUTTON1 */ + <19 0 &gpio0_31 19 0>, /* BUTTON2 */ + <20 0 &gpio0_31 20 0>, /* SWDCK */ + <21 0 &gpio0_31 21 0>, /* SWDIO */ + <22 0 &gpio0_31 22 0>, /* MSPI0_D0, UART0_TX */ + <23 0 &gpio0_31 23 0>, /* MSPI0_D3, UART0_RX */ + <24 0 &gpio0_31 24 0>, /* MSPI0_SCK */ + <25 0 &gpio0_31 25 0>, /* IOM2_MISO_SCK, IOM2_I2C_SDA */ + <26 0 &gpio0_31 26 0>, /* MSPI0_D1 */ + <27 0 &gpio0_31 27 0>, /* IOM2_SPI_SCK, IOM2_I2C_SCL*/ + <28 0 &gpio0_31 28 0>, /* MSPI0_CE0 */ + <29 0 &gpio0_31 29 0>, /* IOM3_CS */ + <30 0 &gpio0_31 30 0>, /* LED1 */ + <31 0 &gpio0_31 31 0>, /* DISP_3V3_EN */ + <32 0 &gpio32_63 0 0>, /* BLEIF_MOSI */ + <33 0 &gpio32_63 1 0>, /* BLEIF_CSN */ + <34 0 &gpio32_63 2 0>, /* IOM1_CS */ + <35 0 &gpio32_63 3 0>, /* BLEIF_STATUS */ + <36 0 &gpio32_63 4 0>, /* PDM_DATA */ + <37 0 &gpio32_63 5 0>, /* PDM_CLK */ + <38 0 &gpio32_63 6 0>, /* DISP_TE */ + <39 0 &gpio32_63 7 0>, /* DISP_PWR_EN */ + <40 0 &gpio32_63 8 0>, /* IOM4_SPI_MISO, IOM4_I2C_SDA */ + <41 0 &gpio32_63 9 0>, /* SWO */ + <42 0 &gpio32_63 10 0>, /* IOM3_I2C_SCL */ + <43 0 &gpio32_63 11 0>, /* IOM3_I2C_SDA */ + <44 0 &gpio32_63 12 0>, /* IOM4_SPI_MOSI */ + <45 0 &gpio32_63 13 0>, /* DISP_2V8_EN */ + <46 0 &gpio32_63 14 0>, /* ACC_INT */ + <47 0 &gpio32_63 15 0>, /* IOM5_SPI_MOSI */ + <48 0 &gpio32_63 16 0>, /* IOM5_I2C_SCL */ + <49 0 &gpio32_63 17 0>, /* IOM5_I2C_SDA */ + <50 0 &gpio32_63 18 0>, /* MSPI1_CE0 */ + <51 0 &gpio32_63 19 0>, /* MSPI1_D0 */ + <52 0 &gpio32_63 20 0>, /* MSPI1_D1 */ + <53 0 &gpio32_63 21 0>, /* MSPI1_D2 */ + <54 0 &gpio32_63 22 0>, /* MSPI1_D3 */ + <55 0 &gpio32_63 23 0>, /* MSPI1_D4 */ + <56 0 &gpio32_63 24 0>, /* MSPI1_D5 */ + <57 0 &gpio32_63 25 0>, /* MSPI1_D6 */ + <58 0 &gpio32_63 26 0>, /* MSPI1_D7 */ + <59 0 &gpio32_63 27 0>, /* MSPI1_SCK */ + <60 0 &gpio32_63 28 0>, /* MSPI1_DMDQS */ + <61 0 &gpio32_63 29 0>, /* MSPI2_CE1 */ + <62 0 &gpio32_63 30 0>, /* MSPI1_CE1 */ + <63 0 &gpio32_63 31 0>, /* MSPI2_CE0 */ + <64 0 &gpio64_95 0 0>, /* MSPI2_D0 */ + <65 0 &gpio64_95 1 0>, /* MSPI2_D1 */ + <66 0 &gpio64_95 2 0>, /* MSPI2_D2 */ + <67 0 &gpio64_95 3 0>, /* MSPI2_D3 */ + <68 0 &gpio64_95 4 0>, /* MSPI0_SCK */ + <69 0 &gpio64_95 5 0>, /* MSPI1_CE0 */ + <70 0 &gpio64_95 6 0>, /* See am_hal_pins.h file for further info */ + <71 0 &gpio64_95 7 0>, /* See am_hal_pins.h file for further info */ + <72 0 &gpio64_95 8 0>, /* See am_hal_pins.h file for further info */ + <73 0 &gpio64_95 9 0>, /* See am_hal_pins.h file for further info */ + <74 0 &gpio64_95 10 0>; /* See am_hal_pins.h file for further info */ + }; +}; + +ambiq_spi0: &spi0 {}; +ambiq_i2c3: &i2c3 {}; diff --git a/boards/ambiq/apollo3p_evb/doc/index.rst b/boards/ambiq/apollo3p_evb/doc/index.rst index 9d56556d69c..c06f3b1e168 100644 --- a/boards/ambiq/apollo3p_evb/doc/index.rst +++ b/boards/ambiq/apollo3p_evb/doc/index.rst @@ -60,7 +60,7 @@ Flashing an application ----------------------- Connect your device to your host computer using the JLINK USB port. -The sample application :ref:`hello_world` is used for this example. +The sample application :zephyr:code-sample:`hello_world` is used for this example. Build the Zephyr kernel and application, then flash it to the device: .. zephyr-app-commands:: @@ -69,7 +69,7 @@ Build the Zephyr kernel and application, then flash it to the device: :goals: flash .. note:: - `west flash` requires `SEGGER J-Link software`_ and `pylink`_ Python module + ``west flash`` requires `SEGGER J-Link software`_ and `pylink`_ Python module to be installed on you host computer. Open a serial terminal (minicom, putty, etc.) with the following settings: diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.defconfig b/boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.defconfig index 46d8af8ef95..5d16de3a1ca 100644 --- a/boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.defconfig +++ b/boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.defconfig @@ -9,17 +9,14 @@ if BT config MAIN_STACK_SIZE default 2048 -config BT_AMBIQ_HCI - default y - config BT_BUF_ACL_TX_COUNT default 14 config BT_BUF_CMD_TX_SIZE - default 255 + default $(UINT8_MAX) config BT_BUF_EVT_RX_SIZE - default 255 + default $(UINT8_MAX) config BT_BUF_ACL_TX_SIZE default 251 diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb-pinctrl.dtsi b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb-pinctrl.dtsi index 0622157b2d0..1d64b010f60 100644 --- a/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb-pinctrl.dtsi +++ b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb-pinctrl.dtsi @@ -77,81 +77,41 @@ group1 { pinmux = , , ; }; - group2 { - pinmux = ; - drive-push-pull; - ambiq,iom-nce-module = <0>; - }; }; spi1_default: spi1_default { group1 { pinmux = , , ; }; - group2 { - pinmux = ; - drive-push-pull; - ambiq,iom-nce-module = <4>; - }; }; spi2_default: spi2_default { group1 { pinmux = , , ; }; - group2 { - pinmux = ; - drive-push-pull; - ambiq,iom-nce-module = <8>; - }; }; spi3_default: spi3_default { group1 { pinmux = , , ; }; - group2 { - pinmux = ; - drive-push-pull; - ambiq,iom-nce-module = <12>; - }; }; spi4_default: spi4_default { group1 { pinmux = , , ; }; - group2 { - pinmux = ; - drive-push-pull; - ambiq,iom-nce-module = <16>; - }; }; spi5_default: spi5_default { group1 { pinmux = , , ; }; - group2 { - pinmux = ; - drive-push-pull; - ambiq,iom-nce-module = <20>; - }; }; spi6_default: spi6_default { group1 { pinmux = , , ; }; - group2 { - pinmux = ; - drive-push-pull; - ambiq,iom-nce-module = <24>; - }; }; spi7_default: spi7_default { group1 { pinmux = , , ; }; - group2 { - pinmux = ; - drive-push-pull; - ambiq,iom-nce-module = <28>; - }; }; mspi0_default: mspi0_default{ group1 { diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts index f9aa3c11c31..6a246a1f12e 100644 --- a/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts +++ b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts @@ -15,6 +15,7 @@ zephyr,shell-uart = &uart0; zephyr,uart-pipe = &uart0; zephyr,flash-controller = &flash; + zephyr,bt-hci = &bt_hci_apollo; }; aliases { @@ -70,7 +71,7 @@ status = "okay"; }; -&iom0 { +&i2c0 { compatible = "ambiq,i2c"; pinctrl-0 = <&i2c0_default>; pinctrl-names = "default"; @@ -78,15 +79,16 @@ status = "okay"; }; -&iom1 { +&spi1 { compatible = "ambiq,spi"; pinctrl-0 = <&spi1_default>; pinctrl-names = "default"; + cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>; clock-frequency = ; status = "okay"; }; -&iom4 { +&spi4 { pinctrl-0 = <&spi4_default>; pinctrl-names = "default"; status = "okay"; diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst b/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst index 214b5d4c2ef..3a1876297d2 100644 --- a/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst +++ b/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst @@ -68,7 +68,7 @@ Flashing an application ----------------------- Connect your device to your host computer using the JLINK USB port. -The sample application :ref:`hello_world` is used for this example. +The sample application :zephyr:code-sample:`hello_world` is used for this example. Build the Zephyr kernel and application, then flash it to the device: .. zephyr-app-commands:: @@ -77,7 +77,7 @@ Build the Zephyr kernel and application, then flash it to the device: :goals: flash .. note:: - `west flash` requires `SEGGER J-Link software`_ and `pylink`_ Python module + ``west flash`` requires `SEGGER J-Link software`_ and `pylink`_ Python module to be installed on you host computer. Open a serial terminal (minicom, putty, etc.) with the following settings: diff --git a/boards/ambiq/apollo4p_evb/apollo4p_evb-pinctrl.dtsi b/boards/ambiq/apollo4p_evb/apollo4p_evb-pinctrl.dtsi index b7b285d6ad8..125e1a7d238 100644 --- a/boards/ambiq/apollo4p_evb/apollo4p_evb-pinctrl.dtsi +++ b/boards/ambiq/apollo4p_evb/apollo4p_evb-pinctrl.dtsi @@ -17,6 +17,12 @@ input-enable; }; }; + adc0_default: adc0_default{ + group1 { + pinmux = , ; + drive-strength = "0.1"; + }; + }; i2c0_default: i2c0_default { group1 { pinmux = , ; @@ -81,87 +87,45 @@ bias-pull-up; }; }; - spi0_default: spi0_default { group1 { pinmux = , , ; }; - group2 { - pinmux = ; - drive-push-pull; - ambiq,iom-nce-module = <0>; - }; }; spi1_default: spi1_default { group1 { pinmux = , , ; }; - group2 { - pinmux = ; - drive-strength = "0.5"; - drive-push-pull; - ambiq,iom-nce-module = <4>; - }; }; spi2_default: spi2_default { group1 { pinmux = , , ; }; - group2 { - pinmux = ; - drive-push-pull; - ambiq,iom-nce-module = <8>; - }; }; spi3_default: spi3_default { group1 { pinmux = , , ; }; - group2 { - pinmux = ; - drive-push-pull; - ambiq,iom-nce-module = <12>; - }; }; spi4_default: spi4_default { group1 { pinmux = , , ; }; - group2 { - pinmux = ; - drive-push-pull; - ambiq,iom-nce-module = <16>; - }; }; spi5_default: spi5_default { group1 { pinmux = , , ; }; - group2 { - pinmux = ; - drive-push-pull; - ambiq,iom-nce-module = <20>; - }; }; spi6_default: spi6_default { group1 { pinmux = , , ; }; - group2 { - pinmux = ; - drive-push-pull; - ambiq,iom-nce-module = <24>; - }; }; spi7_default: spi7_default { group1 { pinmux = , , ; }; - group2 { - pinmux = ; - drive-push-pull; - ambiq,iom-nce-module = <28>; - }; }; mspi0_default: mspi0_default{ group1 { diff --git a/boards/ambiq/apollo4p_evb/apollo4p_evb.dts b/boards/ambiq/apollo4p_evb/apollo4p_evb.dts index 8b87f96ac68..c678604f358 100644 --- a/boards/ambiq/apollo4p_evb/apollo4p_evb.dts +++ b/boards/ambiq/apollo4p_evb/apollo4p_evb.dts @@ -14,6 +14,7 @@ zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,uart-pipe = &uart0; + zephyr,flash-controller = &flash; }; aliases { @@ -23,6 +24,7 @@ led2 = &led2; sw0 = &button0; sw1 = &button1; + rtc = &rtc0; }; leds { @@ -61,10 +63,22 @@ status = "okay"; }; +&adc0 { +compatible = "ambiq,adc"; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + &counter0 { status = "okay"; }; +&rtc0 { + status = "okay"; + clock = "XTAL"; +}; + &wdt0 { status = "okay"; }; @@ -81,6 +95,7 @@ compatible = "ambiq,spi"; pinctrl-0 = <&spi1_default>; pinctrl-names = "default"; + cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>; clock-frequency = <1000000>; status = "okay"; }; @@ -103,6 +118,23 @@ status = "okay"; }; +&flash0 { + erase-block-size = <2048>; + write-block-size = <16>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Set 16KB of storage at the end of the 1952KB of flash */ + storage_partition: partition@1e4000 { + label = "storage"; + reg = <0x001e4000 0x4000>; + }; + }; +}; + &gpio0_31 { status = "okay"; }; diff --git a/boards/ambiq/apollo4p_evb/apollo4p_evb.yaml b/boards/ambiq/apollo4p_evb/apollo4p_evb.yaml index 205da184346..1b7b54a71e6 100644 --- a/boards/ambiq/apollo4p_evb/apollo4p_evb.yaml +++ b/boards/ambiq/apollo4p_evb/apollo4p_evb.yaml @@ -14,6 +14,8 @@ supported: - gpio - spi - i2c + - rtc + - adc - hwinfo testing: ignore_tags: diff --git a/boards/ambiq/apollo4p_evb/doc/index.rst b/boards/ambiq/apollo4p_evb/doc/index.rst index 7c5cd174cf6..fef698b0a1b 100644 --- a/boards/ambiq/apollo4p_evb/doc/index.rst +++ b/boards/ambiq/apollo4p_evb/doc/index.rst @@ -63,7 +63,7 @@ Flashing an application ----------------------- Connect your device to your host computer using the JLINK USB port. -The sample application :ref:`hello_world` is used for this example. +The sample application :zephyr:code-sample:`hello_world` is used for this example. Build the Zephyr kernel and application, then flash it to the device: .. zephyr-app-commands:: @@ -72,7 +72,7 @@ Build the Zephyr kernel and application, then flash it to the device: :goals: flash .. note:: - `west flash` requires `SEGGER J-Link software`_ and `pylink`_ Python module + ``west flash`` requires `SEGGER J-Link software`_ and `pylink`_ Python module to be installed on you host computer. Open a serial terminal (minicom, putty, etc.) with the following settings: diff --git a/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350.yaml b/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350.yaml index 69087b9ad9e..d36d743e289 100644 --- a/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350.yaml +++ b/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350.yaml @@ -16,6 +16,9 @@ supported: - mbox - flash - dma + - led + - syscon + - hwinfo testing: ignore_tags: - bluetooth diff --git a/boards/andestech/adp_xc7k_ae350/doc/index.rst b/boards/andestech/adp_xc7k_ae350/doc/index.rst index ee7dc40d355..3e290dd2f28 100644 --- a/boards/andestech/adp_xc7k_ae350/doc/index.rst +++ b/boards/andestech/adp_xc7k_ae350/doc/index.rst @@ -226,7 +226,7 @@ Building ======== You can build applications in the usual way. Here is an example for -the :ref:`hello_world` application. +the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/arduino/due/doc/index.rst b/boards/arduino/due/doc/index.rst index 5d984027534..dfc6e007801 100644 --- a/boards/arduino/due/doc/index.rst +++ b/boards/arduino/due/doc/index.rst @@ -175,7 +175,7 @@ Applications for the ``arduino_due`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. After +Here is an example for the :zephyr:code-sample:`hello_world` application. After building the application, press the Reset button before running the flash command, so the board will boot into the SAM-BA bootloader and be prepared to receive the new program. diff --git a/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m4_defconfig b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m4_defconfig index c7a9e88969b..d4788745e7e 100644 --- a/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m4_defconfig +++ b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m4_defconfig @@ -4,9 +4,6 @@ # Enable GPIO CONFIG_GPIO=y -# Clock configuration -CONFIG_CLOCK_CONTROL=y - # Enable MPU CONFIG_ARM_MPU=y @@ -19,6 +16,3 @@ CONFIG_SERIAL=y # Console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y - -# Enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.dts b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.dts index a0791514b78..5d6e0dd7d88 100644 --- a/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.dts +++ b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.dts @@ -37,7 +37,6 @@ led0 = &red_led; led1 = &green_led; sw0 = &user_button; - spi-flash0 = &n25q128a1; }; }; diff --git a/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.yaml b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.yaml index cdcaeba7c77..b637d14017b 100644 --- a/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.yaml +++ b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.yaml @@ -14,6 +14,5 @@ supported: - arduino_spi - spi - memc - - usb_cdc - usb_device vendor: arduino diff --git a/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7_defconfig b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7_defconfig index 0bd7546e26a..997a600f382 100644 --- a/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7_defconfig +++ b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7_defconfig @@ -7,9 +7,6 @@ CONFIG_POWER_SUPPLY_DIRECT_SMPS=n # Enable GPIO CONFIG_GPIO=y -# Enable clocks -CONFIG_CLOCK_CONTROL=y - # Enable MPU CONFIG_ARM_MPU=y @@ -23,8 +20,5 @@ CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y -# Enable pin controller -CONFIG_PINCTRL=y - # Use zephyr,code-partition as flash offset CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/arduino/giga_r1/doc/index.rst b/boards/arduino/giga_r1/doc/index.rst index 0e95653edfa..696844a71fa 100644 --- a/boards/arduino/giga_r1/doc/index.rst +++ b/boards/arduino/giga_r1/doc/index.rst @@ -130,7 +130,7 @@ First, connect the Arduino GIGA R1 board to your host computer using the USB port to prepare it for flashing. Double click the ``RST`` button to put the board into the Arduino Bootloader mode. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/arduino/mkrzero/doc/index.rst b/boards/arduino/mkrzero/doc/index.rst index b6fe37ddd16..2ea120d9313 100644 --- a/boards/arduino/mkrzero/doc/index.rst +++ b/boards/arduino/mkrzero/doc/index.rst @@ -130,7 +130,7 @@ bootloader can be entered by quickly tapping the reset button twice. Flashing ======== -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/arduino/nano_33_ble/arduino_nano_33_ble-common.dtsi b/boards/arduino/nano_33_ble/arduino_nano_33_ble-common.dtsi index 3d31ede313f..589d5b66241 100644 --- a/boards/arduino/nano_33_ble/arduino_nano_33_ble-common.dtsi +++ b/boards/arduino/nano_33_ble/arduino_nano_33_ble-common.dtsi @@ -104,6 +104,7 @@ blue-pwm-led = &blue_pwm_led; spi = &spi2; watchdog0 = &wdt0; + accel0 = &lsm9ds1; }; }; @@ -166,6 +167,12 @@ arduino_i2c: &i2c0 { pinctrl-0 = <&i2c1_default>; pinctrl-1 = <&i2c1_sleep>; pinctrl-names = "default", "sleep"; + + lsm9ds1: lsm9ds1@6b { + compatible = "st,lsm9ds1"; + reg = <0x6b>; + }; + }; /* SPI2 is used because SPI1/0 shares conflicts with I2C1/0 */ diff --git a/boards/arduino/nano_33_ble/arduino_nano_33_ble.yaml b/boards/arduino/nano_33_ble/arduino_nano_33_ble.yaml index 733309555cb..385d3bd1559 100644 --- a/boards/arduino/nano_33_ble/arduino_nano_33_ble.yaml +++ b/boards/arduino/nano_33_ble/arduino_nano_33_ble.yaml @@ -14,7 +14,6 @@ supported: - serial - spi - uart - - usb_cdc - usb_device - watchdog vendor: arduino diff --git a/boards/arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense.yaml b/boards/arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense.yaml index b8741e66b35..6a80eaecf48 100644 --- a/boards/arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense.yaml +++ b/boards/arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense.yaml @@ -14,7 +14,6 @@ supported: - serial - spi - uart - - usb_cdc - usb_device - watchdog vendor: arduino diff --git a/boards/arduino/nano_33_ble/doc/index.rst b/boards/arduino/nano_33_ble/doc/index.rst index 05c0605b464..2b5ede0ea11 100644 --- a/boards/arduino/nano_33_ble/doc/index.rst +++ b/boards/arduino/nano_33_ble/doc/index.rst @@ -160,7 +160,7 @@ That license ties to Arduino Nano 33 BLE hardware serial number, it also works with the ZephyrRTOS. Follow the instruction of the tutorial for Arduino -`Lauterbach TRACE32 GDB Front-End Debugger for Nano 33 BLE` +`Lauterbach TRACE32 GDB Front-End Debugger for Nano 33 BLE`_ to install the TRACE32. After installing the TRACE32, You should set the environmental variable ``T32_DIR``. diff --git a/boards/arduino/nano_33_iot/doc/index.rst b/boards/arduino/nano_33_iot/doc/index.rst index 5b87fb52c18..e6a51198b92 100644 --- a/boards/arduino/nano_33_iot/doc/index.rst +++ b/boards/arduino/nano_33_iot/doc/index.rst @@ -118,7 +118,7 @@ will be entered automatically when you run :code:`west flash`. Flashing ======== -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/arduino/nicla_sense_me/arduino_nicla_sense_me.dts b/boards/arduino/nicla_sense_me/arduino_nicla_sense_me.dts index 2329853a1a3..52e376ed140 100644 --- a/boards/arduino/nicla_sense_me/arduino_nicla_sense_me.dts +++ b/boards/arduino/nicla_sense_me/arduino_nicla_sense_me.dts @@ -8,6 +8,7 @@ #include #include "arduino_nicla_sense_me-pinctrl.dtsi" #include +#include / { model = "Arduino Nicla Sense ME"; @@ -37,7 +38,6 @@ aliases { sw0 = &user_button; watchdog0 = &wdt0; - spi-flash0 = &mx25r1635f; }; }; @@ -73,6 +73,18 @@ pinctrl-0 = <&i2c0_default>; pinctrl-1 = <&i2c0_sleep>; pinctrl-names = "default", "sleep"; + + is31fl3194@53 { + compatible = "issi,is31fl3194"; + reg = <0x53>; + led_rgb { + label = "RGB LED"; + color-mapping = , + , + ; + current-limit = <10>; + }; + }; }; /* I2C1 in datasheet */ diff --git a/boards/arduino/nicla_sense_me/doc/index.rst b/boards/arduino/nicla_sense_me/doc/index.rst index 6a6eb3a0d1b..1bf984f23f4 100644 --- a/boards/arduino/nicla_sense_me/doc/index.rst +++ b/boards/arduino/nicla_sense_me/doc/index.rst @@ -95,7 +95,7 @@ Flashing First, connect the Arduino Nicla Sense ME board to your host computer using the USB port to prepare it for flashing. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -118,7 +118,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/arduino/nicla_vision/Kconfig.arduino_nicla_vision b/boards/arduino/nicla_vision/Kconfig.arduino_nicla_vision new file mode 100644 index 00000000000..3d5b76a0749 --- /dev/null +++ b/boards/arduino/nicla_vision/Kconfig.arduino_nicla_vision @@ -0,0 +1,6 @@ +# Copyright 2024 Felipe Neves +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ARDUINO_NICLA_VISION + select SOC_STM32H747XX_M7 if BOARD_ARDUINO_NICLA_VISION_STM32H747XX_M7 + select SOC_STM32H747XX_M4 if BOARD_ARDUINO_NICLA_VISION_STM32H747XX_M4 diff --git a/boards/arduino/nicla_vision/Kconfig.defconfig b/boards/arduino/nicla_vision/Kconfig.defconfig new file mode 100644 index 00000000000..8d737075d08 --- /dev/null +++ b/boards/arduino/nicla_vision/Kconfig.defconfig @@ -0,0 +1,18 @@ +# Copyright 2024 Felipe Neves +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ARDUINO_NICLA_VISION + +if BT + +choice AIROC_PART + default CYW4343W +endchoice + +choice CYW4343W_MODULE + default CYW4343W_MURATA_1DX +endchoice + +endif # BT + +endif # BOARD_ARDUINO_NICLA_VISION diff --git a/boards/arduino/nicla_vision/arduino_nicla_vision.dtsi b/boards/arduino/nicla_vision/arduino_nicla_vision.dtsi new file mode 100644 index 00000000000..cec25611b1b --- /dev/null +++ b/boards/arduino/nicla_vision/arduino_nicla_vision.dtsi @@ -0,0 +1,33 @@ +/* + * Copyright 2024 Felipe Neves + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + leds { + compatible = "gpio-leds"; + red_led: led_0 { + gpios = <&gpioe 3 GPIO_ACTIVE_LOW>; + }; + green_led: led_1 { + gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; + }; + blue_led: led_2 { + gpios = <&gpiof 4 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&rcc { + d1cpre = <1>; + hpre = <2>; + d1ppre = <2>; + d2ppre1 = <2>; + d2ppre2 = <2>; + d3ppre = <2>; +}; + +&mailbox { + status = "okay"; +}; diff --git a/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m4.dts b/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m4.dts new file mode 100644 index 00000000000..f8d97508d83 --- /dev/null +++ b/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m4.dts @@ -0,0 +1,37 @@ +/* + * Copyright 2024 Felipe Neves + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include "arduino_nicla_vision.dtsi" + +/ { + model = "Arduino Nicla Vision Board (M4)"; + compatible = "arduino,nicla-vision"; + + chosen { + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; + zephyr,sram = &sram1; + zephyr,flash = &flash1; + }; + + aliases { + led0 = &blue_led; + }; +}; + +&rcc { + clock-frequency = ; +}; + +&uart4 { + status = "okay"; + pinctrl-0 = <&uart4_tx_pb9 &uart4_rx_pb8>; + pinctrl-names = "default"; + current-speed = <115200>; +}; diff --git a/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m4.yaml b/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m4.yaml new file mode 100644 index 00000000000..727622952e5 --- /dev/null +++ b/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m4.yaml @@ -0,0 +1,18 @@ +identifier: arduino_nicla_vision/stm32h747xx/m4 +name: Arduino Nicla Vision (M4) +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 288 +flash: 1024 +supported: + - gpio +testing: + ignore_tags: + - mpu + - nfc + - net +vendor: arduino diff --git a/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m4_defconfig b/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m4_defconfig new file mode 100644 index 00000000000..b249eb54e0f --- /dev/null +++ b/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m4_defconfig @@ -0,0 +1,18 @@ +# Copyright 2024 Felipe Neves +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable uart driver +CONFIG_SERIAL=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.dts b/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.dts new file mode 100644 index 00000000000..ffd72fe9fb7 --- /dev/null +++ b/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.dts @@ -0,0 +1,194 @@ +/* + * Copyright 2024 Felipe Neves + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include "arduino_nicla_vision.dtsi" + +/ { + model = "Arduino Nicla Vision Board (M7)"; + compatible = "arduino,nicla-vision"; + + chosen { + zephyr,console = &lpuart1; + zephyr,shell-uart = &lpuart1; + zephyr,uart-mcumgr = &lpuart1; + zephyr,bt-hci = &bt_hci_uart; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + sdram1: sdram@c0000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + device_type = "memory"; + reg = <0xc0000000 DT_SIZE_M(8)>; + zephyr,memory-region = "SDRAM1"; + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + }; + + aliases { + led0 = &red_led; + led1 = &green_led; + }; + + otghs_ulpi_phy: otghs_ulpis_phy { + compatible = "usb-ulpi-phy"; + #phy-cells = <0>; + }; +}; + +&clk_hse { + status = "okay"; + clock-frequency = ; +}; + +&clk_lse { + status = "okay"; +}; + +&clk_hsi48 { + status = "okay"; +}; + +&pll { + div-m = <5>; + mul-n = <192>; + div-p = <2>; + div-q = <4>; + div-r = <2>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; +}; + +&lpuart1 { + status = "okay"; + pinctrl-0 = <&lpuart1_tx_pa9 &lpuart1_rx_pa10>; + pinctrl-names = "default"; + current-speed = <115200>; +}; + +&usart1 { + pinctrl-0 = <&usart1_rx_pb7 &usart1_tx_pb6 + &usart1_rts_pa12 &usart1_cts_pa11>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; + hw-flow-control; + + bt_hci_uart: bt_hci_uart { + compatible = "zephyr,bt-hci-uart"; + status = "okay"; + + murata-1dx { + compatible = "infineon,cyw43xxx-bt-hci"; + bt-reg-on-gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>; + bt-host-wake-gpios = <&gpiod 14 GPIO_ACTIVE_HIGH>; + bt-dev-wake-gpios = <&gpioe 9 GPIO_ACTIVE_HIGH>; + fw-download-speed = <115200>; + }; + }; +}; + +&i2c1 { + status = "disabled"; + pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>; + pinctrl-names = "default"; + clock-frequency = ; +}; + +&i2c2 { + status = "okay"; + pinctrl-0 = <&i2c2_scl_pf1 &i2c2_sda_pf0>; + pinctrl-names = "default"; + clock-frequency = ; + + vl53l1x: vl53l1x@52 { + compatible = "st,vl53l1x"; + reg = <0x52>; + status = "okay"; + xshut-gpios = <&gpiog 10 GPIO_ACTIVE_HIGH>; + int-gpios = <&gpiod 8 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c3 { + status = "okay"; + pinctrl-0 = <&i2c3_scl_pa8 &i2c3_sda_pc9>; + pinctrl-names = "default"; + clock-frequency = ; +}; + +&spi4 { + status = "okay"; + pinctrl-0 = <&spi4_nss_pe11 &spi4_sck_pe12 + &spi4_miso_pe13 &spi4_mosi_pe14>; + pinctrl-names = "default"; +}; + +&spi5 { + status = "okay"; + pinctrl-0 = <&spi5_nss_pf6 &spi5_sck_pf7 + &spi5_miso_pf8 &spi5_mosi_pf11>; + pinctrl-names = "default"; + + lsm6dso: lsm6dso@0 { + compatible = "st,lsm6dso"; + status = "okay"; + reg = <0x0>; + irq-gpios = <&gpioa 1 GPIO_ACTIVE_LOW>; + spi-max-frequency = <4000000>; + }; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "bootloader"; + reg = <0x0 0x40000>; + read-only; + }; + + slot0_partition: partition@40000 { + label = "image-0"; + reg = <0x40000 0x000c0000>; + }; + }; +}; + +&rng { + status = "okay"; +}; + +zephyr_udc0: &usbotg_hs { + pinctrl-0 = <&usb_otg_hs_ulpi_ck_pa5 + &usb_otg_hs_ulpi_d0_pa3 + &usb_otg_hs_ulpi_d1_pb0 + &usb_otg_hs_ulpi_d2_pb1 + &usb_otg_hs_ulpi_d3_pb10 + &usb_otg_hs_ulpi_d4_pb11 + &usb_otg_hs_ulpi_d5_pb12 + &usb_otg_hs_ulpi_d6_pb13 + &usb_otg_hs_ulpi_d7_pb5 + &usb_otg_hs_ulpi_stp_pc0 + &usb_otg_hs_ulpi_dir_pc2_c + &usb_otg_hs_ulpi_nxt_pc3_c>; + pinctrl-names = "default"; + maximum-speed = "high-speed"; + phys = <&otghs_ulpi_phy>; + status = "okay"; +}; diff --git a/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.yaml b/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.yaml new file mode 100644 index 00000000000..006cd2b35b4 --- /dev/null +++ b/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.yaml @@ -0,0 +1,15 @@ +identifier: arduino_nicla_vision/stm32h747xx/m7 +name: Arduino Nicla Vision (M7) +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 512 +flash: 1024 +supported: + - gpio + - spi + - i2c +vendor: arduino diff --git a/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7_defconfig b/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7_defconfig new file mode 100644 index 00000000000..1b891847469 --- /dev/null +++ b/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7_defconfig @@ -0,0 +1,24 @@ +# Copyright 2024 Felipe Neves +# SPDX-License-Identifier: Apache-2.0 + +# Disable the internal SMPS regulator +CONFIG_POWER_SUPPLY_DIRECT_SMPS=n + +# Enable GPIO +CONFIG_GPIO=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable uart driver +CONFIG_SERIAL=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Use zephyr,code-partition as flash offset +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/arduino/nicla_vision/board.cmake b/boards/arduino/nicla_vision/board.cmake new file mode 100644 index 00000000000..d90b93bf6b2 --- /dev/null +++ b/boards/arduino/nicla_vision/board.cmake @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_ARDUINO_NICLA_VISION_STM32H747XX_M7) + board_runner_args(jlink "--device=STM32H747XI_M7" "--speed=4000") + board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_arduino_nicla_vision_m7.cfg") + board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) +elseif(CONFIG_BOARD_ARDUINO_NICLA_VISION_STM32H747XX_M4) + board_runner_args(jlink "--device=STM32H747XI_M4" "--speed=4000") + board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_arduino_nicla_vision_m4.cfg") + board_runner_args(openocd --target-handle=_CHIPNAME.cpu1) +endif() +board_runner_args(dfu-util "--pid=2341:035f" "--alt=0" "--dfuse") +board_runner_args(blackmagicprobe "--connect-rst") + +include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake) +include(${ZEPHYR_BASE}/boards/common/blackmagicprobe.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/arduino/nicla_vision/board.yml b/boards/arduino/nicla_vision/board.yml new file mode 100644 index 00000000000..660cb3ca8aa --- /dev/null +++ b/boards/arduino/nicla_vision/board.yml @@ -0,0 +1,5 @@ +board: + name: arduino_nicla_vision + vendor: arduino + socs: + - name: stm32h747xx diff --git a/boards/arduino/nicla_vision/doc/img/arduino_nicla_vision.webp b/boards/arduino/nicla_vision/doc/img/arduino_nicla_vision.webp new file mode 100644 index 00000000000..378b69dc965 Binary files /dev/null and b/boards/arduino/nicla_vision/doc/img/arduino_nicla_vision.webp differ diff --git a/boards/arduino/nicla_vision/doc/index.rst b/boards/arduino/nicla_vision/doc/index.rst new file mode 100644 index 00000000000..fac12f25fac --- /dev/null +++ b/boards/arduino/nicla_vision/doc/index.rst @@ -0,0 +1,193 @@ +.. _arduino_nicla_vision_board: + +Arduino Nicla Vision +#################### + +Overview +******** + +Arduino Nicla Vision is a development board by Arduino based on the +STM32H747GAII, a dual core ARM Cortex-M7 + Cortex-M4 MCU, with 2MBytes of Flash +memory and 1MB SRAM. + +The board features: + +- RGB LED +- Reset Boot button +- USB device +- Murata Type 1DX Bluetooth + WiFi module (CYW4343W based) +- GC2145 2 Megapixel Camera Sensor +- SE050C2HQ1 Crypto IC +- MP34DT06JTR Omnidirectional Microphone +- VL53L1CBV0FY ToF Sensor +- LSM6DSOXTR Gyro+Accelerometer Sensor + +.. image:: img/arduino_nicla_vision.webp + :align: center + :alt: Arduino Nicla Vision + +More information about the board, including the datasheet, pinout and +schematics, can be found at the `Arduino Nicla Vision website`_. + +More information about STM32H747GAII6 can be found here: + +- `STM32H747XI on www.st.com`_ +- `STM32H747xx reference manual`_ +- `STM32H747xx datasheet`_ + +Supported Features +================== + +The current Zephyr ``arduino_nicla_vision/stm32h747xx/m7`` board configuration supports the +following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| IPM | on-chip | virtual mailbox based on HSEM | ++-----------+------------+-------------------------------------+ +| RADIO | Murata 1DX | WiFi and Bluetooth module | ++-----------+------------+-------------------------------------+ + +And the ``arduino_nicla_vision/stm32h747xx/m4`` has the following +support from Zephyr: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr port. + +Fetch Binary Blobs +****************** + +The board Bluetooth/WiFi module requires fetching some binary blob files, to do +that run the command: + +.. code-block:: console + + west blobs fetch hal_infineon + +.. note:: Only Bluetooth functionality is currently supported. + +Resources sharing +================= + +The dual core nature of STM32H747 SoC requires sharing HW resources between the +two cores. This is done in 3 ways: + +- **Compilation**: Clock configuration is only accessible to M7 core. M4 core only + has access to bus clock activation and deactivation. +- **Static pre-compilation assignment**: Peripherals such as a UART are assigned in + devicetree before compilation. The user must ensure peripherals are not assigned + to both cores at the same time. +- **Run time protection**: Interrupt-controller and GPIO configurations could be + accessed by both cores at run time. Accesses are protected by a hardware semaphore + to avoid potential concurrent access issues. + +Programming and Debugging +************************* + +Applications for the ``arduino_nicla_vision`` board should be built per core target, +using either ``arduino_nicla_vision/stm32h747xx/m7`` or ``arduino_nicla_vision/stm32h747xx/m4`` as the target. + +See :ref:`build_an_application` for more information about application builds. + +Flashing +======== + +This board can be flashed either using dfu-util, or with an external debugging +probe, such as a J-Link or Black Magic Probe, connected to the on board MIPI-10 +SWD port marked as "JTAG". + +.. note:: + + The board ships with a custom Arduino bootloader programmed in the first + flash page that can be triggered by double clicking the ``RST`` button. This + bootloader is USB-DFU compatible and supports programming both the internal + and external flash and is the one used by ``west flash`` by default. + +First, connect the Arduino Nicla Vision board to your host computer using the USB +port to prepare it for flashing. Double click the ``RST`` button to put the +board into the Arduino Bootloader mode. Then build and flash your application. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: arduino_nicla_vision/stm32h747xx/m7 + :goals: build flash + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arduino_nicla_vision + +Similarly, you can build and flash samples on the M4 target. + +Here is an example for the :zephyr:code-sample:`blinky` application on M4 core. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: arduino_nicla_vision/stm32h747xx/m4 + :goals: build flash + +Debugging +========= + +Debugging is supported by using ``west debug`` with an external probe such as a +J-Link or Black Magic Probe, connected to the on board through the edge eslov pins +as "SWD". For example:: + + west debug -r jlink + +.. _Arduino Nicla Vision website: + https://docs.arduino.cc/hardware/nicla-vision/ + +.. _Arduino Nicla Vision User Manual: + https://docs.arduino.cc/tutorials/nicla-vision/user-manual/ + +.. _STM32H747XI on www.st.com: + https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32h7-series/stm32h747-757/stm32h747xi.html + +.. _STM32H747xx reference manual: + https://www.st.com/resource/en/reference_manual/dm00176879.pdf + +.. _STM32H747xx datasheet: + https://www.st.com/resource/en/datasheet/stm32h747xi.pdf + +.. _dfu-util: + http://dfu-util.sourceforge.net/build.html diff --git a/boards/arduino/nicla_vision/support/openocd_arduino_nicla_vision_m4.cfg b/boards/arduino/nicla_vision/support/openocd_arduino_nicla_vision_m4.cfg new file mode 100644 index 00000000000..ddceef92cb1 --- /dev/null +++ b/boards/arduino/nicla_vision/support/openocd_arduino_nicla_vision_m4.cfg @@ -0,0 +1,12 @@ + +source [find interface/stlink.cfg] + +transport select hla_swd + +set DUAL_BANK 1 + +set DUAL_CORE 1 + +source [find target/stm32h7x.cfg] + +reset_config srst_only srst_nogate connect_assert_srst diff --git a/boards/arduino/nicla_vision/support/openocd_arduino_nicla_vision_m7.cfg b/boards/arduino/nicla_vision/support/openocd_arduino_nicla_vision_m7.cfg new file mode 100644 index 00000000000..75d441d1809 --- /dev/null +++ b/boards/arduino/nicla_vision/support/openocd_arduino_nicla_vision_m7.cfg @@ -0,0 +1,28 @@ + +source [find interface/stlink.cfg] + +transport select hla_swd + +source [find target/stm32h7x.cfg] + +# Use connect_assert_srst here to be able to program +# even when core is in sleep mode +reset_config srst_only srst_nogate connect_assert_srst + +$_CHIPNAME.cpu0 configure -event gdb-attach { + echo "Debugger attaching: halting execution" + gdb_breakpoint_override hard +} + +$_CHIPNAME.cpu0 configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} + +# Due to the use of connect_assert_srst, running gdb requires +# to reset halt just after openocd init. +rename init old_init +proc init {} { + old_init + reset halt +} diff --git a/boards/arduino/opta/CMakeLists.txt b/boards/arduino/opta/CMakeLists.txt new file mode 100644 index 00000000000..c4483abeb70 --- /dev/null +++ b/boards/arduino/opta/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2021 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(board_gpio_hse.c) diff --git a/boards/arduino/opta/Kconfig.arduino_opta b/boards/arduino/opta/Kconfig.arduino_opta index d591283a6ff..c9805a38100 100644 --- a/boards/arduino/opta/Kconfig.arduino_opta +++ b/boards/arduino/opta/Kconfig.arduino_opta @@ -1,5 +1,7 @@ # Copyright (c) 2023 Felipe Neves +# Copyright (c) 2024 DNDG srl # SPDX-License-Identifier: Apache-2.0 config BOARD_ARDUINO_OPTA - select SOC_STM32H747XX_M4 + select SOC_STM32H747XX_M4 if BOARD_ARDUINO_OPTA_STM32H747XX_M4 + select SOC_STM32H747XX_M7 if BOARD_ARDUINO_OPTA_STM32H747XX_M7 diff --git a/boards/arduino/opta/Kconfig.defconfig b/boards/arduino/opta/Kconfig.defconfig new file mode 100644 index 00000000000..1a89b70db5c --- /dev/null +++ b/boards/arduino/opta/Kconfig.defconfig @@ -0,0 +1,44 @@ +# Copyright 2024 Rahul Arasikere +# Copyright 2024 DNDG srl +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ARDUINO_OPTA + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +if USB_DEVICE_STACK + +config USB_DEVICE_PRODUCT + default "Arduino Opta" + +config USB_DEVICE_PID + default 0x0164 + +config USB_DEVICE_VID + default 0x35d1 + +config USB_DEVICE_INITIALIZE_AT_BOOT + default y + +if LOG + +# Logger cannot use itself to log +choice USB_CDC_ACM_LOG_LEVEL_CHOICE + default USB_CDC_ACM_LOG_LEVEL_OFF +endchoice + +# Set USB log level to error only +choice USB_DEVICE_LOG_LEVEL_CHOICE + default USB_DEVICE_LOG_LEVEL_ERR +endchoice + +endif # LOG + +endif # USB_DEVICE_STACK + +endif # BOARD_ARDUINO_OPTA diff --git a/boards/arduino/opta/arduino_opta-common.dtsi b/boards/arduino/opta/arduino_opta-common.dtsi new file mode 100644 index 00000000000..dcf957265c4 --- /dev/null +++ b/boards/arduino/opta/arduino_opta-common.dtsi @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2023 Felipe Neves + * Copyright (c) 2024 DNDG srl + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + leds { + compatible = "gpio-leds"; + + status_led_1: led_1 { + gpios = <&gpioi 0 GPIO_ACTIVE_HIGH>; + }; + status_led_2: led_2 { + gpios = <&gpioi 1 GPIO_ACTIVE_HIGH>; + }; + status_led_3: led_3 { + gpios = <&gpioi 3 GPIO_ACTIVE_HIGH>; + }; + status_led_4: led_4 { + gpios = <&gpioh 15 GPIO_ACTIVE_HIGH>; + }; + led_reset: led_g { + gpios = <&gpioh 12 GPIO_ACTIVE_HIGH>; + }; + led_reset_red: led_r { + gpios = <&gpioh 11 GPIO_ACTIVE_HIGH>; + }; + led_user: led_b { + gpios = <&gpioe 5 GPIO_ACTIVE_HIGH>; + }; + }; + + relays { + compatible = "gpio-power-switches"; + + output_d0: d0 { + gpios = <&gpioi 6 GPIO_ACTIVE_HIGH>; + }; + output_d1: d1 { + gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>; + }; + output_d2: d2 { + gpios = <&gpioi 7 GPIO_ACTIVE_HIGH>; + }; + output_d3: d3 { + gpios = <&gpioi 4 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_button: button { + gpios = <&gpioe 4 GPIO_ACTIVE_HIGH>; + zephyr,code = ; + }; + }; + + aliases { + sw0 = &user_button; + led0 = &status_led_1; + led1 = &status_led_2; + led2 = &status_led_3; + led3 = &status_led_4; + relay1 = &output_d0; + relay2 = &output_d1; + relay3 = &output_d2; + relay4 = &output_d3; + }; +}; + +&rcc { + d1cpre = <1>; + hpre = <2>; + d1ppre = <2>; + d2ppre1 = <2>; + d2ppre2 = <2>; + d3ppre = <2>; +}; + +&rtc { + status = "okay"; +}; + +&mailbox { + status = "okay"; +}; diff --git a/boards/arduino/opta/arduino_opta_stm32h747xx_m4.dts b/boards/arduino/opta/arduino_opta_stm32h747xx_m4.dts index bc74a2691f4..e2825752ddc 100644 --- a/boards/arduino/opta/arduino_opta_stm32h747xx_m4.dts +++ b/boards/arduino/opta/arduino_opta_stm32h747xx_m4.dts @@ -1,5 +1,6 @@ /* * Copyright (c) 2023 Felipe Neves + * Copyright (c) 2024 DNDG srl * * SPDX-License-Identifier: Apache-2.0 */ @@ -8,6 +9,7 @@ #include #include #include +#include "arduino_opta-common.dtsi" / { model = "Arduino OPTA M4 core Programmable Logic Controller"; @@ -18,36 +20,6 @@ zephyr,flash = &flash1; zephyr,code-partition = &slot0_partition; }; - - leds { - compatible = "gpio-leds"; - status_led_1: led_1 { - gpios = <&gpioi 0 GPIO_ACTIVE_LOW>; - }; - status_led_2: led_2 { - gpios = <&gpioi 1 GPIO_ACTIVE_LOW>; - }; - status_led_3: led_3 { - gpios = <&gpioi 3 GPIO_ACTIVE_LOW>; - }; - status_led_4: led_4 { - gpios = <&gpioh 15 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - user_button: button { - gpios = <&gpioe 4 GPIO_ACTIVE_HIGH>; - zephyr,code = ; - }; - }; - - aliases { - sw0 = &user_button; - led0 = &status_led_1; - }; }; &flash1 { @@ -64,11 +36,5 @@ }; &rcc { - d1cpre = <1>; - hpre = <2>; - d1ppre = <2>; - d2ppre1 = <2>; - d2ppre2 = <2>; - d3ppre = <2>; clock-frequency = ; }; diff --git a/boards/arduino/opta/arduino_opta_stm32h747xx_m4_defconfig b/boards/arduino/opta/arduino_opta_stm32h747xx_m4_defconfig index f9f3e39d9c7..fb2168f361a 100644 --- a/boards/arduino/opta/arduino_opta_stm32h747xx_m4_defconfig +++ b/boards/arduino/opta/arduino_opta_stm32h747xx_m4_defconfig @@ -1,20 +1,14 @@ # Copyright (c) 2023 Felipe Neves # SPDX-License-Identifier: Apache-2.0 -# enable GPIO +# Enable GPIO CONFIG_GPIO=y -# clock configuration -CONFIG_CLOCK_CONTROL=y - # Enable MPU CONFIG_ARM_MPU=y # Enable HW stack protection CONFIG_HW_STACK_PROTECTION=y -# enable pin controller -CONFIG_PINCTRL=y - # Use zephyr,code-partition as flash offset CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/arduino/opta/arduino_opta_stm32h747xx_m7.dts b/boards/arduino/opta/arduino_opta_stm32h747xx_m7.dts new file mode 100644 index 00000000000..e26a16c7858 --- /dev/null +++ b/boards/arduino/opta/arduino_opta_stm32h747xx_m7.dts @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2022 Benjamin Björnsson . + * Copyright (c) 2024 DNDG srl + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include "arduino_opta-common.dtsi" + +/ { + model = "Arduino OPTA M7 core Programmable Logic Controller"; + compatible = "arduino,opta-m7"; + + chosen { + zephyr,console = &cdc_acm_uart0; + zephyr,shell-uart = &cdc_acm_uart0; + zephyr,cdc-acm-uart0 = &cdc_acm_uart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + ethernet_phy_en: ethernet_phy_en { + compatible = "regulator-fixed"; + regulator-name = "ethernet-phy-reset-release"; + enable-gpios = <&gpioj 15 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + status = "okay"; + }; + + sdram2: sdram@d0000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + device_type = "memory"; + reg = <0xd0000000 DT_SIZE_M(32)>; + zephyr,memory-region = "SDRAM2"; + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + }; +}; + +zephyr_udc0: &usbotg_fs { + pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; + pinctrl-names = "default"; + status = "okay"; + + cdc_acm_uart0: cdc_acm_uart0 { + compatible = "zephyr,cdc-acm-uart"; + }; +}; + +&clk_hse { + clock-frequency = ; + hse-bypass; + status = "okay"; +}; + +&clk_lse { + clock-frequency = <32768>; + lse-bypass; + status = "okay"; +}; + +&clk_hsi { + hsi-div = <1>; + status = "okay"; +}; + +&clk_hsi48 { + /* HSI48 required for USB */ + status = "okay"; +}; + +&pll { + div-m = <5>; + mul-n = <160>; + div-p = <2>; + div-r = <2>; + div-q = <10>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + slot0_partition: partition@40000 { + label = "image-0"; + reg = <0x00040000 DT_SIZE_K(768)>; + }; + }; +}; + +&usbotg_fs { + status = "okay"; +}; + +&usbotg_hs { + status = "disabled"; +}; + +&cdc_acm_uart0 { + status = "okay"; +}; + +&mac { + pinctrl-0 = < + ð_ref_clk_pa1 + ð_crs_dv_pa7 + ð_rxd0_pc4 + ð_rxd1_pc5 + ð_tx_en_pg11 + ð_txd1_pg12 + ð_txd0_pg13 + >; + pinctrl-names = "default"; + status = "okay"; +}; + +&mdio { + status = "okay"; + pinctrl-0 = <ð_mdio_pa2 ð_mdc_pc1>; + pinctrl-names = "default"; + + ethernet-phy@0 { + compatible = "ethernet-phy"; + reg = <0x00>; + status = "okay"; + }; +}; + +&rng { + status = "okay"; +}; diff --git a/boards/arduino/opta/arduino_opta_stm32h747xx_m7.yaml b/boards/arduino/opta/arduino_opta_stm32h747xx_m7.yaml new file mode 100644 index 00000000000..5ce1e815a74 --- /dev/null +++ b/boards/arduino/opta/arduino_opta_stm32h747xx_m7.yaml @@ -0,0 +1,22 @@ +identifier: arduino_opta/stm32h747xx/m7 +name: ARDUINO OPTA (M7) +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 512 +flash: 768 +supported: + - gpio + - netif:eth +testing: + ignore_tags: + - mpu + - nfc + - net + - flash + - input + - mcumgr +vendor: arduino diff --git a/boards/arduino/opta/arduino_opta_stm32h747xx_m7_defconfig b/boards/arduino/opta/arduino_opta_stm32h747xx_m7_defconfig new file mode 100644 index 00000000000..a0dd727422e --- /dev/null +++ b/boards/arduino/opta/arduino_opta_stm32h747xx_m7_defconfig @@ -0,0 +1,37 @@ +# Copyright (c) 2023 Felipe Neves +# Copyright (c) 2024 DNDG srl +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Clock configuration +CONFIG_CLOCK_CONTROL=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Use zephyr,code-partition as flash offset +CONFIG_USE_DT_CODE_PARTITION=y + +# Enable correct power supply +CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT_AND_LDO=y + +# Don't start M4 during the M7 boot (this is what the original Opta does) +CONFIG_STM32H7_BOOT_M4_AT_INIT=n + +# Enable console +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_LINE_CTRL=y + +# Enable USB Stack (needed for the console to work) +CONFIG_USB_DEVICE_STACK=y + +# Enable regulator (needed to enable eth) +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED=y diff --git a/boards/arduino/opta/board.cmake b/boards/arduino/opta/board.cmake index 029ae806f4d..af211e0e775 100644 --- a/boards/arduino/opta/board.cmake +++ b/boards/arduino/opta/board.cmake @@ -2,4 +2,17 @@ board_runner_args(dfu-util "--pid=2341:0364" "--alt=0" "--dfuse") +if(CONFIG_BOARD_ARDUINO_OPTA_STM32H747XX_M7) + board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_opta_stm32h747xx_m7.cfg") + board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) +elseif(CONFIG_BOARD_ARDUINO_OPTA_STM32H747XX_M4) + board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_opta_stm32h747xx_m4.cfg") + board_runner_args(openocd --target-handle=_CHIPNAME.cpu1) +endif() + +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") + +# Give priority to dfu-util to flash, ST-Link to debug. include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake) +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) \ No newline at end of file diff --git a/boards/arduino/opta/board_gpio_hse.c b/boards/arduino/opta/board_gpio_hse.c new file mode 100644 index 00000000000..2ee45f52dad --- /dev/null +++ b/boards/arduino/opta/board_gpio_hse.c @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2024 DNDG srl + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +static int board_gpio_hse(void) +{ + /* The external oscillator that drives the HSE clock should be enabled + * by setting the GPIOI1 pin. This function is registered at priority + * RE_KERNEL_1 to be executed before the standard STM clock + * setup code. + */ + + LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOH); + + LL_GPIO_SetPinMode(GPIOH, LL_GPIO_PIN_1, LL_GPIO_MODE_OUTPUT); + LL_GPIO_SetPinSpeed(GPIOH, LL_GPIO_PIN_1, LL_GPIO_SPEED_FREQ_LOW); + LL_GPIO_SetPinOutputType(GPIOH, LL_GPIO_PIN_1, LL_GPIO_OUTPUT_PUSHPULL); + LL_GPIO_SetPinPull(GPIOH, LL_GPIO_PIN_1, LL_GPIO_PULL_UP); + LL_GPIO_SetOutputPin(GPIOH, LL_GPIO_PIN_1); + + return 0; +} + +SYS_INIT(board_gpio_hse, PRE_KERNEL_1, 0); diff --git a/boards/arduino/opta/doc/index.rst b/boards/arduino/opta/doc/index.rst index c50c7e27ec9..01badd338ff 100644 --- a/boards/arduino/opta/doc/index.rst +++ b/boards/arduino/opta/doc/index.rst @@ -1,7 +1,7 @@ .. _arduino_opta_m4_board: -Arduino OPTA M4-Core -#################### +Arduino OPTA +############ Overview ******** @@ -15,14 +15,17 @@ such as Ladder Diagram (LD), Sequential Function Chart (SFC), Function Block Diagram (FBD), Structured Text (ST), and Instruction List (IL), making it an ideal device for automation engineers. -For Zephyr RTOS, only the M4 is supported for now, making the M7 run the PLC -tasks while the M4 core under Zephyr acts as a coprocessor. +For Zephyr RTOS, both cores are supported. It is also possible to run only on +the M4 making the M7 run the PLC tasks while the M4 core under Zephyr acts as +a coprocessor. Additionally, the device features: - Ethernet compliant with IEEE802.3-2002 - 16MB QSPI Flash - 4 x green color status LEDs +- 1 x green or red led over the reset push-button +- 1 x blue led over the user push-button (Opta Advanced only) - 1 x user push-button - 1 x reset push-button accessible via pinhole - 8 x analog inputs @@ -42,7 +45,31 @@ More information about STM32H747XIH6 can be found here: Supported Features ================== -The current Zephyr arduino_opta_m4 board configuration supports the following hardware features: +The ``arduino_opta/stm32h747xx/m7`` board target +supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ +| IPM | on-chip | virtual mailbox based on HSEM | ++-----------+------------+-------------------------------------+ +| USB | on-board | usb-fs | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-board | eth | ++-----------+------------+-------------------------------------+ + +The ``arduino_opta/stm32h747xx/m4`` board target +supports the following hardware features: +-----------+------------+-------------------------------------+ | Interface | Controller | Driver/Component | @@ -62,32 +89,49 @@ The current Zephyr arduino_opta_m4 board configuration supports the following ha Other hardware features are not yet supported on Zephyr porting. -The default configuration per core can be found in the defconfig file: -:zephyr_file:`boards/arduino/opta/arduino_opta_stm32h747xx_m4_defconfig` +The default configuration per core can be found in the defconfig files: +:zephyr_file:`boards/arduino/opta/arduino_opta_stm32h747xx_m4_defconfig` and +:zephyr_file:`boards/arduino/opta/arduino_opta_stm32h747xx_m7_defconfig`. Pin Mapping =========== -ARDUINO OPTA M4 has access to the 9 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. +Both the M7 and M4 cores have access to the 9 GPIO controllers. These +controllers are responsible for pin muxing, input/output, pull-up, etc. For more details please refer to `ARDUINO-OPTA website`_. Default Zephyr Peripheral Mapping --------------------------------- -- Status LED1 : PI0 -- Status LED2 : PI1 -- Status LED3 : PI3 -- Status LED4 : PH15 -- User button : PE4 +- Status LED1: PI0 +- Status LED2: PI1 +- Status LED3: PI3 +- Status LED4: PH15 +- Green "reset" LED: PH12 +- Red "reset" LED: PH11 +- Blue LED: PE5 +- User button: PE4 +- Input 1 : PA0 +- Input 2 : PC2 +- Input 3 : PF12 +- Input 4 : PB0 +- Input 5 : PF10 +- Input 6 : PF8 +- Input 7 : PF6 +- Input 8 : PF4 +- Relay 1: PI6 +- Relay 2: PI5 +- Relay 3: PI7 +- Relay 4: PI4 System Clock ============ The STM32H747I System Clock can be driven by an internal or external oscillator, as well as by the main PLL clock. By default, the CPU2 (Cortex-M4) System clock -is driven at 240MHz. PLL clock is fed by a 25MHz high speed external clock. +is driven at 240MHz. PLL clock is fed by a 25MHz high speed external clock. The +M7 clock is driven at 400MHz. Resources sharing ================= @@ -121,9 +165,30 @@ indicating the board is in bootloader mode. By default: - - CPU2 (Cortex-M4) boot address is set to 0x08180000 (OB: BOOT_CM4_ADD0) + - CPU1 (Cortex-M7) boot address is set to 0x08040000 + - CPU2 (Cortex-M4) boot address is set to 0x08180000 + +Zephyr flash configuration has been set to be compatible with the +"Flash split: 1.5MB M7 + 0.5MB M4" option in the Arduino IDE. The flash is +partitioned as follows: + + - 0x08000000-0x0803FFFF (256k) Arduino MCUboot-derived bootloader + - 0x08040000-0x080FFFFF (768k) M7 application + - 0x08180000-0x081FFFFF (512k) M4 application + + +Flashing an application to ARDUINO OPTA M7 +------------------------------------------ + +First, connect the device to your host computer using +the USB port to prepare it for flashing. Then build and flash your application. + +Here is an example for the :zephyr:code-sample:`blinky` application on M7 core. -Zephyr flash configuration has been set to meet these default settings. +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: arduino_opta/stm32h747xx/m7 + :goals: build flash Flashing an application to ARDUINO OPTA M4 ------------------------------------------ @@ -141,6 +206,9 @@ Here is an example for the :zephyr:code-sample:`blinky` application on M4 core. Starting the application on the ARDUINO OPTA M4 ----------------------------------------------- +If you also flashed an application to M7 the M4 processor is started at boot. +If not you will need to start the processor from an Arduino sketch. + Make sure the option bytes are set to prevent the M4 from auto-starting, and that the M7 side starts the M4 at the correct Flash address. @@ -161,8 +229,9 @@ at least the following code: Debugging ========= -Debugging is not yet supported by this board, since the debug port does -not have an easy access. +The debug port does not have an easy access but it is possible to open the +case and solder a standard 10-pin SWD connector to the board. After that +both flashing and debugging are available via ST-LINK (M7 core only). .. _ARDUINO-OPTA website: https://docs.arduino.cc/hardware/opta diff --git a/boards/arduino/opta/dts/bindings/gpio-power-switches.yaml b/boards/arduino/opta/dts/bindings/gpio-power-switches.yaml new file mode 100644 index 00000000000..580288b2382 --- /dev/null +++ b/boards/arduino/opta/dts/bindings/gpio-power-switches.yaml @@ -0,0 +1,16 @@ +# Copyright (c) 2024 DNDG srl +# SPDX-License-Identifier: Apache-2.0 + +description: | + This allows to define a group of relays (like in the original Opta) + or other kinds of power switches controlled by a GPIO. Each power + switch is defined in a child node of the gpio-power-switches node. + +compatible: "gpio-power-switches" + +child-binding: + description: GPIO power switch child node + properties: + gpios: + type: phandle-array + required: true diff --git a/boards/arduino/opta/support/openocd_opta_stm32h747xx_m7.cfg b/boards/arduino/opta/support/openocd_opta_stm32h747xx_m7.cfg new file mode 100644 index 00000000000..75d441d1809 --- /dev/null +++ b/boards/arduino/opta/support/openocd_opta_stm32h747xx_m7.cfg @@ -0,0 +1,28 @@ + +source [find interface/stlink.cfg] + +transport select hla_swd + +source [find target/stm32h7x.cfg] + +# Use connect_assert_srst here to be able to program +# even when core is in sleep mode +reset_config srst_only srst_nogate connect_assert_srst + +$_CHIPNAME.cpu0 configure -event gdb-attach { + echo "Debugger attaching: halting execution" + gdb_breakpoint_override hard +} + +$_CHIPNAME.cpu0 configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} + +# Due to the use of connect_assert_srst, running gdb requires +# to reset halt just after openocd init. +rename init old_init +proc init {} { + old_init + reset halt +} diff --git a/boards/arduino/portenta_h7/Kconfig.defconfig b/boards/arduino/portenta_h7/Kconfig.defconfig new file mode 100644 index 00000000000..002ff75b5a5 --- /dev/null +++ b/boards/arduino/portenta_h7/Kconfig.defconfig @@ -0,0 +1,43 @@ +# Copyright 2024 Rahul Arasikere +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ARDUINO_PORTENTA_H7 + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +if USB_DEVICE_STACK + +config USB_DEVICE_PRODUCT + default "Arduino SA Portenta H7" + +config USB_DEVICE_PID + default 0x035b + +config USB_DEVICE_VID + default 0x2341 + +config USB_DEVICE_INITIALIZE_AT_BOOT + default y + +if LOG + +# Logger cannot use itself to log +choice USB_CDC_ACM_LOG_LEVEL_CHOICE + default USB_CDC_ACM_LOG_LEVEL_OFF +endchoice + +# Set USB log level to error only +choice USB_DEVICE_LOG_LEVEL_CHOICE + default USB_DEVICE_LOG_LEVEL_ERR +endchoice + +endif # LOG + +endif # USB_DEVICE_STACK + +endif # BOARD_ARDUINO_PORTENTA_H7 diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7-common.dtsi b/boards/arduino/portenta_h7/arduino_portenta_h7-common.dtsi index 87d85f27263..e030d9d1cd0 100644 --- a/boards/arduino/portenta_h7/arduino_portenta_h7-common.dtsi +++ b/boards/arduino/portenta_h7/arduino_portenta_h7-common.dtsi @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { leds { compatible = "gpio-leds"; @@ -18,6 +20,12 @@ }; }; + otghs_ulpi_phy: otghs_ulpis_phy { + compatible = "usb-ulpi-phy"; + reset-gpios = < &gpioj 4 GPIO_ACTIVE_LOW >; + #phy-cells = <0>; + }; + aliases { led0 = &red_led; led1 = &green_led; @@ -31,12 +39,12 @@ }; &rcc { - d1cpre = <1>; - hpre = <1>; - d1ppre = <1>; - d2ppre1 = <1>; - d2ppre2 = <2>; - d3ppre = <1>; + d1cpre = < 1 >; + hpre = < 2 >; + d1ppre = < 2 >; + d2ppre1 = < 2 >; + d2ppre2 = < 2 >; + d3ppre = < 2 >; }; /* UART0 in datasheet */ @@ -113,12 +121,129 @@ status = "okay"; }; -zephyr_udc0: &usbotg_fs { - pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; +&mailbox { + status = "okay"; +}; + +&fmc { + status = "okay"; + pinctrl-0 = < &fmc_d2_pd0 &fmc_d3_pd1 &fmc_d13_pd8 &fmc_d14_pd9 + &fmc_d15_pd10 &fmc_d0_pd14 &fmc_d1_pd15 &fmc_nbl0_pe0 + &fmc_nbl1_pe1 &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9 + &fmc_d7_pe10 &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13 + &fmc_d11_pe14 &fmc_d12_pe15 &fmc_a0_pf0 &fmc_a1_pf1 + &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4 &fmc_a5_pf5 + &fmc_sdnras_pf11 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14 + &fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1 &fmc_a12_pg2 + &fmc_a14_pg4 /* FMC_BA0 */ &fmc_a15_pg5 /* FMC_BA1 */ + &fmc_sdclk_pg8 &fmc_sdncas_pg15 &fmc_sdcke0_ph2 &fmc_sdne0_ph3 + &fmc_sdnwe_ph5 >; pinctrl-names = "default"; - status = "disabled"; + st,mem-swap = "disable"; + sdram { + status = "okay"; + mode-register = < 0x220 >; + + /** From Arduino github repository: + * RefreshRate = 64 ms / 8192 cyc = 7.8125 us/cyc + * RefreshCycles = 7.8125 us * 90 MHz = 703 + * According to the formula on p.1665 of the reference manual, + * we also need to subtract 20 from the value, so the target + * refresh rate is 703 - 20 = 683. + */ + refresh-rate = < 683 >; + num-auto-refresh = < 8 >; + + bank@0 { + reg = < 0 >; + st,sdram-control = < STM32_FMC_SDRAM_NC_8 + STM32_FMC_SDRAM_NR_12 + STM32_FMC_SDRAM_MWID_16 + STM32_FMC_SDRAM_NB_4 + STM32_FMC_SDRAM_CAS_2 + STM32_FMC_SDRAM_SDCLK_PERIOD_2 + STM32_FMC_SDRAM_RBURST_ENABLE + STM32_FMC_SDRAM_RPIPE_0 >; + st,sdram-timing = < 2 7 5 7 2 3 3 >; + }; + }; }; -&mailbox { +&quadspi { + pinctrl-0 = < &quadspi_bk1_io0_pd11 + &quadspi_bk1_io1_pd12 + &quadspi_bk1_io2_pf7 + &quadspi_bk1_io3_pd13 + &quadspi_bk1_ncs_pg6 + &quadspi_clk_pf10 >; + pinctrl-names = "default"; status = "okay"; + + mx25l12833f: qspi-nor-flash@90000000 { + compatible = "st,stm32-qspi-nor"; + reg = < 0x90000000 DT_SIZE_M(16) >; /* 128 MBits */ + qspi-max-frequency = < 40000000 >; + sfdp-bfp = [ e5 20 f1 ff ff ff ff 07 44 eb 08 6b 08 3b 04 bb + fe ff ff ff ff ff 00 ff ff ff 44 eb 0c 20 0f 52 + 10 d8 00 ff 82 41 bd 00 81 e5 7b c6 44 03 67 38 + 30 b0 30 b0 f7 bd d5 5c 4a be 29 ff e1 d0 ff ff ]; + jedec-id = [ 66 66 20 ]; + spi-bus-width = <4>; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = < 1 >; + #size-cells = < 1 >; + + storage_partition: partition@0 { + label = "storage"; + reg=< 0x0 DT_SIZE_K(15872) >; + }; + + wifi_firmware: partition@f80000 { + label = "wifi-firmware"; + reg = < 0xf80000 DT_SIZE_K(512) >; + }; + }; + }; +}; + +&mac { + pinctrl-0 = < ð_ref_clk_pa1 + ð_mdio_pa2 + ð_crs_dv_pa7 + ð_mdc_pc1 + ð_rxd0_pc4 + ð_rxd1_pc5 + ð_tx_en_pg11 + ð_txd1_pg12 + ð_txd0_pg13 >; + pinctrl-names = "default"; +}; + +zephyr_udc0: &usbotg_hs { + pinctrl-0 = < &usb_otg_hs_ulpi_d0_pa3 + &usb_otg_hs_ulpi_ck_pa5 + &usb_otg_hs_ulpi_d1_pb0 + &usb_otg_hs_ulpi_d2_pb1 + &usb_otg_hs_ulpi_d7_pb5 + &usb_otg_hs_ulpi_d3_pb10 + &usb_otg_hs_ulpi_d4_pb11 + &usb_otg_hs_ulpi_d5_pb12 + &usb_otg_hs_ulpi_d6_pb13 + &usb_otg_hs_ulpi_stp_pc0 + &usb_otg_hs_ulpi_nxt_ph4 + &usb_otg_hs_ulpi_dir_pi11 >; + pinctrl-names = "default"; + phys = < &otghs_ulpi_phy >; + maximum-speed = "high-speed"; + /* Include the USB1ULPIEN | USB1OTGHSULPIEN clock enable bit */ + clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x6000000>, + <&rcc STM32_SRC_HSI48 USB_SEL(3)>; + num-bidir-endpoints = < 4 >; + status = "okay"; + cdc_acm_uart0: cdc_acm_uart0 { + compatible = "zephyr,cdc-acm-uart"; + }; }; diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4.dts b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4.dts index e214fbdecd4..12190a28715 100644 --- a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4.dts +++ b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4.dts @@ -24,7 +24,7 @@ }; &rcc { - clock-frequency = ; + clock-frequency = ; }; &usart1 { diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4.yaml b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4.yaml index afbca313573..352ae2b3cce 100644 --- a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4.yaml +++ b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4.yaml @@ -14,4 +14,5 @@ testing: ignore_tags: - mpu - nfc + - flash vendor: arduino diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4_defconfig b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4_defconfig index 4929eecabb7..8a931846ae7 100644 --- a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4_defconfig +++ b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4_defconfig @@ -4,18 +4,12 @@ # Enable GPIO CONFIG_GPIO=y -# Clock configuration -CONFIG_CLOCK_CONTROL=y - # Enable MPU CONFIG_ARM_MPU=y # Enable HW stack protection CONFIG_HW_STACK_PROTECTION=y -# Enable pin controller -CONFIG_PINCTRL=y - # Enable uart driver # CONFIG_SERIAL=y diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.dts b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.dts index 4ad43a01c1c..4b43bb6cbd4 100644 --- a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.dts +++ b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.dts @@ -15,11 +15,12 @@ /* HW resources are split between CM7 and CM4 */ chosen { - zephyr,console = &usart1; - zephyr,shell-uart = &usart1; + zephyr,console = &cdc_acm_uart0; + zephyr,shell-uart = &cdc_acm_uart0; + zephyr,cdc-acm-uart0 = &cdc_acm_uart0; zephyr,sram = &sram0; zephyr,flash = &flash0; - zephyr,code-partition = &code_partition; + zephyr,code-partition = &slot0_partition; }; oscen: oscen { @@ -27,27 +28,56 @@ regulator-name = "oscen"; enable-gpios = <&gpioh 1 GPIO_ACTIVE_HIGH>; regulator-boot-on; + status = "okay"; + }; + + ethernet_phy_en: ethernet_phy_en { + compatible = "regulator-fixed"; + regulator-name = "ethernet-phy-reset-release"; + enable-gpios = <&gpioj 15 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + status = "okay"; + }; + + sdram1: sdram@c0000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + device_type = "memory"; + reg = <0xc0000000 DT_SIZE_M(8)>; + zephyr,memory-region = "SDRAM1"; + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; }; }; +&clk_hse { + clock-frequency = ; + hse-bypass; + status = "okay"; +}; + &clk_hsi { - hsi-div = <8>; + hsi-div = <1>; status = "okay"; }; &pll { - div-m = <1>; - mul-n = <24>; + div-m = <5>; + mul-n = <160>; div-p = <2>; - div-q = <4>; + div-q = <10>; div-r = <2>; - clocks = <&clk_hsi>; + clocks = <&clk_hse>; status = "okay"; }; +/** The power supply for the Portenta H7 is based on a ST PSU reference design. + * The design specification from this reference design limits the maximum + * clock speed to 400 MHz. + * Refer: section 8.1 of the reference design guide. + */ + &rcc { clocks = <&pll>; - clock-frequency = ; + clock-frequency = ; }; @@ -59,7 +89,16 @@ status = "okay"; }; +/* Only one should be enabled */ &usbotg_fs { + status = "disabled"; +}; + +&usbotg_hs { + status = "okay"; +}; + +&cdc_acm_uart0 { status = "okay"; }; @@ -70,27 +109,31 @@ #size-cells = <1>; boot_partition: partition@0 { - label = "bootloader"; - reg = <0x0 0x00040000>; + label = "mcuboot"; + reg = <0x00000000 0x00010000>; read-only; }; - - code_partition: partition@40000 { - label = "code"; - reg = <0x40000 0x000c0000>; - read-only; - }; - /* - * The flash starting at 0x000f8000 and ending at - * 0x000fffff is reserved for use by the application. - * - * Storage partition will be used by FCB/LittleFS/NVS - * if enabled. + * The flash starting at 0x00010000 and ending at + * 0x0001ffff (sectors 16-31) is reserved for use + * by the application. */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; + scratch_partition: partition@10000 { + label = "image-scratch"; + reg = <0x00010000 0x00030000>; + }; + /* The arduino default bootloader occupies the address space 0x0 - 0x40000. + * This way regardless of the user's choice to use the mcuboot bootloader, + * applications will be located at 0x40000 which will be loaded by the + * arduino bootloader. + */ + slot0_partition: partition@40000 { + label = "image-0"; + reg = <0x00040000 0x00060000>; + }; + slot1_partition: partition@A0000 { + label = "image-1"; + reg = <0x000A0000 0x00060000>; }; }; }; diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_1_0_0.overlay b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_1_0_0.overlay new file mode 100644 index 00000000000..3eaba44b34c --- /dev/null +++ b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_1_0_0.overlay @@ -0,0 +1,9 @@ +/** + * Copyright (c) 2024 Rahul Arasikere . + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&clk_lsi { + status = "okay"; +}; diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_4_10_0.overlay b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_4_10_0.overlay new file mode 100644 index 00000000000..2d8e886fdea --- /dev/null +++ b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_4_10_0.overlay @@ -0,0 +1,10 @@ +/** + * Copyright (c) 2024 Rahul Arasikere . + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&clk_lse { + clock-frequency = <32768>; + status = "okay"; +}; diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_defconfig b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_defconfig index 18f533bf91d..ff4b2954d02 100644 --- a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_defconfig +++ b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_defconfig @@ -7,18 +7,12 @@ CONFIG_POWER_SUPPLY_DIRECT_SMPS=y # Enable GPIO CONFIG_GPIO=y -# Enable clocks -CONFIG_CLOCK_CONTROL=y - # Enable MPU CONFIG_ARM_MPU=y # Enable HW stack protection CONFIG_HW_STACK_PROTECTION=y -# enable pin controller -CONFIG_PINCTRL=y - # Use zephyr,code-partition as flash offset CONFIG_USE_DT_CODE_PARTITION=y @@ -30,7 +24,11 @@ CONFIG_SERIAL=y # Enable console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y +CONFIG_UART_LINE_CTRL=y # Enable regulator CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED=y + +# Enable USB Stack +CONFIG_USB_DEVICE_STACK=y diff --git a/boards/arduino/portenta_h7/board.yml b/boards/arduino/portenta_h7/board.yml index be2ba58da96..01e28f0b5fd 100644 --- a/boards/arduino/portenta_h7/board.yml +++ b/boards/arduino/portenta_h7/board.yml @@ -3,3 +3,9 @@ board: vendor: arduino socs: - name: stm32h747xx + revision: + format: major.minor.patch + default: 1.0.0 + revisions: + - name: 1.0.0 + - name: 4.10.0 diff --git a/boards/arduino/portenta_h7/doc/index.rst b/boards/arduino/portenta_h7/doc/index.rst index 87b7aefdfe5..3ed69927f4f 100644 --- a/boards/arduino/portenta_h7/doc/index.rst +++ b/boards/arduino/portenta_h7/doc/index.rst @@ -15,6 +15,7 @@ with 2MBytes of Flash memory, 1MB RAM, 480 MHz CPU, Art Accelerator, L1 cache, e large set of peripherals, SMPS, and MIPI-DSI. Additionally, the board features: + - USB OTG FS - 3 color user LEDs @@ -56,9 +57,23 @@ The current Zephyr arduino_portenta_h7 board configuration supports the followin +-----------+------------+-------------------------------------+ | IPM | on-chip | virtual mailbox based on HSEM | +-----------+------------+-------------------------------------+ +| EXTFLASH | on-chip | qspi | ++-----------+------------+-------------------------------------+ +| SDRAM | on-chip | sdram | ++-----------+------------+-------------------------------------+ +| USB | on-board | usb-hs | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-board | eth | ++-----------+------------+-------------------------------------+ Other hardware features are not yet supported on Zephyr porting. +The high precision low speed external (LSE) clock is only fully supported on +boards with hardware revision 4.10 or greater. By default the internal source +is used; to enable the use of the external oscillator, manually specify the +hardware revision at build time (see :ref:`application_board_version` for +information on how to build for specific revisions of the board). + Resources sharing ================= @@ -99,7 +114,7 @@ First, connect the Arduino Portenta H7 board to your host computer using the USB port to prepare it for flashing. Double tap the button to put the board into the Arduino Bootloader mode. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/arduino/uno_r4/arduino_uno_r4_common.dtsi b/boards/arduino/uno_r4/arduino_uno_r4_common.dtsi index 13ec82502c2..6a81cec8b7d 100644 --- a/boards/arduino/uno_r4/arduino_uno_r4_common.dtsi +++ b/boards/arduino/uno_r4/arduino_uno_r4_common.dtsi @@ -10,7 +10,7 @@ / { model = "Arduino Uno R4 Board"; - compatible = "renesas,r7fa4m1aB3cfm"; + compatible = "renesas,r7fa4m1ab3cfm"; chosen { zephyr,console = &uart2; diff --git a/boards/arduino/zero/doc/index.rst b/boards/arduino/zero/doc/index.rst index 46eb837040c..3ec0a0fd82a 100644 --- a/boards/arduino/zero/doc/index.rst +++ b/boards/arduino/zero/doc/index.rst @@ -118,7 +118,7 @@ OpenOCD. Flashing ======== -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/arm/fvp_base_revc_2xaemv8a/doc/index.rst b/boards/arm/fvp_base_revc_2xaemv8a/doc/index.rst index 495b7ad11f4..81a098b3ae1 100644 --- a/boards/arm/fvp_base_revc_2xaemv8a/doc/index.rst +++ b/boards/arm/fvp_base_revc_2xaemv8a/doc/index.rst @@ -99,7 +99,7 @@ Checkout and Build the TF-A: cd trusted-firmware-a/ make PLAT=fvp PRELOADED_BL33_BASE="0x88000000" all fip -then export the ``ARMFVP_BL1_FILE` and ``ARMFVP_FIP_FILE`` environment variables: +then export the :envvar:`ARMFVP_BL1_FILE` and :envvar:`ARMFVP_FIP_FILE` environment variables: .. code-block:: console diff --git a/boards/arm/mps2/doc/mps2_an385.rst b/boards/arm/mps2/doc/mps2_an385.rst index ffd8942dbfd..79f01dc9c53 100644 --- a/boards/arm/mps2/doc/mps2_an385.rst +++ b/boards/arm/mps2/doc/mps2_an385.rst @@ -253,7 +253,7 @@ V2M MPS2 provides: Flashing an application to V2M MPS2 ----------------------------------- -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/arm/mps2/doc/mps2_an521.rst b/boards/arm/mps2/doc/mps2_an521.rst index 7149902b0db..33a4f4d7ca6 100644 --- a/boards/arm/mps2/doc/mps2_an521.rst +++ b/boards/arm/mps2/doc/mps2_an521.rst @@ -489,7 +489,7 @@ MPS2+ AN521 provides: - A Serial Port which is J10 on MPS2+ board Build applications as described above. -Here is an example for the :ref:`hello_world` application built as +Here is an example for the :zephyr:code-sample:`hello_world` application built as a secure-only application for CPU0. .. zephyr-app-commands:: diff --git a/boards/arm/mps2/mps2_an385.dts b/boards/arm/mps2/mps2_an385.dts index e0046f4dff1..d2db1cebed0 100644 --- a/boards/arm/mps2/mps2_an385.dts +++ b/boards/arm/mps2/mps2_an385.dts @@ -73,6 +73,33 @@ reg = <0 0x400000>; }; + sim_flash_controller: sim_flash_controller { + compatible = "zephyr,sim-flash"; + + #address-cells = <1>; + #size-cells = <1>; + erase-value = <0x00>; + + flash_sim0: flash_sim@0 { + compatible = "soc-nv-flash"; + reg = <0x00000000 0x8000>; + + erase-block-size = <1024>; + write-block-size = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@0 { + label = "storage_partition"; + reg = <0x00000000 0x8000>; + }; + }; + }; + }; + sysclk: system-clock { compatible = "fixed-clock"; clock-frequency = <25000000>; diff --git a/boards/arm/mps2/mps2_an385.yaml b/boards/arm/mps2/mps2_an385.yaml index 7ad92b98996..7bda3fc3dcc 100644 --- a/boards/arm/mps2/mps2_an385.yaml +++ b/boards/arm/mps2/mps2_an385.yaml @@ -11,6 +11,7 @@ supported: - counter - netif:serial-net - gpio + - watchdog testing: default: true vendor: arm diff --git a/boards/arm/mps2/mps2_an521_cpu0_ns.yaml b/boards/arm/mps2/mps2_an521_cpu0_ns.yaml index b5dcadf7fe9..6a24f388785 100644 --- a/boards/arm/mps2/mps2_an521_cpu0_ns.yaml +++ b/boards/arm/mps2/mps2_an521_cpu0_ns.yaml @@ -14,6 +14,5 @@ testing: only_tags: - arm - kernel - - tfm - userspace - trusted-firmware-m diff --git a/boards/arm/mps3/doc/index.rst b/boards/arm/mps3/doc/index.rst index 530999206d4..e618b9a714c 100644 --- a/boards/arm/mps3/doc/index.rst +++ b/boards/arm/mps3/doc/index.rst @@ -142,7 +142,7 @@ Building an application ----------------------- You can build applications in the usual way. Here is an example for -the :ref:`hello_world` application. +the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/arm/mps3/mps3_an547.dts b/boards/arm/mps3/mps3_an547.dts index 50700e8278e..8b6585a13e2 100644 --- a/boards/arm/mps3/mps3_an547.dts +++ b/boards/arm/mps3/mps3_an547.dts @@ -132,8 +132,9 @@ }; sram: sram@11000000 { /* alias @ 0x01000000 */ - compatible = "mmio-sram"; + compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x11000000 DT_SIZE_M(2)>; + zephyr,memory-region = "SRAM"; }; dtcm: dtcm@30000000 { /* alias @ 0x20000000 */ @@ -143,8 +144,9 @@ }; isram: sram@31000000 {/* alias @ 0x21000000 */ - compatible = "mmio-sram"; + compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x31000000 DT_SIZE_M(4)>; + zephyr,memory-region = "ISRAM"; }; /* DDR4 - 2G, alternates non-secure/secure every 256M */ diff --git a/boards/arm/mps3/mps3_an547_ns.dts b/boards/arm/mps3/mps3_an547_ns.dts index dd8c9c4571c..1c6a0fc2605 100644 --- a/boards/arm/mps3/mps3_an547_ns.dts +++ b/boards/arm/mps3/mps3_an547_ns.dts @@ -77,27 +77,34 @@ /* We utilize the secure addresses, if you subtract 0x10000000 * you'll get the non-secure alias */ - itcm: itcm@10000000 { /* alias @ 0x0 */ - reg = <0x10000000 DT_SIZE_K(512)>; + itcm: itcm@0 { + compatible = "zephyr,memory-region"; + reg = <0x0 DT_SIZE_K(512)>; + zephyr,memory-region = "ITCM"; }; - sram: sram@1000000 { /* alias @ 0x11000000 */ - compatible = "mmio-sram"; + sram: sram@1000000 { + compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x1000000 DT_SIZE_M(2)>; + zephyr,memory-region = "SRAM"; }; - dtcm: dtcm@20000000 { /* alias @ 0x30000000 */ + dtcm: dtcm@20000000 { + compatible = "zephyr,memory-region"; reg = <0x20000000 DT_SIZE_K(512)>; + zephyr,memory-region = "DTCM"; }; - isram: sram@31000000 {/* alias @ 0x21000000 */ - compatible = "mmio-sram"; - reg = <0x31000000 DT_SIZE_M(4)>; + isram: sram@21000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x21000000 DT_SIZE_M(4)>; + zephyr,memory-region = "ISRAM"; }; /* DDR4 - 2G, alternates non-secure/secure every 256M */ ddr4: memory@60000000 { device_type = "memory"; + compatible = "zephyr,memory-region"; reg = <0x60000000 DT_SIZE_M(256) 0x70000000 DT_SIZE_M(256) 0x80000000 DT_SIZE_M(256) @@ -106,6 +113,7 @@ 0xb0000000 DT_SIZE_M(256) 0xc0000000 DT_SIZE_M(256) 0xd0000000 DT_SIZE_M(256)>; + zephyr,memory-region = "DDR4"; }; reserved-memory { diff --git a/boards/arm/mps3/mps3_an547_ns.yaml b/boards/arm/mps3/mps3_an547_ns.yaml index 3852415834f..e58f636b555 100644 --- a/boards/arm/mps3/mps3_an547_ns.yaml +++ b/boards/arm/mps3/mps3_an547_ns.yaml @@ -18,4 +18,4 @@ toolchain: testing: default: true only_tags: - - tfm + - trusted-firmware-m diff --git a/boards/arm/v2m_beetle/doc/index.rst b/boards/arm/v2m_beetle/doc/index.rst index 7673e510ebf..49df438d3f9 100644 --- a/boards/arm/v2m_beetle/doc/index.rst +++ b/boards/arm/v2m_beetle/doc/index.rst @@ -229,7 +229,7 @@ Flashing an application to V2M Beetle ------------------------------------- You can build applications in the usual way. Here is an example for -the :ref:`hello_world` application. +the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/arm/v2m_beetle/support/openocd.cfg b/boards/arm/v2m_beetle/support/openocd.cfg index e1d1062ca08..36004576d09 100644 --- a/boards/arm/v2m_beetle/support/openocd.cfg +++ b/boards/arm/v2m_beetle/support/openocd.cfg @@ -22,7 +22,7 @@ if { [info exists CPUTAPID] } { set _CPUTAPID 0x2ba01477 } -adapter_khz 1000 +adapter speed 1000 set _TARGETNAME $_CHIPNAME.cpu diff --git a/boards/arm/v2m_musca_b1/doc/index.rst b/boards/arm/v2m_musca_b1/doc/index.rst index 0a7d41ac883..cb9aa61a0fd 100644 --- a/boards/arm/v2m_musca_b1/doc/index.rst +++ b/boards/arm/v2m_musca_b1/doc/index.rst @@ -308,7 +308,7 @@ Building a secure only application You can build applications in the usual way. Here is an example for -the :ref:`hello_world` application. +the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/arm/v2m_musca_s1/doc/index.rst b/boards/arm/v2m_musca_s1/doc/index.rst index 7072ef7e219..86806891295 100644 --- a/boards/arm/v2m_musca_s1/doc/index.rst +++ b/boards/arm/v2m_musca_s1/doc/index.rst @@ -301,7 +301,7 @@ Building a secure only application ---------------------------------- You can build applications in the usual way. Here is an example for -the :ref:`hello_world` application. +the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -318,7 +318,7 @@ Open a serial terminal (minicom, putty, etc.) with the following settings: Uploading an application to V2M Musca-S1 ---------------------------------------- -To upload the :ref:`hello_world` application to the board, no extra steps are +To upload the :zephyr:code-sample:`hello_world` application to the board, no extra steps are required. You can directly upload ``build/zephyr/zephyr.hex``, which is generated by Zephyr's build system. diff --git a/boards/atmarktechno/degu_evk/Kconfig b/boards/atmarktechno/degu_evk/Kconfig deleted file mode 100644 index ea240584485..00000000000 --- a/boards/atmarktechno/degu_evk/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Degu Evaluation Kit configuration - -# Copyright (c) 2019 Atmark Techno, Inc. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_DEGU_EVK diff --git a/boards/atmarktechno/degu_evk/degu_evk.dts b/boards/atmarktechno/degu_evk/degu_evk.dts index eb3329726e9..e9d579bd367 100644 --- a/boards/atmarktechno/degu_evk/degu_evk.dts +++ b/boards/atmarktechno/degu_evk/degu_evk.dts @@ -88,6 +88,10 @@ }; }; +®1 { + regulator-initial-mode = ; +}; + &adc { status ="okay"; }; diff --git a/boards/atmel/sam/sam4e_xpro/doc/index.rst b/boards/atmel/sam/sam4e_xpro/doc/index.rst index 18d0836c6d6..b01e60cd56d 100644 --- a/boards/atmel/sam/sam4e_xpro/doc/index.rst +++ b/boards/atmel/sam/sam4e_xpro/doc/index.rst @@ -122,7 +122,7 @@ Using OpenOCD ------------- #. Connect the SAM4E Xplained Pro board to your host computer using the USB - debug port. Then build and flash the :ref:`hello_world` application. + debug port. Then build and flash the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -138,7 +138,7 @@ Using SAM-BA bootloader #. Open the ``ERASE`` jumper. #. Connect the SAM4E Xplained Pro board to your host computer using the SoC - USB port. Then build and flash the :ref:`hello_world` application. + USB port. Then build and flash the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -175,7 +175,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/atmel/sam/sam4l_ek/doc/index.rst b/boards/atmel/sam/sam4l_ek/doc/index.rst index a28b0728836..f3e4e27d376 100644 --- a/boards/atmel/sam/sam4l_ek/doc/index.rst +++ b/boards/atmel/sam/sam4l_ek/doc/index.rst @@ -140,7 +140,7 @@ Flashing - Stop bits: 1 #. Connect the SAM4L-EK board to your host computer using the USB debug port. - Then build and flash the :ref:`hello_world` application. + Then build and flash the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -153,7 +153,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/atmel/sam/sam4s_xplained/doc/index.rst b/boards/atmel/sam/sam4s_xplained/doc/index.rst index 9c1b999eca9..a5276bd6716 100644 --- a/boards/atmel/sam/sam4s_xplained/doc/index.rst +++ b/boards/atmel/sam/sam4s_xplained/doc/index.rst @@ -111,7 +111,7 @@ Using JLink accessible from your path. #. Connect the SAM4S Xplained board to your host computer using the USB debug - port. Then build and flash the :ref:`hello_world` application. + port. Then build and flash the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -128,7 +128,7 @@ Using SAM-BA bootloader #. Open the ``J25`` jumper. #. Connect the SAM4S Xplained board to your host computer using the SoC USB - port. Then build and flash the :ref:`hello_world` application. + port. Then build and flash the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -167,7 +167,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/atmel/sam/sam_e70_xplained/doc/index.rst b/boards/atmel/sam/sam_e70_xplained/doc/index.rst index bab33f538c4..67b90d42c59 100644 --- a/boards/atmel/sam/sam_e70_xplained/doc/index.rst +++ b/boards/atmel/sam/sam_e70_xplained/doc/index.rst @@ -141,7 +141,7 @@ Flashing - Stop bits: 1 #. Connect the SAM E70 Xplained board to your host computer using the - USB debug port. Then build and flash the :ref:`hello_world` + USB debug port. Then build and flash the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -171,7 +171,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained-common.dtsi b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained-common.dtsi index ded3866acfe..d6190e050f9 100644 --- a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained-common.dtsi +++ b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained-common.dtsi @@ -210,3 +210,31 @@ zephyr_udc0: &usbhs { max-bitrate = <5000000>; }; }; + +&tc0 { + qdec0: qdec { + pinctrl-0 = <&qdec0_default>; + pinctrl-names = "default"; + }; +}; + +&tc1 { + qdec1: qdec { + pinctrl-0 = <&qdec1_default>; + pinctrl-names = "default"; + }; +}; + +&tc2 { + qdec2: qdec { + pinctrl-0 = <&qdec2_default>; + pinctrl-names = "default"; + }; +}; + +&tc3 { + qdec3: qdec { + pinctrl-0 = <&qdec3_default>; + pinctrl-names = "default"; + }; +}; diff --git a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained-pinctrl.dtsi b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained-pinctrl.dtsi index e41db2f1c55..443bb39651f 100644 --- a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained-pinctrl.dtsi +++ b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained-pinctrl.dtsi @@ -76,28 +76,28 @@ }; }; - tc0_qdec_default: tc0_qdec_default { + qdec0_default: qdec0_default { group1 { pinmux = , ; }; }; - tc1_qdec_default: tc1_qdec_default { + qdec1_default: qdec1_default { group1 { pinmux = , ; }; }; - tc2_qdec_default: tc2_qdec_default { + qdec2_default: qdec2_default { group1 { pinmux = , ; }; }; - tc3_qdec_default: tc3_qdec_default { + qdec3_default: qdec3_default { group1 { pinmux = , ; diff --git a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.dts b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.dts index 64a26cecc88..d96e5083d5b 100644 --- a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.dts +++ b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.dts @@ -15,35 +15,3 @@ model = "Atmel SAM E70 Xplained board"; compatible = "atmel,sam_e70_xplained", "atmel,same70q21", "atmel,same70"; }; - -&tc0 { - status = "okay"; - compatible = "atmel,sam-tc-qdec"; - - pinctrl-0 = <&tc0_qdec_default>; - pinctrl-names = "default"; -}; - -&tc1 { - status = "disabled"; - compatible = "atmel,sam-tc-qdec"; - - pinctrl-0 = <&tc1_qdec_default>; - pinctrl-names = "default"; -}; - -&tc2 { - status = "disabled"; - compatible = "atmel,sam-tc-qdec"; - - pinctrl-0 = <&tc2_qdec_default>; - pinctrl-names = "default"; -}; - -&tc3 { - status = "disabled"; - compatible = "atmel,sam-tc-qdec"; - - pinctrl-0 = <&tc3_qdec_default>; - pinctrl-names = "default"; -}; diff --git a/boards/atmel/sam/sam_v71_xult/doc/index.rst b/boards/atmel/sam/sam_v71_xult/doc/index.rst index e0b5fce6c04..7ce56d58a70 100644 --- a/boards/atmel/sam/sam_v71_xult/doc/index.rst +++ b/boards/atmel/sam/sam_v71_xult/doc/index.rst @@ -144,7 +144,7 @@ Flashing - Stop bits: 1 #. Connect the SAM V71 Xplained Ultra board to your host computer using the - USB debug port. Then build and flash the :ref:`hello_world` + USB debug port. Then build and flash the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -174,7 +174,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/atmel/sam0/samd20_xpro/doc/index.rst b/boards/atmel/sam0/samd20_xpro/doc/index.rst index b0dbff28229..7b788cbbf73 100644 --- a/boards/atmel/sam0/samd20_xpro/doc/index.rst +++ b/boards/atmel/sam0/samd20_xpro/doc/index.rst @@ -110,7 +110,7 @@ OpenOCD. Flashing ======== -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/atmel/sam0/samd21_xpro/samd21_xpro.yaml b/boards/atmel/sam0/samd21_xpro/samd21_xpro.yaml index d5e6a725003..c41c9443285 100644 --- a/boards/atmel/sam0/samd21_xpro/samd21_xpro.yaml +++ b/boards/atmel/sam0/samd21_xpro/samd21_xpro.yaml @@ -20,7 +20,6 @@ supported: - pwm - spi - uart - - usb_cdc - usb_device - watchdog vendor: atmel diff --git a/boards/atmel/sam0/saml21_xpro/saml21_xpro.yaml b/boards/atmel/sam0/saml21_xpro/saml21_xpro.yaml index 3d531f66287..be39f0dc517 100644 --- a/boards/atmel/sam0/saml21_xpro/saml21_xpro.yaml +++ b/boards/atmel/sam0/saml21_xpro/saml21_xpro.yaml @@ -20,7 +20,6 @@ supported: - pwm - spi - uart - - usb_cdc - usb_device - watchdog vendor: atmel diff --git a/boards/atmel/sam0/samr21_xpro/doc/index.rst b/boards/atmel/sam0/samr21_xpro/doc/index.rst index 1172f8a3f98..91a47615b9a 100644 --- a/boards/atmel/sam0/samr21_xpro/doc/index.rst +++ b/boards/atmel/sam0/samr21_xpro/doc/index.rst @@ -159,8 +159,8 @@ externally connected SPI devices. +-------------+------------------------------------------------------------------------------------------+ Zephyr provide several samples that can use this technology. You can check -:zephyr:code-sample:`wpan-usb` and :zephyr:code-sample:`wpan-serial` examples as starting -points. Another good test can be done with IPv6 by using the server/client +:zephyr:code-sample:`wpan-serial` example as starting points. +Another good test can be done with IPv6 by using the server/client echo demo. More information at :zephyr:code-sample:`sockets-echo-server` and :zephyr:code-sample:`sockets-echo-client`. @@ -174,7 +174,7 @@ OpenOCD. Flashing ======== -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/atmel/sam0/samr34_xpro/samr34_xpro.yaml b/boards/atmel/sam0/samr34_xpro/samr34_xpro.yaml index be66ff6cde5..488fba3bb32 100644 --- a/boards/atmel/sam0/samr34_xpro/samr34_xpro.yaml +++ b/boards/atmel/sam0/samr34_xpro/samr34_xpro.yaml @@ -20,7 +20,6 @@ supported: - pwm - spi - uart - - usb_cdc - usb_device - watchdog vendor: atmel diff --git a/boards/bbc/microbit/doc/index.rst b/boards/bbc/microbit/doc/index.rst index aa36d3d662b..c4d11f7a671 100644 --- a/boards/bbc/microbit/doc/index.rst +++ b/boards/bbc/microbit/doc/index.rst @@ -77,7 +77,7 @@ Flashing Build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/bbc/microbit_v2/doc/index.rst b/boards/bbc/microbit_v2/doc/index.rst index 7c94a3e5a4e..d906f13660b 100644 --- a/boards/bbc/microbit_v2/doc/index.rst +++ b/boards/bbc/microbit_v2/doc/index.rst @@ -71,7 +71,7 @@ Flashing Build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/bcdevices/plt_demo_v2/Kconfig b/boards/bcdevices/plt_demo_v2/Kconfig deleted file mode 100644 index 7f18564b1e6..00000000000 --- a/boards/bcdevices/plt_demo_v2/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Blue Clover PLT Demo V2 Configuration - -# Copyright (c) 2021 Blue Clover -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_BLUECLOVER_PLT_DEMO_V2_NRF52832 diff --git a/boards/bcdevices/plt_demo_v2/blueclover_plt_demo_v2_nrf52832.dts b/boards/bcdevices/plt_demo_v2/blueclover_plt_demo_v2_nrf52832.dts index 245b2eb1aad..f7328181109 100644 --- a/boards/bcdevices/plt_demo_v2/blueclover_plt_demo_v2_nrf52832.dts +++ b/boards/bcdevices/plt_demo_v2/blueclover_plt_demo_v2_nrf52832.dts @@ -50,6 +50,10 @@ }; }; +® { + regulator-initial-mode = ; +}; + &uicr { gpio-as-nreset; }; diff --git a/boards/bcdevices/plt_demo_v2/doc/index.rst b/boards/bcdevices/plt_demo_v2/doc/index.rst index 8dfc2c9527b..cf4df2dcb87 100644 --- a/boards/bcdevices/plt_demo_v2/doc/index.rst +++ b/boards/bcdevices/plt_demo_v2/doc/index.rst @@ -125,7 +125,7 @@ an external programmer. The programmer is attached to the SWD header. Build the Zephyr kernel and the :zephyr:code-sample:`led-strip` sample application. .. zephyr-app-commands:: - :zephyr-app: samples/drivers/led_apa102 + :zephyr-app: samples/drivers/led/led_strip :board: blueclover_plt_demo_v2/nrf52832 :goals: build :compact: @@ -133,7 +133,7 @@ Build the Zephyr kernel and the :zephyr:code-sample:`led-strip` sample applicati Flash the image. .. zephyr-app-commands:: - :zephyr-app: samples/drivers/led_apa102 + :zephyr-app: samples/drivers/led/led_strip :board: blueclover_plt_demo_v2/nrf52832 :goals: flash :compact: diff --git a/boards/beagle/beagleconnect_freedom/beagleconnect_freedom-pinctrl.dtsi b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom-pinctrl.dtsi index 201de3fc4b0..cf662d67a2e 100644 --- a/boards/beagle/beagleconnect_freedom/beagleconnect_freedom-pinctrl.dtsi +++ b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom-pinctrl.dtsi @@ -81,14 +81,18 @@ /* On-board antenna pinmux states */ board_ant_tx_pa_off: board_ant_tx_pa_off { pinmux = <29 IOC_PORT_GPIO>; + bias-disable; }; board_ant_tx_pa_on: board_ant_tx_pa_on { pinmux = <29 IOC_PORT_RFC_GPO3>; + bias-disable; }; board_ant_subg_off: board_ant_subg_off { pinmux = <30 IOC_PORT_GPIO>; + bias-disable; }; board_ant_subg_on: board_ant_subg_on { pinmux = <30 IOC_PORT_RFC_GPO0>; + bias-disable; }; }; diff --git a/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts index 9f8c84df956..f94737a9e37 100644 --- a/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts +++ b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts @@ -23,7 +23,6 @@ mcuboot-button0 = &button0; sensor0 = &light; sensor1 = &humidity; - spi-flash0 = &spi_flash0; }; chosen { @@ -43,18 +42,33 @@ }; }; + /** + * The BeagleConnect Freedom has an on-board antenna switch (SKY13317-373LF) used to select + * the appropriate RF signal port based on the currently-used PHY. + * + * Truth table: + * + * Path DIO29 DIO30 + * =========== ===== ===== + * Off 0 0 + * Sub-1 GHz 0 1 // DIO30 mux to IOC_PORT_RFC_GPO0 for auto + * 20 dBm TX 1 0 // DIO29 mux to IOC_PORT_RFC_GPO3 for auto + */ + antenna_mux0: antenna_mux0 { + compatible = "skyworks,sky13317"; + status = "okay"; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>, <&gpio0 30 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&board_ant_tx_pa_off &board_ant_subg_off>; + pinctrl-1 = <&board_ant_tx_pa_off &board_ant_subg_on>; + pinctrl-2 = <&board_ant_tx_pa_on &board_ant_subg_on>; + pinctrl-names = "default", "ant_subg", "ant_subg_pa"; + }; + leds: leds { compatible = "gpio-leds"; led0: led_0 { gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; // 2.4GHz TX/RX }; - - /* U.FL connector switch */ - rf_sw: rf_sw { - gpios = - <&gpio0 29 GPIO_ACTIVE_HIGH>, // SubG TX +20dB - <&gpio0 30 GPIO_ACTIVE_HIGH>; // SubG TX/RX 0dB - }; }; sens_i2c: sensor-switch { diff --git a/boards/beagle/beagleconnect_freedom/board_antenna.c b/boards/beagle/beagleconnect_freedom/board_antenna.c index 131d75448bb..18407c06a78 100644 --- a/boards/beagle/beagleconnect_freedom/board_antenna.c +++ b/boards/beagle/beagleconnect_freedom/board_antenna.c @@ -1,8 +1,9 @@ -/* SPDX-License-Identifier: Apache-2.0 - * +/* * Copyright (c) 2021 Florin Stancu * Copyright (c) 2021 Jason Kridner, BeagleBoard.org Foundation + * Copyright (c) 2024 Ayush Singh * + * SPDX-License-Identifier: Apache-2.0 */ /* @@ -10,107 +11,108 @@ * switch. */ -#include -#include +#define DT_DRV_COMPAT skyworks_sky13317 + #include +#include +#include +#include #include -#include -#include #include +#include -/* DIOs for RF antenna paths */ -#define BOARD_RF_HIGH_PA 29 /* TODO: pull from DT */ -#define BOARD_RF_SUB1GHZ 30 /* TODO: pull from DT */ +/* custom pinctrl states for the antenna mux */ +#define PINCTRL_STATE_ANT_SUBG 1 +#define PINCTRL_STATE_ANT_SUBG_PA 2 -static void board_cc13xx_rf_callback(RF_Handle client, RF_GlobalEvent events, - void *arg); +#define BOARD_ANT_GPIO_PA 0 +#define BOARD_ANT_GPIO_SUBG 1 +static int board_antenna_init(const struct device *dev); +static void board_cc13xx_rf_callback(RF_Handle client, RF_GlobalEvent events, void *arg); const RFCC26XX_HWAttrsV2 RFCC26XX_hwAttrs = { - .hwiPriority = INT_PRI_LEVEL7, - .swiPriority = 0, + .hwiPriority = INT_PRI_LEVEL7, + .swiPriority = 0, .xoscHfAlwaysNeeded = true, /* RF driver callback for custom antenna switching */ .globalCallback = board_cc13xx_rf_callback, /* Subscribe to events */ - .globalEventMask = (RF_GlobalEventRadioSetup | - RF_GlobalEventRadioPowerDown), + .globalEventMask = (RF_GlobalEventRadioSetup | RF_GlobalEventRadioPowerDown), }; +PINCTRL_DT_INST_DEFINE(0); +DEVICE_DT_INST_DEFINE(0, board_antenna_init, NULL, NULL, NULL, POST_KERNEL, + CONFIG_BOARD_ANTENNA_INIT_PRIO, NULL); + +static const struct pinctrl_dev_config *ant_pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0); +static const struct gpio_dt_spec ant_gpios[] = { + DT_FOREACH_PROP_ELEM_SEP(DT_NODELABEL(antenna_mux0), gpios, GPIO_DT_SPEC_GET_BY_IDX, (,))}; + /** * Antenna switch GPIO init routine. */ -static int board_antenna_init(void) +static int board_antenna_init(const struct device *dev) { + ARG_UNUSED(dev); + int i; - /* set all paths to low */ - IOCPinTypeGpioOutput(BOARD_RF_HIGH_PA); - GPIO_setOutputEnableDio(BOARD_RF_HIGH_PA, GPIO_OUTPUT_DISABLE); - IOCPinTypeGpioOutput(BOARD_RF_SUB1GHZ); - GPIO_setOutputEnableDio(BOARD_RF_SUB1GHZ, GPIO_OUTPUT_DISABLE); + /* default pinctrl configuration: set all antenna mux control pins as GPIOs */ + pinctrl_apply_state(ant_pcfg, PINCTRL_STATE_DEFAULT); + /* set all GPIOs to 0 (all RF paths disabled) */ + for (i = 0; i < ARRAY_SIZE(ant_gpios); i++) { + gpio_pin_configure_dt(&ant_gpios[i], 0); + } return 0; } -SYS_INIT(board_antenna_init, POST_KERNEL, CONFIG_BOARD_ANTENNA_INIT_PRIO); - -void board_cc13xx_rf_callback(RF_Handle client, RF_GlobalEvent events, void *arg) +/** + * Custom TI RFCC26XX callback for switching the on-board antenna mux on radio setup. + */ +static void board_cc13xx_rf_callback(RF_Handle client, RF_GlobalEvent events, void *arg) { - bool sub1GHz = false; + bool sub1GHz = false; uint8_t loDivider = 0; + int i; - /* Switch off all paths first. Needs to be done anyway in every sub-case below. */ - GPIO_setOutputEnableDio(BOARD_RF_HIGH_PA, GPIO_OUTPUT_DISABLE); - GPIO_setOutputEnableDio(BOARD_RF_SUB1GHZ, GPIO_OUTPUT_DISABLE); + /* Clear all antenna switch GPIOs (for all cases). */ + for (i = 0; i < ARRAY_SIZE(ant_gpios); i++) { + gpio_pin_configure_dt(&ant_gpios[i], 0); + } if (events & RF_GlobalEventRadioSetup) { /* Decode the current PA configuration. */ - RF_TxPowerTable_PAType paType = (RF_TxPowerTable_PAType) - RF_getTxPower(client).paType; + RF_TxPowerTable_PAType paType = + (RF_TxPowerTable_PAType)RF_getTxPower(client).paType; /* Decode the generic argument as a setup command. */ RF_RadioSetup *setupCommand = (RF_RadioSetup *)arg; switch (setupCommand->common.commandNo) { - case (CMD_RADIO_SETUP): - case (CMD_BLE5_RADIO_SETUP): + case CMD_RADIO_SETUP: + case CMD_BLE5_RADIO_SETUP: loDivider = RF_LODIVIDER_MASK & setupCommand->common.loDivider; - /* Sub-1GHz front-end. */ - if (loDivider != 0) - sub1GHz = true; break; - case (CMD_PROP_RADIO_DIV_SETUP): + case CMD_PROP_RADIO_DIV_SETUP: loDivider = RF_LODIVIDER_MASK & setupCommand->prop_div.loDivider; - /* Sub-1GHz front-end. */ - if (loDivider != 0) - sub1GHz = true; break; default: break; } + sub1GHz = (loDivider != 0); - /* Sub-1 GHz */ - if (paType == RF_TxPowerTable_HighPA) { - /* PA enable --> HIGH PA */ - /* LNA enable --> Sub-1 GHz */ - /* Note: RFC_GPO3 is a work-around because the RFC_GPO1 */ - /* is sometimes not de-asserted on CC1352 Rev A. */ - IOCPortConfigureSet(BOARD_RF_HIGH_PA, - IOC_PORT_RFC_GPO3, IOC_IOMODE_NORMAL); - IOCPortConfigureSet(BOARD_RF_SUB1GHZ, - IOC_PORT_RFC_GPO0, IOC_IOMODE_NORMAL); - } else { - /* RF core active --> Sub-1 GHz */ - IOCPortConfigureSet(BOARD_RF_HIGH_PA, - IOC_PORT_GPIO, IOC_IOMODE_NORMAL); - IOCPortConfigureSet(BOARD_RF_SUB1GHZ, - IOC_PORT_GPIO, IOC_IOMODE_NORMAL); - GPIO_setOutputEnableDio(BOARD_RF_SUB1GHZ, GPIO_OUTPUT_ENABLE); + if (sub1GHz) { + if (paType == RF_TxPowerTable_HighPA) { + /* Note: RFC_GPO3 is a work-around because the RFC_GPO1 */ + /* is sometimes not de-asserted on CC1352 Rev A. */ + pinctrl_apply_state(ant_pcfg, PINCTRL_STATE_ANT_SUBG_PA); + } else { + pinctrl_apply_state(ant_pcfg, PINCTRL_STATE_ANT_SUBG); + /* Manually set the sub-GHZ antenna switch DIO */ + gpio_pin_configure_dt(&ant_gpios[BOARD_ANT_GPIO_SUBG], 1); + } } } else { - /* Reset the IO multiplexer to GPIO functionality */ - IOCPortConfigureSet(BOARD_RF_HIGH_PA, - IOC_PORT_GPIO, IOC_IOMODE_NORMAL); - IOCPortConfigureSet(BOARD_RF_SUB1GHZ, - IOC_PORT_GPIO, IOC_IOMODE_NORMAL); + pinctrl_apply_state(ant_pcfg, PINCTRL_STATE_DEFAULT); } } diff --git a/boards/beagle/beaglev_fire/Kconfig b/boards/beagle/beaglev_fire/Kconfig deleted file mode 100644 index a0ce11033e7..00000000000 --- a/boards/beagle/beaglev_fire/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2023 Microchip Technology Inc -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BEAGLEV_FIRE - select 64BIT - select SCHED_IPI_SUPPORTED - select CPU_HAS_FPU_DOUBLE_PRECISION diff --git a/boards/beagle/beaglev_fire/Kconfig.beaglev_fire b/boards/beagle/beaglev_fire/Kconfig.beaglev_fire index b4bf8b4b2d3..118bee296d0 100644 --- a/boards/beagle/beaglev_fire/Kconfig.beaglev_fire +++ b/boards/beagle/beaglev_fire/Kconfig.beaglev_fire @@ -2,4 +2,6 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_BEAGLEV_FIRE - select SOC_POLARFIRE + select SOC_POLARFIRE_U54 if BOARD_BEAGLEV_FIRE_POLARFIRE_U54 || \ + BOARD_BEAGLEV_FIRE_POLARFIRE_U54_SMP + select SOC_POLARFIRE_E51 if BOARD_BEAGLEV_FIRE_POLARFIRE_E51 diff --git a/boards/beagle/beaglev_fire/beaglev_fire.dts b/boards/beagle/beaglev_fire/beaglev_fire.dts deleted file mode 100644 index df956f5c8f2..00000000000 --- a/boards/beagle/beaglev_fire/beaglev_fire.dts +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2023 Microchip Technology Inc - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include -#include - -/ { - model = "BeagleV-Fire"; - compatible = "beagle,beaglev-fire", "microchip,mpfs"; - aliases { - }; - - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,sram = &sram1; - }; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - clock-frequency = <150000000>; -}; - -&gpio2 { - status = "okay"; -}; diff --git a/boards/beagle/beaglev_fire/beaglev_fire.yaml b/boards/beagle/beaglev_fire/beaglev_fire.yaml deleted file mode 100644 index 79c65d30e0f..00000000000 --- a/boards/beagle/beaglev_fire/beaglev_fire.yaml +++ /dev/null @@ -1,12 +0,0 @@ -identifier: beaglev_fire -name: Beagleboard BeagleV-Fire -type: mcu -arch: riscv -toolchain: - - zephyr -ram: 3840 -testing: - ignore_tags: - - net - - bluetooth -vendor: beagle diff --git a/boards/beagle/beaglev_fire/beaglev_fire_common.dtsi b/boards/beagle/beaglev_fire/beaglev_fire_common.dtsi new file mode 100644 index 00000000000..24b1958a9d9 --- /dev/null +++ b/boards/beagle/beaglev_fire/beaglev_fire_common.dtsi @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2023 Microchip Technology Inc + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include + +/ { + model = "beagle,beaglev-fire"; + compatible = "beagle,beaglev-fire", "microchip,mpfs"; + aliases { + }; +}; + +&gpio2 { + status = "okay"; +}; diff --git a/boards/beagle/beaglev_fire/beaglev_fire_defconfig b/boards/beagle/beaglev_fire/beaglev_fire_defconfig index deb1db784f8..ded4a47c214 100644 --- a/boards/beagle/beaglev_fire/beaglev_fire_defconfig +++ b/boards/beagle/beaglev_fire/beaglev_fire_defconfig @@ -10,4 +10,3 @@ CONFIG_UART_CONSOLE=y CONFIG_XIP=n CONFIG_INIT_STACKS=y CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 -CONFIG_FPU=n diff --git a/boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51.dts b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51.dts new file mode 100644 index 00000000000..5a8537124d4 --- /dev/null +++ b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51.dts @@ -0,0 +1,36 @@ +/dts-v1/; +#include "beaglev_fire_common.dtsi" + +/ { + compatible = "beagle,beaglev-fire", "microchip,mpfs"; + + cpus { + cpu@1 { + status = "disabled"; + }; + + cpu@2 { + status = "disabled"; + }; + + cpu@3 { + status = "disabled"; + }; + + cpu@4 { + status = "disabled"; + }; + }; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &sram1; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <150000000>; +}; diff --git a/boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51.yaml b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51.yaml new file mode 100644 index 00000000000..bc5ee3de628 --- /dev/null +++ b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51.yaml @@ -0,0 +1,12 @@ +identifier: beaglev_fire/polarfire/e51 +name: Beagleboard BeagleV-Fire +type: mcu +arch: riscv +toolchain: + - zephyr +ram: 3840 +testing: + ignore_tags: + - net + - bluetooth +vendor: beagle diff --git a/boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51_defconfig b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51_defconfig new file mode 100644 index 00000000000..ded4a47c214 --- /dev/null +++ b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51_defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2023 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MPFS_HAL=n +CONFIG_BASE64=y +CONFIG_INCLUDE_RESET_VECTOR=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_XIP=n +CONFIG_INIT_STACKS=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 diff --git a/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54.dts b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54.dts new file mode 100644 index 00000000000..7c4fba300fd --- /dev/null +++ b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54.dts @@ -0,0 +1,25 @@ +/dts-v1/; +#include "beaglev_fire_common.dtsi" + +/ { + model = "beagle,beaglev-fire"; + compatible = "beagle,beaglev-fire", "microchip,mpfs"; + + chosen { + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,sram = &sram1; + }; + + cpus { + cpu@0 { + status = "disabled"; + }; + }; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <150000000>; +}; diff --git a/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54.yaml b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54.yaml new file mode 100644 index 00000000000..9204225a766 --- /dev/null +++ b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54.yaml @@ -0,0 +1,12 @@ +identifier: beaglev_fire/polarfire/u54 +name: Beagleboard BeagleV-Fire +type: mcu +arch: riscv +toolchain: + - zephyr +ram: 3840 +testing: + ignore_tags: + - net + - bluetooth +vendor: beagle diff --git a/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_defconfig b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_defconfig new file mode 100644 index 00000000000..ef99af479d4 --- /dev/null +++ b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2023 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MPFS_HAL=n +CONFIG_BASE64=y +CONFIG_INCLUDE_RESET_VECTOR=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_XIP=n +CONFIG_INIT_STACKS=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 +CONFIG_RV_BOOT_HART=1 diff --git a/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp.dts b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp.dts new file mode 100644 index 00000000000..cf9ed20aa3e --- /dev/null +++ b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp.dts @@ -0,0 +1,19 @@ +/dts-v1/; +#include "beaglev_fire_polarfire_u54.dts" + +/ { + model = "beagle,beaglev-fire"; + compatible = "beagle,beaglev-fire", "microchip,mpfs"; + + chosen { + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,sram = &sram1; + }; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <150000000>; +}; diff --git a/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp.yaml b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp.yaml new file mode 100644 index 00000000000..e8f31601438 --- /dev/null +++ b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp.yaml @@ -0,0 +1,12 @@ +identifier: beaglev_fire/polarfire/u54/smp +name: Beagleboard BeagleV-Fire +type: mcu +arch: riscv +toolchain: + - zephyr +ram: 3840 +testing: + ignore_tags: + - net + - bluetooth +vendor: beagle diff --git a/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp_defconfig b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp_defconfig new file mode 100644 index 00000000000..e1e30df8b16 --- /dev/null +++ b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp_defconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2023 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MPFS_HAL=n +CONFIG_BASE64=y +CONFIG_INCLUDE_RESET_VECTOR=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_XIP=n +CONFIG_INIT_STACKS=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 +CONFIG_RV_BOOT_HART=1 +CONFIG_SMP=y diff --git a/boards/beagle/beaglev_fire/board.yml b/boards/beagle/beaglev_fire/board.yml index 89447e4b4ce..60520301134 100644 --- a/boards/beagle/beaglev_fire/board.yml +++ b/boards/beagle/beaglev_fire/board.yml @@ -3,3 +3,6 @@ board: vendor: beagle socs: - name: polarfire + variants: + - name: smp + cpucluster: u54 diff --git a/boards/beagle/beaglev_fire/doc/index.rst b/boards/beagle/beaglev_fire/doc/index.rst index 88808145c9b..23d63f4db7a 100644 --- a/boards/beagle/beaglev_fire/doc/index.rst +++ b/boards/beagle/beaglev_fire/doc/index.rst @@ -57,7 +57,7 @@ from a different terminal, run: .. code-block:: bash - /openocd/bin/openocd --file \ + /openocd/bin/openocd --command "set DEVICE MPFS" --file \ /openocd/share/openocd/scripts/board/microsemi-riscv.cfg diff --git a/boards/blues/swan_r5/doc/index.rst b/boards/blues/swan_r5/doc/index.rst index 644e82e86dd..6ee06251f30 100644 --- a/boards/blues/swan_r5/doc/index.rst +++ b/boards/blues/swan_r5/doc/index.rst @@ -20,8 +20,8 @@ Due to its novel design, for high-volume deployment the low-cost Swan can also be soldered directly to a parent PCB integrating those sensors, utilizing the full range of Swan's I/O capabilities. -The board has three independent power options-USB, Battery, or Line power- -and provides a software-switchable 2 Amp regulator for powering external +The board has three independent power options---USB, Battery, or Line +power---and provides a software-switchable 2 Amp regulator for powering external sensors. When operating in its low-power operating mode, the entire Swan board commonly draws only about 8uA while retaining all of its memory, making it quite suitable for battery-powered devices. @@ -198,7 +198,7 @@ Programming and Debugging Connect Swan to your host computer using the USB port. Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Swan: diff --git a/boards/blues/swan_r5/swan_r5_defconfig b/boards/blues/swan_r5/swan_r5_defconfig index 596cbc88cbd..2453274a086 100644 --- a/boards/blues/swan_r5/swan_r5_defconfig +++ b/boards/blues/swan_r5/swan_r5_defconfig @@ -6,9 +6,6 @@ CONFIG_SERIAL=y # Enable GPIO CONFIG_GPIO=y -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - # Console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y @@ -19,7 +16,4 @@ CONFIG_ARM_MPU=y # Enable HW stack protection CONFIG_HW_STACK_PROTECTION=y -# enable pin controller -CONFIG_PINCTRL=y - CONFIG_REGULATOR=y diff --git a/boards/bytesatwork/bytesensi_l/Kconfig.bytesensi_l b/boards/bytesatwork/bytesensi_l/Kconfig.bytesensi_l new file mode 100644 index 00000000000..530e716b540 --- /dev/null +++ b/boards/bytesatwork/bytesensi_l/Kconfig.bytesensi_l @@ -0,0 +1,6 @@ +# Copyright (c) 2024 bytesatwork AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BYTESENSI_L + bool "bytesatwork bytesSENSI-L nRF52832" + select SOC_NRF52832_QFAA diff --git a/boards/bytesatwork/bytesensi_l/Kconfig.defconfig b/boards/bytesatwork/bytesensi_l/Kconfig.defconfig new file mode 100644 index 00000000000..52c2d397af8 --- /dev/null +++ b/boards/bytesatwork/bytesensi_l/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 bytesatwork AG +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BYTESENSI_L + +config BT_CTLR + default BT + +endif # BOARD_BYTESENSI_L diff --git a/boards/bytesatwork/bytesensi_l/board.cmake b/boards/bytesatwork/bytesensi_l/board.cmake new file mode 100644 index 00000000000..efeed46003e --- /dev/null +++ b/boards/bytesatwork/bytesensi_l/board.cmake @@ -0,0 +1,5 @@ +# Copyright (c) 2024 bytesatwork AG +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=nRF52832_xxAA" "--speed=4000") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/bytesatwork/bytesensi_l/board.yml b/boards/bytesatwork/bytesensi_l/board.yml new file mode 100644 index 00000000000..04e4cd9ad11 --- /dev/null +++ b/boards/bytesatwork/bytesensi_l/board.yml @@ -0,0 +1,7 @@ +# Copyright (c) 2024 bytesatwork AG +# SPDX-License-Identifier: Apache-2.0 +board: + name: bytesensi_l + vendor: bytesatwork + socs: + - name: nrf52832 diff --git a/boards/bytesatwork/bytesensi_l/bytesensi_l.dts b/boards/bytesatwork/bytesensi_l/bytesensi_l.dts new file mode 100644 index 00000000000..2054d6bd2e2 --- /dev/null +++ b/boards/bytesatwork/bytesensi_l/bytesensi_l.dts @@ -0,0 +1,170 @@ +/* + * Copyrigtt (c) 2024 bytesatwork AG + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "bytesensi_l_pinctrl.dtsi" + +#include + +/ { + model = "bytesatwork BLE/LORA sensor board"; + compatible = "bytesatwork,bytesensi-l"; + + chosen { + zephyr,console = &uart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + aliases { + /* Alias for lora samples */ + lora0 = &lora; + /* Alias for gnss samples */ + gnss = &gnss; + }; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0xc000>; + }; + slot0_partition: partition@c000 { + label = "image-0"; + reg = <0x0000C000 0x32000>; + }; + slot1_partition: partition@3e000 { + label = "image-1"; + reg = <0x0003E000 0x32000>; + }; + scratch_partition: partition@70000 { + label = "image-scratch"; + reg = <0x00070000 0xa000>; + }; + storage_partition: partition@7a000 { + label = "storage"; + reg = <0x0007a000 0x00005000>; + }; + }; +}; + +® { + regulator-initial-mode = ; +}; + +&gpiote { + status = "okay"; +}; + +&gpio0 { + status = "okay"; + + /* Enable 1-wire to enable i2c bus as well */ + one-wire-gpio { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&i2c0 { + compatible = "nordic,nrf-twi"; + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-1 = <&i2c0_sleep>; + pinctrl-names = "default", "sleep"; + + light_sensor: apds9960@39 { + status = "okay"; + compatible = "avago,apds9960"; + reg = <0x39>; + int-gpios = <&gpio0 25 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + temperature_sensor: tmp116@4a { + status = "okay"; + compatible = "ti,tmp116"; + reg = <0x4a>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom: ti_tmp116_eeprom@0 { + compatible = "ti,tmp116-eeprom"; + reg = <0x0>; + read-only; + }; + }; + + gas_sensor: ccs811@5a { + status = "okay"; + compatible = "ams,ccs811"; + reg = <0x5a>; + irq-gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; + wake-gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; + }; + + pressure_sensor: lps22hb-press@5c { + status = "okay"; + compatible = "st,lps22hb-press"; + reg = <0x5c>; + }; +}; + +&spi1 { + status = "okay"; + compatible = "nordic,nrf-spi"; + pinctrl-0 = <&spi1_default>; + pinctrl-1 = <&spi1_sleep>; + pinctrl-names = "default", "sleep"; + cs-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>, + <&gpio0 5 GPIO_ACTIVE_LOW>; + + lora: lora@0 { + status = "okay"; + compatible = "semtech,sx1276"; + reg = <0>; + reset-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + dio-gpios = + <&gpio0 19 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, + <&gpio0 20 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, + <&gpio0 22 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, + <&gpio0 23 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; + spi-max-frequency = <1000000>; + power-amplifier-output = "pa-boost"; + }; + + nor_flash: mx25r6435f@1 { + status = "okay"; + compatible ="jedec,spi-nor"; + size = <0x4000000>; + reg = <1>; + spi-max-frequency = <8000000>; + status = "okay"; + jedec-id = [c2 28 17]; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <9600>; + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; + + gnss: u_blox_m8 { + status = "okay"; + compatible = "gnss-nmea-generic"; + }; +}; diff --git a/boards/bytesatwork/bytesensi_l/bytesensi_l.yaml b/boards/bytesatwork/bytesensi_l/bytesensi_l.yaml new file mode 100644 index 00000000000..362508e67a2 --- /dev/null +++ b/boards/bytesatwork/bytesensi_l/bytesensi_l.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2024 bytesatwork AG +# SPDX-License-Identifier: Apache-2.0 +identifier: bytesensi_l +name: bytesatwork byteSENSI-L +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +ram: 64 +flash: 512 +supported: + - ble + - gpio + - i2c + - lora + - spi +vendor: bytesatwork diff --git a/boards/bytesatwork/bytesensi_l/bytesensi_l_defconfig b/boards/bytesatwork/bytesensi_l/bytesensi_l_defconfig new file mode 100644 index 00000000000..24ab5af7406 --- /dev/null +++ b/boards/bytesatwork/bytesensi_l/bytesensi_l_defconfig @@ -0,0 +1,20 @@ +# Copyright (c) 2024 bytesatwork AG +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# enable GPIO +CONFIG_GPIO=y + +# enable UART +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# enable console over segger RTT +CONFIG_CONSOLE=y +CONFIG_RTT_CONSOLE=y +CONFIG_USE_SEGGER_RTT=y diff --git a/boards/bytesatwork/bytesensi_l/bytesensi_l_pinctrl.dtsi b/boards/bytesatwork/bytesensi_l/bytesensi_l_pinctrl.dtsi new file mode 100644 index 00000000000..47f19df7b41 --- /dev/null +++ b/boards/bytesatwork/bytesensi_l/bytesensi_l_pinctrl.dtsi @@ -0,0 +1,54 @@ +/* + * Copyrigtt (c) 2024 bytesatwork AG + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + uart0_default: uart0_default { + group1 { + psels = , + ; + }; + }; + + uart0_sleep: uart0_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + i2c0_default: i2c0_default { + group1 { + psels = , + ; + }; + }; + + i2c0_sleep: i2c0_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + spi1_default: spi1_default{ + group1 { + psels = , + , + ; + }; + }; + + spi1_sleep: spi1_sleep{ + group1 { + psels = , + , + ; + low-power-enable; + }; + }; +}; diff --git a/boards/bytesatwork/bytesensi_l/doc/img/byteSENSI-L.jpg b/boards/bytesatwork/bytesensi_l/doc/img/byteSENSI-L.jpg new file mode 100644 index 00000000000..5baccde618f Binary files /dev/null and b/boards/bytesatwork/bytesensi_l/doc/img/byteSENSI-L.jpg differ diff --git a/boards/bytesatwork/bytesensi_l/doc/index.rst b/boards/bytesatwork/bytesensi_l/doc/index.rst new file mode 100644 index 00000000000..9d16e74d21b --- /dev/null +++ b/boards/bytesatwork/bytesensi_l/doc/index.rst @@ -0,0 +1,159 @@ +.. _bytesensi_l: + +bytesatwork byteSENSI-L +####################### + +Overview +******** + +The byteSENSI-L is a fun LoRa device based on nRF52 MCU that integrates many +sensors. + +.. image:: img/byteSENSI-L.jpg + :width: 800px + :align: center + :alt: byteSENSI-L + +Hardware +******** + +Supported Features +================== + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| GPS | u-blox | gnss | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+----------------------+ +| RADIO | Semtech | LoRa | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Connections and IOs +=================== + +External Connectors +------------------- + +External Supply @ X1 + ++-------+--------------+---------------------------------------+ +| PIN # | Signal Name | Function | ++=======+==============+=======================================+ +| 1 | VBAT | Power input instead of CR2477 battery | ++-------+--------------+---------------------------------------+ +| 2 | GND | Ground | ++-------+--------------+---------------------------------------+ + +Programming Connector @ SL1 + ++-------+--------------+ +| PIN # | Signal Name | ++=======+==============+ +| 1 | VBAT | ++-------+--------------+ +| 2 | SWDIO | ++-------+--------------+ +| 3 | GND | ++-------+--------------+ +| 4 | SWDCLK | ++-------+--------------+ +| 5 | GND | ++-------+--------------+ +| 6 | NC (SWO) | ++-------+--------------+ +| 7 | NC (Key) | ++-------+--------------+ +| 8 | NC | ++-------+--------------+ +| 9 | GND | ++-------+--------------+ +| 10 | nReset | ++-------+--------------+ + +I2C Sensor @ X3 + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | Function | ++=======+==============+=========================+ +| 1 | VBAT | Power out | ++-------+--------------+-------------------------+ +| 2 | SCL | I2C clock at P0.15 | ++-------+--------------+-------------------------+ +| 3 | SDA | I2C data at P0.16 | ++-------+--------------+-------------------------+ +| 4 | INT | Interrupt at P0.13 | ++-------+--------------+-------------------------+ +| 5 | I2C_ADDR | tied to VBAT | ++-------+--------------+-------------------------+ +| 6 | GND | Ground | ++-------+--------------+-------------------------+ + +One Wire Sensor @ X2 + ++-------+----------------+-------------------------+ +| PIN # | Signal Name | Function | ++=======+================+=========================+ +| 1 | VDD | 4V8 | ++-------+----------------+-------------------------+ +| 2 | IO | One Wire | ++-------+----------------+-------------------------+ +| 3 | GND | Ground | ++-------+----------------+-------------------------+ + +External BLE Antenna @ J1 + +External LoRa Antenna @ J2 + +External GPS Antenna @ J3 + +Programming and Debugging +************************* + +Flashing +======== +The byteSENSI-L board can be flashed with the SEGGER JLink programmer. + +You can build and flash applications in the usual way. Here is an example for +the :zephyr:code-sample:`hello_world` application. + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: bytesensi_l + :goals: build flash + :compact: + +Debugging +========= + +Debugging your application can be done with ``west debug``. + +Serial console +============== + +The byteSENSI-L board only uses Segger's RTT console for providing serial +console. There is no physical serial port available. + +References +********** +* `bytesatwork website `_ +* `bytesatwork wiki `_ diff --git a/boards/bytesatwork/bytesensi_l/pre_dt_board.cmake b/boards/bytesatwork/bytesensi_l/pre_dt_board.cmake new file mode 100644 index 00000000000..4bcc2f7a610 --- /dev/null +++ b/boards/bytesatwork/bytesensi_l/pre_dt_board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2024 bytesatwork AG +# SPDX-License-Identifier: Apache-2.0 + +# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: +# - power@40000000 & clock@40000000 & bprot@40000000 +# - acl@4001e000 & flash-controller@4001e000 +list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/bytesatwork/index.rst b/boards/bytesatwork/index.rst new file mode 100644 index 00000000000..cb47fbff333 --- /dev/null +++ b/boards/bytesatwork/index.rst @@ -0,0 +1,10 @@ +.. _boards-bytesatwork: + +bytesatwork +########### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/cdns/xt-sim/doc/index.rst b/boards/cdns/xt-sim/doc/index.rst index d8a4b9c5993..5f97e597250 100644 --- a/boards/cdns/xt-sim/doc/index.rst +++ b/boards/cdns/xt-sim/doc/index.rst @@ -38,7 +38,7 @@ System requirements Prerequisites ============= A Linux host system is required for Xtensa development work. -We recommend using a __``Debian 9.x (Stretch)``__ or recent __``Ubuntu``__ +We recommend using a Debian 9.x (Stretch) or recent Ubuntu releases (with multilib support). Only Xtensa tools version ``RF-2016.4-linux`` or later are officially diff --git a/boards/circuitdojo/feather/circuitdojo_feather_nrf9160_common.dtsi b/boards/circuitdojo/feather/circuitdojo_feather_nrf9160_common.dtsi index 00ce5dcf6c0..186f6ef4662 100644 --- a/boards/circuitdojo/feather/circuitdojo_feather_nrf9160_common.dtsi +++ b/boards/circuitdojo/feather/circuitdojo_feather_nrf9160_common.dtsi @@ -50,7 +50,6 @@ mcuboot-button0 = &button0; mcuboot-led0 = &blue_led; watchdog0 = &wdt0; - spi-flash0 = &w25q32jv; accel0 = &lis2dh; }; @@ -173,58 +172,6 @@ }; }; -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x10000>; - }; - slot0_partition: partition@10000 { - label = "image-0"; - }; - slot0_ns_partition: partition@50000 { - label = "image-0-nonsecure"; - }; - slot1_partition: partition@80000 { - label = "image-1"; - }; - slot1_ns_partition: partition@c0000 { - label = "image-1-nonsecure"; - }; - /* 0xf0000 to 0xf7fff reserved for TF-M partitions */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; - -/ { - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_s: image_s@20000000 { - /* Secure image memory */ - }; - - sram0_bsd: image_bsd@20010000 { - /* BSD (shared) memory */ - }; - - sram0_ns: image_ns@20020000 { - /* Non-Secure image memory */ - }; - }; -}; - / { vbatt { compatible = "voltage-divider"; @@ -235,5 +182,5 @@ }; }; -/* Include partition configuration file */ -#include "circuitdojo_feather_nrf9160_partition_conf.dtsi" +/* Include default memory partition configuration file */ +#include diff --git a/boards/circuitdojo/feather/circuitdojo_feather_nrf9160_ns.dts b/boards/circuitdojo/feather/circuitdojo_feather_nrf9160_ns.dts index 34552478bdb..ae1589e85b2 100644 --- a/boards/circuitdojo/feather/circuitdojo_feather_nrf9160_ns.dts +++ b/boards/circuitdojo/feather/circuitdojo_feather_nrf9160_ns.dts @@ -12,7 +12,7 @@ / { chosen { zephyr,flash = &flash0; - zephyr,sram = &sram0_ns; + zephyr,sram = &sram0_ns_app; zephyr,code-partition = &slot0_ns_partition; }; }; diff --git a/boards/circuitdojo/feather/circuitdojo_feather_nrf9160_partition_conf.dtsi b/boards/circuitdojo/feather/circuitdojo_feather_nrf9160_partition_conf.dtsi deleted file mode 100644 index 007975132d6..00000000000 --- a/boards/circuitdojo/feather/circuitdojo_feather_nrf9160_partition_conf.dtsi +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2018-2020 Nordic Semiconductor ASA - * Copyright (c) 2020 Circuit Dojo LLC - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* - * Default Flash planning for circuitdojo_feather_nrf9160. - * - * Zephyr build for nRF9160 with ARM TrustZone-M support, - * implies building Secure and Non-Secure Zephyr images. - * - * Secure image will be placed, by default, in flash0 - * (or in slot0, if MCUboot is present). - * Secure image will use sram0 for system memory. - * - * Non-Secure image will be placed in slot0_ns, and use - * sram0_ns for system memory. - * - * Note that the Secure image only requires knowledge of - * the beginning of the Non-Secure image (not its size). - */ - -&slot0_partition { - reg = <0x00010000 0x40000>; -}; - -&slot0_ns_partition { - reg = <0x00050000 0x30000>; -}; - -&slot1_partition { - reg = <0x00080000 0x40000>; -}; - -&slot1_ns_partition { - reg = <0x000c0000 0x30000>; -}; - -/* Default SRAM planning when building for nRF9160 with - * ARM TrustZone-M support - * - Lowest 64 kB SRAM allocated to Secure image (sram0_s). - * - 64 kB SRAM reserved for and used by the BSD socket - * library (sram0_bsd). - * - Upper 128 kB allocated to Non-Secure image (sram0_ns). - */ - -&sram0_s { - reg = <0x20000000 DT_SIZE_K(64)>; -}; - -&sram0_bsd { - reg = <0x20010000 DT_SIZE_K(64)>; -}; - -&sram0_ns { - reg = <0x20020000 DT_SIZE_K(128)>; -}; diff --git a/boards/circuitdojo/feather/doc/index.rst b/boards/circuitdojo/feather/doc/index.rst index 1988a00e98f..032b06d29d8 100644 --- a/boards/circuitdojo/feather/doc/index.rst +++ b/boards/circuitdojo/feather/doc/index.rst @@ -100,7 +100,7 @@ or Nordic based examples. Trusted Firmware-M (TF-M) and building the ``ns`` target is not supported for this board. Some of the examples do not use secure mode, so they do not require the -``ns`` suffix. A great example of this is the `hello_world` below. +``ns`` suffix. A great example of this is the ``hello_world`` below. Flashing ======== @@ -111,7 +111,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/common/probe-rs.board.cmake b/boards/common/probe-rs.board.cmake new file mode 100644 index 00000000000..bfc407d73be --- /dev/null +++ b/boards/common/probe-rs.board.cmake @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_set_flasher_ifnset(probe-rs) +board_finalize_runner_args(probe-rs) diff --git a/boards/common/renode.board.cmake b/boards/common/renode.board.cmake new file mode 100644 index 00000000000..c7c9b02ec59 --- /dev/null +++ b/boards/common/renode.board.cmake @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_set_sim_runner_ifnset(renode) + +board_runner_args(renode "--renode-command=$elf=@${PROJECT_BINARY_DIR}/${KERNEL_ELF_NAME}") +board_runner_args(renode "--renode-command=include @${RENODE_SCRIPT}") + +board_finalize_runner_args(renode) diff --git a/boards/common/renode_robot.board.cmake b/boards/common/renode_robot.board.cmake new file mode 100644 index 00000000000..3d42b3b8de1 --- /dev/null +++ b/boards/common/renode_robot.board.cmake @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_set_robot_runner_ifnset(renode-robot) + +# `--variable` is a renode-test argument, for setting a variable that can be later used in a .robot file: +# ELF: used in common.robot to set the `elf` variable in the default .resc script defined in board.cmake +# RESC: path to the .resc script, defined in board.cmake +# UART: default UART used by Robot in tests, defined in board.cmake +# KEYWORDS: path to common.robot, which contains common Robot keywords +# RESULTS_DIR: directory in which Robot artifacts will be generated after running a testsuite +board_runner_args(renode-robot "--renode-robot-arg=--variable=ELF:@${PROJECT_BINARY_DIR}/${KERNEL_ELF_NAME}") +board_runner_args(renode-robot "--renode-robot-arg=--variable=RESC:@${RENODE_SCRIPT}") +board_runner_args(renode-robot "--renode-robot-arg=--variable=UART:${RENODE_UART}") +board_runner_args(renode-robot "--renode-robot-arg=--variable=KEYWORDS:${ZEPHYR_BASE}/tests/robot/common.robot") +board_runner_args(renode-robot "--renode-robot-arg=--variable=RESULTS_DIR:${APPLICATION_BINARY_DIR}") + +board_finalize_runner_args(renode-robot) diff --git a/boards/common/simics.board.cmake b/boards/common/simics.board.cmake new file mode 100644 index 00000000000..792197a54cc --- /dev/null +++ b/boards/common/simics.board.cmake @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +board_finalize_emu_args(simics) diff --git a/boards/contextualelectronics/abc/Kconfig b/boards/contextualelectronics/abc/Kconfig deleted file mode 100644 index b6a9479723e..00000000000 --- a/boards/contextualelectronics/abc/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# ABC board configuration - -# Copyright (c) 2020 Analog Life LLC -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_CONTEXTUALELECTRONICS_ABC diff --git a/boards/contextualelectronics/abc/contextualelectronics_abc.dts b/boards/contextualelectronics/abc/contextualelectronics_abc.dts index 6f60b1ddfed..f2998e15377 100644 --- a/boards/contextualelectronics/abc/contextualelectronics_abc.dts +++ b/boards/contextualelectronics/abc/contextualelectronics_abc.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include "contextualelectronics_abc-pinctrl.dtsi" / { @@ -15,9 +16,6 @@ chosen { zephyr,console = &uart0; zephyr,shell-uart = &uart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; }; aliases { @@ -25,6 +23,10 @@ }; }; +®1 { + regulator-initial-mode = ; +}; + &uicr { gpio-as-nreset; }; @@ -91,43 +93,3 @@ arduino_i2c: &i2c0 { pinctrl-1 = <&spi2_sleep>; pinctrl-names = "default", "sleep"; }; - -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000C000>; - }; - slot0_partition: partition@c000 { - label = "image-0"; - reg = <0x0000C000 0x00067000>; - }; - slot1_partition: partition@73000 { - label = "image-1"; - reg = <0x00073000 0x00067000>; - }; - scratch_partition: partition@da000 { - label = "image-scratch"; - reg = <0x000da000 0x0001e000>; - }; - - /* - * The flash starting at 0x000f8000 and ending at - * 0x000fffff is reserved for use by the application. - */ - - /* - * Storage partition will be used by FCB/LittleFS/NVS - * if enabled. - */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; diff --git a/boards/contextualelectronics/abc/doc/index.rst b/boards/contextualelectronics/abc/doc/index.rst index 15f9e52bca8..dd8aa8acfb0 100644 --- a/boards/contextualelectronics/abc/doc/index.rst +++ b/boards/contextualelectronics/abc/doc/index.rst @@ -93,7 +93,7 @@ Flashing Flashing Zephyr onto the ``contextualelectronics_abc`` board requires an external programmer. The programmer is attached to the SWD header. -Build the Zephyr kernel and the :ref:`hello_world` sample application. +Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/croxel/croxel_cx1825/Kconfig b/boards/croxel/croxel_cx1825/Kconfig deleted file mode 100644 index 81b03929adc..00000000000 --- a/boards/croxel/croxel_cx1825/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2024 Luis Ubieda -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_CROXEL_CX1825 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF52X_HV - default y - -endif # BOARD_CROXEL_CX1825 diff --git a/boards/croxel/croxel_cx1825/croxel_cx1825_nrf52840.dts b/boards/croxel/croxel_cx1825/croxel_cx1825_nrf52840.dts index fac78f10b71..0aaa70158f8 100644 --- a/boards/croxel/croxel_cx1825/croxel_cx1825_nrf52840.dts +++ b/boards/croxel/croxel_cx1825/croxel_cx1825_nrf52840.dts @@ -51,9 +51,20 @@ mcuboot-button0 = &button0; mcuboot-led0 = &led0; watchdog0 = &wdt0; + dht0 = &hts221; + accel0 = &lis3dh; + prox-sensor0 = &apds9960; }; }; +®0 { + status = "okay"; +}; + +®1 { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; @@ -81,7 +92,7 @@ pinctrl-names = "default", "sleep"; }; -arduino_i2c: &i2c0 { +&i2c0 { compatible = "nordic,nrf-twi"; status = "okay"; pinctrl-0 = <&i2c0_default>; diff --git a/boards/croxel/croxel_cx1825/croxel_cx1825_nrf52840.yaml b/boards/croxel/croxel_cx1825/croxel_cx1825_nrf52840.yaml index 8fa7989a6eb..bc550fd4cc4 100644 --- a/boards/croxel/croxel_cx1825/croxel_cx1825_nrf52840.yaml +++ b/boards/croxel/croxel_cx1825/croxel_cx1825_nrf52840.yaml @@ -9,8 +9,6 @@ toolchain: - gnuarmemb - xtools supported: - - arduino_gpio - - arduino_i2c - ble - counter - gpio diff --git a/boards/croxel/croxel_cx1825/doc/index.rst b/boards/croxel/croxel_cx1825/doc/index.rst index f3e42b3657b..c2dc41220b7 100644 --- a/boards/croxel/croxel_cx1825/doc/index.rst +++ b/boards/croxel/croxel_cx1825/doc/index.rst @@ -44,7 +44,7 @@ Hardware - Temperature and Humidity Sensor (HTS221) - Barometric Pressure sensor (LPS22H) - Hall Effect Switch (MLX90248) -- RGB LED with Charge-Pump driver (LPS5521) +- RGB LED with Charge-Pump driver (LP5521) - Digital Microphone - Beeper - QWIIC connector supporting expansion for I2C devices diff --git a/boards/ct/ctcc/Kconfig b/boards/ct/ctcc/Kconfig new file mode 100644 index 00000000000..3a7ec750888 --- /dev/null +++ b/boards/ct/ctcc/Kconfig @@ -0,0 +1,9 @@ +# CTHINGS.CO Connectivity Card board configuration + +# Copyright (c) 2024 CTHINGS.CO +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SERIAL_BACKEND_CDC_ACM + bool "USB CDC" + default y + depends on BOARD_CTCC_NRF52840 diff --git a/boards/ct/ctcc/Kconfig.ctcc b/boards/ct/ctcc/Kconfig.ctcc new file mode 100644 index 00000000000..bdda03b4c0a --- /dev/null +++ b/boards/ct/ctcc/Kconfig.ctcc @@ -0,0 +1,7 @@ +# CTHINGS.CO Connectivity Card board configuration + +# Copyright (c) 2024 CTHINGS.CO +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CTCC + select SOC_NRF52840_QIAA if BOARD_CTCC_NRF52840 diff --git a/boards/ct/ctcc/Kconfig.defconfig b/boards/ct/ctcc/Kconfig.defconfig new file mode 100644 index 00000000000..fb74f895a03 --- /dev/null +++ b/boards/ct/ctcc/Kconfig.defconfig @@ -0,0 +1,58 @@ +# CTHINGS.CO Connectivity Card board configuration + +# Copyright (c) 2024 CTHINGS.CO +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_CTCC_NRF52840 + +if BOARD_SERIAL_BACKEND_CDC_ACM + +config USB_DEVICE_STACK + default y + +config USB_CDC_ACM + default SERIAL + +config CONSOLE + default y + +config UART_CONSOLE + default CONSOLE + +config USB_DEVICE_INITIALIZE_AT_BOOT + default y if !MCUBOOT && CONSOLE + +config USB_DEVICE_REMOTE_WAKEUP + default n + +if LOG + +# Turn off logging for USB CDC ACM +choice USB_CDC_ACM_LOG_LEVEL_CHOICE + default USB_CDC_ACM_LOG_LEVEL_OFF +endchoice + +# Turn off logging for USB Device +choice USB_DEVICE_LOG_LEVEL_CHOICE + default USB_DEVICE_LOG_LEVEL_OFF +endchoice + +# Wait 5s at startup for logging +config LOG_PROCESS_THREAD_STARTUP_DELAY_MS + default 5000 + +endif # LOG + +if USB_DEVICE_STACK + +config SERIAL + default y + +endif # USB_DEVICE_STACK + +endif # BOARD_SERIAL_BACKEND_CDC_ACM + +config BT_CTLR + default BT + +endif # BOARD_CTCC_NRF52840 diff --git a/boards/ct/ctcc/board.cmake b/boards/ct/ctcc/board.cmake new file mode 100644 index 00000000000..3a315c29fbe --- /dev/null +++ b/boards/ct/ctcc/board.cmake @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(nrfjprog "--softreset") +board_runner_args(pyocd "--target=nrf52840" "--frequency=4000000") +include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/ct/ctcc/board.yml b/boards/ct/ctcc/board.yml new file mode 100644 index 00000000000..780a02f7e7c --- /dev/null +++ b/boards/ct/ctcc/board.yml @@ -0,0 +1,4 @@ +board: + name: ctcc + socs: + - name: nrf52840 diff --git a/boards/ct/ctcc/ctcc_nrf52840.dts b/boards/ct/ctcc/ctcc_nrf52840.dts new file mode 100644 index 00000000000..0e026d1a828 --- /dev/null +++ b/boards/ct/ctcc/ctcc_nrf52840.dts @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2024 CTHINGS.CO + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include + +/ { + model = "CTHINGS.CO Connectivity Card nRF52840"; + compatible = "ct,ctcc-nrf52840"; + + chosen { + zephyr,console = &cdc_acm_uart; + zephyr,shell-uart = &cdc_acm_uart; + zephyr,uart-mcumgr = &cdc_acm_uart; + zephyr,bt-mon-uart = &cdc_acm_uart; + zephyr,bt-c2h-uart = &cdc_acm_uart; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,ieee802154 = &ieee802154; + }; + + leds { + compatible = "gpio-leds"; + led1: led_1 { + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; + label = "LED 1"; + }; + led2: led_2 { + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + label = "LED 2"; + }; + }; + + aliases { + led0 = &led1; + led1 = &led2; + mcuboot-led0 = &led1; + watchdog0 = &wdt0; + }; +}; + +&flash0 { + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00012000>; + }; + slot0_partition: partition@12000 { + label = "image-0"; + reg = <0x00012000 0x00076000>; + }; + slot1_partition: partition@87000 { + label = "image-1"; + reg = <0x00088000 0x00074000>; + }; + storage_partition: partition@fc000 { + label = "storage"; + reg = <0x000fc000 0x00004000>; + }; + }; +}; + +®1 { + regulator-initial-mode = ; +}; + +&gpiote { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&ieee802154 { + status = "okay"; +}; + +zephyr_udc0: &usbd { + compatible = "nordic,nrf-usbd"; + status = "okay"; + + cdc_acm_uart: cdc_acm_uart { + compatible = "zephyr,cdc-acm-uart"; + }; +}; diff --git a/boards/ct/ctcc/ctcc_nrf52840.yaml b/boards/ct/ctcc/ctcc_nrf52840.yaml new file mode 100644 index 00000000000..06f83148bbf --- /dev/null +++ b/boards/ct/ctcc/ctcc_nrf52840.yaml @@ -0,0 +1,15 @@ +identifier: ctcc/nrf52840 +name: CTHINGS.CO Connectivity Card nRF52840 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - ble + - gpio + - usb_cdc + - usb_device + - watchdog +vendor: ct diff --git a/boards/ct/ctcc/ctcc_nrf52840_defconfig b/boards/ct/ctcc/ctcc_nrf52840_defconfig new file mode 100644 index 00000000000..d0b5322cfeb --- /dev/null +++ b/boards/ct/ctcc/ctcc_nrf52840_defconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Board Kconfig.defconfig enables USB CDC ACM and should disable USB remote +# wakeup by default. It needs to be disabled here, because the USB nrfx +# driver always overwrites option from Kconfig mentioned above with the +# imply from CONFIG_USB_NRFX. +CONFIG_USB_DEVICE_REMOTE_WAKEUP=n diff --git a/boards/ct/ctcc/doc/img/ctcc_nrf52840_m2.webp b/boards/ct/ctcc/doc/img/ctcc_nrf52840_m2.webp new file mode 100644 index 00000000000..69aa4bd8671 Binary files /dev/null and b/boards/ct/ctcc/doc/img/ctcc_nrf52840_m2.webp differ diff --git a/boards/ct/ctcc/doc/img/ctcc_nrf52840_mpcie.webp b/boards/ct/ctcc/doc/img/ctcc_nrf52840_mpcie.webp new file mode 100644 index 00000000000..9bbd6231b5b Binary files /dev/null and b/boards/ct/ctcc/doc/img/ctcc_nrf52840_mpcie.webp differ diff --git a/boards/ct/ctcc/doc/index.rst b/boards/ct/ctcc/doc/index.rst new file mode 100644 index 00000000000..914df63b3aa --- /dev/null +++ b/boards/ct/ctcc/doc/index.rst @@ -0,0 +1,200 @@ +.. _ctcc_nrf52840: + +CTHINGS.CO Connectivity Card nRF52840 +##################################### + +Overview +******** + +The Connectivity Card nRF52840 enables BLE and IEEE 802.15.4 connectivity +over mPCIe or M.2 using USB port with on-board nRF52840 SoC. + +This board has following features: + +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/ctcc_nrf52840_mpcie.webp + :align: center + :alt: CTCC nRF52840 mPCIe + + ctcc/nrf52840 mPCie board + +.. figure:: img/ctcc_nrf52840_m2.webp + :align: center + :alt: CTCC nRF52840 M.2 + + ctcc/nrf52840 M.2 board + +More information about the board can be found at the +`ctcc_nrf52840 Website`_ and for SoC information: `Nordic Semiconductor Infocenter`_. + +Hardware +******** + +The ``ctcc/nrf52840`` board target has one external oscillator of the 32.768 kHz. + +Supported Features +================== + +The ``ctcc/nrf52840`` board target supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Connections and IOs +=================== + +LED +--- + +Note that board does not have on-board LEDs, however it exposes +LED signals on mPCIe/M.2 pins. + +* LED1 = P0.23 +* LED2 = P0.22 + +Programming and Debugging +************************* + +Applications for the ``ctcc/nrf52840`` board target can be +built in the usual way (see :ref:`build_an_application` for more details). + +Flashing +======== + +The board supports the following programming options: + +1. Using an external :ref:`debug probe ` +2. Using MCUboot with DFU support + +Option 1: Using an External Debug Probe +--------------------------------------- + +Connectivity Card can be programmed using an external debug probe (Segger J-Link) by connecting +to on-board SWD test pads. + +For Segger J-Link debug probes, follow the instructions in the +:ref:`nordic_segger` page to install and configure all the necessary +software. Further information can be found in :ref:`nordic_segger_flashing`. + +Then build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :zephyr:code-sample:`usb-cdc-acm-console` application which prints out +logs on emulated USB port. + +.. zephyr-app-commands:: + :zephyr-app: samples/subsys/usb/console + :board: ctcc/nrf52840 + :goals: build flash + +Debugging +========= + +The ``ctcc/nrf52840`` board target does not have an on-board J-Link debug IC, however +instructions from the :ref:`nordic_segger` page also apply to this board, +with the additional step of connecting an external debugger. + +Option 2: Using MCUboot with DFU support +---------------------------------------- + +It is also possible to use the MCUboot bootloader with DFU support to flash +Zephyr applications. You need to flash MCUboot with DFU support and fill in slot0 with +some application one-time using Option 1. Then you can re-flash an application using DFU utility +by loading images to slot1. Note, it's not possible to have only MCUboot and load directly +software to slot0 due to DFU implementation in Zephyr, which for present slot0 and slot1 in flash +map, it assumes only slot1 partition as writeable. + +Install ``dfu-util`` first and make sure MCUboot's ``imgtool`` is +available for signing your binary for MCUboot as described on :ref:`west-sign`. + +Next, do the **one-time setup** to flash MCUboot with DFU support. +We'll assume you've cloned the `MCUboot`_ as a submodule when initializing +Zephyr repositories using :ref:`west` tool. + +#. Compile MCUboot as a Zephyr application with DFU support. + + .. zephyr-app-commands:: + :app: mcuboot/boot/zephyr + :board: ctcc/nrf52840 + :build-dir: mcuboot + :goals: build + :gen-args: -DCONFIG_BOOT_USB_DFU_WAIT=y + +#. Flash it onto the board as described in Option 1. + +#. Flash other Zephyr application to fill in slot0 e.g: + + .. zephyr-app-commands:: + :zephyr-app: samples/subsys/usb/dfu + :board: ctcc/nrf52840 + :build-dir: dfu + :goals: build + :gen-args: -DCONFIG_BOOTLOADER_MCUBOOT=y -DCONFIG_MCUBOOT_SIGNATURE_KEY_FILE=\"path/to/mcuboot/boot/root-rsa-2048.pem\" + +You can now flash a Zephyr application to the board using DFU util. +As an example we'll use the :zephyr:code-sample:`usb-cdc-acm-console` sample. + + .. zephyr-app-commands:: + :zephyr-app: samples/subsys/usb/console + :board: ctcc/nrf52840 + :goals: build flash + :gen-args: -DCONFIG_BOOTLOADER_MCUBOOT=y -DCONFIG_MCUBOOT_SIGNATURE_KEY_FILE=\"path/to/mcuboot/boot/root-rsa-2048.pem\" + +.. note:: + + In all examples it is assumed to use default :file:`root-rsa-2048.pem` file from ``mcuboot/boot`` + directory. Providing certificate in build args produces signed binary automatically. + Do not use this certificate in your production firmware! + +#. Plug in ``ctcc/nrf52840`` card to mPCIe/M.2 slot or use mPCIe/M.2 adapter to USB + and plug such adapter to USB port. + + You should see ``NordicSemiconductor MCUBOOT`` or ``NordicSemiconductor Zephyr DFU sample`` + (if you flashed ``dfu`` sample to slot0) device once plugging it into host + USB port. You can check that on Linux system by entering ``lsusb`` command. + + To check if DFU device is visible you can enter ``sudo dfu-util -l`` command. Once the + device is visible you can flash Zephyr image using DFU util: ``sudo dfu-util --alt 1 --download build/zephyr/zephyr.signed.bin`` + + +References +********** + +.. target-notes:: + +.. _ctcc_nrf52840 Website: + https://cthings.co/products/connectivity-cards +.. _Nordic Semiconductor Infocenter: + https://infocenter.nordicsemi.com +.. _MCUboot: + https://github.com/JuulLabs-OSS/mcuboot diff --git a/boards/lairdconnect/bl652_dvk/pre_dt_board.cmake b/boards/ct/ctcc/pre_dt_board.cmake similarity index 100% rename from boards/lairdconnect/bl652_dvk/pre_dt_board.cmake rename to boards/ct/ctcc/pre_dt_board.cmake diff --git a/boards/ct/index.rst b/boards/ct/index.rst new file mode 100644 index 00000000000..9c031c3979e --- /dev/null +++ b/boards/ct/index.rst @@ -0,0 +1,10 @@ +.. _boards-ct: + +CTHINGS.CO +########## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_common.dtsi b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_common.dtsi index 437ea9ad225..764348106c9 100644 --- a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_common.dtsi +++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_common.dtsi @@ -86,7 +86,8 @@ &spi6 { cs-gpios = <&gpio_prt12 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>, - <&gpio_prt13 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + <&gpio_prt13 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - pinctrl-0 = <&p12_0_spi6_mosi &p12_1_spi6_miso &p12_2_spi6_clk>; + pinctrl-0 = <&p12_0_scb6_spi_m_mosi &p12_1_scb6_spi_m_miso &p12_2_scb6_spi_m_clk>; + pinctrl-names = "default"; }; diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347-pinctrl.dtsi b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347-pinctrl.dtsi new file mode 100644 index 00000000000..1e42a6e4646 --- /dev/null +++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347-pinctrl.dtsi @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/* Configure pin control bias mode for uart5 pins */ +&p5_1_scb5_uart_tx { + drive-push-pull; +}; + +&p5_0_scb5_uart_rx { + input-enable; +}; + +&p9_1_scb2_uart_tx { + drive-push-pull; +}; + +&p9_0_scb2_uart_rx { + input-enable; +}; + +&p13_1_scb6_uart_tx { + drive-push-pull; +}; + +&p13_0_scb6_uart_rx { + input-enable; +}; + +/* Configure pin control bias mode for SPI pins */ +&p12_0_scb6_spi_m_mosi { + drive-push-pull; +}; + +&p12_1_scb6_spi_m_miso { + input-enable; +}; + +&p12_2_scb6_spi_m_clk { + drive-push-pull; +}; diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.overlay b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.overlay index eab076f247c..9ef0f747cd0 100644 --- a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.overlay +++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.overlay @@ -3,6 +3,7 @@ * * SPDX-License-Identifier: Apache-2.0 */ +#include "cy8ckit_062_ble_cy8c6347-pinctrl.dtsi" / { aliases { @@ -21,7 +22,8 @@ interrupt-parent = <&intmux_ch21>; - pinctrl-0 = <&p5_0_uart5_rx &p5_1_uart5_tx>; + pinctrl-0 = <&p5_0_scb5_uart_rx &p5_1_scb5_uart_tx>; + pinctrl-names = "default"; }; arduino_serial: &uart5 {}; diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.overlay b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.overlay index 49944a6dea4..ea63d017a65 100644 --- a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.overlay +++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.overlay @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include "cy8ckit_062_ble_cy8c6347-pinctrl.dtsi" + / { aliases { uart-2 = &uart2; @@ -21,7 +23,9 @@ interrupt-parent = <&intmux_ch21>; - pinctrl-0 = <&p9_0_uart2_rx &p9_1_uart2_tx>; + pinctrl-0 = <&p9_0_scb2_uart_rx &p9_1_scb2_uart_tx>; + pinctrl-names = "default"; + }; &uart5 { @@ -30,7 +34,9 @@ interrupt-parent = <&intmux_ch22>; - pinctrl-0 = <&p5_0_uart5_rx &p5_1_uart5_tx>; + pinctrl-0 = <&p5_0_scb5_uart_rx &p5_1_scb5_uart_tx>; + pinctrl-names = "default"; + }; arduino_serial: &uart5 {}; diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.overlay b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.overlay index 9284d41cea7..26f422a9b4d 100644 --- a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.overlay +++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.overlay @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include "cy8ckit_062_ble_cy8c6347-pinctrl.dtsi" + / { aliases { uart-6 = &uart6; @@ -19,5 +21,6 @@ status = "okay"; current-speed = <115200>; - pinctrl-0 = <&p13_0_uart6_rx &p13_1_uart6_tx>; + pinctrl-0 = <&p13_0_scb6_uart_rx &p13_1_scb6_uart_tx>; + pinctrl-names = "default"; }; diff --git a/boards/cypress/cy8ckit_062_ble/doc/index.rst b/boards/cypress/cy8ckit_062_ble/doc/index.rst index 155f94f7b03..46940f0691a 100644 --- a/boards/cypress/cy8ckit_062_ble/doc/index.rst +++ b/boards/cypress/cy8ckit_062_ble/doc/index.rst @@ -154,7 +154,7 @@ and J12 that can be used with Segger J-Link [default]. A watchdog timer is enabled by default. To disable it call Cy_WDT_Unlock() and Cy_WDT_Disable(). -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -248,7 +248,7 @@ connections may not allow the correct use of shields. The default board revision (0.0.0) allows use of default connections. The use of Arduino headers are only possible after rework the board and using the revision 1.0.0. -#. Build the Zephyr kernel and the :ref:`hello_world` sample application for +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application for board revision 1.0.0: .. zephyr-app-commands:: diff --git a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247-pinctrl.dtsi b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247-pinctrl.dtsi new file mode 100644 index 00000000000..1e42a6e4646 --- /dev/null +++ b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247-pinctrl.dtsi @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/* Configure pin control bias mode for uart5 pins */ +&p5_1_scb5_uart_tx { + drive-push-pull; +}; + +&p5_0_scb5_uart_rx { + input-enable; +}; + +&p9_1_scb2_uart_tx { + drive-push-pull; +}; + +&p9_0_scb2_uart_rx { + input-enable; +}; + +&p13_1_scb6_uart_tx { + drive-push-pull; +}; + +&p13_0_scb6_uart_rx { + input-enable; +}; + +/* Configure pin control bias mode for SPI pins */ +&p12_0_scb6_spi_m_mosi { + drive-push-pull; +}; + +&p12_1_scb6_spi_m_miso { + input-enable; +}; + +&p12_2_scb6_spi_m_clk { + drive-push-pull; +}; diff --git a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.dts b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.dts index 18fe196201b..73766b76c10 100644 --- a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.dts +++ b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.dts @@ -9,6 +9,7 @@ #include #include +#include "cy8ckit_062_wifi_bt_cy8c6247-pinctrl.dtsi" / { model = "cy8ckit_062_wifi_bt_m0 with a Cypress PSoC6 SoC"; @@ -61,5 +62,6 @@ interrupt-parent = <&intmux_ch21>; - pinctrl-0 = <&p13_0_uart6_rx &p13_1_uart6_tx>; + pinctrl-0 = <&p13_0_scb6_uart_rx &p13_1_scb6_uart_tx>; + pinctrl-names = "default"; }; diff --git a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.dts b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.dts index 7cd87ba8634..29ea4b85134 100644 --- a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.dts +++ b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.dts @@ -7,6 +7,7 @@ /dts-v1/; #include +#include "cy8ckit_062_wifi_bt_cy8c6247-pinctrl.dtsi" / { model = "cy8ckit_062_wifi_bt_m4 with a Cypress PSoC6 SoC"; @@ -28,5 +29,6 @@ status = "okay"; current-speed = <115200>; - pinctrl-0 = <&p5_0_uart5_rx &p5_1_uart5_tx>; + pinctrl-0 = <&p5_0_scb5_uart_rx &p5_1_scb5_uart_tx>; + pinctrl-names = "default"; }; diff --git a/boards/deprecated.cmake b/boards/deprecated.cmake index 89a8b463e69..a96f68b12da 100644 --- a/boards/deprecated.cmake +++ b/boards/deprecated.cmake @@ -1,12 +1,17 @@ # SPDX-License-Identifier: Apache-2.0 -# This file contains boards in Zephyr which has been replaced with a new board +# This file contains boards in Zephyr which have been replaced with a new board # name. # This allows the system to automatically change the board while at the same # time prints a warning to the user, that the board name is deprecated. # # To add a board rename, add a line in following format: # set(_DEPRECATED ) +# +# When adding board aliases here, remember to add a mention in the corresponding GitHub issue +# tracking the removal of API/options +# https://docs.zephyrproject.org/latest/develop/api/api_lifecycle.html#deprecated, +# so these aliases are eventually removed set(96b_carbon_DEPRECATED 96b_carbon/stm32f401xe @@ -29,8 +34,11 @@ set(actinius_icarus_som_dk_ns_DEPRECATED set(actinius_icarus_som_ns_DEPRECATED actinius_icarus_som/nrf9160/ns ) +set(adafruit_feather_DEPRECATED + adafruit_feather_nrf52840/nrf52840 +) set(adafruit_feather_nrf52840_DEPRECATED - adafruit_feather + adafruit_feather_nrf52840/nrf52840 ) set(adafruit_itsybitsy_nrf52840_DEPRECATED adafruit_itsybitsy @@ -138,31 +146,61 @@ set(ebyte_e73_tbb_nrf52832_DEPRECATED ebyte_e73_tbb ) set(efm32pg_stk3402a_DEPRECATED - efm32pg_stk3402a/efm32pg12b500f1024gl125 + slstk3402a/efm32pg12b500f1024gl125 ) set(efm32pg_stk3402a_jg_DEPRECATED - efm32pg_stk3402a/efm32jg12b500f1024gl125 + slstk3402a/efm32jg12b500f1024gl125 +) +set(efm32hg_slstk3400a_DEPRECATED + slstk3400a +) +set(efm32pg_stk3401a_DEPRECATED + slstk3401a +) +set(efm32gg_stk3701a_DEPRECATED + slstk3701a +) +set(efm32gg_slwstk6121a_DEPRECATED + slwrb4321a ) set(efr32_radio_brd4104a_DEPRECATED - efr32_radio/efr32bg13p632f512gm48 + slwrb4104a ) set(efr32_radio_brd4161a_DEPRECATED - efr32_radio/efr32mg12p432f1024gl125 + slwrb4161a ) set(efr32_radio_brd4170a_DEPRECATED - efr32_radio/efr32mg12p433f1024gm68 + slwrb4170a ) set(efr32_radio_brd4180a_DEPRECATED - efr32_radio/efr32mg21a020f1024im32 + slwrb4180a ) set(efr32_radio_brd4187c_DEPRECATED - efr32_radio/efr32mg24b220f1536im48 + xg24_rb4187c ) set(efr32_radio_brd4250b_DEPRECATED - efr32_radio/efr32fg1p133f256gm48 + slwrb4250b ) set(efr32_radio_brd4255a_DEPRECATED - efr32_radio/efr32fg13p233f512gm48 + slwrb4255a +) +set(efm32gg_sltb009a_DEPRECATED + sltb009a +) +set(efr32mg_sltb004a_DEPRECATED + sltb004a +) +set(efr32bg22_brd4184a_DEPRECATED + sltb010a@0 +) +set(efr32bg22_brd4184b_DEPRECATED + sltb010a@2 +) +set(efr32xg24_dk2601b_DEPRECATED + xg24_dk2601b +) +set(efr32bg27_brd2602a_DEPRECATED + xg27_dk2602a ) set(em_starterkit_DEPRECATED em_starterkit/emsk_em9d diff --git a/boards/digilent/arty_a7/doc/index.rst b/boards/digilent/arty_a7/doc/index.rst index 4284320d6de..c6cad8d9453 100644 --- a/boards/digilent/arty_a7/doc/index.rst +++ b/boards/digilent/arty_a7/doc/index.rst @@ -159,7 +159,7 @@ etc.): Flashing ======== -Here is an example for building and flashing the :ref:`hello_world` application +Here is an example for building and flashing the :zephyr:code-sample:`hello_world` application for the Cortex-M1 reference design: .. zephyr-app-commands:: @@ -191,7 +191,7 @@ dump :file:`zephyr.mem` file suitable for initialising the block RAM using Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/digilent/arty_a7/dts/arty_a7_arm_designstart.dtsi b/boards/digilent/arty_a7/dts/arty_a7_arm_designstart.dtsi index 0f51819e180..8162b47d7d3 100644 --- a/boards/digilent/arty_a7/dts/arty_a7_arm_designstart.dtsi +++ b/boards/digilent/arty_a7/dts/arty_a7_arm_designstart.dtsi @@ -26,7 +26,6 @@ sw1 = &sw1; sw2 = &sw2; sw3 = &sw3; - spi-flash0 = &flash0; }; leds { diff --git a/boards/digilent/arty_a7/support/openocd_arty_a7_arm_designstart_m1.cfg b/boards/digilent/arty_a7/support/openocd_arty_a7_arm_designstart_m1.cfg index cf9f88347ec..213703a9247 100644 --- a/boards/digilent/arty_a7/support/openocd_arty_a7_arm_designstart_m1.cfg +++ b/boards/digilent/arty_a7/support/openocd_arty_a7_arm_designstart_m1.cfg @@ -1,7 +1,7 @@ source [find interface/cmsis-dap.cfg] source [find target/swj-dp.tcl] -adapter_khz 5000 +adapter speed 5000 set _CHIPNAME cortex_m1 set _ENDIAN little diff --git a/boards/digilent/arty_a7/support/openocd_arty_a7_arm_designstart_m3.cfg b/boards/digilent/arty_a7/support/openocd_arty_a7_arm_designstart_m3.cfg index 17dbbb997ff..9491c2df0d7 100644 --- a/boards/digilent/arty_a7/support/openocd_arty_a7_arm_designstart_m3.cfg +++ b/boards/digilent/arty_a7/support/openocd_arty_a7_arm_designstart_m3.cfg @@ -1,7 +1,7 @@ source [find interface/cmsis-dap.cfg] source [find target/swj-dp.tcl] -adapter_khz 5000 +adapter speed 5000 set _CHIPNAME cortex_m3 set _ENDIAN little diff --git a/boards/digilent/zybo/doc/index.rst b/boards/digilent/zybo/doc/index.rst index f8e3857227d..7b5bf386f03 100644 --- a/boards/digilent/zybo/doc/index.rst +++ b/boards/digilent/zybo/doc/index.rst @@ -77,7 +77,7 @@ Clone and build Das U-Boot for the Digilent Zybo: Flashing ======== -Here is an example for running the :ref:`hello_world` application via JTAG. +Here is an example for running the :zephyr:code-sample:`hello_world` application via JTAG. Ensure the board is configured for JTAG boot, open a serial terminal, turn on/reset the board (press the ``PS-SRST`` button), and initialize the Zynq-7000 series SoC by uploading and running the U-Boot @@ -97,7 +97,7 @@ You should see the following message in the terminal: *** Booting Zephyr OS vx.xx.x-xxx-gxxxxxxxxxxxx *** Hello World! zybo -Another option is to load and run the :ref:`hello_world` application via U-Boot. Copy +Another option is to load and run the :zephyr:code-sample:`hello_world` application via U-Boot. Copy ``u-boot/spl/boot.bin``, ``u-boot/u-boot.img``, and ``zephyr/zephyr.bin`` to a FAT32 formatted microSD card, insert the card in the ``SD MICRO`` slot on the Zybo board, ensure the board is configured for ``SD`` boot, and turn on the board. @@ -116,7 +116,7 @@ Once U-boot is done initializing, load an run the Zephyr application: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Ensure the board is configured for JTAG boot, open a serial terminal, turn on/reset the board (press the ``PS-SRST`` button), and initialize the Zynq-7000 series SoC by uploading and running the U-Boot diff --git a/boards/dptechnics/index.rst b/boards/dptechnics/index.rst new file mode 100644 index 00000000000..5250730214b --- /dev/null +++ b/boards/dptechnics/index.rst @@ -0,0 +1,10 @@ +.. _boards-dptechnics: + +DPTechnics +########## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/dptechnics/walter/Kconfig.defconfig b/boards/dptechnics/walter/Kconfig.defconfig new file mode 100644 index 00000000000..642988e72fe --- /dev/null +++ b/boards/dptechnics/walter/Kconfig.defconfig @@ -0,0 +1,20 @@ +# Copyright (c) 2024 DPTechnics bv +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_WALTER_ESP32S3_PROCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +endif # BOARD_WALTER_ESP32S3_PROCPU + +if BOARD_WALTER_ESP32S3_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 256 + +endif # BOARD_WALTER_ESP32S3_APPCPU diff --git a/boards/dptechnics/walter/Kconfig.sysbuild b/boards/dptechnics/walter/Kconfig.sysbuild new file mode 100644 index 00000000000..2c336571d83 --- /dev/null +++ b/boards/dptechnics/walter/Kconfig.sysbuild @@ -0,0 +1,10 @@ +# Copyright (c) 2024 DPTechnics bv +# SPDX-License-Identifier: Apache-2.0 + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice BOOT_SIGNATURE_TYPE + default BOOT_SIGNATURE_TYPE_NONE +endchoice diff --git a/boards/dptechnics/walter/Kconfig.walter b/boards/dptechnics/walter/Kconfig.walter new file mode 100644 index 00000000000..5e0fe1ae840 --- /dev/null +++ b/boards/dptechnics/walter/Kconfig.walter @@ -0,0 +1,7 @@ +# Copyright (c) 2024 DPTechnics bv +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_WALTER + select SOC_ESP32S3_WROOM_N16R2 + select SOC_ESP32S3_PROCPU if BOARD_WALTER_ESP32S3_PROCPU + select SOC_ESP32S3_APPCPU if BOARD_WALTER_ESP32S3_APPCPU diff --git a/boards/dptechnics/walter/board.cmake b/boards/dptechnics/walter/board.cmake new file mode 100644 index 00000000000..2f04d1fe886 --- /dev/null +++ b/boards/dptechnics/walter/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/dptechnics/walter/board.yml b/boards/dptechnics/walter/board.yml new file mode 100644 index 00000000000..c416d547fb2 --- /dev/null +++ b/boards/dptechnics/walter/board.yml @@ -0,0 +1,5 @@ +board: + name: walter + vendor: dptechnics + socs: + - name: esp32s3 diff --git a/boards/dptechnics/walter/doc/img/walter.webp b/boards/dptechnics/walter/doc/img/walter.webp new file mode 100644 index 00000000000..b29c42184e4 Binary files /dev/null and b/boards/dptechnics/walter/doc/img/walter.webp differ diff --git a/boards/dptechnics/walter/doc/index.rst b/boards/dptechnics/walter/doc/index.rst new file mode 100644 index 00000000000..bb8d9eecbf5 --- /dev/null +++ b/boards/dptechnics/walter/doc/index.rst @@ -0,0 +1,276 @@ +.. _walter: + +DPTechnics Walter +################# + +Overview +******** + +Walter is a compact IoT development board that combines an Espressif ESP32-S3 SoC +with a Sequans Monarch 2 GM02SP LTE-M/NB-IoT/GNSS modem. +More information about Walter can be found on the `QuickSpot Website`_ and on the +`QuickSpot GitHub page`_. + +.. figure:: img/walter.webp + :align: center + :alt: DPTechnics Walter board + + DPTechnics Walter board (Credit: DPTechnics bv) + +Hardware +******** + +ESP32-S3-WROOM-1-N16R2 microcontroller: + +- Xtensa dual-core 32-bit LX7 CPU +- 16 MiB quad SPI flash memory +- 2 MiB quad SPI PSRAM +- 150 Mbps 802.11 b/g/n Wi-Fi 4 with on-board PCB antenna +- 2 Mbps Bluetooth 5 Low Energy with on-board PCB antenna + +Sequans Monarch 2 GM02SP modem: + +- Dual-mode LTE-M / NB-IoT (NB1, NB2) +- 3GPP LTE release 14 (Upgradable up to release 17) +- Ultra-low, deep-sleep mode in eDRX and PSM +- Adaptive +23 dBm, +20 dBm and +14 dBm output power +- Integrated LNA and SAW filter for GNSS reception +- Assisted and non-assisted GNSS with GPS and Galileo constellations +- Integrated SIM card +- Nano-SIM card slot +- u.FL RF connectors for GNSS and 5G antennas + +Inputs & outputs: + +- 24 GPIO pins for application use +- UART, SPI, I²C, CAN, I²S, and SD available on any of the GPIO pins +- ADC, DAC, and PWM integrated in ESP32-S3 +- 3.3 V software-controllable output +- USB Type-C connector for flashing and debugging +- 22 test points for production programming and testing +- On-board reset button + +Power supply + +- 5.0 V via USB Type-C +- 3.0 - 5.5 V via Vin pin +- Not allowed to use both power inputs simultaneously +- Designed for extremely low quiescent current + +Form factor + +- Easy to integrate via 2.54 mm headers +- 55 mm x 24.8 mm board dimensions +- Pin and footprint compatible with EOL Pycom GPy +- Breadboard friendly + +Supported Features +================== + +Current Zephyr's Walter board supports the following features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| TWAI/CAN | on-chip | can | ++------------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| MCPWM | on-chip | pwm | ++------------+------------+-------------------------------------+ +| PCNT | on-chip | qdec | ++------------+------------+-------------------------------------+ +| GDMA | on-chip | dma | ++------------+------------+-------------------------------------+ +| USB-CDC | on-chip | serial | ++------------+------------+-------------------------------------+ +| Wi-Fi | on-chip | | ++------------+------------+-------------------------------------+ +| Bluetooth | on-chip | | ++------------+------------+-------------------------------------+ +| Cellular | on-board | modem_cellular | ++------------+------------+-------------------------------------+ + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: + + Simple boot does not provide any security features nor OTA updates. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32-S3 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: walter/esp32s3/procpu + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │   └── zephyr + │   ├── zephyr.elf + │   └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: walter/esp32s3/procpu + :goals: build + +The usual ``flash`` target will work with the ``walter`` board +configuration. Here is an example for the :zephyr:code-sample:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: walter/esp32s3/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! walter/esp32s3/procpu + +Debugging +********* + +ESP32-S3 support on OpenOCD is available at `OpenOCD ESP32`_. + +ESP32-S3 has a built-in JTAG circuitry and can be debugged without any additional chip. Only an USB cable connected to the D+/D- pins is necessary. + +Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32-S3`_. + +Here is an example for building the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: walter/esp32s3/procpu + :goals: build flash + +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: walter/esp32s3/procpu + :goals: debug + +References +********** + +.. target-notes:: + +.. _`QuickSpot Website`: https://www.quickspot.io/ +.. _`QuickSpot GitHub page`: https://github.com/QuickSpot +.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ +.. _`OpenOCD ESP32`: https://github.com/openocd-org/openocd diff --git a/boards/dptechnics/walter/support/openocd.cfg b/boards/dptechnics/walter/support/openocd.cfg new file mode 100644 index 00000000000..2f740b4a36a --- /dev/null +++ b/boards/dptechnics/walter/support/openocd.cfg @@ -0,0 +1,7 @@ +set ESP_RTOS none +set ESP32_ONLYCPU 1 + +# Source the JTAG interface configuration file +source [find interface/esp_usb_jtag.cfg] +# Source the ESP32-S3 configuration file +source [find target/esp32s3.cfg] diff --git a/boards/dptechnics/walter/walter-pinctrl.dtsi b/boards/dptechnics/walter/walter-pinctrl.dtsi new file mode 100644 index 00000000000..001d18be8dc --- /dev/null +++ b/boards/dptechnics/walter/walter-pinctrl.dtsi @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2024 DPTechnics bv + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + uart1_default: uart1_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + group3 { + pinmux = ; + output-high; + }; + group4 { + pinmux = ; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; + + i2c1_default: i2c1_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; + + spim2_default: spim2_default { + group1 { + pinmux = , + , + ; + }; + group2 { + pinmux = ; + output-low; + }; + }; + + spim3_default: spim3_default { + group1 { + pinmux = , + , + ; + }; + group2 { + pinmux = ; + output-low; + }; + }; + + twai_default: twai_default { + group1 { + pinmux = , + ; + }; + }; +}; diff --git a/boards/dptechnics/walter/walter_esp32s3_appcpu.dts b/boards/dptechnics/walter/walter_esp32s3_appcpu.dts new file mode 100644 index 00000000000..a2ef2198559 --- /dev/null +++ b/boards/dptechnics/walter/walter_esp32s3_appcpu.dts @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2024 DPTechnics bv + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include + +/ { + model = "DPTechnics Walter APPCPU"; + compatible = "espressif,esp32s3"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&trng0 { + status = "okay"; +}; + +&ipm0 { + status = "okay"; +}; diff --git a/boards/dptechnics/walter/walter_esp32s3_appcpu.yaml b/boards/dptechnics/walter/walter_esp32s3_appcpu.yaml new file mode 100644 index 00000000000..4c83151153e --- /dev/null +++ b/boards/dptechnics/walter/walter_esp32s3_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: walter/esp32s3/appcpu +name: Walter APPCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: dptechnics diff --git a/boards/dptechnics/walter/walter_esp32s3_appcpu_defconfig b/boards/dptechnics/walter/walter_esp32s3_appcpu_defconfig new file mode 100644 index 00000000000..9abf2ff0430 --- /dev/null +++ b/boards/dptechnics/walter/walter_esp32s3_appcpu_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y diff --git a/boards/dptechnics/walter/walter_esp32s3_procpu.dts b/boards/dptechnics/walter/walter_esp32s3_procpu.dts new file mode 100644 index 00000000000..310fa5d59df --- /dev/null +++ b/boards/dptechnics/walter/walter_esp32s3_procpu.dts @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2024 DPTechnics bv + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include "espressif/esp32s3/esp32s3_wroom_n16r2.dtsi" +#include "walter-pinctrl.dtsi" +#include + +/ { + model = "DPTechnics Walter PROCPU"; + compatible = "espressif,esp32s3"; + + aliases { + modem = &modem; + modem-uart = &uart1; + i2c-0 = &i2c0; + watchdog0 = &wdt0; + uart-0 = &usb_serial; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &usb_serial; + zephyr,shell-uart = &usb_serial; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,bt-hci = &esp32_bt_hci; + }; +}; + +&usb_serial { + status = "okay"; +}; + +&uart0 { + status = "disabled"; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + hw-flow-control; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; + modem: modem { + status = "okay"; + compatible = "sqn,gm02s"; + mdm-reset-gpios = <&gpio1 13 (GPIO_OPEN_DRAIN | GPIO_ACTIVE_LOW)>; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&i2c1 { + clock-frequency = ; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; +}; + +&twai { + pinctrl-0 = <&twai_default>; + pinctrl-names = "default"; +}; + +&timer0 { + status = "disabled"; +}; + +&timer1 { + status = "disabled"; +}; + +&timer2 { + status = "disabled"; +}; + +&timer3 { + status = "disabled"; +}; + +&wdt0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&esp32_bt_hci { + status = "okay"; +}; diff --git a/boards/dptechnics/walter/walter_esp32s3_procpu.yaml b/boards/dptechnics/walter/walter_esp32s3_procpu.yaml new file mode 100644 index 00000000000..839c29069a7 --- /dev/null +++ b/boards/dptechnics/walter/walter_esp32s3_procpu.yaml @@ -0,0 +1,23 @@ +identifier: walter/esp32s3/procpu +name: Walter PROCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - uart + - i2c + - spi + - can + - counter + - watchdog + - entropy + - pwm + - dma + - input +testing: + ignore_tags: + - net + - bluetooth +vendor: dptechnics diff --git a/boards/dptechnics/walter/walter_esp32s3_procpu_defconfig b/boards/dptechnics/walter/walter_esp32s3_procpu_defconfig new file mode 100644 index 00000000000..59f3df7a866 --- /dev/null +++ b/boards/dptechnics/walter/walter_esp32s3_procpu_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/dragino/lsn50/doc/index.rst b/boards/dragino/lsn50/doc/index.rst index b3d14f92885..4a29c56af1d 100644 --- a/boards/dragino/lsn50/doc/index.rst +++ b/boards/dragino/lsn50/doc/index.rst @@ -149,7 +149,7 @@ Dragino LSN50 board requires an external debugger. Flashing an application to Dragino LSN50 ---------------------------------------- -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Connect the Dragino LSN50 to a STLinkV2 to your host computer using the USB port, then run a serial host program to connect with your board. For example: @@ -175,7 +175,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/dragino/lsn50/dragino_lsn50_defconfig b/boards/dragino/lsn50/dragino_lsn50_defconfig index 06e8a32bb1f..e3d8f7bb3d2 100644 --- a/boards/dragino/lsn50/dragino_lsn50_defconfig +++ b/boards/dragino/lsn50/dragino_lsn50_defconfig @@ -9,9 +9,3 @@ CONFIG_UART_CONSOLE=y # GPIO Controller CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/dragino/nbsn95/doc/index.rst b/boards/dragino/nbsn95/doc/index.rst index 09a8b91f6ce..27e32b7d06f 100644 --- a/boards/dragino/nbsn95/doc/index.rst +++ b/boards/dragino/nbsn95/doc/index.rst @@ -148,7 +148,7 @@ Dragino NBSN95 board requires an external debugger. Flashing an application to Dragino NBSN95 ----------------------------------------- -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Connect the Dragino NBSN95 to a STLinkV2 to your host computer using the USB port, then run a serial host program to connect with your board. For example: @@ -174,7 +174,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/dragino/nbsn95/dragino_nbsn95_defconfig b/boards/dragino/nbsn95/dragino_nbsn95_defconfig index 1a570d28d13..d680df64400 100644 --- a/boards/dragino/nbsn95/dragino_nbsn95_defconfig +++ b/boards/dragino/nbsn95/dragino_nbsn95_defconfig @@ -10,9 +10,3 @@ CONFIG_UART_CONSOLE=y # GPIO Controller CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/electronut/nrf52840_blip/Kconfig b/boards/electronut/nrf52840_blip/Kconfig deleted file mode 100644 index c733e6aca3d..00000000000 --- a/boards/electronut/nrf52840_blip/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Electronut Labs Blip board configuration - -# Copyright (c) 2018 Electronut Labs -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_NRF52840_BLIP diff --git a/boards/electronut/nrf52840_blip/doc/index.rst b/boards/electronut/nrf52840_blip/doc/index.rst index 9f78cee51ec..67a736bcd06 100644 --- a/boards/electronut/nrf52840_blip/doc/index.rst +++ b/boards/electronut/nrf52840_blip/doc/index.rst @@ -141,7 +141,7 @@ Flashing Applications are flashed and run as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/electronut/nrf52840_blip/nrf52840_blip.dts b/boards/electronut/nrf52840_blip/nrf52840_blip.dts index 3866cdd9733..5658a1ddd09 100644 --- a/boards/electronut/nrf52840_blip/nrf52840_blip.dts +++ b/boards/electronut/nrf52840_blip/nrf52840_blip.dts @@ -9,6 +9,7 @@ /dts-v1/; #include +#include #include "nrf52840_blip-pinctrl.dtsi" #include @@ -17,14 +18,11 @@ compatible = "nordic,pca10056-dk"; chosen { - zephyr,code-partition = &slot0_partition; zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,uart-mcumgr = &uart0; zephyr,bt-mon-uart = &uart0; zephyr,bt-c2h-uart = &uart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; zephyr,ieee802154 = &ieee802154; }; @@ -63,6 +61,10 @@ }; }; +®1 { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; @@ -145,46 +147,6 @@ status = "okay"; }; -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000C000>; - }; - slot0_partition: partition@c000 { - label = "image-0"; - reg = <0x0000C000 0x00067000>; - }; - slot1_partition: partition@73000 { - label = "image-1"; - reg = <0x00073000 0x00067000>; - }; - scratch_partition: partition@da000 { - label = "image-scratch"; - reg = <0x000da000 0x0001e000>; - }; - - /* - * The flash starting at 0x000f8000 and ending at - * 0x000fffff is reserved for use by the application. - */ - - /* - * Storage partition will be used by FCB/LittleFS/NVS - * if enabled. - */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; - zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; diff --git a/boards/electronut/nrf52840_papyr/Kconfig b/boards/electronut/nrf52840_papyr/Kconfig deleted file mode 100644 index 4829ceaae72..00000000000 --- a/boards/electronut/nrf52840_papyr/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Electronut Labs Papyr board configuration - -# Copyright (c) 2018 Electronut Labs -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_NRF52840_PAPYR diff --git a/boards/electronut/nrf52840_papyr/doc/nrf52840_papyr.rst b/boards/electronut/nrf52840_papyr/doc/nrf52840_papyr.rst index 7890cd108e4..814ef881360 100644 --- a/boards/electronut/nrf52840_papyr/doc/nrf52840_papyr.rst +++ b/boards/electronut/nrf52840_papyr/doc/nrf52840_papyr.rst @@ -151,7 +151,7 @@ debugger (see _Bumpy). Applications are flashed and run as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/electronut/nrf52840_papyr/nrf52840_papyr.dts b/boards/electronut/nrf52840_papyr/nrf52840_papyr.dts index 43d81a4adc0..dee9c3db20c 100644 --- a/boards/electronut/nrf52840_papyr/nrf52840_papyr.dts +++ b/boards/electronut/nrf52840_papyr/nrf52840_papyr.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include "nrf52840_papyr-pinctrl.dtsi" #include @@ -14,14 +15,11 @@ compatible = "nordic,pca10056-dk"; chosen { - zephyr,code-partition = &slot0_partition; zephyr,console = &uart0; zephyr,uart-mcumgr = &uart0; zephyr,shell-uart = &uart0; zephyr,bt-mon-uart = &uart0; zephyr,bt-c2h-uart = &uart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; zephyr,ieee802154 = &ieee802154; }; @@ -82,6 +80,10 @@ }; }; +®1 { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; @@ -138,45 +140,6 @@ status = "okay"; }; -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000C000>; - }; - slot0_partition: partition@c000 { - label = "image-0"; - reg = <0x0000C000 0x00067000>; - }; - slot1_partition: partition@73000 { - label = "image-1"; - reg = <0x00073000 0x00067000>; - }; - scratch_partition: partition@da000 { - label = "image-scratch"; - reg = <0x000da000 0x0001e000>; - }; - - /* - * The flash starting at 0x000f8000 and ending at - * 0x000fffff is reserved for use by the application. - */ - - /* - * Storage partition will be used by FCB/LittleFS/NVS - * if enabled. - */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; - zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; diff --git a/boards/element14/warp7/Kconfig.defconfig b/boards/element14/warp7/Kconfig.defconfig index b73424093e0..fcb09419c35 100644 --- a/boards/element14/warp7/Kconfig.defconfig +++ b/boards/element14/warp7/Kconfig.defconfig @@ -13,11 +13,4 @@ config FXAS21002_DRDY_INT1 default y depends on FXAS21002_TRIGGER -if !XIP -config FLASH_SIZE - default 0 -config FLASH_BASE_ADDRESS - default 0 -endif - endif # BOARD_WARP7 diff --git a/boards/enjoydigital/litex_vexriscv/doc/index.rst b/boards/enjoydigital/litex_vexriscv/doc/index.rst index 2946802be5e..f9764907eb4 100644 --- a/boards/enjoydigital/litex_vexriscv/doc/index.rst +++ b/boards/enjoydigital/litex_vexriscv/doc/index.rst @@ -184,7 +184,7 @@ Use `ecpprog `_ to upload the bitstream t ecpprog -S antmicro_sdi_mipi_video_converter.bit -You can boot from a serial port using litex_term (replace `ttyUSBX` with your device) , e.g.: +You can boot from a serial port using litex_term (replace ``ttyUSBX`` with your device) , e.g.: .. code-block:: bash diff --git a/boards/enjoydigital/litex_vexriscv/litex_vexriscv.dts b/boards/enjoydigital/litex_vexriscv/litex_vexriscv.dts index eab0c152666..19f56f8b289 100644 --- a/boards/enjoydigital/litex_vexriscv/litex_vexriscv.dts +++ b/boards/enjoydigital/litex_vexriscv/litex_vexriscv.dts @@ -17,12 +17,20 @@ zephyr,sram = &ram0; }; + aliases { + watchdog0 = &wdt0; + }; + ram0: memory@40000000 { device_type = "memory"; reg = <0x40000000 0x10000000>; }; }; +&ctrl0 { + status = "okay"; +}; + &uart0 { status = "okay"; current-speed = <115200>; @@ -32,6 +40,18 @@ status = "okay"; }; +&wdt0 { + status = "okay"; +}; + +&mdio0 { + status = "okay"; +}; + +&phy0 { + status = "okay"; +}; + ð0 { status = "okay"; }; diff --git a/boards/enjoydigital/litex_vexriscv/litex_vexriscv.yaml b/boards/enjoydigital/litex_vexriscv/litex_vexriscv.yaml index 6d96923354e..b0dcc5b14a1 100644 --- a/boards/enjoydigital/litex_vexriscv/litex_vexriscv.yaml +++ b/boards/enjoydigital/litex_vexriscv/litex_vexriscv.yaml @@ -12,8 +12,12 @@ toolchain: - zephyr ram: 262144 supported: + - gpio + - uart - spi - i2s + - i2c + - watchdog testing: ignore_tags: - bluetooth diff --git a/boards/enjoydigital/litex_vexriscv/litex_vexriscv_defconfig b/boards/enjoydigital/litex_vexriscv/litex_vexriscv_defconfig index d51a5923ff8..8743c6702c6 100644 --- a/boards/enjoydigital/litex_vexriscv/litex_vexriscv_defconfig +++ b/boards/enjoydigital/litex_vexriscv/litex_vexriscv_defconfig @@ -11,3 +11,4 @@ CONFIG_GPIO=y CONFIG_XIP=n CONFIG_CLOCK_CONTROL=y CONFIG_HEAP_MEM_POOL_SIZE=4096 +CONFIG_SPI_NOR_SFDP_RUNTIME=y diff --git a/boards/espressif/esp32_devkitc_wroom/doc/index.rst b/boards/espressif/esp32_devkitc_wroom/doc/index.rst index ec1248da38e..68955f9c17c 100644 --- a/boards/espressif/esp32_devkitc_wroom/doc/index.rst +++ b/boards/espressif/esp32_devkitc_wroom/doc/index.rst @@ -1,17 +1,17 @@ .. _esp32_devkitc_wroom: -ESP32-DEVKITC-WROOM +ESP32-DevKitC-WROOM ################### Overview ******** -ESP32-DEVKITC-WROOM is a series of low cost, low power system on a chip microcontrollers -with integrated Wi-Fi & dual-mode Bluetooth. The ESP32 series employs a +ESP32 is a series of low cost, low power system on a chip microcontrollers +with integrated Wi-Fi & dual-mode Bluetooth. The ESP32 series employs a Tensilica Xtensa LX6 microprocessor in both dual-core and single-core -variations. ESP32-WROOM is created and developed by Espressif Systems, a +variations. ESP32 is created and developed by Espressif Systems, a Shanghai-based Chinese company, and is manufactured by TSMC using their 40nm -process. [1]_ +process. For more information, check `ESP32-DevKitC-WROOM`_. The features include the following: @@ -43,25 +43,27 @@ The features include the following: .. figure:: img/esp32_devkitc_wroom.jpg :align: center - :alt: ESP32-DEVKITC-WROOM + :alt: ESP32-DevKitC-WROOM ESP32-DevKitC-WROOM-32D DK +For more information, check the datasheet at `ESP32 Datasheet`_ or the technical reference +manual at `ESP32 Technical Reference Manual`_. + Asymmetric Multiprocessing (AMP) ******************************** -ESP32-DEVKITC-WROOM allows 2 different applications to be executed in ESP32 SoC. Due to its dual-core architecture, each core can be enabled to execute customized tasks in stand-alone mode +ESP32-DevKitC-WROOM allows 2 different applications to be executed in ESP32 SoC. Due to its dual-core architecture, each core can be enabled to execute customized tasks in stand-alone mode and/or exchanging data over OpenAMP framework. See :ref:`ipc_samples` folder as code reference. Supported Features ================== -Current Zephyr's ESP32-WROOM board supports the following features: +Current Zephyr's ESP32-DevKitC-WROOM board supports the following features: +------------+------------+-------------------------------------+ | Interface | Controller | Driver/Component | +============+============+=====================================+ -+------------+------------+-------------------------------------+ | UART | on-chip | serial port | +------------+------------+-------------------------------------+ | GPIO | on-chip | gpio | @@ -131,7 +133,7 @@ MCUboot bootloader ================== User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. +must be built (and flashed) at least once. There are two options to be used when building an application: @@ -142,9 +144,10 @@ There are two options to be used when building an application: User can select the MCUboot bootloader by adding the following line to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y Sysbuild ======== @@ -156,7 +159,7 @@ To build the sample application using sysbuild use the command: .. zephyr-app-commands:: :tool: west - :app: samples/hello_world + :zephyr-app: samples/hello_world :board: esp_wrover_kit :goals: build :west-args: --sysbuild @@ -192,7 +195,7 @@ Manual build ============ During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. +For that reason, images can be built one at a time using traditional build. The instructions following are relevant for both manual build and sysbuild. The only difference is the structure of the build directory. @@ -210,7 +213,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``esp32_devkitc_wroom`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -235,10 +238,9 @@ message in the monitor: Debugging ********* -ESP32-DEVKITC-WROOM support on OpenOCD is available upstream as of version 0.12.0. -Download and install OpenOCD from `OpenOCD`_. +ESP32 support on OpenOCD is available at `OpenOCD ESP32`_. -On the ESP-WROOM-32 DevKitC board, the JTAG pins are not run to a +On the ESP32-DevKitC-WROOM board, the JTAG pins are not run to a standard connector (e.g. ARM 20-pin) and need to be manually connected to the external programmer (e.g. a Flyswatter2): @@ -260,17 +262,16 @@ to the external programmer (e.g. a Flyswatter2): | IO15 | TDO | +------------+-----------+ -Further documentation can be obtained from the SoC vendor in `JTAG debugging -for ESP32`_. +Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32`_. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: esp32_devkitc_wroom/esp32/procpu :goals: build flash -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -288,12 +289,11 @@ GDB stub is enabled on ESP32. This does not work as the code is on flash which cannot be randomly accessed for modification. -.. _`JTAG debugging for ESP32`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/jtag-debugging/index.html -.. _`OpenOCD`: https://github.com/openocd-org/openocd - References ********** -.. [1] https://en.wikipedia.org/wiki/ESP32 -.. _ESP32 Technical Reference Manual: https://espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf -.. _Hardware Reference: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/hw-reference/index.html +.. _`ESP32-DevKitC-WROOM`: https://docs.espressif.com/projects/esp-idf/en/stable/esp32/hw-reference/esp32/get-started-devkitc.html# +.. _`ESP32 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf +.. _`ESP32 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf +.. _`JTAG debugging for ESP32`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/jtag-debugging/index.html +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.dts b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.dts index c52b029ea55..e86ffdb90bf 100644 --- a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.dts +++ b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include / { model = "Espressif ESP32-DevkitC APPCPU"; @@ -18,14 +19,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &ipm0 { status = "okay"; }; @@ -33,42 +26,3 @@ &trng0 { status = "okay"; }; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.dts b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.dts index 1daad17069f..fb3075c028e 100644 --- a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.dts +++ b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.dts @@ -9,6 +9,7 @@ #include "esp32_devkitc_wroom-pinctrl.dtsi" #include #include +#include / { model = "Espressif ESP32-DevkitC PROCPU"; @@ -40,15 +41,6 @@ }; }; -&cpu0 { - clock-frequency = ; - cpu-power-states = <&light_sleep &deep_sleep>; -}; - -&cpu1 { - clock-frequency = ; -}; - &uart0 { status = "okay"; current-speed = <115200>; @@ -137,45 +129,6 @@ status = "disabled"; }; -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; - &esp32_bt_hci { status = "okay"; }; diff --git a/boards/espressif/esp32_devkitc_wrover/doc/index.rst b/boards/espressif/esp32_devkitc_wrover/doc/index.rst index 1f66f3da8a9..81c75c598ca 100644 --- a/boards/espressif/esp32_devkitc_wrover/doc/index.rst +++ b/boards/espressif/esp32_devkitc_wrover/doc/index.rst @@ -1,17 +1,17 @@ .. _esp32_devkitc_wrover: -ESP32-DEVKITC-WROVER +ESP32-DevKitC-WROVER #################### Overview ******** ESP32 is a series of low cost, low power system on a chip microcontrollers -with integrated Wi-Fi & dual-mode Bluetooth. The ESP32 series employs a +with integrated Wi-Fi & dual-mode Bluetooth. The ESP32 series employs a Tensilica Xtensa LX6 microprocessor in both dual-core and single-core -variations. ESP32 is created and developed by Espressif Systems, a +variations. ESP32 is created and developed by Espressif Systems, a Shanghai-based Chinese company, and is manufactured by TSMC using their 40nm -process. [1]_ +process. For more information, check `ESP32-DevKitC-WROVER`_. The features include the following: @@ -43,25 +43,27 @@ The features include the following: .. figure:: img/esp32_devkitc_wrover.jpg :align: center - :alt: ESP32-DEVKITC-WROVER + :alt: ESP32-DevKitC-WROVER ESP32-DevKitC-WROVER-IE +For more information, check the datasheet at `ESP32 Datasheet`_ or the technical reference +manual at `ESP32 Technical Reference Manual`_. + Asymmetric Multiprocessing (AMP) ******************************** -ESP32-DEVKITC-WROVER allows 2 different applications to be executed in ESP32 SoC. Due to its dual-core architecture, each core can be enabled to execute customized tasks in stand-alone mode +ESP32-DevKitC-WROVER allows 2 different applications to be executed in ESP32 SoC. Due to its dual-core architecture, each core can be enabled to execute customized tasks in stand-alone mode and/or exchanging data over OpenAMP framework. See :ref:`ipc_samples` folder as code reference. Supported Features ================== -Current Zephyr's ESP32-devkitc board supports the following features: +Current Zephyr's ESP32-DevKitC-WROVER board supports the following features: +------------+------------+-------------------------------------+ | Interface | Controller | Driver/Component | +============+============+=====================================+ -+------------+------------+-------------------------------------+ | UART | on-chip | serial port | +------------+------------+-------------------------------------+ | GPIO | on-chip | gpio | @@ -131,7 +133,7 @@ MCUboot bootloader ================== User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. +must be built (and flashed) at least once. There are two options to be used when building an application: @@ -142,9 +144,10 @@ There are two options to be used when building an application: User can select the MCUboot bootloader by adding the following line to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y Sysbuild ======== @@ -156,7 +159,7 @@ To build the sample application using sysbuild use the command: .. zephyr-app-commands:: :tool: west - :app: samples/hello_world + :zephyr-app: samples/hello_world :board: esp32_devkitc_wrover :goals: build :west-args: --sysbuild @@ -192,7 +195,7 @@ Manual build ============ During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. +For that reason, images can be built one at a time using traditional build. The instructions following are relevant for both manual build and sysbuild. The only difference is the structure of the build directory. @@ -210,7 +213,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``esp32_devkitc_wrover`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -235,10 +238,9 @@ message in the monitor: Debugging ********* -ESP32 support on OpenOCD is available upstream as of version 0.12.0. -Download and install OpenOCD from `OpenOCD`_. +ESP32 support on OpenOCD is available at `OpenOCD ESP32`_. -On the ESP-WROOM-32 DevKitC board, the JTAG pins are not run to a +On the ESP32-DevKitC-WROVER board, the JTAG pins are not run to a standard connector (e.g. ARM 20-pin) and need to be manually connected to the external programmer (e.g. a Flyswatter2): @@ -260,17 +262,16 @@ to the external programmer (e.g. a Flyswatter2): | IO15 | TDO | +------------+-----------+ -Further documentation can be obtained from the SoC vendor in `JTAG debugging -for ESP32`_. +Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32`_. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: esp32_devkitc_wrover/esp32/procpu :goals: build flash -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -288,12 +289,11 @@ GDB stub is enabled on ESP32. This does not work as the code is on flash which cannot be randomly accessed for modification. -.. _`JTAG debugging for ESP32`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/jtag-debugging/index.html -.. _`OpenOCD`: https://github.com/openocd-org/openocd - References ********** -.. [1] https://en.wikipedia.org/wiki/ESP32 -.. _ESP32 Technical Reference Manual: https://espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf -.. _Hardware Reference: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/hw-reference/index.html +.. _`ESP32-DevKitC-WROVER`: https://docs.espressif.com/projects/esp-idf/en/stable/esp32/hw-reference/esp32/get-started-devkitc.html# +.. _`ESP32 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf +.. _`ESP32 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf +.. _`JTAG debugging for ESP32`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/jtag-debugging/index.html +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.dts b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.dts index 7298148a2c3..81078114c97 100644 --- a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.dts +++ b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include / { model = "Espressif ESP32-DevkitC WROVER-E APPCPU"; @@ -18,14 +19,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &ipm0 { status = "okay"; }; @@ -33,42 +26,3 @@ &trng0 { status = "okay"; }; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.dts b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.dts index bbdd91e6c87..df8e3c019fc 100644 --- a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.dts +++ b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.dts @@ -9,6 +9,7 @@ #include "esp32_devkitc_wrover-pinctrl.dtsi" #include #include +#include / { model = "Espressif ESP32-DevkitC WROVER-E PROCPU"; @@ -40,14 +41,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &uart0 { status = "okay"; current-speed = <115200>; @@ -132,45 +125,6 @@ status = "okay"; }; -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; - &esp32_bt_hci { status = "okay"; }; diff --git a/boards/espressif/esp32_ethernet_kit/Kconfig.defconfig b/boards/espressif/esp32_ethernet_kit/Kconfig.defconfig index 57924049022..75b0cc9f631 100644 --- a/boards/espressif/esp32_ethernet_kit/Kconfig.defconfig +++ b/boards/espressif/esp32_ethernet_kit/Kconfig.defconfig @@ -6,7 +6,7 @@ if BOARD_ESP32_ETHERNET_KIT_ESP32_PROCPU config ESP_SPIRAM - default y + default y if !MCUBOOT choice SPIRAM_TYPE default SPIRAM_TYPE_ESPPSRAM64 diff --git a/boards/espressif/esp32_ethernet_kit/doc/index.rst b/boards/espressif/esp32_ethernet_kit/doc/index.rst index 2f8ff821aad..4437e479bdf 100644 --- a/boards/espressif/esp32_ethernet_kit/doc/index.rst +++ b/boards/espressif/esp32_ethernet_kit/doc/index.rst @@ -1,8 +1,11 @@ .. _esp32_ethernet_kit: -ESP32-ETHERNET-KIT +ESP32-Ethernet-Kit ################## +Overview +******** + The ESP32-Ethernet-Kit is an Ethernet-to-Wi-Fi development board that enables Ethernet devices to be interconnected over Wi-Fi. At the same time, to provide more flexible power supply options, the ESP32-Ethernet-Kit also supports power @@ -17,16 +20,13 @@ over Ethernet (PoE). ESP32-Ethernet-Kit V1.2 Overview -Overview -******** - -ESP32-Ethernet-Kit is an ESP32-based development board produced by -`Espressif `_. +ESP32-Ethernet-Kit is an ESP32-WROVER-E based development. +For more information, check the datasheet at `ESP32-WROVER-E Datasheet`_. -It consists of two development boards, the Ethernet board A and the PoE -board B. The `Ethernet board (A)`_ contains Bluetooth/Wi-Fi dual-mode +It consists of two development boards, the Ethernet Board A and the PoE +board B. The `Ethernet Board (A)`_ contains Bluetooth/Wi-Fi dual-mode ESP32-WROVER-E module and IP101GRI, a Single Port 10/100 Fast Ethernet -Transceiver (PHY). The `PoE board (B)`_ provides power over Ethernet +Transceiver (PHY). The `PoE Board (B)`_ provides power over Ethernet functionality. The A board can work independently, without the board B installed. @@ -39,7 +39,7 @@ installed. ESP32-Ethernet-Kit V1.2 -For the application loading and monitoring, the Ethernet board (A) also +For the application loading and monitoring, the Ethernet Board (A) also features FTDI FT2232H chip - an advanced multi-interface USB bridge. This chip enables to use JTAG for direct debugging of ESP32 through the USB interface without a separate JTAG debugger. @@ -76,7 +76,7 @@ Ethernet Board (A) :alt: ESP32-Ethernet-Kit V1.2 :figclass: align-center - ESP32-Ethernet-Kit - Ethernet board (A) layout + ESP32-Ethernet-Kit - Ethernet Board (A) layout The table below provides description starting from the picture's top right corner and going clockwise. @@ -104,8 +104,7 @@ corner and going clockwise. ESP32. FT2232H also features USB-to-JTAG interface which is available on channel A of the chip, while USB-to-serial is on channel B. The FT2232H chip enhances user-friendliness in terms of application - development and debugging. See - `ESP32-Ethernet-Kit V1.2 Ethernet board (A) Schematic `_. + development and debugging. See `ESP32-Ethernet-Kit V1.2 Ethernet Board (A) Schematic`_ * - USB Port - USB interface. Power supply for the board as well as the communication interface between a computer and the board. @@ -121,7 +120,7 @@ corner and going clockwise. * - DC/DC Converter - Provided DC 5 V to 3.3 V conversion, output current up to 2 A. * - Board B Connectors - - A pair male and female header pins for mounting the `PoE board (B)`_ + - A pair male and female header pins for mounting the `PoE Board (B)`_ * - IP101GRI (PHY) - The physical layer (PHY) connection to the Ethernet cable is implemented using the @@ -155,27 +154,27 @@ PoE Board (B) ^^^^^^^^^^^^^ This board coverts power delivered over the Ethernet cable (PoE) to provide a -power supply for the Ethernet board (A). The main components of the PoE board +power supply for the Ethernet Board (A). The main components of the PoE Board (B) are shown on the block diagram under `Functionality Overview`_. -The PoE board (B) has the following features: +The PoE Board (B) has the following features: * Support for IEEE 802.3at * Power output: 5 V, 1.4 A To take advantage of the PoE functionality the **RJ45 Port** of the Ethernet board (A) should be connected with an Ethernet cable to a switch that supports -PoE. When the Ethernet board (A) detects 5 V power output from the PoE board +PoE. When the Ethernet Board (A) detects 5 V power output from the PoE Board (B), the USB power will be automatically cut off. .. figure:: img/esp32-ethernet-kit-b-v1.0-layout.jpg :align: center - :alt: ESP32-Ethernet-Kit - PoE board (B) + :alt: ESP32-Ethernet-Kit - PoE Board (B) :figclass: align-center - ESP32-Ethernet-Kit - PoE board (B) layout + ESP32-Ethernet-Kit - PoE Board (B) layout -.. list-table:: Table PoE board (B) +.. list-table:: Table PoE Board (B) :widths: 40 150 :header-rows: 1 @@ -183,11 +182,11 @@ PoE. When the Ethernet board (A) detects 5 V power output from the PoE board - Description * - Board A Connector - Four female (left) and four male (right) header pins for connecting the - PoE board (B) to `Ethernet board (A)`_. The pins on the left accept + PoE Board (B) to `Ethernet Board (A)`_. The pins on the left accept power coming from a PoE switch. The pins on the right deliver 5 V power - supply to the Ethernet board (A). + supply to the Ethernet Board (A). * - External Power Terminals - - Optional power supply (26.6 ~ 54 V) to the PoE board (B). + - Optional power supply (26.6 ~ 54 V) to the PoE Board (B). .. _get-started-esp32-ethernet-kit-v1.2-setup-options: @@ -225,9 +224,7 @@ or generated from internal ESP32 APLL (not recommended). .. note:: For additional information on the RMII clock selection, please refer to - `ESP32-Ethernet-Kit V1.2 Ethernet board (A) Schematic `_, - sheet 2, location D2. - + `ESP32-Ethernet-Kit V1.2 Ethernet Board (A) Schematic`_, sheet 2, location D2. RMII Clock Sourced Externally by PHY ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -267,7 +264,7 @@ for transmission line delay, and then supplied to the PHY. To implement this option, users need to remove or add some RC components on the board. For details please refer to -`ESP32-Ethernet-Kit V1.2 Ethernet board (A) Schematic `_, +`ESP32-Ethernet-Kit V1.2 Ethernet Board (A) Schematic`_, sheet 2, location D2. Please note that if the APLL is already used for other purposes (e.g. I2S peripheral), then you have no choice but use an external RMII clock. @@ -411,7 +408,7 @@ GPIO Allocation Summary module that can be disabled/enabled externally. Similarly like when using RESET_N, the oscillator module should be disabled by default and turned on by ESP32 after power-up. For a reference design please see - `ESP32-Ethernet-Kit V1.2 Ethernet board (A) Schematic `_. + `ESP32-Ethernet-Kit V1.2 Ethernet Board (A) Schematic`_. 2. The ESP32 pins GPIO16 and GPIO17 are not broken out to the ESP32-WROVER-E module and therefore not available for use. If you need @@ -452,7 +449,7 @@ MCUboot bootloader ================== User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. +must be built (and flashed) at least once. There are two options to be used when building an application: @@ -463,9 +460,10 @@ There are two options to be used when building an application: User can select the MCUboot bootloader by adding the following line to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y Sysbuild ======== @@ -477,8 +475,8 @@ To build the sample application using sysbuild use the command: .. zephyr-app-commands:: :tool: west - :app: samples/hello_world - :board: esp32_ethernet_kit + :zephyr-app: samples/hello_world + :board: esp32_ethernet_kit/esp32/procpu :goals: build :west-args: --sysbuild :compact: @@ -513,7 +511,7 @@ Manual build ============ During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. +For that reason, images can be built one at a time using traditional build. The instructions following are relevant for both manual build and sysbuild. The only difference is the structure of the build directory. @@ -532,7 +530,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``esp32_ethernet_kit`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -559,13 +557,13 @@ Debugging As with much custom hardware, the ESP32 modules require patches to OpenOCD that are not upstreamed yet. Espressif maintains their own fork of -the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_. The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the ``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` parameter when building. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -573,7 +571,7 @@ Here is an example for building the :ref:`hello_world` application. :goals: build flash :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -614,13 +612,9 @@ Board Init RESET_N (GPIO5) is automatically set high to enable the Ethernet PHY during board initialization (board_init.c) -Related Documents -***************** +References +********** -* `ESP32-Ethernet-Kit V1.2 Ethernet Board (A) Schematic `_ (PDF) -* `ESP32-Ethernet-Kit PoE Board (B) Schematic `_ (PDF) -* `ESP32-Ethernet-Kit V1.2 Ethernet Board (A) PCB Layout `_ (PDF) -* `ESP32-Ethernet-Kit PoE Board (B) PCB Layout `_ (PDF) -* `ESP32 Datasheet `_ (PDF) -* `ESP32-WROVER-E Datasheet `_ (PDF) -* `OpenOCD ESP32 `_ +.. _`ESP32-Ethernet-Kit V1.2 Ethernet Board (A) Schematic`: https://dl.espressif.com/dl/schematics/SCH_ESP32-Ethernet-Kit_A_V1.2_20200528.pdf +.. _`ESP32-WROVER-E Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-wrover-e_esp32-wrover-ie_datasheet_en.pdf +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_appcpu.dts b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_appcpu.dts index c5e1217b25c..24b4fd8271f 100644 --- a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_appcpu.dts +++ b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_appcpu.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include / { model = "Espressif ESP32-Ethernet-Kit APPCPU"; @@ -18,14 +19,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &ipm0 { status = "okay"; }; @@ -33,42 +26,3 @@ &trng0 { status = "okay"; }; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu.dts b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu.dts index 61f9b1d2634..61838ea748a 100644 --- a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu.dts +++ b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu.dts @@ -7,6 +7,7 @@ #include #include "esp32_ethernet_kit-pinctrl.dtsi" +#include / { model = "Espressif ESP32-Ethernet-Kit PROCPU"; @@ -27,14 +28,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &uart0 { status = "okay"; current-speed = <115200>; @@ -78,45 +71,6 @@ status = "okay"; }; -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; - &mdio { pinctrl-0 = <&mdio_default>; pinctrl-names = "default"; diff --git a/boards/espressif/esp32c3_devkitc/Kconfig.defconfig b/boards/espressif/esp32c3_devkitc/Kconfig.defconfig new file mode 100644 index 00000000000..2e71f23c2d7 --- /dev/null +++ b/boards/espressif/esp32c3_devkitc/Kconfig.defconfig @@ -0,0 +1,11 @@ +# ESP32C3 devkitc board configuration + +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 diff --git a/boards/espressif/esp32c3_devkitc/Kconfig.esp32c3_devkitc b/boards/espressif/esp32c3_devkitc/Kconfig.esp32c3_devkitc new file mode 100644 index 00000000000..7e5744193f8 --- /dev/null +++ b/boards/espressif/esp32c3_devkitc/Kconfig.esp32c3_devkitc @@ -0,0 +1,7 @@ +# ESP32C3 devkitc board configuration + +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32C3_DEVKITC + select SOC_ESP32C3_WROOM_02_N4 diff --git a/boards/espressif/esp32c3_devkitc/Kconfig.sysbuild b/boards/espressif/esp32c3_devkitc/Kconfig.sysbuild new file mode 100644 index 00000000000..8d3acb9e11d --- /dev/null +++ b/boards/espressif/esp32c3_devkitc/Kconfig.sysbuild @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice BOOT_SIGNATURE_TYPE + default BOOT_SIGNATURE_TYPE_NONE +endchoice diff --git a/boards/espressif/esp32c3_devkitc/board.cmake b/boards/espressif/esp32c3_devkitc/board.cmake new file mode 100644 index 00000000000..2f04d1fe886 --- /dev/null +++ b/boards/espressif/esp32c3_devkitc/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/espressif/esp32c3_devkitc/board.yml b/boards/espressif/esp32c3_devkitc/board.yml new file mode 100644 index 00000000000..22db88f664c --- /dev/null +++ b/boards/espressif/esp32c3_devkitc/board.yml @@ -0,0 +1,5 @@ +board: + name: esp32c3_devkitc + vendor: espressif + socs: + - name: esp32c3 diff --git a/boards/espressif/esp32c3_devkitc/doc/index.rst b/boards/espressif/esp32c3_devkitc/doc/index.rst new file mode 100644 index 00000000000..97ce7f181b5 --- /dev/null +++ b/boards/espressif/esp32c3_devkitc/doc/index.rst @@ -0,0 +1,252 @@ +.. _esp32c3_devkitc: + +ESP32-C3-DevKitC +################ + +Overview +******** + +ESP32-C3-DevKitC-02 is an entry-level development board based on ESP32-C3-WROOM-02, +a general-purpose module with 4 MB SPI flash. This board integrates complete Wi-Fi and Bluetooth® Low Energy functions. +For more information, check `ESP32-C3-DevKitC`_. + +Hardware +******** + +ESP32-C3 is a single-core Wi-Fi and Bluetooth 5 (LE) microcontroller SoC, +based on the open-source RISC-V architecture. It strikes the right balance of power, +I/O capabilities and security, thus offering the optimal cost-effective +solution for connected devices. +The availability of Wi-Fi and Bluetooth 5 (LE) connectivity not only makes the device configuration easy, +but it also facilitates a variety of use-cases based on dual connectivity. + +The features include the following: + +- 32-bit core RISC-V microcontroller with a maximum clock speed of 160 MHz +- 400 KB of internal RAM +- 802.11b/g/n/e/i +- A Bluetooth LE subsystem that supports features of Bluetooth 5 and Bluetooth Mesh +- Various peripherals: + + - 12-bit ADC with up to 6 channels + - TWAI compatible with CAN bus 2.0 + - Temperature sensor + - 3x SPI + - 1x I2S + - 1x I2C + - 2x UART + - LED PWM with up to 6 channels + +- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) + +For more information, check the datasheet at `ESP32-C3 Datasheet`_ or the technical reference +manual at `ESP32-C3 Technical Reference Manual`_. + +Supported Features +================== + +Current Zephyr's ESP32-C3-DevKitC board supports the following features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| SPI DMA | on-chip | spi | ++------------+------------+-------------------------------------+ +| TWAI | on-chip | can | ++------------+------------+-------------------------------------+ +| USB-CDC | on-chip | serial | ++------------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++------------+------------+-------------------------------------+ +| Wi-Fi | on-chip | | ++------------+------------+-------------------------------------+ +| Bluetooth | on-chip | | ++------------+------------+-------------------------------------+ + +System requirements +******************* + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: + + Simple boot does not provide any security features nor OTA updates. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be built (and flashed) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/hello_world + :board: esp32c3_devkitc + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be built one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32c3_devkitc + :goals: build + +The usual ``flash`` target will work with the ``esp32c3_devkitc`` board +configuration. Here is an example for the :zephyr:code-sample:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32c3_devkitc + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! esp32c3_devkitc + +Debugging +********* + +As with much custom hardware, the ESP32-C3 modules require patches to +OpenOCD that are not upstreamed yet. Espressif maintains their own fork of +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_. + +The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the +``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` +parameter when building. + +Here is an example for building the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32c3_devkitc + :goals: build flash + :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32c3_devkitc + :goals: debug + +References +********** + +.. _`ESP32-C3-DevKitC`: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32c3/esp32-c3-devkitc-02/index.html +.. _`ESP32-C3 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf +.. _`ESP32-C3 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/espressif/esp32c3_devkitc/esp32c3_devkitc-pinctrl.dtsi b/boards/espressif/esp32c3_devkitc/esp32c3_devkitc-pinctrl.dtsi new file mode 100644 index 00000000000..f6add959a27 --- /dev/null +++ b/boards/espressif/esp32c3_devkitc/esp32c3_devkitc-pinctrl.dtsi @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + + uart0_default: uart0_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + spim2_default: spim2_default { + group1 { + pinmux = , + , + ; + }; + group2 { + pinmux = ; + output-low; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; + + twai_default: twai_default { + group1 { + pinmux = , + ; + }; + }; +}; diff --git a/boards/espressif/esp32c3_devkitc/esp32c3_devkitc.dts b/boards/espressif/esp32c3_devkitc/esp32c3_devkitc.dts new file mode 100644 index 00000000000..c009ccb0d0a --- /dev/null +++ b/boards/espressif/esp32c3_devkitc/esp32c3_devkitc.dts @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "esp32c3_devkitc-pinctrl.dtsi" +#include +#include + +/ { + model = "Espressif ESP32C3-DevkitC"; + compatible = "espressif,esp32c3"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,bt-hci = &esp32_bt_hci; + }; + + aliases { + sw0 = &user_button1; + i2c-0 = &i2c0; + watchdog0 = &wdt0; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button1: button_1 { + label = "User SW1"; + gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&usb_serial { + /* requires resoldering of resistors on the board */ + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&trng0 { + status = "okay"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&timer0 { + status = "disabled"; +}; + +&timer1 { + status = "disabled"; +}; + +&twai { + /* requires external CAN transceiver or jumper on RX and TX pins for loopback testing */ + status = "disabled"; + pinctrl-0 = <&twai_default>; + pinctrl-names = "default"; +}; + +&esp32_bt_hci { + status = "okay"; +}; diff --git a/boards/espressif/esp32c3_devkitc/esp32c3_devkitc.yaml b/boards/espressif/esp32c3_devkitc/esp32c3_devkitc.yaml new file mode 100644 index 00000000000..876ee788553 --- /dev/null +++ b/boards/espressif/esp32c3_devkitc/esp32c3_devkitc.yaml @@ -0,0 +1,22 @@ +identifier: esp32c3_devkitc +name: ESP32-C3 +type: mcu +arch: riscv +toolchain: + - zephyr +supported: + - adc + - gpio + - i2c + - watchdog + - uart + - dma + - pwm + - spi + - counter + - entropy +testing: + ignore_tags: + - net + - bluetooth +vendor: espressif diff --git a/boards/espressif/esp32c3_devkitc/esp32c3_devkitc_defconfig b/boards/espressif/esp32c3_devkitc/esp32c3_devkitc_defconfig new file mode 100644 index 00000000000..ef633ce56a1 --- /dev/null +++ b/boards/espressif/esp32c3_devkitc/esp32c3_devkitc_defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y diff --git a/boards/espressif/esp32c3_devkitc/support/openocd.cfg b/boards/espressif/esp32c3_devkitc/support/openocd.cfg new file mode 100644 index 00000000000..92a792fecb8 --- /dev/null +++ b/boards/espressif/esp32c3_devkitc/support/openocd.cfg @@ -0,0 +1,11 @@ +set ESP_RTOS none + +# ESP32C3 has built-in JTAG interface over USB port in pins GPIO18/GPIO19 (D-/D+). +# Uncomment the line below to enable USB debugging. +# source [find interface/esp_usb_jtag.cfg] + +# Otherwise, use external JTAG programmer as ESP-Prog +source [find interface/ftdi/esp32_devkitj_v1.cfg] + +source [find target/esp32c3.cfg] +adapter speed 5000 diff --git a/boards/espressif/esp32c3_devkitm/doc/index.rst b/boards/espressif/esp32c3_devkitm/doc/index.rst index c2d6551170c..aed67104255 100644 --- a/boards/espressif/esp32c3_devkitm/doc/index.rst +++ b/boards/espressif/esp32c3_devkitm/doc/index.rst @@ -1,17 +1,24 @@ .. _esp32c3_devkitm: -ESP32-C3 -######## +ESP32-C3-DevKitM +################ Overview ******** +ESP32-C3-DevKitM is an entry-level development board based on ESP32-C3-MINI-1, +a module named for its small size. This board integrates complete Wi-Fi and Bluetooth® Low Energy functions. +For more information, check `ESP32-C3-DevKitM`_. + +Hardware +******** + ESP32-C3 is a single-core Wi-Fi and Bluetooth 5 (LE) microcontroller SoC, based on the open-source RISC-V architecture. It strikes the right balance of power, I/O capabilities and security, thus offering the optimal cost-effective solution for connected devices. The availability of Wi-Fi and Bluetooth 5 (LE) connectivity not only makes the device configuration easy, -but it also facilitates a variety of use-cases based on dual connectivity. [1]_ +but it also facilitates a variety of use-cases based on dual connectivity. The features include the following: @@ -32,6 +39,9 @@ The features include the following: - Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) +For more information, check the datasheet at `ESP32-C3 Datasheet`_ or the technical reference +manual at `ESP32-C3 Technical Reference Manual`_. + Supported Features ================== @@ -40,7 +50,6 @@ Current Zephyr's ESP32-C3-Devkitm board supports the following features: +------------+------------+-------------------------------------+ | Interface | Controller | Driver/Component | +============+============+=====================================+ -+------------+------------+-------------------------------------+ | UART | on-chip | serial port | +------------+------------+-------------------------------------+ | GPIO | on-chip | gpio | @@ -106,7 +115,7 @@ MCUboot bootloader ================== User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. +must be built (and flashed) at least once. There are two options to be used when building an application: @@ -117,9 +126,10 @@ There are two options to be used when building an application: User can select the MCUboot bootloader by adding the following line to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y Sysbuild ======== @@ -131,7 +141,7 @@ To build the sample application using sysbuild use the command: .. zephyr-app-commands:: :tool: west - :app: samples/hello_world + :zephyr-app: samples/hello_world :board: esp32c3_devkitm :goals: build :west-args: --sysbuild @@ -167,7 +177,7 @@ Manual build ============ During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. +For that reason, images can be built one at a time using traditional build. The instructions following are relevant for both manual build and sysbuild. The only difference is the structure of the build directory. @@ -185,7 +195,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``esp32c3_devkitm`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -212,13 +222,13 @@ Debugging As with much custom hardware, the ESP32-C3 modules require patches to OpenOCD that are not upstreamed yet. Espressif maintains their own fork of -the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_. The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the ``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` parameter when building. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -226,19 +236,17 @@ Here is an example for building the :ref:`hello_world` application. :goals: build flash :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: esp32c3_devkitm :goals: debug -.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases - References ********** -.. [1] https://www.espressif.com/en/products/socs/esp32-c3 -.. _ESP32C3 Devkitm User Guide: https://docs.espressif.com/projects/esp-idf/en/latest/esp32c3/hw-reference/esp32c3/user-guide-devkitm-1.html -.. _ESP32C3 Technical Reference Manual: https://espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf -.. _ESP32C3 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf +.. _`ESP32-C3-DevKitM`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32c3/hw-reference/esp32c3/user-guide-devkitm-1.html +.. _`ESP32-C3 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf +.. _`ESP32-C3 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/espressif/esp32c3_devkitm/esp32c3_devkitm-pinctrl.dtsi b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm-pinctrl.dtsi index 29969c8da37..1e97415fc76 100644 --- a/boards/espressif/esp32c3_devkitm/esp32c3_devkitm-pinctrl.dtsi +++ b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm-pinctrl.dtsi @@ -43,6 +43,20 @@ }; }; + i2s_default: i2s_default { + group1 { + pinmux = , + , + , + ; + output-enable; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + twai_default: twai_default { group1 { pinmux = , diff --git a/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.dts b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.dts index 945f8e8a598..3cc7c5218de 100644 --- a/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.dts +++ b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.dts @@ -9,9 +9,10 @@ #include #include "esp32c3_devkitm-pinctrl.dtsi" #include +#include / { - model = "Espressif ESP32-DevkitM"; + model = "Espressif ESP32C3-DevkitM"; compatible = "espressif,esp32c3"; chosen { @@ -39,10 +40,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - &uart0 { status = "okay"; current-speed = <115200>; @@ -62,6 +59,12 @@ pinctrl-names = "default"; }; +&i2s { + pinctrl-0 = <&i2s_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + &trng0 { status = "okay"; }; @@ -97,45 +100,6 @@ pinctrl-names = "default"; }; -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; - &esp32_bt_hci { status = "okay"; }; diff --git a/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.yaml b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.yaml index a2c88796ca3..49ba690a563 100644 --- a/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.yaml +++ b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.yaml @@ -8,6 +8,7 @@ supported: - adc - gpio - i2c + - i2s - watchdog - uart - dma diff --git a/boards/espressif/esp32c3_devkitm/support/openocd.cfg b/boards/espressif/esp32c3_devkitm/support/openocd.cfg index 214a4aabf3f..92a792fecb8 100644 --- a/boards/espressif/esp32c3_devkitm/support/openocd.cfg +++ b/boards/espressif/esp32c3_devkitm/support/openocd.cfg @@ -8,4 +8,4 @@ set ESP_RTOS none source [find interface/ftdi/esp32_devkitj_v1.cfg] source [find target/esp32c3.cfg] -adapter_khz 5000 +adapter speed 5000 diff --git a/boards/espressif/esp32c3_rust/Kconfig.defconfig b/boards/espressif/esp32c3_rust/Kconfig.defconfig new file mode 100644 index 00000000000..77418527f48 --- /dev/null +++ b/boards/espressif/esp32c3_rust/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 diff --git a/boards/espressif/esp32c3_rust/Kconfig.esp32c3_rust b/boards/espressif/esp32c3_rust/Kconfig.esp32c3_rust new file mode 100644 index 00000000000..1b5be57a453 --- /dev/null +++ b/boards/espressif/esp32c3_rust/Kconfig.esp32c3_rust @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32C3_RUST + select SOC_ESP32C3_MINI_N4 diff --git a/boards/espressif/esp32c3_rust/Kconfig.sysbuild b/boards/espressif/esp32c3_rust/Kconfig.sysbuild new file mode 100644 index 00000000000..8d3acb9e11d --- /dev/null +++ b/boards/espressif/esp32c3_rust/Kconfig.sysbuild @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice BOOT_SIGNATURE_TYPE + default BOOT_SIGNATURE_TYPE_NONE +endchoice diff --git a/boards/espressif/esp32c3_rust/board.cmake b/boards/espressif/esp32c3_rust/board.cmake new file mode 100644 index 00000000000..91581df2cb0 --- /dev/null +++ b/boards/espressif/esp32c3_rust/board.cmake @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/espressif/esp32c3_rust/board.yml b/boards/espressif/esp32c3_rust/board.yml new file mode 100644 index 00000000000..36dd9b55248 --- /dev/null +++ b/boards/espressif/esp32c3_rust/board.yml @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: esp32c3_rust + vendor: espressif + socs: + - name: esp32c3 diff --git a/boards/espressif/esp32c3_rust/doc/index.rst b/boards/espressif/esp32c3_rust/doc/index.rst new file mode 100644 index 00000000000..7b80d30ee5f --- /dev/null +++ b/boards/espressif/esp32c3_rust/doc/index.rst @@ -0,0 +1,297 @@ +.. _esp32c3_rust: + +ESP32-C3-DevKit-RUST +#################### + +Overview +******** + +ESP32-C3-DevKit-RUST is based on the ESP32-C3, a single-core Wi-Fi and Bluetooth 5 (LE) microcontroller SoC, +based on the open-source RISC-V architecture. This special board also includes the ESP32-C3-MINI-1 module, +a 6DoF IMU, a temperature and humidity sensor, a Li-Ion battery charger, and a Type-C USB. The board is designed +to be easily used in training sessions, demonstrating its capabilities with all the board peripherals. +For more information, check `ESP32-C3-DevKit-RUST`_. + +Hardware +******** + +SoC Features: + +- IEEE 802.11 b/g/n-compliant +- Bluetooth 5, Bluetooth mesh +- 32-bit RISC-V single-core processor, up to 160MHz +- 384 KB ROM +- 400 KB SRAM (16 KB for cache) +- 8 KB SRAM in RTC +- 22 x programmable GPIOs +- 3 x SPI +- 2 x UART +- 1 x I2C +- 1 x I2S +- 2 x 54-bit general-purpose timers +- 3 x watchdog timers +- 1 x 52-bit system timer +- Remote Control Peripheral (RMT) +- LED PWM controller (LEDC) +- Full-speed USB Serial/JTAG controller +- General DMA controller (GDMA) +- 1 x TWAI® +- 2 x 12-bit SAR ADCs, up to 6 channels +- 1 x temperature sensor + +For more information, check the datasheet at `ESP32-C3 Datasheet`_ or the technical reference +manual at `ESP32-C3 Technical Reference Manual`_. + +Supported Features +================== + +Current Zephyr's ESP32-C3-DevKit-RUST board supports the following features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| SPI DMA | on-chip | spi | ++------------+------------+-------------------------------------+ +| TWAI | on-chip | can | ++------------+------------+-------------------------------------+ +| USB-CDC | on-chip | serial | ++------------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++------------+------------+-------------------------------------+ +| Wi-Fi | on-chip | | ++------------+------------+-------------------------------------+ +| Bluetooth | on-chip | | ++------------+------------+-------------------------------------+ + +I2C Peripherals +=============== + +This board includes the following peripherals over the I2C bus: + ++---------------------------+--------------+---------+ +| Peripheral | Part number | Address | ++===========================+==============+=========+ +| IMU | ICM-42670-P | 0x68 | ++---------------------------+--------------+---------+ +| Temperature and Humidity | SHTC3 | 0x70 | ++---------------------------+--------------+---------+ + +I2C Bus Connection +================== + ++---------+--------+ +| Signal | GPIO | ++=========+========+ +| SDA | GPIO10 | ++---------+--------+ +| SCL | GPIO8 | ++---------+--------+ + +I/Os +==== + +The following devices are connected through GPIO: + ++--------------+--------+ +| I/O Devices | GPIO | ++==============+========+ +| WS2812 LED | GPIO2 | ++--------------+--------+ +| LED | GPIO7 | ++--------------+--------+ +| Button/Boot | GPIO9 | ++--------------+--------+ + +Power +===== + +* USB type-C (*no PD compatibility*). +* Li-Ion battery charger. + +System requirements +******************* + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: + + Simple boot does not provide any security features nor OTA updates. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be built (and flashed) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/hello_world + :board: esp32c3_rust + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be built one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32c3_rust + :goals: build + +The usual ``flash`` target will work with the ``esp32c3_rust`` board +configuration. Here is an example for the :zephyr:code-sample:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32c3_rust + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! esp32c3_rust + +Debugging +********* + +As with much custom hardware, the ESP32-C3 modules require patches to +OpenOCD that are not upstreamed yet. Espressif maintains their own fork of +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_. + +The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the +``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` +parameter when building. + +Here is an example for building the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32c3_rust + :goals: build flash + :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32c3_rust + :goals: debug + +References +********** + +.. _`ESP32-C3-DevKit-RUST`: https://github.com/esp-rs/esp-rust-board/tree/v1.2 +.. _`ESP32-C3 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf +.. _`ESP32-C3 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/espressif/esp32c3_rust/esp32c3_rust-pinctrl.dtsi b/boards/espressif/esp32c3_rust/esp32c3_rust-pinctrl.dtsi new file mode 100644 index 00000000000..b1e14c29c91 --- /dev/null +++ b/boards/espressif/esp32c3_rust/esp32c3_rust-pinctrl.dtsi @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + + uart0_default: uart0_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + spim2_default: spim2_default { + group1 { + pinmux = , + , + ; + }; + group2 { + pinmux = ; + output-low; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; +}; diff --git a/boards/espressif/esp32c3_rust/esp32c3_rust.dts b/boards/espressif/esp32c3_rust/esp32c3_rust.dts new file mode 100644 index 00000000000..5d397f3e1c9 --- /dev/null +++ b/boards/espressif/esp32c3_rust/esp32c3_rust.dts @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "esp32c3_rust-pinctrl.dtsi" +#include +#include +#include + +/ { + model = "Espressif ESP32C3-RUST"; + compatible = "espressif,esp32c3_rust"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &usb_serial; + zephyr,shell-uart = &usb_serial; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + aliases { + led0 = &red_led_0; + sw0 = &user_button1; + i2c-0 = &i2c0; + watchdog0 = &wdt0; + led-strip = &led_strip; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button1: button_1 { + label = "User SW1"; + gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + red_led_0: led_0 { + gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; + label = "User LD0"; + }; + }; + +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; + + /* Workaround to support WS2812 driver */ + line-idle-low; + status = "okay"; + + led_strip: ws2812@0 { + compatible = "worldsemi,ws2812-spi"; + + /* SPI */ + reg = <0>; /* ignored, but necessary for SPI bindings */ + spi-max-frequency = <6400000>; + + /* WS2812 */ + chain-length = <1>; /* arbitrary; change at will */ + spi-cpha; + spi-one-frame = <0xf0>; /* 11110000: 625 ns high and 625 ns low */ + spi-zero-frame = <0xc0>; /* 11000000: 312.5 ns high and 937.5 ns low */ + color-mapping = ; + }; +}; + +&usb_serial { + status = "okay"; +}; + + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + + icm42670@68 { + compatible = "invensense,icm42670"; + reg = <0x68>; + status = "okay"; + accel-hz = <800>; + accel-fs = <16>; + gyro-hz = <800>; + gyro-fs = <2000>; + }; + + shtc3@70 { + compatible = "sensirion,shtc3", "sensirion,shtcx"; + reg = <0x70>; + measure-mode = "normal"; + clock-stretching; + }; +}; + +&trng0 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&uart0 { + status = "disabled"; +}; + +&esp32_bt_hci { + status = "okay"; +}; diff --git a/boards/espressif/esp32c3_rust/esp32c3_rust.yaml b/boards/espressif/esp32c3_rust/esp32c3_rust.yaml new file mode 100644 index 00000000000..fedd0178f45 --- /dev/null +++ b/boards/espressif/esp32c3_rust/esp32c3_rust.yaml @@ -0,0 +1,25 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +identifier: esp32c3_rust +name: ESP32-C3-DevKit-RUST-1 +type: mcu +arch: riscv +toolchain: + - zephyr +supported: + - adc + - gpio + - i2c + - watchdog + - uart + - dma + - pwm + - spi + - counter + - entropy +testing: + ignore_tags: + - net + - bluetooth +vendor: espressif diff --git a/boards/espressif/esp32c3_rust/esp32c3_rust_defconfig b/boards/espressif/esp32c3_rust/esp32c3_rust_defconfig new file mode 100644 index 00000000000..a0483fa8a08 --- /dev/null +++ b/boards/espressif/esp32c3_rust/esp32c3_rust_defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y +CONFIG_I2C=y +CONFIG_LED_STRIP=y +CONFIG_SENSOR=y diff --git a/boards/espressif/esp32c3_rust/support/openocd.cfg b/boards/espressif/esp32c3_rust/support/openocd.cfg new file mode 100644 index 00000000000..e846c967fb1 --- /dev/null +++ b/boards/espressif/esp32c3_rust/support/openocd.cfg @@ -0,0 +1,11 @@ +set ESP_RTOS none + +# ESP32C3 has built-in JTAG interface over USB port in pins GPIO18/GPIO19 (D-/D+). +# Uncomment the line below to enable USB debugging. +source [find interface/esp_usb_jtag.cfg] + +# Otherwise, use external JTAG programmer as ESP-Prog +source [find interface/ftdi/esp32_devkitj_v1.cfg] + +source [find target/esp32c3.cfg] +adapter speed 5000 diff --git a/boards/espressif/esp32c6_devkitc/Kconfig.defconfig b/boards/espressif/esp32c6_devkitc/Kconfig.defconfig new file mode 100644 index 00000000000..fccfb36845b --- /dev/null +++ b/boards/espressif/esp32c6_devkitc/Kconfig.defconfig @@ -0,0 +1,11 @@ +# ESP32C6 devkitc board configuration + +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 diff --git a/boards/espressif/esp32c6_devkitc/Kconfig.esp32c6_devkitc b/boards/espressif/esp32c6_devkitc/Kconfig.esp32c6_devkitc new file mode 100644 index 00000000000..4bd1fce4efc --- /dev/null +++ b/boards/espressif/esp32c6_devkitc/Kconfig.esp32c6_devkitc @@ -0,0 +1,7 @@ +# ESP32C6 devkitc board configuration + +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32C6_DEVKITC + select SOC_ESP32_C6_WROOM_1U_N8 diff --git a/boards/espressif/esp32c6_devkitc/Kconfig.sysbuild b/boards/espressif/esp32c6_devkitc/Kconfig.sysbuild new file mode 100644 index 00000000000..3a2d17ac5cf --- /dev/null +++ b/boards/espressif/esp32c6_devkitc/Kconfig.sysbuild @@ -0,0 +1,10 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice BOOT_SIGNATURE_TYPE + default BOOT_SIGNATURE_TYPE_NONE +endchoice diff --git a/boards/espressif/esp32c6_devkitc/board.cmake b/boards/espressif/esp32c6_devkitc/board.cmake new file mode 100644 index 00000000000..2f04d1fe886 --- /dev/null +++ b/boards/espressif/esp32c6_devkitc/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/espressif/esp32c6_devkitc/board.yml b/boards/espressif/esp32c6_devkitc/board.yml new file mode 100644 index 00000000000..ad88f3a9315 --- /dev/null +++ b/boards/espressif/esp32c6_devkitc/board.yml @@ -0,0 +1,5 @@ +board: + name: esp32c6_devkitc + vendor: espressif + socs: + - name: esp32c6 diff --git a/boards/espressif/esp32c6_devkitc/doc/index.rst b/boards/espressif/esp32c6_devkitc/doc/index.rst new file mode 100644 index 00000000000..7b856912a9a --- /dev/null +++ b/boards/espressif/esp32c6_devkitc/doc/index.rst @@ -0,0 +1,287 @@ +.. _esp32c6_devkitc: + +ESP32-C6-DevKitC +################ + +Overview +******** + +ESP32-C6-DevKitC is an entry-level development board based on ESP32-C6-WROOM-1(U), +a general-purpose module with a 8 MB SPI flash. This board integrates complete Wi-Fi, +Bluetooth LE, Zigbee, and Thread functions. For more information, check `ESP32-C6-DevKitC`_. + +Hardware +******** + +ESP32-C6 is Espressif's first Wi-Fi 6 SoC integrating 2.4 GHz Wi-Fi 6, Bluetooth 5.3 (LE) and the +802.15.4 protocol. ESP32-C6 achieves an industry-leading RF performance, with reliable security +features and multiple memory resources for IoT products. +It consists of a high-performance (HP) 32-bit RISC-V processor, which can be clocked up to 160 MHz, +and a low-power (LP) 32-bit RISC-V processor, which can be clocked up to 20 MHz. +It has a 320KB ROM, a 512KB SRAM, and works with external flash. + +ESP32-C6-DevKitC is an entry-level development board based on ESP32-C6-WROOM-1(U), +a general-purpose module with a 8 MB SPI flash. + +Most of the I/O pins are broken out to the pin headers on both sides for easy interfacing. +Developers can either connect peripherals with jumper wires or mount ESP32-C6-DevKitC on +a breadboard. + +ESP32-C6 includes the following features: + +- 32-bit core RISC-V microcontroller with a clock speed of up to 160 MHz +- 400 KB of internal RAM +- WiFi 802.11 ax 2.4GHz +- Fully compatible with IEEE 802.11b/g/n protocol +- Bluetooth LE: Bluetooth 5.3 certified +- Internal co-existence mechanism between Wi-Fi and Bluetooth to share the same antenna +- IEEE 802.15.4 (Zigbee and Thread) + +Digital interfaces: + +- 30x GPIOs (QFN40), or 22x GPIOs (QFN32) +- 2x UART +- 1x Low-power (LP) UART +- 1x General purpose SPI +- 1x I2C +- 1x Low-power (LP) I2C +- 1x I2S +- 1x Pulse counter +- 1x USB Serial/JTAG controller +- 1x TWAI® controller, compatible with ISO 11898-1 (CAN Specification 2.0) +- 1x SDIO 2.0 slave controller +- LED PWM controller, up to 6 channels +- 1x Motor control PWM (MCPWM) +- 1x Remote control peripehral +- 1x Parallel IO interface (PARLIO) +- General DMA controller (GDMA), with 3 transmit channels and 3 receive channels +- Event task matrix (ETM) + +Analog interfaces: + +- 1x 12-bit SAR ADCs, up to 7 channels +- 1x temperature sensor + +Timers: + +- 1x 52-bit system timer +- 1x 54-bit general-purpose timers +- 3x Watchdog timers +- 1x Analog watchdog timer + +Low Power: + +- Four power modes designed for typical scenarios: Active, Modem-sleep, Light-sleep, Deep-sleep + +Security: + +- Secure boot +- Flash encryption +- 4-Kbit OTP, up to 1792 bits for users +- Cryptographic hardware acceleration: (AES-128/256, ECC, HMAC, RSA, SHA, Digital signature, Hash) +- Random number generator (RNG) + +For more information, check the datasheet at `ESP32-C6 Datasheet`_ or the technical reference +manual at `ESP32-C6 Technical Reference Manual`_. + +Supported Features +================== + +Current Zephyr's ESP32-C6-DevKitC board supports the following features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| SPI DMA | on-chip | spi | ++------------+------------+-------------------------------------+ +| GDMA | on-chip | dma | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| USB-CDC | on-chip | serial | ++------------+------------+-------------------------------------+ + +System requirements +******************* + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: + + Simple boot does not provide any security features nor OTA updates. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be built (and flashed) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the EPS32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/hello_world + :board: esp32c6_devkitc + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │   └── zephyr + │   ├── zephyr.elf + │   └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be built one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32c6_devkitc + :goals: build + +The usual ``flash`` target will work with the ``esp32c6_devkitc`` board +configuration. Here is an example for the :zephyr:code-sample:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32c6_devkitc + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! esp32c6_devkitc + +Debugging +********* + +As with much custom hardware, the ESP32-C6 modules require patches to +OpenOCD that are not upstreamed yet. Espressif maintains their own fork of +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_. + +The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the +``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` +parameter when building. + +Here is an example for building the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32c6_devkitc + :goals: build flash + :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32c6_devkitc + :goals: debug + + +References +********** + +.. _`ESP32-C6-DevKitC`: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32c6/esp32-c6-devkitc-1/user_guide.html +.. _`ESP32-C6 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf +.. _`ESP32-C6 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32-c6_technical_reference_manual_en.pdf +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc-pinctrl.dtsi b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc-pinctrl.dtsi new file mode 100644 index 00000000000..a9cda93d22a --- /dev/null +++ b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc-pinctrl.dtsi @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + + uart0_default: uart0_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + spim2_default: spim2_default { + group1 { + pinmux = , + , + ; + }; + group2 { + pinmux = ; + output-low; + }; + }; +}; diff --git a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc.dts b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc.dts new file mode 100644 index 00000000000..a00de99e2b5 --- /dev/null +++ b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc.dts @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "esp32c6_devkitc-pinctrl.dtsi" +#include +#include + +/ { + model = "esp32c6_devkitc"; + compatible = "espressif,esp32c6"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + aliases { + sw0 = &user_button1; + watchdog0 = &wdt0; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button1: button_1 { + label = "User SW1"; + gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&trng0 { + status = "okay"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; diff --git a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc.yaml b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc.yaml new file mode 100644 index 00000000000..e72471a02ed --- /dev/null +++ b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc.yaml @@ -0,0 +1,19 @@ +identifier: esp32c6_devkitc +name: ESP32-C6 +vendor: espressif +type: mcu +arch: riscv +toolchain: + - zephyr +supported: + - gpio + - watchdog + - uart + - dma + - spi + - entropy +testing: + ignore_tags: + - net + - bluetooth + - tracing diff --git a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_defconfig b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_defconfig new file mode 100644 index 00000000000..6539bd42e59 --- /dev/null +++ b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_defconfig @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y diff --git a/boards/espressif/esp32c6_devkitc/support/openocd.cfg b/boards/espressif/esp32c6_devkitc/support/openocd.cfg new file mode 100644 index 00000000000..d86a5517a4c --- /dev/null +++ b/boards/espressif/esp32c6_devkitc/support/openocd.cfg @@ -0,0 +1,4 @@ +# ESP32C6 has built-in JTAG interface over USB port in pins GPIO13/GPIO12 (D-/D+). +set ESP_RTOS none + +source [find board/esp32c6-builtin.cfg] diff --git a/boards/espressif/esp32s2_devkitc/doc/index.rst b/boards/espressif/esp32s2_devkitc/doc/index.rst index bfe8eb3fc7d..9e1bb15fd10 100644 --- a/boards/espressif/esp32s2_devkitc/doc/index.rst +++ b/boards/espressif/esp32s2_devkitc/doc/index.rst @@ -1,13 +1,21 @@ .. _esp32s2_devkitc: -ESP32-S2 -######## +ESP32-S2-DevKitC +################ Overview ******** +ESP32-S2-DevKitC is an entry-level development board. This board integrates complete Wi-Fi functions. +Most of the I/O pins are broken out to the pin headers on both sides for easy interfacing. +Developers can either connect peripherals with jumper wires or mount ESP32-S2-DevKitC on a breadboard. +For more information, check `ESP32-S2-DevKitC`_. + +Hardware +******** + ESP32-S2 is a highly integrated, low-power, single-core Wi-Fi Microcontroller SoC, designed to be secure and -cost-effective, with a high performance and a rich set of IO capabilities. [1]_ +cost-effective, with a high performance and a rich set of IO capabilities. The features include the following: @@ -30,6 +38,9 @@ The features include the following: - DAC - LED PWM with up to 8 channels +For more information, check the datasheet at `ESP32-S2 Datasheet`_ or the technical reference +manual at `ESP32-S2 Technical Reference Manual`_. + Supported Features ================== @@ -38,7 +49,6 @@ Current Zephyr's ESP32-S2-devkitc board supports the following features: +------------+------------+-------------------------------------+ | Interface | Controller | Driver/Component | +============+============+=====================================+ -+------------+------------+-------------------------------------+ | UART | on-chip | serial port | +------------+------------+-------------------------------------+ | GPIO | on-chip | gpio | @@ -102,7 +112,7 @@ MCUboot bootloader ================== User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. +must be built (and flashed) at least once. There are two options to be used when building an application: @@ -113,9 +123,10 @@ There are two options to be used when building an application: User can select the MCUboot bootloader by adding the following line to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y Sysbuild ======== @@ -127,7 +138,7 @@ To build the sample application using sysbuild use the command: .. zephyr-app-commands:: :tool: west - :app: samples/hello_world + :zephyr-app: samples/hello_world :board: esp32s2_devkitc :goals: build :west-args: --sysbuild @@ -163,7 +174,7 @@ Manual build ============ During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. +For that reason, images can be built one at a time using traditional build. The instructions following are relevant for both manual build and sysbuild. The only difference is the structure of the build directory. @@ -181,7 +192,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``esp32s2_devkitc`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -206,8 +217,7 @@ message in the monitor: Debugging ********* -ESP32-S2 support on OpenOCD is available upstream as of version 0.12.0. -Download and install OpenOCD from `OpenOCD`_. +ESP32-S2 support on OpenOCD is available at `OpenOCD ESP32`_. The following table shows the pin mapping between ESP32-S2 board and JTAG interface. @@ -225,28 +235,25 @@ The following table shows the pin mapping between ESP32-S2 board and JTAG interf Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32-S2`_. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: esp32s2_devkitc :goals: build flash -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: esp32s2_devkitc :goals: debug -.. _`OpenOCD`: https://github.com/openocd-org/openocd -.. _`JTAG debugging for ESP32-S2`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/api-guides/jtag-debugging/index.html - - References ********** -.. [1] https://www.espressif.com/en/products/socs/esp32-s2 -.. _ESP32-S2 DevKitC User Guide: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-s2-devkitc-1.html -.. _ESP32S2 Technical Reference Manual: https://espressif.com/sites/default/files/documentation/esp32-s2_technical_reference_manual_en.pdf -.. _ESP32S2 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf +.. _`ESP32-S3-DevKitC`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-saola-1-v1.2.html +.. _`ESP32-S2 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf +.. _`ESP32-S2 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32-s2_technical_reference_manual_en.pdf +.. _`JTAG debugging for ESP32-S2`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/api-guides/jtag-debugging/index.html +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/espressif/esp32s2_devkitc/esp32s2_devkitc.dts b/boards/espressif/esp32s2_devkitc/esp32s2_devkitc.dts index f8282767d22..9038cea4a1e 100644 --- a/boards/espressif/esp32s2_devkitc/esp32s2_devkitc.dts +++ b/boards/espressif/esp32s2_devkitc/esp32s2_devkitc.dts @@ -10,6 +10,7 @@ #include "esp32s2_devkitc-pinctrl.dtsi" #include #include +#include / { model = "Espressif ESP32S2_DevKitC"; @@ -39,10 +40,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - &uart0 { status = "okay"; current-speed = <115200>; @@ -119,47 +116,6 @@ pinctrl-names = "default"; }; - -&flash0 { - status = "okay"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; - &wdt0 { status = "okay"; }; diff --git a/boards/espressif/esp32s2_saola/doc/index.rst b/boards/espressif/esp32s2_saola/doc/index.rst index 1e7c1627fd1..dba54f93cae 100644 --- a/boards/espressif/esp32s2_saola/doc/index.rst +++ b/boards/espressif/esp32s2_saola/doc/index.rst @@ -1,13 +1,21 @@ .. _esp32s2_saola: -ESP32-S2 -######## +ESP32-S2-Saola +############## Overview ******** +ESP32-S2-Saola is a small-sized ESP32-S2 based development board produced by Espressif. +Most of the I/O pins are broken out to the pin headers on both sides for easy interfacing. +Developers can either connect peripherals with jumper wires or mount ESP32-S2-Saola on a breadboard. +For more information, check `ESP32-S3-DevKitC`_. + +Hardware +******** + ESP32-S2 is a highly integrated, low-power, single-core Wi-Fi Microcontroller SoC, designed to be secure and -cost-effective, with a high performance and a rich set of IO capabilities. [1]_ +cost-effective, with a high performance and a rich set of IO capabilities. The features include the following: @@ -30,15 +38,17 @@ The features include the following: - DAC - LED PWM with up to 8 channels +For more information, check the datasheet at `ESP32-S2 Datasheet`_ or the technical reference +manual at `ESP32-S2 Technical Reference Manual`_. + Supported Features ================== -Current Zephyr's ESP32-S2-saola board supports the following features: +Current Zephyr's ESP32-S2-Saola board supports the following features: +------------+------------+-------------------------------------+ | Interface | Controller | Driver/Component | +============+============+=====================================+ -+------------+------------+-------------------------------------+ | UART | on-chip | serial port | +------------+------------+-------------------------------------+ | GPIO | on-chip | gpio | @@ -102,7 +112,7 @@ MCUboot bootloader ================== User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. +must be built (and flashed) at least once. There are two options to be used when building an application: @@ -113,9 +123,10 @@ There are two options to be used when building an application: User can select the MCUboot bootloader by adding the following line to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y Sysbuild ======== @@ -127,7 +138,7 @@ To build the sample application using sysbuild use the command: .. zephyr-app-commands:: :tool: west - :app: samples/hello_world + :zephyr-app: samples/hello_world :board: esp32s2_saola :goals: build :west-args: --sysbuild @@ -163,7 +174,7 @@ Manual build ============ During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. +For that reason, images can be built one at a time using traditional build. The instructions following are relevant for both manual build and sysbuild. The only difference is the structure of the build directory. @@ -181,7 +192,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``esp32s2_saola`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -206,8 +217,7 @@ message in the monitor: Debugging ********* -ESP32-S2 support on OpenOCD is available upstream as of version 0.12.0. -Download and install OpenOCD from `OpenOCD`_. +ESP32-S2 support on OpenOCD is available at `OpenOCD ESP32`_. The following table shows the pin mapping between ESP32-S2 board and JTAG interface. @@ -225,28 +235,25 @@ The following table shows the pin mapping between ESP32-S2 board and JTAG interf Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32-S2`_. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: esp32s2_saola :goals: build flash -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: esp32s2_saola :goals: debug -.. _`OpenOCD`: https://github.com/openocd-org/openocd -.. _`JTAG debugging for ESP32-S2`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/api-guides/jtag-debugging/index.html - - References ********** -.. [1] https://www.espressif.com/en/products/socs/esp32-s2 -.. _ESP32-S2 Saola User Guide: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-saola-1-v1.2.html -.. _ESP32S2 Technical Reference Manual: https://espressif.com/sites/default/files/documentation/esp32-s2_technical_reference_manual_en.pdf -.. _ESP32S2 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf +.. _`ESP32-S3-DevKitC`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-saola-1-v1.2.html +.. _`ESP32-S2 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf +.. _`ESP32-S2 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32-s2_technical_reference_manual_en.pdf +.. _`JTAG debugging for ESP32-S2`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/api-guides/jtag-debugging/index.html +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/espressif/esp32s2_saola/esp32s2_saola.dts b/boards/espressif/esp32s2_saola/esp32s2_saola.dts index f7e73bb8f27..c97108951ab 100644 --- a/boards/espressif/esp32s2_saola/esp32s2_saola.dts +++ b/boards/espressif/esp32s2_saola/esp32s2_saola.dts @@ -10,6 +10,7 @@ #include "esp32s2_saola-pinctrl.dtsi" #include #include +#include / { model = "Espressif ESP32S2-Saola"; @@ -39,10 +40,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - &uart0 { status = "okay"; current-speed = <115200>; @@ -119,47 +116,6 @@ pinctrl-names = "default"; }; - -&flash0 { - status = "okay"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; - &wdt0 { status = "okay"; }; diff --git a/boards/espressif/esp32s3_devkitc/doc/index.rst b/boards/espressif/esp32s3_devkitc/doc/index.rst index 60edc732b56..984a714d0f7 100644 --- a/boards/espressif/esp32s3_devkitc/doc/index.rst +++ b/boards/espressif/esp32s3_devkitc/doc/index.rst @@ -1,14 +1,14 @@ .. _esp32s3_devkitc: -ESP32S3-DevKitC -############### +ESP32-S3-DevKitC +################ Overview ******** The ESP32-S3-DevKitC is an entry-level development board equipped with either ESP32-S3-WROOM-1 or ESP32-S3-WROOM-1U, a module named for its small size. This board integrates complete Wi-Fi -and Bluetooth Low Energy functions. For more information, check `ESP32-S3 DevKitC`_ +and Bluetooth Low Energy functions. For more information, check `ESP32-S3-DevKitC`_. Hardware ******** @@ -18,7 +18,7 @@ and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual- (Xtensa® 32-bit LX7), a low power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband, RF module, and numerous peripherals. -ESP32-S3 DevKitC includes the following features: +ESP32-S3-DevKitC includes the following features: - Dual core 32-bit Xtensa Microprocessor (Tensilica LX7), running up to 240MHz - Additional vector instructions support for AI acceleration @@ -78,7 +78,8 @@ ESP32S3-DevKitC allows 2 different applications to be executed in ESP32-S3 SoC. architecture, each core can be enabled to execute customized tasks in stand-alone mode and/or exchanging data over OpenAMP framework. See :ref:`ipc_samples` folder as code reference. -For more information, check the datasheet at `ESP32-S3 Datasheet`_. +For more information, check the datasheet at `ESP32-S3 Datasheet`_ or the technical reference +manual at `ESP32-S3 Technical Reference Manual`_. Supported Features ================== @@ -88,7 +89,6 @@ Current Zephyr's ESP32-S3-DevKitC board supports the following features: +------------+------------+-------------------------------------+ | Interface | Controller | Driver/Component | +============+============+=====================================+ -+------------+------------+-------------------------------------+ | UART | on-chip | serial port | +------------+------------+-------------------------------------+ | GPIO | on-chip | gpio | @@ -151,7 +151,7 @@ MCUboot bootloader ================== User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. +must be built (and flashed) at least once. There are two options to be used when building an application: @@ -162,9 +162,10 @@ There are two options to be used when building an application: User can select the MCUboot bootloader by adding the following line to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y Sysbuild ======== @@ -176,7 +177,7 @@ To build the sample application using sysbuild use the command: .. zephyr-app-commands:: :tool: west - :app: samples/hello_world + :zephyr-app: samples/hello_world :board: esp32s3_devkitc/esp32s3/procpu :goals: build :west-args: --sysbuild @@ -212,7 +213,7 @@ Manual build ============ During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. +For that reason, images can be built one at a time using traditional build. The instructions following are relevant for both manual build and sysbuild. The only difference is the structure of the build directory. @@ -230,7 +231,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``esp32s3_devkitc`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -255,35 +256,31 @@ message in the monitor: Debugging ********* -ESP32-S3 support on OpenOCD is available upstream as of version 0.12.0. -Download and install OpenOCD from `OpenOCD`_. +ESP32-S3 support on OpenOCD is available at `OpenOCD ESP32`_. ESP32-S3 has a built-in JTAG circuitry and can be debugged without any additional chip. Only an USB cable connected to the D+/D- pins is necessary. -Further documentation can be obtained from the SoC vendor in `JTAG debugging -for ESP32-S3`_. +Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32-S3`_. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: esp32s3_devkitc/esp32s3/procpu :goals: build flash -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: esp32s3_devkitc/esp32s3/procpu :goals: debug -.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ -.. _`OpenOCD`: https://github.com/openocd-org/openocd -.. _`ESP32-S3 DevKitC`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/hw-reference/esp32s3/user-guide-devkitc-1.html - References ********** -.. _ESP32-S3 DevKitC User Guide: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/hw-reference/esp32s3/user-guide-devkitc-1.html -.. _ESP32-S3 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-s3-wroom-1_wroom-1u_datasheet_en.pdf -.. _ESP32 Technical Reference Manual: https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf +.. _`ESP32-S3-DevKitC`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/hw-reference/esp32s3/user-guide-devkitc-1.html +.. _`ESP32-S3 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-s3-wroom-1_wroom-1u_datasheet_en.pdf +.. _`ESP32-S3 Technical Reference Manual`: https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf +.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc-pinctrl.dtsi b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc-pinctrl.dtsi index 5f3fbe8b239..2967cce447d 100644 --- a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc-pinctrl.dtsi +++ b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc-pinctrl.dtsi @@ -40,6 +40,38 @@ }; }; + i2s0_default: i2s0_default { + group1 { + pinmux = , + , + , + , + , + ; + output-enable; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + + i2s1_default: i2s1_default { + group1 { + pinmux = , + , + , + , + , + ; + output-enable; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + spim2_default: spim2_default { group1 { pinmux = , diff --git a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_appcpu.dts b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_appcpu.dts index 5e5a1e2be48..cddc827b4e3 100644 --- a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_appcpu.dts +++ b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_appcpu.dts @@ -6,6 +6,8 @@ /dts-v1/; #include +#include + / { model = "Espressif ESP32S3-DevkitC APPCPU"; compatible = "espressif,esp32s3"; @@ -17,14 +19,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &trng0 { status = "okay"; }; @@ -32,42 +26,3 @@ &ipm0 { status = "okay"; }; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 64kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x00010000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.dts b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.dts index e446d357294..cae78713f81 100644 --- a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.dts +++ b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.dts @@ -9,6 +9,7 @@ #include "esp32s3_devkitc-pinctrl.dtsi" #include #include +#include / { model = "Espressif ESP32S3-DevkitC PROCPU"; @@ -43,14 +44,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &usb_serial { status = "disabled"; }; @@ -94,6 +87,18 @@ pinctrl-names = "default"; }; +&i2s0 { + pinctrl-0 = <&i2s0_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&i2s1 { + pinctrl-0 = <&i2s1_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + &spi2 { #address-cells = <1>; #size-cells = <0>; @@ -139,45 +144,6 @@ status = "okay"; }; -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 64kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x00010000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; - &esp32_bt_hci { status = "okay"; }; diff --git a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.yaml b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.yaml index c4f58917576..2a5e48d464f 100644 --- a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.yaml +++ b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.yaml @@ -8,6 +8,7 @@ supported: - gpio - uart - i2c + - i2s - spi - can - counter diff --git a/boards/espressif/esp32s3_devkitm/doc/index.rst b/boards/espressif/esp32s3_devkitm/doc/index.rst index abef4294733..b1e79766ed9 100644 --- a/boards/espressif/esp32s3_devkitm/doc/index.rst +++ b/boards/espressif/esp32s3_devkitm/doc/index.rst @@ -1,14 +1,14 @@ .. _esp32s3_devkitm: -ESP32S3-DevKitM -############### +ESP32-S3-DevKitM +################ Overview ******** The ESP32-S3-DevKitM is an entry-level development board equipped with either ESP32-S3-MINI-1 or ESP32-S3-MINI-1U, a module named for its small size. This board integrates complete Wi-Fi -and Bluetooth Low Energy functions. For more information, check `ESP32-S3 DevKitM`_ +and Bluetooth Low Energy functions. For more information, check `ESP32-S3-DevKitM User Guide`_. Hardware ******** @@ -18,7 +18,7 @@ and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual- (Xtensa® 32-bit LX7), a low power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband, RF module, and numerous peripherals. -ESP32-S3 DevKitM includes the following features: +ESP32-S3-DevKitM includes the following features: - Dual core 32-bit Xtensa Microprocessor (Tensilica LX7), running up to 240MHz - Additional vector instructions support for AI acceleration @@ -78,7 +78,8 @@ ESP32S3-DevKitM allows 2 different applications to be executed in ESP32-S3 SoC. architecture, each core can be enabled to execute customized tasks in stand-alone mode and/or exchanging data over OpenAMP framework. See :ref:`ipc_samples` folder as code reference. -For more information, check the datasheet at `ESP32-S3 Datasheet`_. +For more information, check the datasheet at `ESP32-S3 Datasheet`_ or the technical reference +manual at `ESP32-S3 Technical Reference Manual`_. Supported Features ================== @@ -88,7 +89,6 @@ Current Zephyr's ESP32-S3-DevKitM board supports the following features: +------------+------------+-------------------------------------+ | Interface | Controller | Driver/Component | +============+============+=====================================+ -+------------+------------+-------------------------------------+ | UART | on-chip | serial port | +------------+------------+-------------------------------------+ | GPIO | on-chip | gpio | @@ -151,7 +151,7 @@ MCUboot bootloader ================== User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. +must be built (and flashed) at least once. There are two options to be used when building an application: @@ -162,9 +162,10 @@ There are two options to be used when building an application: User can select the MCUboot bootloader by adding the following line to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y Sysbuild ======== @@ -176,7 +177,7 @@ To build the sample application using sysbuild use the command: .. zephyr-app-commands:: :tool: west - :app: samples/hello_world + :zephyr-app: samples/hello_world :board: esp32s3_devkitm :goals: build :west-args: --sysbuild @@ -212,7 +213,7 @@ Manual build ============ During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. +For that reason, images can be built one at a time using traditional build. The instructions following are relevant for both manual build and sysbuild. The only difference is the structure of the build directory. @@ -230,7 +231,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``esp32s3_devkitm`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -255,35 +256,31 @@ message in the monitor: Debugging ********* -ESP32-S3 support on OpenOCD is available upstream as of version 0.12.0. -Download and install OpenOCD from `OpenOCD`_. +ESP32-S3 support on OpenOCD is available at `OpenOCD ESP32`_. ESP32-S3 has a built-in JTAG circuitry and can be debugged without any additional chip. Only an USB cable connected to the D+/D- pins is necessary. -Further documentation can be obtained from the SoC vendor in `JTAG debugging -for ESP32-S3`_. +Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32-S3`_. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: esp32s3_devkitm/esp32s3/procpu :goals: build flash -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: esp32s3_devkitm/esp32s3/procpu :goals: debug -.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ -.. _`OpenOCD`: https://github.com/openocd-org/openocd -.. _`ESP32-S3 DevKitM`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/hw-reference/esp32s3/user-guide-devkitm-1.html - References ********** -.. _ESP32-S3 DevKitM User Guide: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/hw-reference/esp32s3/user-guide-devkitm-1.html -.. _ESP32-S3 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-s3-mini-1_mini-1u_datasheet_en.pdf -.. _ESP32 Technical Reference Manual: https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf +.. _`ESP32-S3-DevKitM User Guide`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/hw-reference/esp32s3/user-guide-devkitm-1.html +.. _`ESP32-S3 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-s3-mini-1_mini-1u_datasheet_en.pdf +.. _`ESP32-S3 Technical Reference Manual`: https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases +.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm-pinctrl.dtsi b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm-pinctrl.dtsi index 34fa6e920c6..aa048eb4b7f 100644 --- a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm-pinctrl.dtsi +++ b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm-pinctrl.dtsi @@ -40,6 +40,38 @@ }; }; + i2s0_default: i2s0_default { + group1 { + pinmux = , + , + , + , + , + ; + output-enable; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + + i2s1_default: i2s1_default { + group1 { + pinmux = , + , + , + , + , + ; + output-enable; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + spim2_default: spim2_default { group1 { pinmux = , diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_appcpu.dts b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_appcpu.dts index 3815ebdacf9..0a758507c3f 100644 --- a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_appcpu.dts +++ b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_appcpu.dts @@ -6,6 +6,8 @@ /dts-v1/; #include +#include + / { model = "Espressif ESP32S3-DevkitM APPCPU"; compatible = "espressif,esp32s3"; @@ -17,14 +19,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &trng0 { status = "okay"; }; @@ -32,42 +26,3 @@ &ipm0 { status = "okay"; }; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 64kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x00010000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.dts b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.dts index 6a8e841b95b..d168e97fe60 100644 --- a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.dts +++ b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.dts @@ -9,6 +9,7 @@ #include "esp32s3_devkitm-pinctrl.dtsi" #include #include +#include / { model = "Espressif ESP32S3-DevkitM PROCPU"; @@ -43,18 +44,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - -&usb_serial { - status = "okay"; -}; - &uart0 { status = "okay"; current-speed = <115200>; @@ -94,6 +83,18 @@ pinctrl-names = "default"; }; +&i2s0 { + pinctrl-0 = <&i2s0_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&i2s1 { + pinctrl-0 = <&i2s1_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + &spi2 { #address-cells = <1>; #size-cells = <0>; @@ -143,45 +144,6 @@ status = "disabled"; }; -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 64kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x00010000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; - &esp32_bt_hci { status = "okay"; }; diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.yaml b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.yaml index f9e577353a9..084f6f7539e 100644 --- a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.yaml +++ b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.yaml @@ -8,6 +8,7 @@ supported: - gpio - uart - i2c + - i2s - spi - can - counter @@ -16,6 +17,7 @@ supported: - pwm - dma - input + - video testing: ignore_tags: - net diff --git a/boards/espressif/esp32s3_eye/Kconfig.defconfig b/boards/espressif/esp32s3_eye/Kconfig.defconfig new file mode 100644 index 00000000000..71c7374e095 --- /dev/null +++ b/boards/espressif/esp32s3_eye/Kconfig.defconfig @@ -0,0 +1,25 @@ +# ESP32S3 EYE board configuration + +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ESP32S3_EYE_ESP32S3_PROCPU + +config LV_COLOR_16_SWAP + default y + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +endif # BOARD_ESP32S3_EYE_ESP32S3_PROCPU + +if BOARD_ESP32S3_EYE_ESP32S3_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 256 + +endif # BOARD_ESP32S3_EYE_ESP32S3_APPCPU diff --git a/boards/espressif/esp32s3_eye/Kconfig.esp32s3_eye b/boards/espressif/esp32s3_eye/Kconfig.esp32s3_eye new file mode 100644 index 00000000000..6aa4ac4ef1e --- /dev/null +++ b/boards/espressif/esp32s3_eye/Kconfig.esp32s3_eye @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32S3_EYE + select SOC_ESP32S3_WROOM_N8R8 + select SOC_ESP32S3_PROCPU if BOARD_ESP32S3_EYE_ESP32S3_PROCPU + select SOC_ESP32S3_APPCPU if BOARD_ESP32S3_EYE_ESP32S3_APPCPU diff --git a/boards/espressif/esp32s3_eye/Kconfig.sysbuild b/boards/espressif/esp32s3_eye/Kconfig.sysbuild new file mode 100644 index 00000000000..8d3acb9e11d --- /dev/null +++ b/boards/espressif/esp32s3_eye/Kconfig.sysbuild @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice BOOT_SIGNATURE_TYPE + default BOOT_SIGNATURE_TYPE_NONE +endchoice diff --git a/boards/espressif/esp32s3_eye/board.cmake b/boards/espressif/esp32s3_eye/board.cmake new file mode 100644 index 00000000000..2f04d1fe886 --- /dev/null +++ b/boards/espressif/esp32s3_eye/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/espressif/esp32s3_eye/board.yml b/boards/espressif/esp32s3_eye/board.yml new file mode 100644 index 00000000000..b16a5a1605c --- /dev/null +++ b/boards/espressif/esp32s3_eye/board.yml @@ -0,0 +1,5 @@ +board: + name: esp32s3_eye + vendor: espressif + socs: + - name: esp32s3 diff --git a/boards/espressif/esp32s3_eye/doc/img/ESP32-S3-EYE-isometric.webp b/boards/espressif/esp32s3_eye/doc/img/ESP32-S3-EYE-isometric.webp new file mode 100644 index 00000000000..3fd678c270b Binary files /dev/null and b/boards/espressif/esp32s3_eye/doc/img/ESP32-S3-EYE-isometric.webp differ diff --git a/boards/espressif/esp32s3_eye/doc/img/ESP32-S3-EYE_20210913_V03_SystemBlock.webp b/boards/espressif/esp32s3_eye/doc/img/ESP32-S3-EYE_20210913_V03_SystemBlock.webp new file mode 100644 index 00000000000..7c6ee946402 Binary files /dev/null and b/boards/espressif/esp32s3_eye/doc/img/ESP32-S3-EYE_20210913_V03_SystemBlock.webp differ diff --git a/boards/espressif/esp32s3_eye/doc/img/ESP32-S3-EYE_MB-annotated-photo.webp b/boards/espressif/esp32s3_eye/doc/img/ESP32-S3-EYE_MB-annotated-photo.webp new file mode 100644 index 00000000000..59b10f18436 Binary files /dev/null and b/boards/espressif/esp32s3_eye/doc/img/ESP32-S3-EYE_MB-annotated-photo.webp differ diff --git a/boards/espressif/esp32s3_eye/doc/img/ESP32-S3-EYE_SUB-annotated-photo.webp b/boards/espressif/esp32s3_eye/doc/img/ESP32-S3-EYE_SUB-annotated-photo.webp new file mode 100644 index 00000000000..192244fb687 Binary files /dev/null and b/boards/espressif/esp32s3_eye/doc/img/ESP32-S3-EYE_SUB-annotated-photo.webp differ diff --git a/boards/espressif/esp32s3_eye/doc/index.rst b/boards/espressif/esp32s3_eye/doc/index.rst new file mode 100644 index 00000000000..bbe95728e94 --- /dev/null +++ b/boards/espressif/esp32s3_eye/doc/index.rst @@ -0,0 +1,284 @@ +.. _esp32s3_eye: + +ESP32-S3-EYE +############ + +Overview +******** + +The ESP32-S3-EYE is a small-sized AI development board produced by [Espressif](https://espressif.com). +It is based on the [ESP32-S3](https://www.espressif.com/en/products/socs/esp32-s3) SoC. +It features a 2-Megapixel camera, an LCD display, and a microphone, which are used for image +recognition and audio processing. ESP32-S3-EYE offers plenty of storage, with an 8 MB Octal PSRAM +and a 8 MB flash. + +Hardware +******** + +The ESP32-S3-EYE board consists of two parts: the main board (ESP32-S3-EYE-MB) that integrates the +ESP32-S3-WROOM-1 module, camera, SD card slot, digital microphone, USB port, and function buttons; +and the sub board (ESP32-S3-EYE-SUB) that contains an LCD display. +The main board and sub board are connected through pin headers. + +.. figure:: img/ESP32-S3-EYE-isometric.webp + :align: center + :alt: ESP32-S3-EYE + +Block Diagram +------------- + +The block diagram below presents main components of the ESP32-S3-EYE-MB main board (on the left) +and the ESP32-S3-EYE-SUB sub board (on the right), as well as the interconnections between +components. + +.. figure:: img/ESP32-S3-EYE_20210913_V03_SystemBlock.webp + :align: center + :alt: ESP32-S3-EYE Block Diagram + +Components on the ESP32-S3-EYE-MB Main Board +-------------------------------------------- + +.. figure:: img/ESP32-S3-EYE_MB-annotated-photo.webp + :align: center + :alt: ESP32-S3-EYE_MB + +.. list-table:: Key Components MB + :header-rows: 1 + + * - No. + - Key Component + - Description + * - 1 + - Camera + - The camera OV2640 with 2 million pixels has a 66.5° field of view and a maximum resolution of 1600x1200. You can change the resolution when developing applications. + * - 2 + - Module Power LED + - The LED (green) turns on when USB power is connected to the board. If it is not turned on, it indicates either the USB power is not supplied, or the 5 V to 3.3 V LDO is broken. Software can configure GPIO3 to set different LED statuses (turned on/off, flashing) for different statuses of the board. Note that GPIO3 must be set up in open-drain mode. Pulling GPIO3 up may burn the LED. + * - 3 + - Pin Headers + - Connect the female headers on the sub board. + * - 4 + - 5 V to 3.3 V LDO + - Power regulator that converts a 5 V supply into a 3.3 V output for the module. + * - 5 + - Digital Microphone + - The digital I2S MEMS microphone features 61 dB SNR and –26 dBFS sensitivity, working at 3.3 V. + * - 6 + - FPC Connector + - Connects the main board and the sub board. + * - 7 + - Function Button + - There are six function buttons on the board. Users can configure any functions as needed except for the RST button. + * - 8 + - ESP32-S3-WROOM-1 + - The ESP32-S3-WROOM-1 module embeds the ESP32-S3R8 chip variant that provides Wi-Fi and Bluetooth 5 (LE) connectivity, as well as dedicated vector instructions for accelerating neural network computing and signal processing. On top of the integrated 8 MB Octal SPI PSRAM offered by the SoC, the module also comes with 8 MB flash, allowing for fast data access. ESP32-S3-WROOM-1U module is also supported. + * - 9 + - MicroSD Card Slot + - Used for inserting a MicroSD card to expand memory capacity. + * - 10 + - 3.3 V to 1.5 V LDO + - Power regulator that converts a 3.3 V supply into a 1.5 V output for the camera. + * - 11 + - 3.3 V to 2.8 V LDO + - Power regulator that converts a 3.3 V supply into a 2.8 V output for the camera. + * - 12 + - USB Port + - A Micro-USB port used for 5 V power supply to the board, as well as for communication with the chip via GPIO19 and GPIO20. + * - 13 + - Battery Soldering Points + - Used for soldering a battery socket to connect an external Li-ion battery that can serve as an alternative power supply to the board. If you use an external battery, make sure it has built-in protection circuit and fuse. The recommended specifications of the battery: capacity > 1000 mAh, output voltage 3.7 V, input voltage 4.2 V – 5 V. + * - 14 + - Battery Charger Chip + - 1 A linear Li-ion battery charger (ME4054BM5G-N) in ThinSOT package. The power source for charging is the **USB Port**. + * - 15 + - Battery Red LED + - When the USB power is connected to the board and a battery is not connected, the red LED blinks. If a battery is connected and being charged, the red LED turns on. When the battery is fully charged, it turns off. + * - 16 + - Accelerometer + - Three-axis accelerometer (QMA7981) for screen rotation, etc. + +Components on the ESP32-S3-EYE-SUB Sub Board +-------------------------------------------- + +.. figure:: img/ESP32-S3-EYE_SUB-annotated-photo.webp + :align: center + :alt: ESP32-S3-EYE_SUB + +.. list-table:: Key Components SUB + :header-rows: 1 + + * - Key Component + - Description + * - LCD Display + - 1.3” LCD display, connected to ESP32-S3 over the SPI bus. + * - Strapping Pins + - Four strapping pins led out from the main board. They can be used as testing points. + * - Female Headers + - Used for mounting onto the pin headers on the main board. + * - LCD FPC Connector + - Connects the sub board and the LCD display. + * - LCD_RST + - LCD_RST testing point. You can use it to reset the LCD display with control signals. + +Prerequisites +************* + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +Simple boot +----------- + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: + + Simple boot does not provide any security features nor OTA updates. + +MCUboot bootloader +------------------ + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be built (and flashed) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y + +Sysbuild +-------- + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/hello_world + :board: esp32s3_eye/esp32s3/procpu + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +------------ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be built one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s3_eye/esp32s3/procpu + :goals: build + +The usual ``flash`` target will work with the ``esp32s3_eye/esp32s3/procpu`` board +configuration. Here is an example for the :zephyr:code-sample:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s3_eye/esp32s3/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! esp32s3_eye/esp32s3/procpu + +Debugging +********* + +ESP32-S3 modules require patches to OpenOCD that are not upstreamed yet. +Espressif maintains their own fork of the project. The custom OpenOCD can be obtained at +`OpenOCD ESP32`_ + +The Zephyr SDK uses a bundled version of OpenOCD by default. +You can overwrite that behavior by adding the +``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` +parameter when building. + +Here is an example for building the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s3_eye/esp32s3/procpu + :goals: build flash + :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s3_eye/esp32s3/procpu + :goals: debug + +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/espressif/esp32s3_eye/esp32s3_eye-pinctrl.dtsi b/boards/espressif/esp32s3_eye/esp32s3_eye-pinctrl.dtsi new file mode 100644 index 00000000000..aba99bbe549 --- /dev/null +++ b/boards/espressif/esp32s3_eye/esp32s3_eye-pinctrl.dtsi @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + i2c1_default: i2c1_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; + + spim3_default: spim3_default { + group1 { + pinmux = , + ; + }; + group2 { + pinmux = ; + output-low; + }; + }; + + lcd_cam_default: lcd_cam_default{ + group1 { + pinmux = ; + output-enable; + }; + group2 { + pinmux = , + , + , + , + , + , + , + , + , + , + ; + input-enable; + bias-disable; + }; + + }; +}; diff --git a/boards/espressif/esp32s3_eye/esp32s3_eye_appcpu.dts b/boards/espressif/esp32s3_eye/esp32s3_eye_appcpu.dts new file mode 100644 index 00000000000..4b5d6240185 --- /dev/null +++ b/boards/espressif/esp32s3_eye/esp32s3_eye_appcpu.dts @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +/ { + model = "Espressif ESP32S3-EYE APPCPU"; + compatible = "espressif,esp32s3"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&trng0 { + status = "okay"; +}; + +&ipm0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 64kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/espressif/esp32s3_eye/esp32s3_eye_appcpu.yaml b/boards/espressif/esp32s3_eye/esp32s3_eye_appcpu.yaml new file mode 100644 index 00000000000..787fcd46a10 --- /dev/null +++ b/boards/espressif/esp32s3_eye/esp32s3_eye_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: esp32s3_eye/esp32s3/appcpu +name: ESP32-S3 EYE APPCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: espressif diff --git a/boards/espressif/esp32s3_eye/esp32s3_eye_appcpu_defconfig b/boards/espressif/esp32s3_eye/esp32s3_eye_appcpu_defconfig new file mode 100644 index 00000000000..9abf2ff0430 --- /dev/null +++ b/boards/espressif/esp32s3_eye/esp32s3_eye_appcpu_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y diff --git a/boards/espressif/esp32s3_eye/esp32s3_eye_procpu.dts b/boards/espressif/esp32s3_eye/esp32s3_eye_procpu.dts new file mode 100644 index 00000000000..fab93cbcf6d --- /dev/null +++ b/boards/espressif/esp32s3_eye/esp32s3_eye_procpu.dts @@ -0,0 +1,244 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include "espressif/esp32s3/esp32s3_wroom_n8r8.dtsi" +#include "esp32s3_eye-pinctrl.dtsi" +#include +#include +#include + +/ { + model = "Espressif ESP32S3-EYE PROCPU"; + compatible = "espressif,esp32s3"; + + aliases { + i2c-0 = &i2c0; + watchdog0 = &wdt0; + sw0 = &button0; + led0 = &green_led; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &usb_serial; + zephyr,shell-uart = &usb_serial; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,bt-hci = &esp32_bt_hci; + zephyr,display = &st7789v; + zephyr,camera = &lcd_cam; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "BOOT Button"; + zephyr,code = ; + }; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&adc0 0>; + keyup-threshold-mv = <3300>; + sample-period-ms = <50>; + + menu_key { + press-thresholds-mv = <2800>; + zephyr,code = ; + }; + + play_key { + press-thresholds-mv = <1920>; + zephyr,code = ; + }; + + up_key { + press-thresholds-mv = <350>; + zephyr,code = ; + }; + + down_key { + press-thresholds-mv = <800>; + zephyr,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + green_led: led0 { + gpios = <&gpio0 3 GPIO_OPEN_DRAIN>; + label = "Power LED"; + }; + }; + + mipi_dbi { + compatible = "zephyr,mipi-dbi-spi"; + dc-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + spi-dev = <&spi3>; + write-only; + #address-cells = <1>; + #size-cells = <0>; + + st7789v: st7789v@0 { + compatible = "sitronix,st7789v"; + mipi-max-frequency = <20000000>; + reg = <0>; + width = <240>; + height = <240>; + x-offset = <0>; + y-offset = <0>; + vcom = <0x19>; + gctrl = <0x35>; + vrhs = <0x12>; + vdvs = <0x20>; + mdac = <0x00>; + gamma = <0x01>; + colmod = <0x55>; + lcm = <0x2c>; + porch-param = [0c 0c 00 33 33]; + cmd2en-param = [5a 69 02 01]; + pwctrl1-param = [a4 a1]; + pvgam-param = [D0 04 0D 11 13 2B 3F 54 4C 18 0D 0B 1F 23]; + nvgam-param = [D0 04 0C 11 13 2C 3F 44 51 2F 1F 1F 20 23]; + ram-param = [00 F0]; + rgb-param = [CD 08 14]; + mipi-mode = ; + }; + }; +}; + +&dma { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; + ov2640: ov2640@30 { + compatible = "ovti,ov2640"; + reg = <0x30>; + status = "okay"; + clock-rate-control = <0x80>; + port { + ov2640_ep_out: endpoint { + remote-endpoint = <&dvp_ep_in>; + }; + }; + }; +}; + +&lcd_cam { + status = "okay"; + cam-clk = < 10000000 >; + pinctrl-0 = <&lcd_cam_default>; + pinctrl-names = "default"; + source = <&ov2640>; + dmas = <&dma 2>; + dma-names = "rx"; + port { + dvp_ep_in: endpoint { + remote-endpoint = <&ov2640_ep_out>; + }; + }; +}; + +&usb_serial { + status = "okay"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&adc0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + zephyr,gain = "ADC_GAIN_1_4"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; +}; + +&wdt0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 64kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; + +&esp32_bt_hci { + status = "okay"; +}; diff --git a/boards/espressif/esp32s3_eye/esp32s3_eye_procpu.yaml b/boards/espressif/esp32s3_eye/esp32s3_eye_procpu.yaml new file mode 100644 index 00000000000..adddce2e59e --- /dev/null +++ b/boards/espressif/esp32s3_eye/esp32s3_eye_procpu.yaml @@ -0,0 +1,23 @@ +identifier: esp32s3_eye/esp32s3/procpu +name: ESP32-S3 EYE PROCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - uart + - i2c + - spi + - can + - counter + - watchdog + - entropy + - pwm + - dma + - input +testing: + ignore_tags: + - net + - bluetooth +vendor: espressif diff --git a/boards/espressif/esp32s3_eye/esp32s3_eye_procpu_defconfig b/boards/espressif/esp32s3_eye/esp32s3_eye_procpu_defconfig new file mode 100644 index 00000000000..6c24dead95b --- /dev/null +++ b/boards/espressif/esp32s3_eye/esp32s3_eye_procpu_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=4096 +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y +CONFIG_CLOCK_CONTROL=y +CONFIG_ADC=y +CONFIG_ESP_SPIRAM=y +CONFIG_SPIRAM_MODE_OCT=y diff --git a/boards/espressif/esp32s3_eye/support/openocd.cfg b/boards/espressif/esp32s3_eye/support/openocd.cfg new file mode 100644 index 00000000000..2f740b4a36a --- /dev/null +++ b/boards/espressif/esp32s3_eye/support/openocd.cfg @@ -0,0 +1,7 @@ +set ESP_RTOS none +set ESP32_ONLYCPU 1 + +# Source the JTAG interface configuration file +source [find interface/esp_usb_jtag.cfg] +# Source the ESP32-S3 configuration file +source [find target/esp32s3.cfg] diff --git a/boards/espressif/esp8684_devkitm/Kconfig.defconfig b/boards/espressif/esp8684_devkitm/Kconfig.defconfig new file mode 100644 index 00000000000..60266dd5fd8 --- /dev/null +++ b/boards/espressif/esp8684_devkitm/Kconfig.defconfig @@ -0,0 +1,11 @@ +# ESP8684 devkitm board configuration + +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 diff --git a/boards/espressif/esp8684_devkitm/Kconfig.esp8684_devkitm b/boards/espressif/esp8684_devkitm/Kconfig.esp8684_devkitm new file mode 100644 index 00000000000..5dddf3307a2 --- /dev/null +++ b/boards/espressif/esp8684_devkitm/Kconfig.esp8684_devkitm @@ -0,0 +1,7 @@ +# ESP8684 devkitm board configuration + +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP8684_DEVKITM + select SOC_ESP8684_MINI_H4 diff --git a/boards/espressif/esp8684_devkitm/Kconfig.sysbuild b/boards/espressif/esp8684_devkitm/Kconfig.sysbuild new file mode 100644 index 00000000000..8d3acb9e11d --- /dev/null +++ b/boards/espressif/esp8684_devkitm/Kconfig.sysbuild @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice BOOT_SIGNATURE_TYPE + default BOOT_SIGNATURE_TYPE_NONE +endchoice diff --git a/boards/espressif/esp8684_devkitm/board.cmake b/boards/espressif/esp8684_devkitm/board.cmake new file mode 100644 index 00000000000..2f04d1fe886 --- /dev/null +++ b/boards/espressif/esp8684_devkitm/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/espressif/esp8684_devkitm/board.yml b/boards/espressif/esp8684_devkitm/board.yml new file mode 100644 index 00000000000..5173f52326d --- /dev/null +++ b/boards/espressif/esp8684_devkitm/board.yml @@ -0,0 +1,5 @@ +board: + name: esp8684_devkitm + vendor: espressif + socs: + - name: esp32c2 diff --git a/boards/espressif/esp8684_devkitm/doc/index.rst b/boards/espressif/esp8684_devkitm/doc/index.rst new file mode 100644 index 00000000000..fe2ba1e60bf --- /dev/null +++ b/boards/espressif/esp8684_devkitm/doc/index.rst @@ -0,0 +1,248 @@ +.. _esp8684_devkitm: + +ESP8684-DevKitM +############### + +Overview +******** + +The ESP8684-DevKitM is an entry-level development board based on ESP8684-MINI-1, a general-purpose +module with 1 MB/2 MB/4 MB SPI flash. This board integrates complete Wi-Fi and Bluetooth LE functions. +For more information, check `ESP8684-DevKitM User Guide`_ + +Hardware +******** + +ESP32-C2 (ESP8684 core) is a low-cost, Wi-Fi 4 & Bluetooth 5 (LE) chip. Its unique design +makes the chip smaller and yet more powerful than ESP8266. ESP32-C2 is built around a RISC-V +32-bit, single-core processor, with 272 KB of SRAM (16 KB dedicated to cache) and 576 KB of ROM. +ESP32-C2 has been designed to target simple, high-volume, and low-data-rate IoT applications, +such as smart plugs and smart light bulbs. ESP32-C2 offers easy and robust wireless connectivity, +which makes it the go-to solution for developing simple, user-friendly and reliable +smart-home devices. For more information, check `ESP8684 Datasheet`_. + +Features include the following: + +- 32-bit core RISC-V microcontroller with a maximum clock speed of 120 MHz +- 2 MB or 4 MB in chip (ESP8684) or in package (ESP32-C2) flash +- 272 KB of internal RAM +- 802.11b/g/n +- A Bluetooth LE subsystem that supports features of Bluetooth 5 and Bluetooth Mesh +- Various peripherals: + + - 14 programmable GPIOs + - 3 SPI + - 2 UART + - 1 I2C Master + - LED PWM controller, with up to 6 channels + - General DMA controller (GDMA) + - 1 12-bit SAR ADC, up to 5 channels + - 1 temperature sensor + - 1 54-bit general-purpose timer + - 2 watchdog timers + - 1 52-bit system timer + +- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) + +For detailed information check `ESP8684 Technical Reference Manual`_. + +Supported Features +================== + +Current Zephyr's ESP8684-DevKitM board supports the following features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ +| Wi-Fi | on-chip | | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| SPI DMA | on-chip | spi | ++------------+------------+-------------------------------------+ + +For a getting started user guide, please check `ESP8684-DevKitM User Guide`_. + +System requirements +******************* + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: + + Simple boot does not provide any security features nor OTA updates. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be built (and flashed) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/hello_world + :board: esp8684_devkitm + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be built one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp8684_devkitm + :goals: build + +The usual ``flash`` target will work with the ``esp8684_devkitm`` board +configuration. Here is an example for the :zephyr:code-sample:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp8684_devkitm + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! esp8684_devkitm + +Debugging +********* + +As with much custom hardware, the ESP8684 modules require patches to +OpenOCD that are not upstreamed yet. Espressif maintains their own fork of +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_. + +The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the +``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` +parameter when building. + +Here is an example for building the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp8684_devkitm + :goals: build flash + :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp8684_devkitm + :goals: debug + +References +********** + +.. _`ESP8684-DevKitM User Guide`: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp8684/esp8684-devkitm-1/user_guide.html +.. _`ESP8684 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp8684_datasheet_en.pdf +.. _`ESP8684 Technical Reference Manual`: https://www.espressif.com/sites/default/files/documentation/esp8684_technical_reference_manual_en.pdf +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/espressif/esp8684_devkitm/esp8684_devkitm-pinctrl.dtsi b/boards/espressif/esp8684_devkitm/esp8684_devkitm-pinctrl.dtsi new file mode 100644 index 00000000000..dda91adbd70 --- /dev/null +++ b/boards/espressif/esp8684_devkitm/esp8684_devkitm-pinctrl.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + + uart0_default: uart0_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; +}; diff --git a/boards/espressif/esp8684_devkitm/esp8684_devkitm.dts b/boards/espressif/esp8684_devkitm/esp8684_devkitm.dts new file mode 100644 index 00000000000..0b52a3d2b86 --- /dev/null +++ b/boards/espressif/esp8684_devkitm/esp8684_devkitm.dts @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "esp8684_devkitm-pinctrl.dtsi" +#include +#include + +/ { + model = "Espressif ESP8684-DevkitM"; + compatible = "espressif,esp32c2"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + aliases { + sw0 = &user_button1; + watchdog0 = &wdt0; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button1: button_1 { + label = "User SW1"; + gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <74880>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&trng0 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&timer0 { + status = "disabled"; +}; diff --git a/boards/espressif/esp8684_devkitm/esp8684_devkitm.yaml b/boards/espressif/esp8684_devkitm/esp8684_devkitm.yaml new file mode 100644 index 00000000000..e689bbfe6c1 --- /dev/null +++ b/boards/espressif/esp8684_devkitm/esp8684_devkitm.yaml @@ -0,0 +1,19 @@ +identifier: esp8684_devkitm +name: ESP8684 +type: mcu +arch: riscv +toolchain: + - zephyr +supported: + - gpio + - watchdog + - uart + - counter + - entropy + - pwm + - spi +testing: + ignore_tags: + - net + - bluetooth +vendor: espressif diff --git a/boards/espressif/esp8684_devkitm/esp8684_devkitm_defconfig b/boards/espressif/esp8684_devkitm/esp8684_devkitm_defconfig new file mode 100644 index 00000000000..ef633ce56a1 --- /dev/null +++ b/boards/espressif/esp8684_devkitm/esp8684_devkitm_defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y diff --git a/boards/espressif/esp8684_devkitm/support/openocd.cfg b/boards/espressif/esp8684_devkitm/support/openocd.cfg new file mode 100644 index 00000000000..93209701b69 --- /dev/null +++ b/boards/espressif/esp8684_devkitm/support/openocd.cfg @@ -0,0 +1,5 @@ +set ESP_RTOS none + +# Use external JTAG interface, such as ESP-Prog +source [find interface/ftdi/esp32_devkitj_v1.cfg] +source [find target/esp32c2.cfg] diff --git a/boards/espressif/esp_wrover_kit/doc/index.rst b/boards/espressif/esp_wrover_kit/doc/index.rst index 521307376a0..0bef9a9ce4d 100644 --- a/boards/espressif/esp_wrover_kit/doc/index.rst +++ b/boards/espressif/esp_wrover_kit/doc/index.rst @@ -26,6 +26,8 @@ Most of the ESP32 I/O pins are broken out to the board's pin headers for easy ac ESP32's GPIO16 and GPIO17 are used as chip select and clock signals for PSRAM. By default, the two GPIOs are not broken out to the board's pin headers in order to ensure reliable performance. +For more information, check `ESP32-WROVER-E Datasheet`_ and `ESP32 Datasheet`_. + Functionality Overview ********************** @@ -56,7 +58,7 @@ of the ESP-WROVER-KIT board. ESP-WROVER-KIT board layout - back The table below provides description in the following manner: -- Starting from the first picture’s top right corner and going clockwise +- Starting from the first picture's top right corner and going clockwise - Then moving on to the second picture +------------------+-------------------------------------------------------------------------+ @@ -253,7 +255,7 @@ Legend: - LED - RGB LED - MicroSD - MicroSD Card / J4 - LCD - LCD / U5 - - PSRAM - ESP32-WROVER-E’s PSRAM + - PSRAM - ESP32-WROVER-E's PSRAM 32.768 kHz Oscillator ********************* @@ -270,8 +272,8 @@ Legend: Since GPIO32 and GPIO33 are connected to the oscillator by default, they are not connected to the JP1 I/O connector to maintain signal integrity. This allocation may be changed from the - oscillator to JP1 by desoldering the zero-ohm resistors from positions R11 / R23 and re- - soldering them to positions R12 / R24. + oscillator to JP1 by desoldering the zero-ohm resistors from positions R11 / R23 and re-soldering + them to positions R12 / R24. SPI Flash / JP2 *************** @@ -293,10 +295,10 @@ SPI Flash / JP2 +---+--------------+ .. important:: - The module’s flash bus is connected to the jumper block JP2 through zero-ohm resistors R140 ~ + The module's flash bus is connected to the jumper block JP2 through zero-ohm resistors R140 ~ R145. If the flash memory needs to operate at the frequency of 80 MHz, for reasons such as improving the integrity of bus signals, you can desolder these resistors to disconnect the - module’s flash bus from the pin header JP2. + module's flash bus from the pin header JP2. JTAG / JP2 ********** @@ -447,7 +449,6 @@ Current Zephyr's ESP32-Wrover-Kit board supports the following features: +------------+------------+-------------------------------------+ | Interface | Controller | Driver/Component | +============+============+=====================================+ -+------------+------------+-------------------------------------+ | UART | on-chip | serial port | +------------+------------+-------------------------------------+ | GPIO | on-chip | gpio | @@ -517,7 +518,7 @@ MCUboot bootloader ================== User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. +must be built (and flashed) at least once. There are two options to be used when building an application: @@ -528,9 +529,10 @@ There are two options to be used when building an application: User can select the MCUboot bootloader by adding the following line to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y Sysbuild ======== @@ -542,7 +544,7 @@ To build the sample application using sysbuild use the command: .. zephyr-app-commands:: :tool: west - :app: samples/hello_world + :zephyr-app: samples/hello_world :board: esp_wrover_kit :goals: build :west-args: --sysbuild @@ -578,7 +580,7 @@ Manual build ============ During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. +For that reason, images can be built one at a time using traditional build. The instructions following are relevant for both manual build and sysbuild. The only difference is the structure of the build directory. @@ -596,7 +598,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``esp_wrover_kit`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -621,8 +623,7 @@ message in the monitor: Debugging ********* -ESP32 support on OpenOCD is available upstream as of version 0.12.0. -Download and install OpenOCD from `OpenOCD`_. +ESP32 support on OpenOCD is available at `OpenOCD ESP32`_. On the ESP-WROVER-KIT board, the JTAG pins are connected internally to a USB serial port on the same device as the console. These boards @@ -633,7 +634,7 @@ headers are on the right side of the board as viewed from the power switch, next to similar headers for SPI and UART. See `ESP-WROVER-32 V3 Getting Started Guide`_ for details. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -641,21 +642,17 @@ Here is an example for building the :ref:`hello_world` application. :goals: build flash :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: esp_wrover_kit/esp32/procpu :goals: debug -.. _`OpenOCD`: https://github.com/openocd-org/openocd -.. _`ESP-WROVER-32 V3 Getting Started Guide`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/hw-reference/esp32/get-started-wrover-kit.html - -Related Documents -***************** +References +********** -.. _ESP-WROVER-KIT V4.1 schematics: https://dl.espressif.com/dl/schematics/ESP-WROVER-KIT_V4_1.pdf (PDF) -.. _ESP-WROVER-KIT V4.1 layout: https://dl.espressif.com/dl/schematics/ESP-WROVER-KIT_V4.1.dxf (DXF) -.. _ESP32 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf (PDF) -.. _ESP32-WROVER-E Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-wrover-e_esp32-wrover-ie_datasheet_en.pdf (PDF) -.. _ESP32 Hardware Reference: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/hw-reference/index.html +.. _`ESP32 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf (PDF) +.. _`ESP32-WROVER-E Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-wrover-e_esp32-wrover-ie_datasheet_en.pdf (PDF) +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases +.. _`ESP-WROVER-32 V3 Getting Started Guide`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/hw-reference/esp32/get-started-wrover-kit.html diff --git a/boards/espressif/esp_wrover_kit/esp_wrover_kit_appcpu.dts b/boards/espressif/esp_wrover_kit/esp_wrover_kit_appcpu.dts index f0a046705ee..154857f15e9 100644 --- a/boards/espressif/esp_wrover_kit/esp_wrover_kit_appcpu.dts +++ b/boards/espressif/esp_wrover_kit/esp_wrover_kit_appcpu.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include / { model = "Espressif ESP32-Wrover-Kit APPCPU"; @@ -18,14 +19,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &ipm0 { status = "okay"; }; @@ -33,42 +26,3 @@ &trng0 { status = "okay"; }; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/espressif/esp_wrover_kit/esp_wrover_kit_procpu.dts b/boards/espressif/esp_wrover_kit/esp_wrover_kit_procpu.dts index df387a293bf..a19aa040a46 100644 --- a/boards/espressif/esp_wrover_kit/esp_wrover_kit_procpu.dts +++ b/boards/espressif/esp_wrover_kit/esp_wrover_kit_procpu.dts @@ -7,6 +7,7 @@ #include #include "esp_wrover_kit-pinctrl.dtsi" +#include / { model = "Espressif ESP32-Wrover-Kit PROCPU"; @@ -95,14 +96,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &uart0 { status = "okay"; current-speed = <115200>; @@ -214,45 +207,6 @@ }; }; -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; - &esp32_bt_hci { status = "okay"; }; diff --git a/boards/ezurio/bl5340_dvk/Kconfig b/boards/ezurio/bl5340_dvk/Kconfig new file mode 100644 index 00000000000..e84a37972a0 --- /dev/null +++ b/boards/ezurio/bl5340_dvk/Kconfig @@ -0,0 +1,30 @@ +# BL5340-DVK board configuration + +# Copyright (c) 2019-2021 Nordic Semiconductor ASA +# Copyright (c) 2021-2023 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BL5340_DVK_NRF5340_CPUAPP || BOARD_BL5340_DVK_NRF5340_CPUAPP_NS + +config DOMAIN_CPUNET_BOARD + string + default "bl5340_dvk/nrf5340/cpunet" + help + The board which will be used for CPUNET domain when creating a multi + image application where one or more images should be located on + another board. For example hci_ipc on the bl5340_dvk_cpunet for + Bluetooth applications. + +endif # BOARD_BL5340_DVK_NRF5340_CPUAPP || BOARD_BL5340_DVK_NRF5340_CPUAPP_NS + +if BOARD_BL5340_DVK_NRF5340_CPUNET + +config DOMAIN_CPUAPP_BOARD + string + default "bl5340_dvk/nrf5340/cpuapp" + help + The board which will be used for CPUAPP domain when creating a multi + image application where one or more images should be located on + another board. + +endif # BOARD_BL5340_DVK_NRF5340_CPUNET diff --git a/boards/lairdconnect/bl5340_dvk/Kconfig.bl5340_dvk b/boards/ezurio/bl5340_dvk/Kconfig.bl5340_dvk similarity index 100% rename from boards/lairdconnect/bl5340_dvk/Kconfig.bl5340_dvk rename to boards/ezurio/bl5340_dvk/Kconfig.bl5340_dvk diff --git a/boards/ezurio/bl5340_dvk/Kconfig.defconfig b/boards/ezurio/bl5340_dvk/Kconfig.defconfig new file mode 100644 index 00000000000..d90d05152fa --- /dev/null +++ b/boards/ezurio/bl5340_dvk/Kconfig.defconfig @@ -0,0 +1,112 @@ +# BL5340-DVK board configuration + +# Copyright (c) 2019-2020 Nordic Semiconductor ASA +# Copyright (c) 2021-2023 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BL5340_DVK_NRF5340_CPUAPP || BOARD_BL5340_DVK_NRF5340_CPUAPP_NS + +config I2C + default GPIO || DAC + +# Code Partition: +# +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# SRAM Partition: +# +# If the secure firmware is to be combined with a non-secure image +# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always +# be restricted to the secure image SRAM partition (sram-secure-partition). +# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram +# may be used by the image. +# +# For the non-secure version of the board, the firmware image SRAM is +# always restricted to the allocated non-secure SRAM partition. +# +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition +DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition + +if BOARD_BL5340_DVK_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config SRAM_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K) + +endif # BOARD_BL5340_DVK_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE + +if BOARD_BL5340_DVK_NRF5340_CPUAPP_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_BL5340_DVK_NRF5340_CPUAPP_NS + +config BT_HCI_IPC + default y if BT + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BT_HCI_IPC + +config BT_HCI_VS + default y if BT + +# 2.8" TFT Touch Shield for Arduino w/Capacitive Touch Screen Module +# is mounted to the DVK using standoffs. +# https://www.buydisplay.com/2-8-inch-tft-touch-shield-for-arduino-w-capacitive-touch-screen-module +if DISPLAY + +config INPUT_FT5336_INTERRUPT + default y + +if LVGL + +config LV_Z_VDB_SIZE + default 64 + +config LV_Z_BITS_PER_PIXEL + default 16 + +choice LV_COLOR_DEPTH + default LV_COLOR_DEPTH_16 +endchoice + +config LV_COLOR_16_SWAP + default y + +config INPUT + default y + +endif # LVGL + +endif # DISPLAY + +endif # BOARD_BL5340_DVK_NRF5340_CPUAPP || BOARD_BL5340_DVK_NRF5340_CPUAPP_NS + +if BOARD_BL5340_DVK_NRF5340_CPUNET + +# BT_CTLR depends on BT. When BT is enabled we should default to also +# enabling the controller. +config BT_CTLR + default y if BT + +config BT_ECC + default y if BT + +endif # BOARD_BL5340_DVK_NRF5340_CPUNET diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp.dts b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp.dts similarity index 80% rename from boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp.dts rename to boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp.dts index 7640e86e4aa..a1ef13d63e5 100644 --- a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp.dts +++ b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp.dts @@ -1,5 +1,6 @@ /* * Copyright (c) 2021 Laird Connectivity + * Copyright (c) 2024 Ezurio * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,8 +10,8 @@ #include "bl5340_dvk_nrf5340_cpuapp_common.dtsi" / { - model = "Laird Connectivity BL5340 (nRF5340) Application"; - compatible = "lairdconnect,bl5340-dvk-cpuapp"; + model = "Ezurio BL5340 (nRF5340) Application"; + compatible = "ezurio,bl5340-dvk-cpuapp"; chosen { zephyr,sram = &sram0_image; diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp.yaml b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp.yaml similarity index 88% rename from boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp.yaml rename to boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp.yaml index 1b23d5f23ec..cf432d7ab6e 100644 --- a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp.yaml +++ b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp.yaml @@ -16,7 +16,6 @@ supported: - qspi - spi - uart - - usb_cdc - usb_device - watchdog -vendor: lairdconnect +vendor: ezurio diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common-pinctrl.dtsi b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common-pinctrl.dtsi similarity index 100% rename from boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common-pinctrl.dtsi rename to boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common-pinctrl.dtsi diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common.dtsi b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common.dtsi similarity index 97% rename from boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common.dtsi rename to boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common.dtsi index 8a7f52a224e..af4f1cddeae 100644 --- a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common.dtsi +++ b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common.dtsi @@ -105,14 +105,13 @@ watchdog0 = &wdt0; accel0 = &lis3dh; bbram0 = &extrtc0; - spi-flash0 = &mx25r64; }; mipi_dbi { compatible = "zephyr,mipi-dbi-spi"; reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; dc-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - spi-dev = <&spi2>; + spi-dev = <&spi4>; write-only; #address-cells = <1>; #size-cells = <0>; @@ -128,6 +127,18 @@ }; }; +&vregmain { + regulator-initial-mode = ; +}; + +&vregradio { + regulator-initial-mode = ; +}; + +&vregh { + status = "okay"; +}; + &adc { status = "okay"; }; @@ -152,7 +163,7 @@ pinctrl-1 = <&i2c1_sleep>; pinctrl-names = "default", "sleep"; at24c256@50 { - compatible = "atmel,at24"; + compatible = "atmel,at24c256", "atmel,at24"; reg = <0x50>; size = <32768>; pagesize = <64>; diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_defconfig b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_defconfig similarity index 100% rename from boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_defconfig rename to boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_defconfig diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.dts b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.dts similarity index 76% rename from boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.dts rename to boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.dts index d159b8c4afe..35410c51b70 100644 --- a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.dts +++ b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.dts @@ -1,5 +1,6 @@ /* * Copyright (c) 2021 Laird Connectivity + * Copyright (c) 2024 Ezurio * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,8 +10,8 @@ #include "bl5340_dvk_nrf5340_cpuapp_common.dtsi" / { - model = "Laird Connectivity BL5340 (nRF5340) Application"; - compatible = "lairdconnect,bl5340-dvk-cpuapp"; + model = "Ezurio BL5340 (nRF5340) Application"; + compatible = "ezurio,bl5340-dvk-cpuapp"; chosen { zephyr,sram = &sram0_ns; diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.yaml b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.yaml similarity index 88% rename from boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.yaml rename to boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.yaml index 087975c8d0d..89d29c79e05 100644 --- a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.yaml +++ b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.yaml @@ -15,7 +15,6 @@ supported: - pwm - spi - uart - - usb_cdc - usb_device - watchdog -vendor: lairdconnect +vendor: ezurio diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns_defconfig b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns_defconfig similarity index 100% rename from boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns_defconfig rename to boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns_defconfig diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_partition_conf.dtsi b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_partition_conf.dtsi similarity index 100% rename from boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_partition_conf.dtsi rename to boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_partition_conf.dtsi diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet-pinctrl.dtsi b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet-pinctrl.dtsi similarity index 100% rename from boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet-pinctrl.dtsi rename to boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet-pinctrl.dtsi diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet.dts b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet.dts similarity index 86% rename from boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet.dts rename to boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet.dts index 4df761d0487..ef70281f166 100644 --- a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet.dts +++ b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet.dts @@ -1,5 +1,6 @@ /* * Copyright (c) 2021-2023 Laird Connectivity + * Copyright (c) 2024 Ezurio * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,8 +11,8 @@ #include "bl5340_dvk_nrf5340_cpunet_common.dtsi" / { - model = "Laird Connectivity BL5340 (nRF5340) Network"; - compatible = "lairdconnect,bl5340-dvk-cpunet"; + model = "Ezurio BL5340 (nRF5340) Network"; + compatible = "ezurio,bl5340-dvk-cpunet"; chosen { zephyr,console = &uart0; diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet.yaml b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet.yaml similarity index 91% rename from boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet.yaml rename to boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet.yaml index d9727296714..ab6f60bdd3a 100644 --- a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet.yaml +++ b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet.yaml @@ -15,4 +15,4 @@ supported: - spi - uart - watchdog -vendor: lairdconnect +vendor: ezurio diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_common.dtsi b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_common.dtsi similarity index 100% rename from boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_common.dtsi rename to boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_common.dtsi diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_defconfig b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_defconfig similarity index 100% rename from boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_defconfig rename to boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_defconfig diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_shared_sram_planning_conf.dtsi b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_shared_sram_planning_conf.dtsi similarity index 100% rename from boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_shared_sram_planning_conf.dtsi rename to boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_shared_sram_planning_conf.dtsi diff --git a/boards/lairdconnect/bl5340_dvk/board.cmake b/boards/ezurio/bl5340_dvk/board.cmake similarity index 100% rename from boards/lairdconnect/bl5340_dvk/board.cmake rename to boards/ezurio/bl5340_dvk/board.cmake diff --git a/boards/ezurio/bl5340_dvk/board.yml b/boards/ezurio/bl5340_dvk/board.yml new file mode 100644 index 00000000000..69be46ffe62 --- /dev/null +++ b/boards/ezurio/bl5340_dvk/board.yml @@ -0,0 +1,8 @@ +board: + name: bl5340_dvk + vendor: ezurio + socs: + - name: 'nrf5340' + variants: + - name: 'ns' + cpucluster: 'cpuapp' diff --git a/boards/lairdconnect/bl5340_dvk/doc/img/bl5340_dvk_top.jpg b/boards/ezurio/bl5340_dvk/doc/img/bl5340_dvk_top.jpg similarity index 100% rename from boards/lairdconnect/bl5340_dvk/doc/img/bl5340_dvk_top.jpg rename to boards/ezurio/bl5340_dvk/doc/img/bl5340_dvk_top.jpg diff --git a/boards/ezurio/bl5340_dvk/doc/index.rst b/boards/ezurio/bl5340_dvk/doc/index.rst new file mode 100644 index 00000000000..62a7de87f93 --- /dev/null +++ b/boards/ezurio/bl5340_dvk/doc/index.rst @@ -0,0 +1,436 @@ +.. _bl5340_dvk: + +Ezurio BL5340 DVK +################# + +Overview +******** +The BL5340 Development Kit provides support for the Ezurio +BL5340 module which is powered by a dual-core Nordic Semiconductor +nRF5340 ARM Cortex-M33F CPU. The nRF5340 inside the BL5340 module is a +dual-core SoC based on the Arm® Cortex®-M33 architecture, with: + +* a full-featured Arm Cortex-M33F core with DSP instructions, FPU, and + Armv8-M Security Extension, running at up to 128 MHz, referred to as + the **application core** +* a secondary Arm Cortex-M33 core, with a reduced feature set, running + at a fixed 64 MHz, referred to as the **network core**. + +The ``bl5340_dvk/nrf5340/cpuapp`` build target provides support for the application +core on the BL5340 module. The ``bl5340_dvk/nrf5340/cpunet`` build target provides +support for the network core on the BL5340 module. If ARM TrustZone is +used then the ``bl5340_dvk/nrf5340/cpuapp`` build target provides support for the +non-secure partition of the application core on the BL5340 module. + +This development kit has the following features: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`IDAU (Implementation Defined Attribution Unit)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`I2S (Inter-Integrated Sound)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`QSPI (Quad Serial Peripheral Interface)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/bl5340_dvk_top.jpg + :align: center + :alt: BL5340 DVK + + BL5340 DVK (Credit: Ezurio) + +More information about the module can be found on the +`BL5340 homepage`_. + +The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + +Hardware +******** + +The BL5340 DVK has two external oscillators. The frequency of +the slow clock is 32.768KHz. The frequency of the main clock +is 32MHz. + +Supported Features +================== + +The ``bl5340_dvk/nrf5340/cpuapp`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| QSPI(M) | on-chip | nor | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +The ``bl5340_dvk/nrf5340/cpunet`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See `Nordic Semiconductor Infocenter`_ +for a complete list of hardware features. + +Connections and IOs +=================== + +An eight-pin GPIO port expander is used to provide additional inputs +and outputs to the BL5340 module. + +Refer to the `TI TCA9538 datasheet`_ for further details. + +LEDs +---- + +* LED1 (blue) = via TCA9538 port expander channel P4 (active low) +* LED2 (blue) = via TCA9538 port expander channel P5 (active low) +* LED3 (blue) = via TCA9538 port expander channel P6 (active low) +* LED4 (blue) = via TCA9538 port expander channel P7 (active low) + +Push buttons +------------ + +* BUTTON1 = SW1 = via TCA9538 port expander channel P0 (active low) +* BUTTON2 = SW2 = via TCA9538 port expander channel P1 (active low) +* BUTTON3 = SW3 = via TCA9538 port expander channel P2 (active low) +* BUTTON4 = SW4 = via TCA9538 port expander channel P3 (active low) +* BOOT = boot (active low) + +External Memory +=============== + +Several external memory sources are available for the BL5340 DVK. These +are described as follows. + +Flash Memory +------------ + +A Macronix MX25R6435FZNIL0 8MB external QSPI Flash memory part is +incorporated for application image storage and large datasets. + +Refer to the `Macronix MX25R6435FZNIL0 datasheet`_ for further details. + +EEPROM Memory +------------- + +A 32KB Giantec GT24C256C-2GLI-TR EEPROM is available via I2C for +storage of infrequently updated data and small datasets. + +Refer to the `Giantec GT24C256C-2GLI-TR datasheet`_ for further details. + +External Memory +--------------- + +An on-board micro SD card slot is available for use with micro SD cards. + +Sensors +======= + +The BL5340 DVK incorporates two sensors for user application testing. +These are described as follows. + +Temperature, Pressure, Humidity & Air Quality Sensor +---------------------------------------------------- + +A Bosch BME680 Temperature, Pressure, Humidity & Air Quality sensor is +available via I2C for environmental measurement applications. + +Refer to the `Bosch BME680 datasheet`_ for further details. + +3-Axis Accelerometer +-------------------- + +An ST Microelectronics LIS3DH 3-Axis Accelerometer is available via I2C +for vibration and motion detection applications. + +Refer to the `ST Microelectronics LIS3DH datasheet`_ for further details. + +Ethernet +======== + +Cabled 10/100 Base-T Ethernet Connectivity is available via a Microchip +ENC424J600 Ethernet controller. + +Refer to the `Microchip ENC424J600 datasheet`_ for further details. + +TFT Display & Capacitive Touch Screen Controller +================================================ + +A 2.8 inch, 240 x 320 pixel TFT display with capacitive touch +controller is included with the BL5340 DVK for user interface +application features. + +Refer to the `ER_TFTM028_4 datasheet`_ for a high level overview of the +display. + +An ILI9341 TFT controller is incorporated in the TFT module and +acts as the main controller, controlled via SPI. + +Refer to the `ILI9341 datasheet`_ for further details. + +An FT6206 Capacitive Touch Controller, controlled via I2C is +also incorporated in the TFT module. + +Refer to the `FT6206 datasheet`_ for further details. + +Real-Time Clock +=============== + +A real-time clock is available for accurate time data availability. + +Refer to the `Microchip MCP7940N datasheet`_ for further details. + +DAC +=== + +A 10-bit Digital to Analog Converter is incorporated for generation of +variable voltages. + +Refer to the `Microchip MCP4725 datasheet`_ for further details. + +Security components +=================== + +- Implementation Defined Attribution Unit (`IDAU`_) on the application + core. The IDAU is implemented with the System Protection Unit and is + used to define secure and non-secure memory maps. By default, all of + the memory space (Flash, SRAM, and peripheral address space) is + defined to be secure accessible only. +- Secure boot. + +Programming and Debugging +************************* + +The BL5340's application core supports the Armv8-M Security Extension. +Applications built for the ``bl5340_dvk/nrf5340/cpuapp`` board by default +boot in the Secure state. + +The BL5340's network core does not support the Armv8-M Security +Extension. The IDAU may configure bus accesses by the network core to +have Secure attribute set; the latter allows to build and run Secure +only applications on the BL5340 module. + +Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| +============================================================================= + +Applications on the BL5340 module may contain a Secure and a Non-Secure +firmware image for the application core. The Secure image can be built +using either Zephyr or `Trusted Firmware M`_ (TF-M). Non-Secure +firmware images are always built using Zephyr. The two alternatives are +described below. + +.. note:: + + By default the Secure image for BL5340's application core is + built using TF-M. + +Building the Secure firmware with TF-M +-------------------------------------- + +The process to build the Secure firmware image using TF-M and the +Non-Secure firmware image using Zephyr requires the following steps: + +1. Build the Non-Secure Zephyr application + for the application core using ``-DBOARD=bl5340_dvk/nrf5340/cpuapp/ns``. + To invoke the building of TF-M the Zephyr build system requires the + Kconfig option ``BUILD_WITH_TFM`` to be enabled, which is done by + default when building Zephyr as a Non-Secure application. + The Zephyr build system will perform the following steps automatically: + + * Build the Non-Secure firmware image as a regular Zephyr application + * Build a TF-M (secure) firmware image + * Merge the output image binaries together + * Optionally build a bootloader image (MCUboot) + +.. note:: + + Depending on the TF-M configuration, an application DTS overlay may + be required, to adjust the Non-Secure image Flash and SRAM starting + address and sizes. + +2. Build the application firmware for the network core using + ``-DBOARD=bl5340_dvk/nrf5340/cpunet``. + +Building the Secure firmware using Zephyr +----------------------------------------- + +The process to build the Secure and the Non-Secure firmware images +using Zephyr requires the following steps: + +1. Build the Secure Zephyr application for the application core + using ``-DBOARD=bl5340_dvk/nrf5340/cpuapp`` and + ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` and ``CONFIG_BUILD_WITH_TFM=n`` + in the application project configuration file. +2. Build the Non-Secure Zephyr application for the application core + using ``-DBOARD=bl5340_dvk/nrf5340/cpuapp/ns``. +3. Merge the two binaries together. +4. Build the application firmware for the network core using + ``-DBOARD=bl5340_dvk/nrf5340/cpunet``. + +When building a Secure/Non-Secure application for the BL5340's +application core, the Secure application will have to set the IDAU +(SPU) configuration to allow Non-Secure access to all CPU resources +utilized by the Non-Secure application firmware. SPU configuration +shall take place before jumping to the Non-Secure application. + +Building a Secure only application +================================== + +Build the Zephyr app in the usual way (see :ref:`build_an_application` +and :ref:`application_run`), using ``-DBOARD=bl5340_dvk/nrf5340/cpuapp`` for +the firmware running on the BL5340's application core, and using +``-DBOARD=bl5340_dvk/nrf5340/cpunet`` for the firmware running +on the BL5340's network core. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then you can build and flash +applications as usual (:ref:`build_an_application` and +:ref:`application_run` for more details). + +.. warning:: + + The BL5340 has a flash read-back protection feature. When flash + read-back protection is active, you will need to recover the chip + before reflashing. If you are flashing with + :ref:`west `, run this command for more + details on the related ``--recover`` option: + + .. code-block:: console + + west flash -H -r nrfjprog --skip-rebuild + +.. note:: + + Flashing and debugging applications on the BL5340 DVK requires + upgrading the nRF Command Line Tools to version 10.12.0 or newer. + Further information on how to install the nRF Command Line Tools can + be found in :ref:`nordic_segger_flashing`. + +Here is an example for the :zephyr:code-sample:`hello_world` application running on the +BL5340's application core. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the BL5340 DVK board +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: bl5340_dvk/nrf5340/cpuapp + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging +boards with a Segger IC. + +Testing Bluetooth on the BL5340 DVK +*********************************** +Many of the Bluetooth examples will work on the BL5340 DVK. +Try them out: + +* :zephyr:code-sample:`ble_peripheral` +* :zephyr:code-sample:`bluetooth_eddystone` +* :zephyr:code-sample:`bluetooth_ibeacon` + +References +********** + +.. target-notes:: + +.. _IDAU: + https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau +.. _BL5340 homepage: https://www.ezurio.com/wireless-modules/bluetooth-modules/bluetooth-5-modules/bl5340-series-multi-core-bluetooth-52-802154-nfc-modules +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +.. _TI TCA9538 datasheet: https://www.ti.com/lit/gpn/TCA9538 +.. _Macronix MX25R6435FZNIL0 datasheet: https://www.macronix.com/Lists/Datasheet/Attachments/8868/MX25R6435F,%20Wide%20Range,%2064Mb,%20v1.6.pdf +.. _Giantec GT24C256C-2GLI-TR datasheet: https://www.giantec-semi.com/juchen1123/uploads/pdf/GT24C256C_DS_Cu.pdf +.. _Bosch BME680 datasheet: https://www.bosch-sensortec.com/media/boschsensortec/downloads/datasheets/bst-bme680-ds001.pdf +.. _ST Microelectronics LIS3DH datasheet: https://www.st.com/resource/en/datasheet/lis3dh.pdf +.. _Microchip ENC424J600 datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/39935c.pdf +.. _ER_TFTM028_4 datasheet: https://www.buydisplay.com/download/manual/ER-TFTM028-4_Datasheet.pdf +.. _ILI9341 datasheet: https://www.buydisplay.com/download/ic/ILI9341.pdf +.. _FT6206 datasheet: https://www.buydisplay.com/download/ic/FT6206.pdf +.. _Microchip MCP7940N datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/20005010H.pdf +.. _Microchip MCP4725 datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/22039d.pdf +.. _Trusted Firmware M: https://www.trustedfirmware.org/projects/tf-m/ diff --git a/boards/lairdconnect/bl5340_dvk/pre_dt_board.cmake b/boards/ezurio/bl5340_dvk/pre_dt_board.cmake similarity index 100% rename from boards/lairdconnect/bl5340_dvk/pre_dt_board.cmake rename to boards/ezurio/bl5340_dvk/pre_dt_board.cmake diff --git a/boards/lairdconnect/bl652_dvk/Kconfig.bl652_dvk b/boards/ezurio/bl652_dvk/Kconfig.bl652_dvk similarity index 100% rename from boards/lairdconnect/bl652_dvk/Kconfig.bl652_dvk rename to boards/ezurio/bl652_dvk/Kconfig.bl652_dvk diff --git a/boards/lairdconnect/bl652_dvk/Kconfig.defconfig b/boards/ezurio/bl652_dvk/Kconfig.defconfig similarity index 100% rename from boards/lairdconnect/bl652_dvk/Kconfig.defconfig rename to boards/ezurio/bl652_dvk/Kconfig.defconfig diff --git a/boards/lairdconnect/bl652_dvk/bl652_dvk-pinctrl.dtsi b/boards/ezurio/bl652_dvk/bl652_dvk-pinctrl.dtsi similarity index 100% rename from boards/lairdconnect/bl652_dvk/bl652_dvk-pinctrl.dtsi rename to boards/ezurio/bl652_dvk/bl652_dvk-pinctrl.dtsi diff --git a/boards/lairdconnect/bl652_dvk/bl652_dvk.dts b/boards/ezurio/bl652_dvk/bl652_dvk.dts similarity index 95% rename from boards/lairdconnect/bl652_dvk/bl652_dvk.dts rename to boards/ezurio/bl652_dvk/bl652_dvk.dts index f2cffbd819b..bb64c893af0 100644 --- a/boards/lairdconnect/bl652_dvk/bl652_dvk.dts +++ b/boards/ezurio/bl652_dvk/bl652_dvk.dts @@ -1,6 +1,7 @@ /* * Copyright (c) 2019 Laird Connectivity * Copyright (c) 2023 Nordic Semiconductor ASA + * Copyright (c) 2024 Ezurio * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,8 +12,8 @@ #include / { - model = "Laird BL652 DVK"; - compatible = "lairdconnect,bl652_dvk"; + model = "Ezurio BL652 DVK"; + compatible = "ezurio,bl652_dvk"; chosen { zephyr,console = &uart0; @@ -64,6 +65,10 @@ }; }; +® { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; diff --git a/boards/lairdconnect/bl652_dvk/bl652_dvk.yaml b/boards/ezurio/bl652_dvk/bl652_dvk.yaml similarity index 89% rename from boards/lairdconnect/bl652_dvk/bl652_dvk.yaml rename to boards/ezurio/bl652_dvk/bl652_dvk.yaml index a2fd4370d7f..a549fcfdd66 100644 --- a/boards/lairdconnect/bl652_dvk/bl652_dvk.yaml +++ b/boards/ezurio/bl652_dvk/bl652_dvk.yaml @@ -15,4 +15,4 @@ supported: - pwm - spi - watchdog -vendor: lairdconnect +vendor: ezurio diff --git a/boards/lairdconnect/bl652_dvk/bl652_dvk_defconfig b/boards/ezurio/bl652_dvk/bl652_dvk_defconfig similarity index 100% rename from boards/lairdconnect/bl652_dvk/bl652_dvk_defconfig rename to boards/ezurio/bl652_dvk/bl652_dvk_defconfig diff --git a/boards/lairdconnect/bl652_dvk/board.cmake b/boards/ezurio/bl652_dvk/board.cmake similarity index 100% rename from boards/lairdconnect/bl652_dvk/board.cmake rename to boards/ezurio/bl652_dvk/board.cmake diff --git a/boards/ezurio/bl652_dvk/board.yml b/boards/ezurio/bl652_dvk/board.yml new file mode 100644 index 00000000000..b573627457f --- /dev/null +++ b/boards/ezurio/bl652_dvk/board.yml @@ -0,0 +1,5 @@ +board: + name: bl652_dvk + vendor: ezurio + socs: + - name: nrf52832 diff --git a/boards/lairdconnect/bl652_dvk/doc/bl652_dvk.rst b/boards/ezurio/bl652_dvk/doc/bl652_dvk.rst similarity index 94% rename from boards/lairdconnect/bl652_dvk/doc/bl652_dvk.rst rename to boards/ezurio/bl652_dvk/doc/bl652_dvk.rst index 9acbb30d46e..aaae4b9071b 100644 --- a/boards/lairdconnect/bl652_dvk/doc/bl652_dvk.rst +++ b/boards/ezurio/bl652_dvk/doc/bl652_dvk.rst @@ -1,13 +1,13 @@ .. _bl652_dvk: -Laird Connectivity BL652 DVK -############################ +Ezurio BL652 DVK +################ Overview ******** The BL652 Development Kit hardware provides -support for the Laird Connectivity BL652 module powered by a Nordic Semiconductor nRF52832 ARM Cortex-M4F CPU. +support for the Ezurio BL652 module powered by a Nordic Semiconductor nRF52832 ARM Cortex-M4F CPU. This development kit has the following features: @@ -214,7 +214,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. @@ -245,9 +245,9 @@ Testing Bluetooth on the BL652 DVK Many of the Bluetooth examples will work on the BL652 DVK. Try them out: -* :ref:`ble_peripheral` -* :ref:`bluetooth-eddystone-sample` -* :ref:`bluetooth-ibeacon-sample` +* :zephyr:code-sample:`ble_peripheral` +* :zephyr:code-sample:`bluetooth_eddystone` +* :zephyr:code-sample:`bluetooth_ibeacon` Testing the LEDs and buttons in the BL652 DVK ********************************************* @@ -260,11 +260,11 @@ the board are working properly with Zephyr: You can build and flash the examples to make sure Zephyr is running correctly on your board. The button and LED definitions can be found in -:zephyr_file:`boards/lairdconnect/bl652_dvk/bl652_dvk.dts`. +:zephyr_file:`boards/ezurio/bl652_dvk/bl652_dvk.dts`. References ********** .. target-notes:: -.. _BL652 Module Website: https://connectivity.lairdtech.com/wireless-modules/bluetooth-modules/bluetooth-5-modules/bl652-series-bluetooth-v5-nfc +.. _BL652 Module Website: https://ezurio.com/wireless-modules/bluetooth-modules/bluetooth-5-modules/bl652-series-bluetooth-v5-nfc diff --git a/boards/lairdconnect/bl652_dvk/doc/img/BL652-SA_DVK_BoxContents.jpg b/boards/ezurio/bl652_dvk/doc/img/BL652-SA_DVK_BoxContents.jpg similarity index 100% rename from boards/lairdconnect/bl652_dvk/doc/img/BL652-SA_DVK_BoxContents.jpg rename to boards/ezurio/bl652_dvk/doc/img/BL652-SA_DVK_BoxContents.jpg diff --git a/boards/lairdconnect/bl652_dvk/doc/img/bl652_dvk.jpg b/boards/ezurio/bl652_dvk/doc/img/bl652_dvk.jpg similarity index 100% rename from boards/lairdconnect/bl652_dvk/doc/img/bl652_dvk.jpg rename to boards/ezurio/bl652_dvk/doc/img/bl652_dvk.jpg diff --git a/boards/lairdconnect/bl653_dvk/pre_dt_board.cmake b/boards/ezurio/bl652_dvk/pre_dt_board.cmake similarity index 100% rename from boards/lairdconnect/bl653_dvk/pre_dt_board.cmake rename to boards/ezurio/bl652_dvk/pre_dt_board.cmake diff --git a/boards/lairdconnect/bl653_dvk/Kconfig.bl653_dvk b/boards/ezurio/bl653_dvk/Kconfig.bl653_dvk similarity index 100% rename from boards/lairdconnect/bl653_dvk/Kconfig.bl653_dvk rename to boards/ezurio/bl653_dvk/Kconfig.bl653_dvk diff --git a/boards/lairdconnect/bl653_dvk/Kconfig.defconfig b/boards/ezurio/bl653_dvk/Kconfig.defconfig similarity index 100% rename from boards/lairdconnect/bl653_dvk/Kconfig.defconfig rename to boards/ezurio/bl653_dvk/Kconfig.defconfig diff --git a/boards/lairdconnect/bl653_dvk/bl653_dvk-pinctrl.dtsi b/boards/ezurio/bl653_dvk/bl653_dvk-pinctrl.dtsi similarity index 100% rename from boards/lairdconnect/bl653_dvk/bl653_dvk-pinctrl.dtsi rename to boards/ezurio/bl653_dvk/bl653_dvk-pinctrl.dtsi diff --git a/boards/lairdconnect/bl653_dvk/bl653_dvk.dts b/boards/ezurio/bl653_dvk/bl653_dvk.dts similarity index 95% rename from boards/lairdconnect/bl653_dvk/bl653_dvk.dts rename to boards/ezurio/bl653_dvk/bl653_dvk.dts index 4c536eb4512..c9c8d3ed74c 100644 --- a/boards/lairdconnect/bl653_dvk/bl653_dvk.dts +++ b/boards/ezurio/bl653_dvk/bl653_dvk.dts @@ -1,6 +1,7 @@ /* * Copyright (c) 2020 Laird Connectivity * Copyright (c) 2023 Nordic Semiconductor ASA + * Copyright (c) 2024 Ezurio * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,8 +12,8 @@ #include / { - model = "Laird BL653 Dev Kit"; - compatible = "lairdconnect,bl653_dvk"; + model = "Ezurio BL653 Dev Kit"; + compatible = "ezurio,bl653_dvk"; chosen { zephyr,console = &uart0; @@ -87,6 +88,10 @@ }; }; +®1 { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; diff --git a/boards/lairdconnect/bl653_dvk/bl653_dvk.yaml b/boards/ezurio/bl653_dvk/bl653_dvk.yaml similarity index 90% rename from boards/lairdconnect/bl653_dvk/bl653_dvk.yaml rename to boards/ezurio/bl653_dvk/bl653_dvk.yaml index 6a2792ea521..ee1b610f312 100644 --- a/boards/lairdconnect/bl653_dvk/bl653_dvk.yaml +++ b/boards/ezurio/bl653_dvk/bl653_dvk.yaml @@ -16,4 +16,4 @@ supported: - counter - spi - i2c -vendor: lairdconnect +vendor: ezurio diff --git a/boards/lairdconnect/bl653_dvk/bl653_dvk_defconfig b/boards/ezurio/bl653_dvk/bl653_dvk_defconfig similarity index 100% rename from boards/lairdconnect/bl653_dvk/bl653_dvk_defconfig rename to boards/ezurio/bl653_dvk/bl653_dvk_defconfig diff --git a/boards/lairdconnect/bl653_dvk/board.cmake b/boards/ezurio/bl653_dvk/board.cmake similarity index 100% rename from boards/lairdconnect/bl653_dvk/board.cmake rename to boards/ezurio/bl653_dvk/board.cmake diff --git a/boards/ezurio/bl653_dvk/board.yml b/boards/ezurio/bl653_dvk/board.yml new file mode 100644 index 00000000000..dc42555309a --- /dev/null +++ b/boards/ezurio/bl653_dvk/board.yml @@ -0,0 +1,5 @@ +board: + name: bl653_dvk + vendor: ezurio + socs: + - name: nrf52833 diff --git a/boards/lairdconnect/bl653_dvk/doc/bl653_dvk.rst b/boards/ezurio/bl653_dvk/doc/bl653_dvk.rst similarity index 92% rename from boards/lairdconnect/bl653_dvk/doc/bl653_dvk.rst rename to boards/ezurio/bl653_dvk/doc/bl653_dvk.rst index 71270f6f4e8..48c252b5ff9 100644 --- a/boards/lairdconnect/bl653_dvk/doc/bl653_dvk.rst +++ b/boards/ezurio/bl653_dvk/doc/bl653_dvk.rst @@ -1,13 +1,13 @@ .. _bl653_dvk: -Laird Connectivity BL653 DVK -############################ +Ezurio BL653 DVK +################ Overview ******** The BL653 Development Kit (453-00039-K1, 453-00041-K1) hardware provides -support for the Laird Connectivity BL653 module powered by a Nordic Semiconductor nRF52833 ARM Cortex-M4F CPU. +support for the Ezurio BL653 module powered by a Nordic Semiconductor nRF52833 ARM Cortex-M4F CPU. This development kit has the following features: @@ -120,7 +120,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. @@ -151,9 +151,9 @@ Testing Bluetooth on the BL653 DVK Many of the Bluetooth examples will work on the BL653 DVK. Try them out: -* :ref:`ble_peripheral` -* :ref:`bluetooth-eddystone-sample` -* :ref:`bluetooth-ibeacon-sample` +* :zephyr:code-sample:`ble_peripheral` +* :zephyr:code-sample:`bluetooth_eddystone` +* :zephyr:code-sample:`bluetooth_ibeacon` Testing the LEDs and buttons on the BL653 DVK @@ -167,7 +167,7 @@ the board are working properly with Zephyr: You can build and flash the examples to make sure Zephyr is running correctly on your board. The button and LED definitions can be found in -:zephyr_file:`boards/lairdconnect/bl653_dvk/bl653_dvk.dts`. +:zephyr_file:`boards/ezurio/bl653_dvk/bl653_dvk.dts`. Using UART1 *********** @@ -225,5 +225,5 @@ References .. target-notes:: -.. _BL653 website: https://www.lairdconnect.com/wireless-modules/bluetooth-modules/bluetooth-5-modules/bl653-series-bluetooth-51-802154-nfc-module +.. _BL653 website: https://www.ezurio.com/wireless-modules/bluetooth-modules/bluetooth-5-modules/bl653-series-bluetooth-51-802154-nfc-module .. _nRF52833 Product Specification: https://infocenter.nordicsemi.com/pdf/nRF52833_OPS_v0.7.pdf diff --git a/boards/lairdconnect/bl653_dvk/doc/img/bl653_dvk.jpg b/boards/ezurio/bl653_dvk/doc/img/bl653_dvk.jpg similarity index 100% rename from boards/lairdconnect/bl653_dvk/doc/img/bl653_dvk.jpg rename to boards/ezurio/bl653_dvk/doc/img/bl653_dvk.jpg diff --git a/boards/lairdconnect/bl654_dvk/pre_dt_board.cmake b/boards/ezurio/bl653_dvk/pre_dt_board.cmake similarity index 100% rename from boards/lairdconnect/bl654_dvk/pre_dt_board.cmake rename to boards/ezurio/bl653_dvk/pre_dt_board.cmake diff --git a/boards/lairdconnect/bl654_dvk/Kconfig.bl654_dvk b/boards/ezurio/bl654_dvk/Kconfig.bl654_dvk similarity index 100% rename from boards/lairdconnect/bl654_dvk/Kconfig.bl654_dvk rename to boards/ezurio/bl654_dvk/Kconfig.bl654_dvk diff --git a/boards/lairdconnect/bl654_dvk/Kconfig.defconfig b/boards/ezurio/bl654_dvk/Kconfig.defconfig similarity index 100% rename from boards/lairdconnect/bl654_dvk/Kconfig.defconfig rename to boards/ezurio/bl654_dvk/Kconfig.defconfig diff --git a/boards/lairdconnect/bl654_dvk/bl654_dvk-pinctrl.dtsi b/boards/ezurio/bl654_dvk/bl654_dvk-pinctrl.dtsi similarity index 100% rename from boards/lairdconnect/bl654_dvk/bl654_dvk-pinctrl.dtsi rename to boards/ezurio/bl654_dvk/bl654_dvk-pinctrl.dtsi diff --git a/boards/lairdconnect/bl654_dvk/bl654_dvk.dts b/boards/ezurio/bl654_dvk/bl654_dvk.dts similarity index 77% rename from boards/lairdconnect/bl654_dvk/bl654_dvk.dts rename to boards/ezurio/bl654_dvk/bl654_dvk.dts index 7ede69427de..88e478349a1 100644 --- a/boards/lairdconnect/bl654_dvk/bl654_dvk.dts +++ b/boards/ezurio/bl654_dvk/bl654_dvk.dts @@ -1,18 +1,20 @@ /* * Copyright (c) 2019 Laird Connectivity * Copyright (c) 2023 Nordic Semiconductor ASA + * Copyright (c) 2024 Ezurio * * SPDX-License-Identifier: Apache-2.0 */ /dts-v1/; #include +#include #include "bl654_dvk-pinctrl.dtsi" #include / { - model = "Laird BL654 Dev Kit"; - compatible = "lairdconnect,bl654_dvk"; + model = "Ezurio BL654 Dev Kit"; + compatible = "ezurio,bl654_dvk"; chosen { zephyr,console = &uart0; @@ -20,9 +22,6 @@ zephyr,uart-mcumgr = &uart0; zephyr,bt-mon-uart = &uart0; zephyr,bt-c2h-uart = &uart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; zephyr,ieee802154 = &ieee802154; }; @@ -87,6 +86,10 @@ }; }; +®1 { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; @@ -177,46 +180,6 @@ status = "okay"; }; -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000C000>; - }; - slot0_partition: partition@c000 { - label = "image-0"; - reg = <0x0000C000 0x00067000>; - }; - slot1_partition: partition@73000 { - label = "image-1"; - reg = <0x00073000 0x00067000>; - }; - scratch_partition: partition@da000 { - label = "image-scratch"; - reg = <0x000da000 0x0001e000>; - }; - - /* - * The flash starting at 0x000f8000 and ending at - * 0x000fffff is reserved for use by the application. - */ - - /* - * Storage partition will be used by FCB/LittleFS/NVS - * if enabled. - */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; - zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; diff --git a/boards/lairdconnect/bl654_dvk/bl654_dvk.yaml b/boards/ezurio/bl654_dvk/bl654_dvk.yaml similarity index 88% rename from boards/lairdconnect/bl654_dvk/bl654_dvk.yaml rename to boards/ezurio/bl654_dvk/bl654_dvk.yaml index 27eec7dcaeb..c4d016d63b6 100644 --- a/boards/lairdconnect/bl654_dvk/bl654_dvk.yaml +++ b/boards/ezurio/bl654_dvk/bl654_dvk.yaml @@ -12,4 +12,4 @@ supported: - ble - pwm - watchdog -vendor: lairdconnect +vendor: ezurio diff --git a/boards/lairdconnect/bl654_dvk/bl654_dvk_defconfig b/boards/ezurio/bl654_dvk/bl654_dvk_defconfig similarity index 100% rename from boards/lairdconnect/bl654_dvk/bl654_dvk_defconfig rename to boards/ezurio/bl654_dvk/bl654_dvk_defconfig diff --git a/boards/lairdconnect/bl654_dvk/bl654_dvk_nrf52840_pa.dts b/boards/ezurio/bl654_dvk/bl654_dvk_nrf52840_pa.dts similarity index 100% rename from boards/lairdconnect/bl654_dvk/bl654_dvk_nrf52840_pa.dts rename to boards/ezurio/bl654_dvk/bl654_dvk_nrf52840_pa.dts diff --git a/boards/lairdconnect/bl654_dvk/bl654_dvk_nrf52840_pa.yaml b/boards/ezurio/bl654_dvk/bl654_dvk_nrf52840_pa.yaml similarity index 90% rename from boards/lairdconnect/bl654_dvk/bl654_dvk_nrf52840_pa.yaml rename to boards/ezurio/bl654_dvk/bl654_dvk_nrf52840_pa.yaml index d02d9386284..6ecf9191591 100644 --- a/boards/lairdconnect/bl654_dvk/bl654_dvk_nrf52840_pa.yaml +++ b/boards/ezurio/bl654_dvk/bl654_dvk_nrf52840_pa.yaml @@ -12,4 +12,4 @@ supported: - ble - pwm - watchdog -vendor: lairdconnect +vendor: ezurio diff --git a/boards/lairdconnect/bl654_dvk/bl654_dvk_nrf52840_pa_defconfig b/boards/ezurio/bl654_dvk/bl654_dvk_nrf52840_pa_defconfig similarity index 100% rename from boards/lairdconnect/bl654_dvk/bl654_dvk_nrf52840_pa_defconfig rename to boards/ezurio/bl654_dvk/bl654_dvk_nrf52840_pa_defconfig diff --git a/boards/lairdconnect/bl654_dvk/board.cmake b/boards/ezurio/bl654_dvk/board.cmake similarity index 100% rename from boards/lairdconnect/bl654_dvk/board.cmake rename to boards/ezurio/bl654_dvk/board.cmake diff --git a/boards/ezurio/bl654_dvk/board.yml b/boards/ezurio/bl654_dvk/board.yml new file mode 100644 index 00000000000..fdc9035ff68 --- /dev/null +++ b/boards/ezurio/bl654_dvk/board.yml @@ -0,0 +1,7 @@ +board: + name: bl654_dvk + vendor: ezurio + socs: + - name: nrf52840 + variants: + - name: pa diff --git a/boards/lairdconnect/bl654_dvk/doc/bl654_dvk.rst b/boards/ezurio/bl654_dvk/doc/bl654_dvk.rst similarity index 91% rename from boards/lairdconnect/bl654_dvk/doc/bl654_dvk.rst rename to boards/ezurio/bl654_dvk/doc/bl654_dvk.rst index 7ccb6294f4b..d262a9a5146 100644 --- a/boards/lairdconnect/bl654_dvk/doc/bl654_dvk.rst +++ b/boards/ezurio/bl654_dvk/doc/bl654_dvk.rst @@ -1,13 +1,13 @@ .. _bl654_dvk: -Laird Connectivity BL654 DVK -############################ +Ezurio BL654 DVK +################ Overview ******** The BL654 Development Kit hardware provides -support for the Laird Connectivity BL654 module powered by a Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU. +support for the Ezurio BL654 module powered by a Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU. It is also pin compatible with the BL654PA which adds a power amplifier. The "pa" variant provides this compatibility. Use board ``bl654_dvk/nrf52840/pa`` to build for that target. @@ -131,7 +131,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. @@ -162,9 +162,9 @@ Testing Bluetooth on the BL654 DVK Many of the Bluetooth examples will work on the BL654 DVK. Try them out: -* :ref:`ble_peripheral` -* :ref:`bluetooth-eddystone-sample` -* :ref:`bluetooth-ibeacon-sample` +* :zephyr:code-sample:`ble_peripheral` +* :zephyr:code-sample:`bluetooth_eddystone` +* :zephyr:code-sample:`bluetooth_ibeacon` Testing the LEDs and buttons on the BL654 DVK @@ -178,7 +178,7 @@ the board are working properly with Zephyr: You can build and flash the examples to make sure Zephyr is running correctly on your board. The button and LED definitions can be found in -:zephyr_file:`boards/lairdconnect/bl654_dvk/bl654_dvk.dts`. +:zephyr_file:`boards/ezurio/bl654_dvk/bl654_dvk.dts`. References @@ -186,5 +186,5 @@ References .. target-notes:: -.. _BL654 website: https://connectivity.lairdtech.com/wireless-modules/bluetooth-modules/bluetooth-5-modules/bl654-series +.. _BL654 website: https://ezurio.com/wireless-modules/bluetooth-modules/bluetooth-5-modules/bl654-series .. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html diff --git a/boards/lairdconnect/bl654_dvk/doc/img/455-00001_BoxContents.jpg b/boards/ezurio/bl654_dvk/doc/img/455-00001_BoxContents.jpg similarity index 100% rename from boards/lairdconnect/bl654_dvk/doc/img/455-00001_BoxContents.jpg rename to boards/ezurio/bl654_dvk/doc/img/455-00001_BoxContents.jpg diff --git a/boards/lairdconnect/bl654_dvk/doc/img/bl654_dvk.jpg b/boards/ezurio/bl654_dvk/doc/img/bl654_dvk.jpg similarity index 100% rename from boards/lairdconnect/bl654_dvk/doc/img/bl654_dvk.jpg rename to boards/ezurio/bl654_dvk/doc/img/bl654_dvk.jpg diff --git a/boards/lairdconnect/bl654_sensor_board/pre_dt_board.cmake b/boards/ezurio/bl654_dvk/pre_dt_board.cmake similarity index 100% rename from boards/lairdconnect/bl654_sensor_board/pre_dt_board.cmake rename to boards/ezurio/bl654_dvk/pre_dt_board.cmake diff --git a/boards/lairdconnect/bl654_sensor_board/Kconfig.bl654_sensor_board b/boards/ezurio/bl654_sensor_board/Kconfig.bl654_sensor_board similarity index 100% rename from boards/lairdconnect/bl654_sensor_board/Kconfig.bl654_sensor_board rename to boards/ezurio/bl654_sensor_board/Kconfig.bl654_sensor_board diff --git a/boards/lairdconnect/bl654_sensor_board/Kconfig.defconfig b/boards/ezurio/bl654_sensor_board/Kconfig.defconfig similarity index 100% rename from boards/lairdconnect/bl654_sensor_board/Kconfig.defconfig rename to boards/ezurio/bl654_sensor_board/Kconfig.defconfig diff --git a/boards/lairdconnect/bl654_sensor_board/bl654_sensor_board-pinctrl.dtsi b/boards/ezurio/bl654_sensor_board/bl654_sensor_board-pinctrl.dtsi similarity index 100% rename from boards/lairdconnect/bl654_sensor_board/bl654_sensor_board-pinctrl.dtsi rename to boards/ezurio/bl654_sensor_board/bl654_sensor_board-pinctrl.dtsi diff --git a/boards/lairdconnect/bl654_sensor_board/bl654_sensor_board.dts b/boards/ezurio/bl654_sensor_board/bl654_sensor_board.dts similarity index 93% rename from boards/lairdconnect/bl654_sensor_board/bl654_sensor_board.dts rename to boards/ezurio/bl654_sensor_board/bl654_sensor_board.dts index c43354f2705..66c589486bf 100644 --- a/boards/lairdconnect/bl654_sensor_board/bl654_sensor_board.dts +++ b/boards/ezurio/bl654_sensor_board/bl654_sensor_board.dts @@ -1,5 +1,6 @@ /* * Copyright (c) 2021 Laird Connectivity + * Copyright (c) 2024 Ezurio * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,8 +11,8 @@ #include / { - model = "Laird BL654 Sensor Board"; - compatible = "lairdconnect,bl654-sensor-board"; + model = "Ezurio BL654 Sensor Board"; + compatible = "ezurio,bl654-sensor-board"; chosen { zephyr,console = &uart0; @@ -52,6 +53,10 @@ }; }; +®1 { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; diff --git a/boards/lairdconnect/bl654_sensor_board/bl654_sensor_board.yaml b/boards/ezurio/bl654_sensor_board/bl654_sensor_board.yaml similarity index 92% rename from boards/lairdconnect/bl654_sensor_board/bl654_sensor_board.yaml rename to boards/ezurio/bl654_sensor_board/bl654_sensor_board.yaml index 856805fbd16..bcaafe5669a 100644 --- a/boards/lairdconnect/bl654_sensor_board/bl654_sensor_board.yaml +++ b/boards/ezurio/bl654_sensor_board/bl654_sensor_board.yaml @@ -17,4 +17,4 @@ supported: - pwm - watchdog - netif:openthread -vendor: lairdconnect +vendor: ezurio diff --git a/boards/lairdconnect/bl654_sensor_board/bl654_sensor_board_defconfig b/boards/ezurio/bl654_sensor_board/bl654_sensor_board_defconfig similarity index 100% rename from boards/lairdconnect/bl654_sensor_board/bl654_sensor_board_defconfig rename to boards/ezurio/bl654_sensor_board/bl654_sensor_board_defconfig diff --git a/boards/lairdconnect/bl654_sensor_board/board.cmake b/boards/ezurio/bl654_sensor_board/board.cmake similarity index 100% rename from boards/lairdconnect/bl654_sensor_board/board.cmake rename to boards/ezurio/bl654_sensor_board/board.cmake diff --git a/boards/ezurio/bl654_sensor_board/board.yml b/boards/ezurio/bl654_sensor_board/board.yml new file mode 100644 index 00000000000..566c992411d --- /dev/null +++ b/boards/ezurio/bl654_sensor_board/board.yml @@ -0,0 +1,5 @@ +board: + name: bl654_sensor_board + vendor: ezurio + socs: + - name: nrf52840 diff --git a/boards/lairdconnect/bl654_sensor_board/doc/bl654_sensor_board.rst b/boards/ezurio/bl654_sensor_board/doc/bl654_sensor_board.rst similarity index 90% rename from boards/lairdconnect/bl654_sensor_board/doc/bl654_sensor_board.rst rename to boards/ezurio/bl654_sensor_board/doc/bl654_sensor_board.rst index c990c934952..32036e38ada 100644 --- a/boards/lairdconnect/bl654_sensor_board/doc/bl654_sensor_board.rst +++ b/boards/ezurio/bl654_sensor_board/doc/bl654_sensor_board.rst @@ -1,12 +1,12 @@ .. _bl654_sensor_board: -Laird Connectivity BL654 Sensor Board -##################################### +Ezurio BL654 Sensor Board +######################### Overview ******** -The BL654 Sensor Board hardware provides support for the Laird Connectivity +The BL654 Sensor Board hardware provides support for the Ezurio BL654 module which is powered by a Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU. @@ -132,7 +132,7 @@ Applications for the ``bl654_sensor_board`` board configuration can be built, flashed, and debugged in the usual way. See :ref:`build_an_application` and :ref:`application_run` for more details on building and running. An external debugger/programmer is required which can be connected to using a Tag-Connect -TC2030-CTX cable, a Laird Connectivity USB-SWD Programmer board or Segger JLink +TC2030-CTX cable, a Ezurio USB-SWD Programmer board or Segger JLink programmer can be used to program and debug the BL654 sensor board. Flashing @@ -142,14 +142,14 @@ If using an external JLink, follow the instructions in the :ref:`nordic_segger` page to install and configure all the necessary software. Further information can be found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more -details). If using a Laird Connectivity USB-SWD Programmer Board, see the +details). If using a Ezurio USB-SWD Programmer Board, see the `pyOCD website`_ to find details about the software and how to install it. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output - note that an external UART is required to be connected to the BL654 sensor board's UART, if -using the Laird Connectivity USB-SWD Programmer Board, the BL654 sensor board +using the Ezurio USB-SWD Programmer Board, the BL654 sensor board can be plugged in to the UART header. An FTDI cable can also be used - the voltage of the I/O lines and power line must be between 1.8v and 3.3v, do not connect an FTDI cable with a 5v power line to the BL654 sensor board. @@ -181,7 +181,7 @@ can be found. For example, under Linux, :code:`/dev/ttyACM0`. The BL654 sensor board needs an external programmer to program it, any SWD programmer which has a 9-pin ARM debug port can be used with a Tag-Connect -TC2030-CTX cable. If using the Laird Connectivity USB-SWD Programmer Board, +TC2030-CTX cable. If using the Ezurio USB-SWD Programmer Board, connect the cable to P1 and ensure the board is set to supply power to the target at 3.3v. @@ -214,7 +214,7 @@ Debugging ========= Refer to the :ref:`nordic_segger` page to learn about debugging Nordic based -boards if using an external JLink debugger. If using a Laird Connectivity +boards if using an external JLink debugger. If using a Ezurio USB-SWD Programmer Board, pyOCD can be used for debugging. Testing Bluetooth on the BL654 Sensor Board @@ -222,9 +222,9 @@ Testing Bluetooth on the BL654 Sensor Board Many of the Bluetooth examples will work on the BL654 Sensor Board. Try them out: -* :ref:`ble_peripheral` -* :ref:`bluetooth-eddystone-sample` -* :ref:`bluetooth-ibeacon-sample` +* :zephyr:code-sample:`ble_peripheral` +* :zephyr:code-sample:`bluetooth_eddystone` +* :zephyr:code-sample:`bluetooth_ibeacon` Testing the LED and button on the BL654 Sensor Board @@ -238,7 +238,7 @@ the board are working properly with Zephyr: You can build and flash the examples to make sure Zephyr is running correctly on your board. The button and LED definitions can be found in -:zephyr_file:`boards/lairdconnect/bl654_sensor_board/bl654_sensor_board.dts`. +:zephyr_file:`boards/ezurio/bl654_sensor_board/bl654_sensor_board.dts`. References @@ -247,6 +247,6 @@ References .. target-notes:: .. _Bosch BME280 sensor website: https://www.bosch-sensortec.com/products/environmental-sensors/humidity-sensors-bme280/ -.. _BL654 website: https://connectivity.lairdtech.com/wireless-modules/bluetooth-modules/bluetooth-5-modules/bl654-series +.. _BL654 website: https://ezurio.com/wireless-modules/bluetooth-modules/bluetooth-5-modules/bl654-series .. _pyOCD website: https://github.com/pyocd/pyOCD -.. _USB-SWD Programmer website: https://www.lairdconnect.com/usb-swd-programmer +.. _USB-SWD Programmer website: https://www.ezurio.com/usb-swd-programmer diff --git a/boards/lairdconnect/bl654_sensor_board/doc/img/bl654_sensor_board.jpg b/boards/ezurio/bl654_sensor_board/doc/img/bl654_sensor_board.jpg similarity index 100% rename from boards/lairdconnect/bl654_sensor_board/doc/img/bl654_sensor_board.jpg rename to boards/ezurio/bl654_sensor_board/doc/img/bl654_sensor_board.jpg diff --git a/boards/lairdconnect/bl654_sensor_board/doc/img/bl654_sensor_board_usb_swd_programmer.jpg b/boards/ezurio/bl654_sensor_board/doc/img/bl654_sensor_board_usb_swd_programmer.jpg similarity index 100% rename from boards/lairdconnect/bl654_sensor_board/doc/img/bl654_sensor_board_usb_swd_programmer.jpg rename to boards/ezurio/bl654_sensor_board/doc/img/bl654_sensor_board_usb_swd_programmer.jpg diff --git a/boards/lairdconnect/bl654_usb/pre_dt_board.cmake b/boards/ezurio/bl654_sensor_board/pre_dt_board.cmake similarity index 100% rename from boards/lairdconnect/bl654_usb/pre_dt_board.cmake rename to boards/ezurio/bl654_sensor_board/pre_dt_board.cmake diff --git a/boards/ezurio/bl654_usb/Kconfig b/boards/ezurio/bl654_usb/Kconfig new file mode 100644 index 00000000000..c9779a44da9 --- /dev/null +++ b/boards/ezurio/bl654_usb/Kconfig @@ -0,0 +1,10 @@ +# BL654 USB adapter board configuration + +# Copyright (c) 2021 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +config BL654_USB_SERIAL_BACKEND_CDCACM + bool "Use CDC ACM UART as backend for BL654 USB adapter" + default y if !USB_DEVICE_BLUETOOTH + help + Use CDC ACM UART as backend for console or shell. diff --git a/boards/lairdconnect/bl654_usb/Kconfig.bl654_usb b/boards/ezurio/bl654_usb/Kconfig.bl654_usb similarity index 100% rename from boards/lairdconnect/bl654_usb/Kconfig.bl654_usb rename to boards/ezurio/bl654_usb/Kconfig.bl654_usb diff --git a/boards/lairdconnect/bl654_usb/Kconfig.defconfig b/boards/ezurio/bl654_usb/Kconfig.defconfig similarity index 100% rename from boards/lairdconnect/bl654_usb/Kconfig.defconfig rename to boards/ezurio/bl654_usb/Kconfig.defconfig diff --git a/boards/lairdconnect/bl654_usb/bl654_usb-pinctrl.dtsi b/boards/ezurio/bl654_usb/bl654_usb-pinctrl.dtsi similarity index 100% rename from boards/lairdconnect/bl654_usb/bl654_usb-pinctrl.dtsi rename to boards/ezurio/bl654_usb/bl654_usb-pinctrl.dtsi diff --git a/boards/lairdconnect/bl654_usb/bl654_usb.dts b/boards/ezurio/bl654_usb/bl654_usb.dts similarity index 93% rename from boards/lairdconnect/bl654_usb/bl654_usb.dts rename to boards/ezurio/bl654_usb/bl654_usb.dts index fa814f4b80e..a6f81f64e61 100644 --- a/boards/lairdconnect/bl654_usb/bl654_usb.dts +++ b/boards/ezurio/bl654_usb/bl654_usb.dts @@ -1,5 +1,6 @@ /* * Copyright (c) 2021 Laird Connectivity + * Copyright (c) 2024 Ezurio * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,8 +10,8 @@ #include "bl654_usb-pinctrl.dtsi" / { - model = "Laird Connectivity BL654 USB adapter"; - compatible = "lairdconnect,bl654_usb"; + model = "Ezurio BL654 USB adapter"; + compatible = "ezurio,bl654_usb"; chosen { zephyr,sram = &sram0; @@ -47,6 +48,10 @@ }; }; +®1 { + regulator-initial-mode = ; +}; + &uicr { gpio-as-nreset; }; diff --git a/boards/lairdconnect/bl654_usb/bl654_usb.yaml b/boards/ezurio/bl654_usb/bl654_usb.yaml similarity index 83% rename from boards/lairdconnect/bl654_usb/bl654_usb.yaml rename to boards/ezurio/bl654_usb/bl654_usb.yaml index 620275a516d..4bf396760cc 100644 --- a/boards/lairdconnect/bl654_usb/bl654_usb.yaml +++ b/boards/ezurio/bl654_usb/bl654_usb.yaml @@ -8,9 +8,8 @@ toolchain: - xtools supported: - usb_device - - usb_cdc - ble - pwm - watchdog - counter -vendor: lairdconnect +vendor: ezurio diff --git a/boards/lairdconnect/bl654_usb/bl654_usb_defconfig b/boards/ezurio/bl654_usb/bl654_usb_defconfig similarity index 100% rename from boards/lairdconnect/bl654_usb/bl654_usb_defconfig rename to boards/ezurio/bl654_usb/bl654_usb_defconfig diff --git a/boards/ezurio/bl654_usb/board.yml b/boards/ezurio/bl654_usb/board.yml new file mode 100644 index 00000000000..13642fbe712 --- /dev/null +++ b/boards/ezurio/bl654_usb/board.yml @@ -0,0 +1,5 @@ +board: + name: bl654_usb + vendor: ezurio + socs: + - name: nrf52840 diff --git a/boards/lairdconnect/bl654_usb/doc/bl654_usb.rst b/boards/ezurio/bl654_usb/doc/bl654_usb.rst similarity index 84% rename from boards/lairdconnect/bl654_usb/doc/bl654_usb.rst rename to boards/ezurio/bl654_usb/doc/bl654_usb.rst index 3bb3139b615..c2ba1a23698 100644 --- a/boards/lairdconnect/bl654_usb/doc/bl654_usb.rst +++ b/boards/ezurio/bl654_usb/doc/bl654_usb.rst @@ -1,13 +1,13 @@ .. _bl654_usb: -Laird Connectivity BL654 USB (451-00004) -######################################## +Ezurio BL654 USB (451-00004) +############################ Overview ******** -The BL654 USB adapter hardware (Laird Connectivity part 451-00004) provides -support for the Laird Connectivity BL654 module powered by a Nordic +The BL654 USB adapter hardware (Ezurio part 451-00004) provides +support for the Ezurio BL654 module powered by a Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU. This USB adapter has the following features: @@ -105,14 +105,14 @@ Applications for the ``bl654_usb`` board configuration can be built in the usual way (see :ref:`build_an_application` for more details). The ``bl654_usb`` board cannot be used for debugging. The compatible BL654 DVK board can be used for development. Documentation can be found at the :ref:`bl654_dvk` -site and :zephyr_file:`boards/lairdconnect/bl654_dvk/doc/bl654_dvk.rst` +site and :zephyr_file:`boards/ezurio/bl654_dvk/doc/bl654_dvk.rst` Flashing ======== The board supports programming using the built-in bootloader. -The board is factory-programmed with a Laird Connectivity variation of Nordic's +The board is factory-programmed with a Ezurio variation of Nordic's open bootloader from Nordic's nRF5x SDK. With this option, you'll use Nordic's `nrfutil`_ program to create firmware packages supported by this bootloader and flash them to the device. Make sure ``nrfutil`` is installed @@ -160,9 +160,9 @@ Testing Bluetooth on the BL654 USB Many of the Bluetooth examples will work on the BL654 USB. Try them out: -* :ref:`ble_peripheral` -* :ref:`bluetooth-eddystone-sample` -* :ref:`bluetooth-ibeacon-sample` +* :zephyr:code-sample:`ble_peripheral` +* :zephyr:code-sample:`bluetooth_eddystone` +* :zephyr:code-sample:`bluetooth_ibeacon` Testing the LED on the BL654 USB @@ -175,7 +175,7 @@ the board is working properly with Zephyr: You can build and flash the example to make sure Zephyr is running correctly on your board. The LED definitions can be found in -:zephyr_file:`boards/lairdconnect/bl654_usb/bl654_usb.dts`. +:zephyr_file:`boards/ezurio/bl654_usb/bl654_usb.dts`. References @@ -183,8 +183,8 @@ References .. target-notes:: -.. _BL654 USB Dongle Quick Start Guide: https://www.lairdconnect.com/documentation/user-guide-bl654-usb-nordic-sdk-zephyr -.. _BL654 website: https://connectivity.lairdtech.com/wireless-modules/bluetooth-modules/bluetooth-5-modules/bl654-series +.. _BL654 USB Dongle Quick Start Guide: https://www.ezurio.com/documentation/user-guide-bl654-usb-nordic-sdk-zephyr +.. _BL654 website: https://ezurio.com/wireless-modules/bluetooth-modules/bluetooth-5-modules/bl654-series .. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html -.. _Creating a secure bootloader image: https://www.lairdconnect.com/documentation/application-note-creating-secure-bootloader-image-bl654-usb +.. _Creating a secure bootloader image: https://www.ezurio.com/documentation/application-note-creating-secure-bootloader-image-bl654-usb .. _nrfutil: https://github.com/NordicSemiconductor/pc-nrfutil diff --git a/boards/lairdconnect/bl654_usb/doc/img/bl654_usb.jpg b/boards/ezurio/bl654_usb/doc/img/bl654_usb.jpg similarity index 100% rename from boards/lairdconnect/bl654_usb/doc/img/bl654_usb.jpg rename to boards/ezurio/bl654_usb/doc/img/bl654_usb.jpg diff --git a/boards/lairdconnect/bl654_usb/doc/img/bl654_usb_pcb.jpg b/boards/ezurio/bl654_usb/doc/img/bl654_usb_pcb.jpg similarity index 100% rename from boards/lairdconnect/bl654_usb/doc/img/bl654_usb_pcb.jpg rename to boards/ezurio/bl654_usb/doc/img/bl654_usb_pcb.jpg diff --git a/boards/lairdconnect/bl654_usb/doc/img/bl654_usb_reset.jpg b/boards/ezurio/bl654_usb/doc/img/bl654_usb_reset.jpg similarity index 100% rename from boards/lairdconnect/bl654_usb/doc/img/bl654_usb_reset.jpg rename to boards/ezurio/bl654_usb/doc/img/bl654_usb_reset.jpg diff --git a/boards/lairdconnect/bt510/pre_dt_board.cmake b/boards/ezurio/bl654_usb/pre_dt_board.cmake similarity index 100% rename from boards/lairdconnect/bt510/pre_dt_board.cmake rename to boards/ezurio/bl654_usb/pre_dt_board.cmake diff --git a/boards/lairdconnect/bt510/Kconfig.bt510 b/boards/ezurio/bt510/Kconfig.bt510 similarity index 100% rename from boards/lairdconnect/bt510/Kconfig.bt510 rename to boards/ezurio/bt510/Kconfig.bt510 diff --git a/boards/lairdconnect/bt510/Kconfig.defconfig b/boards/ezurio/bt510/Kconfig.defconfig similarity index 100% rename from boards/lairdconnect/bt510/Kconfig.defconfig rename to boards/ezurio/bt510/Kconfig.defconfig diff --git a/boards/lairdconnect/bt510/board.cmake b/boards/ezurio/bt510/board.cmake similarity index 100% rename from boards/lairdconnect/bt510/board.cmake rename to boards/ezurio/bt510/board.cmake diff --git a/boards/ezurio/bt510/board.yml b/boards/ezurio/bt510/board.yml new file mode 100644 index 00000000000..e4692ed4526 --- /dev/null +++ b/boards/ezurio/bt510/board.yml @@ -0,0 +1,5 @@ +board: + name: bt510 + vendor: ezurio + socs: + - name: nrf52840 diff --git a/boards/lairdconnect/bt510/bt510-pinctrl.dtsi b/boards/ezurio/bt510/bt510-pinctrl.dtsi similarity index 100% rename from boards/lairdconnect/bt510/bt510-pinctrl.dtsi rename to boards/ezurio/bt510/bt510-pinctrl.dtsi diff --git a/boards/lairdconnect/bt510/bt510.dts b/boards/ezurio/bt510/bt510.dts similarity index 95% rename from boards/lairdconnect/bt510/bt510.dts rename to boards/ezurio/bt510/bt510.dts index 984b098e5d5..ddfc15e470b 100644 --- a/boards/lairdconnect/bt510/bt510.dts +++ b/boards/ezurio/bt510/bt510.dts @@ -1,5 +1,6 @@ /* * Copyright (c) 2020 Laird Connectivity + * Copyright (c) 2024 Ezurio * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,8 +11,8 @@ #include / { - model = "Laird Sentrius BT510 Sensor"; - compatible = "lairdconnect,bt510"; + model = "Ezurio Sentrius BT510 Sensor"; + compatible = "ezurio,bt510"; chosen { zephyr,console = &uart0; @@ -68,6 +69,10 @@ }; }; +®1 { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; diff --git a/boards/lairdconnect/bt510/bt510.yaml b/boards/ezurio/bt510/bt510.yaml similarity index 88% rename from boards/lairdconnect/bt510/bt510.yaml rename to boards/ezurio/bt510/bt510.yaml index c9b6823d188..198b538eecd 100644 --- a/boards/lairdconnect/bt510/bt510.yaml +++ b/boards/ezurio/bt510/bt510.yaml @@ -13,4 +13,4 @@ supported: - watchdog - i2c - sm351lt -vendor: lairdconnect +vendor: ezurio diff --git a/boards/lairdconnect/bt510/bt510_defconfig b/boards/ezurio/bt510/bt510_defconfig similarity index 100% rename from boards/lairdconnect/bt510/bt510_defconfig rename to boards/ezurio/bt510/bt510_defconfig diff --git a/boards/lairdconnect/bt510/doc/bt510.rst b/boards/ezurio/bt510/doc/bt510.rst similarity index 93% rename from boards/lairdconnect/bt510/doc/bt510.rst rename to boards/ezurio/bt510/doc/bt510.rst index 13459f69ea7..bcdaf272265 100644 --- a/boards/lairdconnect/bt510/doc/bt510.rst +++ b/boards/ezurio/bt510/doc/bt510.rst @@ -1,7 +1,7 @@ .. _bt510: -Laird Connectivity Sentrius BT510 Sensor -######################################## +Ezurio Sentrius BT510 Sensor +############################ Overview ******** @@ -162,7 +162,7 @@ A non-standard layout is used to include access to the sensor debug UART. Connectivity to the programmer/debugger must be modified to match the pinout shown above. -Laird Connectivity provide the USB-SWD programming board (750-03239) that supports +Ezurio provide the USB-SWD programming board (750-03239) that supports this connector layout, refer to the `USB SWD Programmer product page`_ . @@ -187,7 +187,7 @@ Then build and flash applications as usual (see :ref:`build_an_application` and $ ninja flash -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. @@ -228,9 +228,9 @@ Testing Bluetooth on the BT510 Many of the Bluetooth examples will work on the BT510. Try them out: -* :ref:`ble_peripheral` -* :ref:`bluetooth-eddystone-sample` -* :ref:`bluetooth-ibeacon-sample` +* :zephyr:code-sample:`ble_peripheral` +* :zephyr:code-sample:`bluetooth_eddystone` +* :zephyr:code-sample:`bluetooth_ibeacon` Testing the LEDs and buttons on the BT510 @@ -244,7 +244,7 @@ the board are working properly with Zephyr: You can build and flash the examples to make sure Zephyr is running correctly on your board. The button, LED and sensor device definitions can be found in -:zephyr_file:`boards/lairdconnect/bt510/bt510.dts`. +:zephyr_file:`boards/ezurio/bt510/bt510.dts`. References @@ -252,9 +252,9 @@ References .. target-notes:: -.. _Sentrius BT510 website: https://www.lairdconnect.com/iot-devices/iot-sensors/bt510-bluetooth-5-long-range-ip67-multi-sensor +.. _Sentrius BT510 website: https://www.ezurio.com/iot-devices/iot-sensors/bt510-bluetooth-5-long-range-ip67-multi-sensor .. _TagConnect TC2050 product page: https://www.tag-connect.com/product/tc2050-idc-050 -.. _USB SWD Programmer product page: https://www.lairdconnect.com/wireless-modules/programming-kits/usb-swd-programming-kit +.. _USB SWD Programmer product page: https://www.ezurio.com/wireless-modules/programming-kits/usb-swd-programming-kit .. _MAX3232 datasheet: https://www.ti.com/lit/ds/symlink/max3232.pdf .. _Silabs 7055 datasheet: https://www.silabs.com/documents/public/data-sheets/Si7050-1-3-4-5-A20.pdf .. _ST Microelectronics LIS2DH datasheet: https://www.st.com/resource/en/datasheet/lis2dh.pdf diff --git a/boards/lairdconnect/bt510/doc/img/bt510.jpg b/boards/ezurio/bt510/doc/img/bt510.jpg similarity index 100% rename from boards/lairdconnect/bt510/doc/img/bt510.jpg rename to boards/ezurio/bt510/doc/img/bt510.jpg diff --git a/boards/lairdconnect/bt510/doc/img/bt510_back.jpg b/boards/ezurio/bt510/doc/img/bt510_back.jpg similarity index 100% rename from boards/lairdconnect/bt510/doc/img/bt510_back.jpg rename to boards/ezurio/bt510/doc/img/bt510_back.jpg diff --git a/boards/lairdconnect/bt510/doc/img/bt510_prog.jpg b/boards/ezurio/bt510/doc/img/bt510_prog.jpg similarity index 100% rename from boards/lairdconnect/bt510/doc/img/bt510_prog.jpg rename to boards/ezurio/bt510/doc/img/bt510_prog.jpg diff --git a/boards/lairdconnect/bt610/pre_dt_board.cmake b/boards/ezurio/bt510/pre_dt_board.cmake similarity index 100% rename from boards/lairdconnect/bt610/pre_dt_board.cmake rename to boards/ezurio/bt510/pre_dt_board.cmake diff --git a/boards/lairdconnect/bt610/Kconfig.bt610 b/boards/ezurio/bt610/Kconfig.bt610 similarity index 100% rename from boards/lairdconnect/bt610/Kconfig.bt610 rename to boards/ezurio/bt610/Kconfig.bt610 diff --git a/boards/lairdconnect/bt610/Kconfig.defconfig b/boards/ezurio/bt610/Kconfig.defconfig similarity index 100% rename from boards/lairdconnect/bt610/Kconfig.defconfig rename to boards/ezurio/bt610/Kconfig.defconfig diff --git a/boards/lairdconnect/bt610/board.cmake b/boards/ezurio/bt610/board.cmake similarity index 100% rename from boards/lairdconnect/bt610/board.cmake rename to boards/ezurio/bt610/board.cmake diff --git a/boards/ezurio/bt610/board.yml b/boards/ezurio/bt610/board.yml new file mode 100644 index 00000000000..0e4f29742c5 --- /dev/null +++ b/boards/ezurio/bt610/board.yml @@ -0,0 +1,5 @@ +board: + name: bt610 + vendor: ezurio + socs: + - name: nrf52840 diff --git a/boards/lairdconnect/bt610/bt610-pinctrl.dtsi b/boards/ezurio/bt610/bt610-pinctrl.dtsi similarity index 100% rename from boards/lairdconnect/bt610/bt610-pinctrl.dtsi rename to boards/ezurio/bt610/bt610-pinctrl.dtsi diff --git a/boards/lairdconnect/bt610/bt610.dts b/boards/ezurio/bt610/bt610.dts similarity index 97% rename from boards/lairdconnect/bt610/bt610.dts rename to boards/ezurio/bt610/bt610.dts index c6b9bad9910..abf34ed11fc 100644 --- a/boards/lairdconnect/bt610/bt610.dts +++ b/boards/ezurio/bt610/bt610.dts @@ -1,5 +1,6 @@ /* * Copyright (c) 2021 Laird Connectivity + * Copyright (c) 2024 Ezurio * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,8 +11,8 @@ #include / { - model = "Laird BT610 Sensor"; - compatible = "lairdconnect,bt610"; + model = "Ezurio BT610 Sensor"; + compatible = "ezurio,bt610"; chosen { zephyr,console = &uart0; @@ -77,7 +78,6 @@ mcuboot-button0 = &button1; mcuboot-led0 = &led1; watchdog0 = &wdt0; - spi-flash0 = &mx25r64; }; mag1: mag_1 { @@ -122,6 +122,10 @@ }; }; +®1 { + regulator-initial-mode = ; +}; + &pwm0 { status = "okay"; pinctrl-0 = <&pwm0_default>; diff --git a/boards/lairdconnect/bt610/bt610.yaml b/boards/ezurio/bt610/bt610.yaml similarity index 91% rename from boards/lairdconnect/bt610/bt610.yaml rename to boards/ezurio/bt610/bt610.yaml index 80cbe9975da..5b96d98c527 100644 --- a/boards/lairdconnect/bt610/bt610.yaml +++ b/boards/ezurio/bt610/bt610.yaml @@ -19,4 +19,4 @@ supported: - counter - sm351lt - qspi -vendor: lairdconnect +vendor: ezurio diff --git a/boards/lairdconnect/bt610/bt610_defconfig b/boards/ezurio/bt610/bt610_defconfig similarity index 100% rename from boards/lairdconnect/bt610/bt610_defconfig rename to boards/ezurio/bt610/bt610_defconfig diff --git a/boards/lairdconnect/bt610/doc/bt610.rst b/boards/ezurio/bt610/doc/bt610.rst similarity index 98% rename from boards/lairdconnect/bt610/doc/bt610.rst rename to boards/ezurio/bt610/doc/bt610.rst index baf9827e3d6..528186ec880 100644 --- a/boards/lairdconnect/bt610/doc/bt610.rst +++ b/boards/ezurio/bt610/doc/bt610.rst @@ -1,7 +1,7 @@ .. _bt610: -Laird Connectivity Sentrius BT610 Sensor -######################################## +Ezurio Sentrius BT610 Sensor +############################ Overview ******** @@ -545,7 +545,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. @@ -582,9 +582,9 @@ Testing Bluetooth on the BT610 Many of the Bluetooth examples will work on the BT610. Try them out: -* :ref:`ble_peripheral` -* :ref:`bluetooth-eddystone-sample` -* :ref:`bluetooth-ibeacon-sample` +* :zephyr:code-sample:`ble_peripheral` +* :zephyr:code-sample:`bluetooth_eddystone` +* :zephyr:code-sample:`bluetooth_ibeacon` Testing the LEDs and buttons on the BT610 @@ -598,7 +598,7 @@ on the board are working properly with Zephyr: You can build and flash the examples to make sure Zephyr is running correctly on your board. The button, LED and sensor device definitions can be found in -:zephyr_file:`boards/lairdconnect/bt610/bt610.dts`. +:zephyr_file:`boards/ezurio/bt610/bt610.dts`. References @@ -606,10 +606,10 @@ References .. target-notes:: -.. _Sentrius BT610 website: https://www.lairdconnect.com/iot-devices/iot-sensors/sentrius-bt610-io-sensor +.. _Sentrius BT610 website: https://www.ezurio.com/iot-devices/iot-sensors/sentrius-bt610-io-sensor .. _Honeywell SM351LT datasheet: https://sensing.honeywell.com/honeywell-sensing-nanopower-series-datasheet-50095501-c-en.pdf .. _MAX3232 datasheet: https://www.ti.com/lit/ds/symlink/max3232.pdf .. _TI TMUX1204 datasheet: https://www.ti.com/lit/gpn/TMUX1204 .. _TI TCA9538 datasheet: https://www.ti.com/lit/gpn/TCA9538 .. _Macronix MX25R6435FZNIL0 datasheet: https://www.macronix.com/Lists/Datasheet/Attachments/7913/MX25R6435F,%20Wide%20Range,%2064Mb,%20v1.5.pdf -.. _BT610 Zephyr Application Thermistor Calibration: https://www.lairdconnect.com/technology/bt610-thermistor-coefficient-calculator +.. _BT610 Zephyr Application Thermistor Calibration: https://www.ezurio.com/technology/bt610-thermistor-coefficient-calculator diff --git a/boards/lairdconnect/bt610/doc/img/bt610_back.jpg b/boards/ezurio/bt610/doc/img/bt610_back.jpg similarity index 100% rename from boards/lairdconnect/bt610/doc/img/bt610_back.jpg rename to boards/ezurio/bt610/doc/img/bt610_back.jpg diff --git a/boards/lairdconnect/bt610/doc/img/bt610_board.jpg b/boards/ezurio/bt610/doc/img/bt610_board.jpg similarity index 100% rename from boards/lairdconnect/bt610/doc/img/bt610_board.jpg rename to boards/ezurio/bt610/doc/img/bt610_board.jpg diff --git a/boards/lairdconnect/bt610/doc/img/bt610_front.jpg b/boards/ezurio/bt610/doc/img/bt610_front.jpg similarity index 100% rename from boards/lairdconnect/bt610/doc/img/bt610_front.jpg rename to boards/ezurio/bt610/doc/img/bt610_front.jpg diff --git a/boards/lairdconnect/mg100/pre_dt_board.cmake b/boards/ezurio/bt610/pre_dt_board.cmake similarity index 100% rename from boards/lairdconnect/mg100/pre_dt_board.cmake rename to boards/ezurio/bt610/pre_dt_board.cmake diff --git a/boards/ezurio/index.rst b/boards/ezurio/index.rst new file mode 100644 index 00000000000..5352513a1f3 --- /dev/null +++ b/boards/ezurio/index.rst @@ -0,0 +1,10 @@ +.. _boards-ezurio: + +Ezurio +################## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/ezurio/mg100/Kconfig.defconfig b/boards/ezurio/mg100/Kconfig.defconfig new file mode 100644 index 00000000000..0db2eee8478 --- /dev/null +++ b/boards/ezurio/mg100/Kconfig.defconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2022 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MG100 + +config MODEM + default NETWORKING + +config MODEM_HL7800 + default NETWORKING + +config NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE + default 4096 + +config REGULATOR + default DISK_DRIVER_SDMMC + +config BT_CTLR + default BT + +endif # BOARD_MG100 diff --git a/boards/lairdconnect/mg100/Kconfig.mg100 b/boards/ezurio/mg100/Kconfig.mg100 similarity index 100% rename from boards/lairdconnect/mg100/Kconfig.mg100 rename to boards/ezurio/mg100/Kconfig.mg100 diff --git a/boards/lairdconnect/mg100/board.cmake b/boards/ezurio/mg100/board.cmake similarity index 100% rename from boards/lairdconnect/mg100/board.cmake rename to boards/ezurio/mg100/board.cmake diff --git a/boards/ezurio/mg100/board.yml b/boards/ezurio/mg100/board.yml new file mode 100644 index 00000000000..4c62320fc5e --- /dev/null +++ b/boards/ezurio/mg100/board.yml @@ -0,0 +1,5 @@ +board: + name: mg100 + vendor: ezurio + socs: + - name: nrf52840 diff --git a/boards/lairdconnect/mg100/doc/img/mg100.jpg b/boards/ezurio/mg100/doc/img/mg100.jpg similarity index 100% rename from boards/lairdconnect/mg100/doc/img/mg100.jpg rename to boards/ezurio/mg100/doc/img/mg100.jpg diff --git a/boards/ezurio/mg100/doc/index.rst b/boards/ezurio/mg100/doc/index.rst new file mode 100644 index 00000000000..86b92c52abf --- /dev/null +++ b/boards/ezurio/mg100/doc/index.rst @@ -0,0 +1,248 @@ +.. _mg100: + +Ezurio Sentrius™ MG100 Gateway +############################## + +Overview +******** +The Sentrius™ MG100 Gateway offers a compact, out of box Bluetooth to low power cellular gateway +solution. + +Based on the Pinnacle 100 socket modem, the Sentrius™ MG100 gateway captures data from any +Bluetooth 5 modules or devices and sends it to the cloud via a global low power cellular +(LTE-M/NB-IoT) connection. The MG100 seamlessly incorporates a powerful Cortex M4F controller, +full Bluetooth 5 connectivity, and dual-mode LTE-M/NB-IoT capabilities. The MG100 has full regulatory +and network certifications and End Device carrier approvals. + +Develop your application directly on the integrated Cortex M4F microcontroller using Zephyr RTOS, +enabling your application development with a secure, open source RTOS with more than just kernel +services. Remotely debug your fleet of devices with the `Memfault Platform`_. Take advantage of the +Zephyr community and Ezurio’s `Canvas Software Suite`_ to accelerate your development. +covering all aspects of the product's capabilities and hardware interfaces. The MG100 also delivers +complete antenna flexibility with internal or external antenna options available, and the optional +battery backup provides uninterrupted reporting of remote Bluetooth sensor data. + +More information about the board can be found at the `MG100 website`_. + +The MG100 hardware provides support for the Nordic Semiconductor `nRF52840`_ ARM Cortex-M4F CPU, +`Sierra Wireless HL7800`_ +and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` +* :abbr:`QSPI (Quad Serial Peripheral Interface)` +* :abbr:`LIS3DH (ST Micro 3-axis MEMS accelerometer)` +* :abbr:`HL7800 (Sierra Wireless HL7800 LTE-M1/NB-IoT modem)` +* :abbr:`SD Card` + +.. figure:: img/mg100.jpg + :align: center + :alt: MG100 + + MG100 (450-00054-K1) + +Hardware +******** + +Supported Features +================== + +The MG100 board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ +| QSPI | on-chip | qspi/MX25R64(8MB) | ++-----------+------------+----------------------+ +| LIS3DH | I2C(M) | sensor/lis3dh | ++-----------+------------+----------------------+ +| HL7800 | UART | HL7800 modem driver | ++-----------+------------+----------------------+ +| SDMMC | SPI(M) | SD Card via SPI | ++-----------+------------+----------------------+ + +See `MG100 website`_ for a complete list +of MG100 hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (red) = P1.7 +* LED2 (blue) = P1.6 +* LED3 (green) = P1.5 + +Push buttons +------------ + +* BUTTON1 = P0.3 + +External flash memory +--------------------- + +A 64Mbit external flash memory part is available for storage of application +images and data. Refer to the `Macronix MX25R6435F datasheet`_ for further +details. + +The flash memory is connected to the on-board QSPI device controller. + +* MX25R64 = QSPI + +SCK = P0.19 +IO0 = P0.20 +IO1 = P0.21 +IO2 = P0.22 +IO3 = P0.23 +CSN = P0.17 + +LIS3DH Motion Sensor +-------------------- + +Motion sensor to detect if the gateway moves. + +IRQ IO = P0.28 +I2C SDA = P0.26 +I2C SCL = P0.27 + +SD Card +------- + +SD card used to store large amounts of data. + +SPI CS = P0.29 +SPI SCK = P1.09 +SPI MOSI = P0.11 +SPI MISO = P0.12 + +Programming and Debugging +************************* + +Applications for the ``mg100`` board configuration can be +built and flashed in the usual way. (see :ref:`build_an_application` +and :ref:`application_run` for more details) + +The `Ezurio USB-SWD Programming Kit`_ contains all the necessary +hardware to enable programming and debugging an MG100. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. note:: On the MG100, + the USB connector should be used to access the UART console. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board MG100 +can be found. For example, under Linux, :code:`/dev/ttyUSB0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mg100 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + +Software +******** + +Canvas Software Suite +============================== +The MG100 is a supported hardware platform for `Canvas Software Suite`_. + +Testing Bluetooth on the MG100 +============================== +Many of the Bluetooth examples will work on the MG100. +Try them out: + +* :zephyr:code-sample:`ble_peripheral` +* :zephyr:code-sample:`bluetooth_eddystone` +* :zephyr:code-sample:`bluetooth_ibeacon` + +Testing the LEDs and buttons in the MG100 +==================================================== + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/ezurio/mg100/mg100.dts`. + +References +********** + +.. target-notes:: + +.. _MG100 website: https://www.ezurio.com/iot-devices/iot-gateways/sentrius-mg100-gateway-lte-mnb-iot-and-bluetooth-5 +.. _nRF52840 Product Specification: https://infocenter.nordicsemi.com/pdf/nRF52840_PS_v1.1.pdf +.. _Sierra Wireless HL7800: https://source.sierrawireless.com/devices/hl-series/hl7800/#sthash.641qTTwA.dpbs +.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html +.. _Macronix MX25R6435F datasheet: https://www.macronix.com/Lists/Datasheet/Attachments/7913/MX25R6435F,%20Wide%20Range,%2064Mb,%20v1.5.pdf +.. _Ezurio USB-SWD Programming Kit: https://www.ezurio.com/wireless-modules/programming-kits/usb-swd-programming-kit +.. _Memfault Platform: https://docs.memfault.com/docs/mcu/pinnacle-100-guide +.. _nRF52840: https://www.nordicsemi.com/products/nrf52840 +.. _Canvas Software Suite: https://www.ezurio.com/canvas/software-suite diff --git a/boards/lairdconnect/mg100/mg100-pinctrl.dtsi b/boards/ezurio/mg100/mg100-pinctrl.dtsi similarity index 100% rename from boards/lairdconnect/mg100/mg100-pinctrl.dtsi rename to boards/ezurio/mg100/mg100-pinctrl.dtsi diff --git a/boards/lairdconnect/mg100/mg100.dts b/boards/ezurio/mg100/mg100.dts similarity index 97% rename from boards/lairdconnect/mg100/mg100.dts rename to boards/ezurio/mg100/mg100.dts index 7c6fbb92d24..de091a3ab66 100644 --- a/boards/lairdconnect/mg100/mg100.dts +++ b/boards/ezurio/mg100/mg100.dts @@ -1,5 +1,6 @@ /* * Copyright (c) 2022 Laird Connectivity + * Copyright (c) 2024 Ezurio * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,7 +12,7 @@ / { model = "MG100"; - compatible = "lairdconnect,mg100"; + compatible = "ezurio,mg100"; chosen { zephyr,console = &uart0; @@ -65,10 +66,13 @@ mcuboot-button0 = &button1; mcuboot-led0 = &led1; watchdog0 = &wdt0; - spi-flash0 = &mx25r64; }; }; +®1 { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; diff --git a/boards/lairdconnect/mg100/mg100.yaml b/boards/ezurio/mg100/mg100.yaml similarity index 91% rename from boards/lairdconnect/mg100/mg100.yaml rename to boards/ezurio/mg100/mg100.yaml index 917eb7f0d86..54de18e63ee 100644 --- a/boards/lairdconnect/mg100/mg100.yaml +++ b/boards/ezurio/mg100/mg100.yaml @@ -18,4 +18,4 @@ supported: - spi - watchdog - netif:modem -vendor: lairdconnect +vendor: ezurio diff --git a/boards/lairdconnect/mg100/mg100_defconfig b/boards/ezurio/mg100/mg100_defconfig similarity index 100% rename from boards/lairdconnect/mg100/mg100_defconfig rename to boards/ezurio/mg100/mg100_defconfig diff --git a/boards/lairdconnect/pinnacle_100_dvk/pre_dt_board.cmake b/boards/ezurio/mg100/pre_dt_board.cmake similarity index 100% rename from boards/lairdconnect/pinnacle_100_dvk/pre_dt_board.cmake rename to boards/ezurio/mg100/pre_dt_board.cmake diff --git a/boards/ezurio/pinnacle_100_dvk/Kconfig.defconfig b/boards/ezurio/pinnacle_100_dvk/Kconfig.defconfig new file mode 100644 index 00000000000..c53ec05d15a --- /dev/null +++ b/boards/ezurio/pinnacle_100_dvk/Kconfig.defconfig @@ -0,0 +1,20 @@ +# Pinnacle(TM) 100 DVK board configuration + +# Copyright (c) 2019 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_PINNACLE_100_DVK + +config MODEM + default NETWORKING + +config MODEM_HL7800 + default NETWORKING + +config NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE + default 4096 + +config BT_CTLR + default BT + +endif # BOARD_PINNACLE_100_DVK diff --git a/boards/lairdconnect/pinnacle_100_dvk/Kconfig.pinnacle_100_dvk b/boards/ezurio/pinnacle_100_dvk/Kconfig.pinnacle_100_dvk similarity index 100% rename from boards/lairdconnect/pinnacle_100_dvk/Kconfig.pinnacle_100_dvk rename to boards/ezurio/pinnacle_100_dvk/Kconfig.pinnacle_100_dvk diff --git a/boards/lairdconnect/pinnacle_100_dvk/board.cmake b/boards/ezurio/pinnacle_100_dvk/board.cmake similarity index 100% rename from boards/lairdconnect/pinnacle_100_dvk/board.cmake rename to boards/ezurio/pinnacle_100_dvk/board.cmake diff --git a/boards/ezurio/pinnacle_100_dvk/board.yml b/boards/ezurio/pinnacle_100_dvk/board.yml new file mode 100644 index 00000000000..8ed639a9a0a --- /dev/null +++ b/boards/ezurio/pinnacle_100_dvk/board.yml @@ -0,0 +1,5 @@ +board: + name: pinnacle_100_dvk + vendor: ezurio + socs: + - name: nrf52840 diff --git a/boards/lairdconnect/pinnacle_100_dvk/doc/img/pinnacle_100_dvk.jpg b/boards/ezurio/pinnacle_100_dvk/doc/img/pinnacle_100_dvk.jpg similarity index 100% rename from boards/lairdconnect/pinnacle_100_dvk/doc/img/pinnacle_100_dvk.jpg rename to boards/ezurio/pinnacle_100_dvk/doc/img/pinnacle_100_dvk.jpg diff --git a/boards/ezurio/pinnacle_100_dvk/doc/index.rst b/boards/ezurio/pinnacle_100_dvk/doc/index.rst new file mode 100644 index 00000000000..7b63ada033b --- /dev/null +++ b/boards/ezurio/pinnacle_100_dvk/doc/index.rst @@ -0,0 +1,219 @@ +.. _pinnacle_100_dvk: + +Ezurio Pinnacle 100 DVK +####################### + +Overview +******** +The Pinnacle™ 100 cellular modem seamlessly incorporates a powerful Cortex M4F +controller, full Bluetooth 5 and LTE-M/NB-IoT capabilities – all with full +regulatory certifications and LTE carrier approvals. The Pinnacle 100 also +delivers complete antenna flexibility, with pre-integrated internal or external +antenna options such as the Revie Flex family of LTE and NB-IoT +internal antennas. + +Develop your application directly on the M4F controller using Zephyr RTOS to +cut BOM costs and power consumption. Take advantage of the Zephyr community, +Ezurio’s sample code (cellular, Bluetooth) and hardware interfaces, +or use our hosted mode AT commands set firmware. + +Extremely power conscious, the Pinnacle 100 is ideal for battery-powered +devices operating at the edge of your IoT networks, seamlessly bridging the +cellular WAN to BLE. It’s never been easier to bridge wireless +Bluetooth 5 sensor data to cloud services like AWS IoT over a +low-power LTE connection. + +More information about the board can be found at the `Pinnacle 100 website`_. + +The Pinnacle 100 Development Kit (453-00010-K1 or 453-00011-K1) hardware +provides support for the +Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU, `Sierra Wireless HL7800`_ (Altair ALT1250) +and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` +* :abbr:`QSPI (Quad Serial Peripheral Interface)` +* :abbr:`BME680 (Bosch Sensortec BME680 environmental sensor)` +* :abbr:`HL7800 (Sierra Wireless HL7800 LTE-M1/NB-IoT modem)` + +.. figure:: img/pinnacle_100_dvk.jpg + :align: center + :alt: Pinnacle 100 DVK + + Pinnacle 100 DVK (453-00010-K1) + +Hardware +******** + +Supported Features +================== + +The Pinnacle 100 development board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ +| QSPI | on-chip | qspi/MX25R64(8MB) | ++-----------+------------+----------------------+ +| BME680 | I2C(M) | sensor/bme680 | ++-----------+------------+----------------------+ +| HL7800 | UART | HL7800 modem driver | ++-----------+------------+----------------------+ + +See `Pinnacle 100 website`_ for a complete list +of Pinnacle 100 Development Kit hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (blue) = P1.4 +* LED2 (green) = P1.5 +* LED3 (red) = P1.6 +* LED4 (green) = P1.7 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.31 +* BUTTON2 = SW2 = P0.3 +* BUTTON3 = SW3 = P0.4 +* BUTTON4 = SW4 = P0.2 +* NRF RESET = SW5 = reset + +Programming and Debugging +************************* + +Applications for the ``pinnacle_100_dvk`` board configuration can be +built and flashed in the usual way. (see :ref:`build_an_application` +and :ref:`application_run` for more details) + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. note:: On the Pinnacle 100 development board, + the FTDI USB should be used to access the UART console. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board Pinnacle 100 DVK +can be found. For example, under Linux, :code:`/dev/ttyUSB0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: pinnacle_100_dvk + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + +Software +******** + +Canvas Software Suite +============================== +The Pinnacle 100 is a supported hardware platform for `Canvas Software Suite`_. + +Sample Applications +=================== +`Pinnacle 100 Sample Applications`_ are available. + +Testing Bluetooth on the Pinnacle 100 DVK +========================================= +Many of the Bluetooth examples will work on the Pinnacle 100 DVK. +Try them out: + +* :zephyr:code-sample:`ble_peripheral` +* :zephyr:code-sample:`bluetooth_eddystone` +* :zephyr:code-sample:`bluetooth_ibeacon` + +Testing the LEDs and buttons in the Pinnacle 100 DVK +==================================================== + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/ezurio/pinnacle_100_dvk/pinnacle_100_dvk.dts`. + +References +********** + +.. target-notes:: + +.. _Pinnacle 100 website: https://www.ezurio.com/wireless-modules/cellular-solutions/pinnacle-100-cellular-modem +.. _nRF52840 Product Specification: https://infocenter.nordicsemi.com/pdf/nRF52840_PS_v1.1.pdf +.. _Sierra Wireless HL7800: https://source.sierrawireless.com/devices/hl-series/hl7800/#sthash.641qTTwA.dpbs +.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html +.. _Pinnacle 100 Sample Applications: https://github.com/LairdCP/Pinnacle_100_Sample_Applications +.. _Canvas Software Suite: https://www.ezurio.com/canvas/software-suite diff --git a/boards/lairdconnect/pinnacle_100_dvk/pinnacle_100_dvk-pinctrl.dtsi b/boards/ezurio/pinnacle_100_dvk/pinnacle_100_dvk-pinctrl.dtsi similarity index 100% rename from boards/lairdconnect/pinnacle_100_dvk/pinnacle_100_dvk-pinctrl.dtsi rename to boards/ezurio/pinnacle_100_dvk/pinnacle_100_dvk-pinctrl.dtsi diff --git a/boards/lairdconnect/pinnacle_100_dvk/pinnacle_100_dvk.dts b/boards/ezurio/pinnacle_100_dvk/pinnacle_100_dvk.dts similarity index 97% rename from boards/lairdconnect/pinnacle_100_dvk/pinnacle_100_dvk.dts rename to boards/ezurio/pinnacle_100_dvk/pinnacle_100_dvk.dts index 1e3006dd0d3..a4cbacbd1af 100644 --- a/boards/lairdconnect/pinnacle_100_dvk/pinnacle_100_dvk.dts +++ b/boards/ezurio/pinnacle_100_dvk/pinnacle_100_dvk.dts @@ -1,5 +1,6 @@ /* * Copyright (c) 2019 Laird Connectivity + * Copyright (c) 2024 Ezurio * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,7 +12,7 @@ / { model = "Pinnacle 100 Dev Kit"; - compatible = "lairdconnect,pinnacle-100-dvk"; + compatible = "ezurio,pinnacle-100-dvk"; chosen { zephyr,console = &uart0; @@ -81,10 +82,13 @@ mcuboot-button0 = &button1; mcuboot-led0 = &led1; watchdog0 = &wdt0; - spi-flash0 = &mx25r64; }; }; +®1 { + regulator-initial-mode = ; +}; + &adc { status ="okay"; }; diff --git a/boards/lairdconnect/pinnacle_100_dvk/pinnacle_100_dvk.yaml b/boards/ezurio/pinnacle_100_dvk/pinnacle_100_dvk.yaml similarity index 88% rename from boards/lairdconnect/pinnacle_100_dvk/pinnacle_100_dvk.yaml rename to boards/ezurio/pinnacle_100_dvk/pinnacle_100_dvk.yaml index 153fb6cab08..3d44a009e2d 100644 --- a/boards/lairdconnect/pinnacle_100_dvk/pinnacle_100_dvk.yaml +++ b/boards/ezurio/pinnacle_100_dvk/pinnacle_100_dvk.yaml @@ -16,8 +16,7 @@ supported: - i2c - pwm - spi - - usb_cdc - usb_device - watchdog - netif:modem -vendor: lairdconnect +vendor: ezurio diff --git a/boards/lairdconnect/pinnacle_100_dvk/pinnacle_100_dvk_defconfig b/boards/ezurio/pinnacle_100_dvk/pinnacle_100_dvk_defconfig similarity index 100% rename from boards/lairdconnect/pinnacle_100_dvk/pinnacle_100_dvk_defconfig rename to boards/ezurio/pinnacle_100_dvk/pinnacle_100_dvk_defconfig diff --git a/boards/ezurio/pinnacle_100_dvk/pre_dt_board.cmake b/boards/ezurio/pinnacle_100_dvk/pre_dt_board.cmake new file mode 100644 index 00000000000..3369c21d3af --- /dev/null +++ b/boards/ezurio/pinnacle_100_dvk/pre_dt_board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2022 Nordic Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: +# - power@40000000 & clock@40000000 & bprot@40000000 +# - acl@4001e000 & flash-controller@4001e000 +list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/lairdconnect/rm1xx_dvk/Kconfig.defconfig b/boards/ezurio/rm1xx_dvk/Kconfig.defconfig similarity index 100% rename from boards/lairdconnect/rm1xx_dvk/Kconfig.defconfig rename to boards/ezurio/rm1xx_dvk/Kconfig.defconfig diff --git a/boards/lairdconnect/rm1xx_dvk/Kconfig.rm1xx_dvk b/boards/ezurio/rm1xx_dvk/Kconfig.rm1xx_dvk similarity index 100% rename from boards/lairdconnect/rm1xx_dvk/Kconfig.rm1xx_dvk rename to boards/ezurio/rm1xx_dvk/Kconfig.rm1xx_dvk diff --git a/boards/lairdconnect/rm1xx_dvk/board.cmake b/boards/ezurio/rm1xx_dvk/board.cmake similarity index 100% rename from boards/lairdconnect/rm1xx_dvk/board.cmake rename to boards/ezurio/rm1xx_dvk/board.cmake diff --git a/boards/ezurio/rm1xx_dvk/board.yml b/boards/ezurio/rm1xx_dvk/board.yml new file mode 100644 index 00000000000..4a8792eecc5 --- /dev/null +++ b/boards/ezurio/rm1xx_dvk/board.yml @@ -0,0 +1,5 @@ +board: + name: rm1xx_dvk + vendor: ezurio + socs: + - name: nrf51822 diff --git a/boards/lairdconnect/rm1xx_dvk/doc/img/RM186-DVK.jpg b/boards/ezurio/rm1xx_dvk/doc/img/RM186-DVK.jpg similarity index 100% rename from boards/lairdconnect/rm1xx_dvk/doc/img/RM186-DVK.jpg rename to boards/ezurio/rm1xx_dvk/doc/img/RM186-DVK.jpg diff --git a/boards/lairdconnect/rm1xx_dvk/doc/img/RM186-SM.jpg b/boards/ezurio/rm1xx_dvk/doc/img/RM186-SM.jpg similarity index 100% rename from boards/lairdconnect/rm1xx_dvk/doc/img/RM186-SM.jpg rename to boards/ezurio/rm1xx_dvk/doc/img/RM186-SM.jpg diff --git a/boards/ezurio/rm1xx_dvk/doc/index.rst b/boards/ezurio/rm1xx_dvk/doc/index.rst new file mode 100644 index 00000000000..bd57e8f400d --- /dev/null +++ b/boards/ezurio/rm1xx_dvk/doc/index.rst @@ -0,0 +1,179 @@ +.. _rm1xx_dvk: + +Ezurio RM1xx DVK +################ + +Overview +******** + +Ezurio's RM1xx is a module which integrates both LoRa and +BLE communications, powered by a Nordic Semiconductor nRF51822 ARM +Cortex-M0 CPU and on-board Semtech SX1272 LoRa RF chip. This board +supports the RM1xx on the RM1xx development board - RM191 for the +915MHz version and RM186 for the 868MHz version. + +This development kit has the following features: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/RM186-DVK.jpg + :align: center + :alt: RM1xx development kit (DVK) + + RM1xx development kit (DVK) (Credit: Ezurio) + +.. figure:: img/RM186-SM.jpg + :align: center + :alt: RM1xx module + + RM1xx module (Credit: Ezurio) + +More information about the module can be found on the +`RM1xx homepage`_. + +The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + +Hardware +******** + +The RM1xx has two internal oscillators. The frequency of +the slow clock is 32.768KHz. The frequency of the main clock +is 16MHz. + + +Supported Features +================== + +The rm1xx_dvk board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See `Nordic Semiconductor Infocenter`_ +for a complete list of hardware features. + +Connections and IOs +=================== + +The development board features a Microchip MCP23S08 SPI port expander - +note that this is not currently supported in Zephyr. + +Refer to the `Microchip MCP23S08 datasheet`_ for further details. + +Push buttons +------------ + +* BUTTON2 = SW0 = P0.05 + + +Internal Memory +=============== + +EEPROM Memory +------------- + +A 512KB (4Mb) Adesto AT25DF041B EEPROM is available via SPI for storage +of infrequently updated data and small datasets and can be used with +the spi-nor driver. Note that the EEPROM shares the same SPI bus as the +SX1272 LoRa transceiver so priority access should be given to the LoRa +radio. + +Refer to the `Adesto AT25DF041B datasheet`_ for further details. + +LoRa +==== + +A Semtech SX1272 transceiver chip is present in the module which can be +used in 915MHz LoRa frequency ranges if using an RM191 module or 868MHz +LoRa frequency ranges if uses an RM186 module + +Refer to the `Semtech SX1272 datasheet`_ for further details. + +Programming and Debugging +************************* + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board nRF51 DK +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rm1xx_dvk + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging boards +with a Segger IC. + +References +********** + +.. target-notes:: + +.. _RM1xx homepage: https://www.ezurio.com/wireless-modules/lorawan-solutions/sentrius-rm1xx-lora-ble-module +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +.. _Adesto AT25DF041B datasheet: https://www.dialog-semiconductor.com/sites/default/files/ds-at25df041b_040.pdf +.. _Semtech SX1272 datasheet: https://semtech.my.salesforce.com/sfc/p/#E0000000JelG/a/440000001NCE/v_VBhk1IolDgxwwnOpcS_vTFxPfSEPQbuneK3mWsXlU +.. _Microchip MCP23S08 datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/MCP23008-MCP23S08-Data-Sheet-20001919F.pdf diff --git a/boards/lairdconnect/rm1xx_dvk/pre_dt_board.cmake b/boards/ezurio/rm1xx_dvk/pre_dt_board.cmake similarity index 100% rename from boards/lairdconnect/rm1xx_dvk/pre_dt_board.cmake rename to boards/ezurio/rm1xx_dvk/pre_dt_board.cmake diff --git a/boards/lairdconnect/rm1xx_dvk/rm1xx_dvk-pinctrl.dtsi b/boards/ezurio/rm1xx_dvk/rm1xx_dvk-pinctrl.dtsi similarity index 100% rename from boards/lairdconnect/rm1xx_dvk/rm1xx_dvk-pinctrl.dtsi rename to boards/ezurio/rm1xx_dvk/rm1xx_dvk-pinctrl.dtsi diff --git a/boards/lairdconnect/rm1xx_dvk/rm1xx_dvk.dts b/boards/ezurio/rm1xx_dvk/rm1xx_dvk.dts similarity index 96% rename from boards/lairdconnect/rm1xx_dvk/rm1xx_dvk.dts rename to boards/ezurio/rm1xx_dvk/rm1xx_dvk.dts index 8d364bfa27a..f0b860ac453 100644 --- a/boards/lairdconnect/rm1xx_dvk/rm1xx_dvk.dts +++ b/boards/ezurio/rm1xx_dvk/rm1xx_dvk.dts @@ -1,5 +1,6 @@ /* * Copyright (c) 2021 Laird Connectivity + * Copyright (c) 2024 Ezurio * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,8 +11,8 @@ #include / { - model = "Laird Connectivity RM1XX_DVK"; - compatible = "lairdconnect,rm1xx_dvk"; + model = "Ezurio RM1XX_DVK"; + compatible = "ezurio,rm1xx_dvk"; chosen { zephyr,console = &uart0; @@ -37,7 +38,6 @@ sw0 = &button2; lora0 = &lora0; watchdog0 = &wdt0; - spi-flash0 = &at25; }; }; diff --git a/boards/lairdconnect/rm1xx_dvk/rm1xx_dvk.yaml b/boards/ezurio/rm1xx_dvk/rm1xx_dvk.yaml similarity index 89% rename from boards/lairdconnect/rm1xx_dvk/rm1xx_dvk.yaml rename to boards/ezurio/rm1xx_dvk/rm1xx_dvk.yaml index c673fd4d55e..2dd24375a5b 100644 --- a/boards/lairdconnect/rm1xx_dvk/rm1xx_dvk.yaml +++ b/boards/ezurio/rm1xx_dvk/rm1xx_dvk.yaml @@ -14,4 +14,4 @@ supported: testing: ignore_tags: - net -vendor: lairdconnect +vendor: ezurio diff --git a/boards/lairdconnect/rm1xx_dvk/rm1xx_dvk_defconfig b/boards/ezurio/rm1xx_dvk/rm1xx_dvk_defconfig similarity index 100% rename from boards/lairdconnect/rm1xx_dvk/rm1xx_dvk_defconfig rename to boards/ezurio/rm1xx_dvk/rm1xx_dvk_defconfig diff --git a/boards/fanke/fk7b0m1_vbt6/doc/index.rst b/boards/fanke/fk7b0m1_vbt6/doc/index.rst index dfabfd54e88..19b346585be 100644 --- a/boards/fanke/fk7b0m1_vbt6/doc/index.rst +++ b/boards/fanke/fk7b0m1_vbt6/doc/index.rst @@ -145,7 +145,7 @@ To begin, connect the ST-Link Debug Programmer to the FK7B0M1-VBT6 board using t interface. Next, connect the ST-Link to your host computer via a USB port. Once this setup is complete, you can proceed to build and flash your application to the board -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6.dts b/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6.dts index 090a29a1981..a8db5b677f2 100644 --- a/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6.dts +++ b/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6.dts @@ -41,7 +41,6 @@ aliases { led0 = &user_led; sw0 = &user_button; - spi-flash0 = &w25q64jvssiq_spi; }; }; diff --git a/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6_defconfig b/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6_defconfig index dd4c5e18475..8f6604fff01 100644 --- a/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6_defconfig +++ b/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6_defconfig @@ -14,11 +14,5 @@ CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y -# Enable Pinctrl -CONFIG_PINCTRL=y - # Enable GPIO CONFIG_GPIO=y - -# Enable clocks -CONFIG_CLOCK_CONTROL=y diff --git a/boards/franzininho/esp32s2_franzininho/doc/index.rst b/boards/franzininho/esp32s2_franzininho/doc/index.rst index 54de95ecb40..efa47c90719 100644 --- a/boards/franzininho/esp32s2_franzininho/doc/index.rst +++ b/boards/franzininho/esp32s2_franzininho/doc/index.rst @@ -68,7 +68,7 @@ MCUboot bootloader ================== User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. +must be built (and flashed) at least once. There are two options to be used when building an application: @@ -79,9 +79,10 @@ There are two options to be used when building an application: User can select the MCUboot bootloader by adding the following line to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y Sysbuild ======== @@ -93,7 +94,7 @@ To build the sample application using sysbuild use the command: .. zephyr-app-commands:: :tool: west - :app: samples/hello_world + :zephyr-app: samples/hello_world :board: esp32s2_franzininho :goals: build :west-args: --sysbuild @@ -129,7 +130,7 @@ Manual build ============ During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. +For that reason, images can be built one at a time using traditional build. The instructions following are relevant for both manual build and sysbuild. The only difference is the structure of the build directory. @@ -147,7 +148,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``esp32s2_franzininho`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: diff --git a/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.dts b/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.dts index d8a6f1c7070..74d5f7610a9 100644 --- a/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.dts +++ b/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.dts @@ -43,10 +43,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - &uart0 { status = "okay"; current-speed = <115200>; diff --git a/boards/gaisler/gr716a_mini/gr716a_mini.dts b/boards/gaisler/gr716a_mini/gr716a_mini.dts index 745caa64f67..9433e0d3c03 100644 --- a/boards/gaisler/gr716a_mini/gr716a_mini.dts +++ b/boards/gaisler/gr716a_mini/gr716a_mini.dts @@ -12,9 +12,7 @@ / { model = "GR716-MINI Development Board"; compatible = "gaisler,gr716a-mini"; - aliases { - spi-flash0 = &flash0; - }; + chosen { zephyr,console = &uart0; zephyr,shell-uart = &uart0; @@ -37,3 +35,11 @@ jedec-id = [c2 20 19]; }; }; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; diff --git a/boards/gaisler/gr716a_mini/gr716a_mini.yaml b/boards/gaisler/gr716a_mini/gr716a_mini.yaml index 8b673cebfa6..7898925121e 100644 --- a/boards/gaisler/gr716a_mini/gr716a_mini.yaml +++ b/boards/gaisler/gr716a_mini/gr716a_mini.yaml @@ -10,6 +10,7 @@ toolchain: supported: - netif - spi + - gpio testing: ignore_tags: - net diff --git a/boards/gd/gd32a503v_eval/doc/index.rst b/boards/gd/gd32a503v_eval/doc/index.rst index b926a265bb4..bd9170b16c4 100644 --- a/boards/gd/gd32a503v_eval/doc/index.rst +++ b/boards/gd/gd32a503v_eval/doc/index.rst @@ -119,7 +119,7 @@ The GD32A503V-EVAL includes an onboard programmer/debugger (GD-Link) which allow flash programming and debug over USB. There are also program and debug headers J2 and J100 that can be used with any ARM compatible tools. -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -168,7 +168,7 @@ The GD32A503 MCU have a ROM bootloader which allow flash programming. User should install `GD32 ISP Console`_ software at some Linux path. The recommended is :code:`$HOME/.local/bin`. -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/gd/gd32a503v_eval/gd32a503v_eval.dts b/boards/gd/gd32a503v_eval/gd32a503v_eval.dts index dc6e0325452..41fd7b2d75d 100644 --- a/boards/gd/gd32a503v_eval/gd32a503v_eval.dts +++ b/boards/gd/gd32a503v_eval/gd32a503v_eval.dts @@ -35,7 +35,6 @@ aliases { led0 = &led1; led1 = &led2; - spi-flash0 = &nor_flash; }; }; diff --git a/boards/gd/gd32e103v_eval/doc/index.rst b/boards/gd/gd32e103v_eval/doc/index.rst index 3d9058793fe..f53d0b173d3 100644 --- a/boards/gd/gd32e103v_eval/doc/index.rst +++ b/boards/gd/gd32e103v_eval/doc/index.rst @@ -111,7 +111,7 @@ The GD32E103V-EVAL includes an onboard programmer/debugger (GD-Link) which allow flash programming and debug over USB. There are also program and debug headers J1 and J100 that can be used with any ARM compatible tools. -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -160,7 +160,7 @@ The GD32E103 MCU have a ROM bootloader which allow flash programming. User should install `GD32 ISP Console`_ software at some Linux path. The recommended is :code:`$HOME/.local/bin`. -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/gd/gd32e507v_start/doc/index.rst b/boards/gd/gd32e507v_start/doc/index.rst index 097c5a5c976..902b4a20766 100644 --- a/boards/gd/gd32e507v_start/doc/index.rst +++ b/boards/gd/gd32e507v_start/doc/index.rst @@ -94,7 +94,7 @@ provided you install the necessary CMSIS-Pack: J-Link can also be used to program the board using the SWD interface exposed in the JP1 header. -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/gd/gd32e507z_eval/doc/index.rst b/boards/gd/gd32e507z_eval/doc/index.rst index c3484d8beec..edaac634410 100644 --- a/boards/gd/gd32e507z_eval/doc/index.rst +++ b/boards/gd/gd32e507z_eval/doc/index.rst @@ -102,7 +102,7 @@ provided you install the necessary CMSIS-Pack: J-Link can also be used to program the board using the JTAG interface exposed in the JP2 header. -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/gd/gd32f350r_eval/doc/index.rst b/boards/gd/gd32f350r_eval/doc/index.rst index 8a2317da68e..d5dc24f46c9 100644 --- a/boards/gd/gd32f350r_eval/doc/index.rst +++ b/boards/gd/gd32f350r_eval/doc/index.rst @@ -87,7 +87,7 @@ The GD32F350R-EVAL includes an onboard programmer/debugger (GD-Link) which allows flash programming and debugging over USB. There is also a SWD header (J3) which can be used with tools like Segger J-Link. -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/gd/gd32f403z_eval/doc/index.rst b/boards/gd/gd32f403z_eval/doc/index.rst index 4ea432c31d1..c5c97fd727c 100644 --- a/boards/gd/gd32f403z_eval/doc/index.rst +++ b/boards/gd/gd32f403z_eval/doc/index.rst @@ -114,7 +114,7 @@ The GD32F403Z-EVAL includes an onboard programmer/debugger (GD-Link) which allow flash programming and debug over USB. There are also program and debug headers J1 and J100 that can be used with any ARM compatible tools. -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -163,7 +163,7 @@ The GD32F403 MCU have a ROM bootloader which allow flash programming. User should install `GD32 ISP Console`_ software at some Linux path. The recommended is :code:`$HOME/.local/bin`. -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/gd/gd32f407v_start/doc/index.rst b/boards/gd/gd32f407v_start/doc/index.rst index cd67921e59e..a59243db498 100644 --- a/boards/gd/gd32f407v_start/doc/index.rst +++ b/boards/gd/gd32f407v_start/doc/index.rst @@ -96,7 +96,7 @@ if not installed yet. Also, J-Link can be used to program the board via the SWD interface (PA13/SWDIO and PA14/SWCLK in the JP6 header). -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/gd/gd32f450i_eval/doc/index.rst b/boards/gd/gd32f450i_eval/doc/index.rst index 59e9d258975..e01c3957652 100644 --- a/boards/gd/gd32f450i_eval/doc/index.rst +++ b/boards/gd/gd32f450i_eval/doc/index.rst @@ -112,7 +112,7 @@ The GD32F450I-EVAL includes an onboard programmer/debugger (GD-Link) which allows flash programming and debugging over USB. There is also a JTAG header (J1) which can be used with tools like Segger J-Link. -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/gd/gd32f450i_eval/gd32f450i_eval.dts b/boards/gd/gd32f450i_eval/gd32f450i_eval.dts index 4e2f87c4015..4a9f9d4fb6a 100644 --- a/boards/gd/gd32f450i_eval/gd32f450i_eval.dts +++ b/boards/gd/gd32f450i_eval/gd32f450i_eval.dts @@ -71,7 +71,6 @@ sw0 = &user_key; pwm-led0 = &pwm_led; eeprom-0 = &eeprom0; - spi-flash0 = &nor_flash; watchdog0 = &fwdgt; }; }; diff --git a/boards/gd/gd32f450v_start/doc/index.rst b/boards/gd/gd32f450v_start/doc/index.rst index e45f05a58a6..0b1a781758b 100644 --- a/boards/gd/gd32f450v_start/doc/index.rst +++ b/boards/gd/gd32f450v_start/doc/index.rst @@ -89,7 +89,7 @@ The GD32F450V-START includes an onboard programmer/debugger (GD-Link) which allows flash programming and debugging over USB. There is also a SWD header (JP100) which can be used with tools like Segger J-Link. -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/gd/gd32f450z_eval/doc/index.rst b/boards/gd/gd32f450z_eval/doc/index.rst index 0e31f262db3..cdc4f8f42a7 100644 --- a/boards/gd/gd32f450z_eval/doc/index.rst +++ b/boards/gd/gd32f450z_eval/doc/index.rst @@ -107,7 +107,7 @@ The GD32F450Z-EVAL includes an onboard programmer/debugger (GD-Link) which allows flash programming and debugging over USB. There is also a JTAG header (J1) which can be used with tools like Segger J-Link. -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/gd/gd32f450z_eval/gd32f450z_eval.dts b/boards/gd/gd32f450z_eval/gd32f450z_eval.dts index c636a5647c7..f01fd488b4c 100644 --- a/boards/gd/gd32f450z_eval/gd32f450z_eval.dts +++ b/boards/gd/gd32f450z_eval/gd32f450z_eval.dts @@ -71,7 +71,6 @@ sw0 = &user_key; pwm-led0 = &pwm_led; eeprom-0 = &eeprom0; - spi-flash0 = &nor_flash; watchdog0 = &fwdgt; }; }; diff --git a/boards/gd/gd32f470i_eval/doc/index.rst b/boards/gd/gd32f470i_eval/doc/index.rst index 627dc1fa9e9..75e33eaed2a 100644 --- a/boards/gd/gd32f470i_eval/doc/index.rst +++ b/boards/gd/gd32f470i_eval/doc/index.rst @@ -111,7 +111,7 @@ The GD32F470I-EVAL includes an onboard programmer/debugger (GD-Link) which allows flash programming and debugging over USB. There is also a JTAG header (J1) which can be used with tools like Segger J-Link. -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/gd/gd32f470i_eval/gd32f470i_eval.dts b/boards/gd/gd32f470i_eval/gd32f470i_eval.dts index 306d190b3d4..1bff660f1c6 100644 --- a/boards/gd/gd32f470i_eval/gd32f470i_eval.dts +++ b/boards/gd/gd32f470i_eval/gd32f470i_eval.dts @@ -71,7 +71,6 @@ sw0 = &user_key; pwm-led0 = &pwm_led; eeprom-0 = &eeprom0; - spi-flash0 = &nor_flash; watchdog0 = &fwdgt; }; }; diff --git a/boards/gd/gd32l233r_eval/doc/index.rst b/boards/gd/gd32l233r_eval/doc/index.rst index 8b5a08514e3..884978fd021 100644 --- a/boards/gd/gd32l233r_eval/doc/index.rst +++ b/boards/gd/gd32l233r_eval/doc/index.rst @@ -88,7 +88,7 @@ The GD32L233R-EVAL includes an onboard programmer/debugger (GD-Link) which allows flash programming and debugging over USB. There is also a SWD header which can be used with tools like Segger J-Link(latest version required). -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/gd/gd32vf103c_starter/doc/index.rst b/boards/gd/gd32vf103c_starter/doc/index.rst index aee1ea612e7..29a428c6c98 100644 --- a/boards/gd/gd32vf103c_starter/doc/index.rst +++ b/boards/gd/gd32vf103c_starter/doc/index.rst @@ -83,7 +83,7 @@ The GD32VF103C-STARTER includes an onboard programmer/debugger (GD-Link) which allows flash programming and debugging over USB. There is also a JTAG header (JP1) which can be used with tools like Segger J-Link. -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/gd/gd32vf103v_eval/doc/index.rst b/boards/gd/gd32vf103v_eval/doc/index.rst index 42af6d765d6..5aa8e8327bd 100644 --- a/boards/gd/gd32vf103v_eval/doc/index.rst +++ b/boards/gd/gd32vf103v_eval/doc/index.rst @@ -93,7 +93,7 @@ The GD32VF103V-EVAL includes an onboard programmer/debugger (GD-Link) which allows flash programming and debugging over USB. There is also a JTAG header (JP1) which can be used with tools like Segger J-Link. -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/gd/gd32vf103v_eval/gd32vf103v_eval.dts b/boards/gd/gd32vf103v_eval/gd32vf103v_eval.dts index cea9c00b7e9..bee944f7fdc 100644 --- a/boards/gd/gd32vf103v_eval/gd32vf103v_eval.dts +++ b/boards/gd/gd32vf103v_eval/gd32vf103v_eval.dts @@ -84,7 +84,6 @@ led1 = &led2; sw0 = &key_cet; pwm-led0 = &pwm_led; - spi-flash0 = &nor_flash; watchdog0 = &fwdgt; }; }; diff --git a/boards/google/dragonclaw/google_dragonclaw.dts b/boards/google/dragonclaw/google_dragonclaw.dts index a0f7932d8ae..8c279320d4d 100644 --- a/boards/google/dragonclaw/google_dragonclaw.dts +++ b/boards/google/dragonclaw/google_dragonclaw.dts @@ -92,6 +92,10 @@ }; }; +&rng { + status = "okay"; +}; + /* * Set flags of unused pins as GPIO_ACTIVE_HIGH (0 << 0), which will be * interpreted by GPIO driver as GPIO_DISCONNECTED, without setting the gpio as diff --git a/boards/google/dragonclaw/google_dragonclaw.yaml b/boards/google/dragonclaw/google_dragonclaw.yaml index ddb4f3a7713..bf535af2c1e 100644 --- a/boards/google/dragonclaw/google_dragonclaw.yaml +++ b/boards/google/dragonclaw/google_dragonclaw.yaml @@ -9,3 +9,11 @@ toolchain: ram: 256 flash: 1024 vendor: google +supported: + - counter + - dma + - gpio + - i2c + - spi + - pwm + - rtc diff --git a/boards/google/dragonclaw/google_dragonclaw_defconfig b/boards/google/dragonclaw/google_dragonclaw_defconfig index 3247707e4e4..c48fb0d5c94 100644 --- a/boards/google/dragonclaw/google_dragonclaw_defconfig +++ b/boards/google/dragonclaw/google_dragonclaw_defconfig @@ -12,12 +12,6 @@ CONFIG_UART_CONSOLE=y # GPIO Controller CONFIG_GPIO=y -# Clock Controller -CONFIG_CLOCK_CONTROL=y - -# Pin Controller -CONFIG_PINCTRL=y - # Enable MPU and HW stack protection CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/google/kukui/Kconfig.google_kukui b/boards/google/kukui/Kconfig.google_kukui deleted file mode 100644 index 51b960645ee..00000000000 --- a/boards/google/kukui/Kconfig.google_kukui +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright 2019 The Chromium OS Authors -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GOOGLE_KUKUI - select SOC_STM32F098XX diff --git a/boards/google/kukui/board.cmake b/boards/google/kukui/board.cmake deleted file mode 100644 index 9881313609a..00000000000 --- a/boards/google/kukui/board.cmake +++ /dev/null @@ -1 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/google/kukui/board.yml b/boards/google/kukui/board.yml deleted file mode 100644 index 699218ade22..00000000000 --- a/boards/google/kukui/board.yml +++ /dev/null @@ -1,5 +0,0 @@ -board: - name: google_kukui - vendor: google - socs: - - name: stm32f098xx diff --git a/boards/google/kukui/doc/index.rst b/boards/google/kukui/doc/index.rst deleted file mode 100644 index a68586f311f..00000000000 --- a/boards/google/kukui/doc/index.rst +++ /dev/null @@ -1,88 +0,0 @@ -.. _google_kukui_board: - -Google Kukui EC -############### - -Overview -******** - -Kukui is a reference board for Chromium OS-based devices Krane and -Kodama. These are known as the Lenovo Chromebook Duet and 10e Chromebook -Tablet, respectively. - -Zephyr has support for the STM32-based embedded controller (EC) on-board. - -Hardware -******** - -- STM32F098RCH6 -- MT6370 battery charger -- BMM150 compass -- BMM160 gyroscope -- Connections to the MediaTek AP - -Supported Features -================== - -The following features are supported: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ - -Other features (such as I2C) are not available in Zephyr. - -The default configuration can be found in -:zephyr_file:`boards/google/kukui/google_kukui_defconfig` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output -(push-pull or open-drain), as input (with or without pull-up or -pull-down), or as peripheral alternate function. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA10/PA9 -- I2C_1 SCL/SDA : PB8/PB9 -- I2C_2 SCL/SDA : PA11/PA12 -- Volume down : GPIOB pin 11 -- Volume up : GPIOB pin 10 -- Power : GPIOA pin 0 - -Programming and Debugging -************************* - -Build application as usual for the ``google_kukui`` board, and flash -using Servo V2, μServo, or Servo V4 (CCD). See the -`Chromium EC Flashing Documentation`_ for more information. - -Debugging -========= - -Use SWD with a J-Link or ST-Link. - -References -********** - -.. target-notes:: - -.. _Chromium EC Flashing Documentation: - https://chromium.googlesource.com/chromiumos/platform/ec#Flashing-via-the-servo-debug-board diff --git a/boards/google/kukui/google_kukui.dts b/boards/google/kukui/google_kukui.dts deleted file mode 100644 index cbebcc00c82..00000000000 --- a/boards/google/kukui/google_kukui.dts +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (c) 2019 The Chromium OS Authors - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include - -/ { - model = "Google Kukui EC"; - compatible = "google,kukui-ec", "st,stm32f098"; - - chosen { - zephyr,console = &usart1; - zephyr,shell-uart = &usart1; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - }; -}; - -&clk_hsi { - status = "okay"; -}; - -&rcc { - clocks = <&clk_hsi>; - clock-frequency = ; - ahb-prescaler = <1>; - apb1-prescaler = <1>; -}; - -&usart1 { - pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; - pinctrl-names = "default"; - current-speed = <115200>; - status = "okay"; -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Set 6Kb of storage at the end of the 256Kb of flash */ - storage_partition: partition@3e800 { - label = "storage"; - reg = <0x0003e800 DT_SIZE_K(6)>; - }; - }; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>; - pinctrl-names = "default"; - status = "okay"; - clock-frequency = ; -}; - -&i2c2 { - pinctrl-0 = <&i2c2_scl_pa11 &i2c2_sda_pa12>; - pinctrl-names = "default"; - status = "okay"; - clock-frequency = ; -}; diff --git a/boards/google/kukui/google_kukui.yaml b/boards/google/kukui/google_kukui.yaml deleted file mode 100644 index ad95d286cb2..00000000000 --- a/boards/google/kukui/google_kukui.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: google_kukui -name: Google Kukui EC -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 32 -flash: 256 -testing: - ignore_tags: - - net - - bluetooth -vendor: google diff --git a/boards/google/kukui/google_kukui_defconfig b/boards/google/kukui/google_kukui_defconfig deleted file mode 100644 index 0196b219b8f..00000000000 --- a/boards/google/kukui/google_kukui_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# GPIO Controller -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/google/twinkie_v2/google_twinkie_v2.dts b/boards/google/twinkie_v2/google_twinkie_v2.dts index 1f918f848ed..7eafd8e3612 100644 --- a/boards/google/twinkie_v2/google_twinkie_v2.dts +++ b/boards/google/twinkie_v2/google_twinkie_v2.dts @@ -123,7 +123,7 @@ zephyr,resolution = <12>; }; - channel@15 { + channel@f { reg = <15>; zephyr,gain = "ADC_GAIN_1"; zephyr,reference = "ADC_REF_INTERNAL"; @@ -132,7 +132,7 @@ zephyr,resolution = <12>; }; - channel@17 { + channel@11 { reg = <17>; zephyr,gain = "ADC_GAIN_1"; zephyr,reference = "ADC_REF_INTERNAL"; @@ -141,7 +141,7 @@ zephyr,resolution = <12>; }; - channel@18 { + channel@12 { reg = <18>; zephyr,gain = "ADC_GAIN_1"; zephyr,reference = "ADC_REF_INTERNAL"; diff --git a/boards/google/twinkie_v2/google_twinkie_v2_defconfig b/boards/google/twinkie_v2/google_twinkie_v2_defconfig index 3262a345bd2..bf172e71887 100644 --- a/boards/google/twinkie_v2/google_twinkie_v2_defconfig +++ b/boards/google/twinkie_v2/google_twinkie_v2_defconfig @@ -5,11 +5,5 @@ # GPIO Controller CONFIG_GPIO=y -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/hardkernel/odroid_go/Kconfig.defconfig b/boards/hardkernel/odroid_go/Kconfig.defconfig index 2f38123c8db..121f6e69397 100644 --- a/boards/hardkernel/odroid_go/Kconfig.defconfig +++ b/boards/hardkernel/odroid_go/Kconfig.defconfig @@ -12,10 +12,10 @@ config SPI default y if DISK_DRIVER_SDMMC config ESP_SPIRAM - default y + default y if !MCUBOOT choice SPIRAM_TYPE - default SPIRAM_TYPE_ESPPSRAM64 + default SPIRAM_TYPE_ESPPSRAM32 endchoice config HEAP_MEM_POOL_ADD_SIZE_BOARD diff --git a/boards/hardkernel/odroid_go/Kconfig.odroid_go b/boards/hardkernel/odroid_go/Kconfig.odroid_go index b84b503b415..ecc6d92e4ff 100644 --- a/boards/hardkernel/odroid_go/Kconfig.odroid_go +++ b/boards/hardkernel/odroid_go/Kconfig.odroid_go @@ -4,6 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_ODROID_GO - select SOC_ESP32_WROVER_E_N16R2 + select SOC_ESP32_WROVER_E_N16R4 select SOC_ESP32_PROCPU if BOARD_ODROID_GO_ESP32_PROCPU select SOC_ESP32_APPCPU if BOARD_ODROID_GO_ESP32_APPCPU diff --git a/boards/hardkernel/odroid_go/doc/index.rst b/boards/hardkernel/odroid_go/doc/index.rst index 9fa4d107b13..62f38d4799d 100644 --- a/boards/hardkernel/odroid_go/doc/index.rst +++ b/boards/hardkernel/odroid_go/doc/index.rst @@ -98,18 +98,21 @@ below to retrieve those files. Building & Flashing ******************* -ESP-IDF bootloader -================== +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. + Simple boot does not provide any security features nor OTA updates. MCUboot bootloader ================== User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. +must be built (and flashed) at least once. There are two options to be used when building an application: @@ -120,9 +123,10 @@ There are two options to be used when building an application: User can select the MCUboot bootloader by adding the following line to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y Sysbuild ======== @@ -134,7 +138,7 @@ To build the sample application using sysbuild use the command: .. zephyr-app-commands:: :tool: west - :app: samples/hello_world + :zephyr-app: samples/hello_world :board: odroid_go :goals: build :west-args: --sysbuild @@ -170,7 +174,7 @@ Manual build ============ During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. +For that reason, images can be built one at a time using traditional build. The instructions following are relevant for both manual build and sysbuild. The only difference is the structure of the build directory. @@ -188,7 +192,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``odroid_go`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -215,13 +219,13 @@ Debugging As with much custom hardware, the ESP32 modules require patches to OpenOCD that are not upstreamed yet. Espressif maintains their own fork of -the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_. The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the ``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` parameter when building. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -229,7 +233,7 @@ Here is an example for building the :ref:`hello_world` application. :goals: build flash :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/hardkernel/odroid_go/odroid_go-flash_partition_table.dtsi b/boards/hardkernel/odroid_go/odroid_go-flash_partition_table.dtsi new file mode 100644 index 00000000000..bd0a69298c8 --- /dev/null +++ b/boards/hardkernel/odroid_go/odroid_go-flash_partition_table.dtsi @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2024 Yannis Damigos + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 2048kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00200000>; + }; + + /* Reserve 2048kB for the application in slot 1 */ + slot1_partition: partition@210000 { + label = "image-1"; + reg = <0x00210000 0x00200000>; + }; + + /* Reserve the remaining 12224kB for the storage partition */ + storage_partition: partition@410000 { + label = "storage"; + reg = <0x00410000 0x00BF0000>; + }; + }; +}; diff --git a/boards/hardkernel/odroid_go/odroid_go_appcpu.dts b/boards/hardkernel/odroid_go/odroid_go_appcpu.dts index 6b59353de6d..656272a24e8 100644 --- a/boards/hardkernel/odroid_go/odroid_go_appcpu.dts +++ b/boards/hardkernel/odroid_go/odroid_go_appcpu.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include "odroid_go-flash_partition_table.dtsi" / { model = "ODROID-GO Game Kit APPCPU"; @@ -18,14 +19,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &ipm0 { status = "okay"; }; @@ -33,42 +26,3 @@ &trng0 { status = "okay"; }; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/hardkernel/odroid_go/odroid_go_procpu.dts b/boards/hardkernel/odroid_go/odroid_go_procpu.dts index 4349e6aafe9..108e503cec4 100644 --- a/boards/hardkernel/odroid_go/odroid_go_procpu.dts +++ b/boards/hardkernel/odroid_go/odroid_go_procpu.dts @@ -7,6 +7,7 @@ #include #include "odroid_go-pinctrl.dtsi" +#include "odroid_go-flash_partition_table.dtsi" #include / { @@ -100,14 +101,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &uart0 { status = "okay"; current-speed = <115200>; @@ -177,45 +170,6 @@ status = "okay"; }; -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; - &esp32_bt_hci { status = "okay"; }; diff --git a/boards/hardkernel/odroid_go/odroid_go_procpu_defconfig b/boards/hardkernel/odroid_go/odroid_go_procpu_defconfig index 5de7f124113..1a0608e1def 100644 --- a/boards/hardkernel/odroid_go/odroid_go_procpu_defconfig +++ b/boards/hardkernel/odroid_go/odroid_go_procpu_defconfig @@ -10,3 +10,5 @@ CONFIG_GPIO=y # required to enable LCD backlight CONFIG_REGULATOR=y + +CONFIG_ESP32_USE_UNSUPPORTED_REVISION=y diff --git a/boards/heltec/heltec_wifi_lora32_v2/doc/index.rst b/boards/heltec/heltec_wifi_lora32_v2/doc/index.rst index b97a9980512..ee595e0a847 100644 --- a/boards/heltec/heltec_wifi_lora32_v2/doc/index.rst +++ b/boards/heltec/heltec_wifi_lora32_v2/doc/index.rst @@ -56,7 +56,7 @@ MCUboot bootloader ================== User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. +must be built (and flashed) at least once. There are two options to be used when building an application: @@ -67,9 +67,10 @@ There are two options to be used when building an application: User can select the MCUboot bootloader by adding the following line to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y Sysbuild ======== @@ -81,7 +82,7 @@ To build the sample application using sysbuild use the command: .. zephyr-app-commands:: :tool: west - :app: samples/hello_world + :zephyr-app: samples/hello_world :board: heltec_wifi_lora32_v2 :goals: build :west-args: --sysbuild @@ -117,7 +118,7 @@ Manual build ============ During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. +For that reason, images can be built one at a time using traditional build. The instructions following are relevant for both manual build and sysbuild. The only difference is the structure of the build directory. @@ -135,7 +136,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``heltec_wifi_lora32_v2`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -162,13 +163,13 @@ Debugging As with much custom hardware, the ESP32 modules require patches to OpenOCD that are not upstreamed yet. Espressif maintains their own fork of -the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_. The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the ``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` parameter when building. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -176,7 +177,7 @@ Here is an example for building the :ref:`hello_world` application. :goals: build flash :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_appcpu.dts b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_appcpu.dts index 4cf9e26b89d..1b9f7dff700 100644 --- a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_appcpu.dts +++ b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_appcpu.dts @@ -18,14 +18,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &ipm0 { status = "okay"; }; diff --git a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_procpu.dts b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_procpu.dts index 946c4da81af..4c7cedf82b5 100644 --- a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_procpu.dts +++ b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_procpu.dts @@ -59,14 +59,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &uart0 { status = "okay"; current-speed = <115200>; diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/doc/index.rst b/boards/heltec/heltec_wireless_stick_lite_v3/doc/index.rst index 85470571981..352d158fbac 100644 --- a/boards/heltec/heltec_wireless_stick_lite_v3/doc/index.rst +++ b/boards/heltec/heltec_wireless_stick_lite_v3/doc/index.rst @@ -170,7 +170,7 @@ MCUboot bootloader ================== User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. +must be built (and flashed) at least once. There are two options to be used when building an application: @@ -181,9 +181,10 @@ There are two options to be used when building an application: User can select the MCUboot bootloader by adding the following line to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y Sysbuild ======== @@ -195,7 +196,7 @@ To build the sample application using sysbuild use the command: .. zephyr-app-commands:: :tool: west - :app: samples/hello_world + :zephyr-app: samples/hello_world :board: heltec_wireless_stick_lite_v3 :goals: build :west-args: --sysbuild @@ -231,7 +232,7 @@ Manual build ============ During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. +For that reason, images can be built one at a time using traditional build. The instructions following are relevant for both manual build and sysbuild. The only difference is the structure of the build directory. @@ -249,7 +250,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``heltec_wireless_stick_lite_v3`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -276,13 +277,13 @@ Debugging As with much custom hardware, the ESP32S3 modules require patches to OpenOCD that are not upstreamed yet. Espressif maintains their own fork of -the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_. The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the ``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` parameter when building. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -290,7 +291,7 @@ Here is an example for building the :ref:`hello_world` application. :goals: build flash :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_appcpu.dts b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_appcpu.dts index 6c49e64e8d1..92bde107bc3 100644 --- a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_appcpu.dts +++ b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_appcpu.dts @@ -17,14 +17,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &trng0 { status = "okay"; }; diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_procpu.dts b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_procpu.dts index ef895dfc693..d4b2f2b17e8 100644 --- a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_procpu.dts +++ b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_procpu.dts @@ -76,14 +76,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &adc1 { status ="okay"; }; @@ -136,7 +128,7 @@ dio2-tx-enable; dio3-tcxo-voltage = ; tcxo-power-startup-delay-ms = <5>; - spi-max-frequency = <16000000>; + spi-max-frequency = <4000000>; }; }; diff --git a/boards/holyiot/yj16019/holyiot_yj16019.dts b/boards/holyiot/yj16019/holyiot_yj16019.dts index 99796210fa8..6cdb4fdd938 100644 --- a/boards/holyiot/yj16019/holyiot_yj16019.dts +++ b/boards/holyiot/yj16019/holyiot_yj16019.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include "holyiot_yj16019-pinctrl.dtsi" #include @@ -13,12 +14,6 @@ model = "Holyiot YJ-16019"; compatible = "holyiot,yj-16019"; - chosen { - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; - leds { compatible = "gpio-leds"; led0: led_0 { @@ -58,43 +53,3 @@ pinctrl-1 = <&pwm0_sleep>; pinctrl-names = "default", "sleep"; }; - -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000C000>; - }; - slot0_partition: partition@c000 { - label = "image-0"; - reg = <0x0000C000 0x00067000>; - }; - slot1_partition: partition@73000 { - label = "image-1"; - reg = <0x00073000 0x00067000>; - }; - scratch_partition: partition@da000 { - label = "image-scratch"; - reg = <0x000da000 0x0001e000>; - }; - - /* - * The flash starting at 0x000f8000 and ending at - * 0x000fffff is reserved for use by the application. - */ - - /* - * Storage partition will be used by FCB/LittleFS/NVS - * if enabled. - */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; diff --git a/boards/infineon/cy8ckit_062s4/cy8ckit_062s4.dts b/boards/infineon/cy8ckit_062s4/cy8ckit_062s4.dts index 457878a62b7..9328a0cf60d 100644 --- a/boards/infineon/cy8ckit_062s4/cy8ckit_062s4.dts +++ b/boards/infineon/cy8ckit_062s4/cy8ckit_062s4.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023 David Ullmann + * Copyright (c) 2024 David Ullmann * SPDX-License-Identifier: Apache-2.0 */ @@ -29,6 +29,32 @@ }; + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; /* shared */ + gpio-map = <0 0 &gpio_prt10 0 0>, /* A0 */ + <1 0 &gpio_prt10 1 0>, /* A1 */ + <2 0 &gpio_prt10 2 0>, /* A2 */ + <3 0 &gpio_prt10 3 0>, /* A3 */ + <4 0 &gpio_prt10 4 0>, /* A4 */ + <5 0 &gpio_prt10 5 0>, /* A5 */ + <6 0 &gpio_prt0 2 0>, /* D0-RX-5 */ + <7 0 &gpio_prt0 3 0>, /* D1-TX-5 */ + <8 0 &gpio_prt5 0 0>, /* D2-RTS-5 */ + <9 0 &gpio_prt5 1 0>, /* D3-CTS-5 */ + <10 0 &gpio_prt5 6 0>, /* D4 */ + <11 0 &gpio_prt5 7 0>, /* D5 */ + <12 0 &gpio_prt6 2 0>, /* D6 */ + <13 0 &gpio_prt6 3 0>, /* D7 */ + <14 0 &gpio_prt2 4 0>, /* D8-RX-6 */ + <15 0 &gpio_prt2 6 0>, /* D9-TX-6 */ + <16 0 &gpio_prt2 3 0>, /* D10 */ + <17 0 &gpio_prt2 0 0>, /* D11 */ + <18 0 &gpio_prt2 1 0>, /* D12 */ + <19 0 &gpio_prt2 2 0>; /* D13 */ + }; }; &p3_1_scb2_uart_tx { @@ -55,3 +81,9 @@ uart2: &scb2 { &gpio_prt2 { status = "okay"; }; + +uart0: &scb0 { + compatible = "infineon,cat1-uart"; +}; + +arduino_serial: &uart0 {}; diff --git a/boards/infineon/cy8ckit_062s4/doc/index.rst b/boards/infineon/cy8ckit_062s4/doc/index.rst index f3a026b3b6b..1dfdb93bd30 100644 --- a/boards/infineon/cy8ckit_062s4/doc/index.rst +++ b/boards/infineon/cy8ckit_062s4/doc/index.rst @@ -50,7 +50,7 @@ The board configuration supports the following hardware features: +-----------+------------+-----------------------+ The default configuration can be found in the Kconfig -:zephyr_file:`boards/cypress/cy8ckit_062s4/cy8ckit_062s4_defconfig`. +:zephyr_file:`boards/infineon/cy8ckit_062s4/cy8ckit_062s4_defconfig`. Clock Configuration =================== diff --git a/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w-common.dtsi b/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w-common.dtsi index 75012f88ffc..d68da6f7522 100644 --- a/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w-common.dtsi +++ b/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w-common.dtsi @@ -15,7 +15,7 @@ compatible = "gpio-leds"; user_led: led_0 { label = "LED_0"; - gpios = <&gpio_prt13 7 GPIO_ACTIVE_HIGH>; + gpios = <&gpio_prt13 7 GPIO_ACTIVE_LOW>; }; }; diff --git a/boards/infineon/cy8cproto_062_4343w/doc/index.rst b/boards/infineon/cy8cproto_062_4343w/doc/index.rst index e1be366086c..a5934089f0b 100644 --- a/boards/infineon/cy8cproto_062_4343w/doc/index.rst +++ b/boards/infineon/cy8cproto_062_4343w/doc/index.rst @@ -74,7 +74,7 @@ The board configuration supports the following hardware features: The default configuration can be found in the Kconfig -:zephyr_file:`boards/cypress/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig` +:zephyr_file:`boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig` System Clock diff --git a/boards/infineon/cy8cproto_063_ble/doc/index.rst b/boards/infineon/cy8cproto_063_ble/doc/index.rst index 8ef38711c8f..86cc9cd5c15 100644 --- a/boards/infineon/cy8cproto_063_ble/doc/index.rst +++ b/boards/infineon/cy8cproto_063_ble/doc/index.rst @@ -59,7 +59,7 @@ The board configuration supports the following hardware features: The default configurations can be found in -:zephyr_file:`boards/cypress/cy8cproto_063_ble/cy8cproto_063_ble_defconfig` +:zephyr_file:`boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble_defconfig` System Clock ============ diff --git a/boards/infineon/cyw920829m2evk_02/Kconfig.cyw920829m2evk_02 b/boards/infineon/cyw920829m2evk_02/Kconfig.cyw920829m2evk_02 new file mode 100644 index 00000000000..1565606bbbe --- /dev/null +++ b/boards/infineon/cyw920829m2evk_02/Kconfig.cyw920829m2evk_02 @@ -0,0 +1,7 @@ +# The Infineon AIROC™ CYW20829 Bluetooth® LE evaluation kit (CYW92089M2EVK-02) + +# Copyright (c) 2024 Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CYW920829M2EVK_02 + select SOC_CYW20829B0LKML diff --git a/boards/infineon/cyw920829m2evk_02/Kconfig.defconfig b/boards/infineon/cyw920829m2evk_02/Kconfig.defconfig new file mode 100644 index 00000000000..645567a40c7 --- /dev/null +++ b/boards/infineon/cyw920829m2evk_02/Kconfig.defconfig @@ -0,0 +1,13 @@ +# The Infineon AIROC™ CYW20829 Bluetooth® LE evaluation kit (CYW92089M2EVK-02) + +# Copyright (c) 2024 Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 + +choice AIROC_PART + default CYW20829 if BT +endchoice + +# Heap Pool Size +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 10096 diff --git a/boards/infineon/cyw920829m2evk_02/board.cmake b/boards/infineon/cyw920829m2evk_02/board.cmake new file mode 100644 index 00000000000..9fa085b7448 --- /dev/null +++ b/boards/infineon/cyw920829m2evk_02/board.cmake @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/infineon/cyw920829m2evk_02/board.yml b/boards/infineon/cyw920829m2evk_02/board.yml new file mode 100644 index 00000000000..e25e3922b53 --- /dev/null +++ b/boards/infineon/cyw920829m2evk_02/board.yml @@ -0,0 +1,5 @@ +board: + name: cyw920829m2evk_02 + vendor: infineon + socs: + - name: cyw20829b0lkml diff --git a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02-common.dtsi b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02-common.dtsi new file mode 100644 index 00000000000..d795ccce728 --- /dev/null +++ b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02-common.dtsi @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2024 Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + aliases { + led0 = &user_led0; + led1 = &user_led1; + sw0 = &user_bt0; + sw1 = &user_bt1; + }; + + leds { + compatible = "gpio-leds"; + user_led0: led_0 { + label = "LED_0"; + gpios = <&gpio_prt1 1 GPIO_ACTIVE_LOW>; + }; + + user_led1: led_1 { + label = "LED_1"; + gpios = <&gpio_prt5 2 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_bt0: user_btn0 { + label = "SW_1"; + gpios = <&gpio_prt0 5 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + + user_bt1: user_btn1 { + label = "SW_2"; + gpios = <&gpio_prt1 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + }; +}; + +&gpio_prt0 { + status = "okay"; +}; + +&gpio_prt1 { + status = "okay"; +}; + +&gpio_prt3 { + status = "okay"; +}; + +&gpio_prt5 { + status = "okay"; +}; diff --git a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02-pinctrl.dtsi b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02-pinctrl.dtsi new file mode 100644 index 00000000000..758341c3e1f --- /dev/null +++ b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02-pinctrl.dtsi @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2024 Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Configure pin control bias mode for uart2 pins */ +&p3_3_scb2_uart_tx { + drive-push-pull; +}; + +&p3_2_scb2_uart_rx { + input-enable; +}; + +&p3_1_scb2_uart_rts { + drive-push-pull; +}; + +&p3_0_scb2_uart_cts { + input-enable; +}; diff --git a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts new file mode 100644 index 00000000000..83825dd8693 --- /dev/null +++ b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2024 Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include "cyw920829m2evk_02-common.dtsi" +#include "cyw920829m2evk_02-pinctrl.dtsi" + +/ { + model = "The Infineon AIROC™ CYW20829 Bluetooth® LE evaluation kit (CYW92089M2EVK-02)"; + compatible = "infineon,cyw920829m2evk_02", "infineon,CYW20829"; + + aliases { + watchdog0 = &watchdog0; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &app_region; + zephyr,console = &uart2; + zephyr,shell-uart = &uart2; + zephyr,bt-hci = &bluetooth; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <3>; +}; + +uart2: &scb2 { + compatible = "infineon,cat1-uart"; + status = "okay"; + current-speed = <115200>; + hw-flow-control; + + pinctrl-0 = <&p3_3_scb2_uart_tx &p3_2_scb2_uart_rx &p3_1_scb2_uart_rts &p3_0_scb2_uart_cts>; + pinctrl-names = "default"; +}; + +&fll0 { + status = "okay"; +}; + +&path_mux0 { + status = "okay"; +}; + +&path_mux1 { + status = "okay"; +}; + +&path_mux2 { + status = "okay"; +}; + +&path_mux3 { + status = "okay"; +}; + +&clk_hf0 { + status = "okay"; + clocks = <&fll0>; +}; + +&clk_hf1 { + status = "okay"; +}; + +&clk_hf2 { + status = "okay"; +}; + +&clk_hf3 { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; + +&bluetooth { + status = "okay"; +}; + +/ { + qspi_flash: qspi_flash@40890000 { + compatible = "infineon,cat1-qspi-flash"; + reg = <0x40890000 0x30000>; + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@8000000 { + compatible = "soc-nv-flash"; + reg = <0x08000000 DT_SIZE_K(512)>; + write-block-size = <1>; + erase-block-size = ; + #address-cells = <1>; + #size-cells = <1>; + + toc2_region: toc2_region@8000000 { + compatible = "zephyr,memory-region", "soc-nv-flash"; + zephyr,memory-region = "APP_HEADER_FLASH"; + reg = <0x08000000 0x50>; + }; + bootstrap_region: bootstrap_region@8000050 { + compatible = "zephyr,memory-region", "soc-nv-flash"; + zephyr,memory-region = "BOOTSTRAP_FLASH"; + reg = <0x08000050 DT_SIZE_K(12)>; + }; + app_region: app_region@8003050 { + compatible = "soc-nv-flash"; + reg = <0x08003050 0x6CFB0>; /* 435kb */ + }; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: storage_partition@60000 { + compatible = "soc-nv-flash"; + reg = <0x60000 DT_SIZE_K(64)>; + }; + }; + }; + }; +}; diff --git a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.yaml b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.yaml new file mode 100644 index 00000000000..a02da7d1937 --- /dev/null +++ b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.yaml @@ -0,0 +1,24 @@ +# +# Copyright (c) 2024 Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: cyw920829m2evk_02 +name: The Infineon AIROC™ CYW20829 Bluetooth® LE evaluation kit (CYW92089M2EVK-02) +type: mcu +arch: arm +ram: 1024 +flash: 2048 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - uart + - clock_control + - bluetooth + - watchdog + - spi + - i2c + +vendor: infineon diff --git a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig new file mode 100644 index 00000000000..fea80ce0119 --- /dev/null +++ b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig @@ -0,0 +1,34 @@ +# +# Copyright (c) 2024 Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 +# + +# General configuration +CONFIG_CORTEX_M_SYSTICK=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_OUTPUT_BIN=y + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable pin controller +CONFIG_PINCTRL=y + +# Enable GPIO driver +CONFIG_GPIO=y + +# Enable clock controller +CONFIG_CLOCK_CONTROL=y + +# Main Stack Size +CONFIG_MAIN_STACK_SIZE=2048 + +# Enable code/data relocation to move SMIF driver into RAM +CONFIG_CODE_DATA_RELOCATION=y diff --git a/boards/infineon/cyw920829m2evk_02/doc/img/cyw920829m2evk_02.webp b/boards/infineon/cyw920829m2evk_02/doc/img/cyw920829m2evk_02.webp new file mode 100644 index 00000000000..a93d6f39696 Binary files /dev/null and b/boards/infineon/cyw920829m2evk_02/doc/img/cyw920829m2evk_02.webp differ diff --git a/boards/infineon/cyw920829m2evk_02/doc/index.rst b/boards/infineon/cyw920829m2evk_02/doc/index.rst new file mode 100644 index 00000000000..cac878c01a5 --- /dev/null +++ b/boards/infineon/cyw920829m2evk_02/doc/index.rst @@ -0,0 +1,160 @@ +.. _cyw920829m2evk_02: + +INFINEON CYW920829M2EVK-02 +############################ + +Overview +******** + +The AIROC™ CYW20829 Bluetooth® LE MCU Evaluation Kit (CYW920829M2EVK-02) with its included on-board peripherals enables evaluation, prototyping, and development of a wide array of Bluetooth® Low Energy applications, all on Infineon's low power, high performance AIROC™ CYW20829. The AIROC™ CYW20829's robust RF performance and 10 dBm TX output power without an external power amplifier (PA). This provides enough link budget for the entire spectrum of Bluetooth® LE use cases including industrial IoT applications, smart home, asset tracking, beacons and sensors, and medical devices. + +The system features Dual Arm® Cortex® - M33s for powering the MCU and Bluetooth subsystem with programmable and reconfigurable analog and digital blocks. In addition, on the kit, there is a suite of on-board peripherals including six-axis inertial measurement unit (IMU), thermistor, analog mic, user programmable buttons (2), LEDs (2), and RGB LED. There is also extensive GPIO support with extended headers and Arduino Uno R3 compatibility for third-party shields. + +.. image:: img/cyw920829m2evk_02.webp + :align: center + :alt: CYW920829M2EVK_02 + +Hardware +******** + +For more information about the CYW20829 SoC and CYW920829M2EVK-02 board: + +- `CYW20829 SoC Website`_ +- `CYW920829M2EVK-02 Board Website`_ + +Kit Features: +============= + +- AIROC™ CYW20829 Bluetooth® LE MCU in 56 pin QFN package +- Arduino compatible headers for hardware expansion +- On-board sensors - 6-axis IMU, Thermistor, Infineon analog microphone, and Infineon digital microphone +- User switches, RGB LED and user LEDs +- USB connector for power, programming and USB-UART bridge + +Kit Contents: +============= + +- CYW20829 evaluation board (CYW9BTM2BASE3+CYW920829M2IPA2) +- USB Type-A to Micro-B cable +- Six jumper wires (five inches each) +- Quick start guide + + +Supported Features +================== + +The board configuration supports the following hardware features: + ++-----------+------------+-----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=======================+ +| NVIC | on-chip | nested vectored | +| | | interrupt controller | ++-----------+------------+-----------------------+ +| SYSTICK | on-chip | system clock | ++-----------+------------+-----------------------+ +| GPIO | on-chip | GPIO | ++-----------+------------+-----------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-----------------------+ + + +The default configuration can be found in the Kconfig + +:zephyr_file:`boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig` + +System Clock +============ + +The AIROC™ CYW20829 Bluetooth® MCU SoC is configured to use the internal IMO+FLL as a source for +the system clock. Other sources for the system clock are provided in the SOC, depending on your +system requirements. + +Fetch Binary Blobs +****************** + +cyw920829m2evk_02 board requires fetch binary files (e.g Bluetooth controller firmware). + +To fetch Binary Blobs: + +.. code-block:: console + + west blobs fetch hal_infineon + +Build blinking led sample +************************* + +Here is an example for building the :zephyr:code-sample:`blinky` sample application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: cyw920829m2evk_02 + :goals: build + +Programming and Debugging +************************* + +The CYW920829M2EVK-02 includes an onboard programmer/debugger (`KitProg3`_) to provide debugging, flash programming, and serial communication over USB. Flash and debug commands use OpenOCD and require a custom Infineon OpenOCD version, that supports KitProg3, to be installed. + +Infineon OpenOCD Installation +============================= + +Both the full `ModusToolbox`_ and the `ModusToolbox Programming Tools`_ packages include Infineon OpenOCD. Installing either of these packages will also install Infineon OpenOCD. If neither package is installed, a minimal installation can be done by downloading the `Infineon OpenOCD`_ release for your system and manually extract the files to a location of your choice. + +.. note:: Linux requires device access rights to be set up for KitProg3. This is handled automatically by the ModusToolbox and ModusToolbox Programming Tools installations. When doing a minimal installation, this can be done manually by executing the script ``openocd/udev_rules/install_rules.sh``. + +West Commands +============= + +The path to the installed Infineon OpenOCD executable must be available to the ``west`` tool commands. There are multiple ways of doing this. The example below uses a permanent CMake argument to set the CMake variable ``OPENOCD``. + + .. tabs:: + .. group-tab:: Windows + + .. code-block:: shell + + # Run west config once to set permanent CMake argument + west config build.cmake-args -- -DOPENOCD=path/to/infineon/openocd/bin/openocd.exe + + # Do a pristine build once after setting CMake argument + west build -b cyw920829m2evk_02 -p always samples/basic/blinky + + west flash + west debug + + .. group-tab:: Linux + + .. code-block:: shell + + # Run west config once to set permanent CMake argument + west config build.cmake-args -- -DOPENOCD=path/to/infineon/openocd/bin/openocd + + # Do a pristine build once after setting CMake argument + west build -b cyw920829m2evk_02 -p always samples/basic/blinky + + west flash + west debug + +Once the gdb console starts after executing the west debug command, you may now set breakpoints and perform other standard GDB debugging on the CYW20829 CM33 core. + +.. _CYW20829 SoC Website: + https://www.infineon.com/cms/en/product/wireless-connectivity/airoc-bluetooth-le-bluetooth-multiprotocol/airoc-bluetooth-le/cyw20829/ + +.. _CYW920829M2EVK-02 Board Website: + https://www.infineon.com/cms/en/product/evaluation-boards/cyw920829m2evk-02/ + +.. _CYW920829M2EVK-02 BT User Guide: + https://www.infineon.com/cms/en/product/wireless-connectivity/airoc-bluetooth-le-bluetooth-multiprotocol/airoc-bluetooth-le/cyw20829/#!?fileId=8ac78c8c8929aa4d018a16f726c46b26 + +.. _ModusToolbox: + https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox + +.. _ModusToolbox Programming Tools: + https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolboxprogtools + +.. _Infineon OpenOCD: + https://github.com/Infineon/openocd/releases/latest + +.. _KitProg3: + https://github.com/Infineon/KitProg3 diff --git a/boards/infineon/cyw920829m2evk_02/support/openocd.cfg b/boards/infineon/cyw920829m2evk_02/support/openocd.cfg new file mode 100644 index 00000000000..fe70fb383a8 --- /dev/null +++ b/boards/infineon/cyw920829m2evk_02/support/openocd.cfg @@ -0,0 +1,14 @@ +# +# Copyright (c) 2018 Linaro Limited. +# +# SPDX-License-Identifier: Apache-2.0 + +source [find interface/kitprog3.cfg] + +transport select swd + +source [find target/cyw20829.cfg] + +if { [info exists _ZEPHYR_BOARD_SERIAL] } { + adapter serial $_ZEPHYR_BOARD_SERIAL +} diff --git a/boards/infineon/cyw920829m2evk_02/support/qspi_config.cfg b/boards/infineon/cyw920829m2evk_02/support/qspi_config.cfg new file mode 100644 index 00000000000..f702d5409dc --- /dev/null +++ b/boards/infineon/cyw920829m2evk_02/support/qspi_config.cfg @@ -0,0 +1,29 @@ +################################################################################ +# File Name: qspi_config.cfg +# +# Description: +# This file contains a SMIF Bank layout for use with OpenOCD. +# This file was automatically generated and should not be modified. +# QSPI Configurator: 4.22.0.1756 +# +################################################################################ +# Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or +# an affiliate of Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + +set SMIF_BANKS { + 0 {addr 0x60000000 size 0x100000 psize 0x0000100 esize 0x0001000} +} diff --git a/boards/infineon/xmc45_relax_kit/doc/index.rst b/boards/infineon/xmc45_relax_kit/doc/index.rst index 6d75146046e..621fc1cc83e 100644 --- a/boards/infineon/xmc45_relax_kit/doc/index.rst +++ b/boards/infineon/xmc45_relax_kit/doc/index.rst @@ -63,6 +63,8 @@ The Relax Kit development board configuration supports the following hardware fe +-----------+------------+-----------------------+ | PTP | on-chip | ethernet | +-----------+------------+-----------------------+ +| RTC | on-chip | rtc | ++-----------+------------+-----------------------+ More details about the supported peripherals are available in `XMC4500 TRM`_ Other hardware features are not currently supported by the Zephyr kernel. @@ -72,7 +74,7 @@ Building and Flashing Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -82,7 +84,7 @@ Here is an example for the :ref:`hello_world` application. Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/infineon/xmc45_relax_kit/xmc45_relax_kit.dts b/boards/infineon/xmc45_relax_kit/xmc45_relax_kit.dts index feb0a8e5aba..b8ee566c90b 100644 --- a/boards/infineon/xmc45_relax_kit/xmc45_relax_kit.dts +++ b/boards/infineon/xmc45_relax_kit/xmc45_relax_kit.dts @@ -23,6 +23,7 @@ die-temp0 = &die_temp; pwm-led0 = &pwm_led1; watchdog0 = &wdt0; + rtc = &rtc; }; leds { @@ -162,3 +163,7 @@ reg = <0>; }; }; + +&rtc { + status = "okay"; +}; diff --git a/boards/infineon/xmc45_relax_kit/xmc45_relax_kit.yaml b/boards/infineon/xmc45_relax_kit/xmc45_relax_kit.yaml index 031d9dc5a6c..fde3084c862 100644 --- a/boards/infineon/xmc45_relax_kit/xmc45_relax_kit.yaml +++ b/boards/infineon/xmc45_relax_kit/xmc45_relax_kit.yaml @@ -14,6 +14,7 @@ supported: - uart - watchdog - netif:eth + - rtc ram: 160 flash: 1024 vendor: infineon diff --git a/boards/infineon/xmc47_relax_kit/doc/index.rst b/boards/infineon/xmc47_relax_kit/doc/index.rst index 8fb2ce9997a..57eb28efaed 100644 --- a/boards/infineon/xmc47_relax_kit/doc/index.rst +++ b/boards/infineon/xmc47_relax_kit/doc/index.rst @@ -66,6 +66,8 @@ The Relax Kit development board configuration supports the following hardware fe +-----------+------------+-----------------------+ | PTP | on-chip | ethernet | +-----------+------------+-----------------------+ +| RTC | on-chip | rtc | ++-----------+------------+-----------------------+ More details about the supported peripherals are available in `XMC4700 TRM`_ Other hardware features are not currently supported by the Zephyr kernel. @@ -75,7 +77,7 @@ Building and Flashing Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -85,7 +87,7 @@ Here is an example for the :ref:`hello_world` application. Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/infineon/xmc47_relax_kit/xmc47_relax_kit.dts b/boards/infineon/xmc47_relax_kit/xmc47_relax_kit.dts index ec8879bcb40..93dac050b92 100644 --- a/boards/infineon/xmc47_relax_kit/xmc47_relax_kit.dts +++ b/boards/infineon/xmc47_relax_kit/xmc47_relax_kit.dts @@ -22,6 +22,7 @@ die-temp0 = &die_temp; pwm-led0 = &pwm_led1; watchdog0 = &wdt0; + rtc = &rtc; }; leds { @@ -201,6 +202,10 @@ }; }; +&rtc { + status = "okay"; +}; + &can { clock-prescaler = <6>; }; diff --git a/boards/infineon/xmc47_relax_kit/xmc47_relax_kit.yaml b/boards/infineon/xmc47_relax_kit/xmc47_relax_kit.yaml index 72fa356ef0c..4682227c7cd 100644 --- a/boards/infineon/xmc47_relax_kit/xmc47_relax_kit.yaml +++ b/boards/infineon/xmc47_relax_kit/xmc47_relax_kit.yaml @@ -16,6 +16,7 @@ supported: - arduino_serial - watchdog - netif:eth + - rtc ram: 352 flash: 2048 vendor: infineon diff --git a/boards/innblue/innblue21/doc/index.rst b/boards/innblue/innblue21/doc/index.rst index 333db42bfd9..0990c395c62 100644 --- a/boards/innblue/innblue21/doc/index.rst +++ b/boards/innblue/innblue21/doc/index.rst @@ -119,7 +119,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/innblue/innblue21/innblue21_common.dtsi b/boards/innblue/innblue21/innblue21_common.dtsi index 53160a680c6..fbe58ffbe22 100644 --- a/boards/innblue/innblue21/innblue21_common.dtsi +++ b/boards/innblue/innblue21/innblue21_common.dtsi @@ -159,47 +159,5 @@ pinctrl-names = "default", "sleep"; }; -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x10000>; - }; - slot0_partition: partition@10000 { - label = "image-0"; - }; - slot0_ns_partition: partition@50000 { - label = "image-0-nonsecure"; - }; - slot1_partition: partition@80000 { - label = "image-1"; - }; - slot1_ns_partition: partition@c0000 { - label = "image-1-nonsecure"; - }; - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; - -/ { - /* SRAM allocated and used by the BSD library */ - sram0_bsd: memory@20010000 { - compatible = "mmio-sram"; - }; - - /* SRAM allocated to the Non-Secure image */ - sram0_ns: memory@20020000 { - compatible = "mmio-sram"; - }; -}; - -/* Include partition configuration file */ -#include "innblue21_partition_conf.dtsi" +/* Include default memory partition configuration file */ +#include diff --git a/boards/innblue/innblue21/innblue21_nrf9160_ns.dts b/boards/innblue/innblue21/innblue21_nrf9160_ns.dts index 2ca97a7b162..2afcddfd579 100644 --- a/boards/innblue/innblue21/innblue21_nrf9160_ns.dts +++ b/boards/innblue/innblue21/innblue21_nrf9160_ns.dts @@ -11,7 +11,7 @@ / { chosen { zephyr,flash = &flash0; - zephyr,sram = &sram0_ns; + zephyr,sram = &sram0_ns_app; zephyr,code-partition = &slot0_ns_partition; }; }; diff --git a/boards/innblue/innblue21/innblue21_partition_conf.dtsi b/boards/innblue/innblue21/innblue21_partition_conf.dtsi deleted file mode 100644 index 2c64ba67a8a..00000000000 --- a/boards/innblue/innblue21/innblue21_partition_conf.dtsi +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2020 InnBlue - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* - * Default Flash planning for nRF9160_innblue21. - * - * Zephyr build for nRF9160 with ARM TrustZone-M support, - * implies building Secure and Non-Secure Zephyr images. - * - * Secure image will be placed, by default, in flash0 - * (or in slot0, if MCUboot is present). - * Secure image will use sram0 for system memory. - * - * Non-Secure image will be placed in slot0_ns, and use - * sram0_ns for system memory. - * - * Note that the Secure image only requires knowledge of - * the beginning of the Non-Secure image (not its size). - */ - -&slot0_partition { - reg = <0x00010000 0x40000>; -}; - -&slot0_ns_partition { - reg = <0x00050000 0x30000>; -}; - -&slot1_partition { - reg = <0x00080000 0x40000>; -}; - -&slot1_ns_partition { - reg = <0x000c0000 0x30000>; -}; - -/* Default SRAM planning when building for nRF9160 with - * ARM TrustZone-M support - * - Lowest 64 kB SRAM allocated to Secure image (sram0). - * - 64 kB SRAM reserved for and used by the BSD socket - * library. - * - Upper 128 kB allocated to Non-Secure image (sram0_ns). - */ - -&sram0 { - reg = <0x20000000 DT_SIZE_K(64)>; -}; - -&sram0_bsd { - reg = <0x20010000 DT_SIZE_K(64)>; -}; - -&sram0_ns { - reg = <0x20020000 DT_SIZE_K(128)>; -}; diff --git a/boards/innblue/innblue22/doc/index.rst b/boards/innblue/innblue22/doc/index.rst index 862c42cdd22..3485ad4de77 100644 --- a/boards/innblue/innblue22/doc/index.rst +++ b/boards/innblue/innblue22/doc/index.rst @@ -119,7 +119,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/innblue/innblue22/innblue22_common.dtsi b/boards/innblue/innblue22/innblue22_common.dtsi index de57fa1ced4..6ba2b69bf72 100644 --- a/boards/innblue/innblue22/innblue22_common.dtsi +++ b/boards/innblue/innblue22/innblue22_common.dtsi @@ -162,48 +162,5 @@ pinctrl-names = "default", "sleep"; }; -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x10000>; - }; - slot0_partition: partition@10000 { - label = "image-0"; - }; - slot0_ns_partition: partition@50000 { - label = "image-0-nonsecure"; - }; - slot1_partition: partition@80000 { - label = "image-1"; - }; - slot1_ns_partition: partition@c0000 { - label = "image-1-nonsecure"; - }; - /* 0xf0000 to 0xf7fff reserved for TF-M partitions */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; - -/ { - /* SRAM allocated and used by the BSD library */ - sram0_bsd: memory@20010000 { - compatible = "mmio-sram"; - }; - - /* SRAM allocated to the Non-Secure image */ - sram0_ns: memory@20020000 { - compatible = "mmio-sram"; - }; -}; - -/* Include partition configuration file */ -#include "innblue22_partition_conf.dtsi" +/* Include default memory partition configuration file */ +#include diff --git a/boards/innblue/innblue22/innblue22_partition_conf.dtsi b/boards/innblue/innblue22/innblue22_partition_conf.dtsi deleted file mode 100644 index b14640a02ec..00000000000 --- a/boards/innblue/innblue22/innblue22_partition_conf.dtsi +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2020 InnBlue - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* - * Default Flash planning for nRF9160_innblue22. - * - * Zephyr build for nRF9160 with ARM TrustZone-M support, - * implies building Secure and Non-Secure Zephyr images. - * - * Secure image will be placed, by default, in flash0 - * (or in slot0, if MCUboot is present). - * Secure image will use sram0 for system memory. - * - * Non-Secure image will be placed in slot0_ns, and use - * sram0_ns for system memory. - * - * Note that the Secure image only requires knowledge of - * the beginning of the Non-Secure image (not its size). - */ - -&slot0_partition { - reg = <0x00010000 0x40000>; -}; - -&slot0_ns_partition { - reg = <0x00050000 0x30000>; -}; - -&slot1_partition { - reg = <0x00080000 0x40000>; -}; - -&slot1_ns_partition { - reg = <0x000c0000 0x30000>; -}; - -/* Default SRAM planning when building for nRF9160 with - * ARM TrustZone-M support - * - Lowest 64 kB SRAM allocated to Secure image (sram0). - * - 64 kB SRAM reserved for and used by the BSD socket - * library. - * - Upper 128 kB allocated to Non-Secure image (sram0_ns). - */ - -&sram0 { - reg = <0x20000000 DT_SIZE_K(64)>; -}; - -&sram0_bsd { - reg = <0x20010000 DT_SIZE_K(64)>; -}; - -&sram0_ns { - reg = <0x20020000 DT_SIZE_K(128)>; -}; diff --git a/boards/intel/adl/CMakeLists.txt b/boards/intel/adl/CMakeLists.txt index 36ddcdf9d13..6a250ca315c 100644 --- a/boards/intel/adl/CMakeLists.txt +++ b/boards/intel/adl/CMakeLists.txt @@ -6,7 +6,7 @@ set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py -c ${CMAKE_C_COMPILER} -o ${CMAKE_OBJCOPY} - -i ${ZEPHYR_BASE}/include + -i ${ZEPHYR_BASE}/include ${PROJECT_BINARY_DIR}/include/generated -f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf $<$:--verbose> WORKING_DIRECTORY ${PROJECT_BINARY_DIR} diff --git a/boards/intel/adl/Kconfig.defconfig b/boards/intel/adl/Kconfig.defconfig index 518f0c01ee2..3a6bcaf9ce0 100644 --- a/boards/intel/adl/Kconfig.defconfig +++ b/boards/intel/adl/Kconfig.defconfig @@ -16,6 +16,8 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC if APIC_TIMER config APIC_TIMER_IRQ default 24 +endif +if APIC_TIMER_TSC config APIC_TIMER_TSC_M default 3 config APIC_TIMER_TSC_N diff --git a/boards/intel/adsp/Kconfig.intel_adsp b/boards/intel/adsp/Kconfig.intel_adsp index 2e4c9844720..67c3989fe32 100644 --- a/boards/intel/adsp/Kconfig.intel_adsp +++ b/boards/intel/adsp/Kconfig.intel_adsp @@ -5,4 +5,8 @@ config BOARD_INTEL_ADSP select SOC_INTEL_CAVS_V25 if BOARD_INTEL_ADSP_CAVS25 select SOC_INTEL_CAVS_V25 if BOARD_INTEL_ADSP_CAVS25_TGPH select SOC_INTEL_ACE15_MTPM if BOARD_INTEL_ADSP_ACE15_MTPM + select SOC_INTEL_ACE15_MTPM if BOARD_INTEL_ADSP_ACE15_MTPM_SIM select SOC_INTEL_ACE20_LNL if BOARD_INTEL_ADSP_ACE20_LNL + select SOC_INTEL_ACE20_LNL if BOARD_INTEL_ADSP_ACE20_LNL_SIM + select SOC_INTEL_ACE30_PTL if BOARD_INTEL_ADSP_ACE30_PTL + select SOC_INTEL_ACE30_PTL if BOARD_INTEL_ADSP_ACE30_PTL_SIM diff --git a/boards/intel/adsp/board.cmake b/boards/intel/adsp/board.cmake index bcdfc328646..0add6586426 100644 --- a/boards/intel/adsp/board.cmake +++ b/boards/intel/adsp/board.cmake @@ -23,7 +23,7 @@ if(CONFIG_BOARD_INTEL_ADSP_CAVS25 OR CONFIG_BOARD_INTEL_ADSP_CAVS25_TGPH) board_finalize_runner_args(intel_adsp) -elseif(CONFIG_BOARD_INTEL_ADSP_ACE15_MTPM) +elseif(CONFIG_BOARD_INTEL_ADSP_ACE15_MTPM OR CONFIG_BOARD_INTEL_ADSP_ACE15_MTPM_SIM) board_set_rimage_target(mtl) @@ -31,7 +31,7 @@ elseif(CONFIG_BOARD_INTEL_ADSP_ACE15_MTPM) board_finalize_runner_args(intel_adsp) -elseif(CONFIG_BOARD_INTEL_ADSP_ACE20_LNL) +elseif(CONFIG_BOARD_INTEL_ADSP_ACE20_LNL OR CONFIG_BOARD_INTEL_ADSP_ACE20_LNL_SIM) set(SUPPORTED_EMU_PLATFORMS acesim) @@ -39,4 +39,12 @@ elseif(CONFIG_BOARD_INTEL_ADSP_ACE20_LNL) set(RIMAGE_SIGN_KEY "otc_private_key_3k.pem" CACHE STRING "default in ace20_lnl/board.cmake") +elseif(CONFIG_BOARD_INTEL_ADSP_ACE30_PTL OR CONFIG_BOARD_INTEL_ADSP_ACE30_PTL_SIM) + + board_set_rimage_target(ptl) + + set(RIMAGE_SIGN_KEY "otc_private_key.pem" CACHE STRING "default rimage key") + + board_finalize_runner_args(intel_adsp) + endif() diff --git a/boards/intel/adsp/board.yml b/boards/intel/adsp/board.yml index 9295ae0c3eb..5eadeb4fe1a 100644 --- a/boards/intel/adsp/board.yml +++ b/boards/intel/adsp/board.yml @@ -6,4 +6,11 @@ boards: variants: - name: 'tgph' - name: ace15_mtpm + variants: + - name: 'sim' - name: ace20_lnl + variants: + - name: 'sim' + - name: ace30_ptl + variants: + - name: 'sim' diff --git a/boards/intel/adsp/intel_adsp_ace15_mtpm_sim.dts b/boards/intel/adsp/intel_adsp_ace15_mtpm_sim.dts new file mode 100644 index 00000000000..87d4cfaaeca --- /dev/null +++ b/boards/intel/adsp/intel_adsp_ace15_mtpm_sim.dts @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +#include "intel_adsp_ace15_mtpm.dts" diff --git a/boards/intel/adsp/intel_adsp_ace15_mtpm_sim.yaml b/boards/intel/adsp/intel_adsp_ace15_mtpm_sim.yaml new file mode 100644 index 00000000000..418849ec8a4 --- /dev/null +++ b/boards/intel/adsp/intel_adsp_ace15_mtpm_sim.yaml @@ -0,0 +1,14 @@ +identifier: intel_adsp/ace15_mtpm/sim +name: ACE 1.5 Meteor Lake M Audio DSP +type: sim +simulation: custom +arch: xtensa +toolchain: + - xcc + - zephyr + - xt-clang +testing: + timeout_multiplier: 4 + ignore_tags: + - net + - bluetooth diff --git a/boards/intel/adsp/intel_adsp_ace15_mtpm_sim_defconfig b/boards/intel/adsp/intel_adsp_ace15_mtpm_sim_defconfig new file mode 100644 index 00000000000..7a051327234 --- /dev/null +++ b/boards/intel/adsp/intel_adsp_ace15_mtpm_sim_defconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_INTEL_ADSP_SIM=y +CONFIG_INTEL_ADSP_SIM_NO_SECONDARY_CORE_FLOW=y + +CONFIG_GEN_ISR_TABLES=y +CONFIG_GEN_IRQ_VECTOR_TABLE=n + +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_MM_DRV=y +CONFIG_CRYPTO=y + +CONFIG_DCACHE_LINE_SIZE=64 diff --git a/boards/intel/adsp/intel_adsp_ace20_lnl_sim.dts b/boards/intel/adsp/intel_adsp_ace20_lnl_sim.dts new file mode 100644 index 00000000000..6e316305941 --- /dev/null +++ b/boards/intel/adsp/intel_adsp_ace20_lnl_sim.dts @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +#include "intel_adsp_ace20_lnl.dts" diff --git a/boards/intel/adsp/intel_adsp_ace20_lnl_sim.yaml b/boards/intel/adsp/intel_adsp_ace20_lnl_sim.yaml new file mode 100644 index 00000000000..cde563043da --- /dev/null +++ b/boards/intel/adsp/intel_adsp_ace20_lnl_sim.yaml @@ -0,0 +1,13 @@ +identifier: intel_adsp/ace20_lnl/sim +name: ACE 2.0 Lunar Lake Audio DSP +type: sim +simulation: custom +arch: xtensa +toolchain: + - xcc + - xt-clang +testing: + timeout_multiplier: 6 + ignore_tags: + - net + - bluetooth diff --git a/boards/intel/adsp/intel_adsp_ace20_lnl_sim_defconfig b/boards/intel/adsp/intel_adsp_ace20_lnl_sim_defconfig new file mode 100644 index 00000000000..5f03e403e3c --- /dev/null +++ b/boards/intel/adsp/intel_adsp_ace20_lnl_sim_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_INTEL_ADSP_SIM=y +CONFIG_GEN_ISR_TABLES=y +CONFIG_GEN_IRQ_VECTOR_TABLE=n + +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_MM_DRV=y diff --git a/boards/intel/adsp/intel_adsp_ace30_ptl.dts b/boards/intel/adsp/intel_adsp_ace30_ptl.dts new file mode 100644 index 00000000000..9e25712bc2c --- /dev/null +++ b/boards/intel/adsp/intel_adsp_ace30_ptl.dts @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + model = "intel_adsp_ace30_ptl"; + compatible = "intel"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &mem_window3; + }; +}; diff --git a/boards/intel/adsp/intel_adsp_ace30_ptl.yaml b/boards/intel/adsp/intel_adsp_ace30_ptl.yaml new file mode 100644 index 00000000000..bdfe837bd08 --- /dev/null +++ b/boards/intel/adsp/intel_adsp_ace30_ptl.yaml @@ -0,0 +1,10 @@ +identifier: intel_adsp/ace30_ptl +name: ACE 3.0 Panther Lake Audio DSP +type: mcu +arch: xtensa +toolchain: + - xt-clang +testing: + ignore_tags: + - net + - bluetooth diff --git a/boards/intel/adsp/intel_adsp_ace30_ptl_defconfig b/boards/intel/adsp/intel_adsp_ace30_ptl_defconfig new file mode 100644 index 00000000000..913d2a8c3e3 --- /dev/null +++ b/boards/intel/adsp/intel_adsp_ace30_ptl_defconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=4096 + +CONFIG_GEN_ISR_TABLES=y +CONFIG_GEN_IRQ_VECTOR_TABLE=n + +CONFIG_BUILD_OUTPUT_BIN=n + +CONFIG_DAI_SSP_HAS_POWER_CONTROL=y + +CONFIG_DCACHE_LINE_SIZE=64 diff --git a/boards/intel/adsp/intel_adsp_ace30_ptl_sim.dts b/boards/intel/adsp/intel_adsp_ace30_ptl_sim.dts new file mode 100644 index 00000000000..90fa43821ac --- /dev/null +++ b/boards/intel/adsp/intel_adsp_ace30_ptl_sim.dts @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2022 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + model = "intel_adsp_ace30_ptl_sim"; + compatible = "intel"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &mem_window3; + }; +}; diff --git a/boards/intel/adsp/intel_adsp_ace30_ptl_sim.yaml b/boards/intel/adsp/intel_adsp_ace30_ptl_sim.yaml new file mode 100644 index 00000000000..3bf48d4c383 --- /dev/null +++ b/boards/intel/adsp/intel_adsp_ace30_ptl_sim.yaml @@ -0,0 +1,12 @@ +identifier: intel_adsp/ace30_ptl/sim +name: ACE 3.0 Panther Lake Audio DSP +type: sim +simulation: custom +arch: xtensa +toolchain: + - xt-clang +testing: + timeout_multiplier: 8 + ignore_tags: + - net + - bluetooth diff --git a/boards/intel/adsp/intel_adsp_ace30_ptl_sim_defconfig b/boards/intel/adsp/intel_adsp_ace30_ptl_sim_defconfig new file mode 100644 index 00000000000..429223286bf --- /dev/null +++ b/boards/intel/adsp/intel_adsp_ace30_ptl_sim_defconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_INTEL_ADSP_SIM=y +CONFIG_INTEL_ADSP_SIM_NO_SECONDARY_CORE_FLOW=y + +CONFIG_GEN_ISR_TABLES=y +CONFIG_GEN_IRQ_VECTOR_TABLE=n + +CONFIG_BUILD_OUTPUT_BIN=n + +CONFIG_DAI_SSP_HAS_POWER_CONTROL=y + +CONFIG_DCACHE_LINE_SIZE=64 diff --git a/boards/intel/ehl/CMakeLists.txt b/boards/intel/ehl/CMakeLists.txt index 36ddcdf9d13..6a250ca315c 100644 --- a/boards/intel/ehl/CMakeLists.txt +++ b/boards/intel/ehl/CMakeLists.txt @@ -6,7 +6,7 @@ set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py -c ${CMAKE_C_COMPILER} -o ${CMAKE_OBJCOPY} - -i ${ZEPHYR_BASE}/include + -i ${ZEPHYR_BASE}/include ${PROJECT_BINARY_DIR}/include/generated -f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf $<$:--verbose> WORKING_DIRECTORY ${PROJECT_BINARY_DIR} diff --git a/boards/intel/ehl/Kconfig.defconfig b/boards/intel/ehl/Kconfig.defconfig index 9e7dcf48a04..8b8c89800da 100644 --- a/boards/intel/ehl/Kconfig.defconfig +++ b/boards/intel/ehl/Kconfig.defconfig @@ -27,6 +27,8 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC if APIC_TIMER config APIC_TIMER_IRQ default 24 +endif +if APIC_TIMER_TSC config APIC_TIMER_TSC_M default 3 config APIC_TIMER_TSC_N diff --git a/boards/intel/ish/Kconfig.defconfig b/boards/intel/ish/Kconfig.defconfig index fdedc70fd29..6112d43c049 100644 --- a/boards/intel/ish/Kconfig.defconfig +++ b/boards/intel/ish/Kconfig.defconfig @@ -9,4 +9,5 @@ config TEST_EXTRA_STACK_SIZE endif # TEST config SYS_CLOCK_TICKS_PER_SEC - default 2048 if HPET_TIMER # HPET is 32768 HZ + default 2048 if HPET_TIMER # HPET timer's frequency is 32768 HZ + default 2000 if APIC_TIMER_TSC # APIC timer's frequency is 19.2 MHZ or 100 MHZ diff --git a/boards/intel/ish/board.cmake b/boards/intel/ish/board.cmake new file mode 100644 index 00000000000..aa4b8ad48ae --- /dev/null +++ b/boards/intel/ish/board.cmake @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +set(SUPPORTED_EMU_PLATFORMS simics) + +if(CONFIG_BOARD_INTEL_ISH_5_8_0) + board_emu_args(simics "project=$ENV{SIMICS_PROJECT}") + board_emu_args(simics "zephyr_elf=${APPLICATION_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME}") + board_emu_args(simics "zephyr_start_address=${CONFIG_SRAM_BASE_ADDRESS}") + include(${ZEPHYR_BASE}/boards/common/simics.board.cmake) +endif() + +board_set_flasher_ifnset(misc-flasher) +board_finalize_runner_args(misc-flasher) diff --git a/boards/intel/ish/intel_ish_5_8_0.yaml b/boards/intel/ish/intel_ish_5_8_0.yaml index 09dd57f5e30..566e7f21c13 100644 --- a/boards/intel/ish/intel_ish_5_8_0.yaml +++ b/boards/intel/ish/intel_ish_5_8_0.yaml @@ -5,6 +5,8 @@ arch: x86 toolchain: - zephyr ram: 640 +simulation: simics +simulation_exec: simics supported: - serial testing: diff --git a/boards/intel/rpl/CMakeLists.txt b/boards/intel/rpl/CMakeLists.txt index 36ddcdf9d13..6a250ca315c 100644 --- a/boards/intel/rpl/CMakeLists.txt +++ b/boards/intel/rpl/CMakeLists.txt @@ -6,7 +6,7 @@ set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py -c ${CMAKE_C_COMPILER} -o ${CMAKE_OBJCOPY} - -i ${ZEPHYR_BASE}/include + -i ${ZEPHYR_BASE}/include ${PROJECT_BINARY_DIR}/include/generated -f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf $<$:--verbose> WORKING_DIRECTORY ${PROJECT_BINARY_DIR} diff --git a/boards/intel/rpl/Kconfig.defconfig b/boards/intel/rpl/Kconfig.defconfig index ca8a7742688..4eb5d8c3126 100644 --- a/boards/intel/rpl/Kconfig.defconfig +++ b/boards/intel/rpl/Kconfig.defconfig @@ -17,6 +17,8 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC if APIC_TIMER config APIC_TIMER_IRQ default 24 +endif +if APIC_TIMER_TSC config APIC_TIMER_TSC_M default 3 config APIC_TIMER_TSC_N diff --git a/boards/intel/rpl/doc/index.rst b/boards/intel/rpl/doc/index.rst index 4c078ab765e..e6bc4015256 100644 --- a/boards/intel/rpl/doc/index.rst +++ b/boards/intel/rpl/doc/index.rst @@ -23,7 +23,7 @@ please refer to `RPL`_. Raptor Lake Customer Reference Board (RPL CRB) is an example implementation of a compact single board computer with high performance for IoT edge devices. The -supported boards are `intel_rpl_s_crb` and `intel_rpl_p_crb`. +supported boards are ``intel_rpl_s_crb`` and ``intel_rpl_p_crb``. These board configurations enable kernel support for the supported Raptor Lake boards. diff --git a/boards/intel/socfpga/agilex5_socdk/doc/index.rst b/boards/intel/socfpga/agilex5_socdk/doc/index.rst index 006ca066251..4208d8b70be 100644 --- a/boards/intel/socfpga/agilex5_socdk/doc/index.rst +++ b/boards/intel/socfpga/agilex5_socdk/doc/index.rst @@ -45,7 +45,7 @@ hardware features: NOTE: TODO, more details on dev kit will be updated as and when available. The default configuration can be found in the defconfig file: - `boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk_defconfig` +:zephyr_file:`boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk_defconfig`. Programming and Debugging ************************* diff --git a/boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk.dts b/boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk.dts index 701401f569b..d2f6c4370a3 100644 --- a/boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk.dts +++ b/boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023, Intel Corporation. + * Copyright (c) 2024, Intel Corporation. * * SPDX-License-Identifier: Apache-2.0 */ @@ -34,3 +34,27 @@ status = "okay"; current-speed = <115200>; }; + +&xgmac0 { + full-duplex-mode-en; + num-dma-ch = <1>; + num-tx-queues = <1>; + num-rx-queues = <1>; + num-tc = <1>; + dma-ch-rdrl = <128>; + dma-ch-tdrl = <128>; + max-speed = <1000>; + max-frame-size = <9018>; + jumbo-pkt-en; + zephyr,random-mac-address; + phy-handle = <&phy0>; +}; + +&mdio0 { + csr-clock-indx = <4>; + + phy0: phy@0 { + compatible = "ethernet-phy"; + reg = <0>; + }; +}; diff --git a/boards/intel/socfpga_std/cyclonev_socdk/cyclonev_socdk.dts b/boards/intel/socfpga_std/cyclonev_socdk/cyclonev_socdk.dts index 5218c62f2c7..a45c0768273 100644 --- a/boards/intel/socfpga_std/cyclonev_socdk/cyclonev_socdk.dts +++ b/boards/intel/socfpga_std/cyclonev_socdk/cyclonev_socdk.dts @@ -63,7 +63,7 @@ status = "okay"; eeprom: eeprom@51 { - compatible = "atmel,at24"; + compatible = "microchip,at24lc32a", "atmel,at24"; status = "okay"; reg = <0x51>; size = <4096>; diff --git a/boards/intel/socfpga_std/cyclonev_socdk/doc/index.rst b/boards/intel/socfpga_std/cyclonev_socdk/doc/index.rst index 752284a63b9..6183491690c 100644 --- a/boards/intel/socfpga_std/cyclonev_socdk/doc/index.rst +++ b/boards/intel/socfpga_std/cyclonev_socdk/doc/index.rst @@ -163,7 +163,7 @@ Flashing Kernel into the board ------------------------------ The usual ``flash`` target will work with the ``cyclonev_socdk`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. ``Important!!!`` : Before flashing the board a ``preloader`` is required, diff --git a/boards/ite/it82xx2_evb/doc/index.rst b/boards/ite/it82xx2_evb/doc/index.rst index e969114180e..d31b989f225 100644 --- a/boards/ite/it82xx2_evb/doc/index.rst +++ b/boards/ite/it82xx2_evb/doc/index.rst @@ -151,7 +151,7 @@ Wiring Building ======== -#. Build :ref:`hello_world` application as you would normally do +#. Build :zephyr:code-sample:`hello_world` application as you would normally do (see :`Zephyr Getting Started Guide`_):. .. zephyr-app-commands:: @@ -220,7 +220,7 @@ Ubuntu $ sudo ~/itetool/ite -f build/zephyr/zephyr.bin .. note:: The source code of ITE tool can be downloaded here: - https://www.ite.com.tw/uploads/product_download/itedlb4-linux-v106.tar.bz2 + https://www.ite.com.tw/upload/2024_01_23/6_20240123162336wu55j1Rjm4.bz2 #. Split first and second terminal windows to view both of them. You should see ``"Hello World! it82xx2_evb"`` in the first terminal window. diff --git a/boards/ite/it8xxx2_evb/doc/index.rst b/boards/ite/it8xxx2_evb/doc/index.rst index 9f345639c48..0e215fddf7e 100644 --- a/boards/ite/it8xxx2_evb/doc/index.rst +++ b/boards/ite/it8xxx2_evb/doc/index.rst @@ -79,7 +79,7 @@ Hardware reworks Before using the it8xxx2_evb, some hardware rework is needed. The HW rework guide can be found in ITE's website. -https://www.ite.com.tw/uploads/product_download/IT81302_MECC_Rework_Guide_0927.pdf +https://www.ite.com.tw/upload/2024_01_15/6_20240115100309cgdjgcLzX3.pdf Programming and debugging on it83202 ************************************ @@ -133,7 +133,7 @@ Wiring Building ======== -#. Build :ref:`hello_world` application as you would normally do +#. Build :zephyr:code-sample:`hello_world` application as you would normally do (see :`Zephyr Getting Started Guide`_):. .. zephyr-app-commands:: @@ -202,7 +202,7 @@ Ubuntu $ sudo ~/itetool/ite -f build/zephyr/zephyr.bin .. note:: The source code of ITE tool can be downloaded here: - https://www.ite.com.tw/uploads/product_download/itedlb4-linux-v106.tar.bz2 + https://www.ite.com.tw/upload/2024_01_23/6_20240123162336wu55j1Rjm4.bz2 #. Split first and second terminal windows to view both of them. You should see ``"Hello World! it8xxx2_evb"`` in the first terminal window. @@ -224,5 +224,5 @@ References .. target-notes:: -.. _ITE's website: http://www.ite.com.tw/en/product/view?mid=149 +.. _ITE's website: https://www.ite.com.tw/en/product/cate2/IT81202 .. _Zephyr Getting Started Guide: https://docs.zephyrproject.org/latest/getting_started/index.html diff --git a/boards/ite/it8xxx2_evb/support/it8xxx2_evb.resc b/boards/ite/it8xxx2_evb/support/it8xxx2_evb.resc index 987fed77bac..5ef1ae4e5bb 100644 --- a/boards/ite/it8xxx2_evb/support/it8xxx2_evb.resc +++ b/boards/ite/it8xxx2_evb/support/it8xxx2_evb.resc @@ -12,6 +12,6 @@ cpu PerformanceInMips 80 macro reset """ - sysbus LoadELF $bin + sysbus LoadELF $elf """ runMacro $reset diff --git a/boards/khadas/edgev/doc/index.rst b/boards/khadas/edgev/doc/index.rst index 2c73d109b09..c6c3e44826a 100644 --- a/boards/khadas/edgev/doc/index.rst +++ b/boards/khadas/edgev/doc/index.rst @@ -41,7 +41,7 @@ Programming and Debugging ************************* Use the following configuration to run basic Zephyr applications and -kernel tests on Khadas Edge-V board. For example, with the :ref:`hello_world`: +kernel tests on Khadas Edge-V board. For example, with the :zephyr:code-sample:`hello_world`: 1. Non-SMP mode diff --git a/boards/kincony/kincony_kc868_a32/doc/index.rst b/boards/kincony/kincony_kc868_a32/doc/index.rst index a6117bec55e..ccc8676f512 100644 --- a/boards/kincony/kincony_kc868_a32/doc/index.rst +++ b/boards/kincony/kincony_kc868_a32/doc/index.rst @@ -58,7 +58,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``kincony_kc868_a32`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: diff --git a/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_appcpu.dts b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_appcpu.dts index 7940256ff29..4717ca7fa62 100644 --- a/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_appcpu.dts +++ b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_appcpu.dts @@ -18,14 +18,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &ipm0 { status = "okay"; }; diff --git a/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_procpu.dts b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_procpu.dts index 4bbe6815278..be7da2765ef 100644 --- a/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_procpu.dts +++ b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_procpu.dts @@ -27,15 +27,6 @@ }; }; -&cpu0 { - clock-frequency = ; - cpu-power-states = <&light_sleep &deep_sleep>; -}; - -&cpu1 { - clock-frequency = ; -}; - &gpio0 { status = "okay"; }; diff --git a/boards/lairdconnect/bl5340_dvk/CMakeLists.txt b/boards/lairdconnect/bl5340_dvk/CMakeLists.txt deleted file mode 100644 index 3c648fe1afa..00000000000 --- a/boards/lairdconnect/bl5340_dvk/CMakeLists.txt +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2019 Nordic Semiconductor ASA. -# Copyright (c) 2021-2023 Laird Connectivity. -# SPDX-License-Identifier: Apache-2.0 - -if((CONFIG_BOARD_BL5340_DVK_NRF5340_CPUAPP OR CONFIG_BOARD_BL5340_DVK_NRF5340_CPUAPP_NS) - AND CONFIG_BOARD_ENABLE_CPUNET) - zephyr_library() - zephyr_library_sources(bl5340_dvk_nrf5340_cpunet_reset.c) - - if(CONFIG_BUILD_WITH_TFM) - zephyr_library_include_directories( - $/api_ns/interface/include - ) - endif() -endif() diff --git a/boards/lairdconnect/bl5340_dvk/Kconfig b/boards/lairdconnect/bl5340_dvk/Kconfig deleted file mode 100644 index da61ea66547..00000000000 --- a/boards/lairdconnect/bl5340_dvk/Kconfig +++ /dev/null @@ -1,62 +0,0 @@ -# BL5340-DVK board configuration - -# Copyright (c) 2019-2021 Nordic Semiconductor ASA -# Copyright (c) 2021-2023 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_BL5340_DVK_NRF5340_CPUAPP || BOARD_BL5340_DVK_NRF5340_CPUAPP_NS - -config BOARD_ENABLE_DCDC_APP - bool "Application MCU DCDC converter" - select SOC_DCDC_NRF53X_APP - default y - -config BOARD_ENABLE_DCDC_NET - bool "Network MCU DCDC converter" - select SOC_DCDC_NRF53X_NET - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF53X_HV - default y - -config BOARD_ENABLE_CPUNET - bool "NRF53 Network MCU" - select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ - $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) - help - This option enables releasing the Network 'force off' signal, which - as a consequence will power up the Network MCU during system boot. - Additionally, the option allocates GPIO pins that will be used by UARTE - of the Network MCU. - Note: GPIO pin allocation can only be configured by the secure Application - MCU firmware, so when this option is used with the non-secure version of - the board, the application needs to take into consideration, that the - secure firmware image must already have configured GPIO allocation for the - Network MCU. - default y if (BT || NRF_802154_SER_HOST) - -config DOMAIN_CPUNET_BOARD - string - default "bl5340_dvk/nrf5340/cpunet" - depends on BOARD_ENABLE_CPUNET - help - The board which will be used for CPUNET domain when creating a multi - image application where one or more images should be located on - another board. For example hci_ipc on the bl5340_dvk_cpunet for - Bluetooth applications. - -endif # BOARD_BL5340_DVK_NRF5340_CPUAPP || BOARD_BL5340_DVK_NRF5340_CPUAPP_NS - -if BOARD_BL5340_DVK_NRF5340_CPUNET - -config DOMAIN_CPUAPP_BOARD - string - default "bl5340_dvk/nrf5340/cpuapp" - help - The board which will be used for CPUAPP domain when creating a multi - image application where one or more images should be located on - another board. - -endif # BOARD_BL5340_DVK_NRF5340_CPUNET diff --git a/boards/lairdconnect/bl5340_dvk/Kconfig.defconfig b/boards/lairdconnect/bl5340_dvk/Kconfig.defconfig deleted file mode 100644 index ece5d8d8d39..00000000000 --- a/boards/lairdconnect/bl5340_dvk/Kconfig.defconfig +++ /dev/null @@ -1,118 +0,0 @@ -# BL5340-DVK board configuration - -# Copyright (c) 2019-2020 Nordic Semiconductor ASA -# Copyright (c) 2021-2023 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_BL5340_DVK_NRF5340_CPUAPP || BOARD_BL5340_DVK_NRF5340_CPUAPP_NS - -config I2C - default GPIO || DAC - -# Code Partition: -# -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# SRAM Partition: -# -# If the secure firmware is to be combined with a non-secure image -# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always -# be restricted to the secure image SRAM partition (sram-secure-partition). -# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram -# may be used by the image. -# -# For the non-secure version of the board, the firmware image SRAM is -# always restricted to the allocated non-secure SRAM partition. -# -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition -DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition - -if BOARD_BL5340_DVK_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config SRAM_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K) - -endif # BOARD_BL5340_DVK_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE - -if BOARD_BL5340_DVK_NRF5340_CPUAPP_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_BL5340_DVK_NRF5340_CPUAPP_NS - -config BT_HCI_IPC - default y if BT - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 4096 if BT_HCI_IPC - -config BT_HCI_VS - default y if BT - -# 2.8" TFT Touch Shield for Arduino w/Capacitive Touch Screen Module -# is mounted to the DVK using standoffs. -# https://www.buydisplay.com/2-8-inch-tft-touch-shield-for-arduino-w-capacitive-touch-screen-module -if DISPLAY - -config INPUT_FT5336_INTERRUPT - default y - -if LVGL - -config LV_Z_VDB_SIZE - default 64 - -config LV_Z_BITS_PER_PIXEL - default 16 - -choice LV_COLOR_DEPTH - default LV_COLOR_DEPTH_16 -endchoice - -config LV_COLOR_16_SWAP - default y - -config INPUT - default y - -endif # LVGL - -endif # DISPLAY - -endif # BOARD_BL5340_DVK_NRF5340_CPUAPP || BOARD_BL5340_DVK_NRF5340_CPUAPP_NS - -config IPM_NRFX - default IPM - -config MBOX_NRFX_IPC - default MBOX - -if BOARD_BL5340_DVK_NRF5340_CPUNET - -# BT_CTLR depends on BT. When BT is enabled we should default to also -# enabling the controller. -config BT_CTLR - default y if BT - -config BT_ECC - default y if BT - -endif # BOARD_BL5340_DVK_NRF5340_CPUNET diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_reset.c b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_reset.c deleted file mode 100644 index 49c0e5a1c73..00000000000 --- a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_reset.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2019-2021 Nordic Semiconductor ASA. - * Copyright (c) 2021-2023 Laird Connectivity - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -#include -#include - -LOG_MODULE_REGISTER(bl5340_dvk_cpuapp, CONFIG_LOG_DEFAULT_LEVEL); - -#if defined(CONFIG_BT_CTLR_DEBUG_PINS_CPUAPP) -#include <../subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/debug.h> -#else -#define DEBUG_SETUP() -#endif - -static void remoteproc_mgr_config(void) -{ -#if !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) || defined(CONFIG_BUILD_WITH_TFM) - /* Route Bluetooth Controller Debug Pins */ - DEBUG_SETUP(); -#endif /* !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) || defined(CONFIG_BUILD_WITH_TFM) */ - -#if !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) - /* Retain nRF5340 Network MCU in Secure domain (bus - * accesses by Network MCU will have Secure attribute set). - */ - NRF_SPU->EXTDOMAIN[0].PERM = 1 << 4; -#endif /* !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) */ -} - -static int remoteproc_mgr_boot(void) -{ - - /* Secure domain may configure permissions for the Network MCU. */ - remoteproc_mgr_config(); - -#if !defined(CONFIG_TRUSTED_EXECUTION_SECURE) - /* - * Building Zephyr with CONFIG_TRUSTED_EXECUTION_SECURE=y implies - * building also a Non-Secure image. The Non-Secure image will, in - * this case do the remainder of actions to properly configure and - * boot the Network MCU. - */ - - /* Release the Network MCU, 'Release force off signal' */ - nrf_reset_network_force_off(NRF_RESET, false); - - LOG_DBG("Network MCU released."); -#endif /* !CONFIG_TRUSTED_EXECUTION_SECURE */ - - return 0; -} - -SYS_INIT(remoteproc_mgr_boot, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); diff --git a/boards/lairdconnect/bl5340_dvk/board.yml b/boards/lairdconnect/bl5340_dvk/board.yml deleted file mode 100644 index 71343692f4c..00000000000 --- a/boards/lairdconnect/bl5340_dvk/board.yml +++ /dev/null @@ -1,8 +0,0 @@ -board: - name: bl5340_dvk - vendor: lairdconnect - socs: - - name: 'nrf5340' - variants: - - name: 'ns' - cpucluster: 'cpuapp' diff --git a/boards/lairdconnect/bl5340_dvk/doc/index.rst b/boards/lairdconnect/bl5340_dvk/doc/index.rst deleted file mode 100644 index 4148b639a6d..00000000000 --- a/boards/lairdconnect/bl5340_dvk/doc/index.rst +++ /dev/null @@ -1,436 +0,0 @@ -.. _bl5340_dvk: - -Laird Connectivity BL5340 DVK -############################# - -Overview -******** -The BL5340 Development Kit provides support for the Laird Connectivity -BL5340 module which is powered by a dual-core Nordic Semiconductor -nRF5340 ARM Cortex-M33F CPU. The nRF5340 inside the BL5340 module is a -dual-core SoC based on the Arm® Cortex®-M33 architecture, with: - -* a full-featured Arm Cortex-M33F core with DSP instructions, FPU, and - Armv8-M Security Extension, running at up to 128 MHz, referred to as - the **application core** -* a secondary Arm Cortex-M33 core, with a reduced feature set, running - at a fixed 64 MHz, referred to as the **network core**. - -The ``bl5340_dvk/nrf5340/cpuapp`` build target provides support for the application -core on the BL5340 module. The ``bl5340_dvk/nrf5340/cpunet`` build target provides -support for the network core on the BL5340 module. If ARM TrustZone is -used then the ``bl5340_dvk/nrf5340/cpuapp`` build target provides support for the -non-secure partition of the application core on the BL5340 module. - -This development kit has the following features: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`IDAU (Implementation Defined Attribution Unit)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`I2S (Inter-Integrated Sound)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* :abbr:`QSPI (Quad Serial Peripheral Interface)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UARTE (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/bl5340_dvk_top.jpg - :align: center - :alt: BL5340 DVK - - BL5340 DVK (Credit: Laird Connectivity) - -More information about the module can be found on the -`BL5340 homepage`_. - -The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. - -Hardware -******** - -The BL5340 DVK has two external oscillators. The frequency of -the slow clock is 32.768KHz. The frequency of the main clock -is 32MHz. - -Supported Features -================== - -The ``bl5340_dvk/nrf5340/cpuapp`` board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| QSPI(M) | on-chip | nor | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -The ``bl5340_dvk/nrf5340/cpunet`` board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See `Nordic Semiconductor Infocenter`_ -for a complete list of hardware features. - -Connections and IOs -=================== - -An eight-pin GPIO port expander is used to provide additional inputs -and outputs to the BL5340 module. - -Refer to the `TI TCA9538 datasheet`_ for further details. - -LEDs ----- - -* LED1 (blue) = via TCA9538 port expander channel P4 (active low) -* LED2 (blue) = via TCA9538 port expander channel P5 (active low) -* LED3 (blue) = via TCA9538 port expander channel P6 (active low) -* LED4 (blue) = via TCA9538 port expander channel P7 (active low) - -Push buttons ------------- - -* BUTTON1 = SW1 = via TCA9538 port expander channel P0 (active low) -* BUTTON2 = SW2 = via TCA9538 port expander channel P1 (active low) -* BUTTON3 = SW3 = via TCA9538 port expander channel P2 (active low) -* BUTTON4 = SW4 = via TCA9538 port expander channel P3 (active low) -* BOOT = boot (active low) - -External Memory -=============== - -Several external memory sources are available for the BL5340 DVK. These -are described as follows. - -Flash Memory ------------- - -A Macronix MX25R6435FZNIL0 8MB external QSPI Flash memory part is -incorporated for application image storage and large datasets. - -Refer to the `Macronix MX25R6435FZNIL0 datasheet`_ for further details. - -EEPROM Memory -------------- - -A 32KB Giantec GT24C256C-2GLI-TR EEPROM is available via I2C for -storage of infrequently updated data and small datasets. - -Refer to the `Giantec GT24C256C-2GLI-TR datasheet`_ for further details. - -External Memory ---------------- - -An on-board micro SD card slot is available for use with micro SD cards. - -Sensors -======= - -The BL5340 DVK incorporates two sensors for user application testing. -These are described as follows. - -Temperature, Pressure, Humidity & Air Quality Sensor ----------------------------------------------------- - -A Bosch BME680 Temperature, Pressure, Humidity & Air Quality sensor is -available via I2C for environmental measurement applications. - -Refer to the `Bosch BME680 datasheet`_ for further details. - -3-Axis Accelerometer --------------------- - -An ST Microelectronics LIS3DH 3-Axis Accelerometer is available via I2C -for vibration and motion detection applications. - -Refer to the `ST Microelectronics LIS3DH datasheet`_ for further details. - -Ethernet -======== - -Cabled 10/100 Base-T Ethernet Connectivity is available via a Microchip -ENC424J600 Ethernet controller. - -Refer to the `Microchip ENC424J600 datasheet`_ for further details. - -TFT Display & Capacitive Touch Screen Controller -================================================ - -A 2.8 inch, 240 x 320 pixel TFT display with capacitive touch -controller is included with the BL5340 DVK for user interface -application features. - -Refer to the `ER_TFTM028_4 datasheet`_ for a high level overview of the -display. - -An ILI9341 TFT controller is incorporated in the TFT module and -acts as the main controller, controlled via SPI. - -Refer to the `ILI9341 datasheet`_ for further details. - -An FT6206 Capacitive Touch Controller, controlled via I2C is -also incorporated in the TFT module. - -Refer to the `FT6206 datasheet`_ for further details. - -Real-Time Clock -=============== - -A real-time clock is available for accurate time data availability. - -Refer to the `Microchip MCP7940N datasheet`_ for further details. - -DAC -=== - -A 10-bit Digital to Analog Converter is incorporated for generation of -variable voltages. - -Refer to the `Microchip MCP4725 datasheet`_ for further details. - -Security components -=================== - -- Implementation Defined Attribution Unit (`IDAU`_) on the application - core. The IDAU is implemented with the System Protection Unit and is - used to define secure and non-secure memory maps. By default, all of - the memory space (Flash, SRAM, and peripheral address space) is - defined to be secure accessible only. -- Secure boot. - -Programming and Debugging -************************* - -The BL5340's application core supports the Armv8-M Security Extension. -Applications built for the ``bl5340_dvk/nrf5340/cpuapp`` board by default -boot in the Secure state. - -The BL5340's network core does not support the Armv8-M Security -Extension. The IDAU may configure bus accesses by the network core to -have Secure attribute set; the latter allows to build and run Secure -only applications on the BL5340 module. - -Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| -============================================================================= - -Applications on the BL5340 module may contain a Secure and a Non-Secure -firmware image for the application core. The Secure image can be built -using either Zephyr or `Trusted Firmware M`_ (TF-M). Non-Secure -firmware images are always built using Zephyr. The two alternatives are -described below. - -.. note:: - - By default the Secure image for BL5340's application core is - built using TF-M. - -Building the Secure firmware with TF-M --------------------------------------- - -The process to build the Secure firmware image using TF-M and the -Non-Secure firmware image using Zephyr requires the following steps: - -1. Build the Non-Secure Zephyr application - for the application core using ``-DBOARD=bl5340_dvk/nrf5340/cpuapp/ns``. - To invoke the building of TF-M the Zephyr build system requires the - Kconfig option ``BUILD_WITH_TFM`` to be enabled, which is done by - default when building Zephyr as a Non-Secure application. - The Zephyr build system will perform the following steps automatically: - - * Build the Non-Secure firmware image as a regular Zephyr application - * Build a TF-M (secure) firmware image - * Merge the output image binaries together - * Optionally build a bootloader image (MCUboot) - -.. note:: - - Depending on the TF-M configuration, an application DTS overlay may - be required, to adjust the Non-Secure image Flash and SRAM starting - address and sizes. - -2. Build the application firmware for the network core using - ``-DBOARD=bl5340_dvk/nrf5340/cpunet``. - -Building the Secure firmware using Zephyr ------------------------------------------ - -The process to build the Secure and the Non-Secure firmware images -using Zephyr requires the following steps: - -1. Build the Secure Zephyr application for the application core - using ``-DBOARD=bl5340_dvk/nrf5340/cpuapp`` and - ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` and ``CONFIG_BUILD_WITH_TFM=n`` - in the application project configuration file. -2. Build the Non-Secure Zephyr application for the application core - using ``-DBOARD=bl5340_dvk/nrf5340/cpuapp/ns``. -3. Merge the two binaries together. -4. Build the application firmware for the network core using - ``-DBOARD=bl5340_dvk/nrf5340/cpunet``. - -When building a Secure/Non-Secure application for the BL5340's -application core, the Secure application will have to set the IDAU -(SPU) configuration to allow Non-Secure access to all CPU resources -utilized by the Non-Secure application firmware. SPU configuration -shall take place before jumping to the Non-Secure application. - -Building a Secure only application -================================== - -Build the Zephyr app in the usual way (see :ref:`build_an_application` -and :ref:`application_run`), using ``-DBOARD=bl5340_dvk/nrf5340/cpuapp`` for -the firmware running on the BL5340's application core, and using -``-DBOARD=bl5340_dvk/nrf5340/cpunet`` for the firmware running -on the BL5340's network core. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then you can build and flash -applications as usual (:ref:`build_an_application` and -:ref:`application_run` for more details). - -.. warning:: - - The BL5340 has a flash read-back protection feature. When flash - read-back protection is active, you will need to recover the chip - before reflashing. If you are flashing with - :ref:`west `, run this command for more - details on the related ``--recover`` option: - - .. code-block:: console - - west flash -H -r nrfjprog --skip-rebuild - -.. note:: - - Flashing and debugging applications on the BL5340 DVK requires - upgrading the nRF Command Line Tools to version 10.12.0 or newer. - Further information on how to install the nRF Command Line Tools can - be found in :ref:`nordic_segger_flashing`. - -Here is an example for the :ref:`hello_world` application running on the -BL5340's application core. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the BL5340 DVK board -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: bl5340_dvk/nrf5340/cpuapp - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging -boards with a Segger IC. - -Testing Bluetooth on the BL5340 DVK -*********************************** -Many of the Bluetooth examples will work on the BL5340 DVK. -Try them out: - -* :ref:`ble_peripheral` -* :ref:`bluetooth-eddystone-sample` -* :ref:`bluetooth-ibeacon-sample` - -References -********** - -.. target-notes:: - -.. _IDAU: - https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau -.. _BL5340 homepage: https://www.lairdconnect.com/wireless-modules/bluetooth-modules/bluetooth-5-modules/bl5340-series-multi-core-bluetooth-52-802154-nfc-modules -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com -.. _TI TCA9538 datasheet: https://www.ti.com/lit/gpn/TCA9538 -.. _Macronix MX25R6435FZNIL0 datasheet: https://www.macronix.com/Lists/Datasheet/Attachments/8868/MX25R6435F,%20Wide%20Range,%2064Mb,%20v1.6.pdf -.. _Giantec GT24C256C-2GLI-TR datasheet: https://www.giantec-semi.com/juchen1123/uploads/pdf/GT24C256C_DS_Cu.pdf -.. _Bosch BME680 datasheet: https://www.bosch-sensortec.com/media/boschsensortec/downloads/datasheets/bst-bme680-ds001.pdf -.. _ST Microelectronics LIS3DH datasheet: https://www.st.com/resource/en/datasheet/lis3dh.pdf -.. _Microchip ENC424J600 datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/39935c.pdf -.. _ER_TFTM028_4 datasheet: https://www.buydisplay.com/download/manual/ER-TFTM028-4_Datasheet.pdf -.. _ILI9341 datasheet: https://www.buydisplay.com/download/ic/ILI9341.pdf -.. _FT6206 datasheet: https://www.buydisplay.com/download/ic/FT6206.pdf -.. _Microchip MCP7940N datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/20005010H.pdf -.. _Microchip MCP4725 datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/22039d.pdf -.. _Trusted Firmware M: https://www.trustedfirmware.org/projects/tf-m/ diff --git a/boards/lairdconnect/bl652_dvk/Kconfig b/boards/lairdconnect/bl652_dvk/Kconfig deleted file mode 100644 index 2d123294177..00000000000 --- a/boards/lairdconnect/bl652_dvk/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# BL652 DVK board configuration - -# Copyright (c) 2019 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_BL652_DVK diff --git a/boards/lairdconnect/bl652_dvk/board.yml b/boards/lairdconnect/bl652_dvk/board.yml deleted file mode 100644 index 2c2e672ec80..00000000000 --- a/boards/lairdconnect/bl652_dvk/board.yml +++ /dev/null @@ -1,5 +0,0 @@ -board: - name: bl652_dvk - vendor: lairdconnect - socs: - - name: nrf52832 diff --git a/boards/lairdconnect/bl653_dvk/Kconfig b/boards/lairdconnect/bl653_dvk/Kconfig deleted file mode 100644 index f1feb5f9435..00000000000 --- a/boards/lairdconnect/bl653_dvk/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# BL653 DVK board configuration - -# Copyright (c) 2020 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_BL653_DVK diff --git a/boards/lairdconnect/bl653_dvk/board.yml b/boards/lairdconnect/bl653_dvk/board.yml deleted file mode 100644 index c898247f1f3..00000000000 --- a/boards/lairdconnect/bl653_dvk/board.yml +++ /dev/null @@ -1,5 +0,0 @@ -board: - name: bl653_dvk - vendor: lairdconnect - socs: - - name: nrf52833 diff --git a/boards/lairdconnect/bl654_dvk/Kconfig b/boards/lairdconnect/bl654_dvk/Kconfig deleted file mode 100644 index f61af2a8e30..00000000000 --- a/boards/lairdconnect/bl654_dvk/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# BL654 DVK board configuration - -# Copyright (c) 2019 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_BL654_DVK diff --git a/boards/lairdconnect/bl654_dvk/board.yml b/boards/lairdconnect/bl654_dvk/board.yml deleted file mode 100644 index 788824c7af1..00000000000 --- a/boards/lairdconnect/bl654_dvk/board.yml +++ /dev/null @@ -1,7 +0,0 @@ -board: - name: bl654_dvk - vendor: lairdconnect - socs: - - name: nrf52840 - variants: - - name: pa diff --git a/boards/lairdconnect/bl654_sensor_board/Kconfig b/boards/lairdconnect/bl654_sensor_board/Kconfig deleted file mode 100644 index 233fdff6a57..00000000000 --- a/boards/lairdconnect/bl654_sensor_board/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# BL654 Sensor Board configuration - -# Copyright (c) 2021 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_BL654_SENSOR_BOARD diff --git a/boards/lairdconnect/bl654_sensor_board/board.yml b/boards/lairdconnect/bl654_sensor_board/board.yml deleted file mode 100644 index ebe40b44601..00000000000 --- a/boards/lairdconnect/bl654_sensor_board/board.yml +++ /dev/null @@ -1,5 +0,0 @@ -board: - name: bl654_sensor_board - vendor: lairdconnect - socs: - - name: nrf52840 diff --git a/boards/lairdconnect/bl654_usb/Kconfig b/boards/lairdconnect/bl654_usb/Kconfig deleted file mode 100644 index c4400d5ca60..00000000000 --- a/boards/lairdconnect/bl654_usb/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -# BL654 USB adapter board configuration - -# Copyright (c) 2021 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_BL654_USB - -config BL654_USB_SERIAL_BACKEND_CDCACM - bool "Use CDC ACM UART as backend for BL654 USB adapter" - default y if !USB_DEVICE_BLUETOOTH - help - Use CDC ACM UART as backend for console or shell. diff --git a/boards/lairdconnect/bl654_usb/board.yml b/boards/lairdconnect/bl654_usb/board.yml deleted file mode 100644 index dc616554605..00000000000 --- a/boards/lairdconnect/bl654_usb/board.yml +++ /dev/null @@ -1,5 +0,0 @@ -board: - name: bl654_usb - vendor: lairdconnect - socs: - - name: nrf52840 diff --git a/boards/lairdconnect/bt510/Kconfig b/boards/lairdconnect/bt510/Kconfig deleted file mode 100644 index fbd70855fd3..00000000000 --- a/boards/lairdconnect/bt510/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# BT510 board configuration - -# Copyright (c) 2020 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_BT510 diff --git a/boards/lairdconnect/bt510/board.yml b/boards/lairdconnect/bt510/board.yml deleted file mode 100644 index 1a9760895ec..00000000000 --- a/boards/lairdconnect/bt510/board.yml +++ /dev/null @@ -1,5 +0,0 @@ -board: - name: bt510 - vendor: lairdconnect - socs: - - name: nrf52840 diff --git a/boards/lairdconnect/bt610/Kconfig b/boards/lairdconnect/bt610/Kconfig deleted file mode 100644 index 5b136cbbb45..00000000000 --- a/boards/lairdconnect/bt610/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# BT610 board configuration - -# Copyright (c) 2021 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_BT610 diff --git a/boards/lairdconnect/bt610/board.yml b/boards/lairdconnect/bt610/board.yml deleted file mode 100644 index c5a846a0d8d..00000000000 --- a/boards/lairdconnect/bt610/board.yml +++ /dev/null @@ -1,5 +0,0 @@ -board: - name: bt610 - vendor: lairdconnect - socs: - - name: nrf52840 diff --git a/boards/lairdconnect/index.rst b/boards/lairdconnect/index.rst deleted file mode 100644 index 5c3a6d6621a..00000000000 --- a/boards/lairdconnect/index.rst +++ /dev/null @@ -1,10 +0,0 @@ -.. _boards-lairdconnect: - -Laird Connectivity -################## - -.. toctree:: - :maxdepth: 1 - :glob: - - **/* diff --git a/boards/lairdconnect/mg100/Kconfig b/boards/lairdconnect/mg100/Kconfig deleted file mode 100644 index b2058e28c95..00000000000 --- a/boards/lairdconnect/mg100/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2022 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_MG100 diff --git a/boards/lairdconnect/mg100/Kconfig.defconfig b/boards/lairdconnect/mg100/Kconfig.defconfig deleted file mode 100644 index 7c08d74f8c5..00000000000 --- a/boards/lairdconnect/mg100/Kconfig.defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# Copyright (c) 2022 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MG100 - -config MODEM - default NETWORKING - -config MODEM_HL7800 - default NETWORKING - -config NORDIC_QSPI_NOR - default BOOTLOADER_MCUBOOT - -config NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE - default 4096 if NORDIC_QSPI_NOR - -config REGULATOR - default DISK_DRIVER_SDMMC - -config BT_CTLR - default BT - -endif # BOARD_MG100 diff --git a/boards/lairdconnect/mg100/board.yml b/boards/lairdconnect/mg100/board.yml deleted file mode 100644 index 25a3ace314f..00000000000 --- a/boards/lairdconnect/mg100/board.yml +++ /dev/null @@ -1,5 +0,0 @@ -board: - name: mg100 - vendor: lairdconnect - socs: - - name: nrf52840 diff --git a/boards/lairdconnect/mg100/doc/index.rst b/boards/lairdconnect/mg100/doc/index.rst deleted file mode 100644 index 611f0db5465..00000000000 --- a/boards/lairdconnect/mg100/doc/index.rst +++ /dev/null @@ -1,249 +0,0 @@ -.. _mg100: - -Laird Connectivity Sentrius™ MG100 Gateway -########################################## - -Overview -******** -The Sentrius™ MG100 Gateway offers a compact, out of box Bluetooth to low power cellular gateway -solution. - -Based on the Pinnacle 100 socket modem, the Sentrius™ MG100 gateway captures data from any -Bluetooth 5 modules or devices and sends it to the cloud via a global low power cellular -(LTE-M/NB-IoT) connection. The MG100 seamlessly incorporates a powerful Cortex M4F controller, -full Bluetooth 5 connectivity, and dual-mode LTE-M/NB-IoT capabilities. The MG100 has full regulatory -and network certifications and End Device carrier approvals. - -Develop your application directly on the integrated Cortex M4F microcontroller using Zephyr RTOS, -enabling your application development with a secure, open source RTOS with more than just kernel -services. Remotely debug your fleet of devices with the `Memfault Platform`_. Take advantage of the -Zephyr community and Laird Connectivity’s multi featured Out of Box (OOB) sample source code -covering all aspects of the product's capabilities and hardware interfaces. The MG100 also delivers -complete antenna flexibility with internal or external antenna options available, and the optional -battery backup provides uninterrupted reporting of remote Bluetooth sensor data. - -More information about the board can be found at the `MG100 website`_. - -The MG100 hardware provides support for the Nordic Semiconductor `nRF52840`_ ARM Cortex-M4F CPU, -`Sierra Wireless HL7800`_ -and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` -* :abbr:`QSPI (Quad Serial Peripheral Interface)` -* :abbr:`LIS3DH (ST Micro 3-axis MEMS accelerometer)` -* :abbr:`HL7800 (Sierra Wireless HL7800 LTE-M1/NB-IoT modem)` -* :abbr:`SD Card` - -.. figure:: img/mg100.jpg - :align: center - :alt: MG100 - - MG100 (450-00054-K1) - -Hardware -******** - -Supported Features -================== - -The MG100 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ -| QSPI | on-chip | qspi/MX25R64(8MB) | -+-----------+------------+----------------------+ -| LIS3DH | I2C(M) | sensor/lis3dh | -+-----------+------------+----------------------+ -| HL7800 | UART | HL7800 modem driver | -+-----------+------------+----------------------+ -| SDMMC | SPI(M) | SD Card via SPI | -+-----------+------------+----------------------+ - -See `MG100 website`_ for a complete list -of MG100 hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (red) = P1.7 -* LED2 (blue) = P1.6 -* LED3 (green) = P1.5 - -Push buttons ------------- - -* BUTTON1 = P0.3 - -External flash memory ---------------------- - -A 64Mbit external flash memory part is available for storage of application -images and data. Refer to the `Macronix MX25R6435F datasheet`_ for further -details. - -The flash memory is connected to the on-board QSPI device controller. - -* MX25R64 = QSPI - -SCK = P0.19 -IO0 = P0.20 -IO1 = P0.21 -IO2 = P0.22 -IO3 = P0.23 -CSN = P0.17 - -LIS3DH Motion Sensor --------------------- - -Motion sensor to detect if the gateway moves. - -IRQ IO = P0.28 -I2C SDA = P0.26 -I2C SCL = P0.27 - -SD Card -------- - -SD card used to store large amounts of data. - -SPI CS = P0.29 -SPI SCK = P1.09 -SPI MOSI = P0.11 -SPI MISO = P0.12 - -Programming and Debugging -************************* - -Applications for the ``mg100`` board configuration can be -built and flashed in the usual way. (see :ref:`build_an_application` -and :ref:`application_run` for more details) - -The `Laird Connectivity USB-SWD Programming Kit`_ contains all the necessary -hardware to enable programming and debugging an MG100. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. note:: On the MG100, - the USB connector should be used to access the UART console. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board MG100 -can be found. For example, under Linux, :code:`/dev/ttyUSB0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mg100 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - -Software -******** - -MG100 Out-of-Box Demo Software -============================== -The MG100 ships with an out of the box software demo. -Check out the `BLE Gateway OOB Demo`_ source code and documentation. - -Testing Bluetooth on the MG100 -============================== -Many of the Bluetooth examples will work on the MG100. -Try them out: - -* :ref:`ble_peripheral` -* :ref:`bluetooth-eddystone-sample` -* :ref:`bluetooth-ibeacon-sample` - -Testing the LEDs and buttons in the MG100 -==================================================== - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/lairdconnect/mg100/mg100.dts`. - -References -********** - -.. target-notes:: - -.. _MG100 website: https://www.lairdconnect.com/iot-devices/iot-gateways/sentrius-mg100-gateway-lte-mnb-iot-and-bluetooth-5 -.. _nRF52840 Product Specification: https://infocenter.nordicsemi.com/pdf/nRF52840_PS_v1.1.pdf -.. _Sierra Wireless HL7800: https://source.sierrawireless.com/devices/hl-series/hl7800/#sthash.641qTTwA.dpbs -.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html -.. _BLE Gateway OOB Demo: https://github.com/LairdCP/Pinnacle-100-Firmware-Manifest -.. _Macronix MX25R6435F datasheet: https://www.macronix.com/Lists/Datasheet/Attachments/7913/MX25R6435F,%20Wide%20Range,%2064Mb,%20v1.5.pdf -.. _Laird Connectivity USB-SWD Programming Kit: https://www.lairdconnect.com/wireless-modules/programming-kits/usb-swd-programming-kit -.. _Memfault Platform: https://docs.memfault.com/docs/mcu/pinnacle-100-guide -.. _nRF52840: https://www.nordicsemi.com/products/nrf52840 diff --git a/boards/lairdconnect/pinnacle_100_dvk/Kconfig b/boards/lairdconnect/pinnacle_100_dvk/Kconfig deleted file mode 100644 index 016470b8d82..00000000000 --- a/boards/lairdconnect/pinnacle_100_dvk/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Pinnacle(TM) 100 DVK board configuration -# -# Copyright (c) 2020 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_PINNACLE_100_DVK diff --git a/boards/lairdconnect/pinnacle_100_dvk/Kconfig.defconfig b/boards/lairdconnect/pinnacle_100_dvk/Kconfig.defconfig deleted file mode 100644 index 181dc76a04e..00000000000 --- a/boards/lairdconnect/pinnacle_100_dvk/Kconfig.defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# Pinnacle(TM) 100 DVK board configuration - -# Copyright (c) 2019 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_PINNACLE_100_DVK - -config MODEM - default NETWORKING - -config MODEM_HL7800 - default NETWORKING - -config NORDIC_QSPI_NOR - default BOOTLOADER_MCUBOOT - -config NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE - default 4096 if NORDIC_QSPI_NOR - -config BT_CTLR - default BT - -endif # BOARD_PINNACLE_100_DVK diff --git a/boards/lairdconnect/pinnacle_100_dvk/board.yml b/boards/lairdconnect/pinnacle_100_dvk/board.yml deleted file mode 100644 index 1741e687ace..00000000000 --- a/boards/lairdconnect/pinnacle_100_dvk/board.yml +++ /dev/null @@ -1,5 +0,0 @@ -board: - name: pinnacle_100_dvk - vendor: lairdconnect - socs: - - name: nrf52840 diff --git a/boards/lairdconnect/pinnacle_100_dvk/doc/index.rst b/boards/lairdconnect/pinnacle_100_dvk/doc/index.rst deleted file mode 100644 index 6feaa13833d..00000000000 --- a/boards/lairdconnect/pinnacle_100_dvk/doc/index.rst +++ /dev/null @@ -1,220 +0,0 @@ -.. _pinnacle_100_dvk: - -Laird Connectivity Pinnacle 100 DVK -################################### - -Overview -******** -The Pinnacle™ 100 cellular modem seamlessly incorporates a powerful Cortex M4F -controller, full Bluetooth 5 and LTE-M/NB-IoT capabilities – all with full -regulatory certifications and LTE carrier approvals. The Pinnacle 100 also -delivers complete antenna flexibility, with pre-integrated internal or external -antenna options such as the Revie Flex family of LTE and NB-IoT -internal antennas. - -Develop your application directly on the M4F controller using Zephyr RTOS to -cut BOM costs and power consumption. Take advantage of the Zephyr community, -Laird Connectivity’s sample code (cellular, Bluetooth) and hardware interfaces, -or use our hosted mode AT commands set firmware. - -Extremely power conscious, the Pinnacle 100 is ideal for battery-powered -devices operating at the edge of your IoT networks, seamlessly bridging the -cellular WAN to BLE. It’s never been easier to bridge wireless -Bluetooth 5 sensor data to cloud services like AWS IoT over a -low-power LTE connection. - -More information about the board can be found at the `Pinnacle 100 website`_. - -The Pinnacle 100 Development Kit (453-00010-K1 or 453-00011-K1) hardware -provides support for the -Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU, `Sierra Wireless HL7800`_ (Altair ALT1250) -and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` -* :abbr:`QSPI (Quad Serial Peripheral Interface)` -* :abbr:`BME680 (Bosch Sensortec BME680 environmental sensor)` -* :abbr:`HL7800 (Sierra Wireless HL7800 LTE-M1/NB-IoT modem)` - -.. figure:: img/pinnacle_100_dvk.jpg - :align: center - :alt: Pinnacle 100 DVK - - Pinnacle 100 DVK (453-00010-K1) - -Hardware -******** - -Supported Features -================== - -The Pinnacle 100 development board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ -| QSPI | on-chip | qspi/MX25R64(8MB) | -+-----------+------------+----------------------+ -| BME680 | I2C(M) | sensor/bme680 | -+-----------+------------+----------------------+ -| HL7800 | UART | HL7800 modem driver | -+-----------+------------+----------------------+ - -See `Pinnacle 100 website`_ for a complete list -of Pinnacle 100 Development Kit hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (blue) = P1.4 -* LED2 (green) = P1.5 -* LED3 (red) = P1.6 -* LED4 (green) = P1.7 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.31 -* BUTTON2 = SW2 = P0.3 -* BUTTON3 = SW3 = P0.4 -* BUTTON4 = SW4 = P0.2 -* NRF RESET = SW5 = reset - -Programming and Debugging -************************* - -Applications for the ``pinnacle_100_dvk`` board configuration can be -built and flashed in the usual way. (see :ref:`build_an_application` -and :ref:`application_run` for more details) - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. note:: On the Pinnacle 100 development board, - the FTDI USB should be used to access the UART console. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board Pinnacle 100 DVK -can be found. For example, under Linux, :code:`/dev/ttyUSB0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: pinnacle_100_dvk - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - -Software -******** - -Pinnacle 100 Out-of-Box Demo Software -===================================== -The Pinnacle 100 development kit ships with an out of the box software demo. -Check out the `Pinnacle 100 OOB Demo`_ source code and documentation. - -Sample Applications -=================== -`Pinnacle 100 Sample Applications`_ are available. - -Testing Bluetooth on the Pinnacle 100 DVK -========================================= -Many of the Bluetooth examples will work on the Pinnacle 100 DVK. -Try them out: - -* :ref:`ble_peripheral` -* :ref:`bluetooth-eddystone-sample` -* :ref:`bluetooth-ibeacon-sample` - -Testing the LEDs and buttons in the Pinnacle 100 DVK -==================================================== - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/lairdconnect/pinnacle_100_dvk/pinnacle_100_dvk.dts`. - -References -********** - -.. target-notes:: - -.. _Pinnacle 100 website: https://www.lairdconnect.com/wireless-modules/cellular-solutions/pinnacle-100-cellular-modem -.. _nRF52840 Product Specification: https://infocenter.nordicsemi.com/pdf/nRF52840_PS_v1.1.pdf -.. _Sierra Wireless HL7800: https://source.sierrawireless.com/devices/hl-series/hl7800/#sthash.641qTTwA.dpbs -.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html -.. _Pinnacle 100 OOB Demo: https://github.com/LairdCP/Pinnacle_100_oob_demo -.. _Pinnacle 100 Sample Applications: https://github.com/LairdCP/Pinnacle_100_Sample_Applications diff --git a/boards/lairdconnect/rm1xx_dvk/board.yml b/boards/lairdconnect/rm1xx_dvk/board.yml deleted file mode 100644 index 1e7ddd8f806..00000000000 --- a/boards/lairdconnect/rm1xx_dvk/board.yml +++ /dev/null @@ -1,5 +0,0 @@ -board: - name: rm1xx_dvk - vendor: lairdconnect - socs: - - name: nrf51822 diff --git a/boards/lairdconnect/rm1xx_dvk/doc/index.rst b/boards/lairdconnect/rm1xx_dvk/doc/index.rst deleted file mode 100644 index bd006dc058a..00000000000 --- a/boards/lairdconnect/rm1xx_dvk/doc/index.rst +++ /dev/null @@ -1,179 +0,0 @@ -.. _rm1xx_dvk: - -Laird Connectivity RM1xx DVK -############################ - -Overview -******** - -Laird Connectivity's RM1xx is a module which integrates both LoRa and -BLE communications, powered by a Nordic Semiconductor nRF51822 ARM -Cortex-M0 CPU and on-board Semtech SX1272 LoRa RF chip. This board -supports the RM1xx on the RM1xx development board - RM191 for the -915MHz version and RM186 for the 868MHz version. - -This development kit has the following features: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/RM186-DVK.jpg - :align: center - :alt: RM1xx development kit (DVK) - - RM1xx development kit (DVK) (Credit: Laird Connectivity) - -.. figure:: img/RM186-SM.jpg - :align: center - :alt: RM1xx module - - RM1xx module (Credit: Laird Connectivity) - -More information about the module can be found on the -`RM1xx homepage`_. - -The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. - -Hardware -******** - -The RM1xx has two internal oscillators. The frequency of -the slow clock is 32.768KHz. The frequency of the main clock -is 16MHz. - - -Supported Features -================== - -The rm1xx_dvk board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See `Nordic Semiconductor Infocenter`_ -for a complete list of hardware features. - -Connections and IOs -=================== - -The development board features a Microchip MCP23S08 SPI port expander - -note that this is not currently supported in Zephyr. - -Refer to the `Microchip MCP23S08 datasheet`_ for further details. - -Push buttons ------------- - -* BUTTON2 = SW0 = P0.05 - - -Internal Memory -=============== - -EEPROM Memory -------------- - -A 512KB (4Mb) Adesto AT25DF041B EEPROM is available via SPI for storage -of infrequently updated data and small datasets and can be used with -the spi-nor driver. Note that the EEPROM shares the same SPI bus as the -SX1272 LoRa transceiver so priority access should be given to the LoRa -radio. - -Refer to the `Adesto AT25DF041B datasheet`_ for further details. - -LoRa -==== - -A Semtech SX1272 transceiver chip is present in the module which can be -used in 915MHz LoRa frequency ranges if using an RM191 module or 868MHz -LoRa frequency ranges if uses an RM186 module - -Refer to the `Semtech SX1272 datasheet`_ for further details. - -Programming and Debugging -************************* - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board nRF51 DK -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rm1xx_dvk - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging boards -with a Segger IC. - -References -********** - -.. target-notes:: - -.. _RM1xx homepage: https://www.lairdconnect.com/wireless-modules/lorawan-solutions/sentrius-rm1xx-lora-ble-module -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com -.. _Adesto AT25DF041B datasheet: https://www.dialog-semiconductor.com/sites/default/files/ds-at25df041b_040.pdf -.. _Semtech SX1272 datasheet: https://semtech.my.salesforce.com/sfc/p/#E0000000JelG/a/440000001NCE/v_VBhk1IolDgxwwnOpcS_vTFxPfSEPQbuneK3mWsXlU -.. _Microchip MCP23S08 datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/MCP23008-MCP23S08-Data-Sheet-20001919F.pdf diff --git a/boards/lilygo/index.rst b/boards/lilygo/index.rst new file mode 100644 index 00000000000..8333f691867 --- /dev/null +++ b/boards/lilygo/index.rst @@ -0,0 +1,10 @@ +.. _boards-lilygo: + +Lilygo +###### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/lilygo/ttgo_lora32/Kconfig.defconfig b/boards/lilygo/ttgo_lora32/Kconfig.defconfig new file mode 100644 index 00000000000..d77a95c89b0 --- /dev/null +++ b/boards/lilygo/ttgo_lora32/Kconfig.defconfig @@ -0,0 +1,25 @@ +# Lilygo ttgo LoRa32 board configuration + +# Copyright (c) 2024 Lothar Felten +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_TTGO_LORA32_ESP32_PROCPU + +config ENTROPY_GENERATOR + default y + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +endif # BOARD_TTGO_LORA32_ESP32_PROCPU + +if BOARD_TTGO_LORA32_ESP32_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 256 + +endif # BOARD_TTGO_LORA32_ESP32_APPCPU diff --git a/boards/lilygo/ttgo_lora32/Kconfig.sysbuild b/boards/lilygo/ttgo_lora32/Kconfig.sysbuild new file mode 100644 index 00000000000..3a2d17ac5cf --- /dev/null +++ b/boards/lilygo/ttgo_lora32/Kconfig.sysbuild @@ -0,0 +1,10 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice BOOT_SIGNATURE_TYPE + default BOOT_SIGNATURE_TYPE_NONE +endchoice diff --git a/boards/lilygo/ttgo_lora32/Kconfig.ttgo_lora32 b/boards/lilygo/ttgo_lora32/Kconfig.ttgo_lora32 new file mode 100644 index 00000000000..b1cac2dac48 --- /dev/null +++ b/boards/lilygo/ttgo_lora32/Kconfig.ttgo_lora32 @@ -0,0 +1,9 @@ +# TTGO LoRa32 board configuration + +# Copyright (c) 2024 Lothar Felten +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_TTGO_LORA32 + select SOC_ESP32_PICO_D4 + select SOC_ESP32_PROCPU if BOARD_TTGO_LORA32_ESP32_PROCPU + select SOC_ESP32_APPCPU if BOARD_TTGO_LORA32_ESP32_APPCPU diff --git a/boards/lilygo/ttgo_lora32/board.cmake b/boards/lilygo/ttgo_lora32/board.cmake new file mode 100644 index 00000000000..91b3caa2c75 --- /dev/null +++ b/boards/lilygo/ttgo_lora32/board.cmake @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) + +# the default ESP32 baud rate is not supported +board_runner_args(esp32 "--esp-baud-rate=1500000") diff --git a/boards/lilygo/ttgo_lora32/board.yml b/boards/lilygo/ttgo_lora32/board.yml new file mode 100644 index 00000000000..8cccfbbf7d2 --- /dev/null +++ b/boards/lilygo/ttgo_lora32/board.yml @@ -0,0 +1,5 @@ +board: + name: ttgo_lora32 + vendor: lilygo + socs: + - name: esp32 diff --git a/boards/lilygo/ttgo_lora32/doc/img/ttgo_lora32.webp b/boards/lilygo/ttgo_lora32/doc/img/ttgo_lora32.webp new file mode 100644 index 00000000000..4d240e9d6b9 Binary files /dev/null and b/boards/lilygo/ttgo_lora32/doc/img/ttgo_lora32.webp differ diff --git a/boards/lilygo/ttgo_lora32/doc/index.rst b/boards/lilygo/ttgo_lora32/doc/index.rst new file mode 100644 index 00000000000..c7a04423e90 --- /dev/null +++ b/boards/lilygo/ttgo_lora32/doc/index.rst @@ -0,0 +1,245 @@ +.. _ttgo_lora32: + +Lilygo TTGO LoRa32 +################## + +Overview +******** + +The Lilygo TTGO LoRa32 is a development board for LoRa applications baesed on the ESP32-PICO-D4. + +It's available in two versions supporting two different frequency ranges and features the following integrated components: + +- ESP32-PICO-D4 chip (240MHz dual core, 600 DMIPS, 520KB SRAM, Wi-Fi) +- SSD1306, 128x64 px, 0.96" screen +- SX1278 (433MHz) or SX1276 (868/915/923MHz) LoRa radio frontend +- JST GH 2-pin battery connector +- TF card slot + +Some of the ESP32 I/O pins are accessible on the board's pin headers. + +.. figure:: img/ttgo_lora32.webp + :align: center + :alt: Lilygo TTGO LoRa32 module + :width: 400 px + + Lilygo TTGO LoRa32 module + +Functional Description +********************** + +The following table below describes the key components, interfaces, and controls +of the Lilygo TTGO LoRa32 board. + +.. _SX127x: https://www.semtech.com/products/wireless-rf/lora-connect/sx1276#documentation +.. _ESP32-PICO-D4: https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf +.. _SSD1306: https://cdn-shop.adafruit.com/datasheets/SSD1306.pdf + ++------------------+-------------------------------------------------------------------------+ +| Key Component | Description | ++==================+=========================================================================+ +| ESP32-PICO-D4 | This `ESP32-PICO-D4`_ module provides complete Wi-Fi and Bluetooth | +| | functionalities and integrates a 4-MB SPI flash. | ++------------------+-------------------------------------------------------------------------+ +| Diagnostic LED | One user LED connected to the GPIO pin. | ++------------------+-------------------------------------------------------------------------+ +| USB Port | USB interface. Power supply for the board as well as the | +| | serial communication interface between a computer and the board. | +| | Micro-USB type connector. | ++------------------+-------------------------------------------------------------------------+ +| Power Switch | Sliding power switch. | ++------------------+-------------------------------------------------------------------------+ +| LCD screen | Built-in OLED display \(`SSD1306`_, 0.96", 128x64 px\) controlled | +| | by I2C interface | ++------------------+-------------------------------------------------------------------------+ +| SX1276/SX1278 | LoRa radio frontend chip, connected via SPI. | +| | Use SX1276 for 433MHz and SX1276 for 868/915/923MHz. | ++------------------+-------------------------------------------------------------------------+ +| TF card slot | TF card slot wired to the SD interface of the MCU. | ++------------------+-------------------------------------------------------------------------+ + + +Start Application Development +***************************** + +Before powering up your Lilygo TTGO LoRa32, please make sure that the board is in good +condition with no obvious signs of damage. + +System requirements +******************* + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: + + Simple boot does not provide any security features nor OTA updates. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be built (and flashed) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + + .. code-block:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32-PICO-D4 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/hello_world + :board: ttgo_lora32/esp32/procpu + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32-PICO-D4 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │   └── zephyr + │   ├── zephyr.elf + │   └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be built one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ttgo_lora32/esp32/procpu + :goals: build + +The usual ``flash`` target will work with the ``ttgo_lora32`` board +configuration. Here is an example for the :zephyr:code-sample:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ttgo_lora32/esp32/procpu + :goals: flash + +The default baud rate for the Lilygo TTGO LoRa32 is set to 1500000bps. If experiencing issues when flashing, +try using different values by using ``--esp-baud-rate `` option during +``west flash`` (e.g. ``west flash --esp-baud-rate 115200``). + +You can also open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! ttgo_lora32 + +LoRa samples +============ + +There are two LoRa samples that will work out of the box with this board. + +To build the LoRa transmit sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/drivers/lora/send + :board: ttgo_lora32/esp32/procpu + :goals: build + :west-args: --sysbuild + :compact: + +To build the LoRa receive sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/drivers/lora/receive + :board: ttgo_lora32/esp32/procpu + :goals: build + :west-args: --sysbuild + :compact: + +Debugging +********* + +Lilygo TTGO LoRa32 debugging is not supported due to pinout limitations. + +Related Documents +***************** +- `Lilygo TTGO LoRa32 schematic `_ (PDF) +- `Lilygo TTGO LoRa32 documentation `_ +- `Lilygo github repo `_ +- `ESP32-PICO-D4 Datasheet `_ (PDF) +- `ESP32 Datasheet `_ (PDF) +- `ESP32 Hardware Reference `_ diff --git a/boards/lilygo/ttgo_lora32/support/openocd.cfg b/boards/lilygo/ttgo_lora32/support/openocd.cfg new file mode 100644 index 00000000000..338e6e4e6ea --- /dev/null +++ b/boards/lilygo/ttgo_lora32/support/openocd.cfg @@ -0,0 +1,5 @@ +set ESP_RTOS none +set ESP32_ONLYCPU 1 + +source [find interface/ftdi/esp32_devkitj_v1.cfg] +source [find target/esp32.cfg] diff --git a/boards/lilygo/ttgo_lora32/ttgo_lora32-pinctrl.dtsi b/boards/lilygo/ttgo_lora32/ttgo_lora32-pinctrl.dtsi new file mode 100644 index 00000000000..5f043ddb945 --- /dev/null +++ b/boards/lilygo/ttgo_lora32/ttgo_lora32-pinctrl.dtsi @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2024 Lothar Felten + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + + uart0_default: uart0_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + spim3_default: spim3_default { + group1 { + pinmux = , + ; + }; + group2 { + pinmux = ; + output-low; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; + +}; diff --git a/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_appcpu.dts b/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_appcpu.dts new file mode 100644 index 00000000000..c5eb19c240f --- /dev/null +++ b/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_appcpu.dts @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include + +/ { + model = "ttgo LoRa32 APPCPU"; + compatible = "espressif,esp32"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&ipm0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_appcpu.yaml b/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_appcpu.yaml new file mode 100644 index 00000000000..f0485667260 --- /dev/null +++ b/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: ttgo_lora32/esp32/appcpu +name: TTGO LoRa32 APPCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: lilygo diff --git a/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_appcpu_defconfig b/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_appcpu_defconfig new file mode 100644 index 00000000000..100bb882567 --- /dev/null +++ b/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_appcpu_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu.dts b/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu.dts new file mode 100644 index 00000000000..d8dfad087e3 --- /dev/null +++ b/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu.dts @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2024 Lothar Felten + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "ttgo_lora32-pinctrl.dtsi" +#include + +/ { + model = "ttgo LoRa32 PROCPU"; + compatible = "lilygo,ttgo-lora32"; + + aliases { + led0 = &green_led; + uart-0 = &uart0; + i2c-0 = &i2c0; + watchdog0 = &wdt0; + lora0 = &lora0; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,display = &ssd1306_128x64; + }; + + leds { + compatible = "gpio-leds"; + + green_led: led_0 { + gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; + label = "Green - LED0"; + }; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +/* OLED display */ +&i2c0 { + status = "okay"; + clock-frequency = ; + sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; + scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + ssd1306_128x64: ssd1306@3c { + compatible = "solomon,ssd1306fb"; + reg = <0x3c>; + width = <128>; + height = <64>; + segment-offset = <0>; + page-offset = <0>; + display-offset = <0>; + multiplex-ratio = <63>; + segment-remap; + com-invdir; + prechargep = <0x22>; + }; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; + cs-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; + lora0: lora@0 { + compatible = "semtech,sx1276"; + reg = <0>; + reset-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; + dio-gpios = + /* SX1276 D0 -> GPIO26 */ + <&gpio0 26 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, + /* SX1276 D1 -> GPIO35 */ + <&gpio1 3 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, + /* SX1276 D1 -> GPIO34 */ + <&gpio1 2 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; + spi-max-frequency = <1000000>; + power-amplifier-output = "pa-boost"; + }; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&timer3 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu.yaml b/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu.yaml new file mode 100644 index 00000000000..f4d0e25cc59 --- /dev/null +++ b/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu.yaml @@ -0,0 +1,21 @@ +identifier: ttgo_lora32/esp32/procpu +name: TTGO LoRa32 PROCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - i2c + - spi + - watchdog + - uart + - pinmux + - display + - lora + - nvs +testing: + ignore_tags: + - net + - bluetooth +vendor: lilygo diff --git a/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu_defconfig b/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu_defconfig new file mode 100644 index 00000000000..ee9920cda68 --- /dev/null +++ b/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +CONFIG_GPIO=y +CONFIG_I2C=y diff --git a/boards/lilygo/ttgo_t8c3/Kconfig.defconfig b/boards/lilygo/ttgo_t8c3/Kconfig.defconfig new file mode 100644 index 00000000000..eb2f107cd0d --- /dev/null +++ b/boards/lilygo/ttgo_t8c3/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Lothar Felten +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 diff --git a/boards/lilygo/ttgo_t8c3/Kconfig.sysbuild b/boards/lilygo/ttgo_t8c3/Kconfig.sysbuild new file mode 100644 index 00000000000..3a2d17ac5cf --- /dev/null +++ b/boards/lilygo/ttgo_t8c3/Kconfig.sysbuild @@ -0,0 +1,10 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice BOOT_SIGNATURE_TYPE + default BOOT_SIGNATURE_TYPE_NONE +endchoice diff --git a/boards/lilygo/ttgo_t8c3/Kconfig.ttgo_t8c3 b/boards/lilygo/ttgo_t8c3/Kconfig.ttgo_t8c3 new file mode 100644 index 00000000000..60cd233a9b4 --- /dev/null +++ b/boards/lilygo/ttgo_t8c3/Kconfig.ttgo_t8c3 @@ -0,0 +1,5 @@ +# Copyright 2024 Lothar Felten +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_TTGO_T8C3 + select SOC_ESP32C3_FX4 diff --git a/boards/lilygo/ttgo_t8c3/board.cmake b/boards/lilygo/ttgo_t8c3/board.cmake new file mode 100644 index 00000000000..2f04d1fe886 --- /dev/null +++ b/boards/lilygo/ttgo_t8c3/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/lilygo/ttgo_t8c3/board.yml b/boards/lilygo/ttgo_t8c3/board.yml new file mode 100644 index 00000000000..8b1084a4493 --- /dev/null +++ b/boards/lilygo/ttgo_t8c3/board.yml @@ -0,0 +1,5 @@ +board: + name: ttgo_t8c3 + vendor: lilygo + socs: + - name: esp32c3 diff --git a/boards/lilygo/ttgo_t8c3/doc/img/ttgo_t8c3.webp b/boards/lilygo/ttgo_t8c3/doc/img/ttgo_t8c3.webp new file mode 100644 index 00000000000..ea11307794f Binary files /dev/null and b/boards/lilygo/ttgo_t8c3/doc/img/ttgo_t8c3.webp differ diff --git a/boards/lilygo/ttgo_t8c3/doc/index.rst b/boards/lilygo/ttgo_t8c3/doc/index.rst new file mode 100644 index 00000000000..2b11dd90a0a --- /dev/null +++ b/boards/lilygo/ttgo_t8c3/doc/index.rst @@ -0,0 +1,234 @@ +.. _ttgo_t8c3: + +Lilygo TTGO T8-C3 +################# + +Overview +******** + +Lilygo TTGO T8-C3 is an IoT mini development board based on the +Espressif ESP32-C3 WiFi/Bluetooth dual-mode chip. + +It features the following integrated components: + +- ESP32-C3 chip (160MHz single core, 400KB SRAM, Wi-Fi) +- on board antenna and IPEX connector +- USB-C connector for power and communication +- JST GH 2-pin battery connector +- LED + +.. figure:: img/ttgo_t8c3.webp + :align: center + :alt: TTGO T8-C3 + + Lilygo TTGO T8-C3 + +Functional Description +********************** +This board is based on the ESP32-C3 with 4MB of flash, WiFi and BLE support. It +has an USB-C port for programming and debugging, integrated battery charging +and an on-board antenna. The fitted U.FL external antenna connector can be +enabled by moving a 0-ohm resistor. + +Connections and IOs +=================== + +The TTGO T8-C3 board configuration supports the following hardware features: + ++-----------+------------+------------------+ +| Interface | Controller | Driver/Component | ++===========+============+==================+ +| PMP | on-chip | arch/riscv | ++-----------+------------+------------------+ +| INTMTRX | on-chip | intc_esp32c3 | ++-----------+------------+------------------+ +| PINMUX | on-chip | pinctrl_esp32 | ++-----------+------------+------------------+ +| USB UART | on-chip | serial_esp32_usb | ++-----------+------------+------------------+ +| GPIO | on-chip | gpio_esp32 | ++-----------+------------+------------------+ +| UART | on-chip | uart_esp32 | ++-----------+------------+------------------+ +| I2C | on-chip | i2c_esp32 | ++-----------+------------+------------------+ +| SPI | on-chip | spi_esp32_spim | ++-----------+------------+------------------+ +| TWAI | on-chip | can_esp32_twai | ++-----------+------------+------------------+ + +Start Application Development +***************************** + +Before powering up your Lilygo TTGO T8-C3, please make sure that the board is in good +condition with no obvious signs of damage. + +System requirements +******************* + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: + + Simple boot does not provide any security features nor OTA updates. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be built (and flashed) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32-C3 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/hello_world + :board: ttgo_t8c3 + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32-C3 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │   └── zephyr + │   ├── zephyr.elf + │   └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be built one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ttgo_t8c3 + :goals: build + +The usual ``flash`` target will work with the ``ttgo_t8c3`` board +configuration. Here is an example for the :zephyr:code-sample:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ttgo_t8c3 + :goals: flash + +The default baud rate for the Lilygo TTGO T8-C3 is set to 1500000bps. If experiencing issues when flashing, +try using different values by using ``--esp-baud-rate `` option during +``west flash`` (e.g. ``west flash --esp-baud-rate 115200``). + +You can also open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! ttgo_t8c3 + +Sample applications +=================== + +The following samples will run out of the box on the TTGO T8-C3 board. + +To build the blinky sample: + +.. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/basic/blinky + :board: ttgo_t8c3 + :goals: build + +To build the bluetooth beacon sample: + +.. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/bluetooth/beacon + :board: ttgo_t8c3 + :goals: build + + +Related Documents +***************** +.. _`Lilygo TTGO T8-C3 schematic`: https://github.com/Xinyuan-LilyGO/T8-C3/blob/main/Schematic/T8-C3_V1.1.pdf +.. _`Lilygo github repo`: https://github.com/Xinyuan-LilyGo +.. _`Espressif ESP32-C3 datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf +.. _`Espressif ESP32-C3 technical reference manual`: https://www.espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/lilygo/ttgo_t8c3/support/openocd.cfg b/boards/lilygo/ttgo_t8c3/support/openocd.cfg new file mode 100644 index 00000000000..02754ff2a73 --- /dev/null +++ b/boards/lilygo/ttgo_t8c3/support/openocd.cfg @@ -0,0 +1,6 @@ +set ESP_RTOS none + +source [find interface/esp_usb_jtag.cfg] + +source [find target/esp32c3.cfg] +adapter_khz 5000 diff --git a/boards/lilygo/ttgo_t8c3/ttgo_t8c3-pinctrl.dtsi b/boards/lilygo/ttgo_t8c3/ttgo_t8c3-pinctrl.dtsi new file mode 100644 index 00000000000..72cf16f3765 --- /dev/null +++ b/boards/lilygo/ttgo_t8c3/ttgo_t8c3-pinctrl.dtsi @@ -0,0 +1,51 @@ +/* + * Copyright 2024 Lothar Felten + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + spim2_default: spim2_default { + group1 { + pinmux = , + ; + }; + /* GPIO6 is CS */ + group2 { + pinmux = ; + output-low; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; + + twai_default: twai_default { + group1 { + pinmux = , + ; + }; + }; +}; diff --git a/boards/lilygo/ttgo_t8c3/ttgo_t8c3.dts b/boards/lilygo/ttgo_t8c3/ttgo_t8c3.dts new file mode 100644 index 00000000000..a38f5777762 --- /dev/null +++ b/boards/lilygo/ttgo_t8c3/ttgo_t8c3.dts @@ -0,0 +1,133 @@ +/* + * Copyright 2024 Lothar Felten + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "ttgo_t8c3-pinctrl.dtsi" + +/ { + model = "Lilygo TTGO T8-C3"; + compatible = "lilygo,ttgo-t8c3"; + + aliases { + led0 = &green_led; + i2c-0 = &i2c0; + watchdog0 = &wdt0; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &usb_serial; + zephyr,shell-uart = &usb_serial; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,bt-hci = &esp32_bt_hci; + zephyr,canbus = &twai; + }; + + leds { + compatible = "gpio-leds"; + green_led: led_0 { + gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; + label = "Green - LED0"; + }; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&usb_serial { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&trng0 { + status = "okay"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&twai { + status = "okay"; + pinctrl-0 = <&twai_default>; + pinctrl-names = "default"; +}; + +&wifi { + status = "okay"; +}; + +&esp32_bt_hci{ + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x0000F000>; + read-only; + }; + + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/lilygo/ttgo_t8c3/ttgo_t8c3.yaml b/boards/lilygo/ttgo_t8c3/ttgo_t8c3.yaml new file mode 100644 index 00000000000..e2fc320098a --- /dev/null +++ b/boards/lilygo/ttgo_t8c3/ttgo_t8c3.yaml @@ -0,0 +1,18 @@ +identifier: ttgo_t8c3 +name: TTGO T8C3 +type: mcu +arch: riscv +toolchain: + - zephyr +supported: + - gpio + - i2c + - spi + - uart + - watchdog + - can +testing: + ignore_tags: + - net + - bluetooth +vendor: lilygo diff --git a/boards/lilygo/ttgo_t8c3/ttgo_t8c3_defconfig b/boards/lilygo/ttgo_t8c3/ttgo_t8c3_defconfig new file mode 100644 index 00000000000..ef633ce56a1 --- /dev/null +++ b/boards/lilygo/ttgo_t8c3/ttgo_t8c3_defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y diff --git a/boards/lowrisc/opentitan_earlgrey/doc/index.rst b/boards/lowrisc/opentitan_earlgrey/doc/index.rst index f3edf95e44e..b91c0700def 100644 --- a/boards/lowrisc/opentitan_earlgrey/doc/index.rst +++ b/boards/lowrisc/opentitan_earlgrey/doc/index.rst @@ -57,7 +57,7 @@ Setup`_ guide . Building and Flashing ===================== -Here is an example for building the :ref:`hello_world` application. The +Here is an example for building the :zephyr:code-sample:`hello_world` application. The following steps were tested on OpenTitan master branch @ 6a3c2e98. .. zephyr-app-commands:: diff --git a/boards/luatos/esp32c3_luatos_core/doc/index.rst b/boards/luatos/esp32c3_luatos_core/doc/index.rst index 7b6bbacf982..2e0d5ed56b2 100644 --- a/boards/luatos/esp32c3_luatos_core/doc/index.rst +++ b/boards/luatos/esp32c3_luatos_core/doc/index.rst @@ -54,7 +54,6 @@ Current Zephyr's ESP32C3_LUATOS_CORE board supports the following features: +------------+------------+-------------------------------------+ | Interface | Controller | Driver/Component | +============+============+=====================================+ -+------------+------------+-------------------------------------+ | UART | on-chip | serial port | +------------+------------+-------------------------------------+ | GPIO | on-chip | gpio | @@ -124,7 +123,7 @@ MCUboot bootloader ================== User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. +must be built (and flashed) at least once. There are two options to be used when building an application: @@ -135,9 +134,10 @@ There are two options to be used when building an application: User can select the MCUboot bootloader by adding the following line to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y Sysbuild ======== @@ -149,7 +149,7 @@ To build the sample application using sysbuild use the command: .. zephyr-app-commands:: :tool: west - :app: samples/hello_world + :zephyr-app: samples/hello_world :board: esp32c3_luatos_core :goals: build :west-args: --sysbuild @@ -185,7 +185,7 @@ Manual build ============ During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. +For that reason, images can be built one at a time using traditional build. The instructions following are relevant for both manual build and sysbuild. The only difference is the structure of the build directory. @@ -203,7 +203,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``esp32c3_luatos_core`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -230,13 +230,13 @@ Debugging As with much custom hardware, the ESP32-C3 modules require patches to OpenOCD that are not upstreamed yet. Espressif maintains their own fork of -the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_. The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the ``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` parameter when building. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -244,7 +244,7 @@ Here is an example for building the :ref:`hello_world` application. :goals: build flash :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dtsi b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dtsi index f4c4f553a9a..c7b5b627547 100644 --- a/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dtsi +++ b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dtsi @@ -43,10 +43,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - &uart0 { status = "okay"; current-speed = <115200>; diff --git a/boards/luatos/esp32c3_luatos_core/support/openocd.cfg b/boards/luatos/esp32c3_luatos_core/support/openocd.cfg index b93b20ba46e..12065b5e630 100644 --- a/boards/luatos/esp32c3_luatos_core/support/openocd.cfg +++ b/boards/luatos/esp32c3_luatos_core/support/openocd.cfg @@ -9,4 +9,4 @@ source [find interface/esp_usb_jtag.cfg] # source [find interface/ftdi/esp32_devkitj_v1.cfg] source [find target/esp32c3.cfg] -adapter_khz 5000 +adapter speed 5000 diff --git a/boards/luatos/esp32s3_luatos_core/doc/index.rst b/boards/luatos/esp32s3_luatos_core/doc/index.rst index 94bc0f685d3..7aa43102069 100644 --- a/boards/luatos/esp32s3_luatos_core/doc/index.rst +++ b/boards/luatos/esp32s3_luatos_core/doc/index.rst @@ -6,9 +6,9 @@ ESP32S3-Luatos-Core Overview ******** -The ESP32S3-LUATOS-CORE development board is a compact board based on Espressif ESP32-S3. +The ESP32S3-Luatos-Core development board is a compact board based on Espressif ESP32-S3. The board comes equipped with a 2.4GHz antenna and supports both Wi-Fi and Bluetooth functionalities. -For more information, check `ESP32S3-LUATOS-CORE`_ (chinese) +For more information, check `ESP32S3-Luatos-Core`_ (chinese) .. image:: img/esp32s3_luatos_core.jpg :align: center @@ -22,7 +22,7 @@ and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual- (Xtensa® 32-bit LX7), a low power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband, RF module, and numerous peripherals. -ESP32S3-LUATOS-CORE includes the following features: +ESP32S3-Luatos-Core includes the following features: - Dual core 32-bit Xtensa Microprocessor (Tensilica LX7), running up to 240MHz - Additional vector instructions support for AI acceleration @@ -75,7 +75,8 @@ Security: - 4-Kbit OTP, up to 1792 bits for users - Cryptographic hardware acceleration: (AES-128/256, Hash, RSA, RNG, HMAC, Digital signature) -For more information, check the datasheet at `ESP32-S3 Datasheet`_. +For more information, check the datasheet at `ESP32-S3 Datasheet`_ or the technical reference +manual at `ESP32-S3 Technical Reference Manual`_. .. image:: img/esp32s3_luatos_core_pinout.jpg :align: center @@ -84,12 +85,11 @@ For more information, check the datasheet at `ESP32-S3 Datasheet`_. Supported Features ================== -Current Zephyr's ESP32S3-LUATOS-Core board supports the following features: +Current Zephyr's ESP32S3-Luatos-Core board supports the following features: +------------+------------+-------------------------------------+ | Interface | Controller | Driver/Component | +============+============+=====================================+ -+------------+------------+-------------------------------------+ | UART | on-chip | serial port | +------------+------------+-------------------------------------+ | GPIO | on-chip | gpio | @@ -150,7 +150,7 @@ MCUboot bootloader ================== User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. +must be built (and flashed) at least once. There are two options to be used when building an application: @@ -161,9 +161,10 @@ There are two options to be used when building an application: User can select the MCUboot bootloader by adding the following line to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y Sysbuild ======== @@ -175,7 +176,7 @@ To build the sample application using sysbuild use the command: .. zephyr-app-commands:: :tool: west - :app: samples/hello_world + :zephyr-app: samples/hello_world :board: esp32s3_luatos_core :goals: build :west-args: --sysbuild @@ -211,7 +212,7 @@ Manual build ============ During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. +For that reason, images can be built one at a time using traditional build. The instructions following are relevant for both manual build and sysbuild. The only difference is the structure of the build directory. @@ -232,11 +233,11 @@ If CH343 chip is disabled, You need use the following command to build: .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: esp32s3_luatos_core_usb/esp32s3/procpu + :board: esp32s3_luatos_core/esp32s3/procpu/usb :goals: build The usual ``flash`` target will work with the ``esp32s3_luatos_core`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -261,35 +262,32 @@ message in the monitor: Debugging ********* -ESP32-S3 support on OpenOCD is available upstream as of version 0.12.0. -Download and install OpenOCD from `OpenOCD`_. +ESP32-S3 support on OpenOCD is available at `OpenOCD ESP32`_. ESP32-S3 has a built-in JTAG circuitry and can be debugged without any additional chip. Only an USB cable connected to the D+/D- pins is necessary. -Further documentation can be obtained from the SoC vendor in `JTAG debugging -for ESP32-S3`_. +Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32-S3`_. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: esp32s3_luatos_core/esp32s3/procpu :goals: build flash -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: esp32s3_luatos_core/esp32s3/procpu :goals: debug -.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ -.. _`OpenOCD`: https://github.com/openocd-org/openocd -.. _`ESP32S3-LUATOS-CORE`: https://wiki.luatos.com/chips/esp32s3/board.html References ********** -.. _ESP32S3-LUATOS-CORE User Guide: https://wiki.luatos.com/chips/esp32s3/board.html -.. _ESP32-S3 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-s3-mini-1_mini-1u_datasheet_en.pdf -.. _ESP32 Technical Reference Manual: https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf +.. _`ESP32S3-Luatos-Core`: https://wiki.luatos.com/chips/esp32s3/board.html +.. _`ESP32-S3 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-s3-mini-1_mini-1u_datasheet_en.pdf +.. _`ESP32-S3 Technical Reference Manual`: https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf +.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core.dtsi b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core.dtsi index 4ca147222ac..60365fdcd65 100644 --- a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core.dtsi +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core.dtsi @@ -31,14 +31,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &uart0 { status = "okay"; current-speed = <115200>; diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu.dts b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu.dts index e33c7f43401..510e587925e 100644 --- a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu.dts +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu.dts @@ -17,14 +17,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &trng0 { status = "okay"; }; diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu_usb.dts b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu_usb.dts index 7a251b40e04..b36963af013 100644 --- a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu_usb.dts +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu_usb.dts @@ -17,14 +17,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &trng0 { status = "okay"; }; diff --git a/boards/m5stack/m5stack_atom_lite/doc/index.rst b/boards/m5stack/m5stack_atom_lite/doc/index.rst index 2e8c1fade47..6a47c4a7f32 100644 --- a/boards/m5stack/m5stack_atom_lite/doc/index.rst +++ b/boards/m5stack/m5stack_atom_lite/doc/index.rst @@ -96,7 +96,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``m5stack_atom_lite`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: diff --git a/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_appcpu.dts b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_appcpu.dts index 59a908a3fef..f5db6e76116 100644 --- a/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_appcpu.dts +++ b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_appcpu.dts @@ -18,14 +18,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &ipm0 { status = "okay"; }; diff --git a/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_procpu.dts b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_procpu.dts index 9d953801e1d..3a8557f6794 100644 --- a/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_procpu.dts +++ b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_procpu.dts @@ -54,14 +54,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &uart0 { status = "okay"; current-speed = <115200>; diff --git a/boards/m5stack/m5stack_atoms3/doc/index.rst b/boards/m5stack/m5stack_atoms3/doc/index.rst index c053f73c101..69bff1ee0cf 100644 --- a/boards/m5stack/m5stack_atoms3/doc/index.rst +++ b/boards/m5stack/m5stack_atoms3/doc/index.rst @@ -98,7 +98,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``m5stack_atoms3`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: diff --git a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_appcpu.dts b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_appcpu.dts index 91bcff6c007..a117ee02922 100644 --- a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_appcpu.dts +++ b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_appcpu.dts @@ -17,14 +17,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &trng0 { status = "okay"; }; diff --git a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_procpu.dts b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_procpu.dts index 376056af071..dd20fb00a8d 100644 --- a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_procpu.dts +++ b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_procpu.dts @@ -9,6 +9,7 @@ #include "m5stack_atoms3-pinctrl.dtsi" #include "grove_connectors.dtsi" #include +#include / { model = "M5Stack AtomS3 PROCPU"; @@ -49,14 +50,45 @@ regulator-boot-on; }; -}; + mipi_dbi { + compatible = "zephyr,mipi-dbi-spi"; + spi-dev = <&spi2>; + dc-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; /* G33 */ + reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; /* G34 */ + write-only; + #address-cells = <1>; + #size-cells = <0>; + + st7789v: st7789v@0 { + compatible = "sitronix,st7789v"; + reg = <0>; + mipi-max-frequency = <27000000>; + + width = <128>; + height = <128>; + x-offset = <2>; + y-offset = <1>; + + vcom = <0x28>; + gctrl = <0x35>; + vrhs = <0x10>; + vdvs = <0x20>; + mdac = <0x00>; + gamma = <0x01>; + colmod = <0x55>; + lcm = <0x0c>; + porch-param = [0c 0c 00 33 33]; + cmd2en-param = [5a 69 02 00]; + pwctrl1-param = [a4 a1]; + pvgam-param = [d0 00 02 07 0a 28 32 44 42 06 0e 12 14 17]; + nvgam-param = [d0 00 02 07 0a 28 31 54 47 0e 1c 17 1b 1e]; + ram-param = [00 E0]; + rgb-param = [40 02 14]; + mipi-mode = ; + }; -&cpu0 { - clock-frequency = ; -}; + }; -&cpu1 { - clock-frequency = ; }; &usb_serial { @@ -100,36 +132,6 @@ status = "okay"; pinctrl-0 = <&spim2_default>; pinctrl-names = "default"; - - st7789v: st7789v@0 { - compatible = "sitronix,st7789v"; - reg = <0>; - spi-max-frequency = <27000000>; - cmd-data-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; /* G33 */ - reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; /* G34 */ - - width = <128>; - height = <128>; - x-offset = <2>; - y-offset = <1>; - - vcom = <0x28>; - gctrl = <0x35>; - vrhs = <0x10>; - vdvs = <0x20>; - mdac = <0x00>; - gamma = <0x01>; - colmod = <0x55>; - lcm = <0x0c>; - porch-param = [0c 0c 00 33 33]; - cmd2en-param = [5a 69 02 00]; - pwctrl1-param = [a4 a1]; - pvgam-param = [d0 00 02 07 0a 28 32 44 42 06 0e 12 14 17]; - nvgam-param = [d0 00 02 07 0a 28 31 54 47 0e 1c 17 1b 1e]; - ram-param = [00 E0]; - rgb-param = [40 02 14]; - }; - }; &gpio0 { diff --git a/boards/m5stack/m5stack_atoms3_lite/doc/index.rst b/boards/m5stack/m5stack_atoms3_lite/doc/index.rst index 204d8e5bbec..ffbe8f1cb05 100644 --- a/boards/m5stack/m5stack_atoms3_lite/doc/index.rst +++ b/boards/m5stack/m5stack_atoms3_lite/doc/index.rst @@ -96,7 +96,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``m5stack_atoms3_lite`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: diff --git a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_appcpu.dts b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_appcpu.dts index 994c9b9a3b2..2323548e7fc 100644 --- a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_appcpu.dts +++ b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_appcpu.dts @@ -17,14 +17,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &trng0 { status = "okay"; }; diff --git a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_procpu.dts b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_procpu.dts index 708fdb5a114..166ee2014ca 100644 --- a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_procpu.dts +++ b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_procpu.dts @@ -43,14 +43,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &usb_serial { status = "okay"; }; diff --git a/boards/m5stack/m5stack_core2/doc/index.rst b/boards/m5stack/m5stack_core2/doc/index.rst index 3e492af3532..02ba5fa7249 100644 --- a/boards/m5stack/m5stack_core2/doc/index.rst +++ b/boards/m5stack/m5stack_core2/doc/index.rst @@ -79,7 +79,7 @@ of the M5Stack Core2 board. | MPU6886 | combines a 3-axis gyroscope and a 3-axis accelerometer. | | | | For details please refer to :ref:`m5stack_core2_ext` | | +------------------+--------------------------------------------------------------------------+-----------+ -| Grove port | Note: Grove port requires 5V to be enabled via `bus_5v` regulator | supported | +| Grove port | Note: Grove port requires 5V to be enabled via ``bus_5v`` regulator | supported | +------------------+--------------------------------------------------------------------------+-----------+ | Built-in | The `SPM-1423`_ I2S driven microphone. | todo | | microphone | | | @@ -183,7 +183,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``m5stack_core2`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: diff --git a/boards/m5stack/m5stack_core2/m5stack_core2_appcpu.dts b/boards/m5stack/m5stack_core2/m5stack_core2_appcpu.dts index cd5cf5d0bf2..875d0eaea2a 100644 --- a/boards/m5stack/m5stack_core2/m5stack_core2_appcpu.dts +++ b/boards/m5stack/m5stack_core2/m5stack_core2_appcpu.dts @@ -18,14 +18,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &ipm0 { status = "okay"; }; diff --git a/boards/m5stack/m5stack_core2/m5stack_core2_procpu.dts b/boards/m5stack/m5stack_core2/m5stack_core2_procpu.dts index 0d9f38e7678..841dcdf38be 100644 --- a/boards/m5stack/m5stack_core2/m5stack_core2_procpu.dts +++ b/boards/m5stack/m5stack_core2/m5stack_core2_procpu.dts @@ -74,14 +74,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &psram0 { reg = <0x3f800000 DT_SIZE_M(8)>; status = "disabled"; diff --git a/boards/m5stack/m5stack_stamps3/doc/index.rst b/boards/m5stack/m5stack_stamps3/doc/index.rst index 59e1d5145aa..36881121e8a 100644 --- a/boards/m5stack/m5stack_stamps3/doc/index.rst +++ b/boards/m5stack/m5stack_stamps3/doc/index.rst @@ -153,7 +153,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``m5stack_stamps3`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: diff --git a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_appcpu.dts b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_appcpu.dts index a9e590b9bbf..ce947b57972 100644 --- a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_appcpu.dts +++ b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_appcpu.dts @@ -17,14 +17,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &trng0 { status = "okay"; }; diff --git a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_procpu.dts b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_procpu.dts index e1a92d331a8..9e231fba57f 100644 --- a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_procpu.dts +++ b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_procpu.dts @@ -46,14 +46,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &usb_serial { status = "okay"; }; diff --git a/boards/m5stack/m5stickc_plus/doc/index.rst b/boards/m5stack/m5stickc_plus/doc/index.rst index 1e5907d50cd..4fe431fea84 100644 --- a/boards/m5stack/m5stickc_plus/doc/index.rst +++ b/boards/m5stack/m5stickc_plus/doc/index.rst @@ -87,18 +87,21 @@ below to retrieve those files. Building & Flashing ******************* -ESP-IDF bootloader -================== +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. + Simple boot does not provide any security features nor OTA updates. MCUboot bootloader ================== User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. +must be built (and flashed) at least once. There are two options to be used when building an application: @@ -109,9 +112,10 @@ There are two options to be used when building an application: User can select the MCUboot bootloader by adding the following line to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y Sysbuild ======== @@ -123,7 +127,7 @@ To build the sample application using sysbuild use the command: .. zephyr-app-commands:: :tool: west - :app: samples/hello_world + :zephyr-app: samples/hello_world :board: m5stickc_plus :goals: build :west-args: --sysbuild @@ -159,7 +163,7 @@ Manual build ============ During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. +For that reason, images can be built one at a time using traditional build. The instructions following are relevant for both manual build and sysbuild. The only difference is the structure of the build directory. @@ -177,7 +181,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``m5stickc_plus`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: diff --git a/boards/m5stack/m5stickc_plus/m5stickc_plus_appcpu.dts b/boards/m5stack/m5stickc_plus/m5stickc_plus_appcpu.dts index 8b7e74fdd98..1911e4fe56d 100644 --- a/boards/m5stack/m5stickc_plus/m5stickc_plus_appcpu.dts +++ b/boards/m5stack/m5stickc_plus/m5stickc_plus_appcpu.dts @@ -18,14 +18,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &ipm0 { status = "okay"; }; diff --git a/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu.dts b/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu.dts index 651610a1fe5..28779d87ecb 100644 --- a/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu.dts +++ b/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu.dts @@ -9,6 +9,7 @@ #include "m5stickc_plus-pinctrl.dtsi" #include #include +#include / { model = "M5StickC Plus PROCPU"; @@ -59,14 +60,44 @@ zephyr,code = ; }; }; -}; - -&cpu0 { - clock-frequency = ; -}; -&cpu1 { - clock-frequency = ; + mipi_dbi { + compatible = "zephyr,mipi-dbi-spi"; + spi-dev = <&spi3>; + dc-gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; + write-only; + #address-cells = <1>; + #size-cells = <0>; + + st7789v: st7789v@0 { + compatible = "sitronix,st7789v"; + reg = <0>; + mipi-max-frequency = <20000000>; + + width = <135>; + height = <240>; + x-offset = <53>; + y-offset = <40>; + + vcom = <0x28>; + gctrl = <0x35>; + vrhs = <0x10>; + vdvs = <0x20>; + mdac = <0x00>; + gamma = <0x01>; + colmod = <0x55>; + lcm = <0x2c>; + porch-param = [0c 0c 00 33 33]; + cmd2en-param = [5a 69 02 00]; + pwctrl1-param = [a4 a1]; + pvgam-param = [d0 00 02 07 0a 28 32 44 42 06 0e 12 14 17]; + nvgam-param = [d0 00 02 07 0a 28 31 54 47 0e 1c 17 1b 1e]; + ram-param = [00 F0]; + rgb-param = [40 02 14]; + mipi-mode = ; + }; + }; }; &uart0 { @@ -161,34 +192,6 @@ status = "okay"; pinctrl-0 = <&spim3_default>; pinctrl-names = "default"; - st7789v: st7789v@0 { - compatible = "sitronix,st7789v"; - reg = <0>; - spi-max-frequency = <20000000>; - cmd-data-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; - reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; - - width = <135>; - height = <240>; - x-offset = <53>; - y-offset = <40>; - - vcom = <0x28>; - gctrl = <0x35>; - vrhs = <0x10>; - vdvs = <0x20>; - mdac = <0x00>; - gamma = <0x01>; - colmod = <0x55>; - lcm = <0x2c>; - porch-param = [0c 0c 00 33 33]; - cmd2en-param = [5a 69 02 00]; - pwctrl1-param = [a4 a1]; - pvgam-param = [d0 00 02 07 0a 28 32 44 42 06 0e 12 14 17]; - nvgam-param = [d0 00 02 07 0a 28 31 54 47 0e 1c 17 1b 1e]; - ram-param = [00 F0]; - rgb-param = [40 02 14]; - }; }; &timer0 { diff --git a/boards/m5stack/stamp_c3/doc/index.rst b/boards/m5stack/stamp_c3/doc/index.rst index 9ac2a05b7ec..40869ee0166 100644 --- a/boards/m5stack/stamp_c3/doc/index.rst +++ b/boards/m5stack/stamp_c3/doc/index.rst @@ -56,18 +56,21 @@ below to retrieve those files. Building & Flashing ******************* -ESP-IDF bootloader -================== +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. + Simple boot does not provide any security features nor OTA updates. MCUboot bootloader ================== User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. +must be built (and flashed) at least once. There are two options to be used when building an application: @@ -78,9 +81,10 @@ There are two options to be used when building an application: User can select the MCUboot bootloader by adding the following line to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y Sysbuild ======== @@ -92,7 +96,7 @@ To build the sample application using sysbuild use the command: .. zephyr-app-commands:: :tool: west - :app: samples/hello_world + :zephyr-app: samples/hello_world :board: stamp_c3 :goals: build :west-args: --sysbuild @@ -128,7 +132,7 @@ Manual build ============ During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. +For that reason, images can be built one at a time using traditional build. The instructions following are relevant for both manual build and sysbuild. The only difference is the structure of the build directory. @@ -146,7 +150,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``stamp_c3`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -173,13 +177,13 @@ Debugging As with much custom hardware, the ESP32 modules require patches to OpenOCD that are not upstreamed yet. Espressif maintains their own fork of -the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_. The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the ``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` parameter when building. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -187,7 +191,7 @@ Here is an example for building the :ref:`hello_world` application. :goals: build flash :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/m5stack/stamp_c3/stamp_c3.dts b/boards/m5stack/stamp_c3/stamp_c3.dts index 09370c3d30a..ef026e94454 100644 --- a/boards/m5stack/stamp_c3/stamp_c3.dts +++ b/boards/m5stack/stamp_c3/stamp_c3.dts @@ -39,10 +39,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - &uart0 { status = "okay"; current-speed = <115200>; diff --git a/boards/m5stack/stamp_c3/support/openocd.cfg b/boards/m5stack/stamp_c3/support/openocd.cfg index 5db52f70d83..92e47fabefb 100644 --- a/boards/m5stack/stamp_c3/support/openocd.cfg +++ b/boards/m5stack/stamp_c3/support/openocd.cfg @@ -6,4 +6,4 @@ set ESP_RTOS none source [find interface/esp_usb_jtag.cfg] source [find target/esp32c3.cfg] -adapter_khz 5000 +adapter speed 5000 diff --git a/boards/madmachine/mm_feather/doc/index.rst b/boards/madmachine/mm_feather/doc/index.rst index 5b53ddfc586..0a556bc42b0 100644 --- a/boards/madmachine/mm_feather/doc/index.rst +++ b/boards/madmachine/mm_feather/doc/index.rst @@ -195,7 +195,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Connect a DAPLink debugger from your PC to corresponding SWD pins of SwiftIO Feather. @@ -215,7 +215,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/madmachine/mm_swiftio/doc/index.rst b/boards/madmachine/mm_swiftio/doc/index.rst index d9361404d57..5fb0837e1ea 100644 --- a/boards/madmachine/mm_swiftio/doc/index.rst +++ b/boards/madmachine/mm_swiftio/doc/index.rst @@ -206,7 +206,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Connect a USB cable from your PC to "Serial" port of SwiftIO. On Ubuntu, DAPLink debug probes appear on the host diff --git a/boards/makerdiary/nrf52832_mdk/Kconfig b/boards/makerdiary/nrf52832_mdk/Kconfig deleted file mode 100644 index 29e4f6a9e8b..00000000000 --- a/boards/makerdiary/nrf52832_mdk/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# nRF52832-MDK board configuration - -# Copyright (c) 2018 makerdiary.com. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_NRF52832_MDK diff --git a/boards/makerdiary/nrf52832_mdk/nrf52832_mdk.dts b/boards/makerdiary/nrf52832_mdk/nrf52832_mdk.dts index c51002c6497..c1b85fd017c 100644 --- a/boards/makerdiary/nrf52832_mdk/nrf52832_mdk.dts +++ b/boards/makerdiary/nrf52832_mdk/nrf52832_mdk.dts @@ -86,6 +86,10 @@ }; +® { + regulator-initial-mode = ; +}; + &uicr { gpio-as-nreset; }; diff --git a/boards/makerdiary/nrf52840_mdk/Kconfig b/boards/makerdiary/nrf52840_mdk/Kconfig deleted file mode 100644 index d8f69578087..00000000000 --- a/boards/makerdiary/nrf52840_mdk/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# nRF52840-MDK board configuration - -# Copyright (c) 2018 makerdiary.com -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_NRF52840_MDK diff --git a/boards/makerdiary/nrf52840_mdk/nrf52840_mdk.dts b/boards/makerdiary/nrf52840_mdk/nrf52840_mdk.dts index 2439b0c2aca..086d9bddb13 100644 --- a/boards/makerdiary/nrf52840_mdk/nrf52840_mdk.dts +++ b/boards/makerdiary/nrf52840_mdk/nrf52840_mdk.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include "nrf52840_mdk-pinctrl.dtsi" #include @@ -19,9 +20,6 @@ zephyr,uart-mcumgr = &uart0; zephyr,bt-mon-uart = &uart0; zephyr,bt-c2h-uart = &uart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; zephyr,ieee802154 = &ieee802154; }; @@ -82,10 +80,13 @@ red-pwm-led = &pwm_led1_red; blue-pwm-led = &pwm_led2_blue; watchdog0 = &wdt0; - spi-flash0 = &mx25r64; }; }; +®1 { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; @@ -167,46 +168,6 @@ status = "okay"; }; -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000C000>; - }; - slot0_partition: partition@c000 { - label = "image-0"; - reg = <0x0000C000 0x00067000>; - }; - slot1_partition: partition@73000 { - label = "image-1"; - reg = <0x00073000 0x00067000>; - }; - scratch_partition: partition@da000 { - label = "image-scratch"; - reg = <0x000da000 0x0001e000>; - }; - - /* - * The flash starting at 0x000f8000 and ending at - * 0x000fffff is reserved for use by the application. - */ - - /* - * Storage partition will be used by FCB/LittleFS/NVS - * if enabled. - */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; - zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; diff --git a/boards/makerdiary/nrf52840_mdk_usb_dongle/Kconfig b/boards/makerdiary/nrf52840_mdk_usb_dongle/Kconfig index fb658864a0b..89dc99d19cc 100644 --- a/boards/makerdiary/nrf52840_mdk_usb_dongle/Kconfig +++ b/boards/makerdiary/nrf52840_mdk_usb_dongle/Kconfig @@ -4,18 +4,10 @@ # Copyright (c) 2018 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -if BOARD_NRF52840_MDK_USB_DONGLE - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - config BOARD_HAS_NRF5_BOOTLOADER bool "Board has nRF5 bootloader" default y + depends on BOARD_NRF52840_MDK_USB_DONGLE help If selected, applications are linked so that they can be loaded by Nordic nRF5 bootloader. - -endif # BOARD_NRF52840_MDK_USB_DONGLE diff --git a/boards/makerdiary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.dts b/boards/makerdiary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.dts index 4e13783d656..763aebe86e7 100644 --- a/boards/makerdiary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.dts +++ b/boards/makerdiary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.dts @@ -83,6 +83,10 @@ }; }; +®1 { + regulator-initial-mode = ; +}; + &gpiote { status = "okay"; }; diff --git a/boards/makerdiary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.yaml b/boards/makerdiary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.yaml index 5aac2cd5701..e714e1cafb5 100644 --- a/boards/makerdiary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.yaml +++ b/boards/makerdiary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.yaml @@ -10,7 +10,6 @@ toolchain: - xtools supported: - usb_device - - usb_cdc - ble - watchdog - counter diff --git a/boards/mediatek/mt8195_adsp/Kconfig.defconfig b/boards/mediatek/mt8195_adsp/Kconfig.defconfig new file mode 100644 index 00000000000..31f557670b1 --- /dev/null +++ b/boards/mediatek/mt8195_adsp/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright 2023 The ChromiumOS Authors +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MT8195_ADSP + +config BOARD + default "mt8195_adsp" + +endif # BOARD_MT8195_ADSP diff --git a/boards/mediatek/mt8195_adsp/Kconfig.mt8195_adsp b/boards/mediatek/mt8195_adsp/Kconfig.mt8195_adsp new file mode 100644 index 00000000000..43a3a49f9e1 --- /dev/null +++ b/boards/mediatek/mt8195_adsp/Kconfig.mt8195_adsp @@ -0,0 +1,7 @@ +# Copyright 2023 The ChromiumOS Authors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MT8195_ADSP + select SOC_MT8195_ADSP + help + Board with Mediatek MT8195 Audio DSP diff --git a/boards/mediatek/mt8195_adsp/board.yml b/boards/mediatek/mt8195_adsp/board.yml new file mode 100644 index 00000000000..22c31deb1a0 --- /dev/null +++ b/boards/mediatek/mt8195_adsp/board.yml @@ -0,0 +1,5 @@ +boards: + - name: mt8195_adsp + vendor: mediatek + socs: + - name: mt8195_adsp diff --git a/boards/mediatek/mt8195_adsp/mt8195_adsp.dts b/boards/mediatek/mt8195_adsp/mt8195_adsp.dts new file mode 100644 index 00000000000..c26e2dd0f40 --- /dev/null +++ b/boards/mediatek/mt8195_adsp/mt8195_adsp.dts @@ -0,0 +1,95 @@ +/* Copyright 2023 The ChromiumOS Authors + * SPDX-License-Identifier: Apache-2.0 + */ +#include + +/dts-v1/; +/ { + +#address-cells = <1>; +#size-cells = <1>; + +sram0: memory@40000000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x40000000 DT_SIZE_K(256)>; +}; + +dram0: memory@60000000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x60000000 DT_SIZE_M(17)>; +}; + +soc { + #address-cells = <1>; + #size-cells = <1>; + + cpuclk: cpuclk@10000000 { + compatible = "mediatek,mt8195_cpuclk"; + reg = <0x10000000 380>; + cg_reg = <0x10720180>; + pll_ctrl_reg = <0x1000c7e0>; + freqs_mhz = <26 370 540 720>; + }; + + core_intc: core_intc@0 { + compatible = "cdns,xtensa-core-intc"; + reg = <0 4>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + intc1: intc@10680130 { + compatible = "mediatek,adsp_intc"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x10680130 4>; + status-reg = <0x10680150>; + interrupts = <1 0 0>; + mask = <0x3ffffff0>; + interrupt-parent = <&core_intc>; + }; + + intc23: intc@108030f4 { + compatible = "mediatek,adsp_intc"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x108030f4 4>; + status-reg = <0x108030fc>; + interrupts = <23 0 0>; + mask = <0xffff>; + interrupt-parent = <&core_intc>; + }; + + ostimer64: ostimer64@1080d080 { + compatible = "mediatek,ostimer64"; + reg = <0x1080d080 28>; + }; + + ostimer0: ostimer@1080d000 { + compatible = "mediatek,ostimer"; + reg = <0x1080d000 16>; + interrupt-parent = <&intc23>; + interrupts = <11 0 0>; + }; + + mbox0: mbox@10816000 { + compatible = "mediatek,mbox"; + reg = <0x10816000 56>; + interrupt-parent = <&intc23>; + interrupts = <0 0 0>; + }; + + mbox1: mbox@10817000 { + compatible = "mediatek,mbox"; + reg = <0x10817000 56>; + interrupt-parent = <&intc23>; + interrupts = <1 0 0>; + }; +}; /* soc */ + +chosen { }; +aliases { }; + +}; diff --git a/boards/mediatek/mt8195_adsp/mt8195_adsp_defconfig b/boards/mediatek/mt8195_adsp/mt8195_adsp_defconfig new file mode 100644 index 00000000000..1110a4cfeb1 --- /dev/null +++ b/boards/mediatek/mt8195_adsp/mt8195_adsp_defconfig @@ -0,0 +1,4 @@ +# Copyright 2023 The ChromiumOS Authors +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=13000000 diff --git a/boards/microchip/m2gl025_miv/board.cmake b/boards/microchip/m2gl025_miv/board.cmake index 2919ac78742..b2d72a05eca 100644 --- a/boards/microchip/m2gl025_miv/board.cmake +++ b/boards/microchip/m2gl025_miv/board.cmake @@ -3,3 +3,8 @@ set(SUPPORTED_EMU_PLATFORMS renode) set(RENODE_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/support/m2gl025_miv.resc) set(RENODE_UART sysbus.uart) + +set_ifndef(BOARD_SIM_RUNNER renode) +set_ifndef(BOARD_ROBOT_RUNNER renode-robot) +include(${ZEPHYR_BASE}/boards/common/renode.board.cmake) +include(${ZEPHYR_BASE}/boards/common/renode_robot.board.cmake) diff --git a/boards/microchip/m2gl025_miv/m2gl025_miv.yaml b/boards/microchip/m2gl025_miv/m2gl025_miv.yaml index 3f60b02c59e..4ba9e126a7f 100644 --- a/boards/microchip/m2gl025_miv/m2gl025_miv.yaml +++ b/boards/microchip/m2gl025_miv/m2gl025_miv.yaml @@ -12,4 +12,7 @@ testing: ignore_tags: - net - bluetooth + renode: + uart: sysbus.uart + resc: boards/microchip/m2gl025_miv/support/m2gl025_miv.resc vendor: microchip diff --git a/boards/microchip/m2gl025_miv/support/m2gl025_miv.resc b/boards/microchip/m2gl025_miv/support/m2gl025_miv.resc index 2227e89bff2..d45eb5e7855 100644 --- a/boards/microchip/m2gl025_miv/support/m2gl025_miv.resc +++ b/boards/microchip/m2gl025_miv/support/m2gl025_miv.resc @@ -12,6 +12,6 @@ cpu PerformanceInMips 4 macro reset """ - sysbus LoadELF $bin + sysbus LoadELF $elf """ runMacro $reset diff --git a/boards/microchip/mec1501modular_assy6885/doc/index.rst b/boards/microchip/mec1501modular_assy6885/doc/index.rst index a74f48163fb..a70c20ee961 100644 --- a/boards/microchip/mec1501modular_assy6885/doc/index.rst +++ b/boards/microchip/mec1501modular_assy6885/doc/index.rst @@ -260,7 +260,7 @@ Setup Building ========== -#. Build :ref:`hello_world` application as you would normally do. +#. Build :zephyr:code-sample:`hello_world` application as you would normally do. #. Once you have ``zephyr.bin``, use the `MEC152x SPI Image Gen`_ microchip tool to create the final binary. You need the output from this tool to flash diff --git a/boards/microchip/mec15xxevb_assy6853/doc/index.rst b/boards/microchip/mec15xxevb_assy6853/doc/index.rst index e3b29e99212..4eafd2e758c 100644 --- a/boards/microchip/mec15xxevb_assy6853/doc/index.rst +++ b/boards/microchip/mec15xxevb_assy6853/doc/index.rst @@ -352,7 +352,7 @@ Wiring Building ======== -#. Build :ref:`hello_world` application as you would normally do. +#. Build :zephyr:code-sample:`hello_world` application as you would normally do. #. The file :file:`spi_image.bin` will be created if the build system can find the image generation tool. This binary image can be used diff --git a/boards/microchip/mec172xevb_assy6906/doc/index.rst b/boards/microchip/mec172xevb_assy6906/doc/index.rst index a2100e5a2d6..4765d787d94 100644 --- a/boards/microchip/mec172xevb_assy6906/doc/index.rst +++ b/boards/microchip/mec172xevb_assy6906/doc/index.rst @@ -360,7 +360,7 @@ Wiring Building ======== -#. Build :ref:`hello_world` application as you would normally do. +#. Build :zephyr:code-sample:`hello_world` application as you would normally do. #. The file :file:`spi_image.bin` will be created if the build system can find the image generation tool. This binary image can be used diff --git a/boards/microchip/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.rst b/boards/microchip/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.rst index a3a85487342..a85226e87d0 100644 --- a/boards/microchip/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.rst +++ b/boards/microchip/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.rst @@ -241,7 +241,7 @@ Wiring Building ======== -#. Build :ref:`hello_world` application as you would normally do. +#. Build :zephyr:code-sample:`hello_world` application as you would normally do. #. The file :file:`spi_image.bin` will be created if the build system can find the image generation tool. This binary image can be used diff --git a/boards/microchip/mpfs_icicle/Kconfig b/boards/microchip/mpfs_icicle/Kconfig deleted file mode 100644 index bbacc84d304..00000000000 --- a/boards/microchip/mpfs_icicle/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2021-2022 Microchip Technology Inc -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MPFS_ICICLE - select 64BIT - select SCHED_IPI_SUPPORTED - select CPU_HAS_FPU_DOUBLE_PRECISION diff --git a/boards/microchip/mpfs_icicle/Kconfig.mpfs_icicle b/boards/microchip/mpfs_icicle/Kconfig.mpfs_icicle index cc744a4f940..2efd9446c73 100644 --- a/boards/microchip/mpfs_icicle/Kconfig.mpfs_icicle +++ b/boards/microchip/mpfs_icicle/Kconfig.mpfs_icicle @@ -2,4 +2,6 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_MPFS_ICICLE - select SOC_POLARFIRE + select SOC_POLARFIRE_U54 if BOARD_MPFS_ICICLE_POLARFIRE_U54 || \ + BOARD_MPFS_ICICLE_POLARFIRE_U54_SMP + select SOC_POLARFIRE_E51 if BOARD_MPFS_ICICLE_POLARFIRE_E51 diff --git a/boards/microchip/mpfs_icicle/board.cmake b/boards/microchip/mpfs_icicle/board.cmake deleted file mode 100644 index 0fed4848fa9..00000000000 --- a/boards/microchip/mpfs_icicle/board.cmake +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS renode) -set(RENODE_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/support/mpfs250t.resc) diff --git a/boards/microchip/mpfs_icicle/board.yml b/boards/microchip/mpfs_icicle/board.yml index f97e2409c14..b9799c5830e 100644 --- a/boards/microchip/mpfs_icicle/board.yml +++ b/boards/microchip/mpfs_icicle/board.yml @@ -4,4 +4,5 @@ board: socs: - name: polarfire variants: - - name: 'smp' + - name: smp + cpucluster: u54 diff --git a/boards/microchip/mpfs_icicle/doc/index.rst b/boards/microchip/mpfs_icicle/doc/index.rst index 203745dc4ee..10ab696ae03 100644 --- a/boards/microchip/mpfs_icicle/doc/index.rst +++ b/boards/microchip/mpfs_icicle/doc/index.rst @@ -45,7 +45,7 @@ To establish an OpenOCD connection run: .. code-block:: bash sudo LD_LIBRARY_PATH=/openocd/bin \ - /openocd/bin/openocd --file \ + /openocd/bin/openocd --command "set DEVICE MPFS" --file \ /openocd/share/openocd/scripts/board/microsemi-riscv.cfg diff --git a/boards/microchip/mpfs_icicle/mpfs_icicle.dts b/boards/microchip/mpfs_icicle/mpfs_icicle.dts deleted file mode 100644 index 902180c0a14..00000000000 --- a/boards/microchip/mpfs_icicle/mpfs_icicle.dts +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2020-2021 Microchip Technology Inc - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include -#include - -/ { - model = "Microchip PolarFire-SoC Icicle Kit"; - compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs"; - aliases { - led0 = &led0; - sw0 = &sw0; - i2c0 = &i2c0; - i2c1 = &i2c1; - }; - - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,sram = &sram1; - }; - - leds { - compatible = "gpio-leds"; - - led0: led0 { - gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; - label = "LED_0"; - }; - }; - - keys { - compatible = "gpio-keys"; - sw0: sw0 { - gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; - label = "SW_0"; - zephyr,code = ; - }; - }; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - clock-frequency = <150000000>; -}; - -&qspi0 { - status = "okay"; - qspi_flash: spi-nor-flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <5000000>; - size = ; - jedec-id = [20 ba 19]; - }; -}; - -&spi1 { - status = "okay"; -}; - -&syscontroller_qspi { - status = "okay"; - sys_ctrl_flash: spi-nor-flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <5000000>; - }; -}; - -&gpio2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; diff --git a/boards/microchip/mpfs_icicle/mpfs_icicle.yaml b/boards/microchip/mpfs_icicle/mpfs_icicle.yaml deleted file mode 100644 index 19e051474e6..00000000000 --- a/boards/microchip/mpfs_icicle/mpfs_icicle.yaml +++ /dev/null @@ -1,12 +0,0 @@ -identifier: mpfs_icicle -name: Microchip PolarFire ICICLE kit -type: mcu -arch: riscv -toolchain: - - zephyr -ram: 3840 -testing: - ignore_tags: - - net - - bluetooth -vendor: microchip diff --git a/boards/microchip/mpfs_icicle/mpfs_icicle_common.dtsi b/boards/microchip/mpfs_icicle/mpfs_icicle_common.dtsi new file mode 100644 index 00000000000..0f615ccb861 --- /dev/null +++ b/boards/microchip/mpfs_icicle/mpfs_icicle_common.dtsi @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2020-2021 Microchip Technology Inc + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include + +/ { + model = "microchip,mpfs-icicle-kit"; + compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs"; + aliases { + led0 = &led0; + sw0 = &sw0; + i2c0 = &i2c0; + i2c1 = &i2c1; + }; + + leds { + compatible = "gpio-leds"; + + led0: led0 { + gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; + label = "LED_0"; + }; + }; + + keys { + compatible = "gpio-keys"; + sw0: sw0 { + gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; + label = "SW_0"; + zephyr,code = ; + }; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <150000000>; +}; + +&qspi0 { + status = "okay"; + qspi_flash: spi-nor-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <5000000>; + size = ; + jedec-id = [20 ba 19]; + }; +}; + +&spi1 { + status = "okay"; +}; + +&syscontroller_qspi { + status = "okay"; + sys_ctrl_flash: spi-nor-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <5000000>; + }; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; diff --git a/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_e51.dts b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_e51.dts new file mode 100644 index 00000000000..63287f678aa --- /dev/null +++ b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_e51.dts @@ -0,0 +1,31 @@ +/dts-v1/; +#include "mpfs_icicle_common.dtsi" + +/ { + compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs"; + + cpus { + cpu@1 { + status = "disabled"; + }; + + cpu@2 { + status = "disabled"; + }; + + cpu@3 { + status = "disabled"; + }; + + cpu@4 { + status = "disabled"; + }; + }; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &sram1; + }; + +}; diff --git a/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_e51.yaml b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_e51.yaml new file mode 100644 index 00000000000..3518a70f8d8 --- /dev/null +++ b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_e51.yaml @@ -0,0 +1,13 @@ +identifier: mpfs_icicle/polarfire/e51 +name: Microchip PolarFire SoC Icicle Kit +type: mcu +arch: riscv +toolchain: + - zephyr +ram: 3840 +testing: + ignore_tags: + - net + - bluetooth + - flash +vendor: microchip diff --git a/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_e51_defconfig b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_e51_defconfig new file mode 100644 index 00000000000..bfc0590663a --- /dev/null +++ b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_e51_defconfig @@ -0,0 +1,15 @@ +# Copyright (c) 2020-2021 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MPFS_HAL=n +CONFIG_BASE64=y +CONFIG_INCLUDE_RESET_VECTOR=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_XIP=n +CONFIG_INIT_STACKS=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 +# GPIO driver options +CONFIG_GPIO=y +CONFIG_I2C=y diff --git a/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54.dts b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54.dts new file mode 100644 index 00000000000..e1652c96e3e --- /dev/null +++ b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54.dts @@ -0,0 +1,24 @@ +/dts-v1/; +#include "mpfs_icicle_common.dtsi" + +/ { + compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs"; + + cpus { + cpu@0 { + status = "disabled"; + }; + }; + + chosen { + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,sram = &sram1; + }; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <150000000>; +}; diff --git a/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54.yaml b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54.yaml new file mode 100644 index 00000000000..9599b13e1c5 --- /dev/null +++ b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54.yaml @@ -0,0 +1,13 @@ +identifier: mpfs_icicle/polarfire/u54 +name: Microchip PolarFire SoC Icicle Kit +type: mcu +arch: riscv +toolchain: + - zephyr +ram: 3840 +testing: + ignore_tags: + - net + - bluetooth + - flash +vendor: microchip diff --git a/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_defconfig b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_defconfig new file mode 100644 index 00000000000..c40256dbf73 --- /dev/null +++ b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2020-2021 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MPFS_HAL=n +CONFIG_BASE64=y +CONFIG_INCLUDE_RESET_VECTOR=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_XIP=n +CONFIG_INIT_STACKS=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 +CONFIG_RV_BOOT_HART=1 +# GPIO driver options +CONFIG_GPIO=y +CONFIG_I2C=y diff --git a/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_smp.dts b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_smp.dts new file mode 100644 index 00000000000..11af6fb7622 --- /dev/null +++ b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_smp.dts @@ -0,0 +1,18 @@ +/dts-v1/; +#include "mpfs_icicle_polarfire_u54.dts" + +/ { + compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs"; + + chosen { + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,sram = &sram1; + }; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <150000000>; +}; diff --git a/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_smp.yaml b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_smp.yaml new file mode 100644 index 00000000000..6118303c246 --- /dev/null +++ b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_smp.yaml @@ -0,0 +1,13 @@ +identifier: mpfs_icicle/polarfire/u54/smp +name: Microchip PolarFire SoC Icicle Kit +type: mcu +arch: riscv +toolchain: + - zephyr +ram: 3840 +testing: + ignore_tags: + - net + - bluetooth + - flash +vendor: microchip diff --git a/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_smp_defconfig b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_smp_defconfig new file mode 100644 index 00000000000..e12c515e69a --- /dev/null +++ b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_smp_defconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2020-2021 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MPFS_HAL=n +CONFIG_BASE64=y +CONFIG_INCLUDE_RESET_VECTOR=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_XIP=n +CONFIG_INIT_STACKS=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 +# GPIO driver options +CONFIG_GPIO=y +CONFIG_I2C=y +CONFIG_RV_BOOT_HART=1 +CONFIG_SMP=y diff --git a/boards/microchip/mpfs_icicle/mpfs_icicle_smp.dts b/boards/microchip/mpfs_icicle/mpfs_icicle_smp.dts deleted file mode 100644 index 6d122ed5d97..00000000000 --- a/boards/microchip/mpfs_icicle/mpfs_icicle_smp.dts +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) 2020-2021 Microchip Technology Inc - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include -#include - -/ { - model = "Microchip PolarFire-SoC Icicle Kit"; - compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs"; - - cpus { - cpu@0 { - status = "disabled"; - }; - }; - - aliases { - led0 = &led0; - sw0 = &sw0; - i2c0 = &i2c0; - i2c1 = &i2c1; - }; - - chosen { - zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - zephyr,sram = &sram1; - }; - - leds { - compatible = "gpio-leds"; - - led0: led0 { - gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; - label = "LED_0"; - }; - }; - - keys { - compatible = "gpio-keys"; - sw0: sw0 { - gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; - label = "SW_0"; - zephyr,code = ; - }; - }; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; - clock-frequency = <150000000>; -}; - -&qspi0 { - status = "okay"; - qspi_flash: spi-nor-flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <5000000>; - size = ; - jedec-id = [20 ba 19]; - }; -}; - -&spi1 { - status = "okay"; -}; - -&syscontroller_qspi { - status = "okay"; - sys_ctrl_flash: spi-nor-flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <5000000>; - }; -}; - -&gpio2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; diff --git a/boards/microchip/mpfs_icicle/mpfs_icicle_smp.yaml b/boards/microchip/mpfs_icicle/mpfs_icicle_smp.yaml deleted file mode 100644 index 2f7983ca092..00000000000 --- a/boards/microchip/mpfs_icicle/mpfs_icicle_smp.yaml +++ /dev/null @@ -1,12 +0,0 @@ -identifier: mpfs_icicle/polarfire/smp -name: Microchip PolarFire ICICLE kit (SMP) -type: mcu -arch: riscv -toolchain: - - zephyr -ram: 3840 -testing: - ignore_tags: - - net - - bluetooth -vendor: microchip diff --git a/boards/microchip/mpfs_icicle/mpfs_icicle_smp_defconfig b/boards/microchip/mpfs_icicle/mpfs_icicle_smp_defconfig deleted file mode 100644 index 529171d1c46..00000000000 --- a/boards/microchip/mpfs_icicle/mpfs_icicle_smp_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -CONFIG_MPFS_HAL=n -CONFIG_BASE64=y -CONFIG_INCLUDE_RESET_VECTOR=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_XIP=n -CONFIG_INIT_STACKS=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 -CONFIG_GPIO=y -CONFIG_I2C=y -CONFIG_SMP=y -CONFIG_RV_BOOT_HART=1 -CONFIG_MP_MAX_NUM_CPUS=4 diff --git a/boards/microchip/mpfs_icicle/support/mpfs250t.resc b/boards/microchip/mpfs_icicle/support/mpfs250t.resc deleted file mode 100644 index 8892b2839de..00000000000 --- a/boards/microchip/mpfs_icicle/support/mpfs250t.resc +++ /dev/null @@ -1,17 +0,0 @@ -:name: MPFS-ICICLE-KIT -:description: This script is prepared to run Zephyr on a PolarFire SoC Icicle Kit RISC-V board. - -$name?="MPFS-ICICLE-KIT" - -using sysbus -mach create $name -machine LoadPlatformDescription @platforms/boards/mpfs-icicle-kit.repl - -showAnalyzer mmuart0 -e51 PerformanceInMips 80 - -macro reset -""" - sysbus LoadELF $bin -""" -runMacro $reset diff --git a/boards/mikroe/clicker_2/doc/mikroe_clicker_2.rst b/boards/mikroe/clicker_2/doc/mikroe_clicker_2.rst index 99cb9ce0c61..a1ef4aa09ec 100644 --- a/boards/mikroe/clicker_2/doc/mikroe_clicker_2.rst +++ b/boards/mikroe/clicker_2/doc/mikroe_clicker_2.rst @@ -91,7 +91,7 @@ Unlocking with openocd makes it possible to flash. -f /usr/share/openocd/scripts/target/stm32f4x.cfg -c init\ -c "reset halt" -c "stm32f4x unlock 0" -c "reset run" -c shutdown -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -109,7 +109,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/mikroe/clicker_2/mikroe_clicker_2_defconfig b/boards/mikroe/clicker_2/mikroe_clicker_2_defconfig index 2c36e734c57..ea590d02efb 100644 --- a/boards/mikroe/clicker_2/mikroe_clicker_2_defconfig +++ b/boards/mikroe/clicker_2/mikroe_clicker_2_defconfig @@ -9,9 +9,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/mikroe/clicker_ra4m1/Kconfig.mikroe_clicker_ra4m1 b/boards/mikroe/clicker_ra4m1/Kconfig.mikroe_clicker_ra4m1 new file mode 100644 index 00000000000..1fe44feec08 --- /dev/null +++ b/boards/mikroe/clicker_ra4m1/Kconfig.mikroe_clicker_ra4m1 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Ian Morris +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIKROE_CLICKER_RA4M1 + select SOC_R7FA4M1AB3CFM diff --git a/boards/mikroe/clicker_ra4m1/board.cmake b/boards/mikroe/clicker_ra4m1/board.cmake new file mode 100644 index 00000000000..3f00aea418d --- /dev/null +++ b/boards/mikroe/clicker_ra4m1/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Ian Morris +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(pyocd "--target=r7fa4m1ab") + +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/mikroe/clicker_ra4m1/board.yml b/boards/mikroe/clicker_ra4m1/board.yml new file mode 100644 index 00000000000..1635cd26a5d --- /dev/null +++ b/boards/mikroe/clicker_ra4m1/board.yml @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Ian Morris +# SPDX-License-Identifier: Apache-2.0 + +board: + name: mikroe_clicker_ra4m1 + vendor: mikroe + socs: + - name: r7fa4m1ab3cfm diff --git a/boards/mikroe/clicker_ra4m1/doc/img/mikroe_clicker_ra4m1.jpg b/boards/mikroe/clicker_ra4m1/doc/img/mikroe_clicker_ra4m1.jpg new file mode 100644 index 00000000000..0d9acc54989 Binary files /dev/null and b/boards/mikroe/clicker_ra4m1/doc/img/mikroe_clicker_ra4m1.jpg differ diff --git a/boards/mikroe/clicker_ra4m1/doc/index.rst b/boards/mikroe/clicker_ra4m1/doc/index.rst new file mode 100644 index 00000000000..5af9aa1125a --- /dev/null +++ b/boards/mikroe/clicker_ra4m1/doc/index.rst @@ -0,0 +1,87 @@ +.. _mikroe_clicker_ra4m1: + +Mikroe Clicker RA4M1 +#################### + +Overview +******** + +The Mikroe Clicker RA4M1 development board contains a Renesas Cortex-M4 based +R7FA4M1AB3CFM Microcontroller operating at up to 48 MHz with 256 KB of Flash +memory and 32 KB of SRAM. + +.. figure:: img/mikroe_clicker_ra4m1.jpg + :align: center + :alt: Clicker RA4M1 + + Clicker RA4M1 (Credit: MikroElektronika d.o.o.) + +Hardware +******** + +The Clicker RA4M1 board contains a USB Type-C connector, two LEDs, two push +buttons, and a reset button. It has J-Link onboard and mikroBUS socket for +interfacing with external electronics. For more information about the +development board see the `Clicker RA4M1 website`_. + +Supported Features +================== + +The Zephyr Mikroe Clicker RA4M1 configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | GPIO output | +| | | GPIO input | ++-----------+------------+-------------------------------------+ + +Other hardware features have not been enabled yet for this board. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1_defconfig`. + +Programming and debugging +************************* + +Building & Flashing +=================== + +You can build and flash an application in the usual way (See +:ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for building and flashing the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: mikroe_clicker_ra4m1 + :goals: build flash + +Debugging +========= + +Debugging also can be done in the usual way. +The following command is debugging the :zephyr:code-sample:`blinky` application. +Also, see the instructions specific to the debug server that you use. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: mikroe_clicker_ra4m1 + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _Clicker RA4M1 website: + https://www.mikroe.com/ra4m1-clicker diff --git a/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1.dts b/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1.dts new file mode 100644 index 00000000000..b15242c5fea --- /dev/null +++ b/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1.dts @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2024 Ian Morris + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include + +/ { + model = "Mikroe Clicker RA4M1"; + compatible = "renesas,r7fa4m1ab3cfm"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + leds { + compatible = "gpio-leds"; + ld1: led_1 { + gpios = <&ioport4 9 GPIO_ACTIVE_HIGH>; + label = "User LED 1"; + }; + ld2: led_2 { + gpios = <&ioport4 8 GPIO_ACTIVE_HIGH>; + label = "User LED 2"; + }; + }; + + buttons { + compatible = "gpio-keys"; + btn1: button_1 { + gpios = <&ioport3 4 GPIO_ACTIVE_LOW>; + label = "User Button 1"; + zephyr,code = ; + }; + }; + + aliases { + led0 = &ld1; + led1 = &ld2; + sw0 = &btn1; + }; +}; + +&pinctrl { + sci0_default: sci0_default { + group1 { + pinmux = , ; + }; + }; +}; + +&sci0 { + status = "okay"; + pinctrl-0 = <&sci0_default>; + pinctrl-names = "default"; + uart0: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&ioport3 { + status = "okay"; +}; + +&ioport4 { + status = "okay"; +}; + +&fcu { + status = "okay"; +}; + +&mosc { + status = "okay"; + clock-frequency = <12000000>; +}; + +&cgc { + clock-source = <&mosc>; + iclk-div = <1>; + pclka-div = <1>; + pclkb-div = <2>; + pclkc-div = <1>; + pclkd-div = <1>; + fclk-div = <2>; +}; diff --git a/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1.yaml b/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1.yaml new file mode 100644 index 00000000000..9cc16dc9c8d --- /dev/null +++ b/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1.yaml @@ -0,0 +1,14 @@ +identifier: mikroe_clicker_ra4m1 +name: Mikroe Clicker RA4M1 +vendor: mikroe +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 32 +flash: 256 +supported: + - gpio + - uart diff --git a/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1_defconfig b/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1_defconfig new file mode 100644 index 00000000000..3d89bdc283d --- /dev/null +++ b/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1_defconfig @@ -0,0 +1,22 @@ +# Copyright (c) 2024 Ian Morris +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=12000000 + +CONFIG_BUILD_OUTPUT_HEX=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# enable GPIO +CONFIG_GPIO=y + +# enable pin controller +CONFIG_PINCTRL=y + +# enable Clocks +CONFIG_CLOCK_CONTROL=y diff --git a/boards/mikroe/mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst b/boards/mikroe/mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst index 7198f2da36e..6194953b1da 100644 --- a/boards/mikroe/mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst +++ b/boards/mikroe/mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst @@ -118,7 +118,7 @@ Unlocking with openocd makes it possible to flash. -f /usr/share/openocd/scripts/target/stm32f4x.cfg -c init\ -c "reset halt" -c "stm32f4x unlock 0" -c "reset run" -c shutdown -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -135,7 +135,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/mikroe/mini_m4_for_stm32/mikroe_mini_m4_for_stm32_defconfig b/boards/mikroe/mini_m4_for_stm32/mikroe_mini_m4_for_stm32_defconfig index 201c26b992a..193d4211ebd 100644 --- a/boards/mikroe/mini_m4_for_stm32/mikroe_mini_m4_for_stm32_defconfig +++ b/boards/mikroe/mini_m4_for_stm32/mikroe_mini_m4_for_stm32_defconfig @@ -12,9 +12,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/mikroe/mini_m4_for_stm32/support/openocd.cfg b/boards/mikroe/mini_m4_for_stm32/support/openocd.cfg index b97b1a0527a..4d5e4008c40 100644 --- a/boards/mikroe/mini_m4_for_stm32/support/openocd.cfg +++ b/boards/mikroe/mini_m4_for_stm32/support/openocd.cfg @@ -6,8 +6,8 @@ transport select hla_swd source [find target/stm32f4x.cfg] -adapter_khz 1000 -adapter_nsrst_delay 100 +adapter speed 1000 +adapter srst delay 100 jtag_ntrst_delay 100 reset_config srst_only srst_nogate connect_assert_srst diff --git a/boards/mikroe/stm32_m4_clicker/Kconfig.defconfig b/boards/mikroe/stm32_m4_clicker/Kconfig.defconfig new file mode 100644 index 00000000000..082d099f4b8 --- /dev/null +++ b/boards/mikroe/stm32_m4_clicker/Kconfig.defconfig @@ -0,0 +1,24 @@ +# Copyright (c) 2024 Ian Morris +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MIKROE_STM32_M4_CLICKER + +if USB_DEVICE_STACK + +config UART_CONSOLE + default CONSOLE + +config USB_DEVICE_INITIALIZE_AT_BOOT + default y + +endif # USB_DEVICE_STACK + +if LOG + +# Logger cannot use itself to log +config USB_CDC_ACM_LOG_LEVEL + default 0 + +endif # LOG + +endif # BOARD_MIKROE_STM32_M4_CLICKER diff --git a/boards/mikroe/stm32_m4_clicker/Kconfig.mikroe_stm32_m4_clicker b/boards/mikroe/stm32_m4_clicker/Kconfig.mikroe_stm32_m4_clicker new file mode 100644 index 00000000000..052fb38bc70 --- /dev/null +++ b/boards/mikroe/stm32_m4_clicker/Kconfig.mikroe_stm32_m4_clicker @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Ian Morris +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIKROE_STM32_M4_CLICKER + select SOC_STM32F415XX diff --git a/boards/mikroe/stm32_m4_clicker/board.cmake b/boards/mikroe/stm32_m4_clicker/board.cmake new file mode 100644 index 00000000000..5b2d6e7bd62 --- /dev/null +++ b/boards/mikroe/stm32_m4_clicker/board.cmake @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Ian Morris +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(pyocd "--target=stm32f415rg") +board_runner_args(jlink "--device=STM32F415RG" "--speed=4000") + +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/mikroe/stm32_m4_clicker/board.yml b/boards/mikroe/stm32_m4_clicker/board.yml new file mode 100644 index 00000000000..56a329a900f --- /dev/null +++ b/boards/mikroe/stm32_m4_clicker/board.yml @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Ian Morris +# SPDX-License-Identifier: Apache-2.0 + +board: + name: mikroe_stm32_m4_clicker + vendor: mikroe + socs: + - name: stm32f415xx diff --git a/boards/mikroe/stm32_m4_clicker/doc/img/stm32_m4_clicker.webp b/boards/mikroe/stm32_m4_clicker/doc/img/stm32_m4_clicker.webp new file mode 100644 index 00000000000..bc4797072f0 Binary files /dev/null and b/boards/mikroe/stm32_m4_clicker/doc/img/stm32_m4_clicker.webp differ diff --git a/boards/mikroe/stm32_m4_clicker/doc/index.rst b/boards/mikroe/stm32_m4_clicker/doc/index.rst new file mode 100644 index 00000000000..c1f9f809ac7 --- /dev/null +++ b/boards/mikroe/stm32_m4_clicker/doc/index.rst @@ -0,0 +1,94 @@ +.. _mikroe_stm32_m4_clicker: + +Mikroe STM32 M4 Clicker +####################### + +Overview +******** + +The Mikroe STM32 M4 Clicker development board contains a STMicroelectronics +Cortex-M4 based STM32F415RG Microcontroller operating at up to 168 MHz with +1 MB of Flash memory and 192 KB of SRAM. + +.. figure:: img/stm32_m4_clicker.webp + :align: center + :alt: STM32 M4 Clicker + + STM32 M4 Clicker (Credit: MikroElektronika d.o.o.) + +Hardware +******** + +The STM32 M4 Clicker board contains a USB connector, two LEDs, two push +buttons, and a reset button. It features a mikroBUS socket for interfacing +with external electronics. For more information about the development +board see the `STM32 M4 Clicker website`_. + +Supported Features +================== + +The ``mikroe_stm32_m4_clicker`` board target supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | GPIO output | +| | | GPIO input | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB | ++-----------+------------+-------------------------------------+ + +Other hardware features have not yet been enabled for this board. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/mikroe/stm32_m4_clicker/mikroe_stm32_m4_clicker_defconfig`. + +Programming and debugging +************************* + +Building & Flashing +=================== + +You can build and flash an application in the usual way (See +:ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for building and flashing the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: mikroe_stm32_m4_clicker + :goals: build flash + +Debugging +========= + +Debugging also can be done in the usual way. +The following command is debugging the :zephyr:code-sample:`blinky` application. +Also, see the instructions specific to the debug server that you use. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: mikroe_stm32_m4_clicker + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _STM32 M4 Clicker website: + https://www.mikroe.com/clicker-stm32f4 diff --git a/boards/mikroe/stm32_m4_clicker/mikroe_stm32_m4_clicker.dts b/boards/mikroe/stm32_m4_clicker/mikroe_stm32_m4_clicker.dts new file mode 100644 index 00000000000..1fa6b5f0762 --- /dev/null +++ b/boards/mikroe/stm32_m4_clicker/mikroe_stm32_m4_clicker.dts @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2024 Ian Morris + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include + +/ { + model = "Mikroe STM32 M4 Clicker"; + compatible = "st,stm32f415rg"; + + chosen { + zephyr,console = &usb_cdc_acm_uart; + zephyr,shell-uart = &usb_cdc_acm_uart; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + leds { + compatible = "gpio-leds"; + ld1: led_1 { + gpios = <&gpioa 1 GPIO_ACTIVE_HIGH>; + label = "User LED 1"; + }; + ld2: led_2 { + gpios = <&gpioa 2 GPIO_ACTIVE_HIGH>; + label = "User LED 2"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + btn1: button_1 { + label = "User Button 1"; + gpios = <&gpioc 0 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + btn2: button_2 { + label = "User Button 2"; + gpios = <&gpioc 1 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; + + mikrobus_header: mikrobus-connector { + compatible = "mikro-bus"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpioa 0 0>, /* AN */ + <1 0 &gpiob 5 0>, /* RST */ + <2 0 &gpiob 12 0>, /* CS */ + <3 0 &gpiob 13 0>, /* SCK */ + <4 0 &gpiob 14 0>, /* MISO */ + <5 0 &gpiob 15 0>, /* MOSI */ + /* +3.3V */ + /* GND */ + <6 0 &gpiob 0 0>, /* PWM */ + <7 0 &gpiob 1 0>, /* INT */ + <8 0 &gpioc 11 0>, /* RX */ + <9 0 &gpioc 12 0>, /* TX */ + <10 0 &gpiob 10 0>, /* SCL */ + <11 0 &gpiob 11 0>; /* SDA */ + /* +5V */ + /* GND */ + }; + + aliases { + led0 = &ld1; + led1 = &ld2; + sw0 = &btn1; + }; +}; + +&clk_lsi { + status = "okay"; +}; + +&clk_hse { + clock-frequency = ; + status = "okay"; +}; + +&pll { + div-m = <16>; + mul-n = <336>; + div-p = <2>; + div-q = <7>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <4>; + apb2-prescaler = <2>; +}; + +&usart3 { + pinctrl-0 = <&usart3_tx_pc10 &usart3_rx_pc11>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_scl_pb10 &i2c2_sda_pb11>; + pinctrl-names = "default"; + status = "okay"; +}; + +&spi2 { + pinctrl-0 = <&spi2_nss_pb12 &spi2_sck_pb13 + &spi2_miso_pb14 &spi2_mosi_pb15>; + pinctrl-names = "default"; + status = "okay"; +}; + +zephyr_udc0: &usbotg_fs { + pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; + pinctrl-names = "default"; + status = "okay"; + + usb_cdc_acm_uart: cdc_acm_uart { + compatible = "zephyr,cdc-acm-uart"; + }; +}; + +mikrobus_spi: &spi2 {}; +mikrobus_serial: &usart3 {}; +mikrobus_i2c: &i2c2 {}; diff --git a/boards/mikroe/stm32_m4_clicker/mikroe_stm32_m4_clicker.yaml b/boards/mikroe/stm32_m4_clicker/mikroe_stm32_m4_clicker.yaml new file mode 100644 index 00000000000..96d16aa2d63 --- /dev/null +++ b/boards/mikroe/stm32_m4_clicker/mikroe_stm32_m4_clicker.yaml @@ -0,0 +1,17 @@ +identifier: mikroe_stm32_m4_clicker +name: Mikroe STM32 M4 Clicker +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 128 +flash: 1024 +supported: + - uart + - gpio + - i2c + - spi + - usb_device +vendor: mikroe diff --git a/boards/mikroe/stm32_m4_clicker/mikroe_stm32_m4_clicker_defconfig b/boards/mikroe/stm32_m4_clicker/mikroe_stm32_m4_clicker_defconfig new file mode 100644 index 00000000000..f964f048f77 --- /dev/null +++ b/boards/mikroe/stm32_m4_clicker/mikroe_stm32_m4_clicker_defconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2024 Ian Morris +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Console +CONFIG_SERIAL=y +CONFIG_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# Enable USB +CONFIG_USB_DEVICE_STACK=y diff --git a/boards/mxchip/az3166_iotdevkit/az3166_iotdevkit_defconfig b/boards/mxchip/az3166_iotdevkit/az3166_iotdevkit_defconfig index ee16a27c1e1..61e3b2504b2 100644 --- a/boards/mxchip/az3166_iotdevkit/az3166_iotdevkit_defconfig +++ b/boards/mxchip/az3166_iotdevkit/az3166_iotdevkit_defconfig @@ -14,9 +14,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO ports CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/mxchip/az3166_iotdevkit/doc/index.rst b/boards/mxchip/az3166_iotdevkit/doc/index.rst index 2e44339bec2..694d53517a6 100644 --- a/boards/mxchip/az3166_iotdevkit/doc/index.rst +++ b/boards/mxchip/az3166_iotdevkit/doc/index.rst @@ -76,7 +76,7 @@ Flashing Build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/native/doc/Port_vs_QEMU_vs.svg b/boards/native/doc/Port_vs_QEMU_vs.svg index 923b0df3f99..20f8abbc67c 100644 --- a/boards/native/doc/Port_vs_QEMU_vs.svg +++ b/boards/native/doc/Port_vs_QEMU_vs.svg @@ -365,19 +365,19 @@ QEMU Sheet.88 - native_ posix + native _sim - native_posix + native_sim Sheet.89 - native_posix + native_sim - native_posix + native_sim Sheet.90 diff --git a/boards/native/doc/arch_soc.rst b/boards/native/doc/arch_soc.rst index 09edd476349..d07a9c589a2 100644 --- a/boards/native/doc/arch_soc.rst +++ b/boards/native/doc/arch_soc.rst @@ -33,9 +33,9 @@ target hardware in the early phases of development. Types of POSIX arch based boards ================================ -Today there are two types of POSIX boards: The native boards, :ref:`native_posix` -and :ref:`native_sim`, and the :ref:`bsim boards`. -While they share the main objectives and principles, the first are intended as +Today there are two types of POSIX boards: +:ref:`native_sim`, and the :ref:`bsim boards`. +While they share the main objectives and principles, the first is intended as a HW agnostic test platform which in some cases utilizes the host OS peripherals, while the second intend to simulate a particular HW platform, with focus on their radio (e.g. BT LE) and utilize the `BabbleSim`_ physical layer @@ -183,7 +183,7 @@ Currently, these are the most significant features which are not supported in th * Stack checks: :kconfig:option:`CONFIG_HW_STACK_PROTECTION`, :kconfig:option:`CONFIG_STACK_CANARIES`, and :kconfig:option:`CONFIG_THREAD_ANALYZER`. - This is due to how Zephyr allocated threads' stacks are not `actually` being used like they are + This is due to how Zephyr allocated threads' stacks are not *actually* being used like they are in other architectures. Check :ref:`the architecture section's architecture layer paragraph ` for more information. @@ -355,7 +355,7 @@ while this newly created thread will be the first "SW" thread and start executing the boot of the embedded code (including the POSIX arch code). During this MCU boot process, the Zephyr kernel will be initialized and -eventually this will call into the embedded application `main()`, +eventually this will call into the embedded application ``main()``, just like in the embedded target. As the embedded SW execution progresses, more Zephyr threads may be spawned, and for each the POSIX architecture will create a dedicated pthread. @@ -413,7 +413,7 @@ Busy waits Busy waits work thanks to provided board functionality. This does not need to be the same for all boards, but both native_sim and the nrf52_bsim board work similarly thru the combination of a board specific -`arch_busy_wait()` and a special fake HW timer (provided by the board). +:c:func:`arch_busy_wait()` and a special fake HW timer (provided by the board). When a SW thread wants to busy wait, this fake timer will be programmed in the future time corresponding to the end of the busy wait and the CPU will @@ -422,7 +422,7 @@ When this fake HW timer expires the CPU will be waken with a special non-maskable phony interrupt which does not have a corresponding interrupt handler but will resume the busy_wait SW execution. Note that other interrupts may arrive while the busy wait is in progress, -which may delay the `k_busy_wait()` return just like in real life. +which may delay the :c:func:`k_busy_wait()` return just like in real life. Interrupts may be locked out or masked during this time, but the special fake-timer non-maskable interrupt will wake the CPU nonetheless. diff --git a/boards/native/doc/bsim_boards_design.rst b/boards/native/doc/bsim_boards_design.rst index 7fef9d1b522..b128baba7a2 100644 --- a/boards/native/doc/bsim_boards_design.rst +++ b/boards/native/doc/bsim_boards_design.rst @@ -16,7 +16,7 @@ Bsim boards This page covers the design, architecture and rationale, of the nrf5x_bsim boards and other similar bsim boards. -These boards are postfixed with `_bsim` as they use BabbleSim_ +These boards are postfixed with ``_bsim`` as they use BabbleSim_ (shortened bsim), to simulate the radio environment. These boards use the `native simulator`_ and the :ref:`POSIX architecture` to build and execute the embedded code natively on Linux. @@ -85,7 +85,7 @@ to these boards. - Integration tests on real HW: Allows testing with the real SW components that may be too dependent on the exact HW particularities, and possibly without any changes compared to the final solution. - As such can provide better integration coverage than simulation ins ome cases, + As such can provide better integration coverage than simulation in some cases, but at the expense of slower execution, needing the real HW setups, test in general not being reproducible, and in many cases failures not being easy to debug. @@ -125,6 +125,29 @@ to these boards. Design ****** +Relationship between Zephyr, the native simulator, the nRF HW models and BabbleSim +================================================================================== + +As shown in the figure below, when you build your embedded application targeting one of Zephyr's +nrf_bsim targets, you are using the `native simulator`_, which is being built together with and +expanded by the nRF HW models for that target. +Your application is first built and linked with the Zephyr kernel and any subsystems and network +stacks you may have selected, including mostly the same drivers as for the real target. +The native simulator runner is built together with the HW models which match your desired target. +And then both the embedded SW and runner are linked together to produce a Linux executable. + +.. figure:: components_bsim.svg + :align: center + :alt: nrf_bsim boards and the native simulator + :figclass: align-center + + Relationship between Zephyr, the native simulator, the nRF HW models and BabbleSim. + +When you target a multi MCU SOC like the :ref:`nrf5340bsim`, you can +use :ref:`sysbuild` to build an executable, where, for each MCU, its application, Zephyr +kernel and subsystems are built and linked first, and finally assembled all together with the native +simulator runner into a single executable. + Layering: Zephyr's arch, soc and board layers ============================================= @@ -135,13 +158,13 @@ The basic architecture layering of these boards is as follows: simulation specific ones. - The architecture (arch) is the Zephyr :ref:`POSIX architecture` layer. - The SOC layer is `inf_clock`. And the board layer is dependent on + The SOC layer is ``inf_clock``. And the board layer is dependent on the specific device we are simulating. - The POSIX architecture provides an adaptation from the Zephyr arch API (which handles mostly the thread context switching) to the native simulator CPU thread emulation. See :ref:`POSIX arch architecture` -- The SOC `inf_clock` layer provides an adaptation to the native simulator CPU "simulation" +- The SOC ``inf_clock`` layer provides an adaptation to the native simulator CPU "simulation" and the handling of control between the "CPU simulation" (Zephyr threads) and the HW models thread ( See `Threading`_ ). - The board layer provides all SOC/ IC specific content, including @@ -149,13 +172,13 @@ The basic architecture layering of these boards is as follows: busy wait API (see :ref:`posix_busy_wait`), and Zephyr's printk backend. Note that in a normal Zephyr target interrupt handling and a custom busy wait would be provided by the SOC layer, but abusing Zephyr's layering, and for the - `inf_clock` layer to be generic, these were delegated to the board. + ``inf_clock`` layer to be generic, these were delegated to the board. The board layer provides other test specific functionality like bs_tests hooks, trace control, etc, and by means of the native simulator, provides the :c:func:`main` entry point for the Linux program, command line argument handling, and the overall time scheduling of the simulated device. - Note that the POSIX arch and `inf_clock` soc expect a set of APIs being provided by + Note that the POSIX arch and ``inf_clock`` soc expect a set of APIs being provided by the board. This includes the busy wait API, a basic tracing API, the interrupt controller and interrupt handling APIs, :c:func:`posix_exit`, and :c:func:`posix_get_hw_cycle` (see :file:`posix_board_if.h` and :file:`posix_soc_if.h`). @@ -173,7 +196,7 @@ Important limitations and unsupported features All native and bsim boards share the same set of :ref:`important limitations which` -are inherited from the POSIX arch and `inf_clock` design. +are inherited from the POSIX arch and ``inf_clock`` design. Similarly, they inherit the POSIX architecture :ref:`unsupported features set `. @@ -261,7 +284,7 @@ posix_print and nsi_print backends ================================== The bsim board provides a backend for the ``posix_print`` API which is expected by the posix -ARCH and `inf_clock` code, and for the ``nsi_print`` API expected by the native simulator. +ARCH and ``inf_clock`` code, and for the ``nsi_print`` API expected by the native simulator. These simply route this API calls into the ``bs_trace`` bsim API. Any message printed to these APIs, and by extension by default to Zephyr's ``printk``, @@ -287,12 +310,12 @@ callbacks are assigned to the respective hooks. There is a set of one time hooks at different levels of initialization of the HW and Zephyr OS, a hook to process possible command line arguments, and, a hook that can be used to sniff or capture interrupts. -`bs_tests` also provides a hook which will be called from the embedded application +``bs_tests`` also provides a hook which will be called from the embedded application :c:func:`main`, but this will only work if the main application supports it, that is, if the main app is a version for simulation which calls :c:func:`bst_main` when running in the bsim board. -Apart from these hooks, the `bs_tests` system provides facilities to build a +Apart from these hooks, the ``bs_tests`` system provides facilities to build a dedicated test "task". This will be executed in the HW models thread context, but will have access to all SW variables. This task will be driven with a special timer which can be configured to produce either periodic or one time @@ -302,15 +325,15 @@ at specific points in time. This can be combined with Babblesim's tb_defs macros to build quite complex test tasks which can wait for a given amount of time, for conditions to be fulfilled, etc. -Note when writing the tests with `bs_tests` one needs to be aware that other +Note when writing the tests with ``bs_tests`` one needs to be aware that other bs tests will probably be built with the same application, and that therefore the tests should not be registering initialization or callback functions using NATIVE_TASKS or Zephyr's PRE/POST kernel driver initialization APIs as this will execute even if the test is not selected. -Instead the equivalent `bs_tests` provided hooks should be used. +Instead the equivalent ``bs_tests`` provided hooks should be used. Note also that, for AMP targets like the :ref:`nrf5340bsim `, each embedded MCU has -its own separate `bs_tests` built with that MCU. You can select if and what test is used +its own separate ``bs_tests`` built with that MCU. You can select if and what test is used for each MCU separatedly with the command line options. Command line argument parsing diff --git a/boards/native/doc/components_bsim.svg b/boards/native/doc/components_bsim.svg new file mode 100644 index 00000000000..0dd68f72fa1 --- /dev/null +++ b/boards/native/doc/components_bsim.svg @@ -0,0 +1,4 @@ + + + +
Zephyr's nrf*bsim targets
Zephyr's nrf*bsim ta...
native simulator
native simulator
nRF HW models
nRF HW models
Uses
Uses
Extends the native simulator

Extends the nat...
Embedded SW:
Application + Zephyr kernel + stack + drivers
Embedded SW:...
Built for
Built for
Babblesim Physical layer simulation
Babblesim Physical l...
Connects to
Connects to \ No newline at end of file diff --git a/boards/native/doc/layering.svg b/boards/native/doc/layering.svg index c85357d0132..54677195e31 100644 --- a/boards/native/doc/layering.svg +++ b/boards/native/doc/layering.svg @@ -129,11 +129,11 @@ x="42.81" dy="1.2em" class="st4">layering Sheet.14 - native_posix/sim & _bsim boards Zephyr layering + native_sim & _bsim boards Zephyr layering - native_posix/sim native_sim & _bsim boards Zephyr layering diff --git a/boards/native/native_posix/Kconfig.defconfig b/boards/native/native_posix/Kconfig.defconfig index 95c89071513..2d896061f78 100644 --- a/boards/native/native_posix/Kconfig.defconfig +++ b/boards/native/native_posix/Kconfig.defconfig @@ -3,6 +3,9 @@ if BOARD_NATIVE_POSIX +config BOARD_DEPRECATED_RELEASE + default "v4.2.0" + config BUILD_OUTPUT_BIN default n @@ -32,11 +35,4 @@ config UART_CONSOLE endif # CONSOLE -if I2C - -config EMUL - default y - -endif # I2C - endif # BOARD_NATIVE_POSIX diff --git a/boards/native/native_posix/doc/index.rst b/boards/native/native_posix/doc/index.rst index 950f68193ad..ea53463a7ff 100644 --- a/boards/native/native_posix/doc/index.rst +++ b/boards/native/native_posix/doc/index.rst @@ -11,6 +11,15 @@ Native POSIX execution (native_posix) Overview ******** +.. warning:: + ``native_posix`` is deprecated in favour of :ref:`native_sim`, and will be removed + in the 4.2 release. + +.. note:: + For native_posix users, if needed, :ref:`native_sim` includes a compatibility mode + :kconfig:option:`CONFIG_NATIVE_SIM_NATIVE_POSIX_COMPAT`, + which will set its configuration to mimic a native_posix-like configuration. + ``native_posix`` is the predecessor of :ref:`native_sim`. Just like with :ref:`native_sim` you can build your Zephyr application with the Zephyr kernel, creating a normal Linux executable with your host tooling, @@ -19,15 +28,6 @@ and can debug and instrument it like any other Linux program. But unlike with :ref:`native_sim` you are limited to only using the host C library. :ref:`native_sim` supports all ``native_posix`` use cases. -.. note:: - - | If you are a new user, you are encouraged to use :ref:`native_sim` directly. - | If you have been using native_posix you are recommended to start using - :ref:`native_sim` instead. - | If needed, :ref:`native_sim` includes a compatibility mode - :kconfig:option:`CONFIG_NATIVE_SIM_NATIVE_POSIX_COMPAT`, - which will set its configuration to mimic a native_posix's like configuration. - This board does not intend to simulate any particular HW, but it provides a few peripherals such as an Ethernet driver, display, UART, etc., to enable developing and testing application code which would require them. diff --git a/boards/native/native_posix/native_rtc.h b/boards/native/native_posix/native_rtc.h index 09fc1663882..c17395448af 100644 --- a/boards/native/native_posix/native_rtc.h +++ b/boards/native/native_posix/native_rtc.h @@ -44,7 +44,7 @@ extern "C" { uint64_t native_rtc_gettime_us(int clock_type); /** - * @brief Get the value of a clock split in in nsec and seconds + * @brief Get the value of a clock split in nsec and seconds * * @param clock_type Which clock to measure from * @param nsec Pointer to store the nanoseconds diff --git a/boards/native/native_sim/Kconfig.defconfig b/boards/native/native_sim/Kconfig.defconfig index aa2440c872d..0cb80bbcf45 100644 --- a/boards/native/native_sim/Kconfig.defconfig +++ b/boards/native/native_sim/Kconfig.defconfig @@ -32,11 +32,5 @@ config UART_CONSOLE endif # CONSOLE -if I2C - -config EMUL - default y - -endif # I2C endif # BOARD_NATIVE_SIM diff --git a/boards/native/native_sim/doc/index.rst b/boards/native/native_sim/doc/index.rst index 0a304ca941c..3f6033884b3 100644 --- a/boards/native/native_sim/doc/index.rst +++ b/boards/native/native_sim/doc/index.rst @@ -376,8 +376,7 @@ The following peripherals are currently provided with this board: Note that this device can only be used with Linux hosts. -.. _net-tools: - https://github.com/zephyrproject-rtos/net-tools +.. _`net-tools`: https://github.com/zephyrproject-rtos/net-tools .. _nsim_per_offloaded_sockets: @@ -500,10 +499,14 @@ The following peripherals are currently provided with this board: :ref:`its section `. **CAN controller** - It is possible to use a host CAN controller with the native SockerCAN Linux driver. It can be + It is possible to use a host CAN controller with the native SocketCAN Linux driver. It can be enabled with :kconfig:option:`CONFIG_CAN_NATIVE_LINUX` and configured with the device tree binding :dtcompatible:`zephyr,native-linux-can`. + It is possible to specify which CAN interface will be used by the app using the ``--can-if`` + command-line option. This option overrides **every** Linux SocketCAN driver instance to use the specified + interface. + .. _native_ptty_uart: PTTY UART diff --git a/boards/native/native_sim/native_sim.dts b/boards/native/native_sim/native_sim.dts index 95b5ee5c065..1f1b11ad9e7 100644 --- a/boards/native/native_sim/native_sim.dts +++ b/boards/native/native_sim/native_sim.dts @@ -114,6 +114,7 @@ clock-frequency = ; #address-cells = <1>; #size-cells = <0>; + #forward-cells = <1>; reg = <0x100 4>; }; @@ -134,6 +135,15 @@ #size-cells = <0>; }; + mspi0: mspi@400 { + status = "okay"; + compatible = "zephyr,mspi-emul-controller"; + clock-frequency = <250000000>; + reg = <0x400 4>; + #address-cells = <1>; + #size-cells = <0>; + }; + uart0: uart { status = "okay"; compatible = "zephyr,native-posix-uart"; diff --git a/boards/native/native_sim/native_sim.yaml b/boards/native/native_sim/native_sim.yaml index bed88ab7f3a..0a563c86881 100644 --- a/boards/native/native_sim/native_sim.yaml +++ b/boards/native/native_sim/native_sim.yaml @@ -14,6 +14,7 @@ supported: - dma - eeprom - netif:eth + - mspi - usb_device - adc - i2c diff --git a/boards/native/nrf_bsim/Kconfig b/boards/native/nrf_bsim/Kconfig index 0273667c415..a8865941d74 100644 --- a/boards/native/nrf_bsim/Kconfig +++ b/boards/native/nrf_bsim/Kconfig @@ -94,15 +94,6 @@ config SOC_SERIES_BSIM_NRF54LX help Any NRF54L simulated SOC with BabbleSim, based on the POSIX arch -if BOARD_NRF5340BSIM_NRF5340_CPUAPP - -# Replica of the option provided by the BOARD_NRF5340DK_NRF5340_CPUAPP board so samples can be -# reused as is -config BOARD_ENABLE_CPUNET - bool "NRF53 Network MCU" - -endif # BOARD_NRF5340BSIM_NRF5340_CPUNET - if SOC_SERIES_BSIM_NRF53X # Let's reuse the RTC sync options so applications which use it can be reused as is diff --git a/boards/native/nrf_bsim/Kconfig.defconfig b/boards/native/nrf_bsim/Kconfig.defconfig index 2ff17802977..629372e5e1d 100644 --- a/boards/native/nrf_bsim/Kconfig.defconfig +++ b/boards/native/nrf_bsim/Kconfig.defconfig @@ -48,13 +48,6 @@ config HEAP_MEM_POOL_ADD_SIZE_BOARD default 4096 if NRF_802154_SER_HOST && BOARD_NRF5340BSIM_NRF5340_CPUAPP default 4096 if NRF_802154_SER_RADIO && BOARD_NRF5340BSIM_NRF5340_CPUNET -if BOARD_NRF5340BSIM_NRF5340_CPUAPP || BOARD_NRF5340BSIM_NRF5340_CPUNET - -config MBOX_NRFX_IPC - default MBOX - -endif # BOARD_NRF5340BSIM_NRF5340_CPUAPP || BOARD_NRF5340BSIM_NRF5340_CPUNET - if BOARD_NRF5340BSIM_NRF5340_CPUAPP config IPC_SERVICE_BACKEND_RPMSG_SHMEM_RESET diff --git a/boards/native/nrf_bsim/common/cmdline.h b/boards/native/nrf_bsim/common/cmdline.h index ec658006953..004d6202b53 100644 --- a/boards/native/nrf_bsim/common/cmdline.h +++ b/boards/native/nrf_bsim/common/cmdline.h @@ -5,20 +5,20 @@ */ /** - * This header exists solely to allow drivers meant for the native_posix board - * to be used directly in the nrf52_bsim board. + * This header exists solely to allow drivers meant for the native_sim board + * to be used directly in the nrf5*_bsim boards. * Note that such reuse should be done with great care. * - * The command line arguments parsing logic from native_posix was born as a copy + * The command line arguments parsing logic from native_sim was born as a copy * of the one from the BabbleSim's libUtil library * They are therefore mostly equal except for types and functions names. * - * This header converts these so the native_posix call to dynamically register - * command line arguments is passed to the nrf52_bsim one + * This header converts these so the native_sim call to dynamically register + * command line arguments is passed to the nrf*_bsim one */ -#ifndef BOARDS_POSIX_NRF52_BSIM_CMDLINE_H -#define BOARDS_POSIX_NRF52_BSIM_CMDLINE_H +#ifndef BOARDS_POSIX_NRF_BSIM_CMDLINE_H +#define BOARDS_POSIX_NRF_BSIM_CMDLINE_H #include "../../native_posix/cmdline_common.h" @@ -36,4 +36,4 @@ static inline void native_add_command_line_opts(struct args_struct_t *args) } #endif -#endif /* BOARDS_POSIX_NRF52_BSIM_CMDLINE_H */ +#endif /* BOARDS_POSIX_NRF_BSIM_CMDLINE_H */ diff --git a/boards/native/nrf_bsim/doc/nrf5340bsim.rst b/boards/native/nrf_bsim/doc/nrf5340bsim.rst index 2d6190e7c46..271e0db1bc1 100644 --- a/boards/native/nrf_bsim/doc/nrf5340bsim.rst +++ b/boards/native/nrf_bsim/doc/nrf5340bsim.rst @@ -79,6 +79,7 @@ Simply change the board/target appropriately when building. If an MCU is booted without any image, it will automatically set itself to sleep. +.. _nrf5340bsim_multi_mcu_build: Assembling both MCUs images into a single executable **************************************************** diff --git a/boards/native/nrf_bsim/ipc_backend.c b/boards/native/nrf_bsim/ipc_backend.c index 4f14924a44a..34b265a24ca 100644 --- a/boards/native/nrf_bsim/ipc_backend.c +++ b/boards/native/nrf_bsim/ipc_backend.c @@ -21,7 +21,7 @@ #define DT_DRV_COMPAT zephyr_ipc_openamp_static_vrings #define DEFINE_BACKEND_BUFFER(i) \ - NATIVE_SIMULATOR_IF \ + NATIVE_SIMULATOR_IF_DATA \ char IPC##i##_shm_buffer[DT_REG_SIZE(DT_INST_PHANDLE(i, memory_region))]; DT_INST_FOREACH_STATUS_OKAY(DEFINE_BACKEND_BUFFER) diff --git a/boards/native/nrf_bsim/nrf52_bsim.dts b/boards/native/nrf_bsim/nrf52_bsim.dts index bb6321c4d53..ad3ac181ae7 100644 --- a/boards/native/nrf_bsim/nrf52_bsim.dts +++ b/boards/native/nrf_bsim/nrf52_bsim.dts @@ -38,8 +38,6 @@ zephyr,flash = &flash0; /* UART used by the BT controller UART HCI driver by default: */ zephyr,bt-c2h-uart = &uart1; - /* UART used by the BT host UART HCI driver by default: */ - zephyr,bt-uart = &uart1; }; soc { @@ -117,4 +115,9 @@ pinctrl-1 = <&uart1_sleep>; pinctrl-names = "default", "sleep"; hw-flow-control; + + bt_hci_uart: bt_hci_uart { + compatible = "zephyr,bt-hci-uart"; + status = "okay"; + }; }; diff --git a/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.dts b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.dts index 11073e6182d..256b9bfb875 100644 --- a/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.dts +++ b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.dts @@ -115,4 +115,4 @@ /* We re-use the IPC shared buffer definition from the real HW. But note the start address of the * buffer won't be used. */ -#include <../boards/nordic/nrf5340dk/nrf5340_shared_sram_planning_conf.dtsi> + #include diff --git a/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts index 020003a7b99..d7d6a2fe75d 100644 --- a/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts +++ b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts @@ -76,4 +76,4 @@ /* We re-use the IPC shared buffer definition from the real HW. But note the start address of the * buffer won't be used. */ -#include <../boards/nordic/nrf5340dk/nrf5340_shared_sram_planning_conf.dtsi> + #include diff --git a/boards/nordic/nrf21540dk/Kconfig b/boards/nordic/nrf21540dk/Kconfig deleted file mode 100644 index 522eb6e44dd..00000000000 --- a/boards/nordic/nrf21540dk/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# nRF21540 DK NRF52840 board configuration - -# Copyright (c) 2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_NRF21540DK diff --git a/boards/nordic/nrf21540dk/doc/index.rst b/boards/nordic/nrf21540dk/doc/index.rst index 8ea583edb1a..7ed102b2b61 100644 --- a/boards/nordic/nrf21540dk/doc/index.rst +++ b/boards/nordic/nrf21540dk/doc/index.rst @@ -135,7 +135,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/nordic/nrf21540dk/nrf21540dk_nrf52840.dts b/boards/nordic/nrf21540dk/nrf21540dk_nrf52840.dts index af0ea59794c..51302293ba4 100644 --- a/boards/nordic/nrf21540dk/nrf21540dk_nrf52840.dts +++ b/boards/nordic/nrf21540dk/nrf21540dk_nrf52840.dts @@ -146,6 +146,10 @@ }; }; +®1 { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; diff --git a/boards/nordic/nrf21540dk/nrf21540dk_nrf52840.yaml b/boards/nordic/nrf21540dk/nrf21540dk_nrf52840.yaml index a1bcc36e034..b84c5371d87 100644 --- a/boards/nordic/nrf21540dk/nrf21540dk_nrf52840.yaml +++ b/boards/nordic/nrf21540dk/nrf21540dk_nrf52840.yaml @@ -18,7 +18,6 @@ supported: - i2c - pwm - spi - - usb_cdc - usb_device - watchdog - netif:openthread diff --git a/boards/nordic/nrf51dk/doc/index.rst b/boards/nordic/nrf51dk/doc/index.rst index c905dc0f476..f5a2acbbcde 100644 --- a/boards/nordic/nrf51dk/doc/index.rst +++ b/boards/nordic/nrf51dk/doc/index.rst @@ -110,7 +110,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/nordic/nrf51dongle/doc/index.rst b/boards/nordic/nrf51dongle/doc/index.rst index d8183371654..63f288e23fc 100644 --- a/boards/nordic/nrf51dongle/doc/index.rst +++ b/boards/nordic/nrf51dongle/doc/index.rst @@ -105,7 +105,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/nordic/nrf52833dk/Kconfig b/boards/nordic/nrf52833dk/Kconfig deleted file mode 100644 index 8b53d5bd73f..00000000000 --- a/boards/nordic/nrf52833dk/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# nRF52833 DK NRF52833 board configuration - -# Copyright (c) 2019 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_NRF52833DK diff --git a/boards/nordic/nrf52833dk/doc/index.rst b/boards/nordic/nrf52833dk/doc/index.rst index 027f471586f..ed057bbc93c 100644 --- a/boards/nordic/nrf52833dk/doc/index.rst +++ b/boards/nordic/nrf52833dk/doc/index.rst @@ -119,7 +119,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/nordic/nrf52833dk/nrf52833dk_nrf52820.dts b/boards/nordic/nrf52833dk/nrf52833dk_nrf52820.dts index 4942dd6daa0..0f9526fb21f 100644 --- a/boards/nordic/nrf52833dk/nrf52833dk_nrf52820.dts +++ b/boards/nordic/nrf52833dk/nrf52833dk_nrf52820.dts @@ -93,6 +93,10 @@ }; }; +®1 { + regulator-initial-mode = ; +}; + &sw_pwm { status ="okay"; channel-gpios = <&gpio0 13 PWM_POLARITY_INVERTED>; diff --git a/boards/nordic/nrf52833dk/nrf52833dk_nrf52833.dts b/boards/nordic/nrf52833dk/nrf52833dk_nrf52833.dts index b488b5d1ff3..dcc19542e74 100644 --- a/boards/nordic/nrf52833dk/nrf52833dk_nrf52833.dts +++ b/boards/nordic/nrf52833dk/nrf52833dk_nrf52833.dts @@ -123,6 +123,10 @@ }; }; +®1 { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; diff --git a/boards/nordic/nrf52840dk/Kconfig b/boards/nordic/nrf52840dk/Kconfig deleted file mode 100644 index 61d553e93c5..00000000000 --- a/boards/nordic/nrf52840dk/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -# nRF52840 DK NRF52840 board configuration - -# Copyright (c) 2016 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52840DK - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF52X_HV - default y - depends on SOC_NRF52840_QIAA - -endif # BOARD_NRF52840DK diff --git a/boards/nordic/nrf52840dk/doc/index.rst b/boards/nordic/nrf52840dk/doc/index.rst index faa7f07d5c9..7c948d7cffd 100644 --- a/boards/nordic/nrf52840dk/doc/index.rst +++ b/boards/nordic/nrf52840dk/doc/index.rst @@ -124,7 +124,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/nordic/nrf52840dk/nrf52840dk_nrf52811.dts b/boards/nordic/nrf52840dk/nrf52840dk_nrf52811.dts index a53a174be15..b6631dea9cf 100644 --- a/boards/nordic/nrf52840dk/nrf52840dk_nrf52811.dts +++ b/boards/nordic/nrf52840dk/nrf52840dk_nrf52811.dts @@ -93,6 +93,10 @@ }; }; +® { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; diff --git a/boards/nordic/nrf52840dk/nrf52840dk_nrf52840.dts b/boards/nordic/nrf52840dk/nrf52840dk_nrf52840.dts index 60c3ecf55a1..03a74b76002 100644 --- a/boards/nordic/nrf52840dk/nrf52840dk_nrf52840.dts +++ b/boards/nordic/nrf52840dk/nrf52840dk_nrf52840.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include "nrf52840dk_nrf52840-pinctrl.dtsi" #include @@ -19,9 +20,6 @@ zephyr,uart-mcumgr = &uart0; zephyr,bt-mon-uart = &uart0; zephyr,bt-c2h-uart = &uart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; zephyr,ieee802154 = &ieee802154; }; @@ -131,10 +129,17 @@ mcuboot-button0 = &button0; mcuboot-led0 = &led0; watchdog0 = &wdt0; - spi-flash0 = &mx25r64; }; }; +®0 { + status = "okay"; +}; + +®1 { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; @@ -267,42 +272,6 @@ arduino_spi: &spi3 { status = "okay"; }; -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000C000>; - }; - slot0_partition: partition@c000 { - label = "image-0"; - reg = <0x0000C000 0x00076000>; - }; - slot1_partition: partition@82000 { - label = "image-1"; - reg = <0x00082000 0x00076000>; - }; - - /* - * The flash starting at 0x000f8000 and ending at - * 0x000fffff is reserved for use by the application. - */ - - /* - * Storage partition will be used by FCB/LittleFS/NVS - * if enabled. - */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; - zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; diff --git a/boards/nordic/nrf52840dk/nrf52840dk_nrf52840.yaml b/boards/nordic/nrf52840dk/nrf52840dk_nrf52840.yaml index 764ac198381..313a975e6d0 100644 --- a/boards/nordic/nrf52840dk/nrf52840dk_nrf52840.yaml +++ b/boards/nordic/nrf52840dk/nrf52840dk_nrf52840.yaml @@ -21,7 +21,6 @@ supported: - i2s - pwm - spi - - usb_cdc - usb_device - usbd - watchdog diff --git a/boards/nordic/nrf52840dongle/Kconfig b/boards/nordic/nrf52840dongle/Kconfig index c4e9b309762..b1cb32d2251 100644 --- a/boards/nordic/nrf52840dongle/Kconfig +++ b/boards/nordic/nrf52840dongle/Kconfig @@ -5,16 +5,6 @@ if BOARD_NRF52840DONGLE -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF52X_HV - default y - config BOARD_HAS_NRF5_BOOTLOADER bool "Board has nRF5 bootloader" default y diff --git a/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.dts b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.dts index dcf9fb690d1..655ef346a65 100644 --- a/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.dts +++ b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.dts @@ -91,6 +91,14 @@ }; }; +®0 { + status = "okay"; +}; + +®1 { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; diff --git a/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.yaml b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.yaml index 1e61b0e71e4..e5410c74c71 100644 --- a/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.yaml +++ b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.yaml @@ -11,7 +11,6 @@ toolchain: supported: - adc - usb_device - - usb_cdc - ble - pwm - spi diff --git a/boards/nordic/nrf52dk/Kconfig b/boards/nordic/nrf52dk/Kconfig index fb039240e01..7b41e21fc49 100644 --- a/boards/nordic/nrf52dk/Kconfig +++ b/boards/nordic/nrf52dk/Kconfig @@ -5,11 +5,6 @@ if BOARD_NRF52DK -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - # BT_CTLR depends on BT. When BT is enabled we should default to also # enabling the controller. config BT_CTLR diff --git a/boards/nordic/nrf52dk/doc/index.rst b/boards/nordic/nrf52dk/doc/index.rst index 4ebcac44e6c..61349e8d31c 100644 --- a/boards/nordic/nrf52dk/doc/index.rst +++ b/boards/nordic/nrf52dk/doc/index.rst @@ -357,7 +357,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/nordic/nrf52dk/nrf52dk_nrf52805.dts b/boards/nordic/nrf52dk/nrf52dk_nrf52805.dts index e0eaa911a06..fd84761fe1b 100644 --- a/boards/nordic/nrf52dk/nrf52dk_nrf52805.dts +++ b/boards/nordic/nrf52dk/nrf52dk_nrf52805.dts @@ -85,6 +85,10 @@ }; }; +® { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; @@ -140,9 +144,9 @@ label = "image-0"; reg = <0x0000C000 0xe000>; }; - slot1_partition: partition@19000 { + slot1_partition: partition@1a000 { label = "image-1"; - reg = <0x00020000 0xe000>; + reg = <0x0001a000 0xe000>; }; storage_partition: partition@28000 { label = "storage"; diff --git a/boards/nordic/nrf52dk/nrf52dk_nrf52810.dts b/boards/nordic/nrf52dk/nrf52dk_nrf52810.dts index 4d4600f1222..2bfcad26247 100644 --- a/boards/nordic/nrf52dk/nrf52dk_nrf52810.dts +++ b/boards/nordic/nrf52dk/nrf52dk_nrf52810.dts @@ -87,6 +87,10 @@ }; }; +® { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; diff --git a/boards/nordic/nrf52dk/nrf52dk_nrf52832.dts b/boards/nordic/nrf52dk/nrf52dk_nrf52832.dts index 687bba9254a..458f5918b32 100644 --- a/boards/nordic/nrf52dk/nrf52dk_nrf52832.dts +++ b/boards/nordic/nrf52dk/nrf52dk_nrf52832.dts @@ -134,6 +134,10 @@ }; }; +® { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; diff --git a/boards/nordic/nrf5340_audio_dk/CMakeLists.txt b/boards/nordic/nrf5340_audio_dk/CMakeLists.txt index 63112d0d00b..10ddfc82783 100644 --- a/boards/nordic/nrf5340_audio_dk/CMakeLists.txt +++ b/boards/nordic/nrf5340_audio_dk/CMakeLists.txt @@ -1,14 +1,7 @@ # Copyright (c) 2021 Nordic Semiconductor ASA. # SPDX-License-Identifier: Apache-2.0 -if((CONFIG_BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP OR CONFIG_BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS) - AND CONFIG_BOARD_ENABLE_CPUNET) +if(CONFIG_BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP OR CONFIG_BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS) zephyr_library() - zephyr_library_sources(nrf5340_audio_dk_cpunet_reset.c) - - if(CONFIG_BUILD_WITH_TFM) - zephyr_library_include_directories( - $/api_ns/interface/include - ) - endif() + zephyr_library_sources(nrf5340_audio_dk_config.c) endif() diff --git a/boards/nordic/nrf5340_audio_dk/Kconfig b/boards/nordic/nrf5340_audio_dk/Kconfig index e626c40acc7..d872efa4d2e 100644 --- a/boards/nordic/nrf5340_audio_dk/Kconfig +++ b/boards/nordic/nrf5340_audio_dk/Kconfig @@ -5,41 +5,9 @@ if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP || BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS -config BOARD_ENABLE_DCDC_APP - bool "Application MCU DCDC converter" - select SOC_DCDC_NRF53X_APP - default y - -config BOARD_ENABLE_DCDC_NET - bool "Network MCU DCDC converter" - select SOC_DCDC_NRF53X_NET - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF53X_HV - default y - -config BOARD_ENABLE_CPUNET - bool "nRF53 Network MCU" - select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ - $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) - help - This option enables releasing the Network 'force off' signal, which - as a consequence will power up the Network MCU during system boot. - Additionally, the option allocates GPIO pins that will be used by UARTE - of the Network MCU. - Note: GPIO pin allocation can only be configured by the secure Application - MCU firmware, so when this option is used with the non-secure version of - the board, the application needs to take into consideration, that the - secure firmware image must already have configured GPIO allocation for the - Network MCU. - default y if (BT || NRF_802154_SER_HOST) - config DOMAIN_CPUNET_BOARD string default "nrf5340_audio_dk/nrf5340/cpunet" - depends on BOARD_ENABLE_CPUNET help The board which will be used for CPUNET domain when creating a multi image application where one or more images should be located on diff --git a/boards/nordic/nrf5340_audio_dk/Kconfig.defconfig b/boards/nordic/nrf5340_audio_dk/Kconfig.defconfig index 62316a2aeb0..f8315be4e25 100644 --- a/boards/nordic/nrf5340_audio_dk/Kconfig.defconfig +++ b/boards/nordic/nrf5340_audio_dk/Kconfig.defconfig @@ -62,12 +62,6 @@ config HEAP_MEM_POOL_ADD_SIZE_BOARD endif # BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP || BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS -config IPM_NRFX - default IPM - -config MBOX_NRFX_IPC - default MBOX - if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUNET config BT_CTLR diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_config.c b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_config.c new file mode 100644 index 00000000000..d907aee691a --- /dev/null +++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_config.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2020 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include + +LOG_MODULE_REGISTER(nrf5340_audio_dk_nrf5340_cpuapp, CONFIG_LOG_DEFAULT_LEVEL); + +static int core_config(void) +{ + nrf_gpiote_latency_t latency; + + latency = nrf_gpiote_latency_get(NRF_GPIOTE); + + if (latency != NRF_GPIOTE_LATENCY_LOWPOWER) { + LOG_DBG("Setting gpiote latency to low power"); + nrf_gpiote_latency_set(NRF_GPIOTE, NRF_GPIOTE_LATENCY_LOWPOWER); + } + + return 0; +} + +SYS_INIT(core_config, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_cpunet_reset.c b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_cpunet_reset.c deleted file mode 100644 index f9082e6ca40..00000000000 --- a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_cpunet_reset.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) 2020 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -#include -#include -#include - -LOG_MODULE_REGISTER(nrf5340_audio_dk_nrf5340_cpuapp, CONFIG_LOG_DEFAULT_LEVEL); - -#if defined(CONFIG_BT_CTLR_DEBUG_PINS_CPUAPP) -#include <../subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/debug.h> -#else -#define DEBUG_SETUP() -#endif - -static int core_config(void) -{ - nrf_gpiote_latency_t latency; - - latency = nrf_gpiote_latency_get(NRF_GPIOTE); - - if (latency != NRF_GPIOTE_LATENCY_LOWPOWER) { - LOG_DBG("Setting gpiote latency to low power"); - nrf_gpiote_latency_set(NRF_GPIOTE, NRF_GPIOTE_LATENCY_LOWPOWER); - } - - return 0; -} - -static void remoteproc_mgr_config(void) -{ -#if !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) || defined(CONFIG_BUILD_WITH_TFM) - /* Route Bluetooth Controller Debug Pins */ - DEBUG_SETUP(); -#endif /* !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) || defined(CONFIG_BUILD_WITH_TFM) */ - -#if !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) - /* Retain nRF5340 Network MCU in Secure domain (bus - * accesses by Network MCU will have Secure attribute set). - */ - NRF_SPU->EXTDOMAIN[0].PERM = 1 << 4; -#endif /* !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) */ -} - -static int remoteproc_mgr_boot(void) -{ - int ret; - - - ret = core_config(); - if (ret) { - return ret; - } - - /* Secure domain may configure permissions for the Network MCU. */ - remoteproc_mgr_config(); - -#if !defined(CONFIG_TRUSTED_EXECUTION_SECURE) - /* - * Building Zephyr with CONFIG_TRUSTED_EXECUTION_SECURE=y implies - * building also a Non-Secure image. The Non-Secure image will, in - * this case do the remainder of actions to properly configure and - * boot the Network MCU. - */ - - /* Release the Network MCU, 'Release force off signal' */ - nrf_reset_network_force_off(NRF_RESET, false); - - LOG_DBG("Network MCU released."); -#endif /* !CONFIG_TRUSTED_EXECUTION_SECURE */ - - return 0; -} - -SYS_INIT(remoteproc_mgr_boot, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp.yaml b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp.yaml index a4433e7e030..8d8e3781795 100644 --- a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp.yaml +++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp.yaml @@ -19,6 +19,5 @@ supported: - i2c - pwm - watchdog - - usb_cdc - usb_device vendor: nordic diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_common.dtsi b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_common.dtsi index 7f62b862639..70517a604ea 100644 --- a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_common.dtsi +++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_common.dtsi @@ -72,6 +72,18 @@ }; }; +&vregmain { + regulator-initial-mode = ; +}; + +&vregradio { + regulator-initial-mode = ; +}; + +&vregh { + status = "okay"; +}; + &adc { status = "okay"; #address-cells = <1>; @@ -220,55 +232,6 @@ arduino_spi: &spi4 { pinctrl-names = "default", "sleep"; }; -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x00010000>; - }; - slot0_partition: partition@10000 { - label = "image-0"; - }; - slot0_ns_partition: partition@50000 { - label = "image-0-nonsecure"; - }; - slot1_partition: partition@80000 { - label = "image-1"; - }; - slot1_ns_partition: partition@c0000 { - label = "image-1-nonsecure"; - }; - storage_partition: partition@fa000 { - label = "storage"; - reg = <0x000fa000 0x00006000>; - }; - }; -}; - -/ { - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_image: image@20000000 { - /* Zephyr image(s) memory */ - }; - - sram0_s: image_s@20000000 { - /* Secure image memory */ - }; - - sram0_ns: image_ns@20040000 { - /* Non-Secure image memory */ - }; - }; -}; - zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; @@ -285,6 +248,6 @@ zephyr_udc0: &usbd { }; }; -/* Include partition configuration file */ -#include "nrf5340_audio_dk_nrf5340_cpuapp_partition_conf.dtsi" +/* Include default memory partition configuration file */ +#include #include "nrf5340_audio_dk_nrf5340_shared.dtsi" diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns.dts b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns.dts index 74b120d452b..19e2231ba7e 100644 --- a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns.dts +++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns.dts @@ -13,7 +13,7 @@ compatible = "nordic,nrf5340-audio-dk-nrf5340-cpuapp"; chosen { - zephyr,sram = &sram0_ns; + zephyr,sram = &sram0_ns_app; zephyr,flash = &flash0; zephyr,code-partition = &slot0_ns_partition; }; diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns.yaml b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns.yaml index 4194fc63574..28a29575891 100644 --- a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns.yaml +++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns.yaml @@ -14,6 +14,5 @@ supported: - spi - pwm - watchdog - - usb_cdc - usb_device vendor: nordic diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_partition_conf.dtsi b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_partition_conf.dtsi deleted file mode 100644 index d2d81e728fc..00000000000 --- a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_partition_conf.dtsi +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (c) 2020 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* - * Default Flash planning for nrf5340_audio_dk_nrf5340 CPUAPP (Application MCU). - * - * Zephyr build for nRF5340 with ARM TrustZone-M support, - * implies building Secure and Non-Secure Zephyr images. - * - * Secure image will be placed, by default, in flash0 - * (or in slot0, if MCUboot is present). - * Secure image will use sram0 for system memory. - * - * Non-Secure image will be placed in slot0_ns, and use - * sram0_ns for system memory. - * - * Note that the Secure image only requires knowledge of - * the beginning of the Non-Secure image (not its size). - */ - -&slot0_partition { - reg = <0x00010000 0x40000>; -}; - -&slot0_ns_partition { - reg = <0x00050000 0x30000>; -}; - -&slot1_partition { - reg = <0x00080000 0x40000>; -}; - -&slot1_ns_partition { - reg = <0x000c0000 0x30000>; -}; - -/* Default SRAM planning when building for nRF5340 with - * ARM TrustZone-M support - * - Lowest 256 kB SRAM allocated to Secure image (sram0_s) - * - Middle 192 kB allocated to Non-Secure image (sram0_ns) - * - Upper 64 kB SRAM allocated as Shared memory (sram0_shared) - * (see nrf5340_audio_dk_nrf5340_shared_sram_planning_conf.dtsi) - */ -&sram0_image { - reg = <0x20000000 DT_SIZE_K(448)>; -}; - -&sram0_s { - reg = <0x20000000 0x40000>; -}; - -&sram0_ns { - reg = <0x20040000 0x30000>; -}; - -/* Include shared RAM configuration file */ -#include "nrf5340_audio_dk_nrf5340_shared_sram_planning_conf.dtsi" diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet.dts b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet.dts index beb151d451f..c50a51d3bc5 100644 --- a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet.dts +++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet.dts @@ -83,6 +83,6 @@ arduino_spi: &spi0 { }; }; -/* Include shared RAM configuration file */ -#include "nrf5340_audio_dk_nrf5340_shared_sram_planning_conf.dtsi" +/* Include default shared RAM configuration file */ +#include #include "nrf5340_audio_dk_nrf5340_shared.dtsi" diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_shared_sram_planning_conf.dtsi b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_shared_sram_planning_conf.dtsi deleted file mode 100644 index 2a96677a9dc..00000000000 --- a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_shared_sram_planning_conf.dtsi +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2020 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* Default shared SRAM planning when building for nRF5340. - * This file is included by both nRF5340 CPUAPP (Application MCU) - * and nRF5340 CPUNET (Network MCU). - * - 64 kB SRAM allocated as Shared memory (sram0_shared) - * - Region defined after the image SRAM of Application MCU - */ - -/ { - chosen { - /* shared memory reserved for the inter-processor communication */ - zephyr,ipc_shm = &sram0_shared; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_shared: memory@20070000 { - /* SRAM allocated to shared memory */ - reg = <0x20070000 0x10000>; - }; - }; -}; diff --git a/boards/nordic/nrf5340dk/CMakeLists.txt b/boards/nordic/nrf5340dk/CMakeLists.txt deleted file mode 100644 index 5128462d70c..00000000000 --- a/boards/nordic/nrf5340dk/CMakeLists.txt +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2019 Nordic Semiconductor ASA. -# SPDX-License-Identifier: Apache-2.0 - -if ((CONFIG_BOARD_NRF5340DK_NRF5340_CPUAPP OR CONFIG_BOARD_NRF5340DK_NRF5340_CPUAPP_NS) - AND CONFIG_BOARD_ENABLE_CPUNET) -zephyr_library() -zephyr_library_sources(nrf5340_cpunet_reset.c) - -if (CONFIG_BUILD_WITH_TFM) - zephyr_library_include_directories( - $/api_ns/interface/include - ) -endif() - -endif() diff --git a/boards/nordic/nrf5340dk/Kconfig b/boards/nordic/nrf5340dk/Kconfig index 7513fab4277..ee53c973ae8 100644 --- a/boards/nordic/nrf5340dk/Kconfig +++ b/boards/nordic/nrf5340dk/Kconfig @@ -5,41 +5,9 @@ if BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS -config BOARD_ENABLE_DCDC_APP - bool "Application MCU DCDC converter" - select SOC_DCDC_NRF53X_APP - default y - -config BOARD_ENABLE_DCDC_NET - bool "Network MCU DCDC converter" - select SOC_DCDC_NRF53X_NET - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF53X_HV - default y - -config BOARD_ENABLE_CPUNET - bool "NRF53 Network MCU" - select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ - $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) - help - This option enables releasing the Network 'force off' signal, which - as a consequence will power up the Network MCU during system boot. - Additionally, the option allocates GPIO pins that will be used by UARTE - of the Network MCU. - Note: GPIO pin allocation can only be configured by the secure Application - MCU firmware, so when this option is used with the non-secure version of - the board, the application needs to take into consideration, that the - secure firmware image must already have configured GPIO allocation for the - Network MCU. - default y if (BT || NRF_802154_SER_HOST) - config DOMAIN_CPUNET_BOARD string default "nrf5340dk/nrf5340/cpunet" - depends on BOARD_ENABLE_CPUNET help The board which will be used for CPUNET domain when creating a multi image application where one or more images should be located on diff --git a/boards/nordic/nrf5340dk/Kconfig.defconfig b/boards/nordic/nrf5340dk/Kconfig.defconfig index 972d8433c90..1c10b3e7dca 100644 --- a/boards/nordic/nrf5340dk/Kconfig.defconfig +++ b/boards/nordic/nrf5340dk/Kconfig.defconfig @@ -53,13 +53,6 @@ config FLASH_LOAD_SIZE endif # BOARD_NRF5340DK_NRF5340_CPUAPP_NS -endif # BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS - -config MBOX_NRFX_IPC - default MBOX - -if BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS - config BT_HCI_IPC default y if BT diff --git a/boards/nordic/nrf5340dk/doc/index.rst b/boards/nordic/nrf5340dk/doc/index.rst index e933f43bdb4..9aa3f79180b 100644 --- a/boards/nordic/nrf5340dk/doc/index.rst +++ b/boards/nordic/nrf5340dk/doc/index.rst @@ -278,7 +278,7 @@ applications as usual (:ref:`build_an_application` and information on how to install the nRF Command Line Tools can be found in :ref:`nordic_segger_flashing`. -Here is an example for the :ref:`hello_world` application running on the +Here is an example for the :zephyr:code-sample:`hello_world` application running on the nRF5340 application core. First, run your favorite terminal program to listen for output. diff --git a/boards/nordic/nrf5340dk/nrf5340_cpuapp_common.dtsi b/boards/nordic/nrf5340dk/nrf5340_cpuapp_common.dtsi index 59436374f2c..21701d9922d 100644 --- a/boards/nordic/nrf5340dk/nrf5340_cpuapp_common.dtsi +++ b/boards/nordic/nrf5340dk/nrf5340_cpuapp_common.dtsi @@ -3,6 +3,7 @@ * * SPDX-License-Identifier: Apache-2.0 */ +#include "nrf5340dk_common.dtsi" #include "nrf5340_cpuapp_common-pinctrl.dtsi" #include @@ -19,26 +20,6 @@ zephyr,ieee802154 = &ieee802154; }; - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; - label = "Green LED 0"; - }; - led1: led_1 { - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - label = "Green LED 1"; - }; - led2: led_2 { - gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; - label = "Green LED 2"; - }; - led3: led_3 { - gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; - label = "Green LED 3"; - }; - }; - pwmleds { compatible = "pwm-leds"; pwm_led0: pwm_led_0 { @@ -46,59 +27,6 @@ }; }; - buttons { - compatible = "gpio-keys"; - button0: button_0 { - gpios = <&gpio0 23 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button 1"; - zephyr,code = ; - }; - button1: button_1 { - gpios = <&gpio0 24 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button 2"; - zephyr,code = ; - }; - button2: button_2 { - gpios = <&gpio0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button 3"; - zephyr,code = ; - }; - button3: button_3 { - gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button 4"; - zephyr,code = ; - }; - }; - - arduino_header: connector { - compatible = "arduino-header-r3"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 4 0>, /* A0 */ - <1 0 &gpio0 5 0>, /* A1 */ - <2 0 &gpio0 6 0>, /* A2 */ - <3 0 &gpio0 7 0>, /* A3 */ - <4 0 &gpio0 25 0>, /* A4 */ - <5 0 &gpio0 26 0>, /* A5 */ - <6 0 &gpio1 0 0>, /* D0 */ - <7 0 &gpio1 1 0>, /* D1 */ - <8 0 &gpio1 4 0>, /* D2 */ - <9 0 &gpio1 5 0>, /* D3 */ - <10 0 &gpio1 6 0>, /* D4 */ - <11 0 &gpio1 7 0>, /* D5 */ - <12 0 &gpio1 8 0>, /* D6 */ - <13 0 &gpio1 9 0>, /* D7 */ - <14 0 &gpio1 10 0>, /* D8 */ - <15 0 &gpio1 11 0>, /* D9 */ - <16 0 &gpio1 12 0>, /* D10 */ - <17 0 &gpio1 13 0>, /* D11 */ - <18 0 &gpio1 14 0>, /* D12 */ - <19 0 &gpio1 15 0>, /* D13 */ - <20 0 &gpio1 2 0>, /* D14 */ - <21 0 &gpio1 3 0>; /* D15 */ - }; - arduino_adc: analog-connector { compatible = "arduino,uno-adc"; #io-channel-cells = <1>; @@ -120,23 +48,23 @@ /* These aliases are provided for compatibility with samples */ aliases { - led0 = &led0; - led1 = &led1; - led2 = &led2; - led3 = &led3; pwm-led0 = &pwm_led0; - sw0 = &button0; - sw1 = &button1; - sw2 = &button2; - sw3 = &button3; - bootloader-led0 = &led0; - mcuboot-button0 = &button0; - mcuboot-led0 = &led0; watchdog0 = &wdt0; - spi-flash0 = &mx25r64; }; }; +&vregmain { + regulator-initial-mode = ; +}; + +&vregradio { + regulator-initial-mode = ; +}; + +&vregh { + status = "okay"; +}; + &adc { status = "okay"; }; @@ -222,37 +150,6 @@ arduino_spi: &spi4 { pinctrl-names = "default", "sleep"; }; -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x00010000>; - }; - slot0_partition: partition@10000 { - label = "image-0"; - }; - slot0_ns_partition: partition@50000 { - label = "image-0-nonsecure"; - }; - slot1_partition: partition@80000 { - label = "image-1"; - }; - slot1_ns_partition: partition@c0000 { - label = "image-1-nonsecure"; - }; - /* 0xf0000 to 0xf7fff reserved for TF-M partitions */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; - &ieee802154 { status = "okay"; }; @@ -262,26 +159,5 @@ zephyr_udc0: &usbd { status = "okay"; }; -/ { - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_image: image@20000000 { - /* Zephyr image(s) memory */ - }; - - sram0_s: image_s@20000000 { - /* Secure image memory */ - }; - - sram0_ns: image_ns@20040000 { - /* Non-Secure image memory */ - }; - }; -}; - -/* Include partition configuration file */ -#include "nrf5340_cpuapp_partition_conf.dtsi" +/* Include default memory partition configuration file */ +#include diff --git a/boards/nordic/nrf5340dk/nrf5340_cpuapp_partition_conf.dtsi b/boards/nordic/nrf5340dk/nrf5340_cpuapp_partition_conf.dtsi deleted file mode 100644 index 07eadb8fe74..00000000000 --- a/boards/nordic/nrf5340dk/nrf5340_cpuapp_partition_conf.dtsi +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (c) 2019-2020 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* - * Default Flash planning for nrf5340dk_nrf5340 CPUAPP (Application MCU). - * - * Zephyr build for nRF5340 with ARM TrustZone-M support, - * implies building Secure and Non-Secure Zephyr images. - * - * Secure image will be placed, by default, in flash0 - * (or in slot0, if MCUboot is present). - * Secure image will use sram0 for system memory. - * - * Non-Secure image will be placed in slot0_ns, and use - * sram0_ns for system memory. - * - * Note that the Secure image only requires knowledge of - * the beginning of the Non-Secure image (not its size). - */ - -&slot0_partition { - reg = <0x00010000 0x40000>; -}; - -&slot0_ns_partition { - reg = <0x00050000 0x30000>; -}; - -&slot1_partition { - reg = <0x00080000 0x40000>; -}; - -&slot1_ns_partition { - reg = <0x000c0000 0x30000>; -}; - -/* Default SRAM planning when building for nRF5340 with - * ARM TrustZone-M support - * - Lowest 256 kB SRAM allocated to Secure image (sram0_s) - * - Middle 192 kB allocated to Non-Secure image (sram0_ns) - * - Upper 64 kB SRAM allocated as Shared memory (sram0_shared) - * (see nrf5340_shared_sram_planning_conf.dtsi) - */ -&sram0_image { - reg = <0x20000000 DT_SIZE_K(448)>; -}; - -&sram0_s { - reg = <0x20000000 0x40000>; -}; - -&sram0_ns { - reg = <0x20040000 0x30000>; -}; - -/* Include shared RAM configuration file */ -#include "nrf5340_shared_sram_planning_conf.dtsi" diff --git a/boards/nordic/nrf5340dk/nrf5340_shared_sram_planning_conf.dtsi b/boards/nordic/nrf5340dk/nrf5340_shared_sram_planning_conf.dtsi deleted file mode 100644 index b08bb94f6a5..00000000000 --- a/boards/nordic/nrf5340dk/nrf5340_shared_sram_planning_conf.dtsi +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2019 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* Default shared SRAM planning when building for nRF5340. - * This file is included by both nRF5340 CPUAPP (Application MCU) - * and nRF5340 CPUNET (Network MCU). - * - 64 kB SRAM allocated as Shared memory (sram0_shared) - * - Region defined after the image SRAM of Application MCU - */ - -/ { - chosen { - /* shared memory reserved for the inter-processor communication */ - zephyr,ipc_shm = &sram0_shared; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_shared: memory@20070000 { - /* SRAM allocated to shared memory */ - reg = <0x20070000 0x10000>; - }; - }; -}; diff --git a/boards/nordic/nrf5340dk/nrf5340dk_common.dtsi b/boards/nordic/nrf5340dk/nrf5340dk_common.dtsi new file mode 100644 index 00000000000..f5bbbaa03cd --- /dev/null +++ b/boards/nordic/nrf5340dk/nrf5340dk_common.dtsi @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2020 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; + label = "Green LED 0"; + }; + led1: led_1 { + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + label = "Green LED 1"; + }; + led2: led_2 { + gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; + label = "Green LED 2"; + }; + led3: led_3 { + gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; + label = "Green LED 3"; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio0 23 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 1"; + zephyr,code = ; + }; + button1: button_1 { + gpios = <&gpio0 24 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 2"; + zephyr,code = ; + }; + button2: button_2 { + gpios = <&gpio0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 3"; + zephyr,code = ; + }; + button3: button_3 { + gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 4"; + zephyr,code = ; + }; + }; + + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 4 0>, /* A0 */ + <1 0 &gpio0 5 0>, /* A1 */ + <2 0 &gpio0 6 0>, /* A2 */ + <3 0 &gpio0 7 0>, /* A3 */ + <4 0 &gpio0 25 0>, /* A4 */ + <5 0 &gpio0 26 0>, /* A5 */ + <6 0 &gpio1 0 0>, /* D0 */ + <7 0 &gpio1 1 0>, /* D1 */ + <8 0 &gpio1 4 0>, /* D2 */ + <9 0 &gpio1 5 0>, /* D3 */ + <10 0 &gpio1 6 0>, /* D4 */ + <11 0 &gpio1 7 0>, /* D5 */ + <12 0 &gpio1 8 0>, /* D6 */ + <13 0 &gpio1 9 0>, /* D7 */ + <14 0 &gpio1 10 0>, /* D8 */ + <15 0 &gpio1 11 0>, /* D9 */ + <16 0 &gpio1 12 0>, /* D10 */ + <17 0 &gpio1 13 0>, /* D11 */ + <18 0 &gpio1 14 0>, /* D12 */ + <19 0 &gpio1 15 0>, /* D13 */ + <20 0 &gpio1 2 0>, /* D14 */ + <21 0 &gpio1 3 0>; /* D15 */ + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + led3 = &led3; + sw0 = &button0; + sw1 = &button1; + sw2 = &button2; + sw3 = &button3; + bootloader-led0 = &led0; + mcuboot-button0 = &button0; + mcuboot-led0 = &led0; + }; +}; diff --git a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp.yaml b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp.yaml index 652aa5d4528..50ed4733871 100644 --- a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp.yaml +++ b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp.yaml @@ -14,7 +14,6 @@ supported: - i2s - pwm - watchdog - - usb_cdc - usb_device - usbd - netif:openthread diff --git a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns.dts b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns.dts index 14eb740f008..bf295aecc3a 100644 --- a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns.dts +++ b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns.dts @@ -13,7 +13,7 @@ compatible = "nordic,nrf5340-dk-nrf5340-cpuapp"; chosen { - zephyr,sram = &sram0_ns; + zephyr,sram = &sram0_ns_app; zephyr,flash = &flash0; zephyr,code-partition = &slot0_ns_partition; }; diff --git a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns.yaml b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns.yaml index 087c3025046..4c366d2f363 100644 --- a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns.yaml +++ b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns.yaml @@ -12,7 +12,6 @@ supported: - i2c - pwm - watchdog - - usb_cdc - usb_device - usbd - netif:openthread diff --git a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet.dts b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet.dts index 80c3d183cd2..7bc0cd9a4ba 100644 --- a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet.dts +++ b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include "nrf5340dk_common.dtsi" #include "nrf5340dk_nrf5340_cpunet-pinctrl.dtsi" #include @@ -27,92 +28,8 @@ zephyr,ieee802154 = &ieee802154; }; - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; - label = "Green LED 0"; - }; - led1: led_1 { - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - label = "Green LED 1"; - }; - led2: led_2 { - gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; - label = "Green LED 2"; - }; - led3: led_3 { - gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; - label = "Green LED 3"; - }; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - gpios = <&gpio0 23 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button 1"; - zephyr,code = ; - }; - button1: button_1 { - gpios = <&gpio0 24 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button 2"; - zephyr,code = ; - }; - button2: button_2 { - gpios = <&gpio0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button 3"; - zephyr,code = ; - }; - button3: button_3 { - gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button 4"; - zephyr,code = ; - }; - }; - - arduino_header: connector { - compatible = "arduino-header-r3"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 4 0>, /* A0 */ - <1 0 &gpio0 5 0>, /* A1 */ - <2 0 &gpio0 6 0>, /* A2 */ - <3 0 &gpio0 7 0>, /* A3 */ - <4 0 &gpio0 25 0>, /* A4 */ - <5 0 &gpio0 26 0>, /* A5 */ - <6 0 &gpio1 0 0>, /* D0 */ - <7 0 &gpio1 1 0>, /* D1 */ - <8 0 &gpio1 4 0>, /* D2 */ - <9 0 &gpio1 5 0>, /* D3 */ - <10 0 &gpio1 6 0>, /* D4 */ - <11 0 &gpio1 7 0>, /* D5 */ - <12 0 &gpio1 8 0>, /* D6 */ - <13 0 &gpio1 9 0>, /* D7 */ - <14 0 &gpio1 10 0>, /* D8 */ - <15 0 &gpio1 11 0>, /* D9 */ - <16 0 &gpio1 12 0>, /* D10 */ - <17 0 &gpio1 13 0>, /* D11 */ - <18 0 &gpio1 14 0>, /* D12 */ - <19 0 &gpio1 15 0>, /* D13 */ - <20 0 &gpio1 2 0>, /* D14 */ - <21 0 &gpio1 3 0>; /* D15 */ - }; - /* These aliases are provided for compatibility with samples */ aliases { - led0 = &led0; - led1 = &led1; - led2 = &led2; - led3 = &led3; - sw0 = &button0; - sw1 = &button1; - sw2 = &button2; - sw3 = &button3; - bootloader-led0 = &led0; - mcuboot-button0 = &button0; - mcuboot-led0 = &led0; watchdog0 = &wdt0; }; }; @@ -188,5 +105,5 @@ arduino_spi: &spi0 { status = "okay"; }; -/* Include shared RAM configuration file */ -#include "nrf5340_shared_sram_planning_conf.dtsi" +/* Include default shared RAM configuration file */ +#include diff --git a/boards/nordic/nrf54h20dk/Kconfig.nrf54h20dk b/boards/nordic/nrf54h20dk/Kconfig.nrf54h20dk index 23bea2ba1e1..9a260be4868 100644 --- a/boards/nordic/nrf54h20dk/Kconfig.nrf54h20dk +++ b/boards/nordic/nrf54h20dk/Kconfig.nrf54h20dk @@ -6,3 +6,5 @@ config BOARD_NRF54H20DK select SOC_NRF54H20_CPURAD if BOARD_NRF54H20DK_NRF54H20_CPURAD select SOC_NRF54H20_CPUPPR if BOARD_NRF54H20DK_NRF54H20_CPUPPR || \ BOARD_NRF54H20DK_NRF54H20_CPUPPR_XIP + select SOC_NRF54H20_CPUFLPR if BOARD_NRF54H20DK_NRF54H20_CPUFLPR || \ + BOARD_NRF54H20DK_NRF54H20_CPUFLPR_XIP diff --git a/boards/nordic/nrf54h20dk/board.yml b/boards/nordic/nrf54h20dk/board.yml index fed4c28d3e8..61690145d9f 100644 --- a/boards/nordic/nrf54h20dk/board.yml +++ b/boards/nordic/nrf54h20dk/board.yml @@ -6,3 +6,5 @@ board: variants: - name: xip cpucluster: cpuppr + - name: xip + cpucluster: cpuflpr diff --git a/boards/nordic/nrf54h20dk/doc/index.rst b/boards/nordic/nrf54h20dk/doc/index.rst index 6b8a08f0953..41306357fe4 100644 --- a/boards/nordic/nrf54h20dk/doc/index.rst +++ b/boards/nordic/nrf54h20dk/doc/index.rst @@ -20,11 +20,17 @@ The nRF54H20 is a multicore SoC with: Extensions, running at up to 320 MHz, referred to as the **application core** * an Arm Cortex-M33 core with DSP instructions, FPU, and Armv8-M Security Extensions, running at up to 256 MHz, referred to as the **radio core**. +* a Nordic VPR RISC-V core, referred to as the **ppr core** (Peripheral + Processor). The ``nrf54h20dk/nrf54h20/cpuapp`` build target provides support for the application core on the nRF54H20 SoC. The ``nrf54h20dk/nrf54h20/cpurad`` build target provides support for the radio core on the nRF54H20 SoC. +The ``nrf54h20dk/nrf54h20/cpuppr`` build target provides support for +the PPR core on the nRF54H20 SoC executing from RAM. +The ``nrf54h20dk/nrf54h20/cpuppr/xip`` build target provides support for +the PPR core on the nRF54H20 SoC executing from MRAM. nRF54H20 SoC provides support for the following devices: @@ -115,24 +121,21 @@ Push buttons Programming and Debugging ************************* -Applications for both the ``nrf54h20dk/nrf54h20/cpuapp`` and -``nrf54h20dk/nrf54h20/cpurad`` targets can be built, flashed, -and debugged in the usual way. See :ref:`build_an_application` -and :ref:`application_run` for more details on building and running. +Applications for all targets can be built and flashed the usual way. +See :ref:`build_an_application` and :ref:`application_run` for more details on +building and running. Debugging is for now limited to the application and radio +cores only, using :ref:`nordic_segger`. Flashing ======== -As an example, this section shows how to build and flash the :ref:`hello_world` +As an example, this section shows how to build and flash the :zephyr:code-sample:`hello_world` application. -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. - To build and program the sample to the nRF54H20 DK, complete the following steps: 1. Connect the nRF54H20 DK to your computer using the IMCU USB port on the DK. +2. Install `nRF Util`_ #. Build the sample by running the following command: .. zephyr-app-commands:: @@ -152,3 +155,6 @@ on the board are working properly with Zephyr: You can build and flash the examples to make sure Zephyr is running correctly on your board. The button and LED definitions can be found in :zephyr_file:`boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts`. + +.. _nRF Util: + https://www.nordicsemi.com/Products/Development-tools/nrf-util diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf.dtsi b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf.dtsi index 944dd7fb6ab..a17889fe0b0 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf.dtsi +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf.dtsi @@ -41,6 +41,13 @@ <&cpuppr_vevif 12>; }; + cpuapp_cpuflpr_ipc: ipc-2-14 { + compatible = "zephyr,ipc-icmsg"; + status = "disabled"; + mboxes = <&cpuapp_bellboard 14>, + <&cpuflpr_vevif 16>; + }; + cpurad_cpusys_ipc: ipc-3-12 { compatible = "zephyr,ipc-icmsg"; status = "disabled"; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi index e661beb8350..bf96741de22 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi @@ -110,6 +110,10 @@ }; }; + /* + * NOTE: perm-execute is not required as FLPR has a direct + * bridge with RAM21, bypassing MPC. + */ ram21_region: memory@2f890000 { compatible = "nordic,owned-memory"; status = "disabled"; @@ -121,9 +125,21 @@ #size-cells = <1>; ranges = <0x0 0x2f890000 0x10000>; - dma_fast_region: memory@8000 { + cpuflpr_code_data: memory@0 { + reg = <0x0 DT_SIZE_K(46)>; + }; + + cpuapp_cpuflpr_ipc_shm: memory@b800 { + reg = <0xb800 DT_SIZE_K(1)>; + }; + + cpuflpr_cpuapp_ipc_shm: memory@bc00 { + reg = <0xbc00 DT_SIZE_K(1)>; + }; + + dma_fast_region: memory@c000 { compatible = "zephyr,memory-region"; - reg = <0x8000 DT_SIZE_K(16)>; + reg = <0xc000 DT_SIZE_K(16)>; status = "disabled"; #memory-region-cells = <0>; zephyr,memory-region = "DMA_RAM21"; @@ -211,11 +227,15 @@ #size-cells = <1>; cpuapp_slot0_partition: partition@a6000 { - reg = <0xa6000 DT_SIZE_K(296)>; + reg = <0xa6000 DT_SIZE_K(248)>; + }; + + cpuppr_code_partition: partition@e4000 { + reg = <0xe4000 DT_SIZE_K(64)>; }; - cpuppr_code_partition: partition@f0000 { - reg = <0xf0000 DT_SIZE_K(64)>; + cpuflpr_code_partition: partition@f4000 { + reg = <0xf4000 DT_SIZE_K(48)>; }; }; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-pinctrl.dtsi b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-pinctrl.dtsi index da3effb5af8..79ac2c6b7ad 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-pinctrl.dtsi +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-pinctrl.dtsi @@ -5,13 +5,32 @@ */ &pinctrl { + /omit-if-no-ref/ uart120_default: uart120_default { + group1 { + psels = ; + }; + + group2 { + bias-pull-up; + psels = ; + }; + }; + + /omit-if-no-ref/ uart120_sleep: uart120_sleep { + group1 { + low-power-enable; + psels = , + ; + }; + }; + /omit-if-no-ref/ uart135_default: uart135_default { group1 { psels = , ; }; - group2 { + group3 { bias-pull-up; psels = , ; @@ -34,7 +53,7 @@ ; }; - group2 { + group3 { bias-pull-up; psels = , ; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts index fe48d88703b..3c7a5436a08 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts @@ -139,8 +139,14 @@ status = "okay"; interrupts = <96 NRF_DEFAULT_IRQ_PRIORITY>; interrupt-names = "irq0"; - /* irq0: 0: cpuapp-cpusec, 6: cpuapp-cpusys, 13: cpuapp-cpuppr, 18: cpuapp-cpurad */ - nordic,interrupt-mapping = <0x00042041 0>; + /* irq0: + * - 0: cpuapp-cpusec + * - 6: cpuapp-cpusys + * - 13: cpuapp-cpuppr + * - 14: cpuapp-cpuflpr + * - 18: cpuapp-cpurad + */ + nordic,interrupt-mapping = <0x00046041 0>; }; &cpurad_bellboard { @@ -184,6 +190,12 @@ ipc0: &cpuapp_cpurad_ipc { rx-region = <&cpuppr_cpuapp_ipc_shm>; }; +&cpuapp_cpuflpr_ipc { + mbox-names = "rx", "tx"; + tx-region = <&cpuapp_cpuflpr_ipc_shm>; + rx-region = <&cpuflpr_cpuapp_ipc_shm>; +}; + &cpuapp_dma_region { status = "okay"; }; @@ -205,6 +217,11 @@ ipc0: &cpuapp_cpurad_ipc { source-memory = <&cpuppr_code_partition>; }; +&cpuflpr_vpr { + execution-memory = <&cpuflpr_code_data>; + source-memory = <&cpuflpr_code_partition>; +}; + &gpiote130 { status = "okay"; owned-channels = <0 1 2 3 4 5 6 7>; @@ -225,6 +242,13 @@ ipc0: &cpuapp_cpurad_ipc { owned-channels = <4 5 6>; }; +&uart120 { + current-speed = <115200>; + pinctrl-0 = <&uart120_default>; + pinctrl-1 = <&uart120_sleep>; + pinctrl-names = "default", "sleep"; +}; + &uart135 { current-speed = <115200>; pinctrl-0 = <&uart135_default>; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr.dts new file mode 100644 index 00000000000..cbcf3261dae --- /dev/null +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr.dts @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "nrf54h20dk_nrf54h20-common.dtsi" + +/delete-node/ &cpuapp_cpurad_ipc; +/delete-node/ &cpuapp_cpusys_ipc; +/delete-node/ &cpuapp_cpuppr_ipc; +/delete-node/ &cpurad_cpusys_ipc; +/delete-node/ &cpusec_cpuapp_ipc; +/delete-node/ &cpusec_cpurad_ipc; + +/ { + compatible = "nordic,nrf54h20dk_nrf54h20-cpuflpr"; + model = "Nordic nRF54H20 DK nRF54H20 Fast Lightweight Processor MCU"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &uart120; + zephyr,code-partition = &cpuflpr_code_partition; + zephyr,flash = &mram1x; + zephyr,sram = &cpuflpr_code_data; + zephyr,shell-uart = &uart120; + }; +}; + +&cpuapp_cpuflpr_ipc { + mbox-names = "tx", "rx"; + tx-region = <&cpuflpr_cpuapp_ipc_shm>; + rx-region = <&cpuapp_cpuflpr_ipc_shm>; +}; + +&grtc { + status = "okay"; + owned-channels = <6>; +}; + +&uart120 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart120_default>; + pinctrl-1 = <&uart120_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr.yaml b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr.yaml new file mode 100644 index 00000000000..ba7d9a93382 --- /dev/null +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf54h20dk/nrf54h20/cpuflpr +name: nRF54H20-DK-nRF54H20-FLPR +type: mcu +arch: riscv +toolchain: + - zephyr +sysbuild: true +ram: 46 +flash: 46 +supported: + - counter + - gpio + - i2c + - pwm + - spi diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr_defconfig b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr_defconfig new file mode 100644 index 00000000000..b6ee6107d46 --- /dev/null +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr_defconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_USE_DT_CODE_PARTITION=y + +# Execute from RAM +CONFIG_XIP=n diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr_xip.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr_xip.dts new file mode 100644 index 00000000000..845e338128c --- /dev/null +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr_xip.dts @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "nrf54h20dk_nrf54h20_cpuflpr.dts" diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr_xip.yaml b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr_xip.yaml new file mode 100644 index 00000000000..63c771688b4 --- /dev/null +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr_xip.yaml @@ -0,0 +1,14 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf54h20dk/nrf54h20/cpuflpr/xip +name: nRF54H20-DK-nRF54H20-FLPR (MRAM XIP) +type: mcu +arch: riscv +toolchain: + - zephyr +sysbuild: true +ram: 46 +flash: 48 +supported: + - gpio diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr_xip_defconfig b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr_xip_defconfig new file mode 100644 index 00000000000..d73f271870b --- /dev/null +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr_xip_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_USE_DT_CODE_PARTITION=y + +CONFIG_XIP=y diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.dts index 0249d4bd87d..2143823239c 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.dts @@ -11,6 +11,7 @@ /delete-node/ &cpuapp_cpurad_ipc; /delete-node/ &cpuapp_cpusys_ipc; +/delete-node/ &cpuapp_cpuflpr_ipc; /delete-node/ &cpurad_cpusys_ipc; /delete-node/ &cpusec_cpuapp_ipc; /delete-node/ &cpusec_cpurad_ipc; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts index d0214652c2e..760d7ef34f9 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts @@ -11,6 +11,7 @@ /delete-node/ &cpuapp_cpuppr_ipc; /delete-node/ &cpuapp_cpusys_ipc; +/delete-node/ &cpuapp_cpuflpr_ipc; /delete-node/ &cpusec_cpuapp_ipc; / { diff --git a/boards/nordic/nrf54l15dk/doc/index.rst b/boards/nordic/nrf54l15dk/doc/index.rst index 6980076d954..7d450912661 100644 --- a/boards/nordic/nrf54l15dk/doc/index.rst +++ b/boards/nordic/nrf54l15dk/doc/index.rst @@ -94,7 +94,7 @@ built, flashed, and debugged in the usual way. See building and running. Applications for the ``nrf54l15dk/nrf54l15/cpuflpr`` board target need -to be build as multicore configuration with code snippet called ``vpr_launcher`` +to be built as multicore configuration with code snippet called ``vpr_launcher`` for the application core. Enter the following command to compile ``hello_world`` for the FLPR core:: @@ -103,7 +103,7 @@ Enter the following command to compile ``hello_world`` for the FLPR core:: Flashing ======== -As an example, this section shows how to build and flash the :ref:`hello_world` +As an example, this section shows how to build and flash the :zephyr:code-sample:`hello_world` application. .. warning:: diff --git a/boards/nordic/nrf54l15pdk/Kconfig b/boards/nordic/nrf54l15pdk/Kconfig index 8c937c8c890..841c93c51f0 100644 --- a/boards/nordic/nrf54l15pdk/Kconfig +++ b/boards/nordic/nrf54l15pdk/Kconfig @@ -3,6 +3,15 @@ # Copyright (c) 2024 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 +if BOARD_NRF54L15PDK_NRF54L15_CPUAPP + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_NRF54L_VREG_MAIN_DCDC + default y + +endif # BOARD_NRF54L15PDK_NRF54L15_CPUAPP + if BOARD_NRF54L15PDK_NRF54L15_CPUAPP_NS config NRF_MPC_REGION_SIZE diff --git a/boards/nordic/nrf54l15pdk/doc/index.rst b/boards/nordic/nrf54l15pdk/doc/index.rst index ccc6230dd7d..dc6e69b65e5 100644 --- a/boards/nordic/nrf54l15pdk/doc/index.rst +++ b/boards/nordic/nrf54l15pdk/doc/index.rst @@ -97,7 +97,7 @@ building and running. Flashing ======== -As an example, this section shows how to build and flash the :ref:`hello_world` +As an example, this section shows how to build and flash the :zephyr:code-sample:`hello_world` application. .. warning:: diff --git a/boards/nordic/nrf54l15pdk/nrf54l15_cpuapp_common.dtsi b/boards/nordic/nrf54l15pdk/nrf54l15_cpuapp_common.dtsi index d4532f90362..1327d48f5bd 100644 --- a/boards/nordic/nrf54l15pdk/nrf54l15_cpuapp_common.dtsi +++ b/boards/nordic/nrf54l15pdk/nrf54l15_cpuapp_common.dtsi @@ -14,14 +14,12 @@ zephyr,console = &uart20; zephyr,shell-uart = &uart20; zephyr,uart-mcumgr = &uart20; + zephyr,bt-mon-uart = &uart20; + zephyr,bt-c2h-uart = &uart20; zephyr,flash-controller = &rram_controller; zephyr,flash = &cpuapp_rram; zephyr,ieee802154 = &ieee802154; }; - - aliases { - spi-flash0 = &mx25r64; - }; }; &cpuapp_sram { diff --git a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.yaml b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.yaml index 9213c49fdd7..4b900736910 100644 --- a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.yaml +++ b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.yaml @@ -18,6 +18,7 @@ supported: - gpio - i2c - pwm + - retained_mem - spi - watchdog - i2s diff --git a/boards/nordic/nrf54l20pdk/Kconfig.defconfig b/boards/nordic/nrf54l20pdk/Kconfig.defconfig new file mode 100644 index 00000000000..850f69bdda0 --- /dev/null +++ b/boards/nordic/nrf54l20pdk/Kconfig.defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF54L20PDK_NRF54L20_CPUAPP + +config BT_CTLR + default BT + +config ROM_START_OFFSET + default 0x800 if BOOTLOADER_MCUBOOT + +config SOC_NRF54LX_SKIP_CLOCK_CONFIG + default y + +config SOC_NRF54LX_SKIP_GLITCHDETECTOR_DISABLE + default y + +endif # BOARD_NRF54L20PDK_NRF54L20_CPUAPP diff --git a/boards/nordic/nrf54l20pdk/Kconfig.nrf54l20pdk b/boards/nordic/nrf54l20pdk/Kconfig.nrf54l20pdk new file mode 100644 index 00000000000..09809ff7374 --- /dev/null +++ b/boards/nordic/nrf54l20pdk/Kconfig.nrf54l20pdk @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF54L20PDK + select SOC_NRF54L20_ENGA_CPUAPP if BOARD_NRF54L20PDK_NRF54L20_CPUAPP diff --git a/boards/nordic/nrf54l20pdk/board.cmake b/boards/nordic/nrf54l20pdk/board.cmake new file mode 100644 index 00000000000..5d36ac00a3e --- /dev/null +++ b/boards/nordic/nrf54l20pdk/board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=cortex-m33" "--speed=4000") + +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nordic/nrf54l20pdk/board.yml b/boards/nordic/nrf54l20pdk/board.yml new file mode 100644 index 00000000000..717adf8e75e --- /dev/null +++ b/boards/nordic/nrf54l20pdk/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf54l20pdk + vendor: nordic + socs: + - name: nrf54l20 diff --git a/boards/nordic/nrf54l20pdk/doc/index.rst b/boards/nordic/nrf54l20pdk/doc/index.rst new file mode 100644 index 00000000000..aaed616ecce --- /dev/null +++ b/boards/nordic/nrf54l20pdk/doc/index.rst @@ -0,0 +1,91 @@ +.. _nrf54l20pdk_nrf54l20: + +nRF54L20 PDK +############ + +Overview +******** + +.. note:: + + All software for the nRF54L20 SoC is experimental and hardware availability + is restricted to the participants in the limited sampling program. + +The nRF54L20 Preview Development Kit hardware provides +support for the Nordic Semiconductor nRF54L20 Arm Cortex-M33 CPU and +the following devices: + +* CLOCK +* RRAM +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`GRTC (Global real-time counter)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter)` + +Hardware +******** + +nRF54L20 PDK has two crystal oscillators: + +* High-frequency 32 MHz crystal oscillator (HFXO) +* Low-frequency 32.768 kHz crystal oscillator (LFXO) + +The crystal oscillators can be configured to use either +internal or external capacitors. + +Supported Features +================== + +The ``nrf54l20pdk/nrf54l20/cpuapp`` board target configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| RRAM | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| GRTC | on-chip | system clock | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Programming and Debugging +************************* + +Applications for the ``nrf54l20pdk/nrf54l20/cpuapp`` board target can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +As an example, this section shows how to build and flash the :zephyr:code-sample:`hello_world` +application. + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. + +To build and program the sample to the nRF54L20 PDK, complete the following steps: + +First, connect the nRF54L20 PDK to you computer using the IMCU USB port on the PDK. +Next, build the sample by running the following command: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf54l20pdk/nrf54l20/cpuapp + :goals: build flash + +Testing the LEDs and buttons in the nRF54L20 PDK +************************************************ + +Test the nRF54L20 PDK with a :zephyr:code-sample:`blinky` sample. diff --git a/boards/nordic/nrf54l20pdk/nrf54l20_cpuapp_common.dtsi b/boards/nordic/nrf54l20pdk/nrf54l20_cpuapp_common.dtsi new file mode 100644 index 00000000000..cdf6d62a30a --- /dev/null +++ b/boards/nordic/nrf54l20pdk/nrf54l20_cpuapp_common.dtsi @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* This file is common to the secure and non-secure domain */ + +#include +#include "nrf54l20pdk_nrf54l20-common.dtsi" + +/ { + chosen { + zephyr,console = &uart20; + zephyr,shell-uart = &uart20; + zephyr,uart-mcumgr = &uart20; + zephyr,bt-mon-uart = &uart20; + zephyr,bt-c2h-uart = &uart20; + zephyr,flash-controller = &rram_controller; + zephyr,flash = &cpuapp_rram; + zephyr,bt-hci = &bt_hci_controller; + zephyr,ieee802154 = &ieee802154; + }; +}; + +&cpuapp_sram { + status = "okay"; +}; + +&lfxo { + load-capacitors = "internal"; + load-capacitance-femtofarad = <15500>; +}; + +&hfxo { + load-capacitors = "internal"; + load-capacitance-femtofarad = <15000>; +}; + +&grtc { + owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>; + /* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */ + child-owned-channels = <3 4 7 8 9 10 11>; + status = "okay"; +}; + +&cpuapp_rram { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 DT_SIZE_K(64)>; + }; + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x10000 DT_SIZE_K(449)>; + }; + slot0_ns_partition: partition@80400 { + label = "image-0-nonsecure"; + reg = <0x80400 DT_SIZE_K(449)>; + }; + slot1_partition: partition@f0800 { + label = "image-1"; + reg = <0xf0800 DT_SIZE_K(449)>; + }; + slot1_ns_partition: partition@160c00 { + label = "image-1-nonsecure"; + reg = <0x160c00 DT_SIZE_K(449)>; + }; + }; +}; + +&uart20 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpiote20 { + status = "okay"; +}; + +&gpiote30 { + status = "okay"; +}; + +&radio { + status = "okay"; +}; + +&temp { + status = "okay"; +}; + +&clock { + status = "okay"; +}; + +&bt_hci_controller { + status = "okay"; +}; + +&ieee802154 { + status = "okay"; +}; diff --git a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-common.dtsi b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-common.dtsi new file mode 100644 index 00000000000..c188cd39e93 --- /dev/null +++ b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-common.dtsi @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "nrf54l20pdk_nrf54l20-pinctrl.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + label = "Green LED 0"; + }; + led1: led_1 { + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + label = "Green LED 1"; + }; + led2: led_2 { + gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + label = "Green LED 2"; + }; + led3: led_3 { + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + label = "Green LED 3"; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio1 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 0"; + zephyr,code = ; + }; + button1: button_1 { + gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 1"; + zephyr,code = ; + }; + button2: button_2 { + gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 2"; + zephyr,code = ; + }; + button3: button_3 { + gpios = <&gpio0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 3"; + zephyr,code = ; + }; + }; + + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + led3 = &led3; + sw0 = &button0; + sw1 = &button1; + sw2 = &button2; + sw3 = &button3; + watchdog0 = &wdt31; + }; +}; + +&uart20 { + current-speed = <115200>; + pinctrl-0 = <&uart20_default>; + pinctrl-1 = <&uart20_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-pinctrl.dtsi b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-pinctrl.dtsi new file mode 100644 index 00000000000..83aa91d8a34 --- /dev/null +++ b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-pinctrl.dtsi @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + /omit-if-no-ref/ uart20_default: uart20_default { + group1 { + psels = ; + }; + group2 { + psels = ; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ uart20_sleep: uart20_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; +}; diff --git a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp.dts b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp.dts new file mode 100644 index 00000000000..af32bc27eb7 --- /dev/null +++ b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp.dts @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "nrf54l20_cpuapp_common.dtsi" + +/ { + compatible = "nordic,nrf54l20pdk_nrf54l20-cpuapp"; + model = "Nordic nRF54L20 PDK nRF54L20 Application MCU"; + + chosen { + zephyr,code-partition = &slot0_partition; + zephyr,sram = &cpuapp_sram; + }; +}; diff --git a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp.yaml b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp.yaml new file mode 100644 index 00000000000..d11ea0d869f --- /dev/null +++ b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp.yaml @@ -0,0 +1,17 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf54l20pdk/nrf54l20/cpuapp +name: nRF54L20-PDK-nRF54L20-Application +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +sysbuild: true +ram: 512 +flash: 449 +supported: + - counter + - gpio diff --git a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp_defconfig b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp_defconfig new file mode 100644 index 00000000000..02796a1361e --- /dev/null +++ b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp_defconfig @@ -0,0 +1,29 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# MPU-based null-pointer dereferencing detection cannot +# be applied as the (0x0 - 0x400) is unmapped for this target. +CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y + +# Enable Cache +CONFIG_CACHE_MANAGEMENT=y +CONFIG_EXTERNAL_CACHE=y + +# Start SYSCOUNTER on driver init +CONFIG_NRF_GRTC_START_SYSCOUNTER=y diff --git a/boards/nordic/nrf7002dk/CMakeLists.txt b/boards/nordic/nrf7002dk/CMakeLists.txt new file mode 100644 index 00000000000..db20255712b --- /dev/null +++ b/boards/nordic/nrf7002dk/CMakeLists.txt @@ -0,0 +1,11 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if((CONFIG_BOARD_NRF7002DK_NRF5340_CPUAPP OR + CONFIG_BOARD_NRF7002DK_NRF5340_CPUAPP_NS OR + CONFIG_BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001 OR + CONFIG_BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001_NS) AND + CONFIG_BOARD_ENABLE_CPUNET) + zephyr_library() + zephyr_library_sources(nrf5340_cpunet_reset.c) +endif() diff --git a/boards/nordic/nrf7002dk/Kconfig b/boards/nordic/nrf7002dk/Kconfig new file mode 100644 index 00000000000..4bd84612e7a --- /dev/null +++ b/boards/nordic/nrf7002dk/Kconfig @@ -0,0 +1,71 @@ +# nRF5340 DK board configuration + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config IPM_NRFX + default IPM + +config MBOX_NRFX_IPC + default MBOX + +if BOARD_NRF7002DK_NRF5340_CPUAPP || \ + BOARD_NRF7002DK_NRF5340_CPUAPP_NS || \ + BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001 || \ + BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001_NS + +config BT_HCI_IPC + default y if BT + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BT_HCI_IPC + +config BOARD_ENABLE_CPUNET + bool "nRF53 Network MCU" + select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ + $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) + help + This option enables releasing the Network 'force off' signal, which + as a consequence will power up the Network MCU during system boot. + Additionally, the option allocates GPIO pins that will be used by UARTE + of the Network MCU. + Note: GPIO pin allocation can only be configured by the secure Application + MCU firmware, so when this option is used with the non-secure version of + the board, the application needs to take into consideration, that the + secure firmware image must already have configured GPIO allocation for the + Network MCU. + default y if (BT || NRF_802154_SER_HOST) + +config DOMAIN_CPUNET_BOARD + string + default "nrf7002dk/nrf5340/cpunet" + depends on BOARD_ENABLE_CPUNET + help + The board which will be used for CPUNET domain when creating a multi + image application where one or more images should be located on + another board. For example hci_ipc on the nRF5340_cpunet for + Bluetooth applications. + +endif + +if BOARD_NRF7002DK_NRF5340_CPUNET + +config BT_CTLR + default y if BT + +config BT_ECC + default y if BT + +config DOMAIN_CPUAPP_BOARD + string + default "nrf7002dk/nrf5340/cpuapp" if BOARD_NRF7002DK_NRF5340_CPUAPP + default "nrf7002dk/nrf5340/cpuapp/ns" if BOARD_NRF7002DK_NRF5340_CPUAPP_NS + default "nrf7002dk/nrf5340/cpuapp/nrf7001" if BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001 + default "nrf7002dk/nrf5340/cpuapp/nrf7001/ns" if BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001_NS + help + The board which will be used for CPUAPP domain when creating a multi + image application where one or more images should be located on + another board. + +endif diff --git a/boards/nordic/nrf7002dk/Kconfig.defconfig b/boards/nordic/nrf7002dk/Kconfig.defconfig new file mode 100644 index 00000000000..a6357ae50b2 --- /dev/null +++ b/boards/nordic/nrf7002dk/Kconfig.defconfig @@ -0,0 +1,76 @@ +# nRF5340 DK nRF5340 board configuration + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF7002DK_NRF5340_CPUAPP || \ + BOARD_NRF7002DK_NRF5340_CPUAPP_NS || \ + BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001 || \ + BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001_NS + +# By default, if we build for a Non-Secure version of the board, +# force building with TF-M as the Secure Execution Environment. +config BUILD_WITH_TFM + default y if BOARD_NRF7002DK_NRF5340_CPUAPP_NS || \ + BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001_NS + +if BUILD_WITH_TFM + +# By default, if we build with TF-M, instruct build system to +# flash the combined TF-M (Secure) & Zephyr (Non Secure) image +config TFM_FLASH_MERGED_BINARY + bool + default y + +endif # BUILD_WITH_TFM + +# Code Partition: +# +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# SRAM Partition: +# +# If the secure firmware is to be combined with a non-secure image +# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always +# be restricted to the secure image SRAM partition (sram-secure-partition). +# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram +# may be used by the image. +# +# For the non-secure version of the board, the firmware image SRAM is +# always restricted to the allocated non-secure SRAM partition. +# +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition +DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition + +if (BOARD_NRF7002DK_NRF5340_CPUAPP || BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001) && \ + TRUSTED_EXECUTION_SECURE + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config SRAM_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K) + +endif + +if BOARD_NRF7002DK_NRF5340_CPUAPP_NS || BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif + +endif diff --git a/boards/nordic/nrf7002dk/Kconfig.nrf7002dk b/boards/nordic/nrf7002dk/Kconfig.nrf7002dk new file mode 100644 index 00000000000..91f52ee6f08 --- /dev/null +++ b/boards/nordic/nrf7002dk/Kconfig.nrf7002dk @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Nordic Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF7002DK + select SOC_NRF5340_CPUNET_QKAA if BOARD_NRF7002DK_NRF5340_CPUNET + select SOC_NRF5340_CPUAPP_QKAA if BOARD_NRF7002DK_NRF5340_CPUAPP || \ + BOARD_NRF7002DK_NRF5340_CPUAPP_NS || \ + BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001 || \ + BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001_NS diff --git a/boards/nordic/nrf7002dk/board.cmake b/boards/nordic/nrf7002dk/board.cmake new file mode 100644 index 00000000000..bea0dc92ea9 --- /dev/null +++ b/boards/nordic/nrf7002dk/board.cmake @@ -0,0 +1,25 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_NRF7002DK_NRF5340_CPUAPP_NS OR + CONFIG_BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001_NS) + set(TFM_PUBLIC_KEY_FORMAT "full") +endif() + +if(CONFIG_BOARD_NRF7002DK_NRF5340_CPUAPP OR + CONFIG_BOARD_NRF7002DK_NRF5340_CPUAPP_NS OR + CONFIG_BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001 OR + CONFIG_BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001_NS) + board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000") +endif() + +if(CONFIG_TFM_FLASH_MERGED_BINARY) + set_property(TARGET runners_yaml_props_target PROPERTY hex_file "${CMAKE_BINARY_DIR}/zephyr/tfm_merged.hex") +endif() + +if(CONFIG_BOARD_NRF7002DK_NRF5340_CPUNET) + board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000") +endif() + +include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nordic/nrf7002dk/board.yml b/boards/nordic/nrf7002dk/board.yml new file mode 100644 index 00000000000..ca94d73429e --- /dev/null +++ b/boards/nordic/nrf7002dk/board.yml @@ -0,0 +1,12 @@ +board: + name: nrf7002dk + vendor: nordic + socs: + - name: nrf5340 + variants: + - name: ns + cpucluster: cpuapp + - name: nrf7001 + cpucluster: cpuapp + variants: + - name: ns diff --git a/boards/nordic/nrf7002dk/doc/img/nrf7002dk.jpg b/boards/nordic/nrf7002dk/doc/img/nrf7002dk.jpg new file mode 100644 index 00000000000..51d5572a13b Binary files /dev/null and b/boards/nordic/nrf7002dk/doc/img/nrf7002dk.jpg differ diff --git a/boards/nordic/nrf7002dk/doc/index.rst b/boards/nordic/nrf7002dk/doc/index.rst new file mode 100644 index 00000000000..3e3153c376f --- /dev/null +++ b/boards/nordic/nrf7002dk/doc/index.rst @@ -0,0 +1,341 @@ +.. _nrf7002dk_nrf5340: + +nRF7002 DK +########## + +Overview +******** + +The nRF7002 DK (PCA10143) is a single-board development kit for evaluation and development on +the nRF7002, a Wi-Fi companion IC to Nordic Semiconductor's nRF5340 System-on-Chip (SoC) host +processor. It is certified for the Wi-Fi Alliance® `Wi-Fi Certification program`_ in the +Connectivity, Security, and Optimization categories. See `UG Wi-Fi certification`_ for detailed +information. + +The nRF7002 is an IEEE 802.11ax (Wi-Fi 6) compliant solution that implements the Wi-Fi physical +layer and Medium Access Control (MAC) layer protocols. It implements the nRF Wi-Fi driver +software on the nRF5340 host processor communicating over the QSPI bus. + +The nRF5340 host is a dual-core SoC based on the Arm® Cortex®-M33 architecture. +It has the following features: + +* A full-featured Arm Cortex-M33F core with DSP instructions, FPU, and Armv8-M Security Extension, + running at up to 128 MHz, referred to as the application core. +* A secondary Arm Cortex-M33 core, with a reduced feature set, running at a fixed 64 MHz, + referred to as the network core. + +The ``nrf7002dk/nrf5340/cpuapp`` board target provides support for the application core on the +nRF5340 SoC. The ``nrf7002dk/nrf5340/cpunet`` board target provides support for the network +core on the nRF5340 SoC. + +.. figure:: img/nrf7002dk.jpg + :align: center + :alt: nRF7002 DK + + nRF7002 DK (Credit: Nordic Semiconductor) + +More information about the board can be found at the +`nRF7002 DK website`_. +The `nRF7002 DK Product Specification`_ +contains the processor's information and the datasheet. + +Hardware +======== + +* nRF7002 DK: + The nRF7002 DK has two external oscillators. + + * The frequency of the slow clock is 32.768 kHz. + * The frequency of the main clock is 32 MHz. + +* Micro-USB 2.0 cable + +Supported features +------------------ + +The ``nrf7002dk/nrf5340/cpuapp`` board configuration supports the following hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| RADIO | nrf7002 | Wi-Fi 6 (802.11ax) | ++-----------+------------+----------------------+ +| QSPI | on-chip | qspi | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +The ``nrf7002dk/nrf5340/cpunet`` board configuration supports the following hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See `nRF7002 DK Product Specification`_ +for a complete list of nRF7002 DK board hardware features. + +Connections and IOs +------------------- + +The connections and IOs supported by the development kit are listed in this section. + +LED +^^^ + +* **LED 1** (green) = **P1.06** +* **LED 2** (green) = **P1.07** + +Push buttons +^^^^^^^^^^^^ + +* **Button 1** = **SW1** = **P1.08** +* **Button 2** = **SW2** = **P1.09** +* **BOOT** = **SW5** = boot/reset + +Wi-Fi control +^^^^^^^^^^^^^ + +* BUCKEN = **P0.12** +* IOVDD CONTROL = **P0.31** +* HOST IRQ = **P0.23** +* COEX_REQ = **P0.28** +* COEX_STATUS0 = **P0.30** +* COEX_STATUS1 = **P0.29** +* COEX_GRANT = **P0.24** + +Security components +------------------- + +The following security components are available: + +* Implementation Defined Attribution Unit (`IDAU`_) on the application core. + + The IDAU is implemented with the System Protection Unit and is used to define + secure and non-secure memory maps. By default, the entire memory space + (Flash, SRAM, and peripheral address space) is defined to be secure-accessible only. + +* Secure boot. + +Programming and Debugging +************************* + +The nRF5340 application core supports the Armv8-M Security Extension. +Applications built for the ``nrf7002dk/nrf5340/cpuapp`` board boot by default in the +secure state. + +The nRF5340 network core does not support the Armv8-M Security Extension. +nRF5340 IDAU can configure bus accesses by the nRF5340 network core to have the secure +attribute set. This allows to build and run secure-only applications on the nRF5340 SoC. + +Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| +============================================================================= + +Applications on the nRF5340 may contain a Secure and a Non-Secure firmware +image for the application core. The Secure image can be built using either +Zephyr or `Trusted Firmware M`_ (TF-M). Non-Secure firmware +images are always built using Zephyr. The two alternatives are described below. + +.. note:: + + By default, SPE for the nRF5340 application core is built using TF-M. + +Building the Secure firmware with TF-M +-------------------------------------- + +The process to build the Secure firmware image using TF-M and the Non-Secure +firmware image using Zephyr requires the following steps: + +1. Build the Non-Secure Zephyr application + for the application core using ``-DBOARD=nrf7002dk/nrf5340/cpuapp/ns``. + To invoke the building of TF-M the Zephyr build system requires the + Kconfig option ``BUILD_WITH_TFM`` to be enabled, which is done by + default when building Zephyr as a Non-Secure application. + The Zephyr build system will perform the following steps automatically: + + * Build the Non-Secure firmware image as a regular Zephyr application + * Build a TF-M (secure) firmware image + * Merge the output image binaries together + * Optionally build a bootloader image (MCUboot) + +.. note:: + + Depending on the TF-M configuration, an application DTS overlay may be + required, to adjust the Non-Secure image Flash and SRAM starting address + and sizes. + +2. Build the application firmware for the network core using + ``-DBOARD=nrf7002dk/nrf5340/cpunet``. + +Building the Secure firmware using Zephyr +----------------------------------------- + +The process to build the Secure and the Non-Secure firmware images +using Zephyr requires the following steps: + +1. Build the Secure Zephyr application for the application core + using ``-DBOARD=nrf7002dk/nrf5340/cpuapp`` and + ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` and ``CONFIG_BUILD_WITH_TFM=n`` + in the application project configuration file. +2. Build the Non-Secure Zephyr application for the application core + using ``-DBOARD=nrf7002dk/nrf5340/cpuapp/ns``. +3. Merge the two binaries together. +4. Build the application firmware for the network core using + ``-DBOARD=nrf7002dk/nrf5340/cpunet``. + +When building a Secure/Non-Secure application for the nRF5340 application core, +the Secure application will have to set the IDAU (SPU) configuration to allow +Non-Secure access to all CPU resources utilized by the Non-Secure application +firmware. SPU configuration shall take place before jumping to the Non-Secure +application. + +Building a Secure only application +================================== + +Build the Zephyr app in the usual way (see :ref:`build_an_application` +and :ref:`application_run`), using ``-DBOARD=nrf7002dk/nrf5340/cpuapp`` for +the firmware running on the nRF5340 application core, and using +``-DBOARD=nrf7002dk/nrf5340/cpunet`` for the firmware running +on the nRF5340 network core. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then you can build and flash +applications as usual (:ref:`build_an_application` and +:ref:`application_run` for more details). + +.. warning:: + + The nRF5340 has a flash read-back protection feature. When flash read-back + protection is active, you will need to recover the chip before reflashing. + If you are flashing with :ref:`west `, run + this command for more details on the related ``--recover`` option: + + .. code-block:: console + + west flash -H -r nrfjprog --skip-rebuild + +.. note:: + + Flashing and debugging applications on the nRF5340 DK requires + upgrading the nRF Command Line Tools to version 10.12.0. Further + information on how to install the nRF Command Line Tools can be + found in :ref:`nordic_segger_flashing`. + +Here is an example for the :zephyr:code-sample:`hello_world` application running on the +nRF5340 application core. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board nRF7002 DK +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf7002dk/nrf5340/cpuapp + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic +boards with a Segger IC. + +Next steps +********** + +You have now completed getting started with the nRF7002 DK. +See the following links for where to go next: + +* `Installation`_ and `Configuring and Building`_ documentation to install the + nRF Connect SDK and learn more about its development environment. +* `Developing with nRF70`_ documentation for more advanced topics related to the nRF70 Series. +* `Wi-Fi`_ documentation for information related to Wi-Fi protocol and Wi-Fi modes of operation. + +References +********** + +.. target-notes:: + +.. _Wi-Fi Certification program: + https://www.wi-fi.org/certification +.. _UG Wi-Fi certification: + https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/protocols/wifi/wifi_certification.html#ug-wifi-certification +.. _IDAU: + https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau +.. _nRF7002 DK website: + https://www.nordicsemi.com/Products/Development-hardware/nrf7002-dk +.. _nRF7002 DK Product Specification: + https://docs.nordicsemi.com/bundle/ps_nrf5340/page/keyfeatures_html5.html +.. _Trusted Firmware M: + https://www.trustedfirmware.org/projects/tf-m/ +.. _Installation: + https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/installation.html#installation +.. _Configuring and Building: + https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/app_dev/config_and_build/index.html#configuration-and-build +.. _Developing with nRF70: + https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/app_dev/device_guides/nrf70/index.html#ug-nrf70-developing +.. _Wi-Fi: + https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/protocols/wifi/index.html#ug-wifi diff --git a/boards/nordic/nrf7002dk/nrf5340_cpuapp_common.dtsi b/boards/nordic/nrf7002dk/nrf5340_cpuapp_common.dtsi new file mode 100644 index 00000000000..ce11dbcb61d --- /dev/null +++ b/boards/nordic/nrf7002dk/nrf5340_cpuapp_common.dtsi @@ -0,0 +1,226 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "nrf5340_cpuapp_common_pinctrl.dtsi" +#include + +/ { + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,uart-mcumgr = &uart0; + zephyr,bt-mon-uart = &uart0; + zephyr,bt-c2h-uart = &uart0; + zephyr,bt-hci = &bt_hci_ipc0; + nordic,802154-spinel-ipc = &ipc0; + zephyr,ieee802154 = &ieee802154; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + label = "Green LED 0"; + }; + led1: led_1 { + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + label = "Green LED 1"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 1"; + zephyr,code = ; + }; + button1: button_1 { + gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 2"; + zephyr,code = ; + }; + }; + + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 4 0>, /* A0 */ + <1 0 &gpio0 5 0>, /* A1 */ + <2 0 &gpio0 6 0>, /* A2 */ + <3 0 &gpio0 7 0>, /* A3 */ + <4 0 &gpio0 25 0>, /* A4 */ + <5 0 &gpio0 26 0>, /* A5 */ + <6 0 &gpio1 0 0>, /* D0 */ + <7 0 &gpio1 1 0>, /* D1 */ + <8 0 &gpio1 4 0>, /* D2 */ + <9 0 &gpio1 5 0>, /* D3 */ + <10 0 &gpio1 6 0>, /* D4 */ + <11 0 &gpio1 7 0>, /* D5 */ + <12 0 &gpio1 8 0>, /* D6 */ + <13 0 &gpio1 9 0>, /* D7 */ + <14 0 &gpio1 10 0>, /* D8 */ + <15 0 &gpio1 11 0>, /* D9 */ + <16 0 &gpio1 12 0>, /* D10 */ + <17 0 &gpio1 13 0>, /* D11 */ + <18 0 &gpio1 14 0>, /* D12 */ + <19 0 &gpio1 15 0>, /* D13 */ + <20 0 &gpio1 2 0>, /* D14 */ + <21 0 &gpio1 3 0>; /* D15 */ + }; + + arduino_adc: analog-connector { + compatible = "arduino,uno-adc"; + #io-channel-cells = <1>; + io-channel-map = <0 &adc 0>, /* A0 = P0.4 = AIN0 */ + <1 &adc 1>, /* A1 = P0.5 = AIN1 */ + <2 &adc 2>, /* A2 = P0.6 = AIN2 */ + <3 &adc 3>, /* A3 = P0.7 = AIN3 */ + <4 &adc 4>, /* A4 = P0.25 = AIN4 */ + <5 &adc 5>; /* A5 = P0.26 = AIN5 */ + }; + + gpio_fwd: nrf-gpio-forwarder { + compatible = "nordic,nrf-gpio-forwarder"; + status = "okay"; + uart { + gpios = <&gpio1 1 0>, <&gpio1 0 0>, <&gpio1 5 0>, <&gpio1 4 0>; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + led1 = &led1; + pwm-led0 = &pwm_led0; + sw0 = &button0; + sw1 = &button1; + bootloader-led0 = &led0; + mcuboot-button0 = &button0; + mcuboot-led0 = &led0; + watchdog0 = &wdt0; + }; +}; + +&vregmain { + regulator-initial-mode = ; +}; + +&vregradio { + regulator-initial-mode = ; +}; + +&vregh { + status = "okay"; +}; + +&adc { + status = "okay"; +}; + +&gpiote { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +arduino_i2c: &i2c1 { + compatible = "nordic,nrf-twim"; + status = "okay"; + pinctrl-0 = <&i2c1_default>; + pinctrl-1 = <&i2c1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0_default>; + pinctrl-1 = <&pwm0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&spi4 { + compatible = "nordic,nrf-spim"; + status = "okay"; + pinctrl-0 = <&spi4_default>; + pinctrl-1 = <&spi4_sleep>; + pinctrl-names = "default", "sleep"; + cs-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; + mx25r64: mx25r6435f@0 { + compatible = "jedec,spi-nor"; + status = "disabled"; + reg = <0>; + spi-max-frequency = <33000000>; + jedec-id = [c2 28 17]; + sfdp-bfp = [ + e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb + ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 + 10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 68 44 + 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff + ]; + size = <67108864>; + has-dpd; + t-enter-dpd = <10000>; + t-exit-dpd = <5000>; + }; +}; + +&qspi { + status = "okay"; + pinctrl-0 = <&qspi_default>; + pinctrl-1 = <&qspi_sleep>; + pinctrl-names = "default", "sleep"; +}; + +arduino_serial: &uart1 { + compatible = "nordic,nrf-uarte"; + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-1 = <&uart1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +arduino_spi: &spi3 { + compatible = "nordic,nrf-spim"; + cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */ + pinctrl-0 = <&spi3_default>; + pinctrl-1 = <&spi3_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&ieee802154 { + status = "okay"; +}; + +zephyr_udc0: &usbd { + compatible = "nordic,nrf-usbd"; + status = "okay"; +}; + +/* Include default memory partition configuration file */ +#include diff --git a/boards/nordic/nrf7002dk/nrf5340_cpuapp_common_pinctrl.dtsi b/boards/nordic/nrf7002dk/nrf5340_cpuapp_common_pinctrl.dtsi new file mode 100644 index 00000000000..f04075f374d --- /dev/null +++ b/boards/nordic/nrf7002dk/nrf5340_cpuapp_common_pinctrl.dtsi @@ -0,0 +1,126 @@ +&pinctrl { + i2c1_default: i2c1_default { + group1 { + psels = , + ; + }; + }; + + i2c1_sleep: i2c1_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + uart0_default: uart0_default { + group1 { + psels = , + ; + }; + group2 { + psels = , + ; + bias-pull-up; + }; + }; + + uart0_sleep: uart0_sleep { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; + + pwm0_default: pwm0_default { + group1 { + psels = ; + }; + }; + + pwm0_sleep: pwm0_sleep { + group1 { + psels = ; + low-power-enable; + }; + }; + + qspi_default: qspi_default { + group1 { + psels = , + , + , + , + , + ; + }; + }; + + qspi_sleep: qspi_sleep { + group1 { + psels = , + , + , + , + , + ; + low-power-enable; + }; + }; + + uart1_default: uart1_default { + group1 { + psels = ; + }; + group2 { + psels = ; + bias-pull-up; + }; + }; + + uart1_sleep: uart1_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + spi3_default: spi3_default { + group1 { + psels = , + , + ; + }; + }; + + spi3_sleep: spi3_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; + + spi4_default: spi4_default { + group1 { + psels = , + , + ; + }; + }; + + spi4_sleep: spi4_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; +}; diff --git a/boards/nordic/nrf5340dk/nrf5340_cpunet_reset.c b/boards/nordic/nrf7002dk/nrf5340_cpunet_reset.c similarity index 81% rename from boards/nordic/nrf5340dk/nrf5340_cpunet_reset.c rename to boards/nordic/nrf7002dk/nrf5340_cpunet_reset.c index dadba8c0f54..b86b571db4b 100644 --- a/boards/nordic/nrf5340dk/nrf5340_cpunet_reset.c +++ b/boards/nordic/nrf7002dk/nrf5340_cpunet_reset.c @@ -1,27 +1,26 @@ /* - * Copyright (c) 2019-2021 Nordic Semiconductor ASA. + * Copyright (c) 2024 Nordic Semiconductor ASA * * SPDX-License-Identifier: Apache-2.0 */ -#include +#include #include #include #include #include -LOG_MODULE_REGISTER(nrf5340dk_nrf5340_cpuapp, CONFIG_LOG_DEFAULT_LEVEL); +LOG_MODULE_REGISTER(nrf7002dk_nrf5340_cpuapp, CONFIG_LOG_DEFAULT_LEVEL); #if defined(CONFIG_BT_CTLR_DEBUG_PINS_CPUAPP) #include <../subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/debug.h> -#else -#define DEBUG_SETUP() #endif static void remoteproc_mgr_config(void) { -#if !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) || defined(CONFIG_BUILD_WITH_TFM) +#if defined(CONFIG_BT_CTLR_DEBUG_PINS_CPUAPP) && \ + (!defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) || defined(CONFIG_BUILD_WITH_TFM)) /* Route Bluetooth Controller Debug Pins */ DEBUG_SETUP(); #endif /* !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) || defined(CONFIG_BUILD_WITH_TFM) */ @@ -30,7 +29,7 @@ static void remoteproc_mgr_config(void) /* Retain nRF5340 Network MCU in Secure domain (bus * accesses by Network MCU will have Secure attribute set). */ - NRF_SPU->EXTDOMAIN[0].PERM = 1 << 4; + NRF_SPU->EXTDOMAIN[0].PERM = BIT(4); #endif /* !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) */ } diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp.dts b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp.dts new file mode 100644 index 00000000000..fbe74a82224 --- /dev/null +++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp.dts @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "nrf5340_cpuapp_common.dtsi" +#include "nrf7002dk_nrf5340_cpuapp_pinctrl.dtsi" + +/ { + model = "Nordic NRF7002 DK NRF5340 Application"; + compatible = "nordic,nrf7002-dk-nrf5340-cpuapp"; + + chosen { + zephyr,sram = &sram0_image; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,sram-secure-partition = &sram0_s; + zephyr,sram-non-secure-partition = &sram0_ns; + zephyr,wifi = &wlan0; + }; +}; + +&qspi { + nrf70: nrf7002@1 { + compatible = "nordic,nrf7002-qspi"; + status = "okay"; + reg = <1>; + qspi-frequency = <24000000>; + qspi-quad-mode; + + #include "nrf70_common.dtsi" + #include "nrf70_common_coex.dtsi" + #include "nrf70_common_5g.dtsi" + }; +}; diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp.yaml b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp.yaml new file mode 100644 index 00000000000..9a6c6531442 --- /dev/null +++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp.yaml @@ -0,0 +1,20 @@ +identifier: nrf7002dk/nrf5340/cpuapp +name: NRF7002-DK-NRF5340-application-MCU +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 448 +flash: 1024 +supported: + - gpio + - i2c + - i2s + - pwm + - watchdog + - usbd + - usb_device + - netif:openthread +vendor: nordic diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_defconfig b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_defconfig new file mode 100644 index 00000000000..24eee284902 --- /dev/null +++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_defconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable PINCTRL +CONFIG_PINCTRL=y + +# Enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001.dts b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001.dts new file mode 100644 index 00000000000..1d78dddbe68 --- /dev/null +++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001.dts @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "nrf5340_cpuapp_common.dtsi" +#include "nrf7002dk_nrf5340_cpuapp_pinctrl.dtsi" + +/ { + model = "Nordic NRF7002 DK NRF5340 Application"; + compatible = "nordic,nrf7002-dk-nrf5340-cpuapp"; + + chosen { + zephyr,sram = &sram0_image; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,sram-secure-partition = &sram0_s; + zephyr,sram-non-secure-partition = &sram0_ns; + zephyr,wifi = &wlan0; + }; +}; + +&qspi { + nrf70: nrf7001@1 { + compatible = "nordic,nrf7001-qspi"; + status = "okay"; + reg = <1>; + qspi-frequency = <24000000>; + qspi-quad-mode; + + #include "nrf70_common.dtsi" + #include "nrf70_common_coex.dtsi" + }; +}; diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001.yaml b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001.yaml new file mode 100644 index 00000000000..e74ba0628ab --- /dev/null +++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001.yaml @@ -0,0 +1,20 @@ +identifier: nrf7002dk/nrf5340/cpuapp/nrf7001 +name: NRF7002-DK-NRF7001-NRF5340-application-MCU +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 448 +flash: 1024 +supported: + - gpio + - i2c + - i2s + - pwm + - watchdog + - usbd + - usb_device + - netif:openthread +vendor: nordic diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001_defconfig b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001_defconfig new file mode 100644 index 00000000000..870fdf32425 --- /dev/null +++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001_defconfig @@ -0,0 +1,24 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# enable GPIO +CONFIG_GPIO=y + +# enable PINCTRL +CONFIG_PINCTRL=y + +# Enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001_ns.dts b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001_ns.dts new file mode 100644 index 00000000000..cbbd46dff8b --- /dev/null +++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001_ns.dts @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "nrf5340_cpuapp_common.dtsi" + +/ { + model = "Nordic NRF5340 DK NRF5340 Application"; + compatible = "nordic,nrf5340-dk-nrf5340-cpuapp"; + + chosen { + zephyr,sram = &sram0_ns; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_ns_partition; + zephyr,entropy = &psa_rng; + zephyr,wifi = &wlan0; + }; + + psa_rng: psa-rng { + compatible = "zephyr,psa-crypto-rng"; + status = "okay"; + }; +}; + +&qspi { + nrf70: nrf7001@1 { + compatible = "nordic,nrf7001-qspi"; + status = "okay"; + reg = <1>; + qspi-frequency = <24000000>; + qspi-quad-mode; + + #include "nrf70_common.dtsi" + #include "nrf70_common_coex.dtsi" + }; +}; diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001_ns.yaml b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001_ns.yaml new file mode 100644 index 00000000000..16575969126 --- /dev/null +++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001_ns.yaml @@ -0,0 +1,19 @@ +identifier: nrf7002dk/nrf5340/cpuapp/nrf7001/ns +name: NRF7002-DK-NRF7001-NRF5340-application-MCU-Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 192 +flash: 192 +supported: + - gpio + - i2c + - pwm + - watchdog + - usbd + - usb_device + - netif:openthread +vendor: nordic diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001_ns_defconfig b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001_ns_defconfig new file mode 100644 index 00000000000..c536aae767d --- /dev/null +++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001_ns_defconfig @@ -0,0 +1,27 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# This Board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# enable GPIO +CONFIG_GPIO=y + +# enable PINCTRL +CONFIG_PINCTRL=y + +# Enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_ns.dts b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_ns.dts new file mode 100644 index 00000000000..ed219384795 --- /dev/null +++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_ns.dts @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "nrf5340_cpuapp_common.dtsi" + +/ { + model = "Nordic NRF5340 DK NRF5340 Application"; + compatible = "nordic,nrf5340-dk-nrf5340-cpuapp"; + + chosen { + zephyr,sram = &sram0_ns_app; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_ns_partition; + zephyr,entropy = &psa_rng; + zephyr,wifi = &wlan0; + }; + + psa_rng: psa-rng { + compatible = "zephyr,psa-crypto-rng"; + status = "okay"; + }; +}; + +&qspi { + nrf70: nrf7002@1 { + compatible = "nordic,nrf7002-qspi"; + status = "okay"; + reg = <1>; + qspi-frequency = <24000000>; + qspi-quad-mode; + + #include "nrf70_common.dtsi" + #include "nrf70_common_coex.dtsi" + #include "nrf70_common_5g.dtsi" + }; +}; diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_ns.yaml b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_ns.yaml new file mode 100644 index 00000000000..ea43785b455 --- /dev/null +++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_ns.yaml @@ -0,0 +1,19 @@ +identifier: nrf7002dk/nrf5340/cpuapp/ns +name: NRF7002-DK-NRF5340-application-MCU-Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 192 +flash: 192 +supported: + - gpio + - i2c + - pwm + - watchdog + - usbd + - usb_device + - netif:openthread +vendor: nordic diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_ns_defconfig b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_ns_defconfig new file mode 100644 index 00000000000..c5b2eaadc16 --- /dev/null +++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_ns_defconfig @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# This Board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# enable GPIO +CONFIG_GPIO=y + +# enable PINCTRL +CONFIG_PINCTRL=y + +# Enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_pinctrl.dtsi b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_pinctrl.dtsi new file mode 100644 index 00000000000..a7cde7241e5 --- /dev/null +++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_pinctrl.dtsi @@ -0,0 +1,18 @@ +&pinctrl { + spi2_default: spi2_default { + group1 { + psels = , + , + ; + }; + }; + + spi2_sleep: spi2_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; +}; diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet.dts b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet.dts new file mode 100644 index 00000000000..823c9fafacb --- /dev/null +++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet.dts @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "nrf7002dk_nrf5340_cpunet_pinctrl.dtsi" +#include + +/ { + model = "Nordic NRF7002 DK NRF5340 Network"; + compatible = "nordic,nrf7002-dk-nrf5340-cpunet"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,uart-mcumgr = &uart0; + zephyr,bt-mon-uart = &uart0; + zephyr,bt-c2h-uart = &uart0; + zephyr,bt-hci-ipc = &ipc0; + nordic,802154-spinel-ipc = &ipc0; + zephyr,sram = &sram1; + zephyr,flash = &flash1; + zephyr,code-partition = &slot0_partition; + zephyr,ieee802154 = &ieee802154; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + label = "Green LED 0"; + }; + led1: led_1 { + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + label = "Green LED 1"; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 1"; + zephyr,code = ; + }; + button1: button_1 { + gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 2"; + zephyr,code = ; + }; + }; + + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 4 0>, /* A0 */ + <1 0 &gpio0 5 0>, /* A1 */ + <2 0 &gpio0 6 0>, /* A2 */ + <3 0 &gpio0 7 0>, /* A3 */ + <4 0 &gpio0 25 0>, /* A4 */ + <5 0 &gpio0 26 0>, /* A5 */ + <6 0 &gpio1 0 0>, /* D0 */ + <7 0 &gpio1 1 0>, /* D1 */ + <8 0 &gpio1 4 0>, /* D2 */ + <9 0 &gpio1 5 0>, /* D3 */ + <10 0 &gpio1 6 0>, /* D4 */ + <11 0 &gpio1 7 0>, /* D5 */ + <12 0 &gpio1 8 0>, /* D6 */ + <13 0 &gpio1 9 0>, /* D7 */ + <14 0 &gpio1 10 0>, /* D8 */ + <15 0 &gpio1 11 0>, /* D9 */ + <16 0 &gpio1 12 0>, /* D10 */ + <17 0 &gpio1 13 0>, /* D11 */ + <18 0 &gpio1 14 0>, /* D12 */ + <19 0 &gpio1 15 0>, /* D13 */ + <20 0 &gpio1 2 0>, /* D14 */ + <21 0 &gpio1 3 0>; /* D15 */ + }; + + nrf70: coex { + status = "okay"; + compatible = "nordic,nrf70-coex"; + + #include "nrf70_common_coex.dtsi" + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + led1 = &led1; + sw0 = &button0; + sw1 = &button1; + bootloader-led0 = &led0; + mcuboot-button0 = &button0; + mcuboot-led0 = &led0; + watchdog0 = &wdt0; + }; +}; + +&gpiote { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +arduino_serial: &uart0{}; + +arduino_i2c: &i2c0 { + compatible = "nordic,nrf-twim"; + /* Cannot be used together with uart0. */ + /* status = "okay"; */ + pinctrl-0 = <&i2c0_default>; + pinctrl-1 = <&i2c0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +arduino_spi: &spi0 { + compatible = "nordic,nrf-spim"; + /* Cannot be used together with uart0. */ + /* status = "okay"; */ + cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */ + pinctrl-0 = <&spi0_default>; + pinctrl-1 = <&spi0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&flash1 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0xc000>; + }; + slot0_partition: partition@c000 { + label = "image-0"; + reg = <0x0000C000 0x17000>; + }; + slot1_partition: partition@23000 { + label = "image-1"; + reg = <0x00023000 0x17000>; + }; + storage_partition: partition@3a000 { + label = "storage"; + reg = <0x0003a000 0x6000>; + }; + }; +}; + +&ieee802154 { + status = "okay"; +}; + +/* Include default shared RAM configuration file */ +#include diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet.yaml b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet.yaml new file mode 100644 index 00000000000..f04ef6cee84 --- /dev/null +++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet.yaml @@ -0,0 +1,14 @@ +identifier: nrf7002dk/nrf5340/cpunet +name: NRF7002-DK-NRF5340-network-MCU +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 64 +flash: 256 +supported: + - gpio + - watchdog +vendor: nordic diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet_defconfig b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet_defconfig new file mode 100644 index 00000000000..ec4a0acd7a8 --- /dev/null +++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet_defconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# enable GPIO +CONFIG_GPIO=y + +# enable PINCTRL +CONFIG_PINCTRL=y + +# Enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet_pinctrl.dtsi b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet_pinctrl.dtsi new file mode 100644 index 00000000000..2e19d95f7f9 --- /dev/null +++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet_pinctrl.dtsi @@ -0,0 +1,55 @@ +&pinctrl { + uart0_default: uart0_default { + group1 { + psels = , + ; + }; + group2 { + psels = , + ; + bias-pull-up; + }; + }; + + uart0_sleep: uart0_sleep { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; + + i2c0_default: i2c0_default { + group1 { + psels = , + ; + }; + }; + + i2c0_sleep: i2c0_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + spi0_default: spi0_default { + group1 { + psels = , + , + ; + }; + }; + + spi0_sleep: spi0_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; +}; diff --git a/boards/nordic/nrf7002dk/nrf70_common.dtsi b/boards/nordic/nrf7002dk/nrf70_common.dtsi new file mode 100644 index 00000000000..f40f8ad9bb7 --- /dev/null +++ b/boards/nordic/nrf7002dk/nrf70_common.dtsi @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +iovdd-ctrl-gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; +bucken-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; +host-irq-gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>; + +wifi-max-tx-pwr-2g-dsss = <21>; +wifi-max-tx-pwr-2g-mcs0 = <16>; +wifi-max-tx-pwr-2g-mcs7 = <16>; + +wlan0: wlan { + compatible = "nordic,wlan"; +}; diff --git a/boards/nordic/nrf7002dk/nrf70_common_5g.dtsi b/boards/nordic/nrf7002dk/nrf70_common_5g.dtsi new file mode 100644 index 00000000000..8be559cebc3 --- /dev/null +++ b/boards/nordic/nrf7002dk/nrf70_common_5g.dtsi @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +wifi-max-tx-pwr-5g-low-mcs0 = <9>; +wifi-max-tx-pwr-5g-low-mcs7 = <9>; +wifi-max-tx-pwr-5g-mid-mcs0 = <11>; +wifi-max-tx-pwr-5g-mid-mcs7 = <11>; +wifi-max-tx-pwr-5g-high-mcs0 = <13>; +wifi-max-tx-pwr-5g-high-mcs7 = <13>; diff --git a/boards/nordic/nrf7002dk/nrf70_common_coex.dtsi b/boards/nordic/nrf7002dk/nrf70_common_coex.dtsi new file mode 100644 index 00000000000..03f22c3edba --- /dev/null +++ b/boards/nordic/nrf7002dk/nrf70_common_coex.dtsi @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +req-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; +status0-gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>; +grant-gpios = <&gpio0 24 (GPIO_PULL_DOWN | GPIO_ACTIVE_LOW)>; +swctrl1-gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; +srrf-switch-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; diff --git a/boards/nordic/nrf7002dk/pre_dt_board.cmake b/boards/nordic/nrf7002dk/pre_dt_board.cmake new file mode 100644 index 00000000000..5db1310639d --- /dev/null +++ b/boards/nordic/nrf7002dk/pre_dt_board.cmake @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: +# - flash-controller@39000 & kmu@39000 +# - power@5000 & clock@5000 +# - /reserved-memory/image@20000000 & /reserved-memory/image_s@20000000 +list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/nordic/nrf9131ek/doc/index.rst b/boards/nordic/nrf9131ek/doc/index.rst index accd403a286..236f6b396fc 100644 --- a/boards/nordic/nrf9131ek/doc/index.rst +++ b/boards/nordic/nrf9131ek/doc/index.rst @@ -180,7 +180,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_common.dtsi b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_common.dtsi index 2c3b8481d2a..0442b1cf527 100644 --- a/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_common.dtsi +++ b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_common.dtsi @@ -67,7 +67,6 @@ mcuboot-button0 = &button0; mcuboot-led0 = &led0; watchdog0 = &wdt0; - spi-flash0 = &gd25wb256; }; }; @@ -171,57 +170,5 @@ }; }; -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x10000>; - }; - slot0_partition: partition@10000 { - label = "image-0"; - }; - slot0_ns_partition: partition@50000 { - label = "image-0-nonsecure"; - }; - slot1_partition: partition@85000 { - label = "image-1"; - }; - slot1_ns_partition: partition@c5000 { - label = "image-1-nonsecure"; - }; - storage_partition: partition@fa000 { - label = "storage"; - reg = <0x000fa000 0x00006000>; - }; - }; -}; - - - -/ { - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_s: image_s@20000000 { - /* Secure image memory */ - }; - - sram0_modem: image_modem@20016000 { - /* Modem (shared) memory */ - }; - - sram0_ns: image_ns@20020000 { - /* Non-Secure image memory */ - }; - }; -}; - -/* Include partition configuration file */ -#include "nrf9131ek_nrf9131_partition_conf.dtsi" +/* Include default memory partition configuration file */ +#include diff --git a/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_ns.dts b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_ns.dts index 9a652cd0aed..7dcf700bcf6 100644 --- a/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_ns.dts +++ b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_ns.dts @@ -11,7 +11,7 @@ / { chosen { zephyr,flash = &flash0; - zephyr,sram = &sram0_ns; + zephyr,sram = &sram0_ns_app; zephyr,code-partition = &slot0_ns_partition; }; }; diff --git a/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_partition_conf.dtsi b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_partition_conf.dtsi deleted file mode 100644 index d14d8d95f75..00000000000 --- a/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_partition_conf.dtsi +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (c) 2023 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* - * Default Flash planning for nRF9131ek_nrf9131. - * - * Zephyr build for nRF9131 with ARM TrustZone-M support, - * implies building Secure and Non-Secure Zephyr images. - * - * Secure image will be placed, by default, in flash0 - * (or in slot0, if MCUboot is present). - * Secure image will use sram0 for system memory. - * - * Non-Secure image will be placed in slot0_ns, and use - * sram0_ns for system memory. - * - * Note that the Secure image only requires knowledge of - * the beginning of the Non-Secure image (not its size). - */ - -&slot0_partition { - reg = <0x00010000 0x40000>; -}; - -&slot0_ns_partition { - reg = <0x00050000 0x35000>; -}; - -&slot1_partition { - reg = <0x00085000 0x40000>; -}; - -&slot1_ns_partition { - reg = <0x000c5000 0x35000>; -}; - -/* Default SRAM planning when building for nRF9131 with - * ARM TrustZone-M support - * - Lowest 88 kB SRAM allocated to Secure image (sram0_s). - * - 40 kB SRAM reserved for and used by the modem library - * (sram0_modem). This memory is Non-Secure. - * - Upper 128 kB allocated to Non-Secure image (sram0_ns). - * When building with TF-M, both sram0_modem and sram0_ns - * are allocated to the Non-Secure image. - */ - -&sram0_s { - reg = <0x20000000 DT_SIZE_K(88)>; -}; - -&sram0_modem { - reg = <0x20016000 DT_SIZE_K(40)>; -}; - -&sram0_ns { - reg = <0x20020000 DT_SIZE_K(128)>; -}; diff --git a/boards/nordic/nrf9151dk/doc/index.rst b/boards/nordic/nrf9151dk/doc/index.rst index 4017347c4f8..2365de529f7 100644 --- a/boards/nordic/nrf9151dk/doc/index.rst +++ b/boards/nordic/nrf9151dk/doc/index.rst @@ -150,7 +150,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_common.dtsi b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_common.dtsi index 958e864c63c..8ed282fe49e 100644 --- a/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_common.dtsi +++ b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_common.dtsi @@ -128,7 +128,6 @@ mcuboot-button0 = &button0; mcuboot-led0 = &led0; watchdog0 = &wdt0; - spi-flash0 = &gd25wb256; }; }; @@ -214,55 +213,5 @@ arduino_spi: &spi3 { }; }; -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x10000>; - }; - slot0_partition: partition@10000 { - label = "image-0"; - }; - slot0_ns_partition: partition@50000 { - label = "image-0-nonsecure"; - }; - slot1_partition: partition@85000 { - label = "image-1"; - }; - slot1_ns_partition: partition@c5000 { - label = "image-1-nonsecure"; - }; - storage_partition: partition@fa000 { - label = "storage"; - reg = <0x000fa000 0x00006000>; - }; - }; -}; - -/ { - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_s: image_s@20000000 { - /* Secure image memory */ - }; - - sram0_modem: image_modem@20016000 { - /* Modem (shared) memory */ - }; - - sram0_ns: image_ns@20020000 { - /* Non-Secure image memory */ - }; - }; -}; - -/* Include partition configuration file */ -#include "nrf9151dk_nrf9151_partition_conf.dtsi" +/* Include default memory partition configuration file */ +#include diff --git a/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_ns.dts b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_ns.dts index a41c4aad388..8074695d251 100644 --- a/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_ns.dts +++ b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_ns.dts @@ -11,7 +11,7 @@ / { chosen { zephyr,flash = &flash0; - zephyr,sram = &sram0_ns; + zephyr,sram = &sram0_ns_app; zephyr,code-partition = &slot0_ns_partition; }; }; diff --git a/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_partition_conf.dtsi b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_partition_conf.dtsi deleted file mode 100644 index b209608a725..00000000000 --- a/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_partition_conf.dtsi +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (c) 2023 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* - * Default Flash planning for nRF9151dk_nrf9151. - * - * Zephyr build for nRF9151 with ARM TrustZone-M support, - * implies building Secure and Non-Secure Zephyr images. - * - * Secure image will be placed, by default, in flash0 - * (or in slot0, if MCUboot is present). - * Secure image will use sram0 for system memory. - * - * Non-Secure image will be placed in slot0_ns, and use - * sram0_ns for system memory. - * - * Note that the Secure image only requires knowledge of - * the beginning of the Non-Secure image (not its size). - */ - -&slot0_partition { - reg = <0x00010000 0x40000>; -}; - -&slot0_ns_partition { - reg = <0x00050000 0x35000>; -}; - -&slot1_partition { - reg = <0x00085000 0x40000>; -}; - -&slot1_ns_partition { - reg = <0x000c5000 0x35000>; -}; - -/* Default SRAM planning when building for nRF9151 with - * ARM TrustZone-M support - * - Lowest 88 kB SRAM allocated to Secure image (sram0_s). - * - 40 kB SRAM reserved for and used by the modem library - * (sram0_modem). This memory is Non-Secure. - * - Upper 128 kB allocated to Non-Secure image (sram0_ns). - * When building with TF-M, both sram0_modem and sram0_ns - * are allocated to the Non-Secure image. - */ - -&sram0_s { - reg = <0x20000000 DT_SIZE_K(88)>; -}; - -&sram0_modem { - reg = <0x20016000 DT_SIZE_K(40)>; -}; - -&sram0_ns { - reg = <0x20020000 DT_SIZE_K(128)>; -}; diff --git a/boards/nordic/nrf9160dk/CMakeLists.txt b/boards/nordic/nrf9160dk/CMakeLists.txt index 6b0e7e4ce64..27f5e1ac128 100644 --- a/boards/nordic/nrf9160dk/CMakeLists.txt +++ b/boards/nordic/nrf9160dk/CMakeLists.txt @@ -1,7 +1,7 @@ # Copyright (c) 2019 Nordic Semiconductor ASA. # SPDX-License-Identifier: Apache-2.0 -if(CONFIG_BOARD_NRF9160DK_NRF9160) +if(CONFIG_BOARD_NRF9160DK_NRF9160 OR CONFIG_BOARD_NRF9160DK_NRF9160_NS) zephyr_library() zephyr_library_sources(nrf52840_reset.c) elseif(CONFIG_BOARD_NRF9160DK_NRF52840) diff --git a/boards/nordic/nrf9160dk/Kconfig b/boards/nordic/nrf9160dk/Kconfig index 92b1b9a892a..c3687a10645 100644 --- a/boards/nordic/nrf9160dk/Kconfig +++ b/boards/nordic/nrf9160dk/Kconfig @@ -11,11 +11,6 @@ config BOARD_NRF9160DK if BOARD_NRF9160DK_NRF52840 -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - module = BOARD_NRF9160DK module-str = Board Control source "subsys/logging/Kconfig.template.log_config" diff --git a/boards/nordic/nrf9160dk/doc/index.rst b/boards/nordic/nrf9160dk/doc/index.rst index 70fd2c2fc46..a91cf76547b 100644 --- a/boards/nordic/nrf9160dk/doc/index.rst +++ b/boards/nordic/nrf9160dk/doc/index.rst @@ -214,7 +214,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. @@ -346,7 +346,7 @@ applications as usual (see :ref:`build_an_application` and Remember to set the PROG/DEBUG switch on the DK to nRF52. -See the following example for the :ref:`hello_world` application. +See the following example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf52840.dts b/boards/nordic/nrf9160dk/nrf9160dk_nrf52840.dts index 07dc648b853..937c7935fe7 100644 --- a/boards/nordic/nrf9160dk/nrf9160dk_nrf52840.dts +++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf52840.dts @@ -7,6 +7,7 @@ /dts-v1/; #include +#include #include "nrf9160dk_nrf52840-pinctrl.dtsi" / { @@ -18,9 +19,6 @@ zephyr,shell-uart = &uart0; zephyr,uart-mcumgr = &uart0; zephyr,bt-mon-uart = &uart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; zephyr,ieee802154 = &ieee802154; }; @@ -141,6 +139,10 @@ }; }; +®1 { + regulator-initial-mode = ; +}; + &uicr { gpio-as-nreset; }; @@ -173,39 +175,3 @@ &ieee802154 { status = "okay"; }; - -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000C000>; - }; - slot0_partition: partition@c000 { - label = "image-0"; - reg = <0x0000C000 0x00076000>; - }; - slot1_partition: partition@82000 { - label = "image-1"; - reg = <0x00082000 0x00076000>; - }; - - /* - * The flash starting at 0x000f8000 and ending at - * 0x000fffff is reserved for use by the application. - */ - - /* - * Storage partition will be used by FCB/LittleFS/NVS - * if enabled. - */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common.dtsi b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common.dtsi index a31b37017d5..f57b3fa17c2 100644 --- a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common.dtsi +++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common.dtsi @@ -216,57 +216,5 @@ arduino_spi: &spi3 { pinctrl-names = "default", "sleep"; }; -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x10000>; - }; - slot0_partition: partition@10000 { - label = "image-0"; - }; - slot0_ns_partition: partition@50000 { - label = "image-0-nonsecure"; - }; - slot1_partition: partition@80000 { - label = "image-1"; - }; - slot1_ns_partition: partition@c0000 { - label = "image-1-nonsecure"; - }; - /* 0xf0000 to 0xf7fff reserved for TF-M partitions */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; - -/ { - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_s: image_s@20000000 { - /* Secure image memory */ - }; - - sram0_modem: image_modem@20016000 { - /* Modem (shared) memory */ - }; - - sram0_ns: image_ns@20020000 { - /* Non-Secure image memory */ - }; - }; -}; - -/* Include partition configuration file */ -#include "nrf9160dk_nrf9160_partition_conf.dtsi" +/* Include default memory partition configuration file */ +#include diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common_0_14_0.dtsi b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common_0_14_0.dtsi index ee4f736bf8b..896531d7580 100644 --- a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common_0_14_0.dtsi +++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common_0_14_0.dtsi @@ -4,12 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ -/ { - aliases { - spi-flash0 = &mx25r64; - }; -}; - &interface_to_nrf52840 { gpio-map = <0 0 &gpio0 17 0>, <1 0 &gpio0 18 0>, diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_partition_conf.dtsi b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_partition_conf.dtsi deleted file mode 100644 index a6f16fb115c..00000000000 --- a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_partition_conf.dtsi +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (c) 2018-2020 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* - * Default Flash planning for nRF9160dk_nrf9160. - * - * Zephyr build for nRF9160 with ARM TrustZone-M support, - * implies building Secure and Non-Secure Zephyr images. - * - * Secure image will be placed, by default, in flash0 - * (or in slot0, if MCUboot is present). - * Secure image will use sram0 for system memory. - * - * Non-Secure image will be placed in slot0_ns, and use - * sram0_ns for system memory. - * - * Note that the Secure image only requires knowledge of - * the beginning of the Non-Secure image (not its size). - */ - -&slot0_partition { - reg = <0x00010000 0x40000>; -}; - -&slot0_ns_partition { - reg = <0x00050000 0x30000>; -}; - -&slot1_partition { - reg = <0x00080000 0x40000>; -}; - -&slot1_ns_partition { - reg = <0x000c0000 0x30000>; -}; - -/* Default SRAM planning when building for nRF9160 with - * ARM TrustZone-M support - * - Lowest 88 kB SRAM allocated to Secure image (sram0_s). - * - 40 kB SRAM reserved for and used by the modem library - * (sram0_modem). This memory is Non-Secure. - * - Upper 128 kB allocated to Non-Secure image (sram0_ns). - * When building with TF-M, both sram0_modem and sram0_ns - * are allocated to the Non-Secure image. - */ - -&sram0_s { - reg = <0x20000000 DT_SIZE_K(88)>; -}; - -&sram0_modem { - reg = <0x20016000 DT_SIZE_K(40)>; -}; - -&sram0_ns { - reg = <0x20020000 DT_SIZE_K(128)>; -}; diff --git a/boards/nordic/nrf9161dk/doc/index.rst b/boards/nordic/nrf9161dk/doc/index.rst index 251c8467a21..bb9d4eebbe4 100644 --- a/boards/nordic/nrf9161dk/doc/index.rst +++ b/boards/nordic/nrf9161dk/doc/index.rst @@ -153,7 +153,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common.dtsi b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common.dtsi index 8168a8317e4..7dade3bc0f7 100644 --- a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common.dtsi +++ b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common.dtsi @@ -128,7 +128,6 @@ mcuboot-button0 = &button0; mcuboot-led0 = &led0; watchdog0 = &wdt0; - spi-flash0 = &gd25wb256; }; }; @@ -214,55 +213,5 @@ arduino_spi: &spi3 { }; }; -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x10000>; - }; - slot0_partition: partition@10000 { - label = "image-0"; - }; - slot0_ns_partition: partition@50000 { - label = "image-0-nonsecure"; - }; - slot1_partition: partition@85000 { - label = "image-1"; - }; - slot1_ns_partition: partition@c5000 { - label = "image-1-nonsecure"; - }; - storage_partition: partition@fa000 { - label = "storage"; - reg = <0x000fa000 0x00006000>; - }; - }; -}; - -/ { - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_s: image_s@20000000 { - /* Secure image memory */ - }; - - sram0_modem: image_modem@20016000 { - /* Modem (shared) memory */ - }; - - sram0_ns: image_ns@20020000 { - /* Non-Secure image memory */ - }; - }; -}; - -/* Include partition configuration file */ -#include "nrf9161dk_nrf9161_partition_conf.dtsi" +/* Include default memory partition configuration file */ +#include diff --git a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common_0_7_0.dtsi b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common_0_7_0.dtsi index ae67df77b22..312997e0178 100644 --- a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common_0_7_0.dtsi +++ b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common_0_7_0.dtsi @@ -4,6 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ +/* Remove v0.9.0 variant flash */ +/delete-node/ &gd25wb256; + &spi3 { gd25lb256: gd25lb256e3ir@1 { compatible = "jedec,spi-nor"; @@ -23,9 +26,3 @@ t-exit-dpd = <30000>; }; }; - -/ { - aliases { - spi-flash0 = &gd25lb256; - }; -}; diff --git a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns.dts b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns.dts index b7d0c62965f..1bb0c0f2512 100644 --- a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns.dts +++ b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns.dts @@ -11,7 +11,7 @@ / { chosen { zephyr,flash = &flash0; - zephyr,sram = &sram0_ns; + zephyr,sram = &sram0_ns_app; zephyr,code-partition = &slot0_ns_partition; }; }; diff --git a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_partition_conf.dtsi b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_partition_conf.dtsi deleted file mode 100644 index 9e378cb94e0..00000000000 --- a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_partition_conf.dtsi +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (c) 2023 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* - * Default Flash planning for nRF9161dk_nrf9161. - * - * Zephyr build for nRF9161 with ARM TrustZone-M support, - * implies building Secure and Non-Secure Zephyr images. - * - * Secure image will be placed, by default, in flash0 - * (or in slot0, if MCUboot is present). - * Secure image will use sram0 for system memory. - * - * Non-Secure image will be placed in slot0_ns, and use - * sram0_ns for system memory. - * - * Note that the Secure image only requires knowledge of - * the beginning of the Non-Secure image (not its size). - */ - -&slot0_partition { - reg = <0x00010000 0x40000>; -}; - -&slot0_ns_partition { - reg = <0x00050000 0x35000>; -}; - -&slot1_partition { - reg = <0x00085000 0x40000>; -}; - -&slot1_ns_partition { - reg = <0x000c5000 0x35000>; -}; - -/* Default SRAM planning when building for nRF9161 with - * ARM TrustZone-M support - * - Lowest 88 kB SRAM allocated to Secure image (sram0_s). - * - 40 kB SRAM reserved for and used by the modem library - * (sram0_modem). This memory is Non-Secure. - * - Upper 128 kB allocated to Non-Secure image (sram0_ns). - * When building with TF-M, both sram0_modem and sram0_ns - * are allocated to the Non-Secure image. - */ - -&sram0_s { - reg = <0x20000000 DT_SIZE_K(88)>; -}; - -&sram0_modem { - reg = <0x20016000 DT_SIZE_K(40)>; -}; - -&sram0_ns { - reg = <0x20020000 DT_SIZE_K(128)>; -}; diff --git a/boards/nordic/nrf9280pdk/doc/index.rst b/boards/nordic/nrf9280pdk/doc/index.rst deleted file mode 100644 index ef230148d5e..00000000000 --- a/boards/nordic/nrf9280pdk/doc/index.rst +++ /dev/null @@ -1,175 +0,0 @@ -.. _nrf9280pdk_nrf9280: - -nRF9280 PDK -########### - -Overview -******** - -.. note:: - - All software for the nRF9280 SiP is experimental and hardware availability - is restricted to the participants in the limited sampling program. - -The nRF9280 DK is a single-board development kit for evaluation and development -on the Nordic nRF9280 System-in-Package (SiP). - -The nRF9280 is a multicore SiP with: - -* an Arm Cortex-M33 core with DSP instructions, FPU, and Armv8-M Security - Extensions, running at up to 320 MHz, referred to as the **application core** -* an Arm Cortex-M33 core with DSP instructions, FPU, and Armv8-M Security - Extensions, running at up to 256 MHz, referred to as the **radio core**. - -The ``nrf9280pdk/nrf9280/cpuapp`` board target provides support for -the application core on the nRF9280 SiP. -The ``nrf9280pdk/nrf9280/cpurad`` board target provides support for -the radio core on the nRF9280 SiP. -The ``nrf9280pdk/nrf9280/cpuppr`` board target provides support for -the PPR core on the nRF9280 SiP. - -nRF9280 SiP provides support for the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`GRTC (Global real-time counter)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* MRAM -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -Hardware -******** - -nRF9280 DK has two crystal oscillators: - -* High-frequency 32 MHz crystal oscillator (HFXO) -* Low-frequency 32.768 kHz crystal oscillator (LFXO) - -Supported Features -================== - -The ``nrf9280pdk/nrf9280/cpuapp`` board target supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| GRTC | on-chip | system clock | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -The ``nrf9280pdk/nrf9280/cpurad`` board target supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| GRTC | on-chip | system clock | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -The ``nrf9280pdk/nrf9280/cpuppr`` board target supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| GRTC | on-chip | system clock | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. - -Connections and IOs -=================== - -LEDs ----- - -* LED1 (green) = P9.02 -* LED2 (green) = P9.03 -* LED3 (green) = P9.04 -* LED4 (green) = P9.05 - -Push buttons ------------- - -* BUTTON1 = P0.8 -* BUTTON2 = P0.9 -* BUTTON3 = P0.10 -* BUTTON4 = P0.11 -* RESET (SW1) - -Programming and Debugging -************************* - -Applications for both the ``nrf9280pdk/nrf9280/cpuapp`` and -``nrf9280pdk/nrf9280/cpurad`` board targets can be built, flashed, -and debugged in the usual way. See :ref:`build_an_application` -and :ref:`application_run` for more details on building and running. - -Flashing -======== - -As an example, this section shows how to build and flash the :ref:`hello_world` -application. - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. - -To build and program the sample to the nRF9280 DK, complete the following steps: - -1. Connect the nRF9280 DK to your computer using the IMCU USB port on the DK. -#. Build the sample by running the following command: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf9280pdk/nrf9280/cpuapp - :goals: build flash - -Testing the LEDs and buttons in the nRF9280 DK -*********************************************** - -There are 2 samples that allow you to test that the buttons (switches) and LEDs -on the board are working properly with Zephyr: - -* :zephyr:code-sample:`blinky` -* :zephyr:code-sample:`button` - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.dts`. diff --git a/boards/nordic/thingy52/doc/index.rst b/boards/nordic/thingy52/doc/index.rst index e83968f7469..bef78aa2ed6 100644 --- a/boards/nordic/thingy52/doc/index.rst +++ b/boards/nordic/thingy52/doc/index.rst @@ -376,7 +376,7 @@ The green lightwell LED can be tested with the :zephyr:code-sample:`blinky` exam -Also the temperature and humidity sensor can be tested with the :ref:`hts221` +Also the temperature and humidity sensor can be tested with the :zephyr:code-sample:`hts221` sample. .. zephyr-app-commands:: diff --git a/boards/nordic/thingy53/Kconfig b/boards/nordic/thingy53/Kconfig index d7be16ff007..01b2ee7dfcf 100644 --- a/boards/nordic/thingy53/Kconfig +++ b/boards/nordic/thingy53/Kconfig @@ -9,50 +9,15 @@ config THINGY53_INIT_PRIORITY help Initialization priority of the Thingy:53. -config MBOX_NRFX_IPC - default MBOX - if BOARD_THINGY53_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP_NS -config BOARD_ENABLE_DCDC_APP - bool "Application MCU DCDC converter" - select SOC_DCDC_NRF53X_APP - default y - -config BOARD_ENABLE_DCDC_NET - bool "Network MCU DCDC converter" - select SOC_DCDC_NRF53X_NET - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF53X_HV - default y - config BOARD_SERIAL_BACKEND_CDC_ACM bool "USB CDC" default y -config BOARD_ENABLE_CPUNET - bool "NRF53 Network MCU" - select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ - $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) - help - This option enables releasing the Network 'force off' signal, which - as a consequence will power up the Network MCU during system boot. - Additionally, the option allocates GPIO pins that will be used by UARTE - of the Network MCU. - Note: GPIO pin allocation can only be configured by the secure Application - MCU firmware, so when this option is used with the non-secure version of - the board, the application needs to take into consideration, that the - secure firmware image must already have configured GPIO allocation for the - Network MCU. - default y if (BT || NRF_802154_SER_HOST) - config DOMAIN_CPUNET_BOARD string default "thingy53/nrf5340/cpunet" - depends on BOARD_ENABLE_CPUNET help The board which will be used for CPUNET domain when creating a multi image application where one or more images should be located on diff --git a/boards/nordic/thingy53/board.c b/boards/nordic/thingy53/board.c index 67059bd4ee8..d6a220ab7f7 100644 --- a/boards/nordic/thingy53/board.c +++ b/boards/nordic/thingy53/board.c @@ -6,11 +6,6 @@ #include #include -#include -#include -#include - -LOG_MODULE_REGISTER(thingy53_board_init); /* Initialization chain of Thingy:53 board requires some delays before on board sensors * could be accessed after power up. In particular bme680 and bmm150 sensors require, @@ -34,52 +29,20 @@ BUILD_ASSERT(CONFIG_THINGY53_INIT_PRIORITY < CONFIG_SENSOR_INIT_PRIORITY, "CONFIG_THINGY53_INIT_PRIORITY must be less than CONFIG_SENSOR_INIT_PRIORITY"); #endif -static void enable_cpunet(void) -{ -#if !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) - /* Retain nRF5340 Network MCU in Secure domain (bus - * accesses by Network MCU will have Secure attribute set). - */ - NRF_SPU->EXTDOMAIN[0].PERM = 1 << 4; -#endif /* !CONFIG_TRUSTED_EXECUTION_NONSECURE */ - -#if !defined(CONFIG_TRUSTED_EXECUTION_SECURE) - /* - * Building Zephyr with CONFIG_TRUSTED_EXECUTION_SECURE=y implies - * building also a Non-Secure image. The Non-Secure image will, in - * this case do the remainder of actions to properly configure and - * boot the Network MCU. - */ - - /* Release the Network MCU, 'Release force off signal' */ - nrf_reset_network_force_off(NRF_RESET, false); - - LOG_DBG("Network MCU released."); -#endif /* !CONFIG_TRUSTED_EXECUTION_SECURE */ -} - +#if !defined(CONFIG_TRUSTED_EXECUTION_SECURE) && defined(CONFIG_SENSOR) static int setup(void) { - -#if !defined(CONFIG_TRUSTED_EXECUTION_SECURE) - if (IS_ENABLED(CONFIG_SENSOR)) { - /* Initialization chain of Thingy:53 board requires some delays before on board - * sensors could be accessed after power up. In particular bme680 and bmm150 - * sensors require, 2ms and 1ms power on delay respectively. In order not to sum - * delays, common delay is introduced in the board start up file. This code is - * executed after sensors are powered up and before their initialization. - * It's ensured by build asserts at the beginning of this file. - */ - k_msleep(2); - } - -#endif /* !CONFIG_TRUSTED_EXECUTION_SECURE */ - - if (IS_ENABLED(CONFIG_BOARD_ENABLE_CPUNET)) { - enable_cpunet(); - } + /* Initialization chain of Thingy:53 board requires some delays before on board + * sensors could be accessed after power up. In particular bme680 and bmm150 + * sensors require, 2ms and 1ms power on delay respectively. In order not to sum + * delays, common delay is introduced in the board start up file. This code is + * executed after sensors are powered up and before their initialization. + * It's ensured by build asserts at the beginning of this file. + */ + k_msleep(2); return 0; } SYS_INIT(setup, POST_KERNEL, CONFIG_THINGY53_INIT_PRIORITY); +#endif /* !CONFIG_TRUSTED_EXECUTION_SECURE && CONFIG_SENSOR */ diff --git a/boards/nordic/thingy53/thingy53_nrf5340_common.dtsi b/boards/nordic/thingy53/thingy53_nrf5340_common.dtsi index 26afaee2b0e..926d6377f5c 100644 --- a/boards/nordic/thingy53/thingy53_nrf5340_common.dtsi +++ b/boards/nordic/thingy53/thingy53_nrf5340_common.dtsi @@ -5,6 +5,7 @@ */ #include "thingy53_nrf5340_common-pinctrl.dtsi" #include +#include / { chosen { @@ -90,7 +91,7 @@ regulator-boot-on; }; - vbatt { + vbatt: vbatt { compatible = "voltage-divider"; io-channels = <&adc 2>; output-ohms = <180000>; @@ -98,6 +99,14 @@ power-gpios = <&gpio0 16 0>; }; + fuel_gauge: fuel_gauge { + compatible = "zephyr,fuel-gauge-composite"; + battery-voltage = <&vbatt>; + device-chemistry = "lithium-ion-polymer"; + ocv-capacity-table-0 = ; + charge-full-design-microamp-hours = <1350000>; + }; + regulator_3v3: regulator-3v3-ctrl { compatible = "regulator-fixed"; regulator-name = "ncp114"; @@ -157,7 +166,19 @@ }; &adc { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; + + channel@2 { + reg = <2>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,vref-mv = <600>; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + zephyr,input-positive = ; + }; }; &gpiote { @@ -277,39 +298,6 @@ edge_connector_spi: &spi4 { pinctrl-names = "default", "sleep"; }; -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x00010000>; - }; - slot0_partition: partition@10000 { - label = "image-0"; - }; - slot0_ns_partition: partition@50000 { - label = "image-0-nonsecure"; - }; - slot1_partition: partition@80000 { - label = "image-1"; - }; - slot1_ns_partition: partition@c0000 { - label = "image-1-nonsecure"; - }; - scratch_partition: partition@f0000 { - label = "image-scratch"; - reg = <0x000f0000 0xa000>; - }; - storage_partition: partition@fa000 { - label = "storage"; - reg = <0x000fa000 0x00006000>; - }; - }; -}; - &ieee802154 { status = "okay"; }; @@ -323,26 +311,5 @@ zephyr_udc0: &usbd { }; }; -/ { - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_image: image@20000000 { - /* Zephyr image(s) memory */ - }; - - sram0_s: image_s@20000000 { - /* Secure image memory */ - }; - - sram0_ns: image_ns@20040000 { - /* Non-Secure image memory */ - }; - }; -}; - -/* Include partition configuration file */ -#include "thingy53_nrf5340_partition_conf.dtsi" +/* Include default memory partition configuration file */ +#include diff --git a/boards/nordic/thingy53/thingy53_nrf5340_cpuapp.dts b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp.dts index dd05a7a3981..d058f8da95b 100644 --- a/boards/nordic/thingy53/thingy53_nrf5340_cpuapp.dts +++ b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp.dts @@ -24,3 +24,15 @@ watchdog0 = &wdt0; }; }; + +&vregmain { + regulator-initial-mode = ; +}; + +&vregradio { + regulator-initial-mode = ; +}; + +&vregh { + status = "okay"; +}; diff --git a/boards/nordic/thingy53/thingy53_nrf5340_cpuapp.yaml b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp.yaml index fbc4eb33579..bc3d8de14b6 100644 --- a/boards/nordic/thingy53/thingy53_nrf5340_cpuapp.yaml +++ b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp.yaml @@ -13,7 +13,6 @@ supported: - i2c - pwm - watchdog - - usb_cdc - usb_device - netif:openthread vendor: nordic diff --git a/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.dts b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.dts index 293a36cf78d..84fb9fbfc94 100644 --- a/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.dts +++ b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.dts @@ -13,7 +13,7 @@ compatible = "nordic,thingy53-nrf5340-cpuapp"; chosen { - zephyr,sram = &sram0_ns; + zephyr,sram = &sram0_ns_app; zephyr,flash = &flash0; zephyr,code-partition = &slot0_ns_partition; }; @@ -22,3 +22,15 @@ watchdog0 = &wdt0; }; }; + +&vregmain { + regulator-initial-mode = ; +}; + +&vregradio { + regulator-initial-mode = ; +}; + +&vregh { + status = "okay"; +}; diff --git a/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.yaml b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.yaml index b534406ea07..a48325cb57f 100644 --- a/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.yaml +++ b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.yaml @@ -13,7 +13,6 @@ supported: - i2c - pwm - watchdog - - usb_cdc - usb_device - netif:openthread vendor: nordic diff --git a/boards/nordic/thingy53/thingy53_nrf5340_cpunet.dts b/boards/nordic/thingy53/thingy53_nrf5340_cpunet.dts index 895803a8623..89e9f8c64e5 100644 --- a/boards/nordic/thingy53/thingy53_nrf5340_cpunet.dts +++ b/boards/nordic/thingy53/thingy53_nrf5340_cpunet.dts @@ -145,5 +145,5 @@ status = "okay"; }; -/* Include shared RAM configuration file */ -#include "thingy53_nrf5340_shared_sram_planning_conf.dtsi" +/* Include default shared RAM configuration file */ +#include diff --git a/boards/nordic/thingy53/thingy53_nrf5340_partition_conf.dtsi b/boards/nordic/thingy53/thingy53_nrf5340_partition_conf.dtsi deleted file mode 100644 index 6f5f8a2a6f9..00000000000 --- a/boards/nordic/thingy53/thingy53_nrf5340_partition_conf.dtsi +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (c) 2021 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* - * Default Flash planning for thingy53_nrf5340. - * - * Zephyr build for nRF5340 with ARM TrustZone-M support, - * implies building Secure and Non-Secure Zephyr images. - * - * Secure image will be placed, by default, in flash0 - * (or in slot0, if MCUboot is present). - * Secure image will use sram0 for system memory. - * - * Non-Secure image will be placed in slot0_ns, and use - * sram0_ns for system memory. - * - * Note that the Secure image only requires knowledge of - * the beginning of the Non-Secure image (not its size). - */ - -&slot0_partition { - reg = <0x00010000 0x40000>; -}; - -&slot0_ns_partition { - reg = <0x00050000 0x30000>; -}; - -&slot1_partition { - reg = <0x00080000 0x40000>; -}; - -&slot1_ns_partition { - reg = <0x000c0000 0x30000>; -}; - -/* Default SRAM planning when building for nRF5340 with - * ARM TrustZone-M support - * - Lowest 256 kB SRAM allocated to Secure image (sram0_s) - * - Middle 192 kB allocated to Non-Secure image (sram0_ns) - * - Upper 64 kB SRAM allocated as Shared memory (sram0_shared) - * (see nrf5340_shared_sram_planning_conf.dts) - */ -&sram0_image { - reg = <0x20000000 DT_SIZE_K(448)>; -}; - -&sram0_s { - reg = <0x20000000 0x40000>; -}; - -&sram0_ns { - reg = <0x20040000 0x30000>; -}; - -/* Include shared RAM configuration file */ -#include "thingy53_nrf5340_shared_sram_planning_conf.dtsi" diff --git a/boards/nordic/thingy53/thingy53_nrf5340_shared_sram_planning_conf.dtsi b/boards/nordic/thingy53/thingy53_nrf5340_shared_sram_planning_conf.dtsi deleted file mode 100644 index 726b169eca1..00000000000 --- a/boards/nordic/thingy53/thingy53_nrf5340_shared_sram_planning_conf.dtsi +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2021 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* Default shared SRAM planning when building for nRF5340. - * This file is included by both nRF5340 CPUAPP (Application MCU) - * and nRF5340 CPUNET (Network MCU). - * - 64 kB SRAM allocated as Shared memory (sram0_shared) - * - Region defined after the image SRAM of Application MCU - */ - -/ { - chosen { - /* shared memory reserved for the inter-processor communication */ - zephyr,ipc_shm = &sram0_shared; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_shared: memory@20070000 { - /* SRAM allocated to shared memory */ - reg = <0x20070000 0x10000>; - }; - }; -}; diff --git a/boards/nuvoton/npcm400_evb/Kconfig.defconfig b/boards/nuvoton/npcm400_evb/Kconfig.defconfig new file mode 100644 index 00000000000..058d1ef0ad0 --- /dev/null +++ b/boards/nuvoton/npcm400_evb/Kconfig.defconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Nuvoton Technology Corporation. +# +# SPDX-License-Identifier: Apache-2.0 + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 diff --git a/boards/nuvoton/npcm400_evb/Kconfig.npcm400_evb b/boards/nuvoton/npcm400_evb/Kconfig.npcm400_evb new file mode 100644 index 00000000000..068f536f3f9 --- /dev/null +++ b/boards/nuvoton/npcm400_evb/Kconfig.npcm400_evb @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NPCM400_EVB + select SOC_NPCM400 diff --git a/boards/nuvoton/npcm400_evb/board.cmake b/boards/nuvoton/npcm400_evb/board.cmake new file mode 100644 index 00000000000..1b63186eb8e --- /dev/null +++ b/boards/nuvoton/npcm400_evb/board.cmake @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nuvoton Technology Corporation. +# +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=npcm400" "--speed=4000") +board_runner_args(jlink "--file=./build/zephyr/${CONFIG_KERNEL_BIN_NAME}.npcm.bin") +board_runner_args(jlink "--reset-after-load") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nuvoton/npcm400_evb/board.yml b/boards/nuvoton/npcm400_evb/board.yml new file mode 100644 index 00000000000..1a428cc5fe1 --- /dev/null +++ b/boards/nuvoton/npcm400_evb/board.yml @@ -0,0 +1,5 @@ +board: + name: npcm400_evb + vendor: nuvoton + socs: + - name: npcm400 diff --git a/boards/nuvoton/npcm400_evb/doc/index.rst b/boards/nuvoton/npcm400_evb/doc/index.rst new file mode 100644 index 00000000000..d5d9ee550c2 --- /dev/null +++ b/boards/nuvoton/npcm400_evb/doc/index.rst @@ -0,0 +1,108 @@ +.. _npcm400_evb: + +Nuvoton NPCM400_EVB +#################### + +Overview +******** + +The NPCM400_EVB kit is a development platform to evaluate the +Nuvoton NPCM4 series microcontrollers. This board needs to be mated with +part number NPCM400 Satellite Management Controller (SMC). + +.. image:: npcm400_evb.webp + :align: center + :alt: NPCM400 Evaluation Board + +Hardware +******** + +- ARM Cortex-M4F Processor +- Core clock up to 100 MHz +- 1MB Integrated Flash +- 32KB cache for XIP and Data +- 768 KB RAM and 64 KB boot ROM +- ADC & GPIO headers +- UART0 and UART1 +- I2C/I3C +- RMII +- USB2.0 Device +- USB1.1 Host +- Secure Boot is supported + +Supported Features +================== + +The following features are supported: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc controller | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c port/controller | ++-----------+------------+-------------------------------------+ +| I3C | on-chip | i3c port/controller | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/nuvoton/npcm400_evb/npcm400_evb_defconfig` + +Connections and IOs +=================== + +Nuvoton to provide the schematic for this board. + +Serial Port +=========== + +UART0 is configured for serial logs. The default serial setup is 115200 8N1. + +Programming and Debugging +************************* + +This board comes with a Cortex ETM port which facilitates tracing and debugging +using a single physical connection. In addition, it comes with sockets for +JTAG-only sessions. + +Flashing +======== + +If the correct headers are installed, this board supports J-TAG. + +To flash with J-TAG, install the drivers for your programmer, for example: +SEGGER J-link's drivers are at https://www.segger.com/downloads/jlink/ + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: npcm400_evb + :goals: flash + +Open a serial terminal, and you should see the following message in the terminal: + +.. code-block:: console + + Hello World! npcm400_evb/npcm400 + +Debugging +========= + +Use JTAG/SWD with a J-Link + +References +********** diff --git a/boards/nuvoton/npcm400_evb/doc/npcm400_evb.webp b/boards/nuvoton/npcm400_evb/doc/npcm400_evb.webp new file mode 100644 index 00000000000..479e7c5cec6 Binary files /dev/null and b/boards/nuvoton/npcm400_evb/doc/npcm400_evb.webp differ diff --git a/boards/nuvoton/npcm400_evb/npcm400_evb.dts b/boards/nuvoton/npcm400_evb/npcm400_evb.dts new file mode 100644 index 00000000000..2211799235c --- /dev/null +++ b/boards/nuvoton/npcm400_evb/npcm400_evb.dts @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2024 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + model = "Nuvoton NPCM400 evaluation board"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + aliases { + }; + +}; diff --git a/boards/nuvoton/npcm400_evb/npcm400_evb.yaml b/boards/nuvoton/npcm400_evb/npcm400_evb.yaml new file mode 100644 index 00000000000..c9628e4553d --- /dev/null +++ b/boards/nuvoton/npcm400_evb/npcm400_evb.yaml @@ -0,0 +1,16 @@ +# +# Copyright (c) 2024 Nuvoton Technology Corporation. +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: npcm400_evb +name: Nuvoton NPCM400 EVB +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +ram: 768 +flash: 1024 +vendor: nuvoton diff --git a/boards/nuvoton/npcm400_evb/npcm400_evb_defconfig b/boards/nuvoton/npcm400_evb/npcm400_evb_defconfig new file mode 100644 index 00000000000..687f322919b --- /dev/null +++ b/boards/nuvoton/npcm400_evb/npcm400_evb_defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2024 Nuvoton Technology Corporation. +# +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SRAM_VECTOR_TABLE=y + +# General Kernel Options +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 +CONFIG_XIP=y + +# UART Driver +CONFIG_SERIAL=n + +# Console Driver +CONFIG_CONSOLE=n +CONFIG_UART_CONSOLE=n diff --git a/boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb.dts b/boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb.dts index b90d94b0c9e..2993b816956 100644 --- a/boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb.dts +++ b/boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb.dts @@ -26,7 +26,6 @@ i2c-0 = &i2c0_0; watchdog0 = &twd0; peci-0 = &peci0; - spi-flash0 = &int_flash; kscan0 = &kscan_input; }; diff --git a/boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb.dts b/boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb.dts index a1c6d72403b..34a8cc9de74 100644 --- a/boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb.dts +++ b/boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb.dts @@ -28,8 +28,6 @@ i2c-0 = &i2c0_0; watchdog0 = &twd0; peci-0 = &peci0; - /* For samples/drivers/spi_flash */ - spi-flash0 = &int_flash; /* For kscan test suites */ kscan0 = &kscan_input; }; diff --git a/boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb.dts b/boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb.dts index 841883cc38c..fe186dca262 100644 --- a/boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb.dts +++ b/boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb.dts @@ -31,8 +31,6 @@ /* For watchdog sample */ watchdog0 = &twd0; peci-0 = &peci0; - /* For samples/drivers/spi_flash */ - spi-flash0 = &int_flash; /* For kscan test suites */ kscan0 = &kscan_input; }; diff --git a/boards/nuvoton/numaker_m2l31ki/doc/index.rst b/boards/nuvoton/numaker_m2l31ki/doc/index.rst index 3e2c8b9550b..8c2e8b8bf77 100644 --- a/boards/nuvoton/numaker_m2l31ki/doc/index.rst +++ b/boards/nuvoton/numaker_m2l31ki/doc/index.rst @@ -58,7 +58,7 @@ Building and Flashing Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. On board debugger Nu-link2 can emulate UART0 as a virtual COM port over usb, To enable this, set ISW1 DIP switch 1-3 (TXD RXD VOM) to ON. @@ -77,7 +77,7 @@ run a serial host program to connect with your board. For example: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nuvoton/numaker_pfm_m467/doc/index.rst b/boards/nuvoton/numaker_pfm_m467/doc/index.rst index 483ab34b623..6620acce559 100644 --- a/boards/nuvoton/numaker_pfm_m467/doc/index.rst +++ b/boards/nuvoton/numaker_pfm_m467/doc/index.rst @@ -62,7 +62,7 @@ Building and Flashing Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. On board debugger Nu-link2 can emulate UART0 as a virtual COM port over usb, To enable this, set ISW1 DIP switch 1-3 (TXD RXD VOM) to ON. @@ -81,7 +81,7 @@ run a serial host program to connect with your board. For example: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467.dts b/boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467.dts index 69b0aa3fafc..bd849f0ab1d 100644 --- a/boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467.dts +++ b/boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467.dts @@ -65,8 +65,6 @@ }; &scc { - /* For USB 1.1 Host/Device/OTG, configure to 192MHz, which can generate necessary 48MHz. */ - /* For USB 2.0 Host/Device/OTG or no USB application, comment out to use default. */ core-clock = <192000000>; }; @@ -122,7 +120,7 @@ status = "okay"; }; -/* On enabled, 'core-clock', as above, is required to to be 192MHz. */ +/* On enabled, usbd is required to be clocked in 48MHz. */ zephyr_udc0: &usbd { pinctrl-0 = <&usbd_default>; pinctrl-names = "default"; diff --git a/boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467.yaml b/boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467.yaml index d668f51facb..a7e26960ae6 100644 --- a/boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467.yaml +++ b/boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467.yaml @@ -13,4 +13,5 @@ ram: 512 flash: 1024 supported: - gpio + - usbd vendor: nuvoton diff --git a/boards/nuvoton/numaker_pfm_m487/doc/index.rst b/boards/nuvoton/numaker_pfm_m487/doc/index.rst index 323be5f5923..180ae3c5665 100644 --- a/boards/nuvoton/numaker_pfm_m487/doc/index.rst +++ b/boards/nuvoton/numaker_pfm_m487/doc/index.rst @@ -61,7 +61,7 @@ Building and Flashing Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. On board debugger Nu-link-Me can emulate UART0 as a virtual COM port over usb, To enable this, set ISW1 DIP switch 1-3 (TXD RXD VOM) to ON. @@ -80,7 +80,7 @@ run a serial host program to connect with your board. For example: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/common/opensda-debug.rst b/boards/nxp/common/opensda-debug.rst new file mode 100644 index 00000000000..caf1cdc6727 --- /dev/null +++ b/boards/nxp/common/opensda-debug.rst @@ -0,0 +1,39 @@ +:orphan: + +.. nxp-opensda-probes + +A debug probe is used for both flashing and debugging the board. This board has +an :ref:`opensda-onboard-debug-probe`. The default firmware present on this +probe is the :ref:`opensda-daplink-onboard-debug-probe`. + +Based on the host tool installed, please use the following instructions +to setup your debug probe: + +* :ref:`jlink-debug-host-tools`: `Using J-Link on NXP OpenSDA Boards`_ +* :ref:`linkserver-debug-host-tools`: `Using DAPLink on NXP OpenSDA Boards`_ +* :ref:`pyocd-debug-host-tools`: `Using DAPLink on NXP OpenSDA Boards`_ + +Using DAPLink on NXP OpenSDA Boards +----------------------------------- + +1. If the debug firmware has been modified, follow the instructions provided at + :ref:`opensda-daplink-onboard-debug-probe` to reprogram the default debug + probe firmware on this board. +#. Ensure the SWD isolation jumpers are populated + +Using J-Link on NXP OpenSDA Boards +---------------------------------- + +There are two options: the onboard debug circuit can be updated with Segger +J-Link firmware, or a :ref:`jlink-external-debug-probe` can be attached to the +board. + +To update the onboard debug circuit, please do the following: + +1. If the debug firmware has been modified, follow the instructions provided at + :ref:`opensda-jlink-onboard-debug-probe` to reprogram the default debug + probe firmware on this board. +#. Ensure the SWD isolation jumpers are removed. + +To attach an external J-Link probe, ensure the SWD isolation jumpers are +removed, and connect the external probe to the JTAG/SWD header. diff --git a/boards/nxp/common/rt1xxx-lpclink2-debug.rst b/boards/nxp/common/rt1xxx-lpclink2-debug.rst new file mode 100644 index 00000000000..dae35e4791b --- /dev/null +++ b/boards/nxp/common/rt1xxx-lpclink2-debug.rst @@ -0,0 +1,45 @@ +:orphan: + +.. rt1xxx-lpclink2-probes + +A debug probe is used for both flashing and debugging the board. This board has +an :ref:`lpc-link2-onboard-debug-probe`. The default firmware present on this +probe is the :ref:`lpclink2-daplink-onboard-debug-probe`. + +Based on the host tool installed, please use the following instructions +to setup your debug probe: + +* :ref:`jlink-debug-host-tools`: + `Using J-Link with LPC-Link2 Probe`_ +* :ref:`linkserver-debug-host-tools`: + `Using CMSIS-DAP with LPC-Link2 Probe`_ +* :ref:`pyocd-debug-host-tools`: + `Using CMSIS-DAP with LPC-Link2 Probe`_ + +Using CMSIS-DAP with LPC-Link2 Probe +------------------------------------ + +1. Follow the instructions provided at + :ref:`lpclink2-cmsis-onboard-debug-probe` to reprogram the default debug + probe firmware on this board. +#. Ensure the SWD isolation jumpers are populated + +Using J-Link with LPC-Link2 Probe +--------------------------------- + +There are two options: the onboard debug circuit can be updated with Segger +J-Link firmware, or a :ref:`jlink-external-debug-probe` can be attached to the +EVK. + +To update the onboard debug circuit, please do the following: + +1. Switch the power source for the EVK to a different source than the + debug USB, as the J-Link firmware does not power the EVK via the + debug USB. +#. Follow the instructions provided at + :ref:`lpclink2-jlink-onboard-debug-probe` to reprogram the default debug + probe firmware on this board. +#. Ensure the SWD isolation jumpers are populated. + +To attach an external J-Link probe, ensure the SWD isolation jumpers are +removed, then connect the probe to the external JTAG/SWD header diff --git a/boards/nxp/frdm_k22f/doc/index.rst b/boards/nxp/frdm_k22f/doc/index.rst index f0f98048561..2e5ea18aab8 100644 --- a/boards/nxp/frdm_k22f/doc/index.rst +++ b/boards/nxp/frdm_k22f/doc/index.rst @@ -26,7 +26,7 @@ MCUs. Hardware ******** -- MK22FN512VLH12 (120 MHz, 1 MB flash memory, 256 KB RAM, low-power, +- MK22FN512VLH12 (120 MHz, 512 KB flash memory, 128 KB RAM, low-power, crystal-less USB, and 64 pin Low profile Quad Flat Package (LQFP)) - Dual role USB interface with micro-B USB connector - RGB LED @@ -237,7 +237,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -255,7 +255,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/frdm_k22f/frdm_k22f.dts b/boards/nxp/frdm_k22f/frdm_k22f.dts index 587aaa65ee1..fd36a8285fe 100644 --- a/boards/nxp/frdm_k22f/frdm_k22f.dts +++ b/boards/nxp/frdm_k22f/frdm_k22f.dts @@ -1,12 +1,13 @@ /* * Copyright (c) 2018 Prevas A/S + * Copyright 2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ /dts-v1/; -#include +#include #include #include "frdm_k22f-pinctrl.dtsi" #include @@ -33,6 +34,7 @@ zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &uart1; zephyr,console = &uart1; zephyr,shell-uart = &uart1; zephyr,uart-pipe = &uart1; @@ -203,23 +205,23 @@ zephyr_udc0: &usbotg { boot_partition: partition@0 { label = "mcuboot"; - reg = <0x00000000 0x00010000>; + reg = <0x00000000 DT_SIZE_K(64)>; read-only; }; - /* Note slot 0 has one additional sector, - * this is intended for use with the swap move algorithm + /* The MCUBoot swap-move algorithm uses the last 3 sectors + * of the primary slot0 for swap status and move. */ slot0_partition: partition@10000 { label = "image-0"; - reg = <0x00010000 0x00028800>; + reg = <0x00010000 (DT_SIZE_K(180) + DT_SIZE_K(6))>; }; - slot1_partition: partition@38800 { + slot1_partition: partition@3E800 { label = "image-1"; - reg = <0x00038800 0x00028000>; + reg = <0x0003E800 DT_SIZE_K(180)>; }; - storage_partition: partition@60800 { + storage_partition: partition@6B800 { label = "storage"; - reg = <0x00060800 0x0001f800>; + reg = <0x0006B800 DT_SIZE_K(82)>; }; }; diff --git a/boards/nxp/frdm_k64f/doc/index.rst b/boards/nxp/frdm_k64f/doc/index.rst index 1c240ef400f..17af8d4cf29 100644 --- a/boards/nxp/frdm_k64f/doc/index.rst +++ b/boards/nxp/frdm_k64f/doc/index.rst @@ -309,7 +309,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -327,7 +327,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/frdm_k64f/frdm_k64f.dts b/boards/nxp/frdm_k64f/frdm_k64f.dts index 4c42385a794..7fbc1943ec9 100644 --- a/boards/nxp/frdm_k64f/frdm_k64f.dts +++ b/boards/nxp/frdm_k64f/frdm_k64f.dts @@ -233,23 +233,23 @@ zephyr_udc0: &usbotg { boot_partition: partition@0 { label = "mcuboot"; - reg = <0x00000000 0x00010000>; + reg = <0x00000000 DT_SIZE_K(64)>; read-only; }; - /* Note slot 0 has one additional sector, - * this is intended for use with the swap move algorithm + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. */ slot0_partition: partition@10000 { label = "image-0"; - reg = <0x00010000 0x00069000>; + reg = <0x00010000 (DT_SIZE_K(416) + DT_SIZE_K(8))>; }; - slot1_partition: partition@79000 { + slot1_partition: partition@7a000 { label = "image-1"; - reg = <0x00079000 0x00068000>; + reg = <0x0007a000 DT_SIZE_K(416)>; }; - storage_partition: partition@e1000 { + storage_partition: partition@e2000 { label = "storage"; - reg = <0x000e1000 0x0001f000>; + reg = <0x000e2000 DT_SIZE_K(120)>; }; }; }; @@ -272,7 +272,7 @@ zephyr_udc0: &usbotg { compatible = "microchip,ksz8081"; reg = <0>; status = "okay"; - mc,interface-type = "rmii-25MHz"; + microchip,interface-type = "rmii-25MHz"; }; }; diff --git a/boards/nxp/frdm_k82f/doc/index.rst b/boards/nxp/frdm_k82f/doc/index.rst index f306dc6dada..9903e1b4493 100644 --- a/boards/nxp/frdm_k82f/doc/index.rst +++ b/boards/nxp/frdm_k82f/doc/index.rst @@ -194,7 +194,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -212,7 +212,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/frdm_k82f/frdm_k82f.dts b/boards/nxp/frdm_k82f/frdm_k82f.dts index 44b88975f4d..d2f4ed51457 100644 --- a/boards/nxp/frdm_k82f/frdm_k82f.dts +++ b/boards/nxp/frdm_k82f/frdm_k82f.dts @@ -27,7 +27,6 @@ sw1 = &user_button_1; magn0 = &fxos8700; accel0 = &fxos8700; - spi-flash0 = &mx25u32; }; chosen { @@ -40,6 +39,7 @@ zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &lpuart4; zephyr,console = &lpuart4; zephyr,shell-uart = &lpuart4; zephyr,uart-pipe = &lpuart4; @@ -159,14 +159,14 @@ boot_partition: partition@0 { label = "mcuboot"; - reg = <0x0 DT_SIZE_K(48)>; + reg = <0x0 DT_SIZE_K(44)>; }; - /* Note slot 0 has one additional sector, - * this is intended for use with the swap move algorithm + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. */ - slot0_partition: partition@c000 { + slot0_partition: partition@b000 { label = "image-0"; - reg = <0xc000 DT_SIZE_K(100)>; + reg = <0xb000 (DT_SIZE_K(96) + DT_SIZE_K(8))>; }; slot1_partition: partition@25000 { label = "image-1"; diff --git a/boards/nxp/frdm_ke15z/doc/index.rst b/boards/nxp/frdm_ke15z/doc/index.rst index fd1dec9bc67..772de4f8678 100644 --- a/boards/nxp/frdm_ke15z/doc/index.rst +++ b/boards/nxp/frdm_ke15z/doc/index.rst @@ -129,7 +129,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -147,7 +147,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/frdm_ke17z/Kconfig.frdm_ke17z b/boards/nxp/frdm_ke17z/Kconfig.frdm_ke17z new file mode 100644 index 00000000000..a6285f73c3e --- /dev/null +++ b/boards/nxp/frdm_ke17z/Kconfig.frdm_ke17z @@ -0,0 +1,7 @@ +# FRDM-KE17Z board configuration +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FRDM_KE17Z + select SOC_MKE17Z7 + select SOC_PART_NUMBER_MKE17Z256VLL7 diff --git a/boards/nxp/frdm_ke17z/board.cmake b/boards/nxp/frdm_ke17z/board.cmake new file mode 100644 index 00000000000..9599e8d3fe6 --- /dev/null +++ b/boards/nxp/frdm_ke17z/board.cmake @@ -0,0 +1,8 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(linkserver "--device=MKE17Z256xxx7:FRDM-KE17Z") +board_runner_args(jlink "--device=MKE17Z256xxx7" "--reset-after-load") + +include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nxp/frdm_ke17z/board.yml b/boards/nxp/frdm_ke17z/board.yml new file mode 100644 index 00000000000..a6b72f27f20 --- /dev/null +++ b/boards/nxp/frdm_ke17z/board.yml @@ -0,0 +1,5 @@ +board: + name: frdm_ke17z + vendor: nxp + socs: + - name: mke17z7 diff --git a/boards/nxp/frdm_ke17z/doc/frdmke17z.webp b/boards/nxp/frdm_ke17z/doc/frdmke17z.webp new file mode 100644 index 00000000000..0110e73bd24 Binary files /dev/null and b/boards/nxp/frdm_ke17z/doc/frdmke17z.webp differ diff --git a/boards/nxp/frdm_ke17z/doc/index.rst b/boards/nxp/frdm_ke17z/doc/index.rst new file mode 100644 index 00000000000..1f15fc99fb9 --- /dev/null +++ b/boards/nxp/frdm_ke17z/doc/index.rst @@ -0,0 +1,214 @@ +.. _frdm_ke17z: + +NXP FRDM-KE17Z +############## + +Overview +******** + +The FRDM-KE17Z is a development board for NXP Kinetis KE1xZ 32-bit +MCU-based platforms. The FRDM-KE17Z contains a robust TSI module +with up to 50 channels which makes this board highly flexible +for touch keys. Offers options for serial +communication, flash programming, and run-control debugging. + +.. figure:: frdmke17z.webp + :align: center + :alt: FRDM-KE17Z + + FRDM-KE17Z (Credit: NXP) + +Hardware +******** + +- MKE17Z256VLL7 MCU (up to 72 MHz, 256 KB flash memory, 48 KB SRAM, + and 100 Low profile Quad Flat Package (LQFP)) +- 3.3 V or 5 V MCU operation +- 6-axis FXOS8700CQ digital accelerometer +- 3-axis digital angular rate gyroscope +- One RGB LED +- Two user push-buttons +- Thermistor +- Two capacitive touchpads +- Flex I/O pin header + +For more information about the KE1xZ SoC and the FRDM-KE17Z board, see +these NXP reference documents: + +- `FRDM-KE17Z Website`_ +- `FRDM-KE17Z User Guide`_ +- `FRDM-KE17Z Reference Manual`_ +- `FRDM-KE17Z Datasheet`_ + +Supported Features +================== + +The frdm_ke17z board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINCTRL | on-chip | pinctrl | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| LPTMR | on-chip | counter | ++-----------+------------+-------------------------------------+ +| UART | on-chip | uart | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | dma | ++-----------+------------+-------------------------------------+ +| FTM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| ACMP | on-chip | sensor | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/nxp/frdm_ke17z/frdm_ke17z_defconfig`. + +Other hardware features are not currently supported by the port. + +System Clock +============ + +The KE17Z SoC is configured to run at 48 MHz using the FIRC. + +Serial Port +=========== + +The KE17Z SoC has three UARTs. UART0 is configured for the console. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use Linkserver. + +Early versions of this board have an outdated version of the OpenSDA bootloader +and require an update. Please see the `DAPLink Bootloader Update`_ page for +instructions to update from the CMSIS-DAP bootloader to the DAPLink bootloader. + +Option 1: Linkserver +-------------------- + +Install the :ref:`linkserver-debug-host-tools` and make sure they are in your +search path. LinkServer works with the default CMSIS-DAP firmware included in +the on-board debugger. + + Linkserver is the default for this board, ``west flash`` and ``west debug`` will + call the linkserver runner. + +.. code-block:: console + + west flash + + +External JLink: :ref:`jlink-external-debug-probe` +------------------------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +Attach a J-Link 10-pin connector to J14. Check that jumpers J8 and J9 are +**off** (they are on by default when boards ship from the factory) to ensure +SWD signals are disconnected from the OpenSDA microcontroller. +Use the ``-r jlink`` option with west to use the jlink runner. + +.. code-block:: console + + west flash -r jlink + +Configuring a Console +===================== + +Regardless of your choice in debug probe, we will use the OpenSDA +microcontroller as a usb-to-serial adapter for the serial console. + +Connect a USB cable from your PC to J6. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_ke17z + :goals: flash + +Open a serial terminal, reset the board (press the SW1 button), and you should +see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build xxxxxxxxxxxx *** + Hello World! frdm_ke17z/mke17z7 + +Debugging +========= + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_ke17z + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build xxxxxxxxxxxx *** + Hello World! frdm_ke17z/mke17z7 + +.. _FRDM-KE17Z Website: + https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/freedom-development-platform-for-72mhz-ke17z-ke13z-ke12z-mcus:FRDM-KE17Z + +.. _FRDM-KE17Z User Guide: + https://www.nxp.com/docs/en/user-guide/KE17ZHDG.pdf + +.. _FRDM-KE17Z Reference Manual: + https://www.nxp.com/docs/en/reference-manual/KE1xZP100M72SF1RM.pdf + +.. _FRDM-KE17Z Datasheet: + https://www.nxp.com/docs/en/data-sheet/KE1xZP100M72SF1.pdf + +.. _DAPLink Bootloader Update: + https://os.mbed.com/blog/entry/DAPLink-bootloader-update/ + +.. _OpenSDA DAPLink FRDM-KE17Z Firmware: + https://www.nxp.com/design/design-center/software/sensor-toolbox/opensda-serial-and-debug-adapter:OPENSDA?tid=vanOpenSDA + +.. _linkserver-debug-host-tools: + https://www.nxp.com/lgfiles/updates/mcuxpresso/LinkServer_1.5.30.exe + +.. _OpenSDA J-Link Firmware for FRDM-KE17Z: + https://www.segger.com/downloads/jlink/OpenSDA_FRDM-KE17Z diff --git a/boards/nxp/frdm_ke17z/frdm_ke17z-pinctrl.dtsi b/boards/nxp/frdm_ke17z/frdm_ke17z-pinctrl.dtsi new file mode 100644 index 00000000000..fc9cbcfa44e --- /dev/null +++ b/boards/nxp/frdm_ke17z/frdm_ke17z-pinctrl.dtsi @@ -0,0 +1,68 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +#include + +&pinctrl { + adc0_default: adc0_default { + group0 { + pinmux = ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + + lpuart0_default: lpuart0_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + + ftm2_default: ftm2_default { + group0 { + pinmux = , + , + ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + + lpi2c0_default: lpi2c0_default { + group0 { + pinmux = , + ; + bias-pull-up; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + + flexio_pwm_default: flexio_pwm_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + + lpspi0_default: lpspi0_default { + group0 { + pinmux = , + , + , + ; + bias-pull-up; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; +}; diff --git a/boards/nxp/frdm_ke17z/frdm_ke17z.dts b/boards/nxp/frdm_ke17z/frdm_ke17z.dts new file mode 100644 index 00000000000..46d5ba94c71 --- /dev/null +++ b/boards/nxp/frdm_ke17z/frdm_ke17z.dts @@ -0,0 +1,177 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "frdm_ke17z-pinctrl.dtsi" +#include +#include + +/ { + model = "NXP Freedom KE17Z board"; + compatible = "nxp,frdm-ke17z", "nxp,ke17z", "nxp,mke17z7"; + + aliases { + watchdog0 = &wdog; + led0 = &red_led; + led1 = &green_led; + led2 = &blue_led; + sw0 = &user_button_0; + sw1 = &user_button_1; + pwm-led0 = &red_pwm_led; + pwm-led1 = &green_pwm_led; + pwm-led2 = &blue_pwm_led; + }; + + chosen { + zephyr,sram = &sram_u; + zephyr,flash = &flash0; + zephyr,console = &lpuart0; + zephyr,shell-uart = &lpuart0; + }; + + leds { + compatible = "gpio-leds"; + red_led: led_0 { + gpios = <&gpiod 10 GPIO_ACTIVE_LOW>; + label = "RGB RED"; + }; + green_led: led_1 { + gpios = <&gpiod 11 GPIO_ACTIVE_LOW>; + label = "RGB GREEN"; + }; + blue_led: led_2 { + gpios = <&gpiod 12 GPIO_ACTIVE_LOW>; + label = "RGB BLUE"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + red_pwm_led: led_pwm_0 { + pwms = <&ftm2 0 PWM_HZ(20) PWM_POLARITY_INVERTED>; + label = "RED RGB PWM LED"; + }; + green_pwm_led: led_pwm_1 { + pwms = <&ftm2 1 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + label = "GREEN RGB PWM LED"; + }; + blue_pwm_led: led_pwm_2 { + pwms = <&ftm2 2 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + label = "BLUE RGB PWM LED"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button_0: button_0 { + label = "User SW2"; + gpios = <&gpiod 3 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + user_button_1: button_1 { + label = "User SW3"; + gpios = <&gpioe 14 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; +}; + +&idle { + min-residency-us = <1>; +}; + +&stop { + min-residency-us = <20000>; + exit-latency-us = <13>; +}; + +&lpuart0 { + dmas = <&edma 1 2>, <&edma 2 3>; + dma-names = "rx", "tx"; + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&lpuart0_default>; + pinctrl-names = "default"; +}; + +&adc0 { + status = "okay"; + sample-time = <12>; + vref-mv = <3300>; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; +}; + +&lpi2c0 { + status = "okay"; + pinctrl-0 = <&lpi2c0_default>; + pinctrl-names = "default"; +}; + +&gpiod { + status = "okay"; +}; + +&gpioe { + status = "okay"; +}; + +&ftm2 { + status = "okay"; + compatible = "nxp,kinetis-ftm-pwm"; + #pwm-cells = <3>; + clocks = <&scg KINETIS_SCG_SIRC_CLK>; + prescaler = <128>; + pinctrl-0 = <&ftm2_default>; + pinctrl-names = "default"; + clock-source = "system"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 DT_SIZE_K(44)>; + }; + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. + */ + slot0_partition: partition@b000 { + label = "image-0"; + reg = <0xb000 (DT_SIZE_K(98) + DT_SIZE_K(4))>; + }; + slot1_partition: partition@24800 { + label = "image-1"; + reg = <0x24800 DT_SIZE_K(98)>; + }; + storage_partition: partition@3d000 { + label = "storage"; + reg = <0x3d000 DT_SIZE_K(12)>; + }; + }; +}; + +&lpspi0 { + dmas = <&edma 0 14>, <&edma 1 15>; + dma-names = "rx", "tx"; + status = "okay"; + pinctrl-0 = <&lpspi0_default>; + pinctrl-names = "default"; +}; + +&edma { + status = "okay"; +}; + +&wdog { + status = "okay"; +}; diff --git a/boards/nxp/frdm_ke17z/frdm_ke17z.yaml b/boards/nxp/frdm_ke17z/frdm_ke17z.yaml new file mode 100644 index 00000000000..f4069357439 --- /dev/null +++ b/boards/nxp/frdm_ke17z/frdm_ke17z.yaml @@ -0,0 +1,21 @@ +identifier: frdm_ke17z +name: NXP FRDM-KE17Z +type: mcu +arch: arm +ram: 32 +flash: 256 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - counter + - gpio + - adc + - uart + - pwm + - i2c + - spi + - dma + - watchdog +vendor: nxp diff --git a/boards/nxp/frdm_ke17z/frdm_ke17z_defconfig b/boards/nxp/frdm_ke17z/frdm_ke17z_defconfig new file mode 100644 index 00000000000..906371815be --- /dev/null +++ b/boards/nxp/frdm_ke17z/frdm_ke17z_defconfig @@ -0,0 +1,19 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +# GPIO Controller +CONFIG_GPIO=y + +# Clock Control +CONFIG_CLOCK_CONTROL=y + +# Enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/nxp/frdm_ke17z512/Kconfig.frdm_ke17z512 b/boards/nxp/frdm_ke17z512/Kconfig.frdm_ke17z512 new file mode 100644 index 00000000000..0ac331398d2 --- /dev/null +++ b/boards/nxp/frdm_ke17z512/Kconfig.frdm_ke17z512 @@ -0,0 +1,6 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FRDM_KE17Z512 + select SOC_MKE17Z9 + select SOC_PART_NUMBER_MKE17Z512VLL9 diff --git a/boards/nxp/frdm_ke17z512/board.cmake b/boards/nxp/frdm_ke17z512/board.cmake new file mode 100644 index 00000000000..4c09a06e95e --- /dev/null +++ b/boards/nxp/frdm_ke17z512/board.cmake @@ -0,0 +1,11 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +board_runner_args(linkserver "--device=MKE17Z512xxx9:FRDM-KE17Z512") +board_runner_args(jlink "--device=MKE17Z512xxx9" "--reset-after-load") + +include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nxp/frdm_ke17z512/board.yml b/boards/nxp/frdm_ke17z512/board.yml new file mode 100644 index 00000000000..46839e065b1 --- /dev/null +++ b/boards/nxp/frdm_ke17z512/board.yml @@ -0,0 +1,5 @@ +board: + name: frdm_ke17z512 + vendor: nxp + socs: + - name: mke17z9 diff --git a/boards/nxp/frdm_ke17z512/doc/frdm_ke17z512.webp b/boards/nxp/frdm_ke17z512/doc/frdm_ke17z512.webp new file mode 100644 index 00000000000..d068f925763 Binary files /dev/null and b/boards/nxp/frdm_ke17z512/doc/frdm_ke17z512.webp differ diff --git a/boards/nxp/frdm_ke17z512/doc/index.rst b/boards/nxp/frdm_ke17z512/doc/index.rst new file mode 100644 index 00000000000..ab4948307da --- /dev/null +++ b/boards/nxp/frdm_ke17z512/doc/index.rst @@ -0,0 +1,216 @@ +.. _frdm_ke17z512: + +NXP FRDM-KE17Z512 +################## + +Overview +******** + +The FRDM-KE17Z512 is a development board for NXP Kinetis KE1xZ 32-bit +MCU-based platforms. The onboard OpenSDAv2 serial and debug adapter, +running an open source bootloader, offers options for serial +communication, flash programming, and run-control debugging. + +.. figure:: frdm_ke17z512.webp + :align: center + :alt: FRDM-KE17Z512 + + FRDM-KE17Z512 (Credit: NXP) + +Hardware +******** + +- MKE17Z512VLL9 MCU (up to 96 MHz, 512 KB flash memory, 96 KB RAM, + and 100 Low profile Quad Flat Package (LQFP)) +- 3.3 V or 5 V MCU operation +- 6-axis FXOS8700CQ digital accelerometer and magnetometer +- RGB LED +- Two user push-buttons +- Thermistor +- Arduino compatible I/O pin header +- OpenSDA on-board debugger +- Two Touch Electrodes + +For more information about the KE1xZ SoC and the FRDM-KE17Z512 board, see +these NXP reference documents: + +- `KE1xZ Website`_ +- `KE1xZ Fact Sheet`_ +- `KE1xZ Reference Manual`_ +- `FRDM-KE17Z512 Website`_ +- `FRDM-KE17Z512 Quick Start Guide`_ +- `FRDM-KE17Z512 Reference Manual`_ + +Supported Features +================== + +The frdm_ke17z512 board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| LPTMR | on-chip | counter | ++-----------+------------+-------------------------------------+ +| UART | on-chip | uart polling; | +| | | uart interrupt | ++-----------+------------+-------------------------------------+ +| FTM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | I2C | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | counter | ++-----------+------------+-------------------------------------+ +| ACMP | on-chip | sensor | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | dma | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +``boards/nxp/frdm_ke17z512/frdm_ke17z512_defconfig``. + +Other hardware features are not currently supported by the port. + +System Clock +============ + +The KE17Z9 SoC is configured to run at 48 MHz using the FIRC. + +Serial Port +=========== + +The KE17Z9 SoC has three LPUARTs. UART2 is configured for the console. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use Linkserver. + +Early versions of this board have an outdated version of the OpenSDA bootloader +and require an update. Please see the `DAPLink Bootloader Update`_ page for +instructions to update from the CMSIS-DAP bootloader to the DAPLink bootloader. + +Option 1: Linkserver +-------------------- + +Install the :ref:`linkserver-debug-host-tools` and make sure they are in your +search path. LinkServer works with the default CMSIS-DAP firmware included in +the on-board debugger. + +Linkserver is the default for this board, ``west flash`` and ``west debug`` will +call the linkserver runner. + +Option 2: :ref:`opensda-jlink-onboard-debug-probe` +-------------------------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program +the `Segger J-Link OpenSDA V2.1 Firmware`_. +Use the ``-r jlink`` option with west to use the jlink runner. + +.. code-block:: console + + west flash -r jlink + +Configuring a Console +===================== + +Regardless of your choice in debug probe, we will use the OpenSDA +microcontroller as a usb-to-serial adapter for the serial console. + +Connect a USB cable from your PC to J10. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_ke17z512 + :goals: flash + +Open a serial terminal, reset the board (press the SW1 button), and you should +see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v3.6.0-xxxx-gxxxxxxxxxxxx *** + Hello World! frdm_ke17z512/mke17z9 + +Debugging +========= + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_ke17z512 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v3.6.0-xxxx-gxxxxxxxxxxxx *** + Hello World! frdm_ke17z512/mke17z9 + +.. _FRDM-KE17Z512 Website: + https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/frdm-development-board-for-96-mhz-ke17z-ke13z-ke12z-with-512-kb-flash-mcus:FRDM-KE17Z512 + +.. _FRDM-KE17Z512 Quick Start Guide: + https://www.nxp.com/docs/en/quick-reference-guide/FRDMKE17Z512QSG.pdf + +.. _FRDM-KE17Z512 Reference Manual: + https://www.nxp.com/docs/en/reference-manual/KE1XZP100M96SF0RM.pdf + +.. _KE1xZ Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/ke-series-arm-cortex-m4-m0-plus/ke1xz-arm-cortex-m0-plus-5v-main-stream-mcu-with-nxp-touch-and-can-control:KE1xZ + +.. _KE1xZ Fact Sheet: + https://www.nxp.com/docs/en/fact-sheet/KE1xZMCUFAMFS.pdf + +.. _KE1xZ Reference Manual: + https://www.nxp.com/webapp/Download?colCode=KE1XZP100M72SF0RM + +.. _linkserver-debug-host-tools: + https://www.nxp.com/lgfiles/updates/mcuxpresso/LinkServer_1.5.30.exe + +.. _Segger J-Link OpenSDA V2.1 Firmware: + https://www.segger.com/downloads/jlink/OpenSDA_V2_1.bin + +.. _DAPLink Bootloader Update: + https://os.mbed.com/blog/entry/DAPLink-bootloader-update/ + +.. _jlink-debug-host-tools: + https://www.segger.com/downloads/jlink/JLink_Windows_V794_x86_64.exe diff --git a/boards/nxp/frdm_ke17z512/frdm_ke17z512-pinctrl.dtsi b/boards/nxp/frdm_ke17z512/frdm_ke17z512-pinctrl.dtsi new file mode 100644 index 00000000000..4c1570a16c1 --- /dev/null +++ b/boards/nxp/frdm_ke17z512/frdm_ke17z512-pinctrl.dtsi @@ -0,0 +1,88 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +#include + +&pinctrl { + adc0_default: adc0_default { + group0 { + pinmux = ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + + /* Configures pin routing and optionally pin electrical features. */ + lpuart2_default: lpuart2_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + + ftm2_default: ftm2_default { + group0 { + pinmux = , + , + ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + + lpi2c0_default: lpi2c0_default { + group0 { + pinmux = , + ; + bias-pull-up; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + + lpi2c1_default: lpi2c1_default { + group0 { + pinmux = , + ; + bias-pull-up; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + + uart1_default: uart1_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + + lpspi0_default: lpspi0_default { + group0 { + pinmux = , + , + , + ; + bias-pull-up; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + + flexio_pwm_default: flexio_pwm_default { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; +}; diff --git a/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts b/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts new file mode 100644 index 00000000000..4fa5c16df02 --- /dev/null +++ b/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts @@ -0,0 +1,195 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "frdm_ke17z512-pinctrl.dtsi" +#include +#include + +/ { + model = "NXP Freedom KE17Z512 board"; + compatible = "nxp,ke17z512", "nxp,mke17z9", "nxp,ke1xz"; + + chosen { + zephyr,sram = &sram_u; + zephyr,flash = &flash0; + zephyr,console = &lpuart2; + zephyr,shell-uart = &lpuart2; + }; + + aliases { + watchdog0 = &wdog; + led0 = &red_led; + led1 = &green_led; + led2 = &blue_led; + sw0 = &user_button_2; + sw1 = &user_button_3; + pwm-led0 = &red_pwm_led; + pwm-led1 = &green_pwm_led; + pwm-led2 = &blue_pwm_led; + }; + + leds { + compatible = "gpio-leds"; + red_led: led_0 { + gpios = <&gpiod 10 GPIO_ACTIVE_LOW>; + label = "Red LED"; + }; + green_led: led_1 { + gpios = <&gpiod 5 GPIO_ACTIVE_LOW>; + label = "Green LED"; + }; + blue_led: led_2 { + gpios = <&gpiod 12 GPIO_ACTIVE_LOW>; + label = "Blue LED"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + red_pwm_led: led_pwm_0 { + pwms = <&ftm2 0 PWM_HZ(20) PWM_POLARITY_INVERTED>; + label = "RED RGB PWM LED"; + }; + green_pwm_led: led_pwm_1 { + pwms = <&ftm2 3 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + label = "GREEN RGB PWM LED"; + }; + blue_pwm_led: led_pwm_2 { + pwms = <&ftm2 2 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + label = "BLUE RGB PWM LED"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button_2: button_0 { + label = "User SW2"; + gpios = <&gpioe 14 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + user_button_3: button_1 { + label = "User SW3"; + gpios = <&gpiod 3 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; +}; + +&idle { + min-residency-us = <1>; +}; + +&stop { + min-residency-us = <20000>; + exit-latency-us = <13>; +}; + +&lpuart2 { + dmas = <&edma 5 6>, <&edma 6 7>; + dma-names = "rx", "tx"; + status = "okay"; + pinctrl-0 = <&lpuart2_default>; + pinctrl-names = "default"; + current-speed = <115200>; +}; + +&adc0 { + status = "okay"; + sample-time = <12>; + vref-mv = <3300>; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; +}; + +&gpiod { + status = "okay"; +}; + +&scg { + bus_clk { + clock-div = <2>; + }; +}; + +&gpioe { + status = "okay"; +}; + +&rtc { + status = "okay"; + clock-source = "LPO"; +}; + +&lpi2c0 { + status = "okay"; + pinctrl-0 = <&lpi2c0_default>; + pinctrl-names = "default"; +}; + +&lpi2c1 { + status = "okay"; + pinctrl-0 = <&lpi2c1_default>; + pinctrl-names = "default"; +}; + +&ftm2 { + status = "okay"; + compatible = "nxp,kinetis-ftm-pwm"; + #pwm-cells = <3>; + clocks = <&scg KINETIS_SCG_SIRC_CLK>; + prescaler = <128>; + pinctrl-0 = <&ftm2_default>; + pinctrl-names = "default"; + clock-source = "system"; +}; + +&flash0 { + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(64)>; + read-only; + }; + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. + */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 (DT_SIZE_K(202) + DT_SIZE_K(4))>; + }; + slot1_partition: partition@43800 { + label = "image-1"; + reg = <0x00043800 DT_SIZE_K(202)>; + }; + storage_partition: partition@76000 { + label = "storage"; + reg = <0x00076000 DT_SIZE_K(40)>; + }; + }; +}; + +&lpspi0 { + dmas = <&edma 0 14>, <&edma 1 15>; + dma-names = "rx", "tx"; + status = "okay"; + pinctrl-0 = <&lpspi0_default>; + pinctrl-names = "default"; +}; + +&edma { + status = "okay"; +}; + +&wdog { + status = "okay"; +}; diff --git a/boards/nxp/frdm_ke17z512/frdm_ke17z512.yaml b/boards/nxp/frdm_ke17z512/frdm_ke17z512.yaml new file mode 100644 index 00000000000..6b817b1fb94 --- /dev/null +++ b/boards/nxp/frdm_ke17z512/frdm_ke17z512.yaml @@ -0,0 +1,27 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: frdm_ke17z512 +name: NXP FRDM-KE17Z512 +type: mcu +arch: arm +ram: 64 +flash: 512 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - counter + - gpio + - adc + - uart + - pwm + - i2c + - spi + - dma + - watchdog +vendor: nxp diff --git a/boards/nxp/frdm_ke17z512/frdm_ke17z512_defconfig b/boards/nxp/frdm_ke17z512/frdm_ke17z512_defconfig new file mode 100644 index 00000000000..508db6da853 --- /dev/null +++ b/boards/nxp/frdm_ke17z512/frdm_ke17z512_defconfig @@ -0,0 +1,11 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_PINCTRL=y diff --git a/boards/nxp/frdm_kl25z/doc/index.rst b/boards/nxp/frdm_kl25z/doc/index.rst index 6695974c29e..215c476df03 100644 --- a/boards/nxp/frdm_kl25z/doc/index.rst +++ b/boards/nxp/frdm_kl25z/doc/index.rst @@ -189,7 +189,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -207,7 +207,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/frdm_kw41z/doc/index.rst b/boards/nxp/frdm_kw41z/doc/index.rst index 4457b6d9b16..b1643939f8e 100644 --- a/boards/nxp/frdm_kw41z/doc/index.rst +++ b/boards/nxp/frdm_kw41z/doc/index.rst @@ -201,7 +201,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -219,7 +219,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/frdm_kw41z/frdm_kw41z.dts b/boards/nxp/frdm_kw41z/frdm_kw41z.dts index b9c5051145f..47b44f3e617 100644 --- a/boards/nxp/frdm_kw41z/frdm_kw41z.dts +++ b/boards/nxp/frdm_kw41z/frdm_kw41z.dts @@ -33,6 +33,7 @@ zephyr,shell-uart = &lpuart0; zephyr,ieee802154 = &ieee802154; zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &lpuart0; }; leds { @@ -183,7 +184,7 @@ label = "image-0"; reg = <0x00000000 0x00070000>; }; - storage_partition: partition@700000 { + storage_partition: partition@70000 { label = "storage"; reg = <0x00070000 0x00010000>; }; diff --git a/boards/nxp/frdm_mcxa156/CMakeLists.txt b/boards/nxp/frdm_mcxa156/CMakeLists.txt new file mode 100644 index 00000000000..df4c3939ca7 --- /dev/null +++ b/boards/nxp/frdm_mcxa156/CMakeLists.txt @@ -0,0 +1,8 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_library() +zephyr_library_sources(board.c) diff --git a/boards/nxp/frdm_mcxa156/Kconfig b/boards/nxp/frdm_mcxa156/Kconfig new file mode 100644 index 00000000000..23271bc179f --- /dev/null +++ b/boards/nxp/frdm_mcxa156/Kconfig @@ -0,0 +1,8 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INIT_PRIORITY + int "Board initialization priority" + default 1 + help + Board initialization priority. diff --git a/boards/nxp/frdm_mcxa156/Kconfig.frdm_mcxa156 b/boards/nxp/frdm_mcxa156/Kconfig.frdm_mcxa156 new file mode 100644 index 00000000000..7c90d7cb0d8 --- /dev/null +++ b/boards/nxp/frdm_mcxa156/Kconfig.frdm_mcxa156 @@ -0,0 +1,6 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FRDM_MCXA156 + select SOC_MCXA156 if BOARD_FRDM_MCXA156 + select SOC_PART_NUMBER_MCXA156VLL diff --git a/boards/nxp/frdm_mcxa156/board.c b/boards/nxp/frdm_mcxa156/board.c new file mode 100644 index 00000000000..98801c47a1a --- /dev/null +++ b/boards/nxp/frdm_mcxa156/board.c @@ -0,0 +1,125 @@ +/* + * Copyright 2024 NXP + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#include +#include +#include + +/* Core clock frequency: 150MHz */ +#define CLOCK_INIT_CORE_CLOCK 960000000U +#define BOARD_BOOTCLOCKFRO96M_CORE_CLOCK 960000000U +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +static int frdm_mcxa156_init(void) +{ + uint32_t coreFreq; + spc_active_mode_core_ldo_option_t ldoOption; + spc_sram_voltage_config_t sramOption; + + /* Get the CPU Core frequency */ + coreFreq = CLOCK_GetCoreSysClkFreq(); + + /* The flow of increasing voltage and frequency */ + if (coreFreq <= BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) { + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = + (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P1V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + } + + CLOCK_SetupFROHFClocking(96000000U); /*!< Enable FRO HF(96MHz) output */ + + CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */ + + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */ + + /* The flow of decreasing voltage and frequency */ + if (coreFreq > BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) { + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = + (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P1V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + } + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + + /*!< Set up dividers */ + CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */ + CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */ + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(porta), okay) + RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(portb), okay) + RESET_ReleasePeripheralReset(kPORT1_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(portc), okay) + RESET_ReleasePeripheralReset(kPORT2_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(portd), okay) + RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(porte), okay) + RESET_ReleasePeripheralReset(kPORT4_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio0), okay) + RESET_ReleasePeripheralReset(kGPIO0_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_GateGPIO0); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay) + RESET_ReleasePeripheralReset(kGPIO1_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_GateGPIO1); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio2), okay) + RESET_ReleasePeripheralReset(kGPIO2_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_GateGPIO2); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio3), okay) + RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_GateGPIO3); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio4), okay) + RESET_ReleasePeripheralReset(kGPIO4_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_GateGPIO4); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart0), okay) + CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u); + CLOCK_AttachClk(kFRO12M_to_LPUART0); +#endif + + /* Set SystemCoreClock variable. */ + SystemCoreClock = CLOCK_INIT_CORE_CLOCK; + + return 0; +} + +SYS_INIT(frdm_mcxa156_init, PRE_KERNEL_1, CONFIG_BOARD_INIT_PRIORITY); diff --git a/boards/nxp/frdm_mcxa156/board.cmake b/boards/nxp/frdm_mcxa156/board.cmake new file mode 100644 index 00000000000..a9b42d72ac3 --- /dev/null +++ b/boards/nxp/frdm_mcxa156/board.cmake @@ -0,0 +1,13 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +board_runner_args(jlink "--device=MCXA156") +board_runner_args(linkserver "--device=MCXA156:FRDM-MCXA156") +board_runner_args(pyocd "--target=mcxA156") + +include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/nxp/frdm_mcxa156/board.yml b/boards/nxp/frdm_mcxa156/board.yml new file mode 100644 index 00000000000..fd3cb5a5c6d --- /dev/null +++ b/boards/nxp/frdm_mcxa156/board.yml @@ -0,0 +1,5 @@ +board: + name: frdm_mcxa156 + vendor: nxp + socs: + - name: mcxa156 diff --git a/boards/nxp/frdm_mcxa156/doc/frdm_mcxa156.webp b/boards/nxp/frdm_mcxa156/doc/frdm_mcxa156.webp new file mode 100644 index 00000000000..4261ce082ed Binary files /dev/null and b/boards/nxp/frdm_mcxa156/doc/frdm_mcxa156.webp differ diff --git a/boards/nxp/frdm_mcxa156/doc/index.rst b/boards/nxp/frdm_mcxa156/doc/index.rst new file mode 100644 index 00000000000..df622a40ddf --- /dev/null +++ b/boards/nxp/frdm_mcxa156/doc/index.rst @@ -0,0 +1,204 @@ +.. _frdm_mcxa156: + +NXP FRDM-MCXA156 +################ + +Overview +******** + +FRDM-MCXA156 are compact and scalable development boards for rapid prototyping of +MCX A15X MCUs. They offer industry standard headers for easy access to the +MCUs I/Os, integrated open-standard serial interfaces, external flash memory and +an on-board MCU-Link debugger. MCX N Series are high-performance, low-power +microcontrollers with intelligent peripherals and accelerators providing multi-tasking +capabilities and performance efficiency. + +.. image:: frdm_mcxa156.webp + :align: center + :alt: FRDM-MCXA156 + +Hardware +******** + +- MCX-A156 Arm Cortex-M33 microcontroller running at 96 MHz +- 1MB dual-bank on chip Flash +- 128 KB RAM +- USB high-speed (Host/Device) with on-chip HS PHY. HS USB Type-C connectors +- 2x FlexCAN with FD, 2x I3Cs, 2x SAI +- On-board MCU-Link debugger with CMSIS-DAP +- Arduino Header, FlexIO/LCD Header, SmartDMA/Camera Header, mikroBUS + +For more information about the MCX-A156 SoC and FRDM-MCXA156 board, see: + +- `MCX-A156 SoC Website`_ +- `MCX-A156 Datasheet`_ +- `MCX-A156 Reference Manual`_ +- `FRDM-MCXA156 Website`_ +- `FRDM-MCXA156 User Guide`_ +- `FRDM-MCXA156 Board User Manual`_ +- `FRDM-MCXA156 Schematics`_ + +Supported Features +================== + +The FRDM-MCXA156 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | soc flash | ++-----------+------------+-------------------------------------+ + +Targets available +================== + +The default configuration file +:zephyr_file:`boards/nxp/frdm_mcxa156/frdm_mcxa156_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The MCX-A156 SoC has 5 gpio controllers and has pinmux registers which +can be used to configure the functionality of a pin. + ++------------+-----------------+----------------------------+ +| Name | Function | Usage | ++============+=================+============================+ +| PIO0_2 | UART | UART RX | ++------------+-----------------+----------------------------+ +| PIO0_3 | UART | UART TX | ++------------+-----------------+----------------------------+ + +System Clock +============ + +The MCX-A156 SoC is configured to use FRO running at 96MHz as a source for +the system clock. + +Serial Port +=========== + +The FRDM-MCXA156 SoC has 5 LPUART interfaces for serial communication. +LPUART 0 is configured as UART for the console. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe. + +Using LinkServer +---------------- + +Linkserver is the default runner for this board, and supports the factory +default MCU-Link firmware. Follow the instructions in +:ref:`mcu-link-cmsis-onboard-debug-probe` to reprogram the default MCU-Link +firmware. This only needs to be done if the default onboard debug circuit +firmware was changed. To put the board in ``DFU mode`` to program the firmware, +short jumper JP5. + +Using J-Link +------------ + +There are two options. The onboard debug circuit can be updated with Segger +J-Link firmware by following the instructions in +:ref:`mcu-link-jlink-onboard-debug-probe`. +To be able to program the firmware, you need to put the board in ``DFU mode`` +by shortening the jumper JP5. +The second option is to attach a :ref:`jlink-external-debug-probe` to the +10-pin SWD connector (J24) of the board. Additionally, the jumper JP7 must +be shortened. +For both options use the ``-r jlink`` option with west to use the jlink runner. + +.. code-block:: console + + west flash -r jlink + +Configuring a Console +===================== + +Connect a USB cable from your PC to J21, and use the serial terminal of your choice +(minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_mcxa156 + :goals: flash + +Open a serial terminal, reset the board (press the RESET button), and you should +see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 *** + Hello World! frdm_mcxa156/mcxa156 + +Debugging +========= + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_mcxa156/mcxa156 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 *** + Hello World! frdm_mcxa156/mcxa156 + +.. _MCX-A156 SoC Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-a-series-microcontrollers/mcx-a13x-14x-15x-mcus-with-arm-cortex-m33-scalable-device-options-low-power-and-intelligent-peripherals:MCX-A13X-A14X-A15X + +.. _MCX-A156 Datasheet: + https://www.nxp.com/docs/en/data-sheet/MCXAP100M96FS6.pdf + +.. _MCX-A156 Reference Manual: + https://www.nxp.com/webapp/Download?colCode=MCXAP100M96FS6RM + +.. _FRDM-MCXA156 Website: + https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/frdm-development-board-for-mcx-a144-5-6-a154-5-6-mcus:FRDM-MCXA156 + +.. _FRDM-MCXA156 User Guide: + https://www.nxp.com/document/guide/getting-started-with-frdm-mcxa156:GS-FRDM-MCXA156 + +.. _FRDM-MCXA156 Board User Manual: + https://www.nxp.com/docs/en/user-manual/UM12121.pdf + +.. _FRDM-MCXA156 Schematics: + https://www.nxp.com/webapp/Download?colCode=SPF-90841 diff --git a/boards/nxp/frdm_mcxa156/frdm_mcxa156-pinctrl.dtsi b/boards/nxp/frdm_mcxa156/frdm_mcxa156-pinctrl.dtsi new file mode 100644 index 00000000000..a4e241c1bfe --- /dev/null +++ b/boards/nxp/frdm_mcxa156/frdm_mcxa156-pinctrl.dtsi @@ -0,0 +1,19 @@ +/* + * Copyright 2024 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + + +#include + +&pinctrl { + pinmux_lpuart0: pinmux_lpuart0 { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + +}; diff --git a/boards/nxp/frdm_mcxa156/frdm_mcxa156.dts b/boards/nxp/frdm_mcxa156/frdm_mcxa156.dts new file mode 100644 index 00000000000..73c872a0337 --- /dev/null +++ b/boards/nxp/frdm_mcxa156/frdm_mcxa156.dts @@ -0,0 +1,90 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "frdm_mcxa156-pinctrl.dtsi" +#include + +/ { + model = "NXP FRDM_MCXA156 board"; + compatible = "nxp,mcxa156", "nxp,mcx"; + + aliases{ + led0 = &red_led; + led1 = &green_led; + led2 = &red_led; + sw0 = &user_button_2; + sw1 = &user_button_3; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash; + zephyr,flash-controller = &fmu; + zephyr,console = &lpuart0; + zephyr,shell-uart = &lpuart0; + }; + + leds { + compatible = "gpio-leds"; + red_led: led_0 { + gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + label = "Red LED"; + }; + green_led: led_1 { + gpios = <&gpio3 13 GPIO_ACTIVE_LOW>; + label = "Green LED"; + }; + blue_led: led_2 { + gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + label = "Blue LED"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button_2: button_2 { + label = "User SW2"; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + user_button_3: button_3 { + label = "User SW3"; + gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; + +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&lpuart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&pinmux_lpuart0>; + pinctrl-names = "default"; +}; diff --git a/boards/nxp/frdm_mcxa156/frdm_mcxa156.yaml b/boards/nxp/frdm_mcxa156/frdm_mcxa156.yaml new file mode 100644 index 00000000000..c7809e4548b --- /dev/null +++ b/boards/nxp/frdm_mcxa156/frdm_mcxa156.yaml @@ -0,0 +1,19 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: frdm_mcxa156 +name: NXP FRDM MCXA156 +type: mcu +arch: arm +ram: 128 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio +vendor: nxp diff --git a/boards/nxp/frdm_mcxa156/frdm_mcxa156_defconfig b/boards/nxp/frdm_mcxa156/frdm_mcxa156_defconfig new file mode 100644 index 00000000000..3fc86cf38dc --- /dev/null +++ b/boards/nxp/frdm_mcxa156/frdm_mcxa156_defconfig @@ -0,0 +1,12 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y +CONFIG_PINCTRL=y diff --git a/boards/nxp/frdm_mcxc242/Kconfig.frdm_mcxc242 b/boards/nxp/frdm_mcxc242/Kconfig.frdm_mcxc242 new file mode 100644 index 00000000000..bcfd4b1a229 --- /dev/null +++ b/boards/nxp/frdm_mcxc242/Kconfig.frdm_mcxc242 @@ -0,0 +1,6 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FRDM_MCXC242 + select SOC_MCXC242 + select SOC_PART_NUMBER_MCXC242VLH diff --git a/boards/nxp/frdm_mcxc242/board.cmake b/boards/nxp/frdm_mcxc242/board.cmake new file mode 100644 index 00000000000..4ebdbf562c2 --- /dev/null +++ b/boards/nxp/frdm_mcxc242/board.cmake @@ -0,0 +1,13 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +board_runner_args(jlink "--device=MCXC242") +board_runner_args(linkserver "--device=MCXC242:FRDM-MCXC242") +board_runner_args(pyocd "--target=mcxc242") + +include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nxp/frdm_mcxc242/board.yml b/boards/nxp/frdm_mcxc242/board.yml new file mode 100644 index 00000000000..2aa0aaa3da1 --- /dev/null +++ b/boards/nxp/frdm_mcxc242/board.yml @@ -0,0 +1,5 @@ +board: + name: frdm_mcxc242 + vendor: nxp + socs: + - name: mcxc242 diff --git a/boards/nxp/frdm_mcxc242/doc/frdm_mcxc242.webp b/boards/nxp/frdm_mcxc242/doc/frdm_mcxc242.webp new file mode 100644 index 00000000000..1ca95ad0bef Binary files /dev/null and b/boards/nxp/frdm_mcxc242/doc/frdm_mcxc242.webp differ diff --git a/boards/nxp/frdm_mcxc242/doc/index.rst b/boards/nxp/frdm_mcxc242/doc/index.rst new file mode 100644 index 00000000000..ecde1643da9 --- /dev/null +++ b/boards/nxp/frdm_mcxc242/doc/index.rst @@ -0,0 +1,223 @@ +.. _frdm_mcxc242: + +NXP FRDM-MCXC242 +################ + +Overview +******** + +FRDM-MCXC242 is a compact and scalable development board for rapid +prototyping of MCX C242 MCU. It offers industry standard headers +for easy access to the MCU’s I/Os, integrated open-standard serial +interfaces and on-board MCU-Link debugger. +The MCXC is a general purpose ultra-low-power MCU family, +providing additional memory, communications and analog peripheral. + + +.. image:: frdm_mcxc242.webp + :align: center + :alt: FRDM-MCXC242 + +Hardware +******** + +- MCXC242VLH Arm Cortex-M0+ microcontroller running at 48 MHz +- 64LQFP package +- 64KB flash +- 16KB SRAM +- USB FS 2.0 +- 2x low-power UART, 1x UART, 2x I2C, 2x SPI +- FXLS8974CF accelerometer +- NTC temperature sensor +- RGB user LED +- On-board MCU-Link debugger with CMSIS-DAP +- Arduino Header, mikroBUS, Pmod + +For more information about the MCXC242 SoC and FRDM-MCXC242 board, see +these references: + +- `MCX C14x/24x/44x Website`_ +- `MCX C24x Datasheet`_ +- `MCX C24x Reference Manual`_ +- `FRDM-MCXC242 Website`_ +- `FRDM-MCXC242 User Manual`_ +- `FRDM-MCXC242 Design Files`_ + +Supported Features +================== + +The ``frdm_mcxc242`` board target supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | soc flash | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ + + +Targets available +================== + +The default configuration can be found in +:zephyr_file:`boards/nxp/frdm_mcxc242/frdm_mcxc242_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The MCXC242 SoC has five pairs of pinmux/gpio controllers (PORTA/GPIOA, +PORTB/GPIOB, PORTC/GPIOC, PORTD/GPIOD, and PORTE/GPIOE) for the FRDM-MCXC242 board. + ++-------+-------------+---------------------------+ +| Name | Function | Usage | ++=======+=============+===========================+ +| PTE16 | ADC | ADC0 channel 1 | ++-------+-------------+---------------------------+ +| PTB18 | GPIO | Red LED | ++-------+-------------+---------------------------+ +| PTB19 | GPIO | Green LED | ++-------+-------------+---------------------------+ +| PTA13 | GPIO | Blue LED | ++-------+-------------+---------------------------+ +| PTA1 | LPUART0_RX | UART Console | ++-------+-------------+---------------------------+ +| PTA2 | LPUART0_TX | UART Console | ++-------+-------------+---------------------------+ +| PTA20 | RESET | RESET Button SW1 | ++-------+-------------+---------------------------+ +| PTC1 | GPIO | User button SW2 | ++-------+-------------+---------------------------+ +| PTA4 | GPIO | User button SW3 | ++-------+-------------+---------------------------+ +| PTD6 | I2C1_SDA | I2C accelerometer | ++-------+-------------+---------------------------+ +| PTD7 | I2C1_SCL | I2C accelerometer | ++-------+-------------+---------------------------+ + +System Clock +============ + +The MCXC242 SoC is configured to use HIRC running at 48 MHz as a system clock source. + +Serial Port +=========== + +The MCXC242 LPUART0 is used for the console. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe. + +Using LinkServer +---------------- + +Linkserver is the default runner for this board, and supports the factory +default MCU-Link firmware. Follow the instructions in +:ref:`mcu-link-cmsis-onboard-debug-probe` to reprogram the default MCU-Link +firmware. This only needs to be done if the default onboard debug circuit +firmware was changed. To put the board in ``DFU mode`` to program the firmware, +short jumper JP1. + +Using J-Link +------------ + +There are two options. The onboard debug circuit can be updated with Segger +J-Link firmware by following the instructions in +:ref:`mcu-link-jlink-onboard-debug-probe`. +To be able to program the firmware, you need to put the board in ``DFU mode`` +by shortening the jumper JP1. +The second option is to attach a :ref:`jlink-external-debug-probe` to the +10-pin SWD connector (J10) of the board. Additionally, the jumper JP3 must +be shortened. +For both options use the ``-r jlink`` option with west to use the jlink runner. + +.. code-block:: console + + west flash -r jlink + +Configuring a Console +===================== + +Connect a USB cable from your PC to J9, and use the serial terminal of your choice +(minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_mcxc242 + :goals: flash + +Open a serial terminal, reset the board (press the SW1 button), and you should +see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v3.6.0-4475-gfa5bd8bb098e *** + Hello World! frdm_mcxc242/mcxc242 + +Debugging +========= + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_mcxc242 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v3.6.0-4475-gfa5bd8bb098e *** + Hello World! frdm_mcxc242/mcxc242 + +.. _MCX C14x/24x/44x Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-c-series-microcontrollers/mcx-c14x-24x-44x-mcus-with-arm-cortex-m0-plus-entry-level-mcus-with-usb-segment-lcd-and-classical-peripherals:MCX-C14x-24x-44x + +.. _MCX C24x Datasheet: + https://www.nxp.com/docs/en/data-sheet/MCXC24XP64M48SF2.pdf + +.. _MCX C24x Reference Manual: + https://www.nxp.com/webapp/Download?colCode=MCXC24XP64M48RM + +.. _FRDM-MCXC242 Website: + https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/frdm-development-board-for-mcx-c242-mcus:FRDM-MCXC242 + +.. _FRDM-MCXC242 User Manual: + https://www.nxp.com/webapp/Download?colCode=UM12119 + +.. _FRDM-MCXC242 Design Files: + https://www.nxp.com/webapp/Download?colCode=FRDM-MCXC242-DESIGN-FILES diff --git a/boards/nxp/frdm_mcxc242/frdm_mcxc242-pinctrl.dtsi b/boards/nxp/frdm_mcxc242/frdm_mcxc242-pinctrl.dtsi new file mode 100644 index 00000000000..972cba958e7 --- /dev/null +++ b/boards/nxp/frdm_mcxc242/frdm_mcxc242-pinctrl.dtsi @@ -0,0 +1,28 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +#include + +&pinctrl { + pinmux_lpuart0: pinmux_lpuart0 { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + pinmux_i2c1: pinmux_i2c1 { + group0 { + pinmux = , + ; + drive-strength = "low"; + drive-open-drain; + slew-rate = "fast"; + }; + }; +}; diff --git a/boards/nxp/frdm_mcxc242/frdm_mcxc242.dts b/boards/nxp/frdm_mcxc242/frdm_mcxc242.dts new file mode 100644 index 00000000000..5961363441d --- /dev/null +++ b/boards/nxp/frdm_mcxc242/frdm_mcxc242.dts @@ -0,0 +1,113 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "frdm_mcxc242-pinctrl.dtsi" +#include + +/ { + model = "NXP FRDM-MCXC242 board"; + compatible = "nxp,mcxc242", "nxp,mcx"; + + aliases { + led0 = &red_led; + led1 = &green_led; + led2 = &red_led; + sw0 = &user_button_2; + sw1 = &user_button_3; + accel0 = &fxls8974; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &lpuart0; + zephyr,shell-uart = &lpuart0; + }; + + leds { + compatible = "gpio-leds"; + red_led: led_0 { + gpios = <&gpiob 18 GPIO_ACTIVE_LOW>; + label = "Red LED"; + }; + green_led: led_1 { + gpios = <&gpiob 19 GPIO_ACTIVE_LOW>; + label = "Green LED"; + }; + blue_led: led_2 { + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + label = "Blue LED"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button_2: button_2 { + label = "User SW2"; + gpios = <&gpioc 1 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + user_button_3: button_3 { + label = "User SW3"; + gpios = <&gpioa 4 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; +}; + +&sim { + pllfll-select = ; + er32k-select = ; +}; + +&cpu0 { + clock-frequency = <48000000>; +}; + +&osc { + clock-frequency = <32768>; + mode = "low-power"; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; +}; + +&gpioc { + status = "okay"; +}; + +&gpioe { + status = "okay"; +}; + +&lpuart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&pinmux_lpuart0>; + pinctrl-names = "default"; +}; + +i2c1: &i2c1 { + status = "okay"; + pinctrl-0 = <&pinmux_i2c1>; + pinctrl-names = "default"; + + fxls8974: fxls8974@18 { + status = "okay"; + compatible = "nxp,fxls8974"; + reg = <0x18>; + int1-gpios = <&gpioc 2 GPIO_ACTIVE_LOW>; + int2-gpios = <&gpioc 3 GPIO_ACTIVE_LOW>; + }; +}; diff --git a/boards/nxp/frdm_mcxc242/frdm_mcxc242.yaml b/boards/nxp/frdm_mcxc242/frdm_mcxc242.yaml new file mode 100644 index 00000000000..285b86dde68 --- /dev/null +++ b/boards/nxp/frdm_mcxc242/frdm_mcxc242.yaml @@ -0,0 +1,24 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: frdm_mcxc242 +name: NXP FRDM-MCXC242 +type: mcu +arch: arm +ram: 16 +flash: 64 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - i2c +testing: + ignore_tags: + - net + - bluetooth +vendor: nxp diff --git a/boards/nxp/frdm_mcxc242/frdm_mcxc242_defconfig b/boards/nxp/frdm_mcxc242/frdm_mcxc242_defconfig new file mode 100644 index 00000000000..3d640c35842 --- /dev/null +++ b/boards/nxp/frdm_mcxc242/frdm_mcxc242_defconfig @@ -0,0 +1,10 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y diff --git a/boards/nxp/frdm_mcxn236/CMakeLists.txt b/boards/nxp/frdm_mcxn236/CMakeLists.txt new file mode 100644 index 00000000000..df4c3939ca7 --- /dev/null +++ b/boards/nxp/frdm_mcxn236/CMakeLists.txt @@ -0,0 +1,8 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_library() +zephyr_library_sources(board.c) diff --git a/boards/nxp/frdm_mcxn236/Kconfig b/boards/nxp/frdm_mcxn236/Kconfig new file mode 100644 index 00000000000..23271bc179f --- /dev/null +++ b/boards/nxp/frdm_mcxn236/Kconfig @@ -0,0 +1,8 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INIT_PRIORITY + int "Board initialization priority" + default 1 + help + Board initialization priority. diff --git a/boards/nxp/frdm_mcxn236/Kconfig.frdm_mcxn236 b/boards/nxp/frdm_mcxn236/Kconfig.frdm_mcxn236 new file mode 100644 index 00000000000..f77e46fcb5f --- /dev/null +++ b/boards/nxp/frdm_mcxn236/Kconfig.frdm_mcxn236 @@ -0,0 +1,6 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FRDM_MCXN236 + select SOC_MCXN236 + select SOC_PART_NUMBER_MCXN236VDF diff --git a/boards/nxp/frdm_mcxn236/board.c b/boards/nxp/frdm_mcxn236/board.c new file mode 100644 index 00000000000..8f0d1fd7976 --- /dev/null +++ b/boards/nxp/frdm_mcxn236/board.c @@ -0,0 +1,179 @@ +/* + * Copyright 2024 NXP + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#include +#include +#include + +/* Board xtal frequency in Hz */ +#define BOARD_XTAL0_CLK_HZ 24000000U +/* Core clock frequency: 150MHz */ +#define CLOCK_INIT_CORE_CLOCK 150000000U +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +static void enable_lpcac(void) +{ + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK; + SYSCON->LPCAC_CTRL &= ~(SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK | + SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK); +} + +/* Update Active mode voltage for OverDrive mode. */ +void power_mode_od(void) +{ + /* Set the DCDC VDD regulator to 1.2 V voltage level */ + spc_active_mode_dcdc_option_t opt = { + .DCDCVoltage = kSPC_DCDC_OverdriveVoltage, + .DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength, + }; + SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &opt); + + /* Set the LDO_CORE VDD regulator to 1.2 V voltage level */ + spc_active_mode_core_ldo_option_t ldo_opt = { + .CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage, + .CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength, + }; + SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldo_opt); + + /* Specifies the 1.2V operating voltage for the SRAM's read/write timing margin */ + spc_sram_voltage_config_t cfg = { + .operateVoltage = kSPC_sramOperateAt1P2V, + .requestVoltageUpdate = true, + }; + SPC_SetSRAMOperateVoltage(SPC0, &cfg); +} + +static int frdm_mcxn236_init(void) +{ + enable_lpcac(); + + power_mode_od(); + + /* Enable SCG clock */ + CLOCK_EnableClock(kCLOCK_Scg); + + /* FRO OSC setup - begin, enable the FRO for safety switching */ + + /* Switch to FRO 12M first to ensure we can change the clock setting */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); + + /* Configure Flash wait-states to support 1.2V voltage level and 150000000Hz frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x3U)); + + /* Enable FRO HF(48MHz) output */ + CLOCK_SetupFROHFClocking(48000000U); + + /* Set up PLL0 */ + const pll_setup_t pll0Setup = { + .pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) | + SCG_APLLCTRL_SELP(13U), + .pllndiv = SCG_APLLNDIV_NDIV(8U), + .pllpdiv = SCG_APLLPDIV_PDIV(1U), + .pllmdiv = SCG_APLLMDIV_MDIV(50U), + .pllRate = 150000000U + }; + /* Configure PLL0 to the desired values */ + CLOCK_SetPLL0Freq(&pll0Setup); + /* PLL0 Monitor is disabled */ + CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable); + + /* Switch MAIN_CLK to PLL0 */ + CLOCK_AttachClk(kPLL0_to_MAIN_CLK); + + /* Set AHBCLKDIV divider to value 1 */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm1), okay) + CLOCK_SetClkDiv(kCLOCK_DivFlexcom1Clk, 1u); + CLOCK_AttachClk(kFRO12M_to_FLEXCOMM1); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm2), okay) + CLOCK_SetClkDiv(kCLOCK_DivFlexcom2Clk, 1u); + CLOCK_AttachClk(kFRO12M_to_FLEXCOMM2); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm3), okay) + CLOCK_SetClkDiv(kCLOCK_DivFlexcom3Clk, 1u); + CLOCK_AttachClk(kFRO12M_to_FLEXCOMM3); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm4), okay) + CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u); + CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm5), okay) + CLOCK_SetClkDiv(kCLOCK_DivFlexcom5Clk, 1u); + CLOCK_AttachClk(kFRO12M_to_FLEXCOMM5); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(os_timer), okay) + CLOCK_AttachClk(kCLK_1M_to_OSTIMER); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio0), okay) + CLOCK_EnableClock(kCLOCK_Gpio0); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay) + CLOCK_EnableClock(kCLOCK_Gpio1); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio2), okay) + CLOCK_EnableClock(kCLOCK_Gpio2); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio3), okay) + CLOCK_EnableClock(kCLOCK_Gpio3); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio4), okay) + CLOCK_EnableClock(kCLOCK_Gpio4); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio5), okay) + CLOCK_EnableClock(kCLOCK_Gpio5); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(wwdt0), okay) + CLOCK_SetClkDiv(kCLOCK_DivWdt0Clk, 1u); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer0), okay) + CLOCK_SetClkDiv(kCLOCK_DivCtimer0Clk, 1U); + CLOCK_AttachClk(kPLL0_to_CTIMER0); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer1), okay) + CLOCK_SetClkDiv(kCLOCK_DivCtimer1Clk, 1U); + CLOCK_AttachClk(kPLL0_to_CTIMER1); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer2), okay) + CLOCK_SetClkDiv(kCLOCK_DivCtimer2Clk, 1U); + CLOCK_AttachClk(kPLL0_to_CTIMER2); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer3), okay) + CLOCK_SetClkDiv(kCLOCK_DivCtimer3Clk, 1U); + CLOCK_AttachClk(kPLL0_to_CTIMER3); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer4), okay) + CLOCK_SetClkDiv(kCLOCK_DivCtimer4Clk, 1U); + CLOCK_AttachClk(kPLL0_to_CTIMER4); +#endif + + /* Set SystemCoreClock variable. */ + SystemCoreClock = CLOCK_INIT_CORE_CLOCK; + + return 0; +} + +SYS_INIT(frdm_mcxn236_init, PRE_KERNEL_1, CONFIG_BOARD_INIT_PRIORITY); diff --git a/boards/nxp/frdm_mcxn236/board.cmake b/boards/nxp/frdm_mcxn236/board.cmake new file mode 100644 index 00000000000..705a6443526 --- /dev/null +++ b/boards/nxp/frdm_mcxn236/board.cmake @@ -0,0 +1,25 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +board_runner_args(jlink "--device=MCXN236" "--reset-after-load") +board_runner_args(linkserver "--device=MCXN236:FRDM-MCXN236") +board_runner_args(linkserver "--core=cm33_core0") +board_runner_args(linkserver "--override=/device/memory/1/flash-driver=MCXNxxx_S.cfx") +board_runner_args(linkserver "--override=/device/memory/1/location=0x10000000") +# Linkserver v1.4.85 and earlier do not include the secure regions in the +# MCXN236 memory map, so we add them here +board_runner_args(linkserver "--override=/device/memory/-=\{\"location\":\"0x30000000\",\ + \"size\":\"0x00040000\",\"type\":\"RAM\"\}") +# Define region for peripherals +board_runner_args(linkserver "--override=/device/memory/-=\{\"location\":\"0x50000000\",\ + \"size\":\"0x00140000\",\"type\":\"RAM\"\}") + +# Pyocd support added with the NXP.MCXN236_DFP.17.0.0.pack CMSIS Pack +board_runner_args(pyocd "--target=mcxn236") + +include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/nxp/frdm_mcxn236/board.yml b/boards/nxp/frdm_mcxn236/board.yml new file mode 100644 index 00000000000..0bd2d3928ba --- /dev/null +++ b/boards/nxp/frdm_mcxn236/board.yml @@ -0,0 +1,5 @@ +board: + name: frdm_mcxn236 + vendor: nxp + socs: + - name: mcxn236 diff --git a/boards/nxp/frdm_mcxn236/doc/frdm_mcxn236.webp b/boards/nxp/frdm_mcxn236/doc/frdm_mcxn236.webp new file mode 100644 index 00000000000..8e7516c33fa Binary files /dev/null and b/boards/nxp/frdm_mcxn236/doc/frdm_mcxn236.webp differ diff --git a/boards/nxp/frdm_mcxn236/doc/index.rst b/boards/nxp/frdm_mcxn236/doc/index.rst new file mode 100644 index 00000000000..3ee20c5c1e8 --- /dev/null +++ b/boards/nxp/frdm_mcxn236/doc/index.rst @@ -0,0 +1,211 @@ +.. _frdm_mcxn236: + +NXP FRDM-MCXN236 +################ + +Overview +******** + +FRDM-MCXN236 are compact and scalable development boards for rapid prototyping of +MCX N23X MCUs. They offer industry standard headers for easy access to the +MCUs I/Os, integrated open-standard serial interfaces, external flash memory and +an on-board MCU-Link debugger. MCX N Series are high-performance, low-power +microcontrollers with intelligent peripherals and accelerators providing multi-tasking +capabilities and performance efficiency. + +.. image:: frdm_mcxn236.webp + :align: center + :alt: FRDM-MCXN236 + +Hardware +******** + +- MCX-N236 Arm Cortex-M33 microcontroller running at 150 MHz +- 1MB dual-bank on chip Flash +- 352 KB RAM +- USB high-speed (Host/Device) with on-chip HS PHY. HS USB Type-C connectors +- 8x LP Flexcomms each supporting SPI, I2C, UART +- 2x FlexCAN with FD, 2x I3Cs, 2x SAI +- On-board MCU-Link debugger with CMSIS-DAP +- Arduino Header, FlexIO/LCD Header, SmartDMA/Camera Header, mikroBUS + +For more information about the MCX-N236 SoC and FRDM-MCXN236 board, see: + +- `MCX-N236 SoC Website`_ +- `MCX-N236 Datasheet`_ +- `MCX-N236 Reference Manual`_ +- `FRDM-MCXN236 Website`_ +- `FRDM-MCXN236 User Guide`_ +- `FRDM-MCXN236 Board User Manual`_ +- `FRDM-MCXN236 Schematics`_ + +Supported Features +================== + +The FRDM-MCXN236 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | soc flash | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ + +Targets available +================== + +The default configuration file +:zephyr_file:`boards/nxp/frdm_mcxn236/frdm_mcxn236_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The MCX-N236 SoC has 6 gpio controllers and has pinmux registers which +can be used to configure the functionality of a pin. + ++------------+-----------------+----------------------------+ +| Name | Function | Usage | ++============+=================+============================+ +| P0_PIO1_8 | UART | UART RX | ++------------+-----------------+----------------------------+ +| P1_PIO1_9 | UART | UART TX | ++------------+-----------------+----------------------------+ + +System Clock +============ + +The MCX-N236 SoC is configured to use PLL0 running at 150MHz as a source for +the system clock. + +Serial Port +=========== + +The FRDM-MCXN236 SoC has 8 FLEXCOMM interfaces for serial communication. +Flexcomm 4 is configured as UART for the console. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe. + +Using LinkServer +---------------- + +Linkserver is the default runner for this board, and supports the factory +default MCU-Link firmware. Follow the instructions in +:ref:`mcu-link-cmsis-onboard-debug-probe` to reprogram the default MCU-Link +firmware. This only needs to be done if the default onboard debug circuit +firmware was changed. To put the board in ``DFU mode`` to program the firmware, +short jumper JP5. + +Using J-Link +------------ + +There are two options. The onboard debug circuit can be updated with Segger +J-Link firmware by following the instructions in +:ref:`mcu-link-jlink-onboard-debug-probe`. +To be able to program the firmware, you need to put the board in ``DFU mode`` +by shortening the jumper JP5. +The second option is to attach a :ref:`jlink-external-debug-probe` to the +10-pin SWD connector (J12) of the board. Additionally, the jumper JP7 must +be shortened. +For both options use the ``-r jlink`` option with west to use the jlink runner. + +.. code-block:: console + + west flash -r jlink + +Configuring a Console +===================== + +Connect a USB cable from your PC to J10, and use the serial terminal of your choice +(minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_mcxn236 + :goals: flash + +Open a serial terminal, reset the board (press the RESET button), and you should +see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 *** + Hello World! frdm_mcxn236/mcxn236 + +Debugging +========= + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_mcxn236/mcxn236 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 *** + Hello World! frdm_mcxn236/mcxn236 + +.. _MCX-N236 SoC Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-n-series-microcontrollers/mcx-n23x-highly-integrated-mcus-with-on-chip-accelerators-intelligent-peripherals-and-advanced-security:MCX-N23X + +.. _MCX-N236 Datasheet: + https://www.nxp.com/docs/en/data-sheet/MCXN23x.pdf + +.. _MCX-N236 Reference Manual: + https://www.nxp.com/docs/en/reference-manual/MCXN23xRM.pdf + +.. _FRDM-MCXN236 Website: + https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/frdm-development-board-for-mcx-n23x-mcus:FRDM-MCXN236 + +.. _FRDM-MCXN236 User Guide: + https://www.nxp.com/document/guide/getting-started-with-frdm-mcxn236:GS-FRDM-MCXN236 + +.. _FRDM-MCXN236 Board User Manual: + https://www.nxp.com/docs/en/user-manual/UM12041.pdf + +.. _FRDM-MCXN236 Schematics: + https://www.nxp.com/webapp/Download?colCode=SPF-90828 diff --git a/boards/nxp/frdm_mcxn236/frdm_mcxn236-pinctrl.dtsi b/boards/nxp/frdm_mcxn236/frdm_mcxn236-pinctrl.dtsi new file mode 100644 index 00000000000..7e587aad528 --- /dev/null +++ b/boards/nxp/frdm_mcxn236/frdm_mcxn236-pinctrl.dtsi @@ -0,0 +1,93 @@ +/* + * Copyright 2024 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + + +#include + +&pinctrl { + pinmux_flexcomm2_lpuart: pinmux_flexcomm2_lpuart { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + }; + + pinmux_flexcomm2_lpi2c: pinmux_flexcomm2_lpi2c { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + bias-pull-up; + drive-open-drain; + }; + }; + + pinmux_flexcomm3_lpspi: pinmux_flexcomm3_lpspi { + group0 { + pinmux = , + , + , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + }; + + pinmux_flexcomm4_lpuart: pinmux_flexcomm4_lpuart { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + }; + + pinmux_flexcomm5_lpi2c: pinmux_flexcomm5_lpi2c { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + bias-pull-up; + drive-open-drain; + }; + }; + + pinmux_flexpwm1_pwm0: pinmux_flexpwm1_pwm0 { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + }; + }; + + pinmux_flexpwm1_pwm1: pinmux_flexpwm1_pwm1 { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + }; + }; + + pinmux_flexpwm1_pwm2: pinmux_flexpwm1_pwm2 { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + }; + }; + +}; diff --git a/boards/nxp/frdm_mcxn236/frdm_mcxn236.dts b/boards/nxp/frdm_mcxn236/frdm_mcxn236.dts new file mode 100644 index 00000000000..fe0e60ddbb7 --- /dev/null +++ b/boards/nxp/frdm_mcxn236/frdm_mcxn236.dts @@ -0,0 +1,115 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "frdm_mcxn236.dtsi" + +/ { + model = "NXP FRDM_N236 board"; + compatible = "nxp,mcxn236", "nxp,mcx"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash; + zephyr,flash-controller = &fmu; + zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &flexcomm4_lpuart4; + zephyr,console = &flexcomm4_lpuart4; + zephyr,shell-uart = &flexcomm4_lpuart4; + }; + + aliases{ + watchdog0 = &wwdt0; + pwm-0 = &flexpwm1_pwm0; + }; +}; + +&sram0 { + compatible = "mmio-sram"; + reg = <0x20000000 DT_SIZE_K(192)>; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&green_led { + status = "okay"; +}; + +&red_led { + status = "okay"; +}; + +&user_button_2 { + status = "okay"; +}; + +&edma0 { + status = "okay"; +}; + +&flexcomm2 { + status = "okay"; +}; + +/* + * LPFLEXCOMM supports UART and I2C on the same instance, enable this for + * LFLEXCOMM2 + */ +&flexcomm2_lpuart2 { + status = "okay"; +}; + +&flexcomm2_lpi2c2 { + status = "okay"; +}; + +&flexcomm3 { + status = "okay"; +}; + +&flexcomm3_lpspi3 { + status = "okay"; +}; + +&flexcomm4 { + status = "okay"; +}; + +&flexcomm4_lpuart4 { + status = "okay"; +}; + +&flexcomm5 { + status = "okay"; +}; + +&flexcomm5_lpi2c5 { + status = "okay"; +}; + +&wwdt0 { + status = "okay"; +}; + +&flexpwm1_pwm0 { + status = "okay"; +}; + +&ctimer0 { + status = "okay"; +}; diff --git a/boards/nxp/frdm_mcxn236/frdm_mcxn236.dtsi b/boards/nxp/frdm_mcxn236/frdm_mcxn236.dtsi new file mode 100644 index 00000000000..b4631c79afa --- /dev/null +++ b/boards/nxp/frdm_mcxn236/frdm_mcxn236.dtsi @@ -0,0 +1,120 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "frdm_mcxn236-pinctrl.dtsi" +#include +#include + +/ { + aliases{ + led0 = &red_led; + led1 = &green_led; + led2 = &blue_led; + sw0 = &user_button_2; + sw1 = &user_button_3; + }; + + leds { + compatible = "gpio-leds"; + green_led: led_1 { + gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; + label = "Green LED"; + }; + blue_led: led_2 { + gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + label = "Blue LED"; + }; + red_led: led_3 { + gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; + label = "Red LED"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button_2: button_0 { + label = "User SW2"; + gpios = <&gpio0 20 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + zephyr,code = ; + }; + user_button_3: button_1 { + label = "User SW3"; + gpios = <&gpio0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + zephyr,code = ; + }; + }; +}; + +&flexcomm2_lpuart2 { + current-speed = <115200>; + pinctrl-0 = <&pinmux_flexcomm2_lpuart>; + pinctrl-names = "default"; +}; + +&flexcomm2_lpi2c2 { + pinctrl-0 = <&pinmux_flexcomm2_lpi2c>; + pinctrl-names = "default"; + clock-frequency = ; +}; + +&flexcomm3_lpspi3 { + pinctrl-0 = <&pinmux_flexcomm3_lpspi>; + pinctrl-names = "default"; +}; + +&flexcomm4_lpuart4 { + current-speed = <115200>; + pinctrl-0 = <&pinmux_flexcomm4_lpuart>; + pinctrl-names = "default"; +}; + +&flexcomm5_lpi2c5 { + pinctrl-0 = <&pinmux_flexcomm5_lpi2c>; + pinctrl-names = "default"; + clock-frequency = ; +}; + +/* + * MCXN236 board uses OS timer as the kernel timer + * In case we need to switch to SYSTICK timer, then + * replace &os_timer with &systick + */ +&os_timer { + status = "disabled"; +}; + +&systick { + status = "okay"; +}; + +&flash { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(64)>; + }; + /* Note slot 0 has one additional sector, + * this is intended for use with the swap move algorithm + */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 DT_SIZE_K(480)>; + }; + slot1_partition: partition@88000 { + label = "image-1"; + reg = <0x0088000 DT_SIZE_K(472)>; + }; + }; +}; + +&flexpwm1_pwm0 { + pinctrl-0 = <&pinmux_flexpwm1_pwm0>; + pinctrl-names = "default"; +}; diff --git a/boards/nxp/frdm_mcxn236/frdm_mcxn236.yaml b/boards/nxp/frdm_mcxn236/frdm_mcxn236.yaml new file mode 100644 index 00000000000..ea8cdb1e2e4 --- /dev/null +++ b/boards/nxp/frdm_mcxn236/frdm_mcxn236.yaml @@ -0,0 +1,25 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: frdm_mcxn236 +name: NXP FRDM MCXN236 +type: mcu +arch: arm +ram: 256 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - dma + - gpio + - spi + - i2c + - watchdog + - pwm + - counter +vendor: nxp diff --git a/boards/nxp/frdm_mcxn236/frdm_mcxn236_defconfig b/boards/nxp/frdm_mcxn236/frdm_mcxn236_defconfig new file mode 100644 index 00000000000..41ce4376bdc --- /dev/null +++ b/boards/nxp/frdm_mcxn236/frdm_mcxn236_defconfig @@ -0,0 +1,18 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_TRUSTED_EXECUTION_SECURE=y diff --git a/boards/nxp/frdm_mcxn947/Kconfig.defconfig b/boards/nxp/frdm_mcxn947/Kconfig.defconfig index 461a4ed6286..5334a121e40 100644 --- a/boards/nxp/frdm_mcxn947/Kconfig.defconfig +++ b/boards/nxp/frdm_mcxn947/Kconfig.defconfig @@ -14,4 +14,11 @@ config MAIN_STACK_SIZE endif +if BOOTLOADER_MCUBOOT +choice MCUBOOT_BOOTLOADER_MODE + # Board only supports MCUBoot via "upgrade only" method: + default MCUBOOT_BOOTLOADER_MODE_OVERWRITE_ONLY +endchoice +endif #BOOTLOADER_MCUBOOT + endif diff --git a/boards/nxp/frdm_mcxn947/Kconfig.frdm_mcxn947 b/boards/nxp/frdm_mcxn947/Kconfig.frdm_mcxn947 index 944d25af1b1..fde729ba736 100644 --- a/boards/nxp/frdm_mcxn947/Kconfig.frdm_mcxn947 +++ b/boards/nxp/frdm_mcxn947/Kconfig.frdm_mcxn947 @@ -2,6 +2,6 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_FRDM_MCXN947 - select SOC_MCXN947_CPU0 if BOARD_FRDM_MCXN947_MCXN947_CPU0 + select SOC_MCXN947_CPU0 if BOARD_FRDM_MCXN947_MCXN947_CPU0 || BOARD_FRDM_MCXN947_MCXN947_CPU0_QSPI select SOC_MCXN947_CPU1 if BOARD_FRDM_MCXN947_MCXN947_CPU1 select SOC_PART_NUMBER_MCXN947VDF diff --git a/boards/nxp/frdm_mcxn947/Kconfig.sysbuild b/boards/nxp/frdm_mcxn947/Kconfig.sysbuild new file mode 100644 index 00000000000..4625c7d2929 --- /dev/null +++ b/boards/nxp/frdm_mcxn947/Kconfig.sysbuild @@ -0,0 +1,6 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +choice MCUBOOT_MODE + default MCUBOOT_MODE_OVERWRITE_ONLY +endchoice diff --git a/boards/nxp/frdm_mcxn947/board.c b/boards/nxp/frdm_mcxn947/board.c index e6568204ce9..37ec5f4dd6d 100644 --- a/boards/nxp/frdm_mcxn947/board.c +++ b/boards/nxp/frdm_mcxn947/board.c @@ -25,13 +25,6 @@ /* System clock frequency. */ extern uint32_t SystemCoreClock; -__ramfunc static void enable_lpcac(void) -{ - SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK; - SYSCON->LPCAC_CTRL &= ~(SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK | - SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK); -} - /* Update Active mode voltage for OverDrive mode. */ void power_mode_od(void) { @@ -57,10 +50,38 @@ void power_mode_od(void) SPC_SetSRAMOperateVoltage(SPC0, &cfg); } -static int frdm_mcxn947_init(void) +#if CONFIG_FLASH_MCUX_FLEXSPI_NOR || CONFIG_FLASH_MCUX_FLEXSPI_XIP +__ramfunc static void enable_cache64(void) { - enable_lpcac(); + /* Make sure the FlexSPI clock is enabled before configuring the FlexSPI cache. */ + SYSCON->AHBCLKCTRLSET[0] |= SYSCON_AHBCLKCTRL0_FLEXSPI_MASK; + + /* Set command to invalidate all ways and write GO bit to initiate command */ + CACHE64_CTRL0->CCR = CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_INVW0_MASK; + CACHE64_CTRL0->CCR |= CACHE64_CTRL_CCR_GO_MASK; + /* Wait until the command completes */ + while ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U) { + } + /* Enable cache, enable write buffer */ + CACHE64_CTRL0->CCR = (CACHE64_CTRL_CCR_ENWRBUF_MASK | CACHE64_CTRL_CCR_ENCACHE_MASK); + /* configure reg0, reg1 to cover the whole FlexSPI + * reg 0 covers the space where Zephyr resides in case of XIP from FlexSPI + * reg 1 covers the storage space in case of XIP from FlexSPI + */ + CACHE64_POLSEL0->REG0_TOP = 0x7FFC00; + CACHE64_POLSEL0->REG1_TOP = 0x0; + CACHE64_POLSEL0->POLSEL = + (CACHE64_POLSEL_POLSEL_REG0_POLICY(1) | CACHE64_POLSEL_POLSEL_REG1_POLICY(0) | + CACHE64_POLSEL_POLSEL_REG2_POLICY(0)); + + __ISB(); + __DSB(); +} +#endif + +static int frdm_mcxn947_init(void) +{ power_mode_od(); /* Enable SCG clock */ @@ -106,6 +127,25 @@ static int frdm_mcxn947_init(void) CLOCK_SetupExtClocking(BOARD_XTAL0_CLK_HZ); +#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcan0), okay) + /* Set up PLL1 for 80 MHz FlexCAN clock */ + const pll_setup_t pll1Setup = { + .pllctrl = SCG_SPLLCTRL_SOURCE(1U) | SCG_SPLLCTRL_SELI(27U) | + SCG_SPLLCTRL_SELP(13U), + .pllndiv = SCG_SPLLNDIV_NDIV(3U), + .pllpdiv = SCG_SPLLPDIV_PDIV(1U), + .pllmdiv = SCG_SPLLMDIV_MDIV(10U), + .pllRate = 80000000U + }; + + /* Configure PLL1 to the desired values */ + CLOCK_SetPLL1Freq(&pll1Setup); + /* PLL1 Monitor is disabled */ + CLOCK_SetPll1MonitorMode(kSCG_Pll1MonitorDisable); + /* Set PLL1 CLK0 divider to value 1 */ + CLOCK_SetClkDiv(kCLOCK_DivPLL1Clk0, 1U); +#endif + #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm1), okay) CLOCK_SetClkDiv(kCLOCK_DivFlexcom1Clk, 1u); CLOCK_AttachClk(kFRO12M_to_FLEXCOMM1); @@ -203,17 +243,21 @@ static int frdm_mcxn947_init(void) CLOCK_AttachClk(kPLL0_to_CTIMER4); #endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcan0), okay) + CLOCK_SetClkDiv(kCLOCK_DivFlexcan0Clk, 1U); + CLOCK_AttachClk(kPLL1_CLK0_to_FLEXCAN0); +#endif + #if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc0), okay) CLOCK_SetClkDiv(kCLOCK_DivUSdhcClk, 1u); CLOCK_AttachClk(kFRO_HF_to_USDHC); #endif -#if CONFIG_FLASH_MCUX_FLEXSPI_NOR - /* We downclock the FlexSPI to 50MHz, it will be set to the - * optimum speed supported by the Flash device during FLEXSPI - * Init - */ - flexspi_clock_set_freq(MCUX_FLEXSPI_CLK, MHZ(50)); +#if CONFIG_FLASH_MCUX_FLEXSPI_NOR || CONFIG_FLASH_MCUX_FLEXSPI_XIP + /* Setup the FlexSPI clock */ + flexspi_clock_set_freq(MCUX_FLEXSPI_CLK, + DT_PROP(DT_NODELABEL(w25q64jvssiq), spi_max_frequency)); + enable_cache64(); #endif #if DT_NODE_HAS_STATUS(DT_NODELABEL(vref), okay) @@ -268,6 +312,41 @@ static int frdm_mcxn947_init(void) USB_EhciPhyInit(kUSB_ControllerEhci0, BOARD_XTAL0_CLK_HZ, &usbPhyConfig); #endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpcmp0), okay) + CLOCK_SetClkDiv(kCLOCK_DivCmp0FClk, 1U); + CLOCK_AttachClk(kFRO12M_to_CMP0F); + SPC_EnableActiveModeAnalogModules(SPC0, (kSPC_controlCmp0 | kSPC_controlCmp0Dac)); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(lptmr0), okay) + +/* + * Clock Select Decides what input source the lptmr will clock from + * + * 0 <- 12MHz FRO + * 1 <- 16K FRO + * 2 <- 32K OSC + * 3 <- Output from the OSC_SYS + */ +#if DT_PROP(DT_NODELABEL(lptmr0), clk_source) == 0x0 + CLOCK_SetupClockCtrl(kCLOCK_FRO12MHZ_ENA); +#elif DT_PROP(DT_NODELABEL(lptmr0), clk_source) == 0x1 + CLOCK_SetupClk16KClocking(kCLOCK_Clk16KToVsys); +#elif DT_PROP(DT_NODELABEL(lptmr0), clk_source) == 0x2 + CLOCK_SetupOsc32KClocking(kCLOCK_Osc32kToVsys); +#elif DT_PROP(DT_NODELABEL(lptmr0), clk_source) == 0x3 + /* Value here should not exceed 25MHZ when using lptmr */ + CLOCK_SetupExtClocking(MHZ(24)); + CLOCK_SetupClockCtrl(kCLOCK_CLKIN_ENA_FM_USBH_LPT); +#endif /* DT_PROP(DT_NODELABEL(lptmr0), clk_source) */ + +#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(lptmr0), okay) */ + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexio0), okay) + CLOCK_SetClkDiv(kCLOCK_DivFlexioClk, 1u); + CLOCK_AttachClk(kPLL0_to_FLEXIO); +#endif + /* Set SystemCoreClock variable. */ SystemCoreClock = CLOCK_INIT_CORE_CLOCK; diff --git a/boards/nxp/frdm_mcxn947/board.yml b/boards/nxp/frdm_mcxn947/board.yml index b74b1880cb9..b4a64533333 100644 --- a/boards/nxp/frdm_mcxn947/board.yml +++ b/boards/nxp/frdm_mcxn947/board.yml @@ -3,3 +3,6 @@ board: vendor: nxp socs: - name: mcxn947 + variants: + - name: qspi + cpucluster: 'cpu0' diff --git a/boards/nxp/frdm_mcxn947/doc/index.rst b/boards/nxp/frdm_mcxn947/doc/index.rst index a7724ad69ce..1559dcea969 100644 --- a/boards/nxp/frdm_mcxn947/doc/index.rst +++ b/boards/nxp/frdm_mcxn947/doc/index.rst @@ -84,12 +84,23 @@ The FRDM-MCXN947 board configuration supports the following hardware features: +-----------+------------+-------------------------------------+ | USDHC | on-chip | sdhc | +-----------+------------+-------------------------------------+ -| VREF | on-chip | REGULATOR | +| VREF | on-chip | regulator | +-----------+------------+-------------------------------------+ | ADC | on-chip | adc | +-----------+------------+-------------------------------------+ | USBHS | on-chip | USB device | +-----------+------------+-------------------------------------+ +| LPCMP | on-chip | sensor(comparator) | ++-----------+------------+-------------------------------------+ +| FLEXCAN | on-chip | CAN | ++-----------+------------+-------------------------------------+ +| LPTMR | on-chip | counter | ++-----------+------------+-------------------------------------+ +| FLEXIO | on-chip | flexio | ++-----------+------------+-------------------------------------+ +| DISPLAY | on-chip | flexio; MIPI-DBI. Tested with | +| | | :ref:`lcd_par_s035` | ++-----------+------------+-------------------------------------+ Targets available ================== @@ -179,7 +190,7 @@ Connect a USB cable from your PC to J17, and use the serial terminal of your cho Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -194,10 +205,47 @@ see the following message in the terminal: *** Booting Zephyr OS build v3.6.0-479-g91faa20c6741 *** Hello World! frdm_mcxn947/mcxn947/cpu0 +Flashing to QSPI +================ + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :app: zephyr/samples/hello_world + :board: frdm_mcxn947/mcxn947/cpu0/qspi + :gen-args: -DCONFIG_MCUBOOT_SIGNATURE_KEY_FILE=\"bootloader/mcuboot/root-rsa-2048.pem\" -DCONFIG_BOOTLOADER_MCUBOOT=y + :goals: flash + + +In order to load Zephyr application from QSPI you should program a bootloader like +MCUboot bootloader to internal flash. Here are the steps. + +.. zephyr-app-commands:: + :app: bootloader/mcuboot/boot/zephyr + :board: frdm_mcxn947/mcxn947/cpu0/qspi + :goals: flash + +Open a serial terminal, reset the board (press the RESET button), and you should +see the following message in the terminal: + +.. code-block:: console + + *** Booting MCUboot v2.1.0-rc1-2-g9f034729d99a *** + *** Using Zephyr OS build v3.6.0-4046-gf279a03af8ab *** + I: Starting bootloader + I: Primary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3 + I: Secondary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3 + I: Boot source: none + I: Image index: 0, Swap type: none + I: Bootloader chainload address offset: 0x0 + I: Jumping to the first image slot + *** Booting Zephyr OS build v3.6.0-4046-gf279a03af8ab *** + Hello World! frdm_mcxn947/mcxn947/cpu0/qspi + Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi index 8bdc9e1c91f..68a1fa17301 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi @@ -148,6 +148,7 @@ input-enable; }; }; + pinmux_lpadc0: pinmux_lpadc0 { group0 { pinmux = , @@ -157,4 +158,64 @@ drive-strength = "low"; }; }; + + pinmux_lpcmp0: pinmux_lpcmp0 { + group0 { + pinmux = ; + drive-strength = "low"; + slew-rate = "fast"; + bias-pull-up; + }; + }; + + pinmux_flexcan0: pinmux_flexcan0 { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + }; + + pinmux_flexio_lcd: pinmux_flexio_lcd { + group0 { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + group1 { + pinmux = ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + bias-pull-up; + }; + group2 { + pinmux = ; + slew-rate = "slow"; + drive-strength = "low"; + input-enable; + bias-pull-up; + }; + }; }; diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi index 37e15451bc9..7e95ec16144 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi @@ -52,6 +52,19 @@ status = "disabled"; }; }; + + /* + * This node describes the GPIO pins of the LCD-PAR-S035 panel 8080 interface. + */ + nxp_lcd_8080_connector: lcd-8080-connector { + compatible = "nxp,lcd-8080"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <9 0 &gpio4 6 0>, /* Pin 9, LCD touch INT */ + <10 0 &gpio4 5 0>, /* Pin 10, LCD backlight control */ + <11 0 &gpio4 7 0>; /* Pin 11, LCD and touch reset */ + }; }; &flexcomm1_lpspi1 { @@ -59,7 +72,7 @@ pinctrl-names = "default"; }; -&flexcomm2_lpi2c2 { +nxp_8080_touch_panel_i2c: &flexcomm2_lpi2c2 { pinctrl-0 = <&pinmux_flexcomm2_lpi2c>; pinctrl-names = "default"; clock-frequency = ; @@ -83,6 +96,10 @@ * replace &os_timer with &systick */ &os_timer { + status = "disabled"; +}; + +&systick { status = "okay"; }; @@ -96,16 +113,16 @@ label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(64)>; }; - /* Note slot 0 has one additional sector, - * this is intended for use with the swap move algorithm + /* For the MCUBoot "upgrade only" method, + * the slot sizes must be equal. */ slot0_partition: partition@10000 { label = "image-0"; reg = <0x00010000 DT_SIZE_K(992)>; }; - slot1_partition: partition@100000 { + slot1_partition: partition@108000 { label = "image-1"; - reg = <0x00108000 DT_SIZE_K(984)>; + reg = <0x00108000 DT_SIZE_K(992)>; }; /* storage_partition is placed in WINBOND flash memory*/ }; @@ -191,3 +208,29 @@ pinctrl-0 = <&pinmux_lpadc0>; pinctrl-names = "default"; }; + +nxp_flexio_lcd: &flexio0_lcd { + /* DMA channels 0, muxed to FlexIO TX */ + dmas = <&edma0 0 61>; + dma-names = "tx"; + shifters-count = <8>; + timers-count = <1>; + enwr-pin = <1>; + rd-pin = <0>; + data-pin-start = <16>; + reset-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + rs-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pinmux_flexio_lcd>; + pinctrl-names = "default"; +}; + +&lpcmp0 { + pinctrl-0 = <&pinmux_lpcmp0>; + pinctrl-names = "default"; +}; + +&flexcan0 { + pinctrl-0 = <&pinmux_flexcan0>; + pinctrl-names = "default"; +}; diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts index e3d80335db2..af2cdc2cd9c 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts @@ -6,162 +6,9 @@ /dts-v1/; -#include -#include "frdm_mcxn947.dtsi" +#include "frdm_mcxn947_mcxn947_cpu0.dtsi" / { model = "NXP FRDM_N94 board"; compatible = "nxp,mcxn947", "nxp,mcx"; - - cpus { - /delete-node/ cpu@1; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,flash = &flash; - zephyr,flash-controller = &fmu; - zephyr,code-partition = &slot0_partition; - zephyr,console = &flexcomm4_lpuart4; - zephyr,shell-uart = &flexcomm4_lpuart4; - }; - - aliases{ - watchdog0 = &wwdt0; - pwm-0 = &flexpwm1_pwm0; - }; -}; - -/* - * Default for this board is to allocate SRAM0-5 to cpu0 but the - * application can have an application specific device tree to - * allocate the SRAM0-7 differently. - * - * For example, SRAM0-6 could be allocated to cpu0 with only SRAM7 - * for cpu1. This would require the value of sram0 to have a DT_SIZE_K - * of 384. You would have to make updates to cpu1 sram settings as well. - */ -&sram0 { - compatible = "mmio-sram"; - reg = <0x20000000 DT_SIZE_K(320)>; -}; - -&gpio4 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&green_led { - status = "okay"; -}; - -&red_led { - status = "okay"; -}; - -&user_button_2 { - status = "okay"; -}; - -&edma0 { - status = "okay"; -}; - -&flexcomm1 { - status = "okay"; -}; - -&flexcomm1_lpspi1 { - status = "okay"; -}; - -&flexcomm2 { - status = "okay"; -}; - -&flexcomm2_lpi2c2 { - status = "okay"; -}; - -/* - *LPFLEXCOMM supports UART and I2C on the same instance, enable this for - * LFLEXCOMM2 - */ -&flexcomm2_lpuart2 { - status = "okay"; -}; - -&flexcomm4 { - status = "okay"; -}; - -&flexcomm4_lpuart4 { - status = "okay"; -}; - -&flexspi { - status = "okay"; -}; - -&w25q64jvssiq { - status = "okay"; -}; - -&dac0 { - status = "okay"; -}; - -&enet { - status = "okay"; -}; - -&enet_mac { - status = "okay"; -}; - -&enet_mdio { - status = "okay"; -}; - -&wwdt0 { - status = "okay"; -}; - -&flexpwm1_pwm0 { - status = "okay"; -}; - -&ctimer0 { - status = "okay"; -}; - -&usdhc0 { - status = "okay"; - sdmmc { - compatible = "zephyr,sdmmc-disk"; - status = "okay"; - }; -}; - -&vref { - status = "okay"; -}; - -&lpadc0 { - status = "okay"; -}; - -zephyr_udc0: &usb1 { - status = "okay"; }; diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dtsi new file mode 100644 index 00000000000..d571d35384f --- /dev/null +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dtsi @@ -0,0 +1,186 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Common dts file to enable supported features for CPU 0. + * This file is included by both the default variant + * which is run from internal flash and the QSPI variant. + */ +/dts-v1/; + +#include +#include "frdm_mcxn947.dtsi" + +/ { + cpus { + /delete-node/ cpu@1; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash; + zephyr,flash-controller = &fmu; + zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &flexcomm4_lpuart4; + zephyr,console = &flexcomm4_lpuart4; + zephyr,shell-uart = &flexcomm4_lpuart4; + zephyr,canbus = &flexcan0; + }; + + aliases{ + watchdog0 = &wwdt0; + pwm-0 = &flexpwm1_pwm0; + }; +}; + +/* + * Default for this board is to allocate SRAM0-5 to cpu0 but the + * application can have an application specific device tree to + * allocate the SRAM0-7 differently. + * + * For example, SRAM0-6 could be allocated to cpu0 with only SRAM7 + * for cpu1. This would require the value of sram0 to have a DT_SIZE_K + * of 384. You would have to make updates to cpu1 sram settings as well. + */ +&sram0 { + compatible = "mmio-sram"; + reg = <0x20000000 DT_SIZE_K(320)>; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&green_led { + status = "okay"; +}; + +&red_led { + status = "okay"; +}; + +&user_button_2 { + status = "okay"; +}; + +&edma0 { + status = "okay"; +}; + +&flexcomm1 { + status = "okay"; +}; + +&flexcomm1_lpspi1 { + status = "okay"; +}; + +&flexcomm2 { + status = "okay"; +}; + +&flexcomm2_lpi2c2 { + status = "okay"; +}; + +/* + *LPFLEXCOMM supports UART and I2C on the same instance, enable this for + * LFLEXCOMM2 + */ +&flexcomm2_lpuart2 { + status = "okay"; +}; + +&flexcomm4 { + status = "okay"; +}; + +&flexcomm4_lpuart4 { + status = "okay"; +}; + +&flexspi { + status = "okay"; +}; + +&w25q64jvssiq { + status = "okay"; +}; + +&dac0 { + status = "okay"; +}; + +&enet { + status = "okay"; +}; + +&enet_mac { + status = "okay"; +}; + +&enet_mdio { + status = "okay"; +}; + +&wwdt0 { + status = "okay"; +}; + +&flexpwm1_pwm0 { + status = "okay"; +}; + +&flexcan0 { + status = "okay"; +}; + +&ctimer0 { + status = "okay"; +}; + +&usdhc0 { + status = "okay"; + sdmmc { + compatible = "zephyr,sdmmc-disk"; + status = "okay"; + }; +}; + +&vref { + status = "okay"; +}; + +&lpadc0 { + status = "okay"; +}; + +zephyr_udc0: &usb1 { + status = "okay"; +}; + +&lpcmp0 { + status = "okay"; +}; + +&lptmr0 { + status = "okay"; +}; + +&flexio0 { + status = "okay"; +}; diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml index ef6ea7114dc..76f937fb1e5 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml @@ -15,6 +15,7 @@ toolchain: - gnuarmemb - xtools supported: + - can - dma - gpio - spi diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi.dts b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi.dts new file mode 100644 index 00000000000..d16e42561d4 --- /dev/null +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi.dts @@ -0,0 +1,44 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "frdm_mcxn947_mcxn947_cpu0.dtsi" + +/delete-node/ &slot0_partition; +/delete-node/ &slot1_partition; +/delete-node/ &storage_partition; + +/ { + model = "NXP FRDM_N94 board, QSPI variant"; + compatible = "nxp,mcxn947", "nxp,mcx"; + + chosen { + zephyr,flash = &w25q64jvssiq; + }; + +}; + +&w25q64jvssiq { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + slot0_partition: partition@0 { + label = "image-0"; + reg = <0x00000000 DT_SIZE_M(3)>; + }; + slot1_partition: partition@300000 { + label = "image-1"; + reg = <0x00300000 DT_SIZE_M(3)>; + }; + storage_partition: partition@600000 { + label = "storage"; + reg = <0x00600000 DT_SIZE_M(2)>; + }; + }; +}; diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi.yaml b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi.yaml new file mode 100644 index 00000000000..6cd7ad2e40c --- /dev/null +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi.yaml @@ -0,0 +1,31 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: frdm_mcxn947/mcxn947/cpu0/qspi +name: NXP FRDM MCXN947 QSPI (CPU0) +type: mcu +arch: arm +ram: 320 +flash: 8192 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - can + - dma + - gpio + - spi + - dac + - i2c + - watchdog + - pwm + - counter + - sdhc + - regulator + - adc + - usb_device +vendor: nxp diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi_defconfig b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi_defconfig new file mode 100644 index 00000000000..41ce4376bdc --- /dev/null +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi_defconfig @@ -0,0 +1,18 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_TRUSTED_EXECUTION_SECURE=y diff --git a/boards/nxp/frdm_rw612/Kconfig.defconfig b/boards/nxp/frdm_rw612/Kconfig.defconfig new file mode 100644 index 00000000000..89d264de123 --- /dev/null +++ b/boards/nxp/frdm_rw612/Kconfig.defconfig @@ -0,0 +1,11 @@ +# FRDM_RW612 board + +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_FRDM_RW612 + +config NET_L2_ETHERNET + default y if DT_HAS_NXP_ENET_MAC_ENABLED && NETWORKING + +endif # BOARD_FRDM_RW612 diff --git a/boards/nxp/frdm_rw612/board.cmake b/boards/nxp/frdm_rw612/board.cmake index c7b1d7d51d4..26f7241b20d 100644 --- a/boards/nxp/frdm_rw612/board.cmake +++ b/boards/nxp/frdm_rw612/board.cmake @@ -3,7 +3,7 @@ board_runner_args(jlink "--device=RW612" "--reset-after-load") -board_runner_args(linkserver "--device=RW612:RDRW612") +board_runner_args(linkserver "--device=RW612:FRDM-RW612") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) diff --git a/boards/nxp/frdm_rw612/doc/index.rst b/boards/nxp/frdm_rw612/doc/index.rst index caefff181f0..0044b09cb9c 100644 --- a/boards/nxp/frdm_rw612/doc/index.rst +++ b/boards/nxp/frdm_rw612/doc/index.rst @@ -39,7 +39,26 @@ Supported Features +-----------+------------+-----------------------------------+ | USART | on-chip | serial | +-----------+------------+-----------------------------------+ - +| BLE | on-chip | Bluetooth | ++-----------+------------+-----------------------------------+ +| DMA | on-chip | dma | ++-----------+------------+-----------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-----------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-----------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-----------------------------------+ +| WWDT | on-chip | watchdog | ++-----------+------------+-----------------------------------+ +| USBOTG | on-chip | usb | ++-----------+------------+-----------------------------------+ +| CTIMER | on-chip | counter | ++-----------+------------+-----------------------------------+ +| MRT | on-chip | counter | ++-----------+------------+-----------------------------------+ +| OS_TIMER | on-chip | os timer | ++-----------+------------+-----------------------------------+ The default configuration can be found in the defconfig file: @@ -47,6 +66,16 @@ The default configuration can be found in the defconfig file: Other hardware features are not currently supported +Fetch Binary Blobs +****************** + +To support Bluetooth, frdm_rw612 requires fetching binary blobs, which can be +achieved by running the following command: + +.. code-block:: console + + west blobs fetch hal_nxp + Programming and Debugging ************************* @@ -73,7 +102,7 @@ Connect a USB cable from your PC to J10, and use the serial terminal of your cho Flashing ======== -Here is an example for the :ref:`hello_world` application. This example uses the +Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the :ref:`jlink-debug-host-tools` as default. .. zephyr-app-commands:: @@ -92,7 +121,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. This example uses the +Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the :ref:`jlink-debug-host-tools` as default. .. zephyr-app-commands:: @@ -108,6 +137,26 @@ should see the following message in the terminal: ***** Booting Zephyr OS zephyr-v3.6.0 ***** Hello World! frdm_rw612 +Bluetooth +========= + +BLE functionality requires to fetch binary blobs, so make sure to follow +the ``Fetch Binary Blobs`` section first. + +Those binary blobs can be used in two different ways, depending if :kconfig:option:`CONFIG_NXP_MONOLITHIC_BT` +is enabled or not: + +- :kconfig:option:`CONFIG_NXP_MONOLITHIC_BT` is enabled (default): + +The required binary blob will be linked with the application image directly, forming +one single monolithic image. +The user has nothing else to do other than flashing the application to the board. + +- :kconfig:option:`CONFIG_NXP_MONOLITHIC_BT` is disabled: + +In this case, the BLE blob won't be linked with the application, so the user needs to manually +flash the BLE binary blob to the board at the address ``0x18540000``. +The binary blob will be located here: ``/modules/hal/nxp/zephyr/blobs/rw61x/rw61x_sb_ble_a2.bin`` Resources ========= diff --git a/boards/nxp/frdm_rw612/frdm_rw612-pinctrl.dtsi b/boards/nxp/frdm_rw612/frdm_rw612-pinctrl.dtsi index c9b0bcb8984..80a6caa12ed 100644 --- a/boards/nxp/frdm_rw612/frdm_rw612-pinctrl.dtsi +++ b/boards/nxp/frdm_rw612/frdm_rw612-pinctrl.dtsi @@ -13,4 +13,44 @@ slew-rate = "normal"; }; }; + + pinmux_flexcomm0_usart: pinmux_flexcomm0_usart { + group0 { + pinmux = ; + slew-rate = "normal"; + }; + }; + + pinmux_enet: pinmux_enet { + group0 { + pinmux = ; + slew-rate = "fast"; + }; + }; + + pinmux_mdio: pinmux_mdio { + group0 { + pinmux = ; + slew-rate = "fast"; + }; + }; + + pinmux_flexcomm2_i2c: pinmux_flexcomm2_i2c { + group0 { + pinmux = ; + slew-rate = "normal"; + bias-pull-up; + }; + }; + + pinmux_flexcomm1_spi: pinmux_flexcomm1_spi { + group0 { + pinmux = ; + slew-rate = "ultra"; + }; + }; }; diff --git a/boards/nxp/frdm_rw612/frdm_rw612.dts b/boards/nxp/frdm_rw612/frdm_rw612.dts index ad7237fb658..03c8adc3287 100644 --- a/boards/nxp/frdm_rw612/frdm_rw612.dts +++ b/boards/nxp/frdm_rw612/frdm_rw612.dts @@ -14,12 +14,16 @@ aliases { led0 = &green_led; + watchdog0 = &wwdt; + usart-0 = &flexcomm3; + i2c-0 = &flexcomm2; }; chosen { zephyr,sram = &sram_data; zephyr,flash = &w25q512jvfiq; zephyr,console = &flexcomm3; + zephyr,shell-uart = &flexcomm3; }; leds { @@ -38,6 +42,14 @@ pinctrl-names = "default"; }; +&flexcomm0 { + compatible = "nxp,lpc-usart"; + status = "disabled"; + current-speed = <115200>; + pinctrl-0 = <&pinmux_flexcomm0_usart>; + pinctrl-names = "default"; +}; + &hsgpio0 { status = "okay"; }; @@ -48,10 +60,107 @@ w25q512jvfiq: w25q512jvfiq@0 { compatible = "nxp,imx-flexspi-nor"; reg = <0>; - size = <(DT_SIZE_M(512) / 8)>; + size = ; status = "okay"; erase-block-size = <4096>; write-block-size = <1>; spi-max-frequency = <133000000>; }; }; + +&hci { + status = "okay"; + wakeup-source; +}; + +&enet_mac { + status = "okay"; + pinctrl-0 = <&pinmux_enet>; + pinctrl-names = "default"; + phy-handle = <&phy>; + zephyr,random-mac-address; + phy-connection-type = "rmii"; +}; + +&enet_mdio { + status = "okay"; + pinctrl-0 = <&pinmux_mdio>; + pinctrl-names = "default"; + phy: phy@2 { + compatible = "microchip,ksz8081"; + reg = <2>; + status = "okay"; + reset-gpios = <&hsgpio1 23 GPIO_ACTIVE_HIGH>; + int-gpios = <&hsgpio0 21 GPIO_ACTIVE_HIGH>; + microchip,interface-type = "rmii"; + }; +}; + +&wwdt { + status = "okay"; +}; + +&dma0 { + status = "okay"; +}; + +&mrt0_channel0 { + status = "okay"; +}; + +&ctimer0 { + status = "okay"; +}; + +&pmu { + reset-causes-en = , + , + ; +}; + +/* OS Timer is the wakeup source for PM mode 2 */ +&os_timer { + status = "okay"; + wakeup-source; +}; + +&systick { + status = "disabled"; +}; + +&adc0 { + status = "okay"; +}; + +&dac0 { + status = "okay"; +}; + +zephyr_udc0: &usb_otg { + status = "okay"; +}; + +/* + * the default resistors on the board breaks out the MOSI/MISO + * pins to the nets labelled "UART" which go to J1 2 and 4, + * but we are using it for spi mosi and miso here. + * SCK is on J2 6 as labelled. + */ +&flexcomm1 { + compatible = "nxp,lpc-spi"; + pinctrl-0 = <&pinmux_flexcomm1_spi>; + pinctrl-names = "default"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; +}; + +arduino_i2c: &flexcomm2 { + compatible = "nxp,lpc-i2c"; + status = "okay"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pinmux_flexcomm2_i2c>; + pinctrl-names = "default"; +}; diff --git a/boards/nxp/frdm_rw612/frdm_rw612.yaml b/boards/nxp/frdm_rw612/frdm_rw612.yaml index cbb95c51716..813330e2b56 100644 --- a/boards/nxp/frdm_rw612/frdm_rw612.yaml +++ b/boards/nxp/frdm_rw612/frdm_rw612.yaml @@ -16,3 +16,13 @@ ram: 960 flash: 65536 supported: - gpio + - dma + - spi + - i2c + - entropy + - usb_device + - watchdog + - counter + - hwinfo + - adc + - dac diff --git a/boards/nxp/frdm_rw612/pre_dt_board.cmake b/boards/nxp/frdm_rw612/pre_dt_board.cmake index 2c56668e435..5da215a0a3b 100644 --- a/boards/nxp/frdm_rw612/pre_dt_board.cmake +++ b/boards/nxp/frdm_rw612/pre_dt_board.cmake @@ -1,7 +1,5 @@ # Copyright 2023 NXP # SPDX-License-Identifier: Apache-2.0 -# Suppress "simple_bus_reg" on RW6XX boards as all GPIO ports use the same register. -list(APPEND EXTRA_DTC_FLAGS "-Wno-simple_bus_reg") # Suppress "spi_bus_bridge" as flexcomm node can be used as a SPI device. list(APPEND EXTRA_DTC_FLAGS "-Wno-spi_bus_bridge") diff --git a/boards/nxp/hexiwear/doc/index.rst b/boards/nxp/hexiwear/doc/index.rst index bc4d58a70d4..6f47bddf00d 100644 --- a/boards/nxp/hexiwear/doc/index.rst +++ b/boards/nxp/hexiwear/doc/index.rst @@ -227,7 +227,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -245,7 +245,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -460,7 +460,7 @@ Once you have started a debug session, run telnet: Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -486,7 +486,7 @@ terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/hexiwear/hexiwear_mk64f12.dts b/boards/nxp/hexiwear/hexiwear_mk64f12.dts index 519beb04ab7..f41b3410c2c 100644 --- a/boards/nxp/hexiwear/hexiwear_mk64f12.dts +++ b/boards/nxp/hexiwear/hexiwear_mk64f12.dts @@ -26,6 +26,7 @@ zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &uart0; zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,bt-hci = &bt_hci_uart; @@ -186,26 +187,25 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - boot_partition: partition@0 { label = "mcuboot"; - reg = <0x00000000 0x00010000>; + reg = <0x00000000 DT_SIZE_K(64)>; read-only; }; - /* Note slot 0 has one additional sector, - * this is intended for use with the swap move algorithm + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. */ slot0_partition: partition@10000 { label = "image-0"; - reg = <0x00010000 0x00069000>; + reg = <0x00010000 (DT_SIZE_K(416) + DT_SIZE_K(8))>; }; - slot1_partition: partition@79000 { + slot1_partition: partition@7a000 { label = "image-1"; - reg = <0x00079000 0x00068000>; + reg = <0x0007a000 DT_SIZE_K(416)>; }; - storage_partition: partition@e1000 { + storage_partition: partition@e2000 { label = "storage"; - reg = <0x000e1000 0x0001f000>; + reg = <0x000e2000 DT_SIZE_K(120)>; }; }; }; diff --git a/boards/nxp/imx8mm_evk/Kconfig.defconfig b/boards/nxp/imx8mm_evk/Kconfig.defconfig index 5cc30c81ed1..c5bdd4b8213 100644 --- a/boards/nxp/imx8mm_evk/Kconfig.defconfig +++ b/boards/nxp/imx8mm_evk/Kconfig.defconfig @@ -1,15 +1,44 @@ -# MIMX8MM EVK board defconfig - -# Copyright (c) 2020, Manivannan Sadhasivam +# Copyright 2024 NXP # SPDX-License-Identifier: Apache-2.0 -if BOARD_IMX8MM_EVK_MIMX8MM6_M4 +if BOARD_IMX8MM_EVK + +if BOARD_IMX8MM_EVK_MIMX8MM6_A53 || BOARD_IMX8MM_EVK_MIMX8MM6_A53_SMP + +if NETWORKING + +config NET_L2_ETHERNET + default y + +config NET_TX_STACK_SIZE + default 8192 + +config NET_RX_STACK_SIZE + default 8192 + +if NET_TCP + +config NET_TCP_WORKQ_STACK_SIZE + default 8192 + +endif # NET_TCP + +if NET_MGMT_EVENT + +config NET_MGMT_EVENT_STACK_SIZE + default 8192 + +endif # NET_MGMT_EVENT + +if NET_SOCKETS_SERVICE + +config NET_SOCKETS_SERVICE_STACK_SIZE + default 8192 + +endif # NET_SOCKETS_SERVICE + +endif # NETWORKING -if !XIP -config FLASH_SIZE - default 0 -config FLASH_BASE_ADDRESS - default 0 -endif +endif # BOARD_IMX8MM_EVK_MIMX8MM6_A53 || BOARD_IMX8MM_EVK_MIMX8MM6_A53_SMP -endif # BOARD_IMX8MM_EVK_MIMX8MM6_M4 +endif # BOARD_IMX8MM_EVK diff --git a/boards/nxp/imx8mm_evk/doc/index.rst b/boards/nxp/imx8mm_evk/doc/index.rst index 9c29ba4cb67..d834726d0c1 100644 --- a/boards/nxp/imx8mm_evk/doc/index.rst +++ b/boards/nxp/imx8mm_evk/doc/index.rst @@ -55,8 +55,18 @@ features: +-----------+------------+-------------------------------------+ | ARM TIMER | on-chip | system clock | +-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| RDC | on-chip | Resource Domain Controller | ++-----------+------------+-------------------------------------+ | UART | on-chip | serial port | +-----------+------------+-------------------------------------+ +| GPT | on-chip | timer | ++-----------+------------+-------------------------------------+ +| ENET | on-chip | ethernet port | ++-----------+------------+-------------------------------------+ The Zephyr imx8mm_evk board for Cortex-M4 supports the following hardware features: @@ -212,7 +222,7 @@ MIMX8MM EVK board can be debugged by connecting an external JLink JTAG debugger to the J902 debug connector and to the PC. Then the application can be debugged using the usual way. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk-pinctrl.dtsi b/boards/nxp/imx8mm_evk/imx8mm_evk-pinctrl.dtsi index b994d31c67a..9dff995dd9d 100644 --- a/boards/nxp/imx8mm_evk/imx8mm_evk-pinctrl.dtsi +++ b/boards/nxp/imx8mm_evk/imx8mm_evk-pinctrl.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, NXP + * Copyright 2022,2024 NXP * SPDX-License-Identifier: Apache-2.0 * */ @@ -12,7 +12,7 @@ pinmux = <&iomuxc_uart2_rxd_uart_rx_uart2_rx>, <&iomuxc_uart2_txd_uart_tx_uart2_tx>; slew-rate = "fast"; - drive-strength = "40-ohm"; + drive-strength = "x6"; }; }; @@ -21,8 +21,46 @@ pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx>, <&iomuxc_uart4_txd_uart_tx_uart4_tx>; slew-rate = "fast"; - drive-strength = "40-ohm"; + drive-strength = "x6"; }; }; + pinmux_enet: pinmux_enet { + group0 { + pinmux = <&iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0>, + <&iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1>, + <&iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2>, + <&iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3>, + <&iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc>, + <&iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl>; + slew-rate = "fast"; + drive-strength = "x6"; + }; + + group1 { + pinmux = <&iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0>, + <&iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1>, + <&iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2>, + <&iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3>, + <&iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc>, + <&iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl>; + slew-rate = "fast"; + drive-strength = "x1"; + }; + + group2 { + pinmux = <&iomuxc_sai2_rxc_gpio_io_gpio4_io22>; + slew-rate = "fast"; + drive-strength = "x1"; + }; + }; + + pinmux_mdio: pinmux_mdio { + group0 { + pinmux = <&iomuxc_enet_mdc_enet_mdc_enet1_mdc>, + <&iomuxc_enet_mdio_enet_mdio_enet1_mdio>; + slew-rate = "slow"; + drive-strength = "x6"; + }; + }; }; diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.dts b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.dts index 0a2b5c666ea..57f0a5f1ea6 100644 --- a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.dts +++ b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.dts @@ -1,5 +1,5 @@ /* - * Copyright 2020-2022 NXP + * Copyright 2020-2022,2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -36,6 +36,30 @@ }; }; +&enet { + status = "okay"; +}; + +&enet_mac { + pinctrl-0 = <&pinmux_enet>; + pinctrl-names = "default"; + phy-handle = <&phy>; + zephyr,random-mac-address; + phy-connection-type = "rgmii"; + status = "okay"; +}; + +&enet_mdio { + pinctrl-0 = <&pinmux_mdio>; + pinctrl-names = "default"; + status = "okay"; + phy: phy@0 { + compatible = "qca,ar8031"; + reg = <0>; + status = "okay"; + }; +}; + &uart4 { current-speed = <115200>; pinctrl-0 = <&uart4_default>; diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_defconfig b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_defconfig index 4e31bf4e946..03f34114970 100644 --- a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_defconfig +++ b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_defconfig @@ -13,6 +13,7 @@ CONFIG_ICACHE_LINE_SIZE_DETECT=y # Zephyr Kernel Configuration CONFIG_XIP=n +CONFIG_KERNEL_DIRECT_MAP=y # Serial Drivers CONFIG_SERIAL=y diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp.dts b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp.dts index 308094cfb20..f9d9793bba7 100644 --- a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp.dts +++ b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp.dts @@ -1,5 +1,5 @@ /* - * Copyright 2021-2022 NXP + * Copyright 2021-2022,2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -38,6 +38,30 @@ }; }; +&enet { + status = "okay"; +}; + +&enet_mac { + pinctrl-0 = <&pinmux_enet>; + pinctrl-names = "default"; + phy-handle = <&phy>; + zephyr,random-mac-address; + phy-connection-type = "rgmii"; + status = "okay"; +}; + +&enet_mdio { + pinctrl-0 = <&pinmux_mdio>; + pinctrl-names = "default"; + status = "okay"; + phy: phy@0 { + compatible = "qca,ar8031"; + reg = <0>; + status = "okay"; + }; +}; + &uart4 { current-speed = <115200>; pinctrl-0 = <&uart4_default>; diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp_defconfig b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp_defconfig index 845b48736a7..3c7bc851bf3 100644 --- a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp_defconfig +++ b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp_defconfig @@ -13,6 +13,7 @@ CONFIG_ICACHE_LINE_SIZE_DETECT=y # Zephyr Kernel Configuration CONFIG_XIP=n +CONFIG_KERNEL_DIRECT_MAP=y # SMP CONFIG_SMP=y diff --git a/boards/nxp/imx8mn_evk/Kconfig.defconfig b/boards/nxp/imx8mn_evk/Kconfig.defconfig new file mode 100644 index 00000000000..20e13140916 --- /dev/null +++ b/boards/nxp/imx8mn_evk/Kconfig.defconfig @@ -0,0 +1,44 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_IMX8MN_EVK + +if BOARD_IMX8MN_EVK_MIMX8MN6_A53 || BOARD_IMX8MN_EVK_MIMX8MN6_A53_SMP + +if NETWORKING + +config NET_L2_ETHERNET + default y + +config NET_TX_STACK_SIZE + default 8192 + +config NET_RX_STACK_SIZE + default 8192 + +if NET_TCP + +config NET_TCP_WORKQ_STACK_SIZE + default 8192 + +endif # NET_TCP + +if NET_MGMT_EVENT + +config NET_MGMT_EVENT_STACK_SIZE + default 8192 + +endif # NET_MGMT_EVENT + +if NET_SOCKETS_SERVICE + +config NET_SOCKETS_SERVICE_STACK_SIZE + default 8192 + +endif # NET_SOCKETS_SERVICE + +endif # NETWORKING + +endif # BOARD_IMX8MN_EVK_MIMX8MN6_A53 || BOARD_IMX8MN_EVK_MIMX8MN6_A53_SMP + +endif # BOARD_IMX8MN_EVK diff --git a/boards/nxp/imx8mn_evk/doc/index.rst b/boards/nxp/imx8mn_evk/doc/index.rst index 923967133bf..fd80ad82075 100644 --- a/boards/nxp/imx8mn_evk/doc/index.rst +++ b/boards/nxp/imx8mn_evk/doc/index.rst @@ -55,8 +55,18 @@ features: +-----------+------------+-------------------------------------+ | ARM TIMER | on-chip | system clock | +-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| RDC | on-chip | Resource Domain Controller | ++-----------+------------+-------------------------------------+ | UART | on-chip | serial port | +-----------+------------+-------------------------------------+ +| GPT | on-chip | timer | ++-----------+------------+-------------------------------------+ +| ENET | on-chip | ethernet port | ++-----------+------------+-------------------------------------+ Devices ======== diff --git a/boards/nxp/imx8mn_evk/imx8mn_evk-pinctrl.dtsi b/boards/nxp/imx8mn_evk/imx8mn_evk-pinctrl.dtsi index ea200728c8a..23326b53f8f 100644 --- a/boards/nxp/imx8mn_evk/imx8mn_evk-pinctrl.dtsi +++ b/boards/nxp/imx8mn_evk/imx8mn_evk-pinctrl.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2022 NXP + * Copyright 2022,2024 NXP * SPDX-License-Identifier: Apache-2.0 * */ @@ -12,7 +12,7 @@ pinmux = <&iomuxc_uart2_rxd_uart_rx_uart2_rx>, <&iomuxc_uart2_txd_uart_tx_uart2_tx>; slew-rate = "fast"; - drive-strength = "40-ohm"; + drive-strength = "x6"; }; }; @@ -21,8 +21,46 @@ pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx>, <&iomuxc_uart4_txd_uart_tx_uart4_tx>; slew-rate = "fast"; - drive-strength = "40-ohm"; + drive-strength = "x6"; }; }; + pinmux_enet: pinmux_enet { + group0 { + pinmux = <&iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0>, + <&iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1>, + <&iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2>, + <&iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3>, + <&iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc>, + <&iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl>; + slew-rate = "fast"; + drive-strength = "x6"; + }; + + group1 { + pinmux = <&iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0>, + <&iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1>, + <&iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2>, + <&iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3>, + <&iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc>, + <&iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl>; + slew-rate = "fast"; + drive-strength = "x1"; + }; + + group2 { + pinmux = <&iomuxc_sai2_rxc_gpio_io_gpio4_io22>; + slew-rate = "fast"; + drive-strength = "x1"; + }; + }; + + pinmux_mdio: pinmux_mdio { + group0 { + pinmux = <&iomuxc_enet_mdc_enet_mdc_enet1_mdc>, + <&iomuxc_enet_mdio_enet_mdio_enet1_mdio>; + slew-rate = "slow"; + drive-strength = "x6"; + }; + }; }; diff --git a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.dts b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.dts index 2927ff9d1ca..08fd3d7b19c 100644 --- a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.dts +++ b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.dts @@ -1,5 +1,5 @@ /* - * Copyright 2022 NXP + * Copyright 2022,2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -36,6 +36,30 @@ }; }; +&enet { + status = "okay"; +}; + +&enet_mac { + pinctrl-0 = <&pinmux_enet>; + pinctrl-names = "default"; + phy-handle = <&phy>; + zephyr,random-mac-address; + phy-connection-type = "rgmii"; + status = "okay"; +}; + +&enet_mdio { + pinctrl-0 = <&pinmux_mdio>; + pinctrl-names = "default"; + status = "okay"; + phy: phy@0 { + compatible = "qca,ar8031"; + reg = <0>; + status = "okay"; + }; +}; + &uart4 { current-speed = <115200>; pinctrl-0 = <&uart4_default>; diff --git a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_defconfig b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_defconfig index 4e31bf4e946..03f34114970 100644 --- a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_defconfig +++ b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_defconfig @@ -13,6 +13,7 @@ CONFIG_ICACHE_LINE_SIZE_DETECT=y # Zephyr Kernel Configuration CONFIG_XIP=n +CONFIG_KERNEL_DIRECT_MAP=y # Serial Drivers CONFIG_SERIAL=y diff --git a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp.dts b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp.dts index 3dbc8b593ae..0d115e359bc 100644 --- a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp.dts +++ b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp.dts @@ -1,5 +1,5 @@ /* - * Copyright 2022 NXP + * Copyright 2022,2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -38,6 +38,30 @@ }; }; +&enet { + status = "okay"; +}; + +&enet_mac { + pinctrl-0 = <&pinmux_enet>; + pinctrl-names = "default"; + phy-handle = <&phy>; + zephyr,random-mac-address; + phy-connection-type = "rgmii"; + status = "okay"; +}; + +&enet_mdio { + pinctrl-0 = <&pinmux_mdio>; + pinctrl-names = "default"; + status = "okay"; + phy: phy@0 { + compatible = "qca,ar8031"; + reg = <0>; + status = "okay"; + }; +}; + &uart4 { current-speed = <115200>; pinctrl-0 = <&uart4_default>; diff --git a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp_defconfig b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp_defconfig index 845b48736a7..3c7bc851bf3 100644 --- a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp_defconfig +++ b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp_defconfig @@ -13,6 +13,7 @@ CONFIG_ICACHE_LINE_SIZE_DETECT=y # Zephyr Kernel Configuration CONFIG_XIP=n +CONFIG_KERNEL_DIRECT_MAP=y # SMP CONFIG_SMP=y diff --git a/boards/nxp/imx8mp_evk/Kconfig.defconfig b/boards/nxp/imx8mp_evk/Kconfig.defconfig index 3fdc7b3cd9c..8dcef5acccd 100644 --- a/boards/nxp/imx8mp_evk/Kconfig.defconfig +++ b/boards/nxp/imx8mp_evk/Kconfig.defconfig @@ -1,15 +1,44 @@ -# MIMX8MP EVK board defconfig - -# Copyright (c) 2021, Laird Connectivity +# Copyright 2024 NXP # SPDX-License-Identifier: Apache-2.0 -if BOARD_IMX8MP_EVK_MIMX8ML8_M7 || BOARD_IMX8MP_EVK_MIMX8ML8_M7_DDR +if BOARD_IMX8MP_EVK + +if BOARD_IMX8MP_EVK_MIMX8ML8_A53 || BOARD_IMX8MP_EVK_MIMX8ML8_A53_SMP + +if NETWORKING + +config NET_L2_ETHERNET + default y + +config NET_TX_STACK_SIZE + default 8192 + +config NET_RX_STACK_SIZE + default 8192 + +if NET_TCP + +config NET_TCP_WORKQ_STACK_SIZE + default 8192 + +endif # NET_TCP + +if NET_MGMT_EVENT + +config NET_MGMT_EVENT_STACK_SIZE + default 8192 + +endif # NET_MGMT_EVENT + +if NET_SOCKETS_SERVICE + +config NET_SOCKETS_SERVICE_STACK_SIZE + default 8192 + +endif # NET_SOCKETS_SERVICE + +endif # NETWORKING -if !XIP -config FLASH_SIZE - default 0 -config FLASH_BASE_ADDRESS - default 0 -endif +endif # BOARD_IMX8MP_EVK_MIMX8ML8_A53 || BOARD_IMX8MP_EVK_MIMX8ML8_A53_SMP -endif # BOARD_IMX8MP_EVK_MIMX8ML8_M7 || BOARD_IMX8MP_EVK_MIMX8ML8_M7_DDR +endif # BOARD_IMX8MP_EVK diff --git a/boards/nxp/imx8mp_evk/doc/index.rst b/boards/nxp/imx8mp_evk/doc/index.rst index 6d6e1b7b556..69a9b463b74 100644 --- a/boards/nxp/imx8mp_evk/doc/index.rst +++ b/boards/nxp/imx8mp_evk/doc/index.rst @@ -55,8 +55,16 @@ features: +-----------+------------+-------------------------------------+ | ARM TIMER | on-chip | system clock | +-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| RDC | on-chip | Resource Domain Controller | ++-----------+------------+-------------------------------------+ | UART | on-chip | serial port | +-----------+------------+-------------------------------------+ +| ENET | on-chip | ethernet port | ++-----------+------------+-------------------------------------+ The Zephyr mimx8mp_evk_m7 board configuration supports the following hardware features: @@ -173,6 +181,11 @@ At compilation time you have to choose which RAM will be used. This configuration is done based on board name (imx8mp_evk/mimx8ml8/m7 for ITCM and imx8mp_evk/mimx8ml8/m7/ddr for DDR). +There are two methods to load M7 Core images: U-Boot command and Linux remoteproc. + +Load and Run M7 Zephyr Image from U-Boot +======================================== + Load and run Zephyr on M7 from A53 using u-boot by copying the compiled ``zephyr.bin`` to the first FAT partition of the SD card and plug the SD card into the board. Power it up and stop the u-boot execution at prompt. @@ -180,7 +193,7 @@ card into the board. Power it up and stop the u-boot execution at prompt. Load the M7 binary onto the desired memory and start its execution using: ITCM -=== +==== .. code-block:: console @@ -197,6 +210,86 @@ DDR dcache flush bootaux 0x80000000 +Load and Run M7 Zephyr Image by using Linux remoteproc +====================================================== + +Prepare device tree: + +The device tree must inlcude CM7 dts node with compatible string "fsl,imx8mn-cm7", +and also need to reserve M4 DDR memory if using DDR code and sys address, and also +need to put "m4_reserved" in the list of memory-region property of the cm7 node. + +.. code-block:: console + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + m7_reserved: m4@80000000 { + no-map; + reg = <0 0x80000000 0 0x1000000>; + }; + ... + } + + + imx8mp-cm7 { + compatible = "fsl,imx8mn-cm7"; + rsc-da = <0x55000000>; + clocks = <&clk IMX8MP_CLK_M7_DIV>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_AUDPLL_ROOT>; + clock-names = "core", "audio"; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>, <&m7_reserved>; + status = "okay"; + fsl,startup-delay-ms = <500>; + }; + +Extra Zephyr Kernel configure item for DDR Image: + +If use remotepoc to boot DDR board (imx8mp_evk/mimx8ml8/m7/ddr), also need to enable +"CONFIG_ROMSTART_RELOCATION_ROM" in order to put romstart memory section into ITCM because +M7 Core will get the first instruction from zero address of ITCM, but romstart relocation +will make the storage size of zephyr.bin too large, so we don't enable it by default in +board defconfig. + +.. code-block:: console + + diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr_defconfig b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr_defconfig + index 17542cb4eec..8c30c5b6fa3 100644 + --- a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr_defconfig + +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr_defconfig + @@ -12,3 +12,4 @@ CONFIG_CONSOLE=y + CONFIG_XIP=y + CONFIG_CODE_DDR=y + CONFIG_PINCTRL=y + +CONFIG_ROMSTART_RELOCATION_ROM=y + +Then use the following steps to boot Zephyr kernel: + +1. In U-Boot command line execute prepare script: + +.. code-block:: console + + u-boot=> run prepare_mcore + +2. Boot Linux kernel with specified dtb and then boot Zephyr by using remoteproc: + +.. code-block:: console + + root@imx8mp-lpddr4-evk:~# echo zephyr.elf > /sys/devices/platform/imx8mp-cm7/remoteproc/remoteproc0/firmware + root@imx8mp-lpddr4-evk:~# echo start > /sys/devices/platform/imx8mp-cm7/remoteproc/remoteproc0/state + [ 39.195651] remoteproc remoteproc0: powering up imx-rproc + [ 39.203345] remoteproc remoteproc0: Booting fw image zephyr.elf, size 503992 + [ 39.203388] remoteproc remoteproc0: No resource table in elf + root@imx8mp-lpddr4-evk:~# [ 39.711380] remoteproc remoteproc0: remote processor imx-rproc is now up + + root@imx8mp-lpddr4-evk:~# + Debugging ========= @@ -204,7 +297,7 @@ MIMX8MP EVK board can be debugged by connecting an external JLink JTAG debugger to the J24 debug connector and to the PC. Then the application can be debugged using the usual way. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -226,4 +319,4 @@ References https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-plus-applications-processor:8MPLUSLPD4-EVK .. _i.MX 8M Applications Processor Reference Manual: - https://www.nxp.com/docs/en/reference-manual/IMX8MPRM.pdf + https://www.nxp.com/webapp/Download?colCode=IMX8MPRM diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk-pinctrl.dtsi b/boards/nxp/imx8mp_evk/imx8mp_evk-pinctrl.dtsi index 949b622affb..f88555b13e2 100644 --- a/boards/nxp/imx8mp_evk/imx8mp_evk-pinctrl.dtsi +++ b/boards/nxp/imx8mp_evk/imx8mp_evk-pinctrl.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, NXP + * Copyright 2022-2024 NXP * SPDX-License-Identifier: Apache-2.0 * */ @@ -26,4 +26,44 @@ drive-strength = "x1"; }; }; + + pinmux_mdio: pinmux_mdio { + group0 { + pinmux = <&iomuxc_sai1_rxd2_enet_mdc_enet1_mdc>, + <&iomuxc_sai1_rxd3_enet_mdio_enet1_mdio>; + slew-rate = "slow"; + drive-strength = "x4"; + }; + }; + + pinmux_enet: pinmux_enet { + group0 { + pinmux = <&iomuxc_sai1_rxd4_enet_rgmii_rd_enet1_rgmii_rd0>, + <&iomuxc_sai1_rxd5_enet_rgmii_rd_enet1_rgmii_rd1>, + <&iomuxc_sai1_rxd6_enet_rgmii_rd_enet1_rgmii_rd2>, + <&iomuxc_sai1_rxd7_enet_rgmii_rd_enet1_rgmii_rd3>, + <&iomuxc_sai1_txc_enet_rgmii_rxc_enet1_rgmii_rxc>, + <&iomuxc_sai1_txfs_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl>; + input-schmitt-enable; + slew-rate = "fast"; + drive-strength = "x1"; + }; + + group1 { + pinmux = <&iomuxc_sai1_txd0_enet_rgmii_td_enet1_rgmii_td0>, + <&iomuxc_sai1_txd1_enet_rgmii_td_enet1_rgmii_td1>, + <&iomuxc_sai1_txd2_enet_rgmii_td_enet1_rgmii_td2>, + <&iomuxc_sai1_txd3_enet_rgmii_td_enet1_rgmii_td3>, + <&iomuxc_sai1_txd4_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl>, + <&iomuxc_sai1_txd5_enet_rgmii_txc_enet1_rgmii_txc>; + slew-rate = "fast"; + drive-strength = "x6"; + }; + + group2 { + pinmux = <&iomuxc_sai1_rxd0_gpio_io_gpio4_io2>; + slew-rate = "fast"; + drive-strength = "x1"; + }; + }; }; diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.dts b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.dts index 18cff6569d4..692435c87d3 100644 --- a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.dts +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.dts @@ -1,5 +1,5 @@ /* - * Copyright 2021-2022 NXP + * Copyright 2021-2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -34,6 +34,31 @@ sram0: memory@c0000000 { reg = <0xc0000000 DT_SIZE_M(1)>; }; + +}; + +&enet { + status = "okay"; +}; + +&enet_mac { + pinctrl-0 = <&pinmux_enet>; + pinctrl-names = "default"; + phy-handle = <&phy>; + zephyr,random-mac-address; + phy-connection-type = "rgmii"; + status = "okay"; +}; + +&enet_mdio { + pinctrl-0 = <&pinmux_mdio>; + pinctrl-names = "default"; + status = "okay"; + phy: phy@1 { + compatible = "realtek,rtl8211f"; + reg = <1>; + status = "okay"; + }; }; &uart4 { diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_defconfig b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_defconfig index 4e31bf4e946..03f34114970 100644 --- a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_defconfig +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_defconfig @@ -13,6 +13,7 @@ CONFIG_ICACHE_LINE_SIZE_DETECT=y # Zephyr Kernel Configuration CONFIG_XIP=n +CONFIG_KERNEL_DIRECT_MAP=y # Serial Drivers CONFIG_SERIAL=y diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp.dts b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp.dts index 0137c60d611..3822987d2a4 100644 --- a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp.dts +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp.dts @@ -39,6 +39,30 @@ }; +&enet { + status = "okay"; +}; + +&enet_mac { + pinctrl-0 = <&pinmux_enet>; + pinctrl-names = "default"; + phy-handle = <&phy>; + zephyr,random-mac-address; + phy-connection-type = "rgmii"; + status = "okay"; +}; + +&enet_mdio { + pinctrl-0 = <&pinmux_mdio>; + pinctrl-names = "default"; + status = "okay"; + phy: phy@1 { + compatible = "realtek,rtl8211f"; + reg = <1>; + status = "okay"; + }; +}; + &uart4 { current-speed = <115200>; pinctrl-0 = <&uart4_default>; diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp_defconfig b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp_defconfig index 845b48736a7..3c7bc851bf3 100644 --- a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp_defconfig +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp_defconfig @@ -13,6 +13,7 @@ CONFIG_ICACHE_LINE_SIZE_DETECT=y # Zephyr Kernel Configuration CONFIG_XIP=n +CONFIG_KERNEL_DIRECT_MAP=y # SMP CONFIG_SMP=y diff --git a/boards/nxp/imx8mq_evk/Kconfig.defconfig b/boards/nxp/imx8mq_evk/Kconfig.defconfig deleted file mode 100644 index 054cfde7fb7..00000000000 --- a/boards/nxp/imx8mq_evk/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# MIMX8MQ EVK board defconfig - -# Copyright (c) 2021, Kwon Tae-young -# Copyright 2024 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_IMX8MQ_EVK - -if !XIP -config FLASH_SIZE - default 0 -config FLASH_BASE_ADDRESS - default 0 -endif - -endif # BOARD_IMX8MQ_EVK diff --git a/boards/nxp/imx8mq_evk/doc/index.rst b/boards/nxp/imx8mq_evk/doc/index.rst index 40bd5ac5c50..8f21c6e9328 100644 --- a/boards/nxp/imx8mq_evk/doc/index.rst +++ b/boards/nxp/imx8mq_evk/doc/index.rst @@ -190,7 +190,7 @@ MIMX8MQ EVK board can be debugged by connecting an external JLink JTAG debugger to the J401 debug connector and to the PC. Then the application can be debugged using the usual way. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/imx93_evk/CMakeLists.txt b/boards/nxp/imx93_evk/CMakeLists.txt index 9881313609a..218a0602483 100644 --- a/boards/nxp/imx93_evk/CMakeLists.txt +++ b/boards/nxp/imx93_evk/CMakeLists.txt @@ -1 +1,4 @@ # SPDX-License-Identifier: Apache-2.0 + +zephyr_library() +zephyr_library_sources(board.c) diff --git a/boards/nxp/imx93_evk/Kconfig b/boards/nxp/imx93_evk/Kconfig new file mode 100644 index 00000000000..78598d24b2a --- /dev/null +++ b/boards/nxp/imx93_evk/Kconfig @@ -0,0 +1,16 @@ +# i.MX 93 EVK board configuration + +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIMX93_EVK_EXP_SEL_INIT + bool "Configure i.MX 93 EVK board mux control during init" + default n + +config BOARD_MIMX93_EVK_EXP_SEL_INIT_PRIO + int "i.MX 93 EVK board mux control init priority" + default 60 + +module = BOARD_MIMX93_EVK +module-str = Board Control +source "subsys/logging/Kconfig.template.log_config" diff --git a/boards/nxp/imx93_evk/Kconfig.defconfig b/boards/nxp/imx93_evk/Kconfig.defconfig new file mode 100644 index 00000000000..06b3e06736d --- /dev/null +++ b/boards/nxp/imx93_evk/Kconfig.defconfig @@ -0,0 +1,70 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_IMX93_EVK + +if BOARD_IMX93_EVK_MIMX9352_A55 + +if CAN + +# Enable board mux configure during init +config BOARD_MIMX93_EVK_EXP_SEL_INIT + default y + +# CAN Phy must be initialized after board mux +config CAN_TRANSCEIVER_INIT_PRIORITY + default 65 + +endif # CAN + +if BOARD_MIMX93_EVK_EXP_SEL_INIT + +# Enable I2C, MFD, MFD_APD5585 and GPIO_ADP5585 +config GPIO + default y + +config MFD_ADP5585_INIT_PRIORITY + default 55 + +config GPIO_ADP5585_INIT_PRIORITY + default 56 + +endif # BOARD_MIMX93_EVK_EXP_SEL_INIT + +if NETWORKING + +config NET_L2_ETHERNET + default y + +config NET_TX_STACK_SIZE + default 8192 + +config NET_RX_STACK_SIZE + default 8192 + +if NET_TCP + +config NET_TCP_WORKQ_STACK_SIZE + default 8192 + +endif # NET_TCP + +if NET_MGMT_EVENT + +config NET_MGMT_EVENT_STACK_SIZE + default 8192 + +endif # NET_MGMT_EVENT + +if NET_SOCKETS_SERVICE + +config NET_SOCKETS_SERVICE_STACK_SIZE + default 8192 + +endif # NET_SOCKETS_SERVICE + +endif # NETWORKING + +endif # BOARD_IMX93_EVK_MIMX9352_A55 + +endif # BOARD_IMX93_EVK diff --git a/boards/nxp/imx93_evk/Kconfig.imx93_evk b/boards/nxp/imx93_evk/Kconfig.imx93_evk index 0115518a6d2..412da581ac6 100644 --- a/boards/nxp/imx93_evk/Kconfig.imx93_evk +++ b/boards/nxp/imx93_evk/Kconfig.imx93_evk @@ -3,4 +3,5 @@ config BOARD_IMX93_EVK select SOC_MIMX9352_A55 if BOARD_IMX93_EVK_MIMX9352_A55 - select SOC_PART_NUMBER_MIMX9352CVUXK + select SOC_MIMX9352_M33 if BOARD_IMX93_EVK_MIMX9352_M33 + select SOC_PART_NUMBER_MIMX9352DVVXM diff --git a/boards/nxp/imx93_evk/board.c b/boards/nxp/imx93_evk/board.c new file mode 100644 index 00000000000..169b6899849 --- /dev/null +++ b/boards/nxp/imx93_evk/board.c @@ -0,0 +1,56 @@ +/** + * Copyright 2024 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(board_control, CONFIG_BOARD_MIMX93_EVK_LOG_LEVEL); + +#if DT_HAS_COMPAT_STATUS_OKAY(imx93evk_exp_sel) && IS_ENABLED(CONFIG_BOARD_MIMX93_EVK_EXP_SEL_INIT) + +#define BOARD_EXP_SEL_NODE DT_COMPAT_GET_ANY_STATUS_OKAY(imx93evk_exp_sel) + +#define BOARD_EXP_SEL_MUX_A (0U) +#define BOARD_EXP_SEL_MUX_B (1U) + +static int board_init_exp_sel(void) +{ + int rc = 0; + const struct gpio_dt_spec mux = GPIO_DT_SPEC_GET(BOARD_EXP_SEL_NODE, mux_gpios); + uint32_t pin_state = DT_ENUM_IDX(BOARD_EXP_SEL_NODE, mux); + + if (!gpio_is_ready_dt(&mux)) { + LOG_ERR("EXP_SEL Pin port is not ready"); + return -ENODEV; + } + +#if defined(CONFIG_CAN) + if (pin_state != BOARD_EXP_SEL_MUX_A) { + LOG_WRN("CAN is enabled, EXP_SEL overrides to A"); + pin_state = BOARD_EXP_SEL_MUX_A; + } +#endif /* CONFIG_CAN */ + + rc = gpio_pin_configure_dt(&mux, pin_state); + if (rc) { + LOG_ERR("Write EXP_SEL Pin error %d", rc); + return rc; + } + LOG_INF("EXP_SEL mux %c with priority %d", pin_state ? 'B' : 'A', + CONFIG_BOARD_MIMX93_EVK_EXP_SEL_INIT_PRIO); + + return 0; +} + +SYS_INIT(board_init_exp_sel, POST_KERNEL, CONFIG_BOARD_MIMX93_EVK_EXP_SEL_INIT_PRIO); + +#endif +/* + * DT_HAS_COMPAT_STATUS_OKAY(imx93evk_exp_sel) && \ + * IS_ENABLED(CONFIG_BOARD_MIMX93_EVK_EXP_SEL_INIT) + */ diff --git a/boards/nxp/imx93_evk/doc/index.rst b/boards/nxp/imx93_evk/doc/index.rst index 0fdeb237ec2..c37ad2eea1e 100644 --- a/boards/nxp/imx93_evk/doc/index.rst +++ b/boards/nxp/imx93_evk/doc/index.rst @@ -1,7 +1,7 @@ .. _imx93_evk: -NXP i.MX93 EVK (Cortex-A55) -############################ +NXP i.MX93 EVK +############## Overview ******** @@ -48,8 +48,8 @@ Cortex®-M33 core. Zephyr OS is ported to run on one of the Cortex®-A55 core. Supported Features ================== -The Zephyr mimx93_evk board configuration supports the following hardware -features: +The Zephyr mimx93_evk board Cortex-A Core configuration supports the following +hardware features: +-----------+------------+-------------------------------------+ | Interface | Controller | Driver/Component | @@ -58,8 +58,43 @@ features: +-----------+------------+-------------------------------------+ | ARM TIMER | on-chip | system clock | +-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | GPIO | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | can | ++-----------+------------+-------------------------------------+ +| TPM | on-chip | TPM Counter | ++-----------+------------+-------------------------------------+ +| ENET | on-chip | ethernet port | ++-----------+------------+-------------------------------------+ + +The Zephyr imx93_evk board Cortex-M33 configuration supports the following +hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ | UART | on-chip | serial port | +-----------+------------+-------------------------------------+ +| GPIO | on-chip | GPIO | ++-----------+------------+-------------------------------------+ Devices ======== @@ -68,15 +103,45 @@ System Clock This board configuration uses a system clock frequency of 24 MHz. Cortex-A55 Core runs up to 1.7 GHz. +Cortex-M33 Core runs up to 200MHz in which SYSTICK runs on same frequency. Serial Port ----------- This board configuration uses a single serial communication channel with the -CPU's UART4. +CPU's UART2 for A55 core and M33 core. + +Board MUX Control +----------------- + +This board configuration uses a series of digital multiplexers to switch between +different board functions. The multiplexers are controlled by a GPIO signal called +``EXP_SEL`` from onboard GPIO expander ADP5585. It can be configured to select +function set "A" or "B" by dts configuration if board control module is enabled. +The following dts node is defined: + +.. code-block:: dts -Programming and Debugging -************************* + board_exp_sel: board-exp-sel { + compatible = "imx93evk-exp-sel"; + mux-gpios = <&gpio_exp0 4 GPIO_ACTIVE_HIGH>; + mux = "A"; + }; + +Following steps are required to configure the ``EXP_SEL`` signal: + +1. Enable Kconfig option ``CONFIG_BOARD_MIMX93_EVK_EXP_SEL_INIT``. +2. Select ``mux="A";`` or ``mux="B";`` in ``&board_exp_sel`` devicetree node. + +Kconfig option ``CONFIG_BOARD_MIMX93_EVK_EXP_SEL_INIT`` is enabled if a board +function that requires configuring the mux is enabled. The MUX option is +automatically selected if certain board function is enabled, and takes precedence +over dts config. For instance, if ``CONFIG_CAN`` is enabled, MUX A is selected +even if ``mux="B";`` is configured in dts, and an warning would be reported in +the log. + +Programming and Debugging (A55) +******************************* Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and plug the SD card into the board. Power it up and stop the u-boot execution at @@ -102,19 +167,78 @@ for example, with the :zephyr:code-sample:`synchronization` sample: .. zephyr-app-commands:: :zephyr-app: samples/synchronization :host-os: unix - :board: mimx93_evk/mimx9352/a55 + :board: imx93_evk/mimx9352/a55 + :goals: build + +This will build an image with the synchronization sample app, boot it and +display the following console output: + +.. code-block:: console + + *** Booting Zephyr OS build Booting Zephyr OS build v3.7.0-2055-g630f27a5a867 *** + thread_a: Hello World from cpu 0 on imx93_evk! + thread_b: Hello World from cpu 0 on imx93_evk! + thread_a: Hello World from cpu 0 on imx93_evk! + thread_b: Hello World from cpu 0 on imx93_evk! + +System Reboot (A55) +=================== + +Currently i.MX93 only support cold reboot and doesn't support warm reboot. +Use this configuratiuon to verify cold reboot with :zephyr:code-sample:`shell-module` +sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/subsys/shell/shell_module + :host-os: unix + :board: imx93_evk/mimx9352/a55 + :goals: build + +This will build an image with the shell sample app, boot it and execute +kernel reboot command in shell command line: + +.. code-block:: console + + uart:~$ kernel reboot cold + +Programming and Debugging (M33) +******************************* + +Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and +plug the SD card into the board. Power it up and stop the u-boot execution at +prompt. + +Use U-Boot to load and kick zephyr.bin to Cortex-M33 Core: + +.. code-block:: console + + load mmc 1:1 0x80000000 zephyr.bin;cp.b 0x80000000 0x201e0000 0x30000;bootaux 0x1ffe0000 0 + +Use this configuration to run basic Zephyr applications and kernel tests, +for example, with the :zephyr:code-sample:`synchronization` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: imx93_evk/mimx9352/m33 :goals: run This will build an image with the synchronization sample app, boot it and -display the following ram console output: +display the following console output: .. code-block:: console - *** Booting Zephyr OS build zephyr-v3.2.0-8-g1613870534a0 *** - thread_a: Hello World from cpu 0 on mimx93_evk_a55! - thread_b: Hello World from cpu 0 on mimx93_evk_a55! - thread_a: Hello World from cpu 0 on mimx93_evk_a55! - thread_b: Hello World from cpu 0 on mimx93_evk_a55! + *** Booting Zephyr OS build v3.7.0-684-g71a7d05ba60a *** + thread_a: Hello World from cpu 0 on imx93_evk! + thread_b: Hello World from cpu 0 on imx93_evk! + thread_a: Hello World from cpu 0 on imx93_evk! + thread_b: Hello World from cpu 0 on imx93_evk! + +To make a container image flash.bin with ``zephyr.bin`` for SD/eMMC programming and booting +from BootROM. Refer to user manual of i.MX93 `MCUX SDK release`_. + +.. _MCUX SDK release: + https://mcuxpresso.nxp.com/ References ========== diff --git a/boards/nxp/imx93_evk/dts/bindings/imx93evk-exp-sel.yaml b/boards/nxp/imx93_evk/dts/bindings/imx93evk-exp-sel.yaml new file mode 100644 index 00000000000..4f30d126b47 --- /dev/null +++ b/boards/nxp/imx93_evk/dts/bindings/imx93evk-exp-sel.yaml @@ -0,0 +1,25 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +description: | + The i.MX 93 EVK boards has a series of MUXes that selects between 2 pin + functions. They are controlled by EXP_SEL signal from gpio_exp0, an + ADP5585 GPIO expander. + +compatible: "imx93evk-exp-sel" + +include: base.yaml + +properties: + mux-gpios: + type: phandle-array + required: true + description: Pin used to select the MUX + + mux: + type: string + required: true + enum: + - "A" + - "B" + description: MUX choice diff --git a/boards/nxp/imx93_evk/imx93_evk-pinctrl.dtsi b/boards/nxp/imx93_evk/imx93_evk-pinctrl.dtsi index 31e35907f86..8976def98b4 100644 --- a/boards/nxp/imx93_evk/imx93_evk-pinctrl.dtsi +++ b/boards/nxp/imx93_evk/imx93_evk-pinctrl.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, NXP + * Copyright 2022,2024 NXP * SPDX-License-Identifier: Apache-2.0 * */ @@ -83,4 +83,50 @@ }; }; + flexcan2_default: flexcan2_default { + group0 { + pinmux = <&iomuxc1_gpio_io25_can_tx_can2_tx>, + <&iomuxc1_gpio_io27_can_rx_can2_rx>; + slew-rate = "slightly_fast"; + drive-strength = "x5"; + }; + }; + + pinmux_mdio: pinmux_mdio { + group0 { + pinmux = <&iomuxc1_enet2_mdc_enet_mdc_enet1_mdc>, + <&iomuxc1_enet2_mdio_enet_mdio_enet1_mdio>; + bias-pull-down; + slew-rate = "slightly_fast"; + drive-strength = "x6"; + }; + }; + + pinmux_enet: pinmux_enet { + group0 { + pinmux = <&iomuxc1_enet2_rd0_enet_rgmii_rd_enet1_rgmii_rd0>, + <&iomuxc1_enet2_rd1_enet_rgmii_rd_enet1_rgmii_rd1>, + <&iomuxc1_enet2_rd2_enet_rgmii_rd_enet1_rgmii_rd2>, + <&iomuxc1_enet2_rd3_enet_rgmii_rd_enet1_rgmii_rd3>, + <&iomuxc1_enet2_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl>, + <&iomuxc1_enet2_td0_enet_rgmii_td_enet1_rgmii_td0>, + <&iomuxc1_enet2_td1_enet_rgmii_td_enet1_rgmii_td1>, + <&iomuxc1_enet2_td2_enet_rgmii_td_enet1_rgmii_td2>, + <&iomuxc1_enet2_td3_enet_rgmii_td_enet1_rgmii_td3>, + <&iomuxc1_enet2_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl>; + bias-pull-down; + slew-rate = "slightly_fast"; + drive-strength = "x6"; + }; + + group1 { + pinmux = <&iomuxc1_enet2_rxc_enet_rgmii_rxc_enet1_rgmii_rxc>, + <&iomuxc1_enet2_txc_enet_rgmii_txc_enet1_rgmii_txc>; + bias-pull-down; + slew-rate = "fast"; + drive-strength = "x6"; + }; + + }; + }; diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts index cd025a547e7..8fbf9edf6ba 100644 --- a/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts +++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts @@ -17,6 +17,7 @@ zephyr,console = &lpuart2; zephyr,shell-uart = &lpuart2; zephyr,sram = &sram0; + zephyr,canbus = &flexcan2; }; cpus { @@ -64,6 +65,48 @@ gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; }; }; + + board_exp_sel: board-exp-sel { + /* + * Kconfig BOARD_MIMX93_EVK_A55_EXP_SEL_INIT must be + * enabled to configure it during init. + */ + compatible = "imx93evk-exp-sel"; + mux-gpios = <&gpio_exp0 4 GPIO_ACTIVE_HIGH>; + mux = "A"; + }; + + can_phy0: can-phy0 { + compatible = "nxp,tja1057", "can-transceiver-gpio"; + standby-gpios = <&gpio_exp0 8 GPIO_ACTIVE_HIGH>; + max-bitrate = <8000000>; + #phy-cells = <0>; + status = "okay"; + }; +}; + +&enet { + status = "okay"; +}; + +&enet_mac { + pinctrl-0 = <&pinmux_enet>; + pinctrl-names = "default"; + phy-handle = <&phy>; + zephyr,random-mac-address; + phy-connection-type = "rgmii"; + status = "okay"; +}; + +&enet_mdio { + pinctrl-0 = <&pinmux_mdio>; + pinctrl-names = "default"; + status = "okay"; + phy: phy@2 { + compatible = "realtek,rtl8211f"; + reg = <2>; + status = "okay"; + }; }; &lpuart1 { @@ -91,7 +134,7 @@ }; &lpi2c2 { - status = "disabled"; + status = "okay"; clock-frequency = ; pinctrl-0 = <&i2c2_default>; pinctrl-names = "default"; @@ -99,7 +142,7 @@ mfd0:adp5585@34 { compatible = "adi,adp5585"; reg = <0x34>; - status = "disabled"; + status = "okay"; gpio_exp0: adp5585_gpio { compatible = "adi,adp5585-gpio"; @@ -107,21 +150,24 @@ #gpio-cells = <2>; ngpios = <13>; gpio-reserved-ranges = <5 3>; + status = "okay"; /* * This device has non-contiguous gpio range: * GPIO Pin R0~R4 are gpio0~4 * GPIO Pin C0~C4 are gpio8~12 */ - - gpiohog_exp_sel: exp-sel-hog { - gpio-hog; - gpios = <4 GPIO_ACTIVE_HIGH>; - line-name = "exp_sel"; - output-low; - }; - status = "disabled"; }; }; + + gpio_exp1: pcal6524@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <24>; + int-gpios = <&gpio3 27 (GPIO_ACTIVE_LOW|GPIO_PULL_UP)>; + status = "okay"; + }; }; &lpspi3 { @@ -146,3 +192,10 @@ &gpio4{ status = "okay"; }; + +&flexcan2 { + pinctrl-0 = <&flexcan2_default>; + pinctrl-names = "default"; + phys = <&can_phy0>; + status = "okay"; +}; diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.yaml b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.yaml index 3a045828f84..89cc546d7b3 100644 --- a/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.yaml +++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.yaml @@ -5,7 +5,7 @@ # identifier: imx93_evk/mimx9352/a55 -name: NXP i.MX93 Plus EVK A55 +name: NXP i.MX93 EVK A55 type: mcu arch: arm64 toolchain: @@ -17,6 +17,7 @@ supported: - uart - i2c - spi + - can testing: ignore_tags: - net diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33.dts b/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33.dts new file mode 100644 index 00000000000..5c75e10ccc9 --- /dev/null +++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33.dts @@ -0,0 +1,83 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "imx93_evk-pinctrl.dtsi" + +/ { + model = "NXP i.MX93 EVK board"; + compatible = "nxp,imx93_evk"; + + chosen { + /* TCM */ + zephyr,flash = &itcm; + zephyr,sram = &dtcm; + + zephyr,console = &lpuart2; + zephyr,shell-uart = &lpuart2; + }; + + aliases { + led0 = &led_r; + led1 = &led_g; + sw0 = &btn_1; + }; + + leds { + compatible = "gpio-leds"; + led_r: led_r { + label = "LED_R"; + gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; + }; + led_g: led_g { + label = "LED_G"; + gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; + }; + led_b: led_b { + label = "LED_B"; + gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; + }; + }; + + keys { + compatible = "gpio-keys"; + + btn_1: btn_1{ + label = "BTN1"; + gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + }; + + btn_2: btn_2{ + label = "BTN2"; + gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&lpuart2 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart2_default>; + pinctrl-names = "default"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33.yaml b/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33.yaml new file mode 100644 index 00000000000..b450925b272 --- /dev/null +++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33.yaml @@ -0,0 +1,16 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +identifier: imx93_evk/mimx9352/m33 +name: NXP i.MX93 EVK M33 +type: mcu +arch: arm +toolchain: + - zephyr + - cross-compile +ram: 128 +flash: 128 +supported: + - gpio + - uart +vendor: nxp diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33_defconfig b/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33_defconfig new file mode 100644 index 00000000000..028b1fc71d1 --- /dev/null +++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33_defconfig @@ -0,0 +1,10 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CLOCK_CONTROL=y +CONFIG_PINCTRL=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_XIP=y diff --git a/boards/nxp/imx95_evk/Kconfig.imx95_evk b/boards/nxp/imx95_evk/Kconfig.imx95_evk new file mode 100644 index 00000000000..b37b19bdfc5 --- /dev/null +++ b/boards/nxp/imx95_evk/Kconfig.imx95_evk @@ -0,0 +1,7 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_IMX95_EVK + select SOC_MIMX9596_M7 if BOARD_IMX95_EVK_MIMX9596_M7 || BOARD_IMX95_EVK_MIMX9596_M7_DDR + select SOC_MIMX9596_A55 if BOARD_IMX95_EVK_MIMX9596_A55 || BOARD_IMX95_EVK_MIMX9596_A55_SMP + select SOC_PART_NUMBER_MIMX9596AVZXN diff --git a/boards/nxp/imx95_evk/board.yml b/boards/nxp/imx95_evk/board.yml new file mode 100644 index 00000000000..14909074457 --- /dev/null +++ b/boards/nxp/imx95_evk/board.yml @@ -0,0 +1,10 @@ +board: + name: imx95_evk + vendor: nxp + socs: + - name: mimx9596 + variants: + - name: smp + cpucluster: a55 + - name: ddr + cpucluster: m7 diff --git a/boards/nxp/imx95_evk/doc/index.rst b/boards/nxp/imx95_evk/doc/index.rst new file mode 100644 index 00000000000..078b0abcdac --- /dev/null +++ b/boards/nxp/imx95_evk/doc/index.rst @@ -0,0 +1,283 @@ +.. _imx95_evk: + +NXP i.MX95 EVK +############## + +Overview +******** + +The i.MX95 EVK (IMX95LPD5EVK-19) board is a platform designed to show the +most commonly used features of the i.MX 95 automotive applications processor. +It is an entry-level development board, which helps developers to get familiar +with the processor before investing a large amount of resources in more +specific designs. The i.MX95 device on the board comes in a compact +19 x 19 mm package. + +Hardware +******** + +- i.MX 95 automotive applications processor + + - The processor integrates up to six Arm Cortex-A55 cores, and supports + functional safety with built-in Arm Cortex-M33 and -M7 cores + +- DRAM memory: 128-Gbit LPDDR5 DRAM +- eMMC: 64 GB Micron eMMC +- SPI NOR flash memory: 1 Gbit octal flash memory +- USB interface: Two USB ports: Type-A and Type-C +- Audio codec interface + + - One audio codec WM8962BECSN/R with one TX and RX lane + - One 3.5 mm 4-pole CTIA standard audio jack + - One 4-pin connector to connect speaker + +- Ethernet interface + + - ENET2 controller + + - Connects to a 60-pin Ethernet connector + - Supports Ethernet PHY daughter cards that can be configured to operate + at 100 Mbit/s or 1000 Mbit/s + + - ENET1 controller + + - Supports 100 Mbit/s or 1000 Mbit/s RGMII Ethernet with one RJ45 + connector connected with an external PHY, RTL8211 + + - 10 Gbit Ethernet controller + + - Supports XFI and USXGMII interfaces with one 10 Gbit RJ45 ICM connected + with an external PHY, Marvell AQR113C + +- M.2 interface: One Wi-Fi/Bluetooth Murata Type-2EL module based on NXP AW693 + chip supporting 2x2 Wi-Fi 6 and Bluetooth 5.2 + +- MIPI CSI interface: Connects to one 36-pin miniSAS connector using x4 lane + configuration +- MIPI CSIDSI interface: Connects to one 36-pin miniSAS connector using x4 lane + configuration +- LVDS interface: two mini-SAS connectors each with x4-lane configuration +- CAN interface: Two 4-pin CAN headers for external connection +- SD card interface: one 4-bit SD3.0 microSD card +- I2C interface: I2C1 to I2C7 controllers +- FT4232H I2C interface: PCT2075 temperature sensor and current monitoring devices +- DMIC interface: two digital microphones (DMIC) providing a single-bit PDM output +- ADC interface: two 4-channel ADC header +- Audio board interface + + - Supports PCIe x4 slot for Quantum board connection + - Supports PCIe x8 slot for Audio I/O board connection + +- Debug interface + + - One USB-to-UART/MPSSE device, FT4232H + - One USB 2.0 Type-C connector (J31) for FT4232H provides quad serial ports + +Supported Features +================== + +The Zephyr ``imx95_evk/mimx9596/m7`` board target supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ + +The Zephyr ``imx95_evk/mimx9596/a55`` and ``imx95_evk/mimx9596/a55/smp`` board targets support +the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| GIC-v4 | on-chip | interrupt controller | ++-----------+------------+-------------------------------------+ +| ARM TIMER | on-chip | system clock | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ + +System Clock +------------ + +This board configuration uses a system clock frequency of 24 MHz for Cortex-A55. +Cortex-A55 Core runs up to 1.8 GHz. +Cortex-M7 Core runs up to 800MHz in which SYSTICK runs on same frequency. + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +CPU's UART1 for Cortex-A55, UART3 for Cortex-M7. + +Programming and Debugging (A55) +******************************* + +Use this configuration to run basic Zephyr applications and kernel tests, +for example, with the :zephyr:code-sample:`synchronization` sample: + +1. Build and run the Non-SMP application + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: imx95_evk/mimx9596/a55 + :goals: build + +This will build an image (zephyr.bin) with the synchronization sample app. + +Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and +plug the SD card into the board. Power it up and stop the u-boot execution at +prompt. + +Use U-Boot to load and kick zephyr.bin to Cortex-A55 Core1: + +.. code-block:: console + + fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; cpu 1 release 0xd0000000 + + +Or use the following command to kick zephyr.bin to Cortex-A55 Core0: + +.. code-block:: console + + fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; go 0xd0000000 + + +It will display the following console output: + +.. code-block:: console + + *** Booting Zephyr OS build v3.6.0-4569-g483c01ca11a7 *** + thread_a: Hello World from cpu 0 on imx95_evk! + thread_b: Hello World from cpu 0 on imx95_evk! + thread_a: Hello World from cpu 0 on imx95_evk! + thread_b: Hello World from cpu 0 on imx95_evk! + thread_a: Hello World from cpu 0 on imx95_evk! + +2. Build and run the SMP application + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: imx95_evk/mimx9596/a55/smp + :goals: build + +This will build an image (zephyr.bin) with the synchronization sample app. + +Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and +plug the SD card into the board. Power it up and stop the u-boot execution at +prompt. + +Use the following command to kick zephyr.bin to Cortex-A55 Core0: + +.. code-block:: console + + fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; go 0xd0000000 + + +It will display the following console output: +.. code-block:: console + + *** Booting Zephyr OS build v3.7.0-rc3-15-g2f0beaea144a *** + Secondary CPU core 1 (MPID:0x100) is up + Secondary CPU core 2 (MPID:0x200) is up + Secondary CPU core 3 (MPID:0x300) is up + Secondary CPU core 4 (MPID:0x400) is up + Secondary CPU core 5 (MPID:0x500) is up + thread_a: Hello World from cpu 0 on imx95_evk! + thread_b: Hello World from cpu 4 on imx95_evk! + thread_a: Hello World from cpu 0 on imx95_evk! + thread_b: Hello World from cpu 3 on imx95_evk! + thread_a: Hello World from cpu 0 on imx95_evk! + thread_b: Hello World from cpu 1 on imx95_evk! + thread_a: Hello World from cpu 0 on imx95_evk! + thread_b: Hello World from cpu 5 on imx95_evk! + thread_a: Hello World from cpu 0 on imx95_evk! + thread_b: Hello World from cpu 2 on imx95_evk! + +Programming and Debugging (M7) +****************************** + +The i.MX System Manager (SM) is used on i.MX95, which is an application that runs on +Cortex-M33 processor. The Cortex-M33 is the boot core, runs the boot ROM which loads +the SM (and other boot code), and then branches to the SM. The SM then configures some +aspects of the hardware such as isolation mechanisms and then starts other cores in the +system. After starting these cores, it enters a service mode where it provides access +to clocking, power, sensor, and pin control via a client RPC API based on ARM's +`System Control and Management Interface (SCMI)`_. + +To program M7, an i.MX container image ``flash.bin`` must be made, which contains +multiple elements required, like ELE+V2X firmware, System Manager, TCM OEI, Cortex-M7 +image and so on. + +The steps making flash.bin and programming should refer to ``Getting Started with +MCUXpresso SDK for IMX95LPD5EVK-19.pdf`` in i.MX95 `MCUX SDK release`_. Note that +for the DDR variant, one should use the Makefile targets containing the ``ddr`` keyword. + +See ``4.2 Run an example application``, just rename ``zephyr.bin`` to ``m7_image.bin`` +to make flash.bin and program to SD/eMMC. + +Zephyr supports two M7-based i.MX95 boards: ``imx95_evk/mimx9596/m7`` and +``imx95_evk/mimx9596/m7/ddr``. The main difference between them is the memory +used. ``imx95_evk/mimx9596/m7`` uses TCM (ITCM for code and, generally, read-only +data and DTCM for R/W data), while ``imx95_evk/mimx9596/m7/ddr`` uses DDR. + +1. Building the :zephyr:code-sample:`hello_world` application for the TCM-based board + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: imx95_evk/mimx9596/m7 + :goals: build + +2. Building the :zephyr:code-sample:`hello_world` application for the DDR-based board + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: imx95_evk/mimx9596/m7/ddr + :goals: build + +After making flash.bin and program to SD/eMMC, open a serial terminal, and reset the +board. For the ``imx95_evk/mimx9596/m7`` board you should see something like: + +.. code-block:: console + + *** Booting Zephyr OS build v3.6.0-4569-g483c01ca11a7 *** + Hello World! imx95_evk/mimx9596/m7 + +while, for the ``imx95_evk/mimx9596/m7/ddr`` board, you should get the following output: + +.. code-block:: console + + *** Booting Zephyr OS build v3.6.0-4569-g483c01ca11a7 *** + Hello World! imx95_evk/mimx9596/m7/ddr + +.. _System Control and Management Interface (SCMI): + https://developer.arm.com/documentation/den0056/latest/ + +.. _i.MX Linux BSP release: + https://www.nxp.com/design/design-center/software/embedded-software/i-mx-software/embedded-linux-for-i-mx-applications-processors:IMXLINUX + +.. _MCUX SDK release: + https://mcuxpresso.nxp.com/ + +References +========== + +More information can refer to NXP official website: +`NXP website`_. + +.. _NXP website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-9-processors/i-mx-95-applications-processor-family-high-performance-safety-enabled-platform-with-eiq-neutron-npu:iMX95 diff --git a/boards/nxp/imx95_evk/imx95_evk-pinctrl.dtsi b/boards/nxp/imx95_evk/imx95_evk-pinctrl.dtsi new file mode 100644 index 00000000000..bb4a8db2298 --- /dev/null +++ b/boards/nxp/imx95_evk/imx95_evk-pinctrl.dtsi @@ -0,0 +1,29 @@ +/* + * Copyright 2024 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + + lpuart1_default: lpuart1_default { + group0 { + pinmux = <&iomuxc_uart1_rxd_lpuart_rx_lpuart1_rx>, + <&iomuxc_uart1_txd_lpuart_tx_lpuart1_tx>; + bias-pull-up; + slew-rate = "slightly_fast"; + drive-strength = "x4"; + }; + }; + + lpuart3_default: lpuart3_default { + group0 { + pinmux = <&iomuxc_gpio_io15_lpuart_rx_lpuart3_rx>, + <&iomuxc_gpio_io14_lpuart_tx_lpuart3_tx>; + bias-pull-up; + slew-rate = "slightly_fast"; + drive-strength = "x4"; + }; + }; +}; diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55.dts b/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55.dts new file mode 100644 index 00000000000..8cf6aa2a949 --- /dev/null +++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55.dts @@ -0,0 +1,54 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "imx95_evk-pinctrl.dtsi" + +/ { + model = "NXP i.MX95 A55"; + compatible = "fsl,mimx95"; + + chosen { + zephyr,console = &lpuart1; + zephyr,shell-uart = &lpuart1; + zephyr,sram = &sram0; + }; + + cpus { + cpu@0 { + status = "disabled"; + }; + + cpu@100 { + status = "disabled"; + }; + + cpu@200 { + status = "disabled"; + }; + + cpu@300 { + status = "disabled"; + }; + + cpu@400 { + status = "disabled"; + }; + }; + + sram0: memory@d0000000 { + reg = <0xd0000000 DT_SIZE_M(1)>; + }; +}; + +&lpuart1 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&lpuart1_default>; + pinctrl-names = "default"; +}; diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55.yaml b/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55.yaml new file mode 100644 index 00000000000..c1183ca216a --- /dev/null +++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55.yaml @@ -0,0 +1,17 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx95_evk/mimx9596/a55 +name: NXP i.MX95 EVK A55 +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 1024 +supported: + - uart +vendor: nxp diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_defconfig b/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_defconfig new file mode 100644 index 00000000000..23e5dd52c5a --- /dev/null +++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_defconfig @@ -0,0 +1,35 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +# ARM Options +CONFIG_AARCH64_IMAGE_HEADER=y +CONFIG_ARMV8_A_NS=y + +# MMU Options +CONFIG_MAX_XLAT_TABLES=64 + +# Cache Options +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE_LINE_SIZE_DETECT=y +CONFIG_ICACHE_LINE_SIZE_DETECT=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_KERNEL_DIRECT_MAP=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_CLOCK_CONTROL=y + +CONFIG_MBOX=y +CONFIG_ARM_SCMI=y +CONFIG_INTC_INIT_PRIORITY=2 +CONFIG_MBOX_INIT_PRIORITY=3 diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_smp.dts b/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_smp.dts new file mode 100644 index 00000000000..3cf7ce362a8 --- /dev/null +++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_smp.dts @@ -0,0 +1,37 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "imx95_evk-pinctrl.dtsi" + +/ { + model = "NXP i.MX95 A55"; + compatible = "fsl,mimx95"; + + chosen { + zephyr,console = &lpuart1; + zephyr,shell-uart = &lpuart1; + zephyr,sram = &sram0; + }; + + psci { + compatible = "arm,psci-1.1"; + method = "smc"; + }; + + sram0: memory@d0000000 { + reg = <0xd0000000 DT_SIZE_M(1)>; + }; +}; + +&lpuart1 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&lpuart1_default>; + pinctrl-names = "default"; +}; diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_smp.yaml b/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_smp.yaml new file mode 100644 index 00000000000..210f5f3278a --- /dev/null +++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_smp.yaml @@ -0,0 +1,18 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx95_evk/mimx9596/a55/smp +name: NXP i.MX95 EVK A55 with SMP kernel +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 1024 +supported: + - smp + - uart +vendor: nxp diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_smp_defconfig b/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_smp_defconfig new file mode 100644 index 00000000000..c4449b32aaa --- /dev/null +++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_smp_defconfig @@ -0,0 +1,42 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +# ARM Options +CONFIG_AARCH64_IMAGE_HEADER=y +CONFIG_ARMV8_A_NS=y + +# MMU Options +CONFIG_MAX_XLAT_TABLES=64 + +# Cache Options +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE_LINE_SIZE_DETECT=y +CONFIG_ICACHE_LINE_SIZE_DETECT=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_KERNEL_DIRECT_MAP=y + +# SMP +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=6 +CONFIG_PM_CPU_OPS=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_CLOCK_CONTROL=y + +CONFIG_MBOX=y +CONFIG_ARM_SCMI=y +CONFIG_INTC_INIT_PRIORITY=2 +CONFIG_MBOX_INIT_PRIORITY=3 + +CONFIG_MAX_THREAD_BYTES=5 diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.dts b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.dts new file mode 100644 index 00000000000..5ffc24e8df6 --- /dev/null +++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.dts @@ -0,0 +1,31 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "imx95_evk-pinctrl.dtsi" + +/ { + model = "NXP i.MX95 EVK board"; + compatible = "nxp,imx95_evk"; + + chosen { + /* TCM */ + zephyr,flash = &itcm; + zephyr,sram = &dtcm; + + zephyr,console = &lpuart3; + zephyr,shell-uart = &lpuart3; + }; +}; + +&lpuart3 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&lpuart3_default>; + pinctrl-names = "default"; +}; diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.yaml b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.yaml new file mode 100644 index 00000000000..c8543538d0a --- /dev/null +++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.yaml @@ -0,0 +1,19 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx95_evk/mimx9596/m7 +name: NXP i.MX95 EVK +type: mcu +arch: arm +ram: 256 +flash: 256 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - uart +vendor: nxp diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_ddr.dts b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_ddr.dts new file mode 100644 index 00000000000..3590fccb970 --- /dev/null +++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_ddr.dts @@ -0,0 +1,23 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "imx95_evk_mimx9596_m7.dts" + +/ { + model = "NXP i.MX95 EVK board DDR variant"; + + chosen { + zephyr,sram = &ddr; + /delete-property/ zephyr,flash; + }; + + ddr: memory@80000000 { + device_type = "memory"; + reg = <0x80000000 DT_SIZE_M(4)>; + }; +}; diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_ddr.yaml b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_ddr.yaml new file mode 100644 index 00000000000..b1f0b22dfc9 --- /dev/null +++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_ddr.yaml @@ -0,0 +1,18 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx95_evk/mimx9596/m7/ddr +name: NXP i.MX95 EVK DDR variant +type: mcu +arch: arm +ram: 256 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - uart +vendor: nxp diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_ddr_defconfig b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_ddr_defconfig new file mode 100644 index 00000000000..f89de52c036 --- /dev/null +++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_ddr_defconfig @@ -0,0 +1,22 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +# clock-related configurations +CONFIG_CLOCK_CONTROL=y + +# serial interface-related configurations +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_UART_CONSOLE=y +CONFIG_CONSOLE=y + +# SCMI-related configurations +CONFIG_MBOX=y +CONFIG_MBOX_INIT_PRIORITY=0 +CONFIG_ARM_SCMI=y + +# kernel-related configurations +CONFIG_XIP=n diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_defconfig b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_defconfig new file mode 100644 index 00000000000..180973c667f --- /dev/null +++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_defconfig @@ -0,0 +1,15 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CLOCK_CONTROL=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_XIP=y +CONFIG_MBOX=y +CONFIG_MBOX_INIT_PRIORITY=0 +CONFIG_ARM_SCMI=y diff --git a/boards/nxp/lpcxpresso11u68/pre_dt_board.cmake b/boards/nxp/lpcxpresso11u68/pre_dt_board.cmake deleted file mode 100644 index 2e3b3ff69ec..00000000000 --- a/boards/nxp/lpcxpresso11u68/pre_dt_board.cmake +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2019, NXP -# SPDX-License-Identifier: Apache-2.0 - -# Suppress DTC warnings due to all GPIO nodes sharing the same register address. -list(APPEND EXTRA_DTC_FLAGS "-Wno-simple_bus_reg") - -# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: -# - /soc/flash@0 & /soc/gpio@0 -list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/nxp/lpcxpresso11u68/support/openocd.cfg b/boards/nxp/lpcxpresso11u68/support/openocd.cfg index 3a59e2b51a5..9d3282f59ab 100644 --- a/boards/nxp/lpcxpresso11u68/support/openocd.cfg +++ b/boards/nxp/lpcxpresso11u68/support/openocd.cfg @@ -39,4 +39,4 @@ $_TARGETNAME configure -event reset-end { # Enable Zephyr thread awareness. $_TARGETNAME configure -rtos Zephyr -adapter_khz 100 +adapter speed 100 diff --git a/boards/nxp/lpcxpresso51u68/doc/index.rst b/boards/nxp/lpcxpresso51u68/doc/index.rst index c1fff7e4d7b..491aa2beab1 100644 --- a/boards/nxp/lpcxpresso51u68/doc/index.rst +++ b/boards/nxp/lpcxpresso51u68/doc/index.rst @@ -133,7 +133,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -148,7 +148,7 @@ Here is an example for the :ref:`hello_world` application. Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/lpcxpresso51u68/pre_dt_board.cmake b/boards/nxp/lpcxpresso51u68/pre_dt_board.cmake deleted file mode 100644 index 665c78c7838..00000000000 --- a/boards/nxp/lpcxpresso51u68/pre_dt_board.cmake +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2021 metraTec GmbH -# SPDX-License-Identifier: Apache-2.0 - -# Suppress "simple_bus_reg" on LPC boards as all GPIO ports use the same register. -list(APPEND EXTRA_DTC_FLAGS "-Wno-simple_bus_reg") diff --git a/boards/nxp/lpcxpresso54114/doc/index.rst b/boards/nxp/lpcxpresso54114/doc/index.rst index 644de94e415..df2e2aabf0d 100644 --- a/boards/nxp/lpcxpresso54114/doc/index.rst +++ b/boards/nxp/lpcxpresso54114/doc/index.rst @@ -74,8 +74,8 @@ features: The default configuration for each core can be found in the defconfig files: - `boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4_defconfig` - `boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0_defconfig` +- :zephyr_file:`boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4_defconfig` +- :zephyr_file:`boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0_defconfig` Other hardware features are not currently supported by the port. @@ -166,7 +166,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -184,7 +184,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4.dts b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4.dts index 797c0a7f0d1..513b953844d 100644 --- a/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4.dts +++ b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4.dts @@ -26,6 +26,7 @@ zephyr,console = &flexcomm0; zephyr,shell-uart = &flexcomm0; zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &flexcomm0; }; gpio_keys { diff --git a/boards/nxp/lpcxpresso54114/pre_dt_board.cmake b/boards/nxp/lpcxpresso54114/pre_dt_board.cmake deleted file mode 100644 index 4918baef9a7..00000000000 --- a/boards/nxp/lpcxpresso54114/pre_dt_board.cmake +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2019, NXP -# SPDX-License-Identifier: Apache-2.0 - -# Suppress "simple_bus_reg" on LPC boards as all GPIO ports use the same register. -list(APPEND EXTRA_DTC_FLAGS "-Wno-simple_bus_reg") diff --git a/boards/nxp/lpcxpresso55s06/Kconfig.sysbuild b/boards/nxp/lpcxpresso55s06/Kconfig.sysbuild new file mode 100644 index 00000000000..8c9a9ac4ed2 --- /dev/null +++ b/boards/nxp/lpcxpresso55s06/Kconfig.sysbuild @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +choice MCUBOOT_MODE + default MCUBOOT_MODE_OVERWRITE_ONLY +endchoice diff --git a/boards/nxp/lpcxpresso55s06/doc/index.rst b/boards/nxp/lpcxpresso55s06/doc/index.rst index 01f7f6b539b..10a1b6728ca 100644 --- a/boards/nxp/lpcxpresso55s06/doc/index.rst +++ b/boards/nxp/lpcxpresso55s06/doc/index.rst @@ -156,7 +156,7 @@ settings: Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -174,7 +174,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/lpcxpresso55s06/lpcxpresso55s06_common.dtsi b/boards/nxp/lpcxpresso55s06/lpcxpresso55s06_common.dtsi index 42849ac568b..dd3529fa641 100644 --- a/boards/nxp/lpcxpresso55s06/lpcxpresso55s06_common.dtsi +++ b/boards/nxp/lpcxpresso55s06/lpcxpresso55s06_common.dtsi @@ -13,6 +13,7 @@ zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &flexcomm0; zephyr,console = &flexcomm0; zephyr,shell-uart = &flexcomm0; zephyr,entropy = &rng; diff --git a/boards/nxp/lpcxpresso55s06/pre_dt_board.cmake b/boards/nxp/lpcxpresso55s06/pre_dt_board.cmake deleted file mode 100644 index 180748da25b..00000000000 --- a/boards/nxp/lpcxpresso55s06/pre_dt_board.cmake +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (c) 2022 metraTec -# -# SPDX-License-Identifier: Apache-2.0 -# - -# Suppress "simple_bus_reg" on LPC boards as all GPIO ports use the same register. -list(APPEND EXTRA_DTC_FLAGS "-Wno-simple_bus_reg") - -# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: -# - /soc/peripheral@40000000/syscon@0 & /soc/peripheral@40000000/gpio@0 -list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/nxp/lpcxpresso55s16/Kconfig.sysbuild b/boards/nxp/lpcxpresso55s16/Kconfig.sysbuild new file mode 100644 index 00000000000..8c9a9ac4ed2 --- /dev/null +++ b/boards/nxp/lpcxpresso55s16/Kconfig.sysbuild @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +choice MCUBOOT_MODE + default MCUBOOT_MODE_OVERWRITE_ONLY +endchoice diff --git a/boards/nxp/lpcxpresso55s16/doc/index.rst b/boards/nxp/lpcxpresso55s16/doc/index.rst index 9c25ac8898e..8089e3de0ef 100644 --- a/boards/nxp/lpcxpresso55s16/doc/index.rst +++ b/boards/nxp/lpcxpresso55s16/doc/index.rst @@ -84,6 +84,8 @@ already supported, which can also be re-used on this lpcxpresso55s16 board: +-----------+------------+-------------------------------------+ | IAP | on-chip | flash programming | +-----------+------------+-------------------------------------+ +| COUNTER | on-chip | counter | ++-----------+------------+-------------------------------------+ Other hardware features are not currently enabled. @@ -189,7 +191,7 @@ settings: Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -207,7 +209,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/lpcxpresso55s16/lpcxpresso55s16.dts b/boards/nxp/lpcxpresso55s16/lpcxpresso55s16.dts index f8646b24f59..9a19e69aed7 100644 --- a/boards/nxp/lpcxpresso55s16/lpcxpresso55s16.dts +++ b/boards/nxp/lpcxpresso55s16/lpcxpresso55s16.dts @@ -1,5 +1,6 @@ /* * Copyright (c) 2020 Henrik Brix Andersen + * Copyright 2024, NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,6 +15,23 @@ compatible = "nxp,lpc55xxx", "nxp,lpc"; }; +/* + * Default for this board is to allocate SRAM0-2 for data. But the + * application can have an application specific device tree to + * allocate the SRAMs differently. + */ +&sram0 { + reg = <0x20000000 DT_SIZE_K(64)>; +}; + zephyr_udc0: &usbhs { status = "okay"; + phy_handle = <&usbphy1>; +}; + +&usbphy1 { + status = "okay"; + tx-d-cal = <5>; + tx-cal-45-dp-ohms = <10>; + tx-cal-45-dm-ohms = <10>; }; diff --git a/boards/nxp/lpcxpresso55s16/lpcxpresso55s16.yaml b/boards/nxp/lpcxpresso55s16/lpcxpresso55s16.yaml index e08460382fd..22bd86054f7 100644 --- a/boards/nxp/lpcxpresso55s16/lpcxpresso55s16.yaml +++ b/boards/nxp/lpcxpresso55s16/lpcxpresso55s16.yaml @@ -19,8 +19,10 @@ supported: - arduino_i2c - arduino_spi - can + - counter - gpio - i2c - spi - usb_device + - usbd vendor: nxp diff --git a/boards/nxp/lpcxpresso55s16/lpcxpresso55s16_common.dtsi b/boards/nxp/lpcxpresso55s16/lpcxpresso55s16_common.dtsi index d081a79b969..54ef8478814 100644 --- a/boards/nxp/lpcxpresso55s16/lpcxpresso55s16_common.dtsi +++ b/boards/nxp/lpcxpresso55s16/lpcxpresso55s16_common.dtsi @@ -13,6 +13,7 @@ zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &flexcomm0; zephyr,console = &flexcomm0; zephyr,shell-uart = &flexcomm0; zephyr,entropy = &rng; @@ -161,6 +162,26 @@ pinctrl-names = "default"; }; +&ctimer0 { + status = "okay"; +}; + +&ctimer1 { + status = "okay"; +}; + +&ctimer2 { + status = "okay"; +}; + +&ctimer3 { + status = "okay"; +}; + +&ctimer4 { + status = "okay"; +}; + &flash0 { partitions { compatible = "fixed-partitions"; diff --git a/boards/nxp/lpcxpresso55s16/pre_dt_board.cmake b/boards/nxp/lpcxpresso55s16/pre_dt_board.cmake deleted file mode 100644 index dbc704b3f54..00000000000 --- a/boards/nxp/lpcxpresso55s16/pre_dt_board.cmake +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2020 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -# Suppress "simple_bus_reg" on LPC boards as all GPIO ports use the same register. -list(APPEND EXTRA_DTC_FLAGS "-Wno-simple_bus_reg") - -# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: -# - /soc/peripheral@40000000/syscon@0 & /soc/peripheral@40000000/gpio@0 -list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/nxp/lpcxpresso55s28/Kconfig.sysbuild b/boards/nxp/lpcxpresso55s28/Kconfig.sysbuild new file mode 100644 index 00000000000..8c9a9ac4ed2 --- /dev/null +++ b/boards/nxp/lpcxpresso55s28/Kconfig.sysbuild @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +choice MCUBOOT_MODE + default MCUBOOT_MODE_OVERWRITE_ONLY +endchoice diff --git a/boards/nxp/lpcxpresso55s28/doc/index.rst b/boards/nxp/lpcxpresso55s28/doc/index.rst index 1e97071456f..df40571a18b 100644 --- a/boards/nxp/lpcxpresso55s28/doc/index.rst +++ b/boards/nxp/lpcxpresso55s28/doc/index.rst @@ -164,7 +164,7 @@ choice (minicom, putty, etc.) with the following settings: Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -182,7 +182,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/lpcxpresso55s28/lpcxpresso55s28.dts b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28.dts index a71ffb15157..9fe9ed0c3d5 100644 --- a/boards/nxp/lpcxpresso55s28/lpcxpresso55s28.dts +++ b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28.dts @@ -27,6 +27,7 @@ zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &flexcomm0; zephyr,console = &flexcomm0; zephyr,shell-uart = &flexcomm0; zephyr,entropy = &rng; diff --git a/boards/nxp/lpcxpresso55s28/pre_dt_board.cmake b/boards/nxp/lpcxpresso55s28/pre_dt_board.cmake deleted file mode 100644 index fcdd6b77a2b..00000000000 --- a/boards/nxp/lpcxpresso55s28/pre_dt_board.cmake +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2020 Lemonbeat GmbH -# SPDX-License-Identifier: Apache-2.0 - -# Suppress "simple_bus_reg" on LPC boards as all GPIO ports use the same register. -list(APPEND EXTRA_DTC_FLAGS "-Wno-simple_bus_reg") - -# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: -# - /soc/peripheral@40000000/syscon@0 & /soc/peripheral@40000000/gpio@0 -list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/nxp/lpcxpresso55s36/Kconfig.sysbuild b/boards/nxp/lpcxpresso55s36/Kconfig.sysbuild new file mode 100644 index 00000000000..8c9a9ac4ed2 --- /dev/null +++ b/boards/nxp/lpcxpresso55s36/Kconfig.sysbuild @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +choice MCUBOOT_MODE + default MCUBOOT_MODE_OVERWRITE_ONLY +endchoice diff --git a/boards/nxp/lpcxpresso55s36/doc/index.rst b/boards/nxp/lpcxpresso55s36/doc/index.rst index bff3ef5d36a..32c7993c3a3 100644 --- a/boards/nxp/lpcxpresso55s36/doc/index.rst +++ b/boards/nxp/lpcxpresso55s36/doc/index.rst @@ -195,7 +195,7 @@ settings: Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -213,7 +213,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.dts b/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.dts index 42b48e8c203..d81a21d48ff 100644 --- a/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.dts +++ b/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.dts @@ -18,6 +18,7 @@ zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &flexcomm0; zephyr,console = &flexcomm0; zephyr,shell-uart = &flexcomm0; zephyr,canbus = &can0; diff --git a/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.yaml b/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.yaml index 5a28b2149c5..806fadc48d3 100644 --- a/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.yaml +++ b/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.yaml @@ -19,4 +19,6 @@ supported: - gpio - pwm - dac + - usb_device + - usbd vendor: nxp diff --git a/boards/nxp/lpcxpresso55s36/pre_dt_board.cmake b/boards/nxp/lpcxpresso55s36/pre_dt_board.cmake deleted file mode 100644 index d97bfca8cf1..00000000000 --- a/boards/nxp/lpcxpresso55s36/pre_dt_board.cmake +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -# Suppress "simple_bus_reg" on LPC boards as all GPIO ports use the same register. -list(APPEND EXTRA_DTC_FLAGS "-Wno-simple_bus_reg") - -# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: -# - /soc/peripheral@40000000/syscon@0 & /soc/peripheral@40000000/gpio@0 -list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/nxp/lpcxpresso55s69/Kconfig.defconfig b/boards/nxp/lpcxpresso55s69/Kconfig.defconfig index 5a48b7afe24..de1910595b4 100644 --- a/boards/nxp/lpcxpresso55s69/Kconfig.defconfig +++ b/boards/nxp/lpcxpresso55s69/Kconfig.defconfig @@ -42,6 +42,9 @@ config FLASH_LOAD_SIZE default 0x40000 if (!TFM_BL2 && BUILD_WITH_TFM) default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) +config PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY + default y if MBEDTLS_PSA_CRYPTO_CLIENT && MBEDTLS_KEY_EXCHANGE_RSA_ENABLED + endif # TRUSTED_EXECUTION_NONSECURE || BOARD_LPCXPRESSO55S69_LPC55S69_CPU1 choice TFM_PROFILE_TYPE diff --git a/boards/nxp/lpcxpresso55s69/Kconfig.sysbuild b/boards/nxp/lpcxpresso55s69/Kconfig.sysbuild new file mode 100644 index 00000000000..8c9a9ac4ed2 --- /dev/null +++ b/boards/nxp/lpcxpresso55s69/Kconfig.sysbuild @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +choice MCUBOOT_MODE + default MCUBOOT_MODE_OVERWRITE_ONLY +endchoice diff --git a/boards/nxp/lpcxpresso55s69/doc/index.rst b/boards/nxp/lpcxpresso55s69/doc/index.rst index 1d909d18942..85336fa2855 100644 --- a/boards/nxp/lpcxpresso55s69/doc/index.rst +++ b/boards/nxp/lpcxpresso55s69/doc/index.rst @@ -124,6 +124,7 @@ included during the build process. CPU1 does not work without CPU0 enabling it. To enable it, run one of the following samples in ``subsys\ipc``: + - ``ipm_mcux`` - ``openamp`` @@ -298,7 +299,7 @@ board. ----------------------------------------- 1. Install the :ref:`linkserver-debug-host-tools` and make sure they are in your search path. - 2. To update the debug firmware, please follow the instructions on `LPCXPRESSO55S69 Debug Firmware` + 2. To update the debug firmware, please follow the instructions on `LPCXPRESSO55S69 Debug Firmware`_ :ref:`opensda-daplink-onboard-debug-probe` ------------------------------------------ @@ -321,7 +322,7 @@ Connect a USB cable from your PC to P6, and use the serial terminal of your choi Flashing ======== -Here is an example for the :ref:`hello_world` application. This example uses the +Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the :ref:`jlink-debug-host-tools` as default. .. zephyr-app-commands:: @@ -364,7 +365,7 @@ an example of building for both cores with sysbuild, see Debugging ========= -Here is an example for the :ref:`hello_world` application. This example uses the +Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the :ref:`jlink-debug-host-tools` as default. .. zephyr-app-commands:: diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69.dtsi b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69.dtsi index e3d5b08fa19..af651dc9c90 100644 --- a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69.dtsi +++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NXP + * Copyright 2019,2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -107,8 +107,6 @@ &flexcomm0 { compatible = "nxp,lpc-usart"; current-speed = <115200>; - dmas = <&dma0 4>, <&dma0 5>; - dma-names = "rx", "tx"; }; &flash0 { diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.dts b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.dts index 14ba04fa448..bf583af5342 100644 --- a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.dts +++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NXP + * Copyright 2019,2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -37,6 +37,7 @@ zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &flexcomm0; zephyr,code-cpu1-partition = &slot0_ns_partition; zephyr,sram-cpu1-partition = &sram3; zephyr,console = &flexcomm0; @@ -125,8 +126,6 @@ &hs_lspi { status = "okay"; - dmas = <&dma0 2>, <&dma0 3>; - dma-names = "rx", "tx"; cs-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; }; @@ -151,6 +150,14 @@ zephyr_udc0: &usbhs { status = "okay"; + phy_handle = <&usbphy1>; +}; + +&usbphy1 { + status = "okay"; + tx-d-cal = <5>; + tx-cal-45-dp-ohms = <10>; + tx-cal-45-dm-ohms = <10>; }; &ctimer0 { @@ -179,8 +186,6 @@ i2s0: &flexcomm6 { compatible = "nxp,lpc-i2s"; #address-cells = <1>; #size-cells = <0>; - dmas = <&dma0 16>; - dma-names = "rx"; }; /* I2S transmit channel */ @@ -189,8 +194,6 @@ i2s1: &flexcomm7 { compatible = "nxp,lpc-i2s"; #address-cells = <1>; #size-cells = <0>; - dmas = <&dma0 19>; - dma-names = "tx"; }; &sc_timer { diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.dts b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.dts index c68006a123f..16ddf4e791a 100644 --- a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.dts +++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NXP + * Copyright 2019,2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -30,6 +30,7 @@ zephyr,sram = &non_secure_ram; zephyr,flash = &flash0; zephyr,code-partition = &slot0_ns_partition; + zephyr,uart-mcumgr = &flexcomm0; zephyr,console = &flexcomm0; zephyr,shell-uart = &flexcomm0; zephyr,entropy = &rng; @@ -85,8 +86,6 @@ &hs_lspi { status = "okay"; - dmas = <&dma0 2>, <&dma0 3>; - dma-names = "rx", "tx"; }; &wwdt0 { diff --git a/boards/nxp/lpcxpresso55s69/pre_dt_board.cmake b/boards/nxp/lpcxpresso55s69/pre_dt_board.cmake deleted file mode 100644 index a7c79990aa5..00000000000 --- a/boards/nxp/lpcxpresso55s69/pre_dt_board.cmake +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2019, NXP -# SPDX-License-Identifier: Apache-2.0 - -# Suppress "simple_bus_reg" on LPC boards as all GPIO ports use the same register. -list(APPEND EXTRA_DTC_FLAGS "-Wno-simple_bus_reg") - -# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: -# - /soc/peripheral@40000000/syscon@0 & /soc/peripheral@40000000/gpio@0 -list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/nxp/mimxrt1010_evk/doc/index.rst b/boards/nxp/mimxrt1010_evk/doc/index.rst index 438b038baea..6422927371e 100644 --- a/boards/nxp/mimxrt1010_evk/doc/index.rst +++ b/boards/nxp/mimxrt1010_evk/doc/index.rst @@ -159,45 +159,26 @@ and the remaining are not used. Programming and Debugging ************************* -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). +This board supports 3 debug host tools. Please install your preferred host +tool, then follow the instructions in `Configuring a Debug Probe`_ to +configure the board appropriately. -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, -however the :ref:`pyocd-debug-host-tools` do not yet support programming the -external flashes on this board so you must reconfigure the board for one of the -following debug probes instead. - -:ref:`jlink-external-debug-probe` -------------------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -Attach a J-Link 10-pin connector to J55. Check that jumpers J61 and J62 are -**off** (they are on by default when boards ship from the factory) to ensure -SWD signals are disconnected from the OpenSDA microcontroller. +* :ref:`linkserver-debug-host-tools` (Default, Supported by NXP) +* :ref:`jlink-debug-host-tools` (Supported by NXP) +* :ref:`pyocd-debug-host-tools` (Not supported by NXP) -Using LinkServer ----------------- +Once the host tool and board are configured, build and flash applications +as usual (see :ref:`build_an_application` and :ref:`application_run` for more +details). -Install the :ref:`linkserver-debug-host-tools` and make sure they are in your -search path. To use LinkServer the on board CMSIS-DAP firmware need updated with -LPCScrypt installed with LinkServer. - -To enter board debuger FW update mode, connect J22 first, and power cycle board. -For more details please refer to `Debug_Probe_Firmware_Programming.pdf`, which is -installed with LinkServer. - -.. code-block:: console +Configuring a Debug Probe +========================= - :Ubuntu/Mac: scripts/program_CMSIS - :Windows: scripts/program_CMSIS.cmd +For the RT1010, J61/J62 are the SWD isolation jumpers, J22 is the DFU +mode jumper, and J16 is the 10 pin JTAG/SWD header. -You may also se the ``-r linkserver`` option with West to use the LinkServer. +.. include:: ../../common/rt1xxx-lpclink2-debug.rst + :start-after: rt1xxx-lpclink2-probes Configuring a Console ===================== @@ -220,7 +201,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts b/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts index 39b65271fd4..0b879fb44a2 100644 --- a/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts +++ b/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts @@ -29,6 +29,7 @@ zephyr,flash = &at25sf128a; zephyr,flash-controller = &at25sf128a; zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &lpuart1; }; leds { @@ -105,19 +106,22 @@ arduino_serial: &lpuart1 {}; #size-cells = <1>; boot_partition: partition@0 { label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(64)>; + reg = <0x00000000 DT_SIZE_K(128)>; }; - slot0_partition: partition@10000 { + /* The MCUBoot swap-move algorithm uses the last 3 sectors + * of the primary slot0 for swap status and move. + */ + slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00010000 DT_SIZE_M(7)>; + reg = <0x00020000 (DT_SIZE_M(7) + DT_SIZE_K(12))>; }; - slot1_partition: partition@710000 { + slot1_partition: partition@723000 { label = "image-1"; - reg = <0x00710000 DT_SIZE_M(7)>; + reg = <0x00723000 DT_SIZE_M(7)>; }; - storage_partition: partition@E10000 { + storage_partition: partition@E23000 { label = "storage"; - reg = <0x00E10000 DT_SIZE_K(1984)>; + reg = <0x00E23000 (DT_SIZE_M(2) - DT_SIZE_K(140))>; }; }; }; diff --git a/boards/nxp/mimxrt1015_evk/doc/index.rst b/boards/nxp/mimxrt1015_evk/doc/index.rst index 65de50063ce..7e22bd4c554 100644 --- a/boards/nxp/mimxrt1015_evk/doc/index.rst +++ b/boards/nxp/mimxrt1015_evk/doc/index.rst @@ -161,40 +161,26 @@ and the remaining are not used. Programming and Debugging ************************* -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). +This board supports 3 debug host tools. Please install your preferred host +tool, then follow the instructions in `Configuring a Debug Probe`_ to +configure the board appropriately. -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`. +* :ref:`linkserver-debug-host-tools` (Default, Supported by NXP) +* :ref:`jlink-debug-host-tools` (Supported by NXP) +* :ref:`pyocd-debug-host-tools` (Not supported by NXP) -Using LinkServer: :ref:`opensda-daplink-onboard-debug-probe` ------------------------------------------------------------- +Once the host tool and board are configured, build and flash applications +as usual (see :ref:`build_an_application` and :ref:`application_run` for more +details). -Install the :ref:`linkserver-debug-host-tools` and make sure they are in your -search path. LinkServer works with the default CMSIS-DAP firmware included in -the on-board debugger. - -Linkserver is the default runner. You may also se the ``-r linkserver`` option -with West to use the LinkServer runner. - -.. code-block:: console - - west flash - west debug - - -External JLink: :ref:`jlink-external-debug-probe` -------------------------------------------------- +Configuring a Debug Probe +========================= -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. +For the RT1015, J47/J48 are the SWD isolation jumpers, J42 is the DFU +mode jumper, and J34 is the 10 pin JTAG/SWD header. -Attach a J-Link 10-pin connector to J55. Check that jumpers J47 and J48 are -**off** (they are on by default when boards ship from the factory) to ensure -SWD signals are disconnected from the OpenSDA microcontroller. +.. include:: ../../common/rt1xxx-lpclink2-debug.rst + :start-after: rt1xxx-lpclink2-probes Configuring a Console ===================== @@ -217,7 +203,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.dts b/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.dts index 0a28acc04ca..10959b0edae 100644 --- a/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.dts +++ b/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.dts @@ -28,6 +28,7 @@ zephyr,flash = &at25sf128a; zephyr,flash-controller = &at25sf128a; zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &lpuart1; }; leds { @@ -102,19 +103,22 @@ arduino_serial: &lpuart4 { #size-cells = <1>; boot_partition: partition@0 { label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(64)>; + reg = <0x00000000 DT_SIZE_K(128)>; }; - slot0_partition: partition@10000 { + /* The MCUBoot swap-move algorithm uses the last 3 sectors + * of the primary slot0 for swap status and move. + */ + slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00010000 DT_SIZE_M(7)>; + reg = <0x00020000 (DT_SIZE_M(7) + DT_SIZE_K(12))>; }; - slot1_partition: partition@710000 { + slot1_partition: partition@723000 { label = "image-1"; - reg = <0x00710000 DT_SIZE_M(7)>; + reg = <0x00723000 DT_SIZE_M(7)>; }; - storage_partition: partition@E10000 { + storage_partition: partition@E23000 { label = "storage"; - reg = <0x00E10000 DT_SIZE_K(1984)>; + reg = <0x00E23000 (DT_SIZE_M(2) - DT_SIZE_K(140))>; }; }; }; diff --git a/boards/nxp/mimxrt1020_evk/doc/index.rst b/boards/nxp/mimxrt1020_evk/doc/index.rst index 4b409031729..0057dcd58ab 100644 --- a/boards/nxp/mimxrt1020_evk/doc/index.rst +++ b/boards/nxp/mimxrt1020_evk/doc/index.rst @@ -106,6 +106,8 @@ already supported, which can also be re-used on this mimxrt1020_evk board: | UART | on-chip | serial port-polling; | | | | serial port-interrupt | +-----------+------------+-------------------------------------+ +| ENET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ | USB | on-chip | USB device | +-----------+------------+-------------------------------------+ | ADC | on-chip | adc | @@ -217,53 +219,26 @@ remaining are not used. Programming and Debugging ************************* -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, -however the :ref:`pyocd-debug-host-tools` do not yet support programming the -external flashes on this board so you must reconfigure the board for one of the -following debug probes instead. - -Using LinkServer ----------------- - -Install the :ref:`linkserver-debug-host-tools` and make sure they are in your -search path. LinkServer works with the default CMSIS-DAP firmware included in -the on-board debugger. +This board supports 3 debug host tools. Please install your preferred host +tool, then follow the instructions in `Configuring a Debug Probe`_ to +configure the board appropriately. -Linkserver is the default runner. You may also se the ``-r linkserver`` option -with West to use the LinkServer runner. +* :ref:`linkserver-debug-host-tools` (Default, Supported by NXP) +* :ref:`jlink-debug-host-tools` (Supported by NXP) +* :ref:`pyocd-debug-host-tools` (Not supported by NXP) -.. code-block:: console - - west flash - west debug - -JLink (on-board): :ref:`opensda-jlink-onboard-debug-probe` ----------------------------------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. +Once the host tool and board are configured, build and flash applications +as usual (see :ref:`build_an_application` and :ref:`application_run` for more +details). -Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program -the `OpenSDA J-Link MIMXRT1020-EVK Firmware`_. Check that jumpers J27 and J28 -are **on** (they are on by default when boards ship from the factory) to ensure -SWD signals are connected to the OpenSDA microcontroller. - -External JLink: :ref:`jlink-external-debug-probe` -------------------------------------------------- +Configuring a Debug Probe +========================= -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. +For the RT1020, J47/J48 are the SWD isolation jumpers, J42 is the DFU +mode jumper, and J16 is the 20 pin JTAG/SWD header. -Attach a J-Link 20-pin connector to J16. Check that jumpers J27 and J28 are -**off** (they are on by default when boards ship from the factory) to ensure -SWD signals are disconnected from the OpenSDA microcontroller. +.. include:: ../../common/rt1xxx-lpclink2-debug.rst + :start-after: rt1xxx-lpclink2-probes Configuring a Console ===================== @@ -286,7 +261,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -304,7 +279,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/mimxrt1020_evk/mimxrt1020_evk-pinctrl.dtsi b/boards/nxp/mimxrt1020_evk/mimxrt1020_evk-pinctrl.dtsi index 9fe3a42bf9f..8fdf5ebbc38 100644 --- a/boards/nxp/mimxrt1020_evk/mimxrt1020_evk-pinctrl.dtsi +++ b/boards/nxp/mimxrt1020_evk/mimxrt1020_evk-pinctrl.dtsi @@ -31,21 +31,29 @@ input-enable; }; group1 { - pinmux = <&iomuxc_gpio_ad_b0_04_gpio1_io04>; + pinmux = <&iomuxc_gpio_ad_b0_09_enet_rx_data1>, + <&iomuxc_gpio_ad_b0_11_enet_rx_en>, + <&iomuxc_gpio_ad_b0_14_enet_tx_data0>, + <&iomuxc_gpio_ad_b0_15_enet_tx_data1>, + <&iomuxc_gpio_ad_b0_13_enet_tx_en>, + <&iomuxc_gpio_ad_b0_12_enet_rx_er>; drive-strength = "r0-5"; bias-pull-up; bias-pull-up-value = "100k"; slew-rate = "fast"; - nxp,speed = "100-mhz"; + nxp,speed = "200-mhz"; }; group2 { - pinmux = <&iomuxc_gpio_ad_b0_09_enet_rx_data1>, - <&iomuxc_gpio_ad_b0_11_enet_rx_en>, - <&iomuxc_gpio_ad_b0_14_enet_tx_data0>, - <&iomuxc_gpio_ad_b0_15_enet_tx_data1>, - <&iomuxc_gpio_ad_b0_13_enet_tx_en>, - <&iomuxc_gpio_ad_b0_12_enet_rx_er>, - <&iomuxc_gpio_emc_40_enet_mdio>, + pinmux = <&iomuxc_gpio_ad_b0_10_enet_rx_data0>; + drive-strength = "r0-6"; + slew-rate = "slow"; + nxp,speed = "100-mhz"; + }; + }; + + pinmux_enet_mdio: pinmux_enet_mdio { + group0 { + pinmux = <&iomuxc_gpio_emc_40_enet_mdio>, <&iomuxc_gpio_emc_41_enet_mdc>; drive-strength = "r0-5"; bias-pull-up; @@ -53,7 +61,7 @@ slew-rate = "fast"; nxp,speed = "200-mhz"; }; - group3 { + group1 { pinmux = <&iomuxc_gpio_ad_b1_06_gpio1_io22>; drive-strength = "r0-5"; bias-pull-up; @@ -61,14 +69,20 @@ slew-rate = "slow"; nxp,speed = "100-mhz"; }; - group4 { - pinmux = <&iomuxc_gpio_ad_b0_10_enet_rx_data0>; - drive-strength = "r0-6"; - slew-rate = "slow"; + group2 { + pinmux = <&iomuxc_gpio_ad_b0_04_gpio1_io04>; + drive-strength = "r0-5"; + bias-pull-up; + bias-pull-up-value = "100k"; + slew-rate = "fast"; nxp,speed = "100-mhz"; }; }; + pinmux_ptp: pinmux_ptp { + /* Intentionally empty */ + }; + pinmux_flexcan1: pinmux_flexcan1 { group0 { pinmux = <&iomuxc_gpio_sd_b1_00_flexcan1_tx>, @@ -173,9 +187,7 @@ }; }; - /* intentionally left empty */ - pinmux_ptp: pinmux_ptp { - }; + pinmux_sai3: pinmux_sai3 { group0 { diff --git a/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.dts b/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.dts index efa02f80add..34997b73f1f 100644 --- a/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.dts +++ b/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.dts @@ -24,6 +24,7 @@ zephyr,flash-controller = &is25wp064; zephyr,flash = &is25wp064; zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &lpuart1; zephyr,sram = &sdram0; zephyr,itcm = &itcm; zephyr,dtcm = &dtcm; @@ -107,30 +108,58 @@ arduino_serial: &lpuart2 { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - boot_partition: partition@0 { label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(64)>; + reg = <0x00000000 DT_SIZE_K(128)>; }; - /* Note slot 0 has one additional sector, - * this is intended for use with the swap move algorithm + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. */ - slot0_partition: partition@10000 { + slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00010000 (DT_SIZE_M(3) + DT_SIZE_K(4))>; + reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(8))>; }; - slot1_partition: partition@311000 { + slot1_partition: partition@322000 { label = "image-1"; - reg = <0x00311000 DT_SIZE_M(3)>; + reg = <0x00322000 DT_SIZE_M(3)>; }; - storage_partition: partition@611000 { + storage_partition: partition@622000 { label = "storage"; - reg = <0x00611000 DT_SIZE_K(1980)>; + reg = <0x00622000 (DT_SIZE_M(2) - DT_SIZE_K(136))>; }; }; }; }; +&enet_mac { + status = "okay"; + pinctrl-0 = <&pinmux_enet>; + pinctrl-names = "default"; + phy-handle = <&phy>; + zephyr,random-mac-address; + phy-connection-type = "rmii"; +}; + +&enet_mdio { + status = "okay"; + pinctrl-0 = <&pinmux_enet_mdio>; + pinctrl-names = "default"; + phy: phy@0 { + compatible = "microchip,ksz8081"; + reg = <0>; + status = "okay"; + reset-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + int-gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; + microchip,interface-type = "rmii"; + }; +}; + +&enet_ptp_clock { + status = "okay"; + pinctrl-0 = <&pinmux_ptp>; + pinctrl-names = "default"; +}; + &lpi2c1 { status = "okay"; pinctrl-0 = <&pinmux_lpi2c1>; diff --git a/boards/nxp/mimxrt1024_evk/doc/index.rst b/boards/nxp/mimxrt1024_evk/doc/index.rst index 88eeb46c946..e451a027432 100644 --- a/boards/nxp/mimxrt1024_evk/doc/index.rst +++ b/boards/nxp/mimxrt1024_evk/doc/index.rst @@ -206,27 +206,21 @@ remaining are not used. Programming and Debugging ************************* -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). +This board supports 2 debug host tools. Please install your preferred host +tool, then follow the instructions in `Configuring a Debug Probe`_ to +configure the board appropriately. + +* :ref:`jlink-debug-host-tools` (Default, Supported by NXP) +* :ref:`pyocd-debug-host-tools` (Not supported by NXP) Configuring a Debug Probe ========================= -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, -however the :ref:`pyocd-debug-host-tools` do not yet support programming the -external flashes on this board so you must reconfigure the board for one of the -following debug probes instead. - -:ref:`jlink-external-debug-probe` ---------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. +For the RT1024, J47/J48 are the SWD isolation jumpers, J42 is the DFU +mode jumper, and J55 is the 10 pin JTAG/SWD header. -Attach a J-Link 10-pin connector to J55. Check that jumpers J47 and J48 are -**off** (they are on by default when boards ship from the factory) to ensure -SWD signals are disconnected from the OpenSDA microcontroller. +.. include:: ../../common/rt1xxx-lpclink2-debug.rst + :start-after: rt1xxx-lpclink2-probes Configuring a Console ===================== @@ -249,7 +243,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -267,7 +261,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.dts b/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.dts index c2c90d85996..4a1811afa41 100644 --- a/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.dts +++ b/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.dts @@ -27,6 +27,7 @@ zephyr,flash-controller = &w25q32jvwj0; zephyr,flash = &w25q32jvwj0; zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &lpuart1; zephyr,sram = &sdram0; zephyr,itcm = &itcm; zephyr,dtcm = &dtcm; @@ -100,25 +101,24 @@ arduino_serial: &lpuart2 { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - boot_partition: partition@0 { label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(64)>; + reg = <0x00000000 DT_SIZE_K(128)>; }; - /* Note slot 0 has one additional sector, - * this is intended for use with the swap move algorithm + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. */ - slot0_partition: partition@10000 { + slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00010000 DT_SIZE_K(1924)>; + reg = <0x00020000 (DT_SIZE_K(1920) + DT_SIZE_K(8))>; }; - slot1_partition: partition@1f1000 { + slot1_partition: partition@202000 { label = "image-1"; - reg = <0x001F1000 DT_SIZE_K(1920)>; + reg = <0x00202000 DT_SIZE_K(1920)>; }; - storage_partition: partition@3d1000 { + storage_partition: partition@3E2000 { label = "storage"; - reg = <0x003D1000 DT_SIZE_K(188)>; + reg = <0x003E2000 DT_SIZE_K(120)>; }; }; }; @@ -140,9 +140,9 @@ arduino_serial: &lpuart2 { compatible = "microchip,ksz8081"; reg = <0>; status = "okay"; - mc,reset-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; - mc,interrupt-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; - mc,interface-type = "rmii"; + reset-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + int-gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; + microchip,interface-type = "rmii"; }; }; diff --git a/boards/nxp/mimxrt1040_evk/CMakeLists.txt b/boards/nxp/mimxrt1040_evk/CMakeLists.txt index 9fc000a98ab..e5e2d4d4140 100644 --- a/boards/nxp/mimxrt1040_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt1040_evk/CMakeLists.txt @@ -4,6 +4,11 @@ # SPDX-License-Identifier: Apache-2.0 # +if (CONFIG_DISPLAY) +message(WARNING " +CONFIG_DISPLAY: Running this firmware on a board without a display may damage the board +") +endif() if(CONFIG_NXP_IMXRT_BOOT_HEADER) zephyr_library() diff --git a/boards/nxp/mimxrt1040_evk/doc/index.rst b/boards/nxp/mimxrt1040_evk/doc/index.rst index a73b6a05b4d..fffd3873fa5 100644 --- a/boards/nxp/mimxrt1040_evk/doc/index.rst +++ b/boards/nxp/mimxrt1040_evk/doc/index.rst @@ -118,6 +118,12 @@ already supported, which can also be re-used on this mimxrt1040_evk board: +-----------+------------+-------------------------------------+ | I2C | on-chip | i2c | +-----------+------------+-------------------------------------+ +| DISPLAY | on-chip | eLCDIF. Tested with | +| | | :ref:`rk043fn02h_ct`, and | +| | | :ref:`rk043fn66hs_ctg` shields | ++-----------+------------+-------------------------------------+ +| UART | NXP NW61x | M.2 WIFI/BT module | ++-----------+------------+-------------------------------------+ The default configuration can be found in :zephyr_file:`boards/nxp/mimxrt1040_evk/mimxrt1040_evk_defconfig` @@ -158,6 +164,14 @@ The MIMXRT1040 SoC has five pairs of pinmux/gpio controllers. +---------------+-----------------+---------------------------+ | GPIO_AD_B1_01 | LPI2C1_SDA | I2C Data | +---------------+-----------------+---------------------------+ +| GPIO_AD_B1_06 | LPUART3_TX | M.2 BT HCI | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_07 | LPUART3_RX | M.2 BT HCI | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_04 | LPUART3_CTS_b | M.2 BT HCI | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_05 | LPUART3_RTS_b | M.2 BT HCI | ++---------------+-----------------+---------------------------+ .. note:: In order to use the SPI peripheral on this board, resistors R350, R346, @@ -178,60 +192,44 @@ Serial Port =========== The MIMXRT1040 SoC has eight UARTs. ``LPUART1`` is configured for the console, +``LPUART3`` for the Bluetooth Host Controller Interface (BT HCI), and the remaining UARTs are not used. +Fetch Binary Blobs +================== -Programming and Debugging -************************* +The board Bluetooth/WiFi module requires fetching some binary blob files, to do +that run the command: -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). +.. code-block:: console -Configuring a Debug Probe -========================= + west blobs fetch hal_nxp + +.. note:: Only Bluetooth functionality is currently supported. Programming and Debugging ************************* -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, -however the :ref:`pyocd-debug-host-tools` do not yet support programming the -external flashes on this board so you must reconfigure the board for one of the -following debug probes instead. - -Option 1: :ref:`opensda-jlink-onboard-debug-probe` (Recommended) ----------------------------------------------------------------- +This board supports 3 debug host tools. Please install your preferred host +tool, then follow the instructions in `Configuring a Debug Probe`_ to +configure the board appropriately. -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. +* :ref:`jlink-debug-host-tools` (Default, Supported by NXP) +* :ref:`linkserver-debug-host-tools` (Supported by NXP) +* :ref:`pyocd-debug-host-tools` (Not supported by NXP) -Check that jumpers J9 and J10 are **on** to ensure SWD signals are connected to -the OpenSDA microcontroller. Then, follow the instructions in `NXP AN13206`_ to -program a JLink based firmware to the LPC4322 based debugger on this board. +Once the host tool and board are configured, build and flash applications +as usual (see :ref:`build_an_application` and :ref:`application_run` for more +details). -Once the JLink based firmware is present on this board, the SOC will no longer -be powered via the USB connection to J1. Move J40 to short pins 3 and 4 in -order to use J48 for USB power, and connect another USB cable to power the SoC. -LED D16 should illuminate to indicate the board is powered, and it should now be -possible to program the SoC. - -Option 2: :ref:`jlink-external-debug-probe` -------------------------------------------- +Configuring a Debug Probe +========================= -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. +For the RT1040, J9/J10 are the SWD isolation jumpers, J12 is the DFU +mode jumper, and J2 is the 20 pin JTAG/SWD header. -The board can be programmed using the :ref:`jlink-external-debug-probe`, -provided the onboard debug circuit's SWD signals are isolated from the MCU. -To do so, ensure that jumpers J9 and J10 are **off** (they are on by default -when the board ships from the factory). The external probe's 20 pin connector -can then be connected to J2 to program the SOC. +.. include:: ../../common/rt1xxx-lpclink2-debug.rst + :start-after: rt1xxx-lpclink2-probes Configuring a Console ===================== @@ -254,7 +252,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -272,7 +270,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -328,6 +326,16 @@ steps: #. Reset by pressing SW1 +Bluetooth Module +---------------- + +For Murate 2EL M.2 Mdoule, the following hardware rework needs to be applied, +Solder 0 ohm resistors for R96, and R93. +Remove resistors from R497, R498, R456 and R457. + +And due to pin conflict issue, the PCM interface of Bluetooth module cannot be supported. + +For the debugger fails to connect with the following error, please refer to the next section. WiFi Module ----------- diff --git a/boards/nxp/mimxrt1040_evk/mimxrt1040_evk-pinctrl.dtsi b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk-pinctrl.dtsi index ad26eeecc3f..4ff94aa892d 100644 --- a/boards/nxp/mimxrt1040_evk/mimxrt1040_evk-pinctrl.dtsi +++ b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk-pinctrl.dtsi @@ -43,11 +43,11 @@ }; }; - /* Conflicts with lpspi1 pin routing. SDA: J17 pin 3, SCL: J17 pin 6 */ + /* LPI2C3 SDA: J33 pin 6, LPI2C3 SCL: J33 pin 5 */ pinmux_lpi2c3: pinmux_lpi2c3 { group0 { - pinmux = <&iomuxc_gpio_sd_b0_00_lpi2c3_scl>, - <&iomuxc_gpio_sd_b0_01_lpi2c3_sda>; + pinmux = <&iomuxc_gpio_ad_b1_06_lpi2c3_sda>, + <&iomuxc_gpio_ad_b1_07_lpi2c3_scl>; drive-strength = "r0-6"; slew-rate = "slow"; nxp,speed = "100-mhz"; @@ -94,5 +94,66 @@ }; }; + pinmux_lpuart3_flowcontrol: pinmux_lpuart3_flowcontrol { + group0 { + pinmux = <&iomuxc_gpio_ad_b1_04_lpuart3_cts_b>, + <&iomuxc_gpio_ad_b1_05_lpuart3_rts_b>, + <&iomuxc_gpio_ad_b1_06_lpuart3_tx>, + <&iomuxc_gpio_ad_b1_07_lpuart3_rx>; + drive-strength = "r0-6"; + slew-rate = "slow"; + nxp,speed = "100-mhz"; + }; + }; + + pinmux_lpuart3_sleep: pinmux_lpuart3_sleep { + group0 { + pinmux = <&iomuxc_gpio_ad_b1_05_gpio1_io21>, + <&iomuxc_gpio_ad_b1_07_gpio1_io23>; + drive-strength = "r0"; + bias-pull-up; + bias-pull-up-value = "100k"; + slew-rate = "slow"; + nxp,speed = "50-mhz"; + }; + group1 { + pinmux = <&iomuxc_gpio_ad_b1_04_lpuart3_cts_b>, + <&iomuxc_gpio_ad_b1_06_lpuart3_tx>; + drive-strength = "r0-6"; + slew-rate = "slow"; + nxp,speed = "100-mhz"; + }; + }; + + pinmux_lcdif: pinmux_lcdif { + group0 { + pinmux = <&iomuxc_gpio_b0_00_lcdif_clk>, + <&iomuxc_gpio_b0_01_lcdif_enable>, + <&iomuxc_gpio_b0_02_lcdif_hsync>, + <&iomuxc_gpio_b0_03_lcdif_vsync>, + <&iomuxc_gpio_b0_04_lcdif_data00>, + <&iomuxc_gpio_b0_05_lcdif_data01>, + <&iomuxc_gpio_b0_06_lcdif_data02>, + <&iomuxc_gpio_b0_07_lcdif_data03>, + <&iomuxc_gpio_b0_08_lcdif_data04>, + <&iomuxc_gpio_b0_09_lcdif_data05>, + <&iomuxc_gpio_b0_10_lcdif_data06>, + <&iomuxc_gpio_b0_11_lcdif_data07>, + <&iomuxc_gpio_b0_12_lcdif_data08>, + <&iomuxc_gpio_b0_13_lcdif_data09>, + <&iomuxc_gpio_b0_14_lcdif_data10>, + <&iomuxc_gpio_b0_15_lcdif_data11>, + <&iomuxc_gpio_b1_00_lcdif_data12>, + <&iomuxc_gpio_b1_01_lcdif_data13>, + <&iomuxc_gpio_b1_02_lcdif_data14>, + <&iomuxc_gpio_b1_03_lcdif_data15>; + drive-strength = "r0-6"; + input-schmitt-enable; + bias-pull-up; + bias-pull-up-value = "100k"; + slew-rate = "slow"; + nxp,speed = "100-mhz"; + }; + }; }; diff --git a/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.dts b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.dts index 5beae5ffc40..37467121ca3 100644 --- a/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.dts +++ b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.dts @@ -18,6 +18,7 @@ led0 = &green_led; sw0 = &user_button; pwm-0 = &flexpwm1_pwm3; + accel0 = &fxls8974; }; chosen { @@ -29,6 +30,8 @@ zephyr,flash = &w25q64jvssiq; zephyr,flash-controller = &w25q64jvssiq; zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &lpuart1; + zephyr,bt-hci = &bt_hci_uart; }; sdram0: memory@80000000 { @@ -37,6 +40,33 @@ reg = <0x80000000 DT_SIZE_M(32)>; }; + /* + * This node describes the GPIO pins of the parallel FPC interface, + * This interface is standard to several NXP EVKs, and is used with + * several parallel LCD displays (available as zephyr shields) + */ + nxp_parallel_lcd_connector: parallel-connector { + compatible = "nxp,parallel-lcd-connector"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio2 31 0>; /* Pin 1, BL+ */ + }; + + /* + * This node describes the GPIO pins of the I2C display FPC interface, + * This interface is standard to several NXP EVKs, and is used with + * several parallel LCD displays (available as zephyr shields) + */ + nxp_i2c_touch_fpc: i2c-touch-connector { + compatible = "nxp,i2c-tsc-fpc"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <1 0 &gpio1 19 0>, /* Pin 2, LCD touch RST */ + <2 0 &gpio1 11 0>; /* Pin 3, LCD touch INT */ + }; + leds { compatible = "gpio-leds"; green_led: led_0 { @@ -103,19 +133,22 @@ #size-cells = <1>; boot_partition: partition@0 { label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(64)>; + reg = <0x00000000 DT_SIZE_K(128)>; }; - slot0_partition: partition@10000 { + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. + */ + slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00010000 DT_SIZE_M(3)>; + reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(8))>; }; - slot1_partition: partition@310000 { + slot1_partition: partition@322000 { label = "image-1"; - reg = <0x00310000 DT_SIZE_M(3)>; + reg = <0x00322000 DT_SIZE_M(3)>; }; - storage_partition: partition@610000 { + storage_partition: partition@622000 { label = "storage"; - reg = <0x00610000 DT_SIZE_K(1984)>; + reg = <0x00622000 (DT_SIZE_M(2) - DT_SIZE_K(136))>; }; }; }; @@ -160,10 +193,31 @@ pinctrl-names = "default"; }; -/* Leave LPI2C3 disabled by default, since it conflicts with LPSPI1 pins */ -&lpi2c3 { +nxp_touch_i2c: &lpi2c1 {}; + +zephyr_lcdif: &lcdif { + pinctrl-0 = <&pinmux_lcdif>; + pinctrl-names = "default"; +}; + +lpi2c3: &lpi2c3 { pinctrl-0 = <&pinmux_lpi2c3>; pinctrl-names = "default"; + status = "okay"; + + fxls8974: fxls8974@18 { + compatible = "nxp,fxls8974"; + reg = <0x18>; + status = "okay"; + + /* Two zero ohm resistors (R115 and R122) isolate sensor + * interrupt gpios from the soc and are unpopulated by default. + * Note that if you populate them, they conflict with JTAG_TDO and + * ethernet PHY interrupt signals. + * int1-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + * int2-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + */ + }; }; /* GPT and Systick are enabled. If power management is enabled, the GPT @@ -177,3 +231,29 @@ &systick { status = "okay"; }; + +m2_hci_uart: &lpuart3 { + pinctrl-0 = <&pinmux_lpuart3_flowcontrol>; + pinctrl-1 = <&pinmux_lpuart3_sleep>; + pinctrl-names = "default", "sleep"; + + bt_hci_uart: bt_hci_uart { + compatible = "zephyr,bt-hci-uart"; + + m2_bt_module { + compatible = "nxp,bt-hci-uart"; + sdio-reset-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; + w-disable-gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>; + hci-operation-speed = <115200>; + hw-flow-control; + fw-download-primary-speed = <115200>; + fw-download-secondary-speed = <3000000>; + fw-download-secondary-flowcontrol; + }; + }; +}; + +&m2_hci_uart { + status = "okay"; + current-speed = <115200>; +}; diff --git a/boards/nxp/mimxrt1050_evk/Kconfig.defconfig b/boards/nxp/mimxrt1050_evk/Kconfig.defconfig index 1db4e04d777..56603850195 100644 --- a/boards/nxp/mimxrt1050_evk/Kconfig.defconfig +++ b/boards/nxp/mimxrt1050_evk/Kconfig.defconfig @@ -10,17 +10,6 @@ config DEVICE_CONFIGURATION_DATA config NXP_IMX_EXTERNAL_SDRAM default y - -config INPUT - default y if LVGL - -if INPUT - -config INPUT_FT5336_INTERRUPT - default y - -endif # INPUT - if NETWORKING config NET_L2_ETHERNET @@ -35,39 +24,4 @@ endif # ETH_MCUX endif # NETWORKING -if LVGL - -# LVGL should allocate buffers equal to size of display -config LV_Z_VDB_SIZE - default 100 - -# Enable double buffering -config LV_Z_DOUBLE_VDB - default y - -# Force full refresh. This prevents memory copy associated with partial -# display refreshes, which is not necessary for the eLCDIF driver -config LV_Z_FULL_REFRESH - default y - -config LV_DPI_DEF - default 128 - -config LV_Z_BITS_PER_PIXEL - default 16 - -# Force display buffers to be aligned to cache line size (32 bytes) -config LV_Z_VDB_ALIGN - default 32 - -# Use offloaded render thread -config LV_Z_FLUSH_THREAD - default y - -choice LV_COLOR_DEPTH - default LV_COLOR_DEPTH_16 -endchoice - -endif # LVGL - endif # BOARD_MIMXRT1050_EVK diff --git a/boards/nxp/mimxrt1050_evk/board.cmake b/boards/nxp/mimxrt1050_evk/board.cmake index 3e42ddc78fe..c53e6474ca1 100644 --- a/boards/nxp/mimxrt1050_evk/board.cmake +++ b/boards/nxp/mimxrt1050_evk/board.cmake @@ -4,15 +4,16 @@ # SPDX-License-Identifier: Apache-2.0 # board_runner_args(jlink "--device=MCIMXRT1052") +board_runner_args(linkserver "--device=MIMXRT1052xxxxB:EVKB-IMXRT1050") if("${BOARD_REVISION}" STREQUAL "qspi") board_runner_args(jlink "--loader=BankAddr=0x60000000&Loader=QSPI") board_runner_args(pyocd "--target=mimxrt1050_quadspi") + board_runner_args(linkserver "--override=/device/memory/3/flash-driver=MIMXRT1050_SFDP_QSPI.cfx") else() board_runner_args(pyocd "--target=mimxrt1050_hyperflash") - board_runner_args(linkserver "--device=MIMXRT1052xxxxB:EVKB-IMXRT1050") - include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) endif() +include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/nxp/mimxrt1050_evk/doc/index.rst b/boards/nxp/mimxrt1050_evk/doc/index.rst index c5351b9b636..19deec55f09 100644 --- a/boards/nxp/mimxrt1050_evk/doc/index.rst +++ b/boards/nxp/mimxrt1050_evk/doc/index.rst @@ -17,9 +17,6 @@ and camera sensors. As with other i.MX processors, i.MX RT1050 also has rich audio and video features, including LCD display, basic 2D graphics, camera interface, SPDIF, and I2S audio interface. -The following document refers to the discontinued MIMXRT1050-EVK board. For the -MIMXRT1050-EVKB board, refer to `Board Revisions`_ section. - .. image:: mimxrt1050_evk.jpg :align: center :alt: MIMXRT1050-EVK @@ -119,7 +116,9 @@ already supported, which can also be re-used on this mimxrt1050_evk board: +-----------+------------+-------------------------------------+ | SYSTICK | on-chip | systick | +-----------+------------+-------------------------------------+ -| DISPLAY | on-chip | display | +| DISPLAY | on-chip | eLCDIF. Tested with | +| | | :ref:`rk043fn02h_ct`, and | +| | | :ref:`rk043fn66hs_ctg` shields | +-----------+------------+-------------------------------------+ | GPIO | on-chip | gpio | +-----------+------------+-------------------------------------+ @@ -309,58 +308,43 @@ Only USB device function is supported in Zephyr at the moment. Programming and Debugging ************************* -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, -however the :ref:`pyocd-debug-host-tools` do not yet support programming the -external flashes on this board so you must reconfigure the board for one of the -following debug probes instead. - -Using LinkServer ----------------- - -Install the :ref:`linkserver-debug-host-tools` and make sure they are in your -search path. LinkServer works with the default CMSIS-DAP firmware included in -the on-board debugger. +.. note:: + Newer revisions of this board use :ref:`lpc-link2-onboard-debug-probe`, + while older revisions use the :ref:`opensda-onboard-debug-probe`. + Schematic revisions A/A1 use the K20 OpenSDA probe, and B/B1 use the + LPC-Link2 LPC4322 probe. -Linkserver is the default runner. You may also se the ``-r linkserver`` option -with West to use the LinkServer runner. +This board supports 3 debug host tools. Please install your preferred host +tool, then follow the instructions in `Configuring a Debug Probe +(Schematic A/A1)`_ or `Configuring a Debug Probe (Schematic B/B1)`_, +depending on board schematic revision to configure the board appropriately. -.. code-block:: console +* :ref:`linkserver-debug-host-tools` (Default, NXP Supported) +* :ref:`jlink-debug-host-tools` (NXP Supported) +* :ref:`pyocd-debug-host-tools` (Not supported by NXP) - west flash - west debug +Once the host tool and board are configured, build and flash applications +as usual (see :ref:`build_an_application` and :ref:`application_run` for more +details). -JLink (on-board): :ref:`opensda-jlink-onboard-debug-probe` ----------------------------------------------------------- +Configuring a Debug Probe (Schematic A/A1) +========================================== -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. +For the RT1050 Schematic Rev A, J32/J33 are the SWD isolation jumpers, SW4 is +the reset button, and J21 is the 20 pin JTAG/SWD header. -Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program -the `OpenSDA J-Link MIMXRT1050-EVK-Hyperflash Firmware`_. Check that jumpers -J32 and J33 are **on** (they are on by default when boards ship from the -factory) to ensure SWD signals are connected to the OpenSDA microcontroller. +.. include:: ../../common/opensda-debug.rst + :start-after: nxp-opensda-probes -Follow the instructions in `Enable QSPI flash support in SEGGER JLink`_ -in order to support your EVK if you have modified it to boot from QSPI NOR -flash as specified by NXP AN12108. -External JLink :ref:`jlink-external-debug-probe` ------------------------------------------------- +Configuring a Debug Probe (Schematic B/B1) +========================================== -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. +For the RT1050 Schematic Rev B, J47/J48 are the SWD isolation jumpers, J42 is +the DFU mode jumper, and J21 is the 20 pin JTAG/SWD header. -Attach a J-Link 20-pin connector to J21. Check that jumpers J32 and J33 with -schematic rev A0/A1 or J47 and J48 with schematic rev B1 are **off** (they are -on by default when boards ship from the factory) to ensure SWD signals are -disconnected from the OpenSDA microcontroller. +.. include:: ../../common/rt1xxx-lpclink2-debug.rst + :start-after: rt1xxx-lpclink2-probes Configuring a Console ===================== @@ -383,7 +367,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -401,7 +385,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dts b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dts index 4bd6b5bb441..7edf96e9517 100644 --- a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dts +++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dts @@ -8,7 +8,6 @@ #include #include "mimxrt1050_evk-pinctrl.dtsi" -#include #include / { @@ -28,9 +27,9 @@ zephyr,sram = &sdram0; zephyr,itcm = &itcm; zephyr,dtcm = &dtcm; + zephyr,uart-mcumgr = &lpuart1; zephyr,console = &lpuart1; zephyr,shell-uart = &lpuart1; - zephyr,display = &lcdif; }; sdram0: memory@80000000 { @@ -39,6 +38,33 @@ reg = <0x80000000 DT_SIZE_M(32)>; }; + /* + * This node describes the GPIO pins of the parallel FPC interface, + * This interface is standard to several NXP EVKs, and is used with + * several parallel LCD displays (available as zephyr shields) + */ + nxp_parallel_lcd_connector: parallel-connector { + compatible = "nxp,parallel-lcd-connector"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio2 31 0>; /* Pin 1, BL+ */ + }; + + /* + * This node describes the GPIO pins of the I2C display FPC interface, + * This interface is standard to several NXP EVKs, and is used with + * several parallel LCD displays (available as zephyr shields) + */ + nxp_i2c_touch_fpc: i2c-touch-connector { + compatible = "nxp,i2c-tsc-fpc"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <1 0 &gpio1 2 0>, /* Pin 2, LCD touch RST */ + <2 0 &gpio1 11 0>; /* Pin 3, LCD touch INT */ + }; + leds { compatible = "gpio-leds"; green_led: led_0 { @@ -56,11 +82,6 @@ }; }; - lvgl_pointer { - compatible = "zephyr,lvgl-pointer-input"; - input = <&ft5336>; - }; - arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; @@ -89,15 +110,6 @@ <20 0 &gpio1 1 0>, /* D14 */ <21 0 &gpio1 0 0>; /* D15 */ }; - - panel { - compatible = "rocktech,rk043fn02h-ct"; - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_panel_out>; - }; - }; - }; }; arduino_serial: &lpuart3 { @@ -112,34 +124,11 @@ arduino_serial: &lpuart3 { pinctrl-names = "default"; }; -&lcdif { - status = "okay"; - width = <480>; - height = <272>; - display-timings { - compatible = "zephyr,panel-timing"; - hsync-len = <41>; - hfront-porch = <4>; - hback-porch = <8>; - vsync-len = <10>; - vfront-porch = <4>; - vback-porch = <2>; - de-active= <1>; - pixelclk-active = <1>; - hsync-active = <0>; - vsync-active = <0>; - clock-frequency = <9210240>; - }; - pixel-format = ; - data-bus-width = "16-bit"; +nxp_touch_i2c: &lpi2c1 {}; + +zephyr_lcdif: &lcdif { pinctrl-0 = <&pinmux_lcdif>; pinctrl-names = "default"; - backlight-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; - port { - lcd_panel_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; }; &lpi2c1 { @@ -159,12 +148,6 @@ arduino_serial: &lpuart3 { int1-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; int2-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; }; - - ft5336: ft5336@38 { - compatible = "focaltech,ft5336"; - reg = <0x38>; - int-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; }; &lpuart1 { @@ -210,9 +193,9 @@ arduino_serial: &lpuart3 { compatible = "microchip,ksz8081"; reg = <0>; status = "okay"; - mc,reset-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - mc,interrupt-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; - mc,interface-type = "rmii"; + reset-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + int-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + microchip,interface-type = "rmii"; }; }; diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.overlay b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.overlay index ccce00a5628..4b3923c36d9 100644 --- a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.overlay +++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.overlay @@ -46,25 +46,24 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - boot_partition: partition@0 { label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(256)>; + reg = <0x00000000 DT_SIZE_K(128)>; }; - /* Note slot 0 has one additional sector, - * this is intended for use with the swap move algorithm + /* The MCUBoot swap-move algorithm uses the last 14 sectors + * of the primary slot0 for swap status and move. */ - slot0_partition: partition@40000 { + slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00040000 (DT_SIZE_M(3) + DT_SIZE_K(4))>; + reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(56))>; }; - slot1_partition: partition@341000 { + slot1_partition: partition@32E000 { label = "image-1"; - reg = <0x00341000 DT_SIZE_M(3)>; + reg = <0x0032E000 DT_SIZE_M(3)>; }; - storage_partition: partition@641000 { + storage_partition: partition@62E000 { label = "storage"; - reg = <0x00641000 (DT_SIZE_M(57) + DT_SIZE_K(764))>; + reg = <0x0062E000 (DT_SIZE_M(58) - DT_SIZE_K(184))>; }; }; }; diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.yaml b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.yaml index a19f9f10dba..211c0e9aebd 100644 --- a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.yaml +++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.yaml @@ -26,6 +26,7 @@ supported: - sdhc - spi - usb_device + - usbd - watchdog - adc vendor: nxp diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.overlay b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.overlay index 1fd770ec655..d18cda45c60 100644 --- a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.overlay +++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.overlay @@ -27,30 +27,28 @@ jedec-id = [9d 70 17]; erase-block-size = <4096>; write-block-size = <1>; - partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - boot_partition: partition@0 { label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(64)>; + reg = <0x00000000 DT_SIZE_K(128)>; }; - /* Note slot 0 has one additional sector, - * this is intended for use with the swap move algorithm + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. */ - slot0_partition: partition@10000 { + slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00010000 (DT_SIZE_M(3) + DT_SIZE_K(4))>; + reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(8))>; }; - slot1_partition: partition@311000 { + slot1_partition: partition@322000 { label = "image-1"; - reg = <0x00311000 DT_SIZE_M(3)>; + reg = <0x00322000 DT_SIZE_M(3)>; }; - storage_partition: partition@611000 { + storage_partition: partition@622000 { label = "storage"; - reg = <0x00611000 DT_SIZE_K(1980)>; + reg = <0x00622000 (DT_SIZE_M(2) - DT_SIZE_K(136))>; }; }; }; diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.yaml b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.yaml index 6476d666984..a9adaba0526 100644 --- a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.yaml +++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.yaml @@ -26,6 +26,7 @@ supported: - sdhc - spi - usb_device + - usbd - watchdog - adc vendor: nxp diff --git a/boards/nxp/mimxrt1060_evk/Kconfig.defconfig b/boards/nxp/mimxrt1060_evk/Kconfig.defconfig index 37dc90279dd..899e8b3ffe0 100644 --- a/boards/nxp/mimxrt1060_evk/Kconfig.defconfig +++ b/boards/nxp/mimxrt1060_evk/Kconfig.defconfig @@ -11,16 +11,6 @@ config DEVICE_CONFIGURATION_DATA config NXP_IMX_EXTERNAL_SDRAM default y -config INPUT - default y if LVGL - -if INPUT - -config INPUT_FT5336_INTERRUPT - default y - -endif # INPUT - if NETWORKING config NET_L2_ETHERNET @@ -35,39 +25,4 @@ endif # ETH_MCUX endif # NETWORKING -if LVGL - -# LVGL should allocate buffers equal to size of display -config LV_Z_VDB_SIZE - default 100 - -# Enable double buffering -config LV_Z_DOUBLE_VDB - default y - -# Force full refresh. This prevents memory copy associated with partial -# display refreshes, which is not necessary for the eLCDIF driver -config LV_Z_FULL_REFRESH - default y - -config LV_DPI_DEF - default 128 - -config LV_Z_BITS_PER_PIXEL - default 16 - -# Force display buffers to be aligned to cache line size (32 bytes) -config LV_Z_VDB_ALIGN - default 32 - -# Use offloaded render thread -config LV_Z_FLUSH_THREAD - default y - -choice LV_COLOR_DEPTH - default LV_COLOR_DEPTH_16 -endchoice - -endif # LVGL - endif # BOARD_MIMXRT1060_EVK || BOARD_MIMXRT1060_EVKB diff --git a/boards/nxp/mimxrt1060_evk/doc/index.rst b/boards/nxp/mimxrt1060_evk/doc/index.rst index e33336ea986..e17f57ee77f 100644 --- a/boards/nxp/mimxrt1060_evk/doc/index.rst +++ b/boards/nxp/mimxrt1060_evk/doc/index.rst @@ -115,7 +115,9 @@ already supported, which can also be re-used on this mimxrt1060_evk board: +-----------+------------+-------------------------------------+ | SYSTICK | on-chip | systick | +-----------+------------+-------------------------------------+ -| DISPLAY | on-chip | display | +| DISPLAY | on-chip | eLCDIF. Tested with | +| | | :ref:`rk043fn02h_ct`, and | +| | | :ref:`rk043fn66hs_ctg` shields | +-----------+------------+-------------------------------------+ | FLASH | on-chip | QSPI flash | +-----------+------------+-------------------------------------+ @@ -323,35 +325,31 @@ remaining are not used. Programming and Debugging ************************* -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). +This board supports 3 debug host tools. Please install your preferred host +tool, then follow the instructions in `Configuring a Debug Probe`_ to +configure the board appropriately. -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, -however the :ref:`pyocd-debug-host-tools` do not yet support programming the -external flashes on this board so you must reconfigure the board for one of the -following debug probes instead. +* :ref:`jlink-debug-host-tools` (Default, Supported by NXP) +* :ref:`linkserver-debug-host-tools` (Supported by NXP) +* :ref:`pyocd-debug-host-tools` (Not Supported by NXP) -.. _Using LinkServer: +Once the host tool and board are configured, build and flash applications +as usual (see :ref:`build_an_application` and :ref:`application_run` for more +details). - 1. Install the :ref:`linkserver-debug-host-tools` and make sure they are in your search path. - 2. To update the debug firmware, please follow the instructions on `MIMXRT1060-EVK Debug Firmware` - -.. _Using J-Link RT1060: +Configuring a Debug Probe +========================= -Using J-Link ---------------------------------- +Two revisions of the RT1060 EVK exist. For the RT1060 EVK, J47/J48 are the SWD +isolation jumpers, J42 is the DFU mode jumper, and the 20 pin JTAG/SWD header +is present on J21. For the RT1060 EVKB, J9/J10 are the SWD isolation jumpers, +J12 is the DFU mode jumper, and the 20 pin JTAG/SWD header is present on J2. -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. +.. include:: ../../common/rt1xxx-lpclink2-debug.rst + :start-after: rt1xxx-lpclink2-probes -There are two options: the onboard debug circuit can be updated with Segger -J-Link firmware, or :ref:`jlink-external-debug-probe` can be attached to the -EVK. See `Using J-Link with MIMXRT1060-EVK or MIMXRT1064-EVK`_ or -`Using J-Link with MIMXRT1060-EVKB`_ for more details. +See `Using J-Link with MIMXRT1060-EVK or MIMXRT1064-EVK`_ or `Using J-Link with +MIMXRT1060-EVKB`_ for more details. Configuring a Console ===================== @@ -380,7 +378,7 @@ SWO frequency of 7500KHz. Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -398,7 +396,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -446,7 +444,7 @@ steps: If the west flash or debug commands fail, and the command hangs while executing runners.jlink, confirm the J-Link debug probe is configured, powered, and -connected to the EVK properly. See :ref:`Using J-Link RT1060` for more details. +connected to the EVK properly. .. _MIMXRT1060-EVK Website: https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt1060-evaluation-kit:MIMXRT1060-EVKB diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dts b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dts index 08eb8541432..4f0be3d23bd 100644 --- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dts +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dts @@ -8,7 +8,6 @@ #include #include "mimxrt1060_evk-pinctrl.dtsi" -#include #include / { @@ -27,10 +26,10 @@ zephyr,sram = &sdram0; zephyr,itcm = &itcm; zephyr,dtcm = &dtcm; + zephyr,uart-mcumgr = &lpuart1; zephyr,console = &lpuart1; zephyr,shell-uart = &lpuart1; zephyr,canbus = &flexcan3; - zephyr,display = &lcdif; }; sdram0: memory@80000000 { @@ -39,6 +38,33 @@ reg = <0x80000000 DT_SIZE_M(32)>; }; + /* + * This node describes the GPIO pins of the parallel FPC interface, + * This interface is standard to several NXP EVKs, and is used with + * several parallel LCD displays (available as zephyr shields) + */ + nxp_parallel_lcd_connector: parallel-connector { + compatible = "nxp,parallel-lcd-connector"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio2 31 0>; /* Pin 1, BL+ */ + }; + + /* + * This node describes the GPIO pins of the I2C display FPC interface, + * This interface is standard to several NXP EVKs, and is used with + * several parallel LCD displays (available as zephyr shields) + */ + nxp_i2c_touch_fpc: i2c-touch-connector { + compatible = "nxp,i2c-tsc-fpc"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <1 0 &gpio1 2 0>, /* Pin 2, LCD touch RST */ + <2 0 &gpio1 11 0>; /* Pin 3, LCD touch INT */ + }; + leds { compatible = "gpio-leds"; green_led: led-1 { @@ -63,11 +89,6 @@ }; }; - lvgl_pointer { - compatible = "zephyr,lvgl-pointer-input"; - input = <&ft5336>; - }; - arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; @@ -96,15 +117,6 @@ <20 0 &gpio1 17 0>, /* D14 */ <21 0 &gpio1 16 0>; /* D15 */ }; - - panel { - compatible = "rocktech,rk043fn02h-ct"; - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_panel_out>; - }; - }; - }; }; arduino_serial: &lpuart3 { @@ -114,46 +126,17 @@ arduino_serial: &lpuart3 { pinctrl-names = "default", "flowcontrol", "sleep"; }; -&lcdif { - status = "okay"; - width = <480>; - height = <272>; - display-timings { - compatible = "zephyr,panel-timing"; - hsync-len = <41>; - hfront-porch = <4>; - hback-porch = <8>; - vsync-len = <10>; - vfront-porch = <4>; - vback-porch = <2>; - de-active= <1>; - pixelclk-active = <1>; - hsync-active = <0>; - vsync-active = <0>; - clock-frequency = <9210240>; - }; - pixel-format = ; - data-bus-width = "16-bit"; +zephyr_lcdif: &lcdif { pinctrl-0 = <&pinmux_lcdif>; pinctrl-names = "default"; - backlight-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; - port { - lcd_panel_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; }; +nxp_touch_i2c: &lpi2c1 {}; + arduino_i2c: &lpi2c1 { status = "okay"; pinctrl-0 = <&pinmux_lpi2c1>; pinctrl-names = "default"; - - ft5336: ft5336@38 { - compatible = "focaltech,ft5336"; - reg = <0x38>; - int-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; }; &lpuart1 { @@ -181,9 +164,9 @@ arduino_i2c: &lpi2c1 { compatible = "microchip,ksz8081"; reg = <0>; status = "okay"; - mc,reset-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - mc,interrupt-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; - mc,interface-type = "rmii"; + reset-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + int-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + microchip,interface-type = "rmii"; }; }; @@ -201,6 +184,19 @@ arduino_i2c: &lpi2c1 { zephyr_udc0: &usb1 { status = "okay"; + phy_handle = <&usbphy1>; +}; + +&usbphy1 { + status = "okay"; + tx-d-cal = <12>; + tx-cal-45-dp-ohms = <6>; + tx-cal-45-dm-ohms = <6>; +}; + +&csi { + pinctrl-0 = <&pinmux_csi>; + pinctrl-names = "default"; }; &flexpwm2_pwm3 { @@ -307,3 +303,7 @@ arduino_spi: &lpspi1 { &pit0 { status = "okay"; }; + +dvp_fpc24_i2c: &lpi2c1 {}; + +dvp_fpc24_interface: &csi {}; diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.overlay b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.overlay index 4d94e82f611..25d33e462a0 100644 --- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.overlay +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.overlay @@ -44,25 +44,24 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - boot_partition: partition@0 { label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(256)>; + reg = <0x00000000 DT_SIZE_K(128)>; }; - /* Note slot 0 has one additional sector, - * this is intended for use with the swap move algorithm + /* The MCUBoot swap-move algorithm uses the last 14 sectors + * of the primary slot0 for swap status and move. */ - slot0_partition: partition@40000 { + slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00040000 (DT_SIZE_M(3) + DT_SIZE_K(4))>; + reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(56))>; }; - slot1_partition: partition@341000 { + slot1_partition: partition@32E000 { label = "image-1"; - reg = <0x00341000 DT_SIZE_M(3)>; + reg = <0x0032E000 DT_SIZE_M(3)>; }; - storage_partition: partition@641000 { + storage_partition: partition@62E000 { label = "storage"; - reg = <0x00641000 (DT_SIZE_M(57) + DT_SIZE_K(764))>; + reg = <0x0062E000 (DT_SIZE_M(58) - DT_SIZE_K(184))>; }; }; }; diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.yaml b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.yaml index 8dbd8533c1c..c453d1c9ee6 100644 --- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.yaml +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.yaml @@ -29,5 +29,6 @@ supported: - sdhc - spi - usb_device + - usbd - watchdog vendor: nxp diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.overlay b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.overlay index 9fddaea0c62..8a0abae2fb3 100644 --- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.overlay +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.overlay @@ -34,25 +34,24 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - boot_partition: partition@0 { label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(64)>; + reg = <0x00000000 DT_SIZE_K(128)>; }; - /* Note slot 0 has one additional sector, - * this is intended for use with the swap move algorithm + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. */ - slot0_partition: partition@10000 { + slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00010000 (DT_SIZE_M(3) + DT_SIZE_K(4))>; + reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(8))>; }; - slot1_partition: partition@311000 { + slot1_partition: partition@322000 { label = "image-1"; - reg = <0x00311000 DT_SIZE_M(3)>; + reg = <0x00322000 DT_SIZE_M(3)>; }; - storage_partition: partition@611000 { + storage_partition: partition@622000 { label = "storage"; - reg = <0x00611000 DT_SIZE_K(1980)>; + reg = <0x00622000 (DT_SIZE_M(2) - DT_SIZE_K(136))>; }; }; }; diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.yaml b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.yaml index 1cd757e66d5..41181dd8bb3 100644 --- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.yaml +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.yaml @@ -31,5 +31,6 @@ supported: - sdhc - spi - usb_device + - usbd - watchdog vendor: nxp diff --git a/boards/nxp/mimxrt1062_fmurt6/doc/index.rst b/boards/nxp/mimxrt1062_fmurt6/doc/index.rst index edcd5bc5f11..e587a8c5087 100644 --- a/boards/nxp/mimxrt1062_fmurt6/doc/index.rst +++ b/boards/nxp/mimxrt1062_fmurt6/doc/index.rst @@ -303,7 +303,7 @@ SWO frequency of 7500KHz. Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -321,7 +321,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts b/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts index 85a53c07f29..96a96958a03 100644 --- a/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts +++ b/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts @@ -29,6 +29,7 @@ zephyr,flash-controller = &s26ks512s0; zephyr,flash = &s26ks512s0; zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &lpuart7; zephyr,sram = &ocram; zephyr,itcm = &itcm; zephyr,dtcm = &dtcm; @@ -206,22 +207,24 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - boot_partition: partition@0 { label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(256)>; + reg = <0x00000000 DT_SIZE_K(128)>; }; - slot0_partition: partition@40000 { + /* The MCUBoot swap-move algorithm uses the last 14 sectors + * of the primary slot0 for swap status and move. + */ + slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00040000 DT_SIZE_M(3)>; + reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(56))>; }; - slot1_partition: partition@340000 { + slot1_partition: partition@32E000 { label = "image-1"; - reg = <0x00340000 DT_SIZE_M(3)>; + reg = <0x0032E000 DT_SIZE_M(3)>; }; - storage_partition: partition@640000 { + storage_partition: partition@62E000 { label = "storage"; - reg = <0x00640000 (DT_SIZE_M(557) + DT_SIZE_K(768))>; + reg = <0x0062E000 (DT_SIZE_M(58) - DT_SIZE_K(184))>; }; }; }; diff --git a/boards/nxp/mimxrt1064_evk/Kconfig.defconfig b/boards/nxp/mimxrt1064_evk/Kconfig.defconfig index 4ec3c9ebe2f..6454f9b6329 100644 --- a/boards/nxp/mimxrt1064_evk/Kconfig.defconfig +++ b/boards/nxp/mimxrt1064_evk/Kconfig.defconfig @@ -11,16 +11,6 @@ config DEVICE_CONFIGURATION_DATA config NXP_IMX_EXTERNAL_SDRAM default y -config INPUT - default y if LVGL - -if INPUT - -config INPUT_FT5336_INTERRUPT - default y - -endif # INPUT - if NETWORKING config NET_L2_ETHERNET @@ -35,18 +25,4 @@ endif # ETH_MCUX endif # NETWORKING -if LVGL - -config LV_Z_VDB_SIZE - default 16 - -config LV_DPI_DEF - default 128 - -choice LV_COLOR_DEPTH - default LV_COLOR_DEPTH_16 -endchoice - -endif # LVGL - endif # BOARD_MIMXRT1064_EVK diff --git a/boards/nxp/mimxrt1064_evk/doc/index.rst b/boards/nxp/mimxrt1064_evk/doc/index.rst index fb9195693fd..4f6fab6f0f6 100644 --- a/boards/nxp/mimxrt1064_evk/doc/index.rst +++ b/boards/nxp/mimxrt1064_evk/doc/index.rst @@ -111,7 +111,9 @@ configuration supports the following hardware features: +-----------+------------+-------------------------------------+ | SYSTICK | on-chip | systick | +-----------+------------+-------------------------------------+ -| DISPLAY | on-chip | display | +| DISPLAY | on-chip | eLCDIF. Tested with | +| | | :ref:`rk043fn02h_ct`, and | +| | | :ref:`rk043fn66hs_ctg` shields | +-----------+------------+-------------------------------------+ | VIDEO | on-chip | video, using CSI | +-----------+------------+-------------------------------------+ @@ -315,8 +317,17 @@ and the remaining are not used. Programming and Debugging ************************* -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). +This board supports 3 debug host tools. Please install your preferred host +tool, then follow the instructions in `Configuring a Debug Probe`_ to +configure the board appropriately. + +* :ref:`jlink-debug-host-tools` (Default, Supported by NXP) +* :ref:`linkserver-debug-host-tools` (Supported by NXP) +* :ref:`pyocd-debug-host-tools` (Not supported by NXP) + +Once the host tool and board are configured, build and flash applications +as usual (see :ref:`build_an_application` and :ref:`application_run` for more +details). Configuring a Debug Probe ========================= @@ -326,28 +337,13 @@ Configuring a Debug Probe unable to access the chip. Use caution when enabling ``CONFIG_PM``, and if the debugger cannot flash the part, see :ref:`Troubleshooting RT1064` -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, -however the :ref:`pyocd-debug-host-tools` do not yet support programming the -external flashes on this board so you must reconfigure the board for one of the -following debug probes instead. - -.. _Using LinkServer: - - 1. Install the :ref:`linkserver-debug-host-tools` and make sure they are in your search path. - 2. To update the debug firmware, please follow the instructions on `MIMXRT1064-EVK Debug Firmware` +For the RT1064, J47/J48 are the SWD isolation jumpers, J42 is the DFU +mode jumper, and J21 is the 20 pin JTAG/SWD header. -.. _Using J-Link RT1064: +.. include:: ../../common/rt1xxx-lpclink2-debug.rst + :start-after: rt1xxx-lpclink2-probes -Using J-Link ---------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -There are two options: the onboard debug circuit can be updated with Segger -J-Link firmware, or :ref:`jlink-external-debug-probe` can be attached to the -EVK. See `Using J-Link with MIMXRT1060-EVK or MIMXRT1064-EVK`_ for more +See `Using J-Link with MIMXRT1060-EVK or MIMXRT1064-EVK`_ for more details. Configuring a Console @@ -377,7 +373,7 @@ SWO frequency of 7500KHz. Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -395,7 +391,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -446,8 +442,7 @@ steps: If the west flash or debug commands fail, and the command hangs while executing runners.jlink, confirm the J-Link debug probe is configured, powered, and -connected to the EVK properly. See :ref:`Using J-Link RT1064` for more -details. +connected to the EVK properly. .. _MIMXRT1064-EVK Website: https://www.nxp.com/support/developer-resources/run-time-software/i.mx-developer-resources/mimxrt1064-evk-i.mx-rt1064-evaluation-kit:MIMXRT1064-EVK diff --git a/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts b/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts index 7351659dd87..f3d060d7283 100644 --- a/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts +++ b/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts @@ -8,7 +8,6 @@ #include #include "mimxrt1064_evk-pinctrl.dtsi" -#include #include / { @@ -27,13 +26,13 @@ zephyr,flash-controller = &is25wp064; zephyr,flash = &w25q32jvwj0; zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &lpuart1; zephyr,sram = &sdram0; zephyr,itcm = &itcm; zephyr,dtcm = &dtcm; zephyr,console = &lpuart1; zephyr,shell-uart = &lpuart1; zephyr,canbus = &flexcan2; - zephyr,display = &lcdif; }; sdram0: memory@80000000 { @@ -42,6 +41,33 @@ reg = <0x80000000 DT_SIZE_M(32)>; }; + /* + * This node describes the GPIO pins of the parallel FPC interface, + * This interface is standard to several NXP EVKs, and is used with + * several parallel LCD displays (available as zephyr shields) + */ + nxp_parallel_lcd_connector: parallel-connector { + compatible = "nxp,parallel-lcd-connector"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio2 31 0>; /* Pin 1, BL+ */ + }; + + /* + * This node describes the GPIO pins of the I2C display FPC interface, + * This interface is standard to several NXP EVKs, and is used with + * several parallel LCD displays (available as zephyr shields) + */ + nxp_i2c_touch_fpc: i2c-touch-connector { + compatible = "nxp,i2c-tsc-fpc"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <1 0 &gpio1 2 0>, /* Pin 2, LCD touch RST */ + <2 0 &gpio1 11 0>; /* Pin 3, LCD touch INT */ + }; + leds { compatible = "gpio-leds"; green_led: led-1 { @@ -100,67 +126,23 @@ <20 0 &gpio1 17 0>, /* D14 */ <21 0 &gpio1 16 0>; /* D15 */ }; - - panel { - compatible = "rocktech,rk043fn02h-ct"; - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_panel_out>; - }; - }; - }; }; -arduino_i2c: &lpi2c1 {}; +nxp_touch_i2c: &lpi2c1 {}; -&lcdif { - status = "okay"; - width = <480>; - height = <272>; - display-timings { - compatible = "zephyr,panel-timing"; - hsync-len = <41>; - hfront-porch = <4>; - hback-porch = <8>; - vsync-len = <10>; - vfront-porch = <4>; - vback-porch = <2>; - de-active= <1>; - pixelclk-active = <1>; - hsync-active = <0>; - vsync-active = <0>; - clock-frequency = <9210240>; - }; - pixel-format = ; - data-bus-width = "16-bit"; +zephyr_lcdif: &lcdif { pinctrl-0 = <&pinmux_lcdif>; pinctrl-names = "default"; - backlight-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; - port { - lcd_panel_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; }; +nxp_parallel_i2c: &lpi2c1 {}; + &lpi2c1 { status = "okay"; pinctrl-0 = <&pinmux_lpi2c1>; pinctrl-names = "default"; - mt9m114: mt9m114@48 { - compatible = "aptina,mt9m114"; - reg = <0x48>; - status = "okay"; - - port { - mt9m114_ep_out: endpoint { - remote-endpoint = <&csi_ep_in>; - }; - }; - }; - ft5336: ft5336@38 { compatible = "focaltech,ft5336"; reg = <0x38>; @@ -202,22 +184,22 @@ arduino_i2c: &lpi2c1 {}; compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - boot_partition: partition@0 { label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(64)>; + reg = <0x00000000 DT_SIZE_K(128)>; }; - /* Note slot 0 has one additional sector, - * this is intended for use with the swap move algorithm + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. */ - slot0_partition: partition@10000 { + slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00010000 DT_SIZE_K(2016)>; + reg = <0x00020000 (DT_SIZE_K(1980) + DT_SIZE_K(8))>; }; - slot1_partition: partition@208000 { + slot1_partition: partition@211000 { label = "image-1"; - reg = <0x00208000 DT_SIZE_K(2012)>; + reg = <0x00211000 DT_SIZE_K(1980)>; }; + /* The storage partition is located in is25wp064 */ }; }; @@ -253,9 +235,9 @@ arduino_serial: &lpuart3 { compatible = "microchip,ksz8081"; reg = <0>; status = "okay"; - mc,reset-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - mc,interrupt-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; - mc,interface-type = "rmii"; + reset-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + int-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + microchip,interface-type = "rmii"; }; }; @@ -271,16 +253,8 @@ zephyr_udc0: &usb1 { }; &csi { - status = "okay"; - source = <&mt9m114>; pinctrl-0 = <&pinmux_csi>; pinctrl-names = "default"; - - port { - csi_ep_in: endpoint { - remote-endpoint = <&mt9m114_ep_out>; - }; - }; }; &flexpwm2_pwm3 { @@ -362,3 +336,15 @@ zephyr_udc0: &usb1 { pinctrl-0 = <&pinmux_swo>; pinctrl-names = "default"; }; + +&pxp { + status = "okay"; +}; + +&pit0 { + status = "okay"; +}; + +dvp_fpc24_i2c: &lpi2c1 {}; + +dvp_fpc24_interface: &csi {}; diff --git a/boards/nxp/mimxrt1160_evk/Kconfig.defconfig b/boards/nxp/mimxrt1160_evk/Kconfig.defconfig index 340878191a0..d4743f1db06 100644 --- a/boards/nxp/mimxrt1160_evk/Kconfig.defconfig +++ b/boards/nxp/mimxrt1160_evk/Kconfig.defconfig @@ -31,15 +31,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC default 240000000 if BOARD_MIMXRT1160_EVK_MIMXRT1166_CM4 && CORTEX_M_SYSTICK default 600000000 if BOARD_MIMXRT1160_EVK_MIMXRT1166_CM7 && CORTEX_M_SYSTICK -if FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI - -choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET - default FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM if CPU_CORTEX_M7 - default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM if CPU_CORTEX_M4 -endchoice - -endif # FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI - if NETWORKING config NET_L2_ETHERNET diff --git a/boards/nxp/mimxrt1160_evk/doc/index.rst b/boards/nxp/mimxrt1160_evk/doc/index.rst index deaac1c22ec..5b8a110d1b0 100644 --- a/boards/nxp/mimxrt1160_evk/doc/index.rst +++ b/boards/nxp/mimxrt1160_evk/doc/index.rst @@ -145,6 +145,11 @@ already supported, which can also be re-used on this mimxrt1160_evk board: +-----------+------------+-------------------------------------+ | PIT | on-chip | pit | +-----------+------------+-------------------------------------+ +| DISPLAY | on-chip | eLCDIF; MIPI-DSI. Tested with | +| | | :ref:`rk055hdmipi4m`, | +| | | :ref:`rk055hdmipi4ma0`, | +| | | and :ref:`g1120b0mipi` shields | ++-----------+------------+-------------------------------------+ The default configuration can be found in the defconfig file: :zephyr_file:`boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7_defconfig` @@ -309,7 +314,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Before power on the board, make sure SW1 is set to 0001b @@ -330,7 +335,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk-pinctrl.dtsi b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk-pinctrl.dtsi index e9428ef79e6..15ad56deb2d 100644 --- a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk-pinctrl.dtsi +++ b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk-pinctrl.dtsi @@ -169,6 +169,7 @@ drive-strength = "normal"; drive-open-drain; slew-rate = "fast"; + input-enable; }; }; diff --git a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk.dtsi b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk.dtsi index 62d3bd59998..3d74d093105 100644 --- a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk.dtsi +++ b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk.dtsi @@ -5,6 +5,7 @@ */ #include "mimxrt1160_evk-pinctrl.dtsi" +#include #include / { @@ -66,7 +67,7 @@ &lpi2c5 { status = "okay"; - pinctrl-0 = <&pinmux_lpi2c1>; + pinctrl-0 = <&pinmux_lpi2c5>; pinctrl-names = "default"; fxos8700: fxos8700@1f { @@ -91,7 +92,7 @@ reg = <0x400cc000 0x4000>, <0x30000000 DT_SIZE_M(16)>; is25wp128: is25wp128@0 { compatible = "nxp,imx-flexspi-nor"; - size = <134217728>; + size = ; reg = <0>; spi-max-frequency = <133000000>; status = "okay"; @@ -103,25 +104,24 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; - /* Note slot 0 has one additional sector, - * this is intended for use with the swap move algorithm + /* The MCUBoot swap-move algorithm uses the last 3 sectors + * of the primary slot0 for swap status and move. */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 0x301000>; + reg = <0x00020000 (DT_SIZE_M(7) + DT_SIZE_K(12))>; }; - slot1_partition: partition@321000 { + slot1_partition: partition@723000 { label = "image-1"; - reg = <0x00321000 0x300000>; + reg = <0x00723000 DT_SIZE_M(7)>; }; - storage_partition: partition@621000 { + storage_partition: partition@E23000 { label = "storage"; - reg = <0x00621000 DT_SIZE_K(1984)>; + reg = <0x00E23000 (DT_SIZE_M(2) - DT_SIZE_K(140))>; }; }; }; @@ -150,9 +150,9 @@ compatible = "microchip,ksz8081"; reg = <0>; status = "okay"; - mc,reset-gpio = <&gpio12 12 GPIO_ACTIVE_HIGH>; - mc,interrupt-gpio = <&gpio9 11 GPIO_ACTIVE_HIGH>; - mc,interface-type = "rmii"; + reset-gpios = <&gpio12 12 GPIO_ACTIVE_HIGH>; + int-gpios = <&gpio9 11 GPIO_ACTIVE_HIGH>; + microchip,interface-type = "rmii"; }; }; @@ -178,7 +178,7 @@ }; &lpi2c1 { - pinctrl-0 =<&pinmux_lpi2c5>; + pinctrl-0 =<&pinmux_lpi2c1>; pinctrl-names = "default"; }; diff --git a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.dts b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.dts index 2f4e842873f..daf97cca88c 100644 --- a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.dts +++ b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.dts @@ -23,6 +23,7 @@ zephyr,flash-controller = &is25wp128; zephyr,flash = &is25wp128; zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &lpuart1; zephyr,cpu1-region = &ocram; zephyr,ipc = &mailbox_a; }; @@ -36,6 +37,43 @@ aliases { watchdog0 = &wdog1; }; + + /* + * This node describes the GPIO pins mapping of the 44-pin camera + * connector, J2 on the EVK. This camera interface is supported + * on several NXP RT11xx EVKs, such as RT1170 and RT1160 EVK and + * is used with an ov5640 camera module available as a Zephyr shield + */ + nxp_cam_connector: cam-connector { + compatible = "nxp,cam-44pins-connector"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <9 0 &gpio11 15 0>, /* Pin 9, RESETB */ + <17 0 &gpio9 25 0>; /* Pin 17, PWDN */ + }; + + /* + * This node describes the GPIO pins of the MIPI FPC interface, + * J48 on the EVK. This interface is standard to several + * NXP EVKs, and is used with several MIPI displays + * (available as zephyr shields) + */ + nxp_mipi_connector: mipi-connector { + compatible = "gpio-nexus"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio9 29 0>, /* Pin 1, LEDK */ + <21 0 &gpio9 1 0>, /* Pin 21, RESET */ + <22 0 &gpio9 4 0>, /* Pin 22, LPTE */ + <26 0 &gpio6 4 0>, /* Pin 26, CTP_I2C SDA */ + <27 0 &gpio6 5 0>, /* Pin 27, CTP_I2C SCL */ + <28 0 &gpio9 0 0>, /* Pin 28, CTP_RST */ + <29 0 &gpio2 31 0>, /* Pin 29, CTP_INT */ + <32 0 &gpio11 16 0>, /* Pin 32, PWR_EN */ + <34 0 &gpio9 29 0>; /* Pin 34, BL_PWM */ + }; }; &lpuart1 { @@ -97,3 +135,22 @@ zephyr_udc0: &usb1 { &pit2 { status = "okay"; }; + +nxp_cam_i2c: &lpi2c6 {}; + +nxp_mipi_csi: &mipi_csi2rx {}; + +nxp_csi: &csi {}; + +zephyr_lcdif: &lcdif {}; + +zephyr_mipi_dsi: &mipi_dsi { + dphy-ref-frequency = <24000000>; +}; + +nxp_mipi_i2c: &lpi2c5 { + pinctrl-0 = <&pinmux_lpi2c5>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; +}; diff --git a/boards/nxp/mimxrt1170_evk/Kconfig.defconfig b/boards/nxp/mimxrt1170_evk/Kconfig.defconfig index a54b1b8a145..3dcd48449bd 100644 --- a/boards/nxp/mimxrt1170_evk/Kconfig.defconfig +++ b/boards/nxp/mimxrt1170_evk/Kconfig.defconfig @@ -34,15 +34,6 @@ config IMX_USDHC_DAT3_PWR_TOGGLE endif # DISK_DRIVERS -if FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI - -choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET - default FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM if CPU_CORTEX_M7 - default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM if CPU_CORTEX_M4 -endchoice - -endif # FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI - if NETWORKING config NET_L2_ETHERNET diff --git a/boards/nxp/mimxrt1170_evk/Kconfig.sysbuild b/boards/nxp/mimxrt1170_evk/Kconfig.sysbuild new file mode 100644 index 00000000000..aa90200fe71 --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/Kconfig.sysbuild @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +choice MCUBOOT_MODE + default MCUBOOT_MODE_SWAP_WITHOUT_SCRATCH if BOARD_MIMXRT1170_EVK_MIMXRT1176_CM7 +endchoice diff --git a/boards/nxp/mimxrt1170_evk/doc/index.rst b/boards/nxp/mimxrt1170_evk/doc/index.rst index d6a80009e7c..7500442bd1b 100644 --- a/boards/nxp/mimxrt1170_evk/doc/index.rst +++ b/boards/nxp/mimxrt1170_evk/doc/index.rst @@ -69,6 +69,7 @@ Hardware - Expansion port - Arduino interface + - M.2 WIFI/BT interface - CAN bus connector @@ -110,8 +111,8 @@ NXP considers the MIMXRT1170-EVK as the superset board for the i.MX RT11xx family of MCUs. This board is a focus for NXP's Full Platform Support for Zephyr, to better enable the entire RT11xx family. NXP prioritizes enabling this board with new support for Zephyr features. Note that this table -covers two boards: the RT1170 EVK (`mimxrt1170_evk//cm7/cm4`), and -RT1170 EVKB (`mimxrt1170_evk@B//cm7/cm4`) +covers two boards: the RT1170 EVK (``mimxrt1170_evk//cm7/cm4``), and +RT1170 EVKB (``mimxrt1170_evk@B//cm7/cm4``) +-----------+------------+-------------------------------------+-----------------+-----------------+ | Interface | Controller | Driver/Component | RT1170 EVK | RT1170 EVKB | @@ -144,8 +145,9 @@ RT1170 EVKB (`mimxrt1170_evk@B//cm7/cm4`) +-----------+------------+-------------------------------------+-----------------+-----------------+ | WATCHDOG | on-chip | watchdog | Supported (M7) | Supported (M7) | +-----------+------------+-------------------------------------+-----------------+-----------------+ -| ENET | on-chip | ethernet - 10/100M (ENET_QOS or | Supported (M7) | No support | -| ENET1G | | GigE not supported yet) | | | +| ENET | on-chip | ethernet - 10/100M | Supported (M7) | No support | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| ENET1G | on-chip | ethernet - 10/100/1000M | Supported (M7) | No support | +-----------+------------+-------------------------------------+-----------------+-----------------+ | SAI | on-chip | i2s | Supported | No support | +-----------+------------+-------------------------------------+-----------------+-----------------+ @@ -168,6 +170,11 @@ RT1170 EVKB (`mimxrt1170_evk@B//cm7/cm4`) +-----------+------------+-------------------------------------+-----------------+-----------------+ | PIT | on-chip | pit | Supported (M7) | Supported (M7) | +-----------+------------+-------------------------------------+-----------------+-----------------+ +| VIDEO | on-chip | CSI; MIPI CSI-2 Rx. Tested with | Supported (M7) | Supported (M7) | +| | | :ref:`nxp_btb44_ov5640` shield | | | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| UART | NXP NW61x | M.2 WIFI/BT module | Unsupported | Supported (M7) | ++-----------+------------+-------------------------------------+-----------------+-----------------+ The default configuration can be found in the defconfig files: :zephyr_file:`boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_defconfig` @@ -243,6 +250,14 @@ The MIMXRT1170 SoC has six pairs of pinmux/gpio controllers. +---------------------------+----------------+------------------+ | GPIO_AD_20_SAI1_RX_DATA00 | SAI1_RX_DATA00 | SAI | +---------------------------+----------------+------------------+ +| GPIO_DISP_B2_10 | LPUART2_TX | M.2 BT HCI | ++---------------------------+----------------+------------------+ +| GPIO_DISP_B2_11 | LPUART2_RX | M.2 BT HCI | ++---------------------------+----------------+------------------+ +| GPIO_DISP_B2_12 | LPUART2_CTS_B | M.2 BT HCI | ++---------------------------+----------------+------------------+ +| GPIO_DISP_B2_13 | LPUART1_RTS_B | M.2 BT HCI | ++---------------------------+----------------+------------------+ Dual Core samples ***************** @@ -287,9 +302,22 @@ cost of reduced resolution Serial Port =========== -The MIMXRT1170 SoC has 12 UARTs. One is configured for the console and the +The MIMXRT1170 SoC has 12 UARTs. ``LPUART1`` is configured for the console, +``LPUART2`` for the Bluetooth Host Controller Interface (BT HCI), and the remaining are not used. +Fetch Binary Blobs +================== + +The board Bluetooth/WiFi module requires fetching some binary blob files, to do +that run the command: + +.. code-block:: console + + west blobs fetch hal_nxp + +.. note:: Only Bluetooth functionality is currently supported. + Programming and Debugging ************************* @@ -316,6 +344,7 @@ Configuring a Debug Probe A debug probe is used for both flashing and debugging the board. The on-board debugger listed below works with the LinkServer runner by default, or can be reprogrammed with JLink firmware. + - MIMXRT1170-EVKB: :ref:`mcu-link-cmsis-onboard-debug-probe` - MIMXRT1170-EVK: :ref:`opensda-daplink-onboard-debug-probe` @@ -334,9 +363,6 @@ Using LinkServer ---------------- Known limitations with LinkServer and these boards include: -- ``west debug`` does not yet work correctly, and the application image is not -properly written to the memory. `NXP MCUXpresso for Visual Studio Code`_ -can be used to debug Zephyr applications with LinkServer. - ``west flash`` will not write images to non-flash locations. The flash command only works when all data in the image is written to flash memory regions. @@ -364,10 +390,12 @@ We will use the on-board debugger microcontroller as a usb-to-serial adapter for the serial console. The following jumper settings are default on these boards, and are required to connect the UART signals to the USB bridge circuit: + - MIMXRT1170-EVKB: JP2 open (default) - MIMXRT1170-EVK: J31 and J32 shorted (default) Connect a USB cable from your PC to the on-board debugger USB port: + - MIMXRT1170-EVKB: J86 - MIMXRT1170-EVK: J11 @@ -382,7 +410,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Before powering the board, make sure SW1 is set to 0001b @@ -403,7 +431,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -444,3 +472,10 @@ should see the following message in the terminal: .. _NXP MCUXpresso for Visual Studio Code: https://www.nxp.com/design/software/development-software/mcuxpresso-software-and-tools-/mcuxpresso-for-visual-studio-code:MCUXPRESSO-VSC + +ENET1G Driver +============= + +Current default of ethernet driver is to use 100M Ethernet instance ENET. +To use the 1G Ethernet instance ENET1G, include the overlay to west build with +the option ``-DEXTRA_DTC_OVERLAY_FILE=nxp,enet1g.overlay`` instead. diff --git a/boards/nxp/mimxrt1170_evk/dts/nxp,enet1g.overlay b/boards/nxp/mimxrt1170_evk/dts/nxp,enet1g.overlay new file mode 100644 index 00000000000..cff3f6bad7c --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/dts/nxp,enet1g.overlay @@ -0,0 +1,36 @@ +/* + * Copyright 2023-2024 NXP + * + * ENET_1G binding overlay + */ + +/ { + soc { + /delete-node/ ethernet@40424000; + }; +}; + +&enet1g { + status = "okay"; +}; + +&enet1g_mac { + status = "okay"; +}; + +&enet1g_mdio { + status = "okay"; + enet1g_phy: phy@1 { + status = "okay"; + }; +}; + +&enet1g_ptp_clock { + status = "okay"; +}; + +&pinctrl { + /delete-node/ pinmux_enet; + /delete-node/ pinmux_enet_mdio; + /delete-node/ pinmux_ptp; +}; diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk-pinctrl.dtsi b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk-pinctrl.dtsi index 43b1642da96..d33ed7cfb33 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk-pinctrl.dtsi +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk-pinctrl.dtsi @@ -85,6 +85,64 @@ pinmux_ptp: pinmux_ptp { }; + pinmux_enet1g: pinmux_enet1g { + group0 { + pinmux = <&iomuxc_gpio_disp_b1_11_enet_1g_tx_clk_io>, // ENET_RGMII_TXC + <&iomuxc_gpio_disp_b1_01_enet_1g_rx_clk>; // ENET_RGMII_RXC + bias-disable; + drive-strength = "high"; + slew-rate = "fast"; + input-enable; + }; + group1 { + pinmux = <&iomuxc_gpio_disp_b1_09_enet_1g_tdata00>, // ENET_RGMII_TXD0 + <&iomuxc_gpio_disp_b1_08_enet_1g_tdata01>, // ENET_RGMII_TXD1 + <&iomuxc_gpio_disp_b1_07_enet_1g_tdata02>, // ENET_RGMII_TXD2 + <&iomuxc_gpio_disp_b1_06_enet_1g_tdata03>, // ENET_RGMII_TXD3 + <&iomuxc_gpio_disp_b1_10_enet_1g_tx_en>; // ENET_RGMII_TX_EN + drive-strength = "high"; + bias-pull-up; + slew-rate = "fast"; + }; + group2 { + pinmux = <&iomuxc_gpio_disp_b1_02_enet_1g_rdata00>, // ENET_RGMII_RXD0 + <&iomuxc_gpio_disp_b1_03_enet_1g_rdata01>, // ENET_RGMII_RXD1 + <&iomuxc_gpio_disp_b1_04_enet_1g_rdata02>, // ENET_RGMII_RXD2 + <&iomuxc_gpio_disp_b1_05_enet_1g_rdata03>, // ENET_RGMII_RXD3 + <&iomuxc_gpio_disp_b1_00_enet_1g_rx_en>; // ENET_RGMII_RX_EN + drive-strength = "high"; + bias-pull-down; + slew-rate = "fast"; + input-enable; + }; + }; + + pinmux_enet1g_mdio: pinmux_enet1g_mdio { + group0 { + pinmux = <&iomuxc_gpio_disp_b2_13_gpio11_io14>; // ETHPHY_RST_B + drive-strength = "high"; + bias-pull-down; + slew-rate = "slow"; + }; + group1 { + pinmux = <&iomuxc_gpio_disp_b2_12_gpio_mux5_io13>; // RGMII1_PHY_INTB + drive-strength = "high"; + bias-pull-down; + slew-rate = "fast"; + input-enable; + }; + group2 { + pinmux = <&iomuxc_gpio_emc_b2_19_enet_1g_mdc>, // ENET_RGMII_MDC + <&iomuxc_gpio_emc_b2_20_enet_1g_mdio>; // ENET_RGMII_MDIO + drive-strength = "high"; + bias-pull-down; + slew-rate = "fast"; + }; + }; + + pinmux_enet1g_ptp: pinmux_enet1g_ptp { + }; + pinmux_flexcan3: pinmux_flexcan3 { group0 { pinmux = <&iomuxc_lpsr_gpio_lpsr_01_can3_rx>, @@ -232,6 +290,17 @@ }; }; + pinmux_lpuart2_flowcontrol: pinmux_lpuart2_flowcontrol { + group0 { + pinmux = <&iomuxc_gpio_disp_b2_11_lpuart2_rx>, + <&iomuxc_gpio_disp_b2_10_lpuart2_tx>, + <&iomuxc_gpio_disp_b2_12_lpuart2_cts_b>, + <&iomuxc_gpio_disp_b2_13_lpuart2_rts_b>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + pinmux_sai1: pinmux_sai1 { group0 { pinmux = <&iomuxc_gpio_ad_17_sai1_mclk>, diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk.dtsi b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk.dtsi index e70890f911d..c479300c8a9 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk.dtsi +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk.dtsi @@ -5,6 +5,7 @@ */ #include "mimxrt1170_evk-pinctrl.dtsi" +#include #include / { @@ -113,9 +114,9 @@ compatible = "microchip,ksz8081"; reg = <0>; status = "okay"; - mc,reset-gpio = <&gpio12 12 GPIO_ACTIVE_HIGH>; - mc,interrupt-gpio = <&gpio9 11 GPIO_ACTIVE_HIGH>; - mc,interface-type = "rmii"; + reset-gpios = <&gpio12 12 GPIO_ACTIVE_HIGH>; + int-gpios = <&gpio9 11 GPIO_ACTIVE_HIGH>; + microchip,interface-type = "rmii"; }; }; @@ -125,6 +126,34 @@ pinctrl-names = "default"; }; +&enet1g_mac { + status = "disabled"; + pinctrl-0 = <&pinmux_enet1g>; + pinctrl-names = "default"; + phy-handle = <&enet1g_phy>; + phy-connection-type = "rgmii"; + zephyr,random-mac-address; +}; + +&enet1g_mdio { + status = "disabled"; + pinctrl-0 = <&pinmux_enet1g_mdio>; + pinctrl-names = "default"; + enet1g_phy: phy@1 { + compatible = "realtek,rtl8211f"; + reg = <1>; + status = "disabled"; + reset-gpios = <&gpio11 14 GPIO_ACTIVE_HIGH>; + int-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + }; +}; + +&enet1g_ptp_clock { + status = "disabled"; + pinctrl-0 = <&pinmux_enet1g_ptp>; + pinctrl-names = "default"; +}; + &csi { pinctrl-0 = <&pinmux_csi>; pinctrl-names = "default"; @@ -190,7 +219,7 @@ reg = <0x400cc000 0x4000>, <0x30000000 DT_SIZE_M(16)>; is25wp128: is25wp128@0 { compatible = "nxp,imx-flexspi-nor"; - size = <134217728>; + size = ; reg = <0>; spi-max-frequency = <133000000>; status = "okay"; @@ -207,20 +236,20 @@ label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; - /* Note slot 0 has one additional sector, - * this is intended for use with the swap move algorithm + /* The MCUBoot swap-move algorithm uses the last 3 sectors + * of the primary slot0 for swap status and move. */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 0x301000>; + reg = <0x00020000 (DT_SIZE_M(7) + DT_SIZE_K(12))>; }; - slot1_partition: partition@321000 { + slot1_partition: partition@723000 { label = "image-1"; - reg = <0x00321000 0x300000>; + reg = <0x00723000 DT_SIZE_M(7)>; }; - storage_partition: partition@621000 { + storage_partition: partition@E23000 { label = "storage"; - reg = <0x00621000 DT_SIZE_K(1984)>; + reg = <0x00E23000 (DT_SIZE_M(2) - DT_SIZE_K(140))>; }; }; }; diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.overlay b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.overlay index c92d197f548..b65621ee632 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.overlay +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.overlay @@ -22,9 +22,8 @@ status = "okay"; reg = <0x400cc000 0x4000>, <0x30000000 DT_SIZE_M(64)>; w25q512nw:w25q512nw@0 { - /* IS25WP128 flash chip not currently enabled */ compatible = "nxp,imx-flexspi-nor"; - size = ; + size = ; reg = <0>; spi-max-frequency = <133000000>; status = "okay"; @@ -32,10 +31,6 @@ erase-block-size = <4096>; write-block-size = <1>; - /* - * Partitions are present to support dual core operation. - * as flash write is not supported, MCUBoot is not enabled. - */ partitions { compatible = "fixed-partitions"; #address-cells = <1>; @@ -45,20 +40,20 @@ label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; - /* Note slot 0 has one additional sector, - * this is intended for use with the swap move algorithm + /* The MCUBoot swap-move algorithm uses the last 3 sectors + * of the primary slot0 for swap status and move. */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 0x301000>; + reg = <0x00020000 (DT_SIZE_M(7) + DT_SIZE_K(12))>; }; - slot1_partition: partition@321000 { + slot1_partition: partition@723000 { label = "image-1"; - reg = <0x00321000 0x300000>; + reg = <0x00723000 DT_SIZE_M(7)>; }; - storage_partition: partition@621000 { + storage_partition: partition@E23000 { label = "storage"; - reg = <0x00621000 DT_SIZE_K(1984)>; + reg = <0x00E23000 (DT_SIZE_M(50) - DT_SIZE_K(140))>; }; }; }; diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts index 95eff6eb715..f01c8f7f431 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts @@ -28,6 +28,7 @@ zephyr,flash-controller = &is25wp128; zephyr,flash = &is25wp128; zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &lpuart1; zephyr,cpu1-region = &ocram; zephyr,ipc = &mailbox_a; }; @@ -59,6 +60,21 @@ <32 0 &gpio11 16 0>, /* Pin 32, PWR_EN */ <34 0 &gpio9 29 0>; /* Pin 34, BL_PWM */ }; + + /* + * This node describes the GPIO pins mapping of the 44-pin camera + * connector, J2 on the EVK. This camera interface is supported + * on several NXP RT11xx EVKs, such as RT1170 and RT1160 EVK and + * is used with an ov5640 camera module available as a Zephyr shield + */ + nxp_cam_connector: cam-connector { + compatible = "nxp,cam-44pins-connector"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <9 0 &gpio11 15 0>, /* Pin 9, RESETB */ + <17 0 &gpio9 25 0>; /* Pin 17, PWDN */ + }; }; zephyr_lcdif: &lcdif {}; @@ -133,6 +149,14 @@ nxp_mipi_i2c: &lpi2c5 { zephyr_udc0: &usb1 { status = "okay"; + phy_handle = <&usbphy1>; +}; + +&usbphy1 { + status = "okay"; + tx-d-cal = <7>; + tx-cal-45-dp-ohms = <6>; + tx-cal-45-dm-ohms = <6>; }; &mailbox_a { @@ -146,3 +170,9 @@ zephyr_udc0: &usb1 { &pit2 { status = "okay"; }; + +nxp_cam_i2c: &lpi2c6 {}; + +nxp_mipi_csi: &mipi_csi2rx {}; + +nxp_csi: &csi {}; diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.yaml b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.yaml index c7e846adf6a..05eabe8136c 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.yaml +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.yaml @@ -28,4 +28,6 @@ supported: - spi - usb_device - watchdog + - video + - usbd vendor: nxp diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.overlay b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.overlay index a43339de27b..bc7995fcb4e 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.overlay +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.overlay @@ -7,8 +7,10 @@ / { chosen { zephyr,flash = &w25q512nw; - /delete-property/ zephyr,flash-controller; - /delete-property/ zephyr,code-partition; + zephyr,flash-controller = &w25q512nw; + zephyr,flash = &w25q512nw; + zephyr,code-partition = &slot0_partition; + zephyr,bt-hci = &bt_hci_uart; }; aliases { @@ -23,9 +25,8 @@ status = "okay"; reg = <0x400cc000 0x4000>, <0x30000000 DT_SIZE_M(64)>; w25q512nw:w25q512nw@0 { - /* IS25WP128 flash chip not currently enabled */ compatible = "nxp,imx-flexspi-nor"; - size = ; + size = ; reg = <0>; spi-max-frequency = <133000000>; status = "okay"; @@ -33,10 +34,6 @@ erase-block-size = <4096>; write-block-size = <1>; - /* - * Partitions are present to support dual core operation. - * as flash write is not supported, MCUBoot is not enabled. - */ partitions { compatible = "fixed-partitions"; #address-cells = <1>; @@ -46,20 +43,20 @@ label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; - /* Note slot 0 has one additional sector, - * this is intended for use with the swap move algorithm + /* The MCUBoot swap-move algorithm uses the last 3 sectors + * of the primary slot0 for swap status and move. */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 0x301000>; + reg = <0x00020000 (DT_SIZE_M(7) + DT_SIZE_K(12))>; }; - slot1_partition: partition@321000 { + slot1_partition: partition@723000 { label = "image-1"; - reg = <0x00321000 0x300000>; + reg = <0x00723000 DT_SIZE_M(7)>; }; - storage_partition: partition@621000 { + storage_partition: partition@E23000 { label = "storage"; - reg = <0x00621000 DT_SIZE_K(1984)>; + reg = <0x00E23000 (DT_SIZE_M(50) - DT_SIZE_K(140))>; }; }; }; @@ -79,3 +76,29 @@ status = "okay"; }; }; + +m2_hci_uart: &lpuart2 { + pinctrl-0 = <&pinmux_lpuart2_flowcontrol>; + pinctrl-1 = <&pinmux_lpuart2_sleep>; + pinctrl-names = "default", "sleep"; + + bt_hci_uart: bt_hci_uart { + compatible = "zephyr,bt-hci-uart"; + + m2_bt_module { + compatible = "nxp,bt-hci-uart"; + sdio-reset-gpios = <&gpio9 15 GPIO_ACTIVE_HIGH>; + w-disable-gpios = <&gpio9 30 GPIO_ACTIVE_HIGH>; + hci-operation-speed = <115200>; + hw-flow-control; + fw-download-primary-speed = <115200>; + fw-download-secondary-speed = <3000000>; + fw-download-secondary-flowcontrol; + }; + }; +}; + +&m2_hci_uart { + status = "okay"; + current-speed = <115200>; +}; diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.yaml b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.yaml index 5cdfdf97c87..62eeec200ea 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.yaml +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.yaml @@ -26,4 +26,5 @@ supported: - spi - usb_device - watchdog + - video vendor: nxp diff --git a/boards/nxp/mimxrt1180_evk/CMakeLists.txt b/boards/nxp/mimxrt1180_evk/CMakeLists.txt new file mode 100644 index 00000000000..beb30185675 --- /dev/null +++ b/boards/nxp/mimxrt1180_evk/CMakeLists.txt @@ -0,0 +1,30 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + zephyr_library() + if(NOT ((DEFINED CONFIG_BOARD_MIMXRT1180_EVK_MIMXRT1189_CM33) + OR (DEFINED CONFIG_BOARD_MIMXRT1180_EVK_MIMXRT1189_CM7))) + message(WARNING "It appears you are using the board definition for " + "the MIMXRT1180-EVK, but targeting a custom board. You may need to " + "update your flash configuration or device configuration data blocks") + endif() + set(RT1180_BOARD_DIR + "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1180") + if(CONFIG_BOOT_FLEXSPI_NOR) + # Include flash configuration block for RT1180 EVK from NXP's HAL. + # This configuration block may need modification if another flash chip is + # used on your custom board. + zephyr_compile_definitions(XIP_EXTERNAL_FLASH=1) + zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + if(CONFIG_EXTERNAL_MEM_CONFIG_DATA AND CONFIG_NXP_IMX_EXTERNAL_HYPERRAM) + zephyr_compile_definitions(USE_HYPERRAM) + endif() + zephyr_library_sources(${RT1180_BOARD_DIR}/xip/evkmimxrt1180_flexspi_nor_config.c) + zephyr_library_include_directories(${RT1180_BOARD_DIR}/xip) + zephyr_library_include_directories(${RT1180_BOARD_DIR}) + endif() +endif() diff --git a/boards/nxp/mimxrt1180_evk/Kconfig.defconfig b/boards/nxp/mimxrt1180_evk/Kconfig.defconfig new file mode 100644 index 00000000000..3b62e522d2d --- /dev/null +++ b/boards/nxp/mimxrt1180_evk/Kconfig.defconfig @@ -0,0 +1,15 @@ +# MIMXRT1180-EVK board + +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MIMXRT1180_EVK + +# Use External Memory Configuration Data (XMCD) by default when booting primary core (M33) +config EXTERNAL_MEM_CONFIG_DATA + default y if CPU_CORTEX_M33 + +config NXP_IMX_EXTERNAL_HYPERRAM + default y if CPU_CORTEX_M33 + +endif # BOARD_MIMXRT1180_EVK diff --git a/boards/nxp/mimxrt1180_evk/Kconfig.mimxrt1180_evk b/boards/nxp/mimxrt1180_evk/Kconfig.mimxrt1180_evk new file mode 100644 index 00000000000..4d44fd9bd81 --- /dev/null +++ b/boards/nxp/mimxrt1180_evk/Kconfig.mimxrt1180_evk @@ -0,0 +1,10 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_MIMXRT1180_EVK + select SOC_PART_NUMBER_MIMXRT1189CVM8B + select SOC_MIMXRT1189_CM33 if BOARD_MIMXRT1180_EVK_MIMXRT1189_CM33 + select SOC_MIMXRT1189_CM7 if BOARD_MIMXRT1180_EVK_MIMXRT1189_CM7 diff --git a/boards/nxp/mimxrt1180_evk/board.cmake b/boards/nxp/mimxrt1180_evk/board.cmake new file mode 100644 index 00000000000..36f76d83153 --- /dev/null +++ b/boards/nxp/mimxrt1180_evk/board.cmake @@ -0,0 +1,23 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +set(RT1180_BOARD_DIR +"${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1180") +# Note1: Suggest developers use Secure Provisioning Tool(SPT) to download RT1180 image +# SPT can be downloaded on NXP web: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/mcuxpresso-secure-provisioning-tool:MCUXPRESSO-SECURE-PROVISIONING +# Details about the usage of SPT on MIMXRT1180-EVK board can be referred on chapter 7 of getting start with Mcuxpresso SDK for MIMXRT1180-EVK doc in SDK package. +if(CONFIG_SOC_MIMXRT1189_CM33) +board_runner_args(linkserver "--device=MIMXRT1189xxxxx:MIMXRT1180-EVK") +board_runner_args(jlink "--device=MIMXRT1189xxx8_M33" "--reset-after-load" "--tool-opt=-jlinkscriptfile ${RT1180_BOARD_DIR}/jlinkscript/evkmimxrt1180_cm33.jlinkscript") +elseif(CONFIG_SOC_MIMXRT1189_CM7) +# Note: Only support run cm7 image when debugging due to default boot core on board is cm33 core +board_runner_args(linkserver "--device=MIMXRT1189xxxxx:MIMXRT1180-EVK") +board_runner_args(linkserver "--core=cm7") +board_runner_args(jlink "--device=MIMXRT1189xxx8_M7" "--speed=4000" "--no-reset" "--tool-opt=-jlinkscriptfile ${RT1180_BOARD_DIR}/jlinkscript/evkmimxrt1180_cm7.jlinkscript" "--tool-opt=-ir") +endif() + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) diff --git a/boards/nxp/mimxrt1180_evk/board.yml b/boards/nxp/mimxrt1180_evk/board.yml new file mode 100644 index 00000000000..0153cf4260d --- /dev/null +++ b/boards/nxp/mimxrt1180_evk/board.yml @@ -0,0 +1,5 @@ +board: + name: mimxrt1180_evk + vendor: nxp + socs: + - name: mimxrt1189 diff --git a/boards/nxp/mimxrt1180_evk/doc/index.rst b/boards/nxp/mimxrt1180_evk/doc/index.rst new file mode 100644 index 00000000000..71066d77f3f --- /dev/null +++ b/boards/nxp/mimxrt1180_evk/doc/index.rst @@ -0,0 +1,254 @@ +.. _mimxrt1180_evk: + +NXP MIMXRT1180-EVK +################## + +Overview +******** + +The dual core i.MX RT1180 runs on the Cortex-M33 core at 240 MHz and on the +Cortex-M7 at 792 MHz. The i.MX RT1180 MCU offers support over a wide +temperature range and is qualified for consumer, industrial and automotive +markets. + +.. image:: mimxrt1180_evk.webp + :align: center + :alt: MIMXRT1180-EVK + +Hardware +******** + +- MIMXRT1189CVM8B MCU + + - 240MHz Cortex-M33 & 792Mhz Cortex-M7 + - 1.5MB SRAM with 512KB of TCM for Cortex-M7 and 256KB of TCM for Cortex-M4 + +- Memory + + - 512 Mbit SDRAM + - 128 Mbit QSPI Flash + - 512 Mbit HYPER RAM + - TF socket for SD card + +- Ethernet + + - 1000 Mbit/s Ethernet PHY + +- USB + + - 2* USB 2.0 OTG connector + +- Audio + + - 3.5 mm audio stereo headphone jack + - Board-mounted microphone + - Left and right speaker out connectors + +- Power + + - 5 V DC jack + +- Debug + + - JTAG 20-pin connector + - MCU-Link with DAPLink + +- Expansion port + + - Arduino interface + +- CAN bus connector + +For more information about the MIMXRT1180 SoC and MIMXRT1180-EVK board, see +these references: + +- `i.MX RT1180 Website`_ +- `MIMXRT1180-EVK Website`_ + +External Memory +=============== + +This platform has the following external memories: + ++--------------------+------------+-------------------------------------+ +| Device | Controller | Status | ++====================+============+=====================================+ +| W9825G6KH | SEMC | Enabled via device configuration | +| | | data block, which sets up SEMC at | +| | | boot time | ++--------------------+------------+-------------------------------------+ +| W25Q128JWSIQ | FLEXSPI | Enabled via flash configurationn | +| | | block, which sets up FLEXSPI at | +| | | boot time. | ++--------------------+------------+-------------------------------------+ + +Supported Features +================== + +NXP considers the MIMXRT1180-EVK as the superset board for the i.MX RT118x +family of MCUs. This board is a focus for NXP's Full Platform Support for +Zephyr, to better enable the entire RT118x family. NXP prioritizes enabling +this board with new support for Zephyr features. The mimxrt1180_evk board +configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| GPT | on-chip | counter | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| ACMP | on-chip | analog comparator | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33_defconfig` + +Other hardware features are not currently supported by the port. + + +Connections and I/Os +==================== + +The MIMXRT1180 SoC has six pairs of pinmux/gpio controllers. + ++---------------+-----------------+---------------------------+ +| Name | Function | Usage | ++===============+=================+===========================+ +| GPIO_AON_04 | GPIO | SW8 | ++---------------+-----------------+---------------------------+ +| GPIO_AD_27 | GPIO | LED | ++---------------+-----------------+---------------------------+ +| GPIO_AON_08 | LPUART1_TX | UART Console | ++---------------+-----------------+---------------------------+ +| GPIO_AON_09 | LPUART1_RX | UART Console | ++---------------+-----------------+---------------------------+ + +System Clock +============ + +The MIMXRT1180 SoC is configured to use SysTick as the system clock source, +running at 240MHz. When targeting the M7 core, SysTick will also be used, +running at 792MHz + +Serial Port +=========== + +The MIMXRT1180 SoC has 12 UARTs. One is configured for the console and the +remaining are not used. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`mcu-link-cmsis-onboard-debug-probe`, +however the :ref:`pyocd-debug-host-tools` do not yet support programming the +external flashes on this board so you must reconfigure the board for one of the +following debug probes instead. + +.. _Using J-Link RT1180: + +Using J-Link +------------ + +Please ensure used JLINK above V7.94g and jumper JP5 installed if using +external jlink plus on J37 as debugger. + +When debugging cm33 core, need to ensure the SW5 on "0100" mode. +When debugging cm7 core, need to ensure the SW5 on "0001" mode. +(Only support run cm7 image when debugging due to default boot core on board is cm33 core) + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +There are two options: the onboard debug circuit can be updated with Segger +J-Link firmware, or :ref:`jlink-external-debug-probe` can be attached to the +EVK. + + +Using Linkserver +---------------- + +Please ensure used linkserver above V1.5.30 and jumper JP5 uninstalled. + +When debugging cm33 core, need to ensure the SW5 on "0100" mode. +When debugging cm7 core, need to ensure the SW5 on "0001" mode. +(Only support run cm7 image when debugging due to default boot core on board is cm33 core) + +Configuring a Console +===================== + +Regardless of your choice in debug probe, we will use the MCU-Link +microcontroller as a usb-to-serial adapter for the serial console. Check that +jumpers JP5 and JP3 are **on** (they are on by default when boards ship from +the factory) to connect UART signals to the MCU-Link microcontroller. + +Connect a USB cable from your PC to J53. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :zephyr:code-sample:`hello_world` application on cm33 core. + +Before power on the board, make sure SW5 is set to 0100b + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt1180_evk/mimxrt1189/cm33 + :goals: flash + +Power off the board, then power on the board and +open a serial terminal, reset the board (press the SW3 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v3.7.0-xxx-xxxxxxxxxxxxx ***** + Hello World! mimxrt1180_evk/mimxrt1189/cm33 + +Debugging +========= + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt1180_evk/mimxrt1189/cm33 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v3.7.0-xxx-xxxxxxxxxxxxx ***** + Hello World! mimxrt1180_evk/mimxrt1189/cm33 + +.. _MIMXRT1180-EVK Website: + https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/i-mx-rt1180-evaluation-kit:MIMXRT1180-EVK + +.. _i.MX RT1180 Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt1180-crossover-mcu-with-tsn-switch-and-edgelock:i.MX-RT1180 diff --git a/boards/nxp/mimxrt1180_evk/doc/mimxrt1180_evk.webp b/boards/nxp/mimxrt1180_evk/doc/mimxrt1180_evk.webp new file mode 100644 index 00000000000..6039fa3e4f3 Binary files /dev/null and b/boards/nxp/mimxrt1180_evk/doc/mimxrt1180_evk.webp differ diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk-pinctrl.dtsi b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk-pinctrl.dtsi new file mode 100644 index 00000000000..5b2eba4f8c1 --- /dev/null +++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk-pinctrl.dtsi @@ -0,0 +1,66 @@ +/* + * Copyright 2024 NXP + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#include + +&pinctrl { + pinmux_lpspi3: pinmux_lpspi3 { + group0 { + pinmux = <&iomuxc_gpio_sd_b1_00_lpspi3_pcs0>, + <&iomuxc_gpio_sd_b1_01_lpspi3_sck>, + <&iomuxc_gpio_sd_b1_02_lpspi3_sout>, + <&iomuxc_gpio_sd_b1_03_lpspi3_sin>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + + pinmux_lpuart1: pinmux_lpuart1 { + group0 { + pinmux = <&iomuxc_aon_gpio_aon_09_lpuart1_rxd>, + <&iomuxc_aon_gpio_aon_08_lpuart1_txd>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + + pinmux_lpuart1_sleep: pinmux_lpuart1_sleep { + group0 { + pinmux = <&iomuxc_aon_gpio_aon_09_gpio1_io09>; + drive-strength = "high"; + bias-pull-up; + slew-rate = "fast"; + }; + group1 { + pinmux = <&iomuxc_aon_gpio_aon_08_lpuart1_txd>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + + /* Connected to FXLS8974 */ + pinmux_lpi2c2: pinmux_lpi2c2 { + group0 { + pinmux = <&iomuxc_aon_gpio_aon_15_lpi2c2_sda>, + <&iomuxc_aon_gpio_aon_16_lpi2c2_scl>; + drive-strength = "normal"; + drive-open-drain; + slew-rate = "fast"; + input-enable; + }; + }; + + pinmux_lpi2c3: pinmux_lpi2c3 { + group0 { + pinmux = <&iomuxc_gpio_ad_18_lpi2c3_scl>, + <&iomuxc_gpio_ad_19_lpi2c3_sda>; + drive-strength = "normal"; + drive-open-drain; + slew-rate = "fast"; + input-enable; + }; + }; +}; diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi new file mode 100644 index 00000000000..a6b51df8239 --- /dev/null +++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi @@ -0,0 +1,83 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "mimxrt1180_evk-pinctrl.dtsi" +#include + +/ { + aliases { + led0 = &green_led; + sw0 = &user_button; + }; + + leds { + compatible = "gpio-leds"; + green_led: led-1 { + gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; + label = "User LED D6"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button: button-1 { + label = "User SW8"; + gpios = <&gpio1 4 (GPIO_PULL_UP | GPIO_ACTIVE_HIGH)>; + zephyr,code = ; + }; + }; +}; + +&lpuart1 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&pinmux_lpuart1>; + pinctrl-1 = <&pinmux_lpuart1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&user_button { + status = "okay"; +}; + +&green_led { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&flexspi1 { + status = "okay"; + ahb-prefetch; + ahb-read-addr-opt; + rx-clock-source = <1>; + w25q128jw: w25q128jw@0 { + compatible = "nxp,imx-flexspi-nor"; + size = <134217728>; + reg = <0>; + spi-max-frequency = <133000000>; + status = "okay"; + jedec-id = [ef 80 18]; + erase-block-size = <4096>; + write-block-size = <1>; + }; +}; + +&lpi2c2 { + pinctrl-0 = <&pinmux_lpi2c2>; + pinctrl-names = "default"; +}; + +&lpi2c3 { + pinctrl-0 = <&pinmux_lpi2c3>; + pinctrl-names = "default"; +}; diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.dts b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.dts new file mode 100644 index 00000000000..5b9d29bd58d --- /dev/null +++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.dts @@ -0,0 +1,45 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "mimxrt1180_evk.dtsi" + +/ { + model = "NXP MIMXRT1180-EVK board"; + compatible = "nxp,mimxrt1189"; + + chosen { + zephyr,sram = &hyperram0; + zephyr,dtcm = &dtcm; + zephyr,itcm = &itcm; + zephyr,flash-controller = &w25q128jw; + zephyr,flash = &w25q128jw; + zephyr,console = &lpuart1; + zephyr,shell-uart = &lpuart1; + }; + + hyperram0: memory@14000000 { + /* Winbond W957A8MFYA5K */ + device_type = "memory"; + reg = <0x14000000 DT_SIZE_M(8)>; + }; +}; + +&lpuart1 { + status = "okay"; + current-speed = <115200>; +}; + + +&systick { + status = "okay"; +}; + +&gpt2 { + status = "okay"; +}; diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.yaml b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.yaml new file mode 100644 index 00000000000..485f26734ac --- /dev/null +++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.yaml @@ -0,0 +1,22 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mimxrt1180_evk/mimxrt1189/cm33 +name: NXP MIMXRT1180-EVK CM33 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 128 +flash: 16384 +supported: + - gpio + - uart + - i2c + - counter +vendor: nxp diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33_defconfig b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33_defconfig new file mode 100644 index 00000000000..d5b8dbd0d80 --- /dev/null +++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33_defconfig @@ -0,0 +1,15 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_PINCTRL=y +# Enable TrustZone-M +CONFIG_TRUSTED_EXECUTION_SECURE=y diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.dts b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.dts new file mode 100644 index 00000000000..e6a55ae5dc9 --- /dev/null +++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.dts @@ -0,0 +1,36 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "mimxrt1180_evk.dtsi" + +/ { + model = "NXP MIMXRT1180-EVK board"; + compatible = "nxp,mimxrt1189"; + + chosen { + zephyr,sram = &dtcm; + zephyr,flash-controller = &w25q128jw; + zephyr,flash = &itcm; + zephyr,console = &lpuart1; + zephyr,shell-uart = &lpuart1; + }; +}; + +&lpuart1 { + status = "okay"; + current-speed = <115200>; +}; + +&systick { + status = "okay"; +}; + +&gpt2 { + status = "okay"; +}; diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.yaml b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.yaml new file mode 100644 index 00000000000..504ce887ac0 --- /dev/null +++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.yaml @@ -0,0 +1,22 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mimxrt1180_evk/mimxrt1189/cm7 +name: NXP MIMXRT1180-EVK CM7 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 256 +flash: 256 +supported: + - gpio + - uart + - i2c + - counter +vendor: nxp diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7_defconfig b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7_defconfig new file mode 100644 index 00000000000..89be0a5ebab --- /dev/null +++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7_defconfig @@ -0,0 +1,14 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_PINCTRL=y +CONFIG_NXP_IMXRT_BOOT_HEADER=n diff --git a/boards/nxp/mimxrt595_evk/Kconfig.defconfig b/boards/nxp/mimxrt595_evk/Kconfig.defconfig index 9813fb6bdf1..f5061f58d32 100644 --- a/boards/nxp/mimxrt595_evk/Kconfig.defconfig +++ b/boards/nxp/mimxrt595_evk/Kconfig.defconfig @@ -8,10 +8,6 @@ if BOARD_MIMXRT595_EVK_MIMXRT595S_CM33 config FLASH_MCUX_FLEXSPI_MX25UM51345G default y if FLASH -choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET - default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM -endchoice - config FXOS8700_DRDY_INT1 default y depends on FXOS8700_TRIGGER diff --git a/boards/nxp/mimxrt595_evk/board.c b/boards/nxp/mimxrt595_evk/board.c index dd2cb36354c..8db60fdcb6b 100644 --- a/boards/nxp/mimxrt595_evk/board.c +++ b/boards/nxp/mimxrt595_evk/board.c @@ -279,34 +279,32 @@ static int mimxrt595_evk_init(void) pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES); #ifdef CONFIG_I2S - +#ifdef CONFIG_I2S_TEST_SEPARATE_DEVICES /* Set shared signal set 0 SCK, WS from Transmit I2S - Flexcomm3 */ SYSCTL1->SHAREDCTRLSET[0] = SYSCTL1_SHAREDCTRLSET_SHAREDSCKSEL(3) | SYSCTL1_SHAREDCTRLSET_SHAREDWSSEL(3); - -#ifdef CONFIG_I2S_TEST_SEPARATE_DEVICES /* Select Data in from Transmit I2S - Flexcomm 3 */ SYSCTL1->SHAREDCTRLSET[0] |= SYSCTL1_SHAREDCTRLSET_SHAREDDATASEL(3); /* Enable Transmit I2S - Flexcomm 3 for Shared Data Out */ SYSCTL1->SHAREDCTRLSET[0] |= SYSCTL1_SHAREDCTRLSET_FC3DATAOUTEN(1); +#else + /* Set shared signal set 0: SCK, WS from Flexcomm1 */ + SYSCTL1->SHAREDCTRLSET[0] = SYSCTL1_SHAREDCTRLSET_SHAREDSCKSEL(1) | + SYSCTL1_SHAREDCTRLSET_SHAREDWSSEL(1); #endif - /* Set Receive I2S - Flexcomm 1 SCK, WS from shared signal set 0 */ SYSCTL1->FCCTRLSEL[1] = SYSCTL1_FCCTRLSEL_SCKINSEL(1) | SYSCTL1_FCCTRLSEL_WSINSEL(1); - /* Set Transmit I2S - Flexcomm 3 SCK, WS from shared signal set 0 */ SYSCTL1->FCCTRLSEL[3] = SYSCTL1_FCCTRLSEL_SCKINSEL(1) | SYSCTL1_FCCTRLSEL_WSINSEL(1); - #ifdef CONFIG_I2S_TEST_SEPARATE_DEVICES /* Select Receive I2S - Flexcomm 1 Data in from shared signal set 0 */ SYSCTL1->FCCTRLSEL[1] |= SYSCTL1_FCCTRLSEL_DATAINSEL(1); /* Select Transmit I2S - Flexcomm 3 Data out to shared signal set 0 */ SYSCTL1->FCCTRLSEL[3] |= SYSCTL1_FCCTRLSEL_DATAOUTSEL(1); -#endif - -#endif +#endif /* CONFIG_I2S_TEST_SEPARATE_DEVICES */ +#endif /* CONFIG_I2S */ #ifdef CONFIG_REBOOT diff --git a/boards/nxp/mimxrt595_evk/doc/index.rst b/boards/nxp/mimxrt595_evk/doc/index.rst index 5be8e0da21c..5465a912e8b 100644 --- a/boards/nxp/mimxrt595_evk/doc/index.rst +++ b/boards/nxp/mimxrt595_evk/doc/index.rst @@ -244,7 +244,7 @@ Connect a USB cable from your PC to J40, and use the serial terminal of your cho Flashing ======== -Here is an example for the :ref:`hello_world` application. This example uses the +Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the :ref:`jlink-debug-host-tools` as default. .. zephyr-app-commands:: @@ -263,7 +263,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. This example uses the +Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the :ref:`jlink-debug-host-tools` as default. .. zephyr-app-commands:: diff --git a/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33-pinctrl.dtsi b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33-pinctrl.dtsi index 3f1bb622689..cb994f3326e 100644 --- a/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33-pinctrl.dtsi +++ b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33-pinctrl.dtsi @@ -2,7 +2,7 @@ * NOTE: File generated by gen_board_pinctrl.py * from MIMXRT595-EVK.mex * - * Copyright 2022, NXP + * Copyright 2022, 2024 NXP * SPDX-License-Identifier: Apache-2.0 */ @@ -29,7 +29,8 @@ group0 { pinmux = , , - ; + , + ; slew-rate = "normal"; input-enable; drive-strength = "high"; @@ -39,7 +40,7 @@ /* TX */ pinmux_flexcomm3_i2s: pinmux_flexcomm3_i2s { group0 { - pinmux = ; + pinmux = , ; input-enable; slew-rate = "normal"; drive-strength = "high"; @@ -236,8 +237,9 @@ pinmux = , ; input-enable; + bias-pull-up; slew-rate = "slow"; - drive-strength = "high"; + drive-strength = "normal"; }; group1 { @@ -246,5 +248,4 @@ drive-strength = "normal"; }; }; - }; diff --git a/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.dts b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.dts index eccf7d45365..2bccfcbed57 100644 --- a/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.dts +++ b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.dts @@ -35,6 +35,7 @@ zephyr,flash-controller = &mx25um51345g; zephyr,flash = &mx25um51345g; zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &flexcomm0; zephyr,sram = &sram0; zephyr,console = &flexcomm0; zephyr,shell-uart = &flexcomm0; @@ -396,7 +397,7 @@ zephyr_udc0: &usbhs { status = "okay"; jedec-id = [c2 81 3a]; erase-block-size = <4096>; - write-block-size = <16>; + write-block-size = <2>; /* FLASH_MCUX_FLEXSPI_MX25UM51345G_OPI_DTR set */ partitions { compatible = "fixed-partitions"; @@ -407,17 +408,20 @@ zephyr_udc0: &usbhs { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; + /* The MCUBoot swap-move algorithm uses the last 3 sectors + * of the primary slot0 for swap status and move. + */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 DT_SIZE_K(3076)>; + reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(3 * 4))>; }; - slot1_partition: partition@321000 { + slot1_partition: partition@323000 { label = "image-1"; - reg = <0x00321000 DT_SIZE_K(3072)>; + reg = <0x00323000 DT_SIZE_M(3)>; }; - storage_partition: partition@621000 { + storage_partition: partition@623000 { label = "storage"; - reg = <0x00621000 DT_SIZE_M(57)>; + reg = <0x00623000 (DT_SIZE_M(58) - DT_SIZE_K(140))>; }; }; }; @@ -461,6 +465,15 @@ zephyr_udc0: &usbhs { pinctrl-names = "default"; status = "okay"; + + audio_codec: wm8904@1a0000000000000000 { + compatible = "wolfson,wm8904"; + reg = <0x1a 0 0>; + clock-source = "MCLK"; + + clocks = <&clkctl0 MCUX_AUDIO_MCLK>; + clock-names = "mclk"; + }; }; &mbox { diff --git a/boards/nxp/mimxrt595_evk/pre_dt_board.cmake b/boards/nxp/mimxrt595_evk/pre_dt_board.cmake deleted file mode 100644 index 5dd7773bba4..00000000000 --- a/boards/nxp/mimxrt595_evk/pre_dt_board.cmake +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2022, NXP -# SPDX-License-Identifier: Apache-2.0 - -# Suppress "simple_bus_reg" on RT5XX boards as all GPIO ports use the same register. -list(APPEND EXTRA_DTC_FLAGS "-Wno-simple_bus_reg") diff --git a/boards/nxp/mimxrt685_evk/Kconfig.defconfig b/boards/nxp/mimxrt685_evk/Kconfig.defconfig index 02a69187a24..680230281ec 100644 --- a/boards/nxp/mimxrt685_evk/Kconfig.defconfig +++ b/boards/nxp/mimxrt685_evk/Kconfig.defconfig @@ -18,10 +18,6 @@ choice FLASH_MCUX_FLEXSPI_MX25UM51345G_OPI_MODE default FLASH_MCUX_FLEXSPI_MX25UM51345G_OPI_STR endchoice -choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET - default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM -endchoice - config FXOS8700_DRDY_INT1 default y depends on FXOS8700_TRIGGER diff --git a/boards/nxp/mimxrt685_evk/doc/index.rst b/boards/nxp/mimxrt685_evk/doc/index.rst index 109dfde16e6..4f53d6435b5 100644 --- a/boards/nxp/mimxrt685_evk/doc/index.rst +++ b/boards/nxp/mimxrt685_evk/doc/index.rst @@ -110,7 +110,7 @@ already supported, which can also be re-used on this mimxrt685_evk board: +-----------+------------+-------------------------------------+ The default configuration can be found in -:zephyr_file:`boards/nxp/mimxrt685_evk/mimxrt685_evk_defconfig` +:zephyr_file:`boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33_defconfig` Other hardware features are not currently supported by the port. @@ -285,7 +285,7 @@ Connect a USB cable from your PC to J16, and use the serial terminal of your cho Flashing ======== -Here is an example for the :ref:`hello_world` application. This example uses the +Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the :ref:`linkserver-debug-host-tools` as default. .. zephyr-app-commands:: @@ -304,7 +304,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. This example uses the +Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the :ref:`linkserver-debug-host-tools` as default. .. zephyr-app-commands:: @@ -363,7 +363,7 @@ steps: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt600-crossover-mcu-with-arm-cortex-m33-and-dsp-cores:i.MX-RT600 .. _i.MX RT685 Datasheet: - https://www.nxp.com/docs/en/data-sheet/DS-RT600.pdf + https://www.nxp.com/docs/en/data-sheet/RT600.pdf .. _i.MX RT685 Reference Manual: https://www.nxp.com/webapp/Download?colCode=UM11147 diff --git a/boards/nxp/mimxrt685_evk/mimxrt685_evk-pinctrl.dtsi b/boards/nxp/mimxrt685_evk/mimxrt685_evk-pinctrl.dtsi index 63febf90fce..ece0fe64b8e 100644 --- a/boards/nxp/mimxrt685_evk/mimxrt685_evk-pinctrl.dtsi +++ b/boards/nxp/mimxrt685_evk/mimxrt685_evk-pinctrl.dtsi @@ -2,7 +2,7 @@ * NOTE: File generated by gen_board_pinctrl.py * from MIMXRT685-EVK.mex * - * Copyright 2022, NXP + * Copyright 2022, 2024 NXP * SPDX-License-Identifier: Apache-2.0 */ @@ -49,7 +49,8 @@ group0 { pinmux = , , - ; + , + ; input-enable; slew-rate = "normal"; drive-strength = "high"; @@ -82,6 +83,16 @@ }; }; + pinmux_dmic0: pinmux_dmic0 { + group0 { + pinmux = , , + ; + slew-rate = "normal"; + drive-strength = "normal"; + input-enable; + }; + }; + pinmux_flexspi: pinmux_flexspi { group0 { pinmux = , diff --git a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts index a7df8a693ef..3228147ec31 100644 --- a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts +++ b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2023, NXP + * Copyright 2020-2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -33,12 +33,14 @@ magn0 = &fxos8700; accel0 = &fxos8700; sdhc0 = &usdhc0; + dmic-dev = &dmic0; }; chosen { zephyr,flash-controller = &mx25um51345g; zephyr,flash = &mx25um51345g; zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &flexcomm0; zephyr,sram = &sram0; zephyr,console = &flexcomm0; zephyr,shell-uart = &flexcomm0; @@ -257,7 +259,7 @@ i2s1: &flexcomm3 { status = "okay"; jedec-id = [c2 81 3a]; erase-block-size = <4096>; - write-block-size = <16>; + write-block-size = <1>; /* FLASH_MCUX_FLEXSPI_MX25UM51345G_OPI_STR set */ partitions { compatible = "fixed-partitions"; @@ -268,17 +270,20 @@ i2s1: &flexcomm3 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. + */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 DT_SIZE_K(3076)>; + reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(2 * 4))>; }; - slot1_partition: partition@321000 { + slot1_partition: partition@323000 { label = "image-1"; - reg = <0x00321000 DT_SIZE_K(3072)>; + reg = <0x00323000 DT_SIZE_M(3)>; }; - storage_partition: partition@621000 { + storage_partition: partition@623000 { label = "storage"; - reg = <0x00621000 DT_SIZE_M(57)>; + reg = <0x00623000 (DT_SIZE_M(58) - DT_SIZE_K(136))>; }; }; }; @@ -352,6 +357,14 @@ i2s1: &flexcomm3 { zephyr_udc0: &usbhs { status = "okay"; + phy_handle = <&usbphy>; +}; + +&usbphy { + status = "okay"; + tx-d-cal = <12>; + tx-cal-45-dp-ohms = <6>; + tx-cal-45-dm-ohms = <6>; }; &ctimer0 { @@ -379,9 +392,43 @@ zephyr_udc0: &usbhs { pinctrl-names = "default"; status = "okay"; + + audio_codec: wm8904@1a0000000000000000 { + compatible = "wolfson,wm8904"; + reg = <0x1a 0 0>; + + clock-source = "MCLK"; + + clocks = <&clkctl0 MCUX_AUDIO_MCLK>; + clock-names = "mclk"; + }; }; /* Disable this node if not using USB and need another MPU region */ &sram1 { status = "okay"; }; + +&dmic0 { + status = "okay"; + pinctrl-0 = <&pinmux_dmic0>; + pinctrl-names = "default"; + use2fs; +}; + +/* Configure pdm channels 0 and 1 with gain, and cutoff settings + * appropriate for the attached MEMS microphones. + */ +&pdmc0 { + status = "okay"; + gainshift = <3>; + dc-cutoff = "155hz"; + dc-gain = <1>; +}; + +&pdmc1 { + status = "okay"; + gainshift = <3>; + dc-cutoff = "155hz"; + dc-gain = <1>; +}; diff --git a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.yaml b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.yaml index 22ab15ecfd9..59ccb0922be 100644 --- a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.yaml +++ b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.yaml @@ -31,4 +31,5 @@ supported: - spi - watchdog - usb_device + - usbd vendor: nxp diff --git a/boards/nxp/mimxrt685_evk/pre_dt_board.cmake b/boards/nxp/mimxrt685_evk/pre_dt_board.cmake deleted file mode 100644 index e23600abc77..00000000000 --- a/boards/nxp/mimxrt685_evk/pre_dt_board.cmake +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2020, NXP -# SPDX-License-Identifier: Apache-2.0 - -# Suppress "simple_bus_reg" on RT6XX boards as all GPIO ports use the same register. -list(APPEND EXTRA_DTC_FLAGS "-Wno-simple_bus_reg") diff --git a/boards/nxp/mr_canhubk3/doc/index.rst b/boards/nxp/mr_canhubk3/doc/index.rst index f398e170857..1de065e202a 100644 --- a/boards/nxp/mr_canhubk3/doc/index.rst +++ b/boards/nxp/mr_canhubk3/doc/index.rst @@ -56,10 +56,13 @@ LPI2C on-chip i2c ADC SAR on-chip adc LPSPI on-chip spi WDT FS26 SBC watchdog +SWT on-chip watchdog EMAC on-chip ethernet mdio eMIOS on-chip pwm EDMA on-chip dma +FLEXIO PWM on-chip pwm +STM on-chip counter ============ ========== ================================ The default configuration can be found in the Kconfig file diff --git a/boards/nxp/mr_canhubk3/mr_canhubk3-pinctrl.dtsi b/boards/nxp/mr_canhubk3/mr_canhubk3-pinctrl.dtsi index 49c4d164c81..9a9e7894a7d 100644 --- a/boards/nxp/mr_canhubk3/mr_canhubk3-pinctrl.dtsi +++ b/boards/nxp/mr_canhubk3/mr_canhubk3-pinctrl.dtsi @@ -300,6 +300,13 @@ }; }; + flexio0_pwm_default: flexio0_pwm_default { + group1 { + pinmux = , ; + output-enable; + }; + }; + qdec_s32: qdec_s32 { group1 { pinmux = , diff --git a/boards/nxp/mr_canhubk3/mr_canhubk3.dts b/boards/nxp/mr_canhubk3/mr_canhubk3.dts index ba74e255f62..6759aaf49fb 100644 --- a/boards/nxp/mr_canhubk3/mr_canhubk3.dts +++ b/boards/nxp/mr_canhubk3/mr_canhubk3.dts @@ -37,9 +37,10 @@ led2 = &user_led1_blue; sw0 = &user_button_1; sw1 = &user_button_2; - watchdog0 = &fs26_wdt; + watchdog0 = &swt0; /* For pwm test suites */ pwm-0 = &emios0_pwm; + pwm-1 = &flexio0_pwm; red-pwm-led = &user_led1_red_pwm; green-pwm-led = &user_led1_green_pwm; blue-pwm-led = &user_led1_blue_pwm; @@ -200,6 +201,10 @@ }; }; +&pmc { + lm-reg; +}; + &flash0 { partitions { compatible = "fixed-partitions"; @@ -616,6 +621,27 @@ }; }; +&flexio0 { + status = "okay"; + + flexio0_pwm: flexio0_pwm { + pinctrl-0 = <&flexio0_pwm_default>; + pinctrl-names = "default"; + status = "okay"; + + pwm_0 { + pin-id = <19>; + prescaler = <1>; + }; + + pwm_1 { + pin-id = <11>; + prescaler = <1>; + }; + }; + +}; + &lcu1 { status = "okay"; }; diff --git a/boards/nxp/mr_canhubk3/mr_canhubk3.yaml b/boards/nxp/mr_canhubk3/mr_canhubk3.yaml index 010db5cdf3c..7fd4f2b7996 100644 --- a/boards/nxp/mr_canhubk3/mr_canhubk3.yaml +++ b/boards/nxp/mr_canhubk3/mr_canhubk3.yaml @@ -21,4 +21,5 @@ supported: - pwm - dma - display + - counter vendor: nxp diff --git a/boards/nxp/rd_rw612_bga/Kconfig.defconfig b/boards/nxp/rd_rw612_bga/Kconfig.defconfig index 376f96da2b3..6f644448c7f 100644 --- a/boards/nxp/rd_rw612_bga/Kconfig.defconfig +++ b/boards/nxp/rd_rw612_bga/Kconfig.defconfig @@ -34,4 +34,11 @@ endif # LVGL config INPUT_FT5336_INTERRUPT default y if INPUT +if DT_HAS_NXP_ENET_MAC_ENABLED && NETWORKING + +config NET_L2_ETHERNET + default y + +endif # DT_HAS_NXP_ENET_MAC_ENABLED && NETWORKING + endif # BOARD_RD_RW612_BGA diff --git a/boards/nxp/rd_rw612_bga/board.yml b/boards/nxp/rd_rw612_bga/board.yml index fe2573bfdbb..3316d695614 100644 --- a/boards/nxp/rd_rw612_bga/board.yml +++ b/boards/nxp/rd_rw612_bga/board.yml @@ -3,3 +3,5 @@ board: vendor: nxp socs: - name: rw612 + variants: + - name: ethernet diff --git a/boards/nxp/rd_rw612_bga/doc/index.rst b/boards/nxp/rd_rw612_bga/doc/index.rst index 42783abb9bb..e0215ececad 100644 --- a/boards/nxp/rd_rw612_bga/doc/index.rst +++ b/boards/nxp/rd_rw612_bga/doc/index.rst @@ -66,6 +66,8 @@ Supported Features | PM | on-chip | power management; uses SoC Power | | | | Modes 1 and 2 | +-----------+------------+-----------------------------------+ +| BLE | on-chip | Bluetooth | ++-----------+------------+-----------------------------------+ The default configuration can be found in the defconfig file: @@ -73,6 +75,16 @@ The default configuration can be found in the defconfig file: Other hardware features are not currently supported +Fetch Binary Blobs +****************** + +To support Bluetooth, rd_rw612_bga requires fetching binary blobs, which can be +achieved by running the following command: + +.. code-block:: console + + west blobs fetch hal_nxp + Programming and Debugging ************************* @@ -99,7 +111,7 @@ Connect a USB cable from your PC to J7, and use the serial terminal of your choi Flashing ======== -Here is an example for the :ref:`hello_world` application. This example uses the +Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the :ref:`jlink-debug-host-tools` as default. .. zephyr-app-commands:: @@ -118,7 +130,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. This example uses the +Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the :ref:`jlink-debug-host-tools` as default. .. zephyr-app-commands:: @@ -134,9 +146,60 @@ should see the following message in the terminal: ***** Booting Zephyr OS zephyr-v3.6.0 ***** Hello World! rd_rw612_bga +Bluetooth +********* + +BLE functionality requires to fetch binary blobs, so make sure to follow +the ``Fetch Binary Blobs`` section first. + +Those binary blobs can be used in two different ways, depending if :kconfig:option:`CONFIG_NXP_MONOLITHIC_BT` +is enabled or not: + +- :kconfig:option:`CONFIG_NXP_MONOLITHIC_BT` is enabled (default): + +The required binary blob will be linked with the application image directly, forming +one single monolithic image. +The user has nothing else to do other than flashing the application to the board. + +- :kconfig:option:`CONFIG_NXP_MONOLITHIC_BT` is disabled: + +In this case, the BLE blob won't be linked with the application, so the user needs to manually +flash the BLE binary blob to the board at the address ``0x18540000``. +The binary blob will be located here: ``/modules/hal/nxp/zephyr/blobs/rw61x/rw61x_sb_ble_a2.bin`` + +Board variants +************** + +Ethernet +======== + +To use ethernet on the RD_RW612_BGA board, you first need to make the following +modifications to the board hardware: + +Add resistors: + +- R485 +- R486 +- R487 +- R488 +- R489 +- R491 +- R490 + +Remove resistors: + +- R522 +- R521 +- R520 +- R524 +- R523 +- R508 +- R505 + +Then, build for the board target ``rd_rw612_bga//ethernet``. Resources -========= +********* .. _RW612 Website: https://www.nxp.com/products/wireless-connectivity/wi-fi-plus-bluetooth-plus-802-15-4/wireless-mcu-with-integrated-tri-radiobr1x1-wi-fi-6-plus-bluetooth-low-energy-5-3-802-15-4:RW612 diff --git a/boards/nxp/rd_rw612_bga/pre_dt_board.cmake b/boards/nxp/rd_rw612_bga/pre_dt_board.cmake index 2c56668e435..5da215a0a3b 100644 --- a/boards/nxp/rd_rw612_bga/pre_dt_board.cmake +++ b/boards/nxp/rd_rw612_bga/pre_dt_board.cmake @@ -1,7 +1,5 @@ # Copyright 2023 NXP # SPDX-License-Identifier: Apache-2.0 -# Suppress "simple_bus_reg" on RW6XX boards as all GPIO ports use the same register. -list(APPEND EXTRA_DTC_FLAGS "-Wno-simple_bus_reg") # Suppress "spi_bus_bridge" as flexcomm node can be used as a SPI device. list(APPEND EXTRA_DTC_FLAGS "-Wno-spi_bus_bridge") diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi b/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi index db565403583..78193e6b512 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi @@ -14,6 +14,13 @@ }; }; + pinmux_flexcomm0_usart: pinmux_flexcomm0_usart { + group0 { + pinmux = ; + slew-rate = "normal"; + }; + }; + pinmux_flexcomm0_spi: pinmux_flexcomm0_spi { group0 { pinmux = , @@ -87,4 +94,22 @@ bias-pull-down; }; }; + + pinmux_enet: pinmux_enet { + group0 { + pinmux = ; + slew-rate = "fast"; + }; + }; + + pinmux_mdio: pinmux_mdio { + group0 { + pinmux = ; + slew-rate = "fast"; + }; + }; }; diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dts b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dts index 4a3f9588494..41552feecff 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dts +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dts @@ -6,10 +6,4 @@ /dts-v1/; -#include #include "rd_rw612_bga.dtsi" - -/ { - model = "nxp,rd_rw612_bga"; - compatible = "nxp,rd_rw612_bga"; -}; diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi index 3310e806608..ace4c03c56c 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi @@ -4,10 +4,13 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include #include "rd_rw612_bga-pinctrl.dtsi" #include / { + model = "nxp,rd_rw612_bga"; + compatible = "nxp,rd_rw612_bga"; aliases { usart-0 = &flexcomm3; @@ -22,6 +25,7 @@ zephyr,sram = &sram_data; zephyr,flash = &mx25u51245g; zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &flexcomm3; zephyr,flash-controller = &mx25u51245g; zephyr,console = &flexcomm3; zephyr,shell-uart = &flexcomm3; @@ -147,6 +151,16 @@ arduino_i2c: &flexcomm2 { label = "image-0"; reg = <0x00020000 0x3e0000>; }; + + /* This partition is reserved for connectivity firmwares storage + * and shouldn't be moved. + */ + fw_storage: partition@400000 { + label = "fw_storage"; + reg = <0x400000 0x280000>; + read-only; + }; + slot1_partition: partition@680000 { label = "image-1"; reg = <0x680000 0x3e0000>; @@ -264,3 +278,13 @@ zephyr_udc0: &usb_otg { &systick { status = "disabled"; }; + +&hci { + status = "okay"; + wakeup-source; +}; + +&pin1 { + status = "okay"; + wakeup-level = "low"; +}; diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga_rw612_ethernet.dts b/boards/nxp/rd_rw612_bga/rd_rw612_bga_rw612_ethernet.dts new file mode 100644 index 00000000000..2a793e6cdca --- /dev/null +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga_rw612_ethernet.dts @@ -0,0 +1,47 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "rd_rw612_bga.dtsi" + +/* + * To use ethernet on RD_RW612_BGA board: + * + * Load R485, R486, R487, R488, R489, R491, R490, + * R522, R521, R520, R524, R523, R508, R505 + * Remove R518, R507, R506 + */ +&enet_mac { + status = "okay"; + pinctrl-0 = <&pinmux_enet>; + pinctrl-names = "default"; + phy-handle = <&phy>; + zephyr,random-mac-address; + phy-connection-type = "rmii"; +}; + +&enet_mdio { + status = "okay"; + pinctrl-0 = <&pinmux_mdio>; + pinctrl-names = "default"; + phy: phy@2 { + compatible = "microchip,ksz8081"; + reg = <2>; + status = "okay"; + reset-gpios = <&hsgpio1 23 GPIO_ACTIVE_HIGH>; + int-gpios = <&hsgpio0 21 GPIO_ACTIVE_HIGH>; + microchip,interface-type = "rmii"; + }; +}; + +/* XTAL is disconnected */ +/* TODO: this should be uncommented once it is added */ +/* + * &rtc { + * status = "disabled"; + * }; + */ diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga_rw612_ethernet.yaml b/boards/nxp/rd_rw612_bga/rd_rw612_bga_rw612_ethernet.yaml new file mode 100644 index 00000000000..19d26ea8162 --- /dev/null +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga_rw612_ethernet.yaml @@ -0,0 +1,20 @@ +# +# Copyright 2023 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: rd_rw612_bga/rw612/ethernet +name: NXP RD_RW612_BGA ETHERNET +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 960 +flash: 65536 +supported: + - netif:eth +testing: + default: false diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga_rw612_ethernet_defconfig b/boards/nxp/rd_rw612_bga/rd_rw612_bga_rw612_ethernet_defconfig new file mode 100644 index 00000000000..b987fa24dc0 --- /dev/null +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga_rw612_ethernet_defconfig @@ -0,0 +1,15 @@ +# +# Copyright 2022 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_PINCTRL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_TRUSTED_EXECUTION_SECURE=y diff --git a/boards/nxp/rddrone_fmuk66/doc/index.rst b/boards/nxp/rddrone_fmuk66/doc/index.rst index 69d862455ac..e938c685ba7 100644 --- a/boards/nxp/rddrone_fmuk66/doc/index.rst +++ b/boards/nxp/rddrone_fmuk66/doc/index.rst @@ -144,7 +144,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -162,7 +162,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/rddrone_fmuk66/rddrone_fmuk66.dts b/boards/nxp/rddrone_fmuk66/rddrone_fmuk66.dts index 8d2b01c44ba..1dbc7ec3e12 100644 --- a/boards/nxp/rddrone_fmuk66/rddrone_fmuk66.dts +++ b/boards/nxp/rddrone_fmuk66/rddrone_fmuk66.dts @@ -37,6 +37,7 @@ zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &lpuart0; zephyr,console = &lpuart0; zephyr,shell-uart = &lpuart0; zephyr,uart-pipe = &lpuart0; @@ -236,23 +237,23 @@ zephyr_udc0: &usbotg { boot_partition: partition@0 { label = "mcuboot"; - reg = <0x00000000 0x00010000>; + reg = <0x00000000 DT_SIZE_K(64)>; read-only; }; - /* Note slot 0 has one additional sector, - * this is intended for use with the swap move algorithm + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. */ slot0_partition: partition@10000 { label = "image-0"; - reg = <0x00010000 0x000E9000>; + reg = <0x00010000 (DT_SIZE_K(928) + DT_SIZE_K(8))>; }; - slot1_partition: partition@F9000 { + slot1_partition: partition@FA000 { label = "image-1"; - reg = <0x000F9000 0x000E8000>; + reg = <0x000FA000 DT_SIZE_K(928)>; }; - storage_partition: partition@1e1000 { + storage_partition: partition@1E2000 { label = "storage"; - reg = <0x001e1000 0x0001f000>; + reg = <0x001E2000 DT_SIZE_K(120)>; }; }; }; diff --git a/boards/nxp/s32z2xxdc2/Kconfig.defconfig b/boards/nxp/s32z2xxdc2/Kconfig.defconfig index f54f3ca4d13..2b5dffc8933 100644 --- a/boards/nxp/s32z2xxdc2/Kconfig.defconfig +++ b/boards/nxp/s32z2xxdc2/Kconfig.defconfig @@ -23,4 +23,11 @@ config SHELL_STACK_SIZE endif # SHELL +if NETWORKING + +config NET_L2_ETHERNET + default y if !NET_LOOPBACK && !NET_TEST + +endif # NETWORKING + endif # BOARD_S32Z2XXDC2_S32Z270_RTU0 || BOARD_S32Z2XXDC2_S32Z270_RTU1 diff --git a/boards/nxp/s32z2xxdc2/doc/index.rst b/boards/nxp/s32z2xxdc2/doc/index.rst index 18660e2fee5..d864059de00 100644 --- a/boards/nxp/s32z2xxdc2/doc/index.rst +++ b/boards/nxp/s32z2xxdc2/doc/index.rst @@ -53,6 +53,12 @@ The boards support the following hardware features: +-----------+------------+-------------------------------------+ | CANEXCEL | on-chip | can | +-----------+------------+-------------------------------------+ +| FLEXCAN | on-chip | can | ++-----------+------------+-------------------------------------+ +| SAR_ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| LPI2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ Other hardware features are not currently supported by the port. @@ -106,13 +112,13 @@ board. System Clock ============ -The Cortex-R52 cores are configured to run at 800 MHz. +The Cortex-R52 cores are configured to run at 1 GHz. Serial Port =========== The SoC has 12 LINFlexD instances that can be used in UART mode. The console can -be accessed by default on the USB micro-B connector `J119`. +be accessed by default on the USB micro-B connector J119. Watchdog ======== @@ -126,18 +132,36 @@ Ethernet NETC driver supports to manage the Physical Station Interface (PSI0) and/or a single Virtual SI (VSI). The rest of the VSI's shall be assigned to different -cores of the system. Refer to :ref:`nxp_s32_netc-samples` to learn how to +cores of the system. Refer to :zephyr:code-sample:`nxp_s32_netc` to learn how to configure the Ethernet network controller. -Controller Area Network (CAN) -============================= +Controller Area Network +======================= + +CANEXCEL +-------- + +CANEXCEL supports CAN Classic (CAN 2.0) and CAN FD modes. Remote transmission +request is not supported. -Currently, the CANXL transceiver is not populated in this board. So CAN transceiver -connection is required for running external traffic. We can use any CAN transceiver, -which supports CAN 2.0 and CAN FD protocol. +Note that this board does not currently come with CAN transceivers installed for +the CANEXCEL ports. To facilitate external traffic, you will need to add a CAN +transceiver. Any transceiver pin-compatible with CAN 2.0 and CAN FD protocols +can be used. -CAN driver supports classic (CAN 2.0) and CAN FD mode. Remote transmission request is -not supported as this feature is not available on NXP S32 CANXL HAL. +FlexCAN +------- + +FlexCAN supports CAN Classic (CAN 2.0) and CAN FD modes. + +ADC +=== + +ADC is provided through ADC SAR controller with 2 instances. Each ADC SAR instance has +12-bit resolution. ADC channels are divided into 2 groups (precision and internal/standard). + +.. note:: + All channels of an instance only run on 1 group channel at the same time. Programming and Debugging ************************* @@ -176,7 +200,7 @@ under Linux, ``/dev/ttyUSB0``. Debugging ========= -You can build and debug the :ref:`hello_world` sample for the board +You can build and debug the :zephyr:code-sample:`hello_world` sample for the board ``s32z2xxdc2/s32z270/rtu0`` with: .. zephyr-app-commands:: @@ -272,7 +296,7 @@ Where: - ```` is the zero-based core index relative to the RTU on which to run the Zephyr application (0, 1, 2 or 3) -For example, to build the :ref:`hello_world` sample for the board +For example, to build the :zephyr:code-sample:`hello_world` sample for the board ``s32z2xxdc2/s32z270/rtu0`` with split-lock core configuration: .. zephyr-app-commands:: diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270.dtsi b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270.dtsi index 1270676c77a..65f04794ce3 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270.dtsi +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270.dtsi @@ -31,13 +31,30 @@ status = "okay"; }; -&can0 { - pinctrl-0 = <&can0_default>; +&canxl0 { + pinctrl-0 = <&canxl0_default>; + pinctrl-names = "default"; +}; + +&canxl1 { + pinctrl-0 = <&canxl1_default>; pinctrl-names = "default"; - status = "okay"; }; -&can1 { - pinctrl-0 = <&can1_default>; +&flexcan0 { + pinctrl-0 = <&flexcan0_default>; pinctrl-names = "default"; }; + +&flexcan1 { + pinctrl-0 = <&flexcan1_default>; + pinctrl-names = "default"; +}; + +&sar_adc0 { + vref-mv = <1800>; +}; + +&sar_adc1 { + vref-mv = <1800>; +}; diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_pinctrl.dtsi b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_pinctrl.dtsi index 482b43d4b72..05b92b08931 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_pinctrl.dtsi +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_pinctrl.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2022-2023 NXP + * Copyright 2022-2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -64,7 +64,7 @@ }; }; - can0_default: can0_default { + canxl0_default: canxl0_default { group1 { pinmux = ; input-enable; @@ -75,7 +75,7 @@ }; }; - can1_default: can1_default { + canxl1_default: canxl1_default { group1 { pinmux = ; input-enable; @@ -85,4 +85,46 @@ output-enable; }; }; + + flexcan0_default: flexcan0_default { + group1 { + pinmux = ; + input-enable; + }; + group2 { + pinmux = ; + output-enable; + }; + }; + + flexcan1_default: flexcan1_default { + group1 { + pinmux = ; + input-enable; + }; + group2 { + pinmux = ; + output-enable; + }; + }; + + i2c1_default: i2c1_default { + group1 { + pinmux = <(PC15_I2C_1_SDA_I | PC15_I2C_1_SDA_O)>, + <(PD0_I2C_1_SCL_I | PD0_I2C_1_SCL_O)>; + input-enable; + output-enable; + drive-open-drain; + }; + }; + + i2c2_default: i2c2_default { + group1 { + pinmux = <(PJ11_I2C_2_SDA_I | PJ11_I2C_2_SDA_O)>, + <(PJ10_I2C_2_SCL_I | PJ10_I2C_2_SCL_O)>; + input-enable; + output-enable; + drive-open-drain; + }; + }; }; diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts index 37c2f6b74ff..3db4df08388 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts @@ -14,7 +14,7 @@ chosen { zephyr,sram = &sram0; - zephyr,canbus = &can0; + zephyr,canbus = &canxl0; }; aliases { @@ -31,3 +31,7 @@ mboxes = <&mru0 0>; mbox-names = "rx"; }; + +&canxl0 { + status = "okay"; +}; diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml index 9bbb05c6414..1ec2dc27de4 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml @@ -16,4 +16,6 @@ supported: - can - spi - counter + - adc + - i2c vendor: nxp diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml index 75d0455ee59..329e11384c7 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml @@ -16,4 +16,6 @@ supported: - can - spi - counter + - adc + - i2c vendor: nxp diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts index ce5d16260ab..4aadfbebb1d 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts @@ -16,7 +16,7 @@ zephyr,sram = &sram1; zephyr,console = &uart0; zephyr,shell-uart = &uart0; - zephyr,canbus = &can0; + zephyr,canbus = &flexcan0; }; aliases { @@ -33,3 +33,7 @@ mboxes = <&mru4 0>; mbox-names = "rx"; }; + +&flexcan0 { + status = "okay"; +}; diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml index 77a57961550..ff384e953be 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml @@ -16,4 +16,6 @@ supported: - can - spi - counter + - adc + - i2c vendor: nxp diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml index 1d99009466c..1165ca80194 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml @@ -16,4 +16,6 @@ supported: - can - spi - counter + - adc + - i2c vendor: nxp diff --git a/boards/nxp/twr_ke18f/doc/index.rst b/boards/nxp/twr_ke18f/doc/index.rst index a72227beb67..4d91e6e3352 100644 --- a/boards/nxp/twr_ke18f/doc/index.rst +++ b/boards/nxp/twr_ke18f/doc/index.rst @@ -193,7 +193,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -211,7 +211,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/twr_ke18f/twr_ke18f.dts b/boards/nxp/twr_ke18f/twr_ke18f.dts index e0f3e1d242c..a3cfd3d54dc 100644 --- a/boards/nxp/twr_ke18f/twr_ke18f.dts +++ b/boards/nxp/twr_ke18f/twr_ke18f.dts @@ -47,6 +47,7 @@ zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &lpuart0; zephyr,console = &lpuart0; zephyr,shell-uart = &lpuart0; zephyr,uart-pipe = &lpuart0; @@ -283,6 +284,7 @@ &adc0 { status = "okay"; sample-time = <12>; + vref-mv = <3300>; pinctrl-0 = <&adc0_default>; pinctrl-names = "default"; }; @@ -335,25 +337,25 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - boot_partition: partition@0 { label = "mcuboot"; - reg = <0x00000000 0xc000>; + reg = <0x00000000 DT_SIZE_K(64)>; + read-only; }; - /* Note slot 0 has one additional sector, - * this is intended for use with the swap move algorithm + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. */ - slot0_partition: partition@c000 { + slot0_partition: partition@10000 { label = "image-0"; - reg = <0x0000c000 0x37000>; + reg = <0x00010000 (DT_SIZE_K(200) + DT_SIZE_K(8))>; }; - slot1_partition: partition@43000 { + slot1_partition: partition@44000 { label = "image-1"; - reg = <0x00043000 0x36000>; + reg = <0x00044000 DT_SIZE_K(200)>; }; - storage_partition: partition@79000 { + storage_partition: partition@76000 { label = "storage"; - reg = <0x00079000 0x00007000>; + reg = <0x00076000 DT_SIZE_K(40)>; }; }; }; diff --git a/boards/nxp/twr_kv58f220m/doc/index.rst b/boards/nxp/twr_kv58f220m/doc/index.rst index 98cc3a880af..f9adc60064a 100644 --- a/boards/nxp/twr_kv58f220m/doc/index.rst +++ b/boards/nxp/twr_kv58f220m/doc/index.rst @@ -148,7 +148,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -166,7 +166,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/twr_kv58f220m/twr_kv58f220m.dts b/boards/nxp/twr_kv58f220m/twr_kv58f220m.dts index f79c840942c..f42607c334f 100644 --- a/boards/nxp/twr_kv58f220m/twr_kv58f220m.dts +++ b/boards/nxp/twr_kv58f220m/twr_kv58f220m.dts @@ -31,6 +31,7 @@ zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &uart0; zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,uart-pipe = &uart0; @@ -113,25 +114,25 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - boot_partition: partition@0 { label = "mcuboot"; - reg = <0x00000000 0x10000>; + reg = <0x00000000 DT_SIZE_K(64)>; + read-only; }; - /* Note slot 0 has one additional sector, - * this is intended for use with the swap move algorithm + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. */ slot0_partition: partition@10000 { label = "image-0"; - reg = <0x00010000 0x68000>; + reg = <0x00010000 (DT_SIZE_K(416) + DT_SIZE_K(16))>; }; - slot1_partition: partition@78000 { + slot1_partition: partition@7C000 { label = "image-1"; - reg = <0x00078000 0x66000>; + reg = <0x0007C000 DT_SIZE_K(416)>; }; - storage_partition: partition@de000 { - label = "image-scratch"; - reg = <0x000de000 0x22000>; + storage_partition: partition@E4000 { + label = "storage"; + reg = <0x000E4000 DT_SIZE_K(112)>; }; }; }; diff --git a/boards/nxp/ucans32k1sic/doc/index.rst b/boards/nxp/ucans32k1sic/doc/index.rst index 969d67e815a..3eca2900922 100644 --- a/boards/nxp/ucans32k1sic/doc/index.rst +++ b/boards/nxp/ucans32k1sic/doc/index.rst @@ -53,6 +53,7 @@ FTM on-chip pwm FlexCAN on-chip can Watchdog on-chip watchdog RTC on-chip counter +ADC on-chip adc ============ ========== ================================ The default configuration can be found in the Kconfig file diff --git a/boards/nxp/ucans32k1sic/ucans32k1sic.dts b/boards/nxp/ucans32k1sic/ucans32k1sic.dts index 77b95236343..4c1fdeb0732 100644 --- a/boards/nxp/ucans32k1sic/ucans32k1sic.dts +++ b/boards/nxp/ucans32k1sic/ucans32k1sic.dts @@ -98,6 +98,10 @@ }; }; +&cpu0 { + clock-frequency = <80000000>; +}; + &gpioa { status = "okay"; }; @@ -188,3 +192,15 @@ phys = <&can_phy1>; status = "okay"; }; + +&adc0 { + sample-time = <65>; + vref-mv = <3300>; + status = "okay"; +}; + +&adc1 { + sample-time = <65>; + vref-mv = <3300>; + status = "okay"; +}; diff --git a/boards/nxp/ucans32k1sic/ucans32k1sic.yaml b/boards/nxp/ucans32k1sic/ucans32k1sic.yaml index 798c1096409..4c7c80fdbde 100644 --- a/boards/nxp/ucans32k1sic/ucans32k1sic.yaml +++ b/boards/nxp/ucans32k1sic/ucans32k1sic.yaml @@ -21,3 +21,4 @@ supported: - can - watchdog - counter + - adc diff --git a/boards/nxp/ucans32k1sic/ucans32k1sic_defconfig b/boards/nxp/ucans32k1sic/ucans32k1sic_defconfig index e852568a799..6be7cd5f2a7 100644 --- a/boards/nxp/ucans32k1sic/ucans32k1sic_defconfig +++ b/boards/nxp/ucans32k1sic/ucans32k1sic_defconfig @@ -3,9 +3,6 @@ CONFIG_BUILD_OUTPUT_HEX=y -# Use Systick as system clock -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=80000000 - # Run from internal program flash CONFIG_XIP=y diff --git a/boards/nxp/usb_kw24d512/doc/index.rst b/boards/nxp/usb_kw24d512/doc/index.rst index b617edcf6d6..37bbb88726d 100644 --- a/boards/nxp/usb_kw24d512/doc/index.rst +++ b/boards/nxp/usb_kw24d512/doc/index.rst @@ -170,7 +170,7 @@ Once you have started a debug session, run telnet: Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -196,7 +196,7 @@ terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/usb_kw24d512/usb_kw24d512.dts b/boards/nxp/usb_kw24d512/usb_kw24d512.dts index 6b0dbdb6668..59e616a605e 100644 --- a/boards/nxp/usb_kw24d512/usb_kw24d512.dts +++ b/boards/nxp/usb_kw24d512/usb_kw24d512.dts @@ -106,7 +106,7 @@ zephyr_udc0: &usbd { label = "image-0"; reg = <0x00000000 0x00070000>; }; - storage_partition: partition@700000 { + storage_partition: partition@70000 { label = "storage"; reg = <0x00070000 0x00010000>; }; diff --git a/boards/nxp/vmu_rt1170/Kconfig.defconfig b/boards/nxp/vmu_rt1170/Kconfig.defconfig index f0f7bffa888..7c62ad7ecde 100644 --- a/boards/nxp/vmu_rt1170/Kconfig.defconfig +++ b/boards/nxp/vmu_rt1170/Kconfig.defconfig @@ -12,23 +12,11 @@ config IMX_USDHC_DAT3_PWR_TOGGLE endif # DISK_DRIVERS -if FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI - -choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET - default FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM if CPU_CORTEX_M7 - default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM if CPU_CORTEX_M4 -endchoice - -endif # FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI - if NETWORKING config NET_L2_ETHERNET default y if CPU_CORTEX_M7 # No cache memory support is required for driver -config ETH_MCUX_PHY_RESET - default n - config ETH_MCUX_RMII_EXT_CLK default y diff --git a/boards/nxp/vmu_rt1170/doc/index.rst b/boards/nxp/vmu_rt1170/doc/index.rst index a683fc8ad1e..4ad7bad0c17 100644 --- a/boards/nxp/vmu_rt1170/doc/index.rst +++ b/boards/nxp/vmu_rt1170/doc/index.rst @@ -61,11 +61,13 @@ Hardware - CAN bus JST-GH connectors +- RC IN + + - RC input connector for SBUS compatible RC receivers + For more information about the MIMXRT1176 SoC and VMU RT1170 board, see these references: -- `VMU RT1170 Website`_ -- `VMU RT1170 User Guide`_ - `VMU RT1170 Schematics`_ - `i.MX RT1170 Datasheet`_ - `i.MX RT1170 Reference Manual`_ @@ -94,7 +96,7 @@ following hardware features: +-----------+------------+-------------------------------------+ | I2C | on-chip | i2c | +-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | +| PWM | on-chip | flexpwm, qtmr | +-----------+------------+-------------------------------------+ | ADC | on-chip | adc | +-----------+------------+-------------------------------------+ @@ -125,7 +127,7 @@ following hardware features: +-----------+------------+-------------------------------------+ The default configuration can be found in -:zephyr_file:`boards/nxp/vmu_rt1170/vmu_rt1170_defconfig` +:zephyr_file:`boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm7_defconfig` Other hardware features are not currently supported by the port. @@ -134,71 +136,337 @@ Connections and I/Os The MIMXRT1170 SoC has six pairs of pinmux/gpio controllers. -+---------------------------+----------------+------------------+ -| Name | Function | Usage | -+---------------------------+----------------+------------------+ -| WAKEUP | GPIO | SW7 | -+---------------------------+----------------+------------------+ -| GPIO_AD_04 | GPIO | LED | -+---------------------------+----------------+------------------+ -| GPIO_AD_24 | LPUART1_TX | UART Console | -+---------------------------+----------------+------------------+ -| GPIO_AD_25 | LPUART1_RX | UART Console | -+---------------------------+----------------+------------------+ -| GPIO_LPSR_00 | CAN3_TX | flexcan | -+---------------------------+----------------+------------------+ -| GPIO_LPSR_01 | CAN3_RX | flexcan | -+---------------------------+----------------+------------------+ -| GPIO_AD_29 | SPI1_CS0 | spi | -+---------------------------+----------------+------------------+ -| GPIO_AD_28 | SPI1_CLK | spi | -+---------------------------+----------------+------------------+ -| GPIO_AD_30 | SPI1_SDO | spi | -+---------------------------+----------------+------------------+ -| GPIO_AD_31 | SPI1_SDI | spi | -+---------------------------+----------------+------------------+ -| GPIO_AD_08 | LPI2C1_SCL | i2c | -+---------------------------+----------------+------------------+ -| GPIO_AD_09 | LPI2C1_SDA | i2c | -+---------------------------+----------------+------------------+ -| GPIO_LPSR_05 | LPI2C5_SCL | i2c | -+---------------------------+----------------+------------------+ -| GPIO_LPSR_04 | LPI2C5_SDA | i2c | -+---------------------------+----------------+------------------+ -| GPIO_AD_04 | FLEXPWM1_PWM2 | pwm | -+---------------------------+----------------+------------------+ -| GPIO_AD_32 | ENET_MDC | Ethernet | -+---------------------------+----------------+------------------+ -| GPIO_AD_33 | ENET_MDIO | Ethernet | -+---------------------------+----------------+------------------+ -| GPIO_DISP_B2_02 | ENET_TX_DATA00 | Ethernet | -+---------------------------+----------------+------------------+ -| GPIO_DISP_B2_03 | ENET_TX_DATA01 | Ethernet | -+---------------------------+----------------+------------------+ -| GPIO_DISP_B2_04 | ENET_TX_EN | Ethernet | -+---------------------------+----------------+------------------+ -| GPIO_DISP_B2_05 | ENET_REF_CLK | Ethernet | -+---------------------------+----------------+------------------+ -| GPIO_DISP_B2_06 | ENET_RX_DATA00 | Ethernet | -+---------------------------+----------------+------------------+ -| GPIO_DISP_B2_07 | ENET_RX_DATA01 | Ethernet | -+---------------------------+----------------+------------------+ -| GPIO_DISP_B2_08 | ENET_RX_EN | Ethernet | -+---------------------------+----------------+------------------+ -| GPIO_DISP_B2_09 | ENET_RX_ER | Ethernet | -+---------------------------+----------------+------------------+ -| GPIO_AD_17_SAI1_MCLK | SAI_MCLK | SAI | -+---------------------------+----------------+------------------+ -| GPIO_AD_21_SAI1_TX_DATA00 | SAI1_TX_DATA | SAI | -+---------------------------+----------------+------------------+ -| GPIO_AD_22_SAI1_TX_BCLK | SAI1_TX_BCLK | SAI | -+---------------------------+----------------+------------------+ -| GPIO_AD_23_SAI1_TX_SYNC | SAI1_TX_SYNC | SAI | -+---------------------------+----------------+------------------+ -| GPIO_AD_17_SAI1_MCLK | SAI1_MCLK | SAI | -+---------------------------+----------------+------------------+ -| GPIO_AD_20_SAI1_RX_DATA00 | SAI1_RX_DATA00 | SAI | -+---------------------------+----------------+------------------+ ++-----------------+--------------------------------+----------------------------+ +| Name | Function | Usage | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_00 | FLEXCAN2_TX | CAN2_TX | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_01 | FLEXCAN2_RX | CAN2_RX | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_02 | LPUART8_TXD | UART8_TX_TELEM2 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_03 | LPUART8_RXD | UART8_RX_TELEM2 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_04 | LPUART8_CTS_B | UART8_CTS_TELEM2 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_05 | LPUART8_RTS_B | UART8_RTS_TELEM2 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_06 | FLEXCAN1_TX | CAN1_TX | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_07 | FLEXCAN1_RX | CAN1_RX | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_08 | LPI2C1_SCL | I2C1_SCL_GPS1 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_09 | LPI2C1_SDA | I2C1_SDA_GPS1 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_10 | LPADC1_CH2A | SCALED_VDD_3V3_SENSORS1 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_11 | LPADC1_CH2B | SCALED_VDD_3V3_SENSORS2 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_12 | LPADC1_CH3A | SCALED_VDD_3V3_SENSORS3 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_13 | LPADC1_CH3B | SCALED_V5 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_14 | LPADC1_CH4A | ADC_6V6 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_15 | LPUART10_TXD | UART10_TX_TELEM3 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_16 | LPADC1_CH5A | ADC_3V3 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_17 | LPADC1_CHB | SCALED_VDD_3V3_SENSORS4 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_18 | LPI2C2_SCL | I2C2_SCL_GPS2 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_19 | LPI2C2_SDA | I2C2_SDA_GPS2 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_20 | GPIO3_IO19 | SPI1_DRDY1_SENSOR1 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_21 | GPIO3_IO20 | SPI3_DRDY1_SENSOR3 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_22 | LPADC2_CH2A | HW_VER_SENSE | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_23 | LPADC2_CH2B | HW_REV_SENSE | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_24 | LPSPI2_SCK | SPI2_SCK_SENSOR2 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_25 | LPSPI2_PCS0 | SPI2_nCS0_SENSOR2 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_26 | LPSPI2_SOUT | SPI2_MOSI_SENSOR2 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_27 | LPSPI2_SIN | SPI2_MISO_SENSOR2 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_28 | LPUART5_TXD | UART5_TX_GPS2 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_29 | LPUART5_RXD | UART5_RX_GPS2 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_30 | LPUART3_TXD | UART3_TX_GPS1 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_31 | LPUART3_RXD | UART3_RX_GPS1 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_32 | USDHC1_CD_B | USDHC1_CD | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_33 | LPUART10_RXD | UART10_RX_TELEM3 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_34 | LPUART10_CTS_B | UART10_CTS_TELEM3 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_AD_35 | LPUART10_RTS_B | UART10_RTS_TELEM3 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_DISP_B1_00 | ENET_1G_RX_EN | ETH_CRS_DV | ++-----------------+--------------------------------+----------------------------+ +| GPIO_DISP_B1_01 | ENET_1G_RX_ER | ETH_RX_ER | ++-----------------+--------------------------------+----------------------------+ +| GPIO_DISP_B1_02 | LPUART1_TXD | UART1_TX_DEBUG | ++-----------------+--------------------------------+----------------------------+ +| GPIO_DISP_B1_03 | LPUART1_RXD | UART1_RX_DEBUG | ++-----------------+--------------------------------+----------------------------+ +| GPIO_DISP_B1_04 | LPUART4_RXD | UART4_RX_TELEM1 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_DISP_B1_05 | LPUART4_CTS_B | UART4_CTS_TELEM1 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_DISP_B1_06 | LPUART4_TXD | UART4_TX_TELEM1 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_DISP_B1_07 | LPUART4_RTS_B | UART4_RTS_TELEM1 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_DISP_B1_08 | ENET_1G_TDATA1 | ETH_TXD1 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_DISP_B1_09 | ENET_1G_TDATA0 | ETH_TXD0 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_DISP_B1_10 | ENET_1G_TX_EN | ETH_TX_EN | ++-----------------+--------------------------------+----------------------------+ +| GPIO_DISP_B1_11 | ENET_1G_REF_CLK | ETH_REF_CLK | ++-----------------+--------------------------------+----------------------------+ +| GPIO_DISP_B2_00 | GPIO5_IO01 | nLED_RED | ++-----------------+--------------------------------+----------------------------+ +| GPIO_DISP_B2_01 | GPIO5_IO02 | nLED_GREEN | ++-----------------+--------------------------------+----------------------------+ +| GPIO_DISP_B2_02 | ARM_TRACE0 | TRACED0 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_DISP_B2_03 | ARM_TRACE1 | TRACED1 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_DISP_B2_04 | ARM_TRACE2 | TRACED2 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_DISP_B2_05 | ARM_TRACE3 | TRACED3 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_DISP_B2_06 | ARM_TRACE_CLK | TRACECLK | ++-----------------+--------------------------------+----------------------------+ +| GPIO_DISP_B2_07 | ARM_TRACE_SWO | TRACESWO | ++-----------------+--------------------------------+----------------------------+ +| GPIO_DISP_B2_08 | GPIO5_IO09 | ETH_POWER_EN | ++-----------------+--------------------------------+----------------------------+ +| GPIO_DISP_B2_09 | GPIO5_IO10 | ETH_PHY_nINT | ++-----------------+--------------------------------+----------------------------+ +| GPIO_DISP_B2_10 | LPI2C3_SCL | I2C3_SCL_FMU | ++-----------------+--------------------------------+----------------------------+ +| GPIO_DISP_B2_11 | LPI2C3_SDA | I2C3_SDA_FMU | ++-----------------+--------------------------------+----------------------------+ +| GPIO_DISP_B2_12 | LPSPI4_SCK | SPI4_SCK_SENSOR4 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_DISP_B2_13 | LPSPI4_SIN | SPI4_MISO_SENSOR4 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_DISP_B2_14 | LPSPI4_SOUT | SPI4_MOSI_SENSOR4 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_DISP_B2_15 | LPSPI4_PCS0 | SPI4_nCS0_SENSOR4 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_00 | FLEXPWM4_PWM0_A + FLEXIO1_IO00 | FMU_CH11 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_01 | GPIO1_IO01 | VDD_3V3_SD_CARD_EN | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_02 | FLEXPWM4_PWM1_A + FLEXIO1_IO02 | FMU_CH12 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_03 | GPIO1_IO03 | FMU_nSAFETY_SWITCH_LED_OUT | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_04 | GPIO1_IO04 | NFC_GPIO | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_05 | GPIO1_IO05 | SPI6_DRDY1_EXTERNAL1 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_06 | FLEXPWM2_PWM0_A + FLEXIO1_IO06 | FMU_CH4 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_07 | GPIO1_IO07 | SPI6_DRDY2_EXTERNAL1 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_08 | FLEXPWM2_PWM1_A + FLEXIO1_IO08 | FMU_CH5 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_09 | GPT5_CAPTURE1 | FMU_PPM_INPUT | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_10 | FLEXPWM2_PWM2_A + FLEXIO1_IO10 | FMU_CH6 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_11 | GPIO1_IO11 | SPI6_nRESET_EXTERNAL1 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_12 | GPIO1_IO12 | VDD_5V_HIPOWER_nOC | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_13 | GPIO1_IO13 | nLED_BLUE | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_14 | GPIO1_IO14 | VDD_3V3_SENSORS3_EN | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_15 | GPIO1_IO15 | VDD_5V_PERIPH_nOC | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_16 | GPIO1_IO16 | SPI4_DRDY1_SENSOR4 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_17 | GPIO1_IO17 | nARMED | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_18 | TMR2_TIMER0 | SPIX_SYNC | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_19 | FLEXPWM2_PWM3_A + FLEXIO1_IO19 | FMU_CH7 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_20 | TMR4_TIMER0 | FMU_CAP1 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_21 | FLEXPWM3_PWM3_A + FLEXIO1_IO21 | FMU_CH10 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_22 | GPIO1_IO22 | VDD_3V3_SENSORS2_EN | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_23 | FLEXPWM1_PWM0_A | FMU_CH1 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_24 | GPIO1_IO24 | FMU_SAFETY_SWITCH_IN | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_25 | FLEXPWM1_PWM1_A + FLEXIO1_IO25 | FMU_CH2 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_26 | GPIO1_IO26 | HW_VER_REV_DRIVE | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_27 | FLEXPWM1_PWM2_A + FLEXIO1_IO27 | FMU_CH3 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_28 | GPIO1_IO28 | nPOWER_IN_A | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_29 | FLEXPWM3_PWM0_A + FLEXIO1_IO29 | FMU_CH8 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_30 | GPIO1_IO30 | nPOWER_IN_B | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_31 | FLEXPWM3_PWM1_A + FLEXIO1_IO31 | FMU_CH9 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_32 | GPIO2_IO00 | nPOWER_IN_C | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_33 | GPIO2_IO01 | VDD_3V3_SENSORS1_EN | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_34 | GPIO2_IO02 | VDD_5V_PERIPH_nEN | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_35 | GPIO2_IO03 | I2C2_DRDY1 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_36 | GPIO2_IO04 | VDD_3V3_SENSORS4_EN | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_37 | GPIO2_IO05 | VDD_5V_HIPOWER_nEN | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_38 | GPIO2_IO06 | VDD_3V3_SPEKTRUM_POWER_EN | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_39 | GPIO2_IO07 | SPI2_DRDY1_SENSOR2 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_40 | LPUART6_TXD | UART6_TX_TO_IO__RC_INPUT | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B1_41 | LPUART6_RXD | UART6_RX_FROM_IO__NC | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B2_00 | LPSPI1_SCK | SPI1_SCK_SENSOR1 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B2_01 | LPSPI1_PCS0 | SPI1_nCS0_SENSOR1 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B2_02 | LPSPI1_SOUT | SPI1_MOSI_SENSOR1 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B2_03 | LPSPI1_SIN | SPI1_MISO_SENSOR1 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B2_04 | LPSPI3_SCK | SPI3_SCK_SENSOR3 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B2_05 | LPSPI3_PCS0 | SPI3_nCS0_SENSOR3 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B2_06 | LPSPI3_SOUT | SPI3_MOSI_SENSOR3 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B2_07 | LPSPI3_SIN | SPI3_MISO_SENSOR3 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B2_08 | LPSPI3_PCS1 | SPI3_nCS1_SENSOR3 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B2_09 | TMR1_TIMER0 | BUZZER_1 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B2_10 | FLEXSPI2_A_SCLK | FLEXSPI2_SCK_FRAM | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B2_11 | FLEXSPI2_A_SS0_B | FLEXSPI2_nCS0_FRAM | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B2_12 | GPIO2_IO22 | GPIO_EMC_B2_12 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B2_13 | FLEXSPI2_A_DATA0 | FLEXSPI2_DATA0_FRAM | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B2_14 | FLEXSPI2_A_DATA1 | FLEXSPI2_DATA1_FRAM | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B2_15 | ENET_1G_RDATA0 | ETH_RXD0 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B2_16 | ENET_1G_RDATA1 | ETH_RXD1 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B2_17 | TMR3_TIMER0 | HEATER | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B2_18 | GPIO2_IO28 | SPI3_DRDY2_SENSOR3 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B2_19 | ENET_1G_MDC | ETH_MDC | ++-----------------+--------------------------------+----------------------------+ +| GPIO_EMC_B2_20 | ENET_1G_MDIO | ETH_MDIO | ++-----------------+--------------------------------+----------------------------+ +| GPIO_LPSR_00 | FLEXCAN3_TX | CAN3_TX | ++-----------------+--------------------------------+----------------------------+ +| GPIO_LPSR_01 | FLEXCAN3_RX | CAN3_RX | ++-----------------+--------------------------------+----------------------------+ +| GPIO_LPSR_02 | SRC_BOOT_MODE00 | BT_MODE0 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_LPSR_03 | SRC_BOOT_MODE01 | BT_MODE1 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_LPSR_04 | LPUART11_TXD | UART11_TX_EXTERNAL2 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_LPSR_05 | LPUART11_RXD | UART11_RX_EXTERNAL2 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_LPSR_06 | LPI2C6_SDA | I2C6_SDA_EXTERNAL2 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_LPSR_07 | LPI2C6_SCL | I2C6_SCL_EXTERNAL2 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_LPSR_08 | LPSPI6_PCS1 | SPI6_nCS1_EXTERNAL1 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_LPSR_09 | LPSPI6_PCS0 | SPI6_nCS0 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_LPSR_10 | LPSPI6_SCK | SPI6_SCK_EXTERNAL1 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_LPSR_11 | LPSPI6_SOUT | SPI6_MOSI_EXTERNAL1 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_LPSR_12 | LPSPI6_SIN | SPI6_MISO_EXTERNAL1 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_LPSR_13 | JTAG_MOD | NC_JTAG_MOD_PD | ++-----------------+--------------------------------+----------------------------+ +| GPIO_LPSR_14 | SWD_CLK | FMU_SWCLK | ++-----------------+--------------------------------+----------------------------+ +| GPIO_LPSR_15 | SWD_DIO | FMU_SWDIO | ++-----------------+--------------------------------+----------------------------+ +| GPIO_SD_B1_00 | USDHC1_CMD | USDHC1_CMD | ++-----------------+--------------------------------+----------------------------+ +| GPIO_SD_B1_01 | USDHC1_CLK | USDHC1_CLK | ++-----------------+--------------------------------+----------------------------+ +| GPIO_SD_B1_02 | USDHC1_DATA0 | USDHC1_DATA0 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_SD_B1_03 | USDHC1_DATA1 | USDHC1_DATA1 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_SD_B1_04 | USDHC1_DATA2 | USDHC1_DATA2 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_SD_B1_05 | USDHC1_DATA3 | USDHC1_DATA3 | ++-----------------+--------------------------------+----------------------------+ +| GPIO_SD_B2_00 | FLEXSPI1_B_DATA3 | FLEXSPI1_DATA7_HYPERFLASH | ++-----------------+--------------------------------+----------------------------+ +| GPIO_SD_B2_01 | FLEXSPI1_B_DATA2 | FLEXSPI1_DATA6_HYPERFLASH | ++-----------------+--------------------------------+----------------------------+ +| GPIO_SD_B2_02 | FLEXSPI1_B_DATA1 | FLEXSPI1_DATA5_HYPERFLASH | ++-----------------+--------------------------------+----------------------------+ +| GPIO_SD_B2_03 | FLEXSPI1_B_DATA0 | FLEXSPI1_DATA4_HYPERFLASH | ++-----------------+--------------------------------+----------------------------+ +| GPIO_SD_B2_04 | FLEXSPI1_B_SCLK | FLEXSPI1_nSCK_HYPERFLASH | ++-----------------+--------------------------------+----------------------------+ +| GPIO_SD_B2_05 | FLEXSPI1_A_DQS | FLEXSPI1_DQS_HYPERFLASH | ++-----------------+--------------------------------+----------------------------+ +| GPIO_SD_B2_06 | FLEXSPI1_A_SS0_B | FLEXSPI1_nCS0_HYPERFLASH | ++-----------------+--------------------------------+----------------------------+ +| GPIO_SD_B2_07 | FLEXSPI1_A_SCLK | FLEXSPI1_SCK_HYPERFLASH | ++-----------------+--------------------------------+----------------------------+ +| GPIO_SD_B2_08 | FLEXSPI1_A_DATA0 | FLEXSPI1_DATA0_HYPERFLASH | ++-----------------+--------------------------------+----------------------------+ +| GPIO_SD_B2_09 | FLEXSPI1_A_DATA0 | FLEXSPI1_DATA1_HYPERFLASH | ++-----------------+--------------------------------+----------------------------+ +| GPIO_SD_B2_10 | FLEXSPI1_A_DATA2 | FLEXSPI1_DATA2_HYPERFLASH | ++-----------------+--------------------------------+----------------------------+ +| GPIO_SD_B2_11 | FLEXSPI1_A_DATA3 | FLEXSPI1_DATA3_HYPERFLASH | ++-----------------+--------------------------------+----------------------------+ +| USB1_DN | USB_OG1_DN | USB_D_N | ++-----------------+--------------------------------+----------------------------+ +| USB1_DP | USB_OTG1_DP | USB_D_P | ++-----------------+--------------------------------+----------------------------+ +| USB1_VBUS | USB_OTG1_VBUS | VBUS | ++-----------------+--------------------------------+----------------------------+ Serial Port =========== @@ -239,7 +507,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -256,7 +524,7 @@ You should see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -271,12 +539,6 @@ should see the following message in the terminal: ***** Booting Zephyr OS v3.4.0-xxxx-xxxxxxxxxxxxx ***** Hello World! vmu_rt1170 -.. _VMU RT1170 Website: - https://www.nxp.com/part/VMU-RT1170 - -.. _VMU RT1170 User Guide: - https://cognipilot.org/cerebri/boards/nxp_vmu_rt1170/ - .. _VMU RT1170 Schematics: https://github.com/CogniPilot/NXP-VMU_RT117x-HW diff --git a/boards/nxp/vmu_rt1170/flexspi_nor_config.c b/boards/nxp/vmu_rt1170/flexspi_nor_config.c index 85ad476cf84..7a59acd6c54 100644 --- a/boards/nxp/vmu_rt1170/flexspi_nor_config.c +++ b/boards/nxp/vmu_rt1170/flexspi_nor_config.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2019, MADMACHINE LIMITED + * Copyright 2024 NXP * * refer to hal_nxp board file * @@ -101,7 +102,7 @@ const struct flexspi_nor_config_t g_flash_fast_config = { [0 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xEE, CMD_DDR, FLEXSPI_8PAD, 0x11), [0 + 1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, - 0x20, DUMMY_DDR, FLEXSPI_8PAD, 0x04), + 0x20, DUMMY_DDR, FLEXSPI_8PAD, 0x28), [0 + 2] = FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x00), diff --git a/boards/nxp/vmu_rt1170/vmu_rt1170-pinctrl.dtsi b/boards/nxp/vmu_rt1170/vmu_rt1170-pinctrl.dtsi index e7ab7ce896b..e6d00911b13 100644 --- a/boards/nxp/vmu_rt1170/vmu_rt1170-pinctrl.dtsi +++ b/boards/nxp/vmu_rt1170/vmu_rt1170-pinctrl.dtsi @@ -3,16 +3,15 @@ * SPDX-License-Identifier: Apache-2.0 * * Note: File generated by gen_board_pinctrl.py - * from vmu_rt1170.mex + * from vmu_rt1170.mex, then updated manually */ #include &pinctrl { - pinmux_enet: pinmux_enet { + pinmux_enet1g: pinmux_enet1g { group0 { - pinmux = <&iomuxc_gpio_disp_b2_09_gpio_mux5_io10>, - <&iomuxc_gpio_disp_b1_00_enet_1g_rx_en>, + pinmux = <&iomuxc_gpio_disp_b1_00_enet_1g_rx_en>, <&iomuxc_gpio_disp_b1_01_enet_1g_rx_er>; drive-strength = "high"; bias-pull-down; @@ -27,9 +26,7 @@ input-enable; }; group2 { - pinmux = <&iomuxc_gpio_emc_b2_19_enet_1g_mdc>, - <&iomuxc_gpio_emc_b2_20_enet_1g_mdio>, - <&iomuxc_gpio_disp_b1_09_enet_1g_tdata00>, + pinmux = <&iomuxc_gpio_disp_b1_09_enet_1g_tdata00>, <&iomuxc_gpio_disp_b1_08_enet_1g_tdata01>, <&iomuxc_gpio_disp_b1_10_enet_1g_tx_en>; drive-strength = "high"; @@ -44,6 +41,24 @@ }; }; + pinmux_enet1g_mdio: pinmux_enet1g_mdio { + group0 { + pinmux = <&iomuxc_gpio_emc_b2_19_enet_1g_mdc>, + <&iomuxc_gpio_emc_b2_20_enet_1g_mdio>; + drive-strength = "high"; + slew-rate = "fast"; + }; + group1 { + pinmux = <&iomuxc_gpio_disp_b2_09_gpio_mux5_io10>; + drive-strength = "high"; + bias-pull-down; + slew-rate = "fast"; + }; + }; + + pinmux_enet1g_ptp: pinmux_enet1g_ptp { + }; + pinmux_flexcan1: pinmux_flexcan1 { group0 { pinmux = <&iomuxc_gpio_ad_07_can1_rx>, @@ -156,6 +171,14 @@ }; }; + pinmux_qtmr_pwm_buzzer: pinmux_qtmr_pwm_buzzer { + group0 { + pinmux = <&iomuxc_gpio_emc_b2_09_qtimer1_timer0>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + pinmux_lpadc1: pinmux_lpadc1 { group0 { pinmux = <&iomuxc_gpio_ad_10_adc1_ch2a>; diff --git a/boards/nxp/vmu_rt1170/vmu_rt1170.dtsi b/boards/nxp/vmu_rt1170/vmu_rt1170.dtsi index 075dc1860dc..43dcb4b1d33 100644 --- a/boards/nxp/vmu_rt1170/vmu_rt1170.dtsi +++ b/boards/nxp/vmu_rt1170/vmu_rt1170.dtsi @@ -5,6 +5,7 @@ */ #include "vmu_rt1170-pinctrl.dtsi" +#include / { aliases { @@ -97,8 +98,26 @@ status = "okay"; }; -&enet1g { - pinctrl-0 = <&pinmux_enet>; +&enet1g_mac { + pinctrl-0 = <&pinmux_enet1g>; + pinctrl-names = "default"; + phy-handle = <&enet1g_phy>; + phy-connection-type = "rmii"; + zephyr,random-mac-address; +}; + +&enet1g_mdio { + pinctrl-0 = <&pinmux_enet1g_mdio>; + pinctrl-names = "default"; + enet1g_phy: phy@1 { + compatible = "nxp,tja1103"; + reg = <1>; + master-slave = "master"; + }; +}; + +&enet1g_ptp_clock { + pinctrl-0 = <&pinmux_enet1g_ptp>; pinctrl-names = "default"; }; @@ -177,7 +196,7 @@ ahb-prefetch; ahb-read-addr-opt; rx-clock-source = <1>; - reg = <0x400cc000 0x4000>, <0x30000000 DT_SIZE_M(16)>; + reg = <0x400cc000 0x4000>, <0x30000000 DT_SIZE_M(64)>; mx25um51345g: mx25um51345g@0 { compatible = "nxp,imx-flexspi-mx25um51345g"; /* MX25UM51245G is 64MB, 512MBit flash part */ @@ -187,28 +206,30 @@ status = "okay"; jedec-id = [c2 81 3a]; erase-block-size = <4096>; - write-block-size = <16>; + write-block-size = <2>; /* FLASH_MCUX_FLEXSPI_MX25UM51345G_OPI_DTR set */ partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; + /* The MCUBoot swap-move algorithm uses the last 3 sectors + * of the primary slot0 for swap status and move. + */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 DT_SIZE_K(3076)>; + reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(3 * 4))>; }; - slot1_partition: partition@321000 { + slot1_partition: partition@32E000 { label = "image-1"; - reg = <0x00321000 DT_SIZE_K(3072)>; + reg = <0x0032E000 DT_SIZE_M(3)>; }; - storage_partition: partition@621000 { + storage_partition: partition@62E000 { label = "storage"; - reg = <0x00621000 DT_SIZE_M(57)>; + reg = <0x0062E000 (DT_SIZE_M(58) - DT_SIZE_K(140))>; }; }; }; diff --git a/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm7.dts b/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm7.dts index c2ea2f47496..b6011a38098 100644 --- a/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm7.dts +++ b/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm7.dts @@ -21,6 +21,7 @@ watchdog0 = &wdog1; sdhc0 = &usdhc1; sw0 = &arming_button; + pwm-led0 = &buzzer0; }; chosen { @@ -34,6 +35,7 @@ zephyr,flash-controller = &mx25um51345g; zephyr,flash = &mx25um51345g; zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &lpuart1; }; /* This is the Arming Button on the included GPS module for 10 pin JST-GH */ @@ -121,6 +123,13 @@ regulator-always-on; status = "okay"; }; + + pwm_shell: pwm_shell { + compatible = "pwm-leds"; + buzzer0: buzzer0 { + pwms = <&qtmr1 0 PWM_HZ(50) PWM_POLARITY_NORMAL>; + }; + }; }; @@ -170,6 +179,41 @@ current-speed = <115200>; }; +&lpuart6 { + status = "okay"; + single-wire; + rx-invert; + + sbus { + compatible = "futaba,sbus"; + right_stick_x { + channel = <1>; + type = ; + zephyr,code = ; + }; + right_stick_y { + channel = <2>; + type = ; + zephyr,code = ; + }; + left_stick_y { + channel = <3>; + type = ; + zephyr,code = ; + }; + left_stick_x { + channel = <4>; + type = ; + zephyr,code = ; + }; + kill_switch { + channel = <5>; + type = ; + zephyr,code = ; + }; + }; +}; + &flexcan1 { status = "okay"; @@ -198,6 +242,8 @@ }; }; +#include + &lpspi1 { status = "okay"; cs-gpios =<&gpio2 11 GPIO_ACTIVE_LOW>; @@ -207,10 +253,12 @@ reg = <0>; int-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; spi-max-frequency = <24000000>; - accel-hz = <1000>; - accel-fs = <16>; - gyro-hz = <1000>; - gyro-fs = <2000>; + accel-pwr-mode = ; + accel-odr = ; + accel-fs = ; + gyro-pwr-mode = ; + gyro-odr = ; + gyro-fs = ; }; }; @@ -223,10 +271,12 @@ reg = <0>; int-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; spi-max-frequency = <24000000>; - accel-hz = <1000>; - accel-fs = <16>; - gyro-hz = <1000>; - gyro-fs = <2000>; + accel-pwr-mode = ; + accel-odr = ; + accel-fs = ; + gyro-pwr-mode = ; + gyro-odr = ; + gyro-fs = ; }; }; @@ -392,6 +442,15 @@ capture-channel = <1>; }; +&qtmr1 { + compatible = "nxp,qtmr-pwm"; + pinctrl-0 = <&pinmux_qtmr_pwm_buzzer>; + pinctrl-names = "default"; + #pwm-cells = <3>; + prescaler = <128>; + status = "okay"; +}; + &usdhc1 { status = "okay"; no-1-8-v; @@ -429,7 +488,18 @@ &enet1g { status = "okay"; - int-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>; +}; + +&enet1g_mac { + status = "okay"; +}; + +&enet1g_mdio { + status = "okay"; + enet1g_phy: phy@1 { + status = "okay"; + int-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>; + }; }; zephyr_udc0: &usb1 { diff --git a/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_defconfig b/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_defconfig index 0d6dc9f80d3..8b09bb0775d 100644 --- a/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_defconfig +++ b/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_defconfig @@ -4,9 +4,6 @@ CONFIG_SERIAL=y # enable GPIO CONFIG_GPIO=y -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - # console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y @@ -16,6 +13,3 @@ CONFIG_ARM_MPU=y # Enable HW stack protection CONFIG_HW_STACK_PROTECTION=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/olimex/olimex_esp32_evb/doc/index.rst b/boards/olimex/olimex_esp32_evb/doc/index.rst index bcfc8a3c346..5af913a1273 100644 --- a/boards/olimex/olimex_esp32_evb/doc/index.rst +++ b/boards/olimex/olimex_esp32_evb/doc/index.rst @@ -84,9 +84,9 @@ features: +-----------+------------+-------------------------------------+ The default configuration can be found in -:zephyr_file:`boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_appcpu_defconfig` +:zephyr_file:`boards/olimex/olimex_esp32_evb/olimex_esp32_evb_appcpu_defconfig` and -:zephyr_file:`boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_procpu_defconfig` +:zephyr_file:`boards/olimex/olimex_esp32_evb/olimex_esp32_evb_procpu_defconfig` Other hardware features are not currently supported by the port. @@ -125,7 +125,7 @@ MCUboot bootloader ================== User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. +must be built (and flashed) at least once. There are two options to be used when building an application: @@ -136,9 +136,10 @@ There are two options to be used when building an application: User can select the MCUboot bootloader by adding the following line to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y Sysbuild ======== @@ -150,7 +151,7 @@ To build the sample application using sysbuild use the command: .. zephyr-app-commands:: :tool: west - :app: samples/hello_world + :zephyr-app: samples/hello_world :board: olimex_esp32_evb :goals: build :west-args: --sysbuild @@ -186,7 +187,7 @@ Manual build ============ During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. +For that reason, images can be built one at a time using traditional build. The instructions following are relevant for both manual build and sysbuild. The only difference is the structure of the build directory. @@ -204,7 +205,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``olimex_esp32_evb`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -231,13 +232,13 @@ Debugging As with much custom hardware, the ESP32 modules require patches to OpenOCD that are not upstreamed yet. Espressif maintains their own fork of -the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_. The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the ``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` parameter when building. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -245,7 +246,7 @@ Here is an example for building the :ref:`hello_world` application. :goals: build flash :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_appcpu.dts b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_appcpu.dts index c52b029ea55..ae7a2e1e7f6 100644 --- a/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_appcpu.dts +++ b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_appcpu.dts @@ -18,14 +18,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &ipm0 { status = "okay"; }; diff --git a/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_procpu.dts b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_procpu.dts index f731d277684..c239263ea53 100644 --- a/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_procpu.dts +++ b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_procpu.dts @@ -54,14 +54,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - uext_serial: &uart1 {}; uext_i2c: &i2c0 {}; uext_spi: &spi2 {}; diff --git a/boards/olimex/olimexino_stm32/olimexino_stm32_defconfig b/boards/olimex/olimexino_stm32/olimexino_stm32_defconfig index 9472e788675..d9ffe5b49a7 100644 --- a/boards/olimex/olimexino_stm32/olimexino_stm32_defconfig +++ b/boards/olimex/olimexino_stm32/olimexino_stm32_defconfig @@ -15,9 +15,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# enable clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/olimex/stm32_e407/doc/index.rst b/boards/olimex/stm32_e407/doc/index.rst index 6abdc3b564c..6af85cf75e0 100644 --- a/boards/olimex/stm32_e407/doc/index.rst +++ b/boards/olimex/stm32_e407/doc/index.rst @@ -336,7 +336,7 @@ Flashing an application to the Olimex-STM32-E407 Connect the ST-Link USB dongle to your host computer and to the JTAG port of the OLIMEX-STM32-E407 board. Then build and flash an application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -360,7 +360,7 @@ Debugging ========= Provided that you have a JTAG probe, you can debug an application in the usual -way. Here is an example for the :ref:`hello_world` application. +way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/olimex/stm32_e407/olimex_stm32_e407_defconfig b/boards/olimex/stm32_e407/olimex_stm32_e407_defconfig index c729b83e3d0..51eadcb4809 100644 --- a/boards/olimex/stm32_e407/olimex_stm32_e407_defconfig +++ b/boards/olimex/stm32_e407/olimex_stm32_e407_defconfig @@ -14,9 +14,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/olimex/stm32_e407/support/openocd.cfg b/boards/olimex/stm32_e407/support/openocd.cfg index d97149f9691..c416c6958c0 100644 --- a/boards/olimex/stm32_e407/support/openocd.cfg +++ b/boards/olimex/stm32_e407/support/openocd.cfg @@ -1,13 +1,12 @@ -source [find interface/stlink.cfg] +source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg] +# source [find interface/stlink.cfg] set WORKAREASIZE 0x10000 -transport select hla_swd - source [find target/stm32f4x.cfg] -adapter_khz 1000 -adapter_nsrst_delay 100 +adapter speed 1000 +adapter srst delay 100 jtag_ntrst_delay 100 reset_config srst_only srst_nogate diff --git a/boards/olimex/stm32_h103/doc/index.rst b/boards/olimex/stm32_h103/doc/index.rst index 3abfb3b8885..291b34bfc34 100644 --- a/boards/olimex/stm32_h103/doc/index.rst +++ b/boards/olimex/stm32_h103/doc/index.rst @@ -219,7 +219,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/olimex/stm32_h103/olimex_stm32_h103_defconfig b/boards/olimex/stm32_h103/olimex_stm32_h103_defconfig index 9fd4400ac20..5568aa36c02 100644 --- a/boards/olimex/stm32_h103/olimex_stm32_h103_defconfig +++ b/boards/olimex/stm32_h103/olimex_stm32_h103_defconfig @@ -8,9 +8,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# enable clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/olimex/stm32_h103/support/openocd_olimex_jtag.cfg b/boards/olimex/stm32_h103/support/openocd_olimex_jtag.cfg index e953fd32a05..3020364ce9c 100644 --- a/boards/olimex/stm32_h103/support/openocd_olimex_jtag.cfg +++ b/boards/olimex/stm32_h103/support/openocd_olimex_jtag.cfg @@ -4,8 +4,8 @@ transport select jtag source [find board/olimex_stm32_h103.cfg] -adapter_khz 1000 -adapter_nsrst_delay 100 +adapter speed 1000 +adapter srst delay 100 jtag_ntrst_delay 100 reset_config srst_only srst_nogate diff --git a/boards/olimex/stm32_h405/doc/index.rst b/boards/olimex/stm32_h405/doc/index.rst index ab051345b9c..ff3c8b2bf46 100644 --- a/boards/olimex/stm32_h405/doc/index.rst +++ b/boards/olimex/stm32_h405/doc/index.rst @@ -171,7 +171,7 @@ In the following examples a ST-Link V2 USB dongle is used. Flashing an application to the Olimex-STM32-H405 ================================================ -The sample application :ref:`hello_world` is being used in this tutorial. +The sample application :zephyr:code-sample:`hello_world` is being used in this tutorial. Connect the ST-Link USB dongle to your host computer and to the JTAG port of the OLIMEX-STM32-H405 board. @@ -201,7 +201,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/olimex/stm32_h405/olimex_stm32_h405_defconfig b/boards/olimex/stm32_h405/olimex_stm32_h405_defconfig index c729b83e3d0..51eadcb4809 100644 --- a/boards/olimex/stm32_h405/olimex_stm32_h405_defconfig +++ b/boards/olimex/stm32_h405/olimex_stm32_h405_defconfig @@ -14,9 +14,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/olimex/stm32_h405/support/openocd.cfg b/boards/olimex/stm32_h405/support/openocd.cfg index 1f577d2c243..427feadd2c1 100644 --- a/boards/olimex/stm32_h405/support/openocd.cfg +++ b/boards/olimex/stm32_h405/support/openocd.cfg @@ -6,8 +6,8 @@ transport select hla_swd source [find target/stm32f4x.cfg] -adapter_khz 1000 -adapter_nsrst_delay 100 +adapter speed 1000 +adapter srst delay 100 jtag_ntrst_delay 100 reset_config srst_only srst_nogate diff --git a/boards/olimex/stm32_h407/doc/index.rst b/boards/olimex/stm32_h407/doc/index.rst index 3555ed52a35..114543e27cf 100644 --- a/boards/olimex/stm32_h407/doc/index.rst +++ b/boards/olimex/stm32_h407/doc/index.rst @@ -332,7 +332,7 @@ Flashing an application to the Olimex-STM32-H407 Connect the ARM-USB-OCD-H debugger to your host computer and to the JTAG port of the OLIMEX-STM32-H407 board. Then build and flash an application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -357,7 +357,7 @@ Debugging ========= Provided that you have a JTAG probe, you can debug an application in the usual -way. Here is an example for the :ref:`hello_world` application. +way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/olimex/stm32_h407/olimex_stm32_h407_defconfig b/boards/olimex/stm32_h407/olimex_stm32_h407_defconfig index c729b83e3d0..51eadcb4809 100644 --- a/boards/olimex/stm32_h407/olimex_stm32_h407_defconfig +++ b/boards/olimex/stm32_h407/olimex_stm32_h407_defconfig @@ -14,9 +14,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/olimex/stm32_h407/support/openocd.cfg b/boards/olimex/stm32_h407/support/openocd.cfg index c48bab3646b..a9db97fb87f 100644 --- a/boards/olimex/stm32_h407/support/openocd.cfg +++ b/boards/olimex/stm32_h407/support/openocd.cfg @@ -6,8 +6,8 @@ transport select jtag source [find target/stm32f4x.cfg] -adapter_khz 1000 -adapter_nsrst_delay 100 +adapter speed 1000 +adapter srst delay 100 jtag_ntrst_delay 100 reset_config srst_only srst_nogate diff --git a/boards/olimex/stm32_p405/doc/index.rst b/boards/olimex/stm32_p405/doc/index.rst index e68bcb589ca..c754213c954 100644 --- a/boards/olimex/stm32_p405/doc/index.rst +++ b/boards/olimex/stm32_p405/doc/index.rst @@ -216,7 +216,7 @@ In the following examples a ST-Link V2 USB dongle is used. Flashing an application to the Olimex-STM32-P405 ================================================ -The sample application :ref:`hello_world` is being used in this tutorial. +The sample application :zephyr:code-sample:`hello_world` is being used in this tutorial. Connect the ST-Link USB dongle to your host computer and to the JTAG port of the OLIMEX-STM32-P405 board. @@ -245,7 +245,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/olimex/stm32_p405/olimex_stm32_p405_defconfig b/boards/olimex/stm32_p405/olimex_stm32_p405_defconfig index 758675b14ba..a6763abd156 100644 --- a/boards/olimex/stm32_p405/olimex_stm32_p405_defconfig +++ b/boards/olimex/stm32_p405/olimex_stm32_p405_defconfig @@ -15,10 +15,4 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - CONFIG_ENTROPY_GENERATOR=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/olimex/stm32_p405/support/openocd.cfg b/boards/olimex/stm32_p405/support/openocd.cfg index d97149f9691..269578295d4 100644 --- a/boards/olimex/stm32_p405/support/openocd.cfg +++ b/boards/olimex/stm32_p405/support/openocd.cfg @@ -6,8 +6,8 @@ transport select hla_swd source [find target/stm32f4x.cfg] -adapter_khz 1000 -adapter_nsrst_delay 100 +adapter speed 1000 +adapter srst delay 100 jtag_ntrst_delay 100 reset_config srst_only srst_nogate diff --git a/boards/openisa/rv32m1_vega/doc/index.rst b/boards/openisa/rv32m1_vega/doc/index.rst index 339b8dc5e0c..92d9e999752 100644 --- a/boards/openisa/rv32m1_vega/doc/index.rst +++ b/boards/openisa/rv32m1_vega/doc/index.rst @@ -577,7 +577,7 @@ toolchain and OpenOCD:: The above only sets these variables for your current shell session. You need to make sure this happens every time you use this board. -Now let's compile the :ref:`hello_world` application. (You can try +Now let's compile the :zephyr:code-sample:`hello_world` application. (You can try others as well; see :ref:`samples-and-demos` for more.) .. We can't use zephyr-app-commands to provide build instructions diff --git a/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy.dts b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy.dts index 44f3ca3bc6f..ceba94b4794 100644 --- a/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy.dts +++ b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy.dts @@ -21,10 +21,6 @@ zephyr,code-partition = &slot0_partition; zephyr,bt-hci = &bt_hci_controller; }; - - aliases { - spi-flash0 = &mx25r32; - }; }; &bt_hci_controller { diff --git a/boards/openisa/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg b/boards/openisa/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg index 11f5deb062d..08a4880dc04 100644 --- a/boards/openisa/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg +++ b/boards/openisa/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg @@ -3,7 +3,7 @@ set _WORKAREASIZE 0x2000 -adapter_khz 1000 +adapter speed 1000 interface jlink transport select jtag diff --git a/boards/openisa/rv32m1_vega/support/openocd_rv32m1_vega_zero_riscy.cfg b/boards/openisa/rv32m1_vega/support/openocd_rv32m1_vega_zero_riscy.cfg index 491dc56a54d..71d23a125d3 100644 --- a/boards/openisa/rv32m1_vega/support/openocd_rv32m1_vega_zero_riscy.cfg +++ b/boards/openisa/rv32m1_vega/support/openocd_rv32m1_vega_zero_riscy.cfg @@ -3,7 +3,7 @@ set _WORKAREASIZE 0x2000 -adapter_khz 1000 +adapter speed 1000 interface jlink transport select jtag diff --git a/boards/others/black_f407ve/black_f407ve.dts b/boards/others/black_f407ve/black_f407ve.dts index 539f9838fbf..2411e0e5a94 100644 --- a/boards/others/black_f407ve/black_f407ve.dts +++ b/boards/others/black_f407ve/black_f407ve.dts @@ -57,7 +57,6 @@ led0 = &green_led_1; led1 = &green_led_2; sw0 = &user_button_UP; - spi-flash0 = &w25q16cv; }; }; diff --git a/boards/others/black_f407ve/black_f407ve_defconfig b/boards/others/black_f407ve/black_f407ve_defconfig index 02216f83f72..2ccb0d375b5 100644 --- a/boards/others/black_f407ve/black_f407ve_defconfig +++ b/boards/others/black_f407ve/black_f407ve_defconfig @@ -13,11 +13,5 @@ CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - # Enable GPIO CONFIG_GPIO=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/others/black_f407ve/doc/index.rst b/boards/others/black_f407ve/doc/index.rst index a338e7ccf4b..cffdd4d41be 100644 --- a/boards/others/black_f407ve/doc/index.rst +++ b/boards/others/black_f407ve/doc/index.rst @@ -222,7 +222,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/others/black_f407zg_pro/black_f407zg_pro_defconfig b/boards/others/black_f407zg_pro/black_f407zg_pro_defconfig index 02216f83f72..2ccb0d375b5 100644 --- a/boards/others/black_f407zg_pro/black_f407zg_pro_defconfig +++ b/boards/others/black_f407zg_pro/black_f407zg_pro_defconfig @@ -13,11 +13,5 @@ CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - # Enable GPIO CONFIG_GPIO=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/others/black_f407zg_pro/doc/index.rst b/boards/others/black_f407zg_pro/doc/index.rst index 1ca764cdf1d..4857e8bb8da 100644 --- a/boards/others/black_f407zg_pro/doc/index.rst +++ b/boards/others/black_f407zg_pro/doc/index.rst @@ -204,7 +204,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/others/icev_wireless/doc/index.rst b/boards/others/icev_wireless/doc/index.rst index 5484924e8d6..5b56cd94c3d 100644 --- a/boards/others/icev_wireless/doc/index.rst +++ b/boards/others/icev_wireless/doc/index.rst @@ -112,7 +112,7 @@ MCUboot bootloader ================== User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. +must be built (and flashed) at least once. There are two options to be used when building an application: @@ -123,9 +123,10 @@ There are two options to be used when building an application: User can select the MCUboot bootloader by adding the following line to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y Sysbuild ======== @@ -137,7 +138,7 @@ To build the sample application using sysbuild use the command: .. zephyr-app-commands:: :tool: west - :app: samples/hello_world + :zephyr-app: samples/hello_world :board: icev_wireless :goals: build :west-args: --sysbuild @@ -173,7 +174,7 @@ Manual build ============ During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. +For that reason, images can be built one at a time using traditional build. The instructions following are relevant for both manual build and sysbuild. The only difference is the structure of the build directory. @@ -223,7 +224,7 @@ The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite t ``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` parameter when building. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -232,7 +233,7 @@ Here is an example for building the :ref:`hello_world` application. :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/others/icev_wireless/icev_wireless.dts b/boards/others/icev_wireless/icev_wireless.dts index 8bd52196603..6209aeac7c2 100644 --- a/boards/others/icev_wireless/icev_wireless.dts +++ b/boards/others/icev_wireless/icev_wireless.dts @@ -48,10 +48,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - &uart0 { current-speed = <115200>; pinctrl-0 = <&uart0_default>; diff --git a/boards/others/icev_wireless/support/openocd.cfg b/boards/others/icev_wireless/support/openocd.cfg index 02754ff2a73..7421637880c 100644 --- a/boards/others/icev_wireless/support/openocd.cfg +++ b/boards/others/icev_wireless/support/openocd.cfg @@ -3,4 +3,4 @@ set ESP_RTOS none source [find interface/esp_usb_jtag.cfg] source [find target/esp32c3.cfg] -adapter_khz 5000 +adapter speed 5000 diff --git a/boards/others/neorv32/doc/index.rst b/boards/others/neorv32/doc/index.rst index 6626c24d0d0..a2dedba0a76 100644 --- a/boards/others/neorv32/doc/index.rst +++ b/boards/others/neorv32/doc/index.rst @@ -121,7 +121,7 @@ etc.): Flashing via JTAG ================= -Here is an example for building and flashing the :ref:`hello_world` application +Here is an example for building and flashing the :zephyr:code-sample:`hello_world` application for the NEORV32 via JTAG. Flashing via JTAG requires a NEORV32 SoC implementation with the On-Chip Debugger (OCD) and bootloader enabled. @@ -185,7 +185,7 @@ built-in bootloader as described in the NEORV32 user guide. Debugging via JTAG ================== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/others/neorv32/neorv32.dts b/boards/others/neorv32/neorv32.dts index aa9bf121679..ec78e301fb0 100644 --- a/boards/others/neorv32/neorv32.dts +++ b/boards/others/neorv32/neorv32.dts @@ -11,6 +11,9 @@ #include / { + model = "NEORV32"; + compatible = "neorv32"; + aliases { led0 = &led0; led1 = &led1; diff --git a/boards/others/serpente/doc/index.rst b/boards/others/serpente/doc/index.rst index 4b6bf5e7390..c624c5ad062 100644 --- a/boards/others/serpente/doc/index.rst +++ b/boards/others/serpente/doc/index.rst @@ -56,7 +56,7 @@ following hardware features: Other hardware features are not currently supported by Zephyr. The default configuration can be found in the Kconfig file -:zephyr_file:`boards/arturo182/serpente/serpente_defconfig`. +:zephyr_file:`boards/others/serpente/serpente_defconfig`. Connections and IOs =================== diff --git a/boards/others/stm32_min_dev/doc/index.rst b/boards/others/stm32_min_dev/doc/index.rst index 61caf674f95..e27ea5c59f5 100644 --- a/boards/others/stm32_min_dev/doc/index.rst +++ b/boards/others/stm32_min_dev/doc/index.rst @@ -172,7 +172,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/others/stm32_min_dev/stm32_min_dev_defconfig b/boards/others/stm32_min_dev/stm32_min_dev_defconfig index ac78c1fed4e..e603f1cf766 100644 --- a/boards/others/stm32_min_dev/stm32_min_dev_defconfig +++ b/boards/others/stm32_min_dev/stm32_min_dev_defconfig @@ -13,9 +13,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# enable clock control -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/others/stm32f030_demo/stm32f030_demo_defconfig b/boards/others/stm32f030_demo/stm32f030_demo_defconfig index d7de7d90f54..8c2017d2bcc 100644 --- a/boards/others/stm32f030_demo/stm32f030_demo_defconfig +++ b/boards/others/stm32f030_demo/stm32f030_demo_defconfig @@ -16,9 +16,3 @@ CONFIG_UART_CONSOLE=y # GPIO Controller CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32f103_mini/Kconfig.stm32f103_mini b/boards/others/stm32f103_mini/Kconfig.stm32f103_mini similarity index 100% rename from boards/st/stm32f103_mini/Kconfig.stm32f103_mini rename to boards/others/stm32f103_mini/Kconfig.stm32f103_mini diff --git a/boards/st/stm32f103_mini/board.cmake b/boards/others/stm32f103_mini/board.cmake similarity index 100% rename from boards/st/stm32f103_mini/board.cmake rename to boards/others/stm32f103_mini/board.cmake diff --git a/boards/st/stm32f103_mini/board.yml b/boards/others/stm32f103_mini/board.yml similarity index 100% rename from boards/st/stm32f103_mini/board.yml rename to boards/others/stm32f103_mini/board.yml diff --git a/boards/st/stm32f103_mini/doc/img/stm32f103_mini_blue.jpg b/boards/others/stm32f103_mini/doc/img/stm32f103_mini_blue.jpg similarity index 100% rename from boards/st/stm32f103_mini/doc/img/stm32f103_mini_blue.jpg rename to boards/others/stm32f103_mini/doc/img/stm32f103_mini_blue.jpg diff --git a/boards/st/stm32f103_mini/doc/img/stm32f103_mini_pin.jpg b/boards/others/stm32f103_mini/doc/img/stm32f103_mini_pin.jpg similarity index 100% rename from boards/st/stm32f103_mini/doc/img/stm32f103_mini_pin.jpg rename to boards/others/stm32f103_mini/doc/img/stm32f103_mini_pin.jpg diff --git a/boards/st/stm32f103_mini/doc/img/stm32f103_mini_yellow.jpg b/boards/others/stm32f103_mini/doc/img/stm32f103_mini_yellow.jpg similarity index 100% rename from boards/st/stm32f103_mini/doc/img/stm32f103_mini_yellow.jpg rename to boards/others/stm32f103_mini/doc/img/stm32f103_mini_yellow.jpg diff --git a/boards/st/stm32f103_mini/doc/index.rst b/boards/others/stm32f103_mini/doc/index.rst similarity index 100% rename from boards/st/stm32f103_mini/doc/index.rst rename to boards/others/stm32f103_mini/doc/index.rst diff --git a/boards/st/stm32f103_mini/stm32f103_mini.dts b/boards/others/stm32f103_mini/stm32f103_mini.dts similarity index 100% rename from boards/st/stm32f103_mini/stm32f103_mini.dts rename to boards/others/stm32f103_mini/stm32f103_mini.dts diff --git a/boards/st/stm32f103_mini/stm32f103_mini.yaml b/boards/others/stm32f103_mini/stm32f103_mini.yaml similarity index 96% rename from boards/st/stm32f103_mini/stm32f103_mini.yaml rename to boards/others/stm32f103_mini/stm32f103_mini.yaml index ef1427ba5f9..792145e6a16 100644 --- a/boards/st/stm32f103_mini/stm32f103_mini.yaml +++ b/boards/others/stm32f103_mini/stm32f103_mini.yaml @@ -16,4 +16,5 @@ supported: - watchdog - adc - counter + - usbd vendor: st diff --git a/boards/others/stm32f103_mini/stm32f103_mini_defconfig b/boards/others/stm32f103_mini/stm32f103_mini_defconfig new file mode 100644 index 00000000000..5568aa36c02 --- /dev/null +++ b/boards/others/stm32f103_mini/stm32f103_mini_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +# enable uart driver +CONFIG_SERIAL=y +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# enable GPIO +CONFIG_GPIO=y diff --git a/boards/st/stm32f103_mini/support/openocd.cfg b/boards/others/stm32f103_mini/support/openocd.cfg similarity index 100% rename from boards/st/stm32f103_mini/support/openocd.cfg rename to boards/others/stm32f103_mini/support/openocd.cfg diff --git a/boards/others/stm32f401_mini/stm32f401_mini_defconfig b/boards/others/stm32f401_mini/stm32f401_mini_defconfig index 8f08a2bfe96..eea1cfeeb30 100644 --- a/boards/others/stm32f401_mini/stm32f401_mini_defconfig +++ b/boards/others/stm32f401_mini/stm32f401_mini_defconfig @@ -14,9 +14,3 @@ CONFIG_UART_CONSOLE=y # Enable GPIO CONFIG_GPIO=y - -# Clock configuration -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/panasonic/pan1770_evb/Kconfig b/boards/panasonic/pan1770_evb/Kconfig deleted file mode 100644 index 305b35abf99..00000000000 --- a/boards/panasonic/pan1770_evb/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -# PAN1770 EVB configuration - -# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_PAN1770_EVB - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF52X_HV - default y - -endif # BOARD_PAN1770_EVB diff --git a/boards/panasonic/pan1770_evb/pan1770_evb.dts b/boards/panasonic/pan1770_evb/pan1770_evb.dts index 2b2a9d561a7..886539344f4 100644 --- a/boards/panasonic/pan1770_evb/pan1770_evb.dts +++ b/boards/panasonic/pan1770_evb/pan1770_evb.dts @@ -133,6 +133,14 @@ }; }; +®0 { + status = "okay"; +}; + +®1 { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; diff --git a/boards/panasonic/pan1770_evb/pan1770_evb.yaml b/boards/panasonic/pan1770_evb/pan1770_evb.yaml index d19c0f4e33a..35ada5617cc 100644 --- a/boards/panasonic/pan1770_evb/pan1770_evb.yaml +++ b/boards/panasonic/pan1770_evb/pan1770_evb.yaml @@ -25,7 +25,6 @@ supported: - i2s - pwm - spi - - usb_cdc - usb_device - watchdog - netif:openthread diff --git a/boards/panasonic/pan1780_evb/Kconfig b/boards/panasonic/pan1780_evb/Kconfig deleted file mode 100644 index 2ac3fc5cef5..00000000000 --- a/boards/panasonic/pan1780_evb/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -# PAN1780 EVB configuration - -# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_PAN1780_EVB - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF52X_HV - default y - -endif # BOARD_PAN1780_EVB diff --git a/boards/panasonic/pan1780_evb/pan1780_evb.dts b/boards/panasonic/pan1780_evb/pan1780_evb.dts index da9a7e7fdb8..0fdde8ec355 100644 --- a/boards/panasonic/pan1780_evb/pan1780_evb.dts +++ b/boards/panasonic/pan1780_evb/pan1780_evb.dts @@ -133,6 +133,14 @@ }; }; +®0 { + status = "okay"; +}; + +®1 { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; diff --git a/boards/panasonic/pan1780_evb/pan1780_evb.yaml b/boards/panasonic/pan1780_evb/pan1780_evb.yaml index 9f29b96007a..8833f01c3a2 100644 --- a/boards/panasonic/pan1780_evb/pan1780_evb.yaml +++ b/boards/panasonic/pan1780_evb/pan1780_evb.yaml @@ -25,7 +25,6 @@ supported: - i2s - pwm - spi - - usb_cdc - usb_device - watchdog - netif:openthread diff --git a/boards/panasonic/pan1781_evb/Kconfig b/boards/panasonic/pan1781_evb/Kconfig deleted file mode 100644 index 3eace417b93..00000000000 --- a/boards/panasonic/pan1781_evb/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# PAN1781 EVB configuration - -# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_PAN1781_EVB diff --git a/boards/panasonic/pan1781_evb/pan1781_evb.dts b/boards/panasonic/pan1781_evb/pan1781_evb.dts index 8ab6af51ea9..e5c501093f8 100644 --- a/boards/panasonic/pan1781_evb/pan1781_evb.dts +++ b/boards/panasonic/pan1781_evb/pan1781_evb.dts @@ -92,6 +92,10 @@ }; }; +®1 { + regulator-initial-mode = ; +}; + &sw_pwm { status ="okay"; channel-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; diff --git a/boards/panasonic/pan1782_evb/Kconfig b/boards/panasonic/pan1782_evb/Kconfig deleted file mode 100644 index c6fc324ec20..00000000000 --- a/boards/panasonic/pan1782_evb/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# PAN1782 EVB configuration - -# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_PAN1782_EVB diff --git a/boards/panasonic/pan1782_evb/pan1782_evb.dts b/boards/panasonic/pan1782_evb/pan1782_evb.dts index fdc86f792ec..181aa6cb372 100644 --- a/boards/panasonic/pan1782_evb/pan1782_evb.dts +++ b/boards/panasonic/pan1782_evb/pan1782_evb.dts @@ -94,6 +94,10 @@ }; }; +®1 { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; diff --git a/boards/panasonic/pan1783/CMakeLists.txt b/boards/panasonic/pan1783/CMakeLists.txt deleted file mode 100644 index 88360ce24f7..00000000000 --- a/boards/panasonic/pan1783/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_SOC_NRF5340_CPUAPP_QKAA AND CONFIG_BOARD_ENABLE_CPUNET) - zephyr_library() - zephyr_library_sources(pan1783_nrf5340_cpunet_reset.c) -endif() diff --git a/boards/panasonic/pan1783/Kconfig b/boards/panasonic/pan1783/Kconfig index 671d17acad9..7951989cde3 100644 --- a/boards/panasonic/pan1783/Kconfig +++ b/boards/panasonic/pan1783/Kconfig @@ -5,38 +5,11 @@ if SOC_NRF5340_CPUAPP_QKAA -config BOARD_ENABLE_DCDC_APP - bool "Application MCU DCDC converter" - select SOC_DCDC_NRF53X_APP - default y - -config BOARD_ENABLE_DCDC_NET - bool "Network MCU DCDC converter" - select SOC_DCDC_NRF53X_NET - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF53X_HV - default y - -config BOARD_ENABLE_CPUNET - bool "NRF53 Network MCU" - select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ - $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) - help - This option enables releasing the Network 'force off' signal, which - as a consequence will power up the Network MCU during system boot. - Additionally, the option allocates GPIO pins that will be used by UARTE - of the Network MCU. - default y if (BT || NRF_802154_SER_HOST) - config DOMAIN_CPUNET_BOARD string default "pan1783_evb/nrf5340/cpunet" if BOARD_PAN1783_EVB_NRF5340_CPUAPP default "pan1783a_evb/nrf5340/cpunet" if BOARD_PAN1783A_EVB_NRF5340_CPUAPP default "pan1783a_pa_evb/nrf5340/cpunet" if BOARD_PAN1783A_PA_EVB_NRF5340_CPUAPP - depends on BOARD_ENABLE_CPUNET help The board which will be used for CPUNET domain when creating a multi image application where one or more images should be located on diff --git a/boards/panasonic/pan1783/Kconfig.defconfig b/boards/panasonic/pan1783/Kconfig.defconfig index 6c70d441e91..9f69518027a 100644 --- a/boards/panasonic/pan1783/Kconfig.defconfig +++ b/boards/panasonic/pan1783/Kconfig.defconfig @@ -3,9 +3,6 @@ # Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH # SPDX-License-Identifier: Apache-2.0 -config MBOX_NRFX_IPC - default MBOX - if SOC_NRF5340_CPUAPP_QKAA config BT_HCI_IPC diff --git a/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp.yaml b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp.yaml index 401745b3333..771055b508a 100644 --- a/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp.yaml +++ b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp.yaml @@ -14,7 +14,6 @@ supported: - i2s - pwm - watchdog - - usb_cdc - usb_device - netif:openthread - gpio diff --git a/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet.dts b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet.dts index 28feb6d660f..81eff2968c3 100644 --- a/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet.dts +++ b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet.dts @@ -19,5 +19,5 @@ }; }; -/* Include shared RAM configuration file */ -#include "pan1783_nrf5340_shared_sram_planning_conf.dtsi" +/* Include default shared RAM configuration file */ +#include diff --git a/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common.dtsi b/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common.dtsi index 315e1c8372a..421ca523925 100644 --- a/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common.dtsi +++ b/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common.dtsi @@ -156,10 +156,21 @@ mcuboot-button0 = &evb_sw1; mcuboot-led0 = &evb_led1; watchdog0 = &wdt0; - spi-flash0 = &mx25r64; }; }; +&vregmain { + regulator-initial-mode = ; +}; + +&vregradio { + regulator-initial-mode = ; +}; + +&vregh { + status = "okay"; +}; + &adc { status = "okay"; }; @@ -245,31 +256,6 @@ arduino_spi: &spi4 { pinctrl-names = "default", "sleep"; }; -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x00010000>; - }; - slot0_partition: partition@10000 { - label = "image-0"; - }; - slot1_partition: partition@80000 { - label = "image-1"; - }; - /* 0xf0000 to 0xf7fff reserved for TF-M partitions */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; - &ieee802154 { status = "okay"; }; @@ -279,22 +265,5 @@ zephyr_udc0: &usbd { status = "okay"; }; -/ { - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_image: image@20000000 { - /* Zephyr image(s) memory */ - }; - - sram0_s: image_s@20000000 { - /* Secure image memory */ - }; - }; -}; - -/* Include partition configuration file */ -#include "pan1783_nrf5340_cpuapp_partition_conf.dtsi" +/* Include default memory partition configuration file */ +#include diff --git a/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_partition_conf.dtsi b/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_partition_conf.dtsi deleted file mode 100644 index a6edad09bba..00000000000 --- a/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_partition_conf.dtsi +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* - * Default Flash planning for pan1783_evb CPUAPP (Application MCU). - * - * Secure image will be placed, by default, in flash0 - * (or in slot0, if MCUboot is present). - * Secure image will use sram0 for system memory. - * - */ - -&slot0_partition { - reg = <0x00010000 0x40000>; -}; - -&slot1_partition { - reg = <0x00080000 0x40000>; -}; - -/* Default SRAM planning when building for nRF5340 - * - Lowest 448 kB SRAM allocated to Secure image (sram0_s) - * - Upper 64 kB SRAM allocated as Shared memory (sram0_shared) - * (see shared_sram_planning_conf.dtsi) - */ -&sram0_image { - reg = <0x20000000 DT_SIZE_K(448)>; -}; - -&sram0_s { - reg = <0x20000000 0x70000>; -}; - -/* Include shared RAM configuration file */ -#include "pan1783_nrf5340_shared_sram_planning_conf.dtsi" diff --git a/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_common.dtsi b/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_common.dtsi index a23b1d87b10..3fcdfba3dbb 100644 --- a/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_common.dtsi +++ b/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_common.dtsi @@ -203,5 +203,5 @@ arduino_spi: &spi0 { status = "okay"; }; -/* Include shared RAM configuration file */ -#include "pan1783_nrf5340_shared_sram_planning_conf.dtsi" +/* Include default shared RAM configuration file */ +#include diff --git a/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_reset.c b/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_reset.c deleted file mode 100644 index bf0626ce30b..00000000000 --- a/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_reset.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -#include -#include - -#if defined(CONFIG_BOARD_PAN1783_EVB_NRF5340_CPUAPP) -LOG_MODULE_REGISTER(pan1783_evb_cpuapp, CONFIG_LOG_DEFAULT_LEVEL); -#elif defined(CONFIG_BOARD_PAN1783A_EVB_NRF5340_CPUAPP) -LOG_MODULE_REGISTER(pan1783a_evb_cpuapp, CONFIG_LOG_DEFAULT_LEVEL); -#elif defined(CONFIG_BOARD_PAN1783A_PA_EVB_NRF5340_CPUAPP) -LOG_MODULE_REGISTER(pan1783a_pa_evb_cpuapp, CONFIG_LOG_DEFAULT_LEVEL); -#else -#error "No board selected!" -#endif - -#if defined(CONFIG_BT_CTLR_DEBUG_PINS_CPUAPP) -#include <../subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/debug.h> -#else -#define DEBUG_SETUP() -#endif - -static void remoteproc_mgr_config(void) -{ - /* Route Bluetooth Controller Debug Pins */ - DEBUG_SETUP(); - - /* Retain nRF5340 Network MCU */ - NRF_SPU->EXTDOMAIN[0].PERM = 1 << 4; -} - -static int remoteproc_mgr_boot(void) -{ - /* Configure permissions for the Network MCU. */ - remoteproc_mgr_config(); - - /* Release the Network MCU, 'Release force off signal' */ - nrf_reset_network_force_off(NRF_RESET, false); - - LOG_DBG("Network MCU released."); - - return 0; -} - -SYS_INIT(remoteproc_mgr_boot, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); diff --git a/boards/panasonic/pan1783/pan1783_nrf5340_shared_sram_planning_conf.dtsi b/boards/panasonic/pan1783/pan1783_nrf5340_shared_sram_planning_conf.dtsi deleted file mode 100644 index 9e2b673f84a..00000000000 --- a/boards/panasonic/pan1783/pan1783_nrf5340_shared_sram_planning_conf.dtsi +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* Default shared SRAM planning when building for PAN1783 EVB. - * This file is included by both nRF5340 CPUAPP (Application MCU) - * and nRF5340 CPUNET (Network MCU). - * - 64 kB SRAM allocated as Shared memory (sram0_shared) - * - Region defined after the image SRAM of Application MCU - */ - -/ { - chosen { - /* shared memory reserved for the inter-processor communication */ - zephyr,ipc_shm = &sram0_shared; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_shared: memory@20070000 { - /* SRAM allocated to shared memory */ - reg = <0x20070000 0x10000>; - }; - }; -}; diff --git a/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpuapp.yaml b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpuapp.yaml index f5a789788bf..3d9bea54228 100644 --- a/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpuapp.yaml +++ b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpuapp.yaml @@ -14,7 +14,6 @@ supported: - i2s - pwm - watchdog - - usb_cdc - usb_device - netif:openthread - gpio diff --git a/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpunet.dts b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpunet.dts index 44d61d69c25..52deb048576 100644 --- a/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpunet.dts +++ b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpunet.dts @@ -19,5 +19,5 @@ }; }; -/* Include shared RAM configuration file */ -#include "pan1783_nrf5340_shared_sram_planning_conf.dtsi" +/* Include default shared RAM configuration file */ +#include diff --git a/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpuapp.yaml b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpuapp.yaml index dc5600a999a..d9936750286 100644 --- a/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpuapp.yaml +++ b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpuapp.yaml @@ -14,7 +14,6 @@ supported: - i2s - pwm - watchdog - - usb_cdc - usb_device - netif:openthread - gpio diff --git a/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet.dts b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet.dts index 4856deaa3a1..54e580ffb75 100644 --- a/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet.dts +++ b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet.dts @@ -29,5 +29,5 @@ fem = <&nrf_radio_fem>; }; -/* Include shared RAM configuration file */ -#include "pan1783_nrf5340_shared_sram_planning_conf.dtsi" +/* Include default shared RAM configuration file */ +#include diff --git a/boards/particle/argon/Kconfig b/boards/particle/argon/Kconfig deleted file mode 100644 index 4746f2a5d96..00000000000 --- a/boards/particle/argon/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Particle Argon configuration - -# Copyright (c) 2018 Matthias Boesl -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_PARTICLE_ARGON diff --git a/boards/particle/argon/doc/index.rst b/boards/particle/argon/doc/index.rst index 2bbb15a546f..0cfedf946db 100644 --- a/boards/particle/argon/doc/index.rst +++ b/boards/particle/argon/doc/index.rst @@ -145,7 +145,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/particle/argon/dts/mesh_feather.dtsi b/boards/particle/argon/dts/mesh_feather.dtsi index ee3c4340d5b..de18a85facc 100644 --- a/boards/particle/argon/dts/mesh_feather.dtsi +++ b/boards/particle/argon/dts/mesh_feather.dtsi @@ -9,6 +9,8 @@ * * NOTE: This file is replicated in particle_{argon,boron,xenon}. * Changes should be made in all instances. */ + +#include #include "mesh_feather-pinctrl.dtsi" #include @@ -20,16 +22,12 @@ led3 = &status_blue; sw0 = &mode_button; sw1 = &reset_button; - spi-flash0 = &mx25l32; }; chosen { zephyr,console = &uart0; zephyr,uart-mcumgr = &uart0; zephyr,shell-uart = &uart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; zephyr,ieee802154 = &ieee802154; }; @@ -134,45 +132,6 @@ feather_adc: &adc { /* feather ADC */ status = "okay"; }; -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000C000>; - }; - slot0_partition: partition@c000 { - label = "image-0"; - reg = <0x0000C000 0x00067000>; - }; - slot1_partition: partition@73000 { - label = "image-1"; - reg = <0x00073000 0x00067000>; - }; - scratch_partition: partition@da000 { - label = "image-scratch"; - reg = <0x000da000 0x0001e000>; - }; - - /* - * The flash starting at 0x000f8000 and ending at - * 0x000fffff is reserved for use by the application. - */ - - /* - * Storage partition will be used by FCB/LittleFS/NVS - * if enabled. - */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; - &gpio0 { status = "okay"; }; diff --git a/boards/particle/argon/particle_argon.dts b/boards/particle/argon/particle_argon.dts index a88199fe40b..1d722585a52 100644 --- a/boards/particle/argon/particle_argon.dts +++ b/boards/particle/argon/particle_argon.dts @@ -32,6 +32,10 @@ }; }; +®1 { + regulator-initial-mode = ; +}; + &uicr { gpio-as-nreset; }; diff --git a/boards/particle/boron/Kconfig b/boards/particle/boron/Kconfig deleted file mode 100644 index 404b31d0460..00000000000 --- a/boards/particle/boron/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Particle Boron configuration - -# Copyright (c) 2018 Peter Bigot Consulting, LLC -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_PARTICLE_BORON diff --git a/boards/particle/boron/doc/index.rst b/boards/particle/boron/doc/index.rst index d5b7ce1f5d0..da87b144a0d 100644 --- a/boards/particle/boron/doc/index.rst +++ b/boards/particle/boron/doc/index.rst @@ -141,7 +141,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/particle/boron/dts/mesh_feather.dtsi b/boards/particle/boron/dts/mesh_feather.dtsi index 0005ca547ff..d9601ed9b77 100644 --- a/boards/particle/boron/dts/mesh_feather.dtsi +++ b/boards/particle/boron/dts/mesh_feather.dtsi @@ -9,6 +9,8 @@ * * NOTE: This file is replicated in particle_{argon,boron,xenon}. * Changes should be made in all instances. */ + +#include #include "mesh_feather-pinctrl.dtsi" #include @@ -20,16 +22,12 @@ led3 = &status_blue; sw0 = &mode_button; sw1 = &reset_button; - spi-flash0 = &mx25l32; }; chosen { zephyr,console = &uart0; zephyr,uart-mcumgr = &uart0; zephyr,shell-uart = &uart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; zephyr,ieee802154 = &ieee802154; }; @@ -134,45 +132,6 @@ feather_adc: &adc { /* feather ADC */ status = "okay"; }; -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000C000>; - }; - slot0_partition: partition@c000 { - label = "image-0"; - reg = <0x0000C000 0x00067000>; - }; - slot1_partition: partition@73000 { - label = "image-1"; - reg = <0x00073000 0x00067000>; - }; - scratch_partition: partition@da000 { - label = "image-scratch"; - reg = <0x000da000 0x0001e000>; - }; - - /* - * The flash starting at 0x000f8000 and ending at - * 0x000fffff is reserved for use by the application. - */ - - /* - * Storage partition will be used by FCB/LittleFS/NVS - * if enabled. - */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; - &gpio0 { status = "okay"; }; diff --git a/boards/particle/boron/particle_boron.dts b/boards/particle/boron/particle_boron.dts index 06e75a5a52e..a515d1a1601 100644 --- a/boards/particle/boron/particle_boron.dts +++ b/boards/particle/boron/particle_boron.dts @@ -36,6 +36,10 @@ }; }; +®1 { + regulator-initial-mode = ; +}; + &uicr { gpio-as-nreset; }; diff --git a/boards/particle/nrf51_blenano/doc/index.rst b/boards/particle/nrf51_blenano/doc/index.rst index 4caae408e21..1d6d2ea4a2a 100644 --- a/boards/particle/nrf51_blenano/doc/index.rst +++ b/boards/particle/nrf51_blenano/doc/index.rst @@ -79,7 +79,7 @@ DAPLink board, then attach that to your computer via USB. properly solder headers and assemble the DAPLink and BLE Nano boards. Now build and flash applications as usual. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -91,7 +91,7 @@ Debugging After mounting the BLE Nano on its DAPLink board as described above, you can debug an application in the usual way. Here is an example for -the :ref:`hello_world` application. +the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/particle/nrf52_blenano2/doc/index.rst b/boards/particle/nrf52_blenano2/doc/index.rst index 6c32b4f3d77..b2d0824bfc1 100644 --- a/boards/particle/nrf52_blenano2/doc/index.rst +++ b/boards/particle/nrf52_blenano2/doc/index.rst @@ -77,7 +77,7 @@ DAPLink board, then attach that to your computer via USB. connector. Now build and flash applications as usual. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -89,7 +89,7 @@ Debugging After mounting the BLE Nano 2 on its DAPLink board as described above, you can debug an application in the usual way. Here is an example for -the :ref:`hello_world` application. +the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/particle/xenon/Kconfig b/boards/particle/xenon/Kconfig deleted file mode 100644 index c98c3e9603a..00000000000 --- a/boards/particle/xenon/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Particle Xenon configuration - -# Copyright (c) 2018 Endre Karlson -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_PARTICLE_XENON diff --git a/boards/particle/xenon/doc/index.rst b/boards/particle/xenon/doc/index.rst index cf18340943a..d28b8aac1c0 100644 --- a/boards/particle/xenon/doc/index.rst +++ b/boards/particle/xenon/doc/index.rst @@ -146,7 +146,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/particle/xenon/dts/mesh_feather.dtsi b/boards/particle/xenon/dts/mesh_feather.dtsi index 13b7e238230..d9601ed9b77 100644 --- a/boards/particle/xenon/dts/mesh_feather.dtsi +++ b/boards/particle/xenon/dts/mesh_feather.dtsi @@ -9,6 +9,8 @@ * * NOTE: This file is replicated in particle_{argon,boron,xenon}. * Changes should be made in all instances. */ + +#include #include "mesh_feather-pinctrl.dtsi" #include @@ -26,9 +28,6 @@ zephyr,console = &uart0; zephyr,uart-mcumgr = &uart0; zephyr,shell-uart = &uart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; zephyr,ieee802154 = &ieee802154; }; @@ -133,45 +132,6 @@ feather_adc: &adc { /* feather ADC */ status = "okay"; }; -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000C000>; - }; - slot0_partition: partition@c000 { - label = "image-0"; - reg = <0x0000C000 0x00067000>; - }; - slot1_partition: partition@73000 { - label = "image-1"; - reg = <0x00073000 0x00067000>; - }; - scratch_partition: partition@da000 { - label = "image-scratch"; - reg = <0x000da000 0x0001e000>; - }; - - /* - * The flash starting at 0x000f8000 and ending at - * 0x000fffff is reserved for use by the application. - */ - - /* - * Storage partition will be used by FCB/LittleFS/NVS - * if enabled. - */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; - &gpio0 { status = "okay"; }; diff --git a/boards/particle/xenon/particle_xenon.dts b/boards/particle/xenon/particle_xenon.dts index 2d64ba119b2..7b33e54d5ad 100644 --- a/boards/particle/xenon/particle_xenon.dts +++ b/boards/particle/xenon/particle_xenon.dts @@ -29,10 +29,13 @@ aliases { watchdog0 = &wdt0; - spi-flash0 = &mx25l32; }; }; +®1 { + regulator-initial-mode = ; +}; + &uicr { gpio-as-nreset; }; diff --git a/boards/phytec/mimx8mm_phyboard_polis/Kconfig.defconfig b/boards/phytec/mimx8mm_phyboard_polis/Kconfig.defconfig deleted file mode 100644 index ec8c8486351..00000000000 --- a/boards/phytec/mimx8mm_phyboard_polis/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# MIMX8MM_PHYBOARD_POLIS board defconfig -# -# Copyright (c) 2022 PHYTEC Messtechnik GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMX8MM_PHYBOARD_POLIS - -if !XIP -config FLASH_SIZE - default 0 -config FLASH_BASE_ADDRESS - default 0 -endif - -endif # BOARD_MIMX8MM_PHYBOARD_POLIS diff --git a/boards/phytec/mimx8mm_phyboard_polis/doc/index.rst b/boards/phytec/mimx8mm_phyboard_polis/doc/index.rst index 010baf5760a..dc388d52c07 100644 --- a/boards/phytec/mimx8mm_phyboard_polis/doc/index.rst +++ b/boards/phytec/mimx8mm_phyboard_polis/doc/index.rst @@ -220,10 +220,10 @@ This should output something like this: .. code-block:: console - u-boot=> tftp 0x48000000 192.168.3.10:zyphr.bin + u-boot=> tftp 0x48000000 192.168.3.10:zephyr.bin Using ethernet@30be0000 device TFTP from server 192.168.3.10; our IP address is 192.168.3.11 - Filename 'zepyhr.bin'. + Filename 'zephyr.bin'. Load address: 0x48000000 Loading: ## 2 KiB/s @@ -249,7 +249,7 @@ And finaly starting the M4-Core at the right memory address: Starting the M4-Core via remoteproc =================================== -Copy the zepyhr.elf to ``/lib/firmware`` on the target. Maybe a Zephyr sample +Copy the zephyr.elf to ``/lib/firmware`` on the target. Maybe a Zephyr sample will be included in a future BSP release. .. note:: @@ -265,12 +265,12 @@ To load and start a firmware use this commands: .. code-block:: console - target$ echo /lib/firmware/zepyhr.elf > /sys/class/remoteproc/remoteproc0/firmware + target$ echo /lib/firmware/zephyr.elf > /sys/class/remoteproc/remoteproc0/firmware target$ echo start > /sys/class/remoteproc/remoteproc0/state [ 90.700611] remoteproc remoteproc0: powering up imx-rproc - [ 90.706114] remoteproc remoteproc0: Direct firmware load for /lib/firmware/zepyhr.elf failed w2 - [ 90.716571] remoteproc remoteproc0: Falling back to sysfs fallback for: /lib/firmware/zepyhr.elf - [ 90.739280] remoteproc remoteproc0: Booting fw image /lib/firmware/zepyhr.elf, size 599356 + [ 90.706114] remoteproc remoteproc0: Direct firmware load for /lib/firmware/zephyr.elf failed w2 + [ 90.716571] remoteproc remoteproc0: Falling back to sysfs fallback for: /lib/firmware/zephyr.elf + [ 90.739280] remoteproc remoteproc0: Booting fw image /lib/firmware/zephyr.elf, size 599356 [ 90.804448] remoteproc remoteproc0: remote processor imx-rproc is now up diff --git a/boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis-pinctrl.dtsi b/boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis-pinctrl.dtsi index 91efe29d219..928908a6162 100644 --- a/boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis-pinctrl.dtsi +++ b/boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis-pinctrl.dtsi @@ -12,7 +12,7 @@ pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx>, <&iomuxc_uart4_txd_uart_tx_uart4_tx>; slew-rate = "fast"; - drive-strength = "40-ohm"; + drive-strength = "x6"; }; }; @@ -21,7 +21,7 @@ pinmux = <&iomuxc_uart3_rxd_uart_rx_uart3_rx>, <&iomuxc_uart3_txd_uart_tx_uart3_tx>; slew-rate = "fast"; - drive-strength = "40-ohm"; + drive-strength = "x6"; }; }; @@ -32,7 +32,7 @@ <&iomuxc_sai3_txfs_uart_tx_uart2_rx>, <&iomuxc_sai3_txc_uart_rx_uart2_tx>; slew-rate = "fast"; - drive-strength = "40-ohm"; + drive-strength = "x6"; }; }; @@ -43,7 +43,7 @@ <&iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b>, <&iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b>; slew-rate = "fast"; - drive-strength = "40-ohm"; + drive-strength = "x6"; }; }; }; diff --git a/boards/phytec/mimx8mp_phyboard_pollux/Kconfig.defconfig b/boards/phytec/mimx8mp_phyboard_pollux/Kconfig.defconfig deleted file mode 100644 index e860faf97cf..00000000000 --- a/boards/phytec/mimx8mp_phyboard_pollux/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# PhyBOARD Pollux (i.MX8MP) defconfig - -# Copyright (c) 2022 PHYTEC Messtechnik GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMX8MP_PHYBOARD_POLLUX - -if !XIP -config FLASH_SIZE - default 0 -config FLASH_BASE_ADDRESS - default 0 -endif - -endif # BOARD_MIMX8MP_PHYBOARD_POLLUX diff --git a/boards/phytec/mimx8mp_phyboard_pollux/doc/index.rst b/boards/phytec/mimx8mp_phyboard_pollux/doc/index.rst index 501c7f541a0..6314b716513 100644 --- a/boards/phytec/mimx8mp_phyboard_pollux/doc/index.rst +++ b/boards/phytec/mimx8mp_phyboard_pollux/doc/index.rst @@ -47,8 +47,7 @@ Board features: :height: 405px :alt: PhyBOARD Pollux -More information about the board can be found at the -`PHYTEC website`_. +More information about the board can be found at the `PHYTEC website`_. Supported Features ================== @@ -56,32 +55,30 @@ Supported Features The Zephyr mimx8mp_phyboard_polis board configuration supports the following hardware features: -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | GPIO output | -| | | GPIO input | -+-----------+------------+-------------------------------------+ ++-----------+------------+------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+------------------------------------+ +| GPIO | on-chip | GPIO output | +| | | GPIO input | ++-----------+------------+------------------------------------+ The default configuration can be found in the defconfig file: :zephyr_file:`boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_mimx8ml8_m7_defconfig`. It's recommended to disable peripherals used by the M7-Core on the host running -on the Linux host. - -Other hardware features are not currently supported with Zephyr on the -M7-Core. +on the Linux host. Other hardware features are not currently supported with +Zephyr on the M7-Core. Connections and IOs =================== @@ -91,32 +88,27 @@ The following Compontens are tested and working correctly. UART ---- -+---------------+-----------------+-----------------------------------+ -| Board Name | SoM Name | Usage | -+===============+=================+===================================+ -| Debug USB(A53)| UART1 | UART Debug Console via USB | -+---------------+-----------------+-----------------------------------+ -| Wo WiFi Module| UART3 | UART to WiFi/BLE Module | -+---------------+-----------------+-----------------------------------+ -| Debug USB(M4) | UART4 | UART Debug Console via USB | -+---------------+-----------------+-----------------------------------+ ++-----------------+----------+----------------------------+ +| Board Name | SoM Name | Usage | ++=================+==========+============================+ +| Debug USB (A53) | UART1 | UART Debug Console via USB | ++-----------------+----------+----------------------------+ +| Wo WiFi Module | UART3 | UART to WiFi/BLE Module | ++-----------------+----------+----------------------------+ +| Debug USB (M7) | UART4 | UART Debug Console via USB | ++-----------------+----------+----------------------------+ .. note:: - Please note, that the, to UART3 connected, Wifi/BLE Module isn't working with - Zephyr yet. UART3 can also be used through pin 31(RX) and 33(TX) of the - X6 Connector. + The WiFi/BLE Module connected to UART3 isn't working with Zephyr yet. UART3 + can also be used through pin 31(RX) and 33(TX) of connector X6. GPIO ---- The pinmuxing for the GPIOs is the standard pinmuxing of the mimx8mp devicetree -created by NXP. You can find it here: - -:zephyr_file:`dts/arm/nxp/nxp_imx8ml_m7.dtsi`. - -The Pinout of the PhyBOARD Polis can be found here: - -`PHYTEC website`_ +created by NXP and can be found at +:zephyr_file:`dts/arm/nxp/nxp_imx8ml_m7.dtsi`. The Pinout of the PhyBOARD Polis +can be found at the `PHYTEC website`_. Programming and Debugging ************************* @@ -124,25 +116,23 @@ Programming and Debugging The i.MX8MP does not have a separate flash for the M7-Core. Because of this the A53-Core has to load the program for the M7-Core to the right memory address, set the PC and start the processor. -This can only by done with u-boot at the moment. We are working on our BSP to -enable remoteproc support. The M7 can use up to 3 different RAMs (currently, only two configurations are supported: ITCM and DDR). These are the memory mapping for A53 and M7: -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| Region | Cortex-A53 | Cortex-M7 (System Bus) | Cortex-M7 (Code Bus) | Size | -+============+=========================+========================+=======================+======================+ -| OCRAM | 0x00900000-0x0098FFFF | 0x20200000-0x2028FFFF | 0x00900000-0x0098FFFF | 576KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| DTCM | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| ITCM | 0x007E0000-0x007FFFFF | | 0x00000000-0x0001FFFF | 128KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| OCRAM_S | 0x00180000-0x00188FFF | 0x20180000-0x20188FFF | 0x00180000-0x00188FFF | 36KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| DDR | 0x80000000-0x803FFFFF | 0x80200000-0x803FFFFF | 0x80000000-0x801FFFFF | 2MB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ ++---------+-----------------------+------------------------+-----------------------+-------+ +| Region | Cortex-A53 | Cortex-M7 (System Bus) | Cortex-M7 (Code Bus) | Size | ++=========+=======================+========================+=======================+=======+ +| OCRAM | 0x00900000-0x0098FFFF | 0x20200000-0x2028FFFF | 0x00900000-0x0098FFFF | 576KB | ++---------+-----------------------+------------------------+-----------------------+-------+ +| DTCM | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | ++---------+-----------------------+------------------------+-----------------------+-------+ +| ITCM | 0x007E0000-0x007FFFFF | | 0x00000000-0x0001FFFF | 128KB | ++---------+-----------------------+------------------------+-----------------------+-------+ +| OCRAM_S | 0x00180000-0x00188FFF | 0x20180000-0x20188FFF | 0x00180000-0x00188FFF | 36KB | ++---------+-----------------------+------------------------+-----------------------+-------+ +| DDR | 0x80000000-0x803FFFFF | 0x80200000-0x803FFFFF | 0x80000000-0x801FFFFF | 2MB | ++---------+-----------------------+------------------------+-----------------------+-------+ For more information about memory mapping see the `i.MX 8M Plus Applications Processor Reference Manual`_ (section 2.1 to 2.3) @@ -151,20 +141,17 @@ At compilation time you have to choose which memory region will be used. This configuration is done in the devicetree and the defconfig / the config of your program. -**By default Zephyr will use the TCM memory region.** You can configure it like -this for the DDR region: - -In the devicetree overwrite the following nodes like this: +**By default Zephyr will use the TCM memory region.** You can configure it +to use the DDR region. In the devicetree overwrite you can select both options. .. code-block:: DTS chosen { /* TCM */ zephyr,flash = &itcm; - zephyr,sram = &dtcm; + zephyr,sram = &dtcm; }; -change it to .. code-block:: DTS @@ -175,55 +162,45 @@ change it to }; -In your prj.conf overwrite the configuration like this for the **DDR** memory -region: +And in the prj.conf the configuration to the **DDR** memory region: -.. code-block:: console +.. code-block:: cfg CONFIG_CODE_DDR=y CONFIG_CODE_ITCM=n +Connecting to the Serial Console +================================ -Starting the M7-Core via U-Boot -=============================== - -Load the compiled zephyr.bin to memory address 0x4800000. -This should output something like this: +A serial console for both the application CPU and the Cortex M7 coprocessor are +available via the onboard dual USB-to-UART converter. If you use Linux, create a +udev rule (as ``root``) to fix a permission issue when not using root for +flashing. .. code-block:: console - u-boot=> tftp 0x48000000 192.168.3.10:zyphr.bin - Using ethernet@30be0000 device - TFTP from server 192.168.3.10; our IP address is 192.168.3.11 - Filename 'zepyhr.bin'. - Load address: 0x48000000 - Loading: ## - 2 KiB/s - done - Bytes transferred = 27240 (6a68 hex) + # echo 'ATTR{idProduct}=="0a70", ATTR{idVendor}=="10c4", MODE="0666", GROUP="plugdev"' > /etc/udev/rules.d/50-usb-uart.rules -Because it's not possible to load directly to the TCM memory area you have to -copy the binaries. The last argument given is the size of the file in bytes, -you can copy it from the output of the last command. +Reload the rules and replug the device. .. code-block:: console - u-boot=> cp.b 0x48000000 0x7e0000 27240 + $ sudo udevadm control --reload-rules -And finaly starting the M7-Core at the right memory address: +Finally, unplug and plug the board again for the rules to take effect. + +Connect to the console via your favorite terminal program. For example: .. code-block:: console - u-boot=> bootaux 0x7e0000 - ## Starting auxiliary core stack = 0x20003A58, pc = 0x1FFE1905... + $ minicom -D /dev/ttyUSB1 -b 115200 -Debugging -========= +Flashing and Debugging via JTAG +=============================== -The PhyBOARD Polis can be debugged using a JTAG Debugger. -The easiest way to do that is to use a SEGGER JLink Debugger and Phytec's -``PEB-EVAL-01`` Shield, which can be directly connected to the JLink. -You can find the JLink Software package here: `JLink Software`_ +The PhyBOARD-Pollux can be debugged using a JTAG or SWD debug adapter. A Segger +JLink can be connected to the compatible JTAG connector on Phytec's +``PEB-EVAL-01`` shield. .. figure:: img/PEB-EVAL-01.jpg :alt: PEB-EVAL-01 @@ -231,37 +208,47 @@ You can find the JLink Software package here: `JLink Software`_ PEB-EVAL-01 -To debug efficiently you have to use multiple terminals: - -After connecting everything and building with west use this command while in -the directory of the program you build earlier to start a debug server: +Before flashing or debugging via a JTAG debug adapter, +the M7 core has to be switched on: .. code-block:: console - host$ west debugserver + u-boot=> bootaux 0x7e0000 -West automatically connects via the JLink to the Target and keeps open a -debug server. +Here is an example for the :zephyr:code-sample:`hello_world` application: -Use another terminal, start gdb, connect to target and load Zephyr on the -target: +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimx8mp_phyboard_pollux/mimx8ml8/m7 + :goals: flash + +The console should now show the output of the application: .. code-block:: console - host$ gdb-multiarch build/zephyr/zephyr.elf -tui - (gdb) targ rem :2331 - Remote debugging using :2331 - 0x1ffe0008 in _vector_table () - (gdb) mon halt - (gdb) mon reset - (gdb) c - Continuing. + *** Booting Zephyr OS build v3.7.0 *** + Hello World! mimx8mp_phyboard_pollux/mimx8ml8/m7 + +Starting a debug session is similar to flashing: -The program can be debugged using standard gdb techniques. +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimx8mp_phyboard_pollux/mimx8ml8/m7 + :goals: debug + +Starting the M7-Core from U-Boot and Linux +========================================== + +Loading binaries and starting the M7-Core is supported from Linux via remoteproc +or from U-boot by directly copying the firmware binary. Please check the +`phyCORE-i.MX 8M Plus BSP Manual`_ for more information. References ========== +- `i.MX 8M Plus Applications Processor Reference Manual`_ +- `phyCORE-i.MX 8M Plus BSP Manual`_ + .. _PHYTEC website: https://www.phytec.de/produkte/single-board-computer/phyboard-pollux/ @@ -270,3 +257,6 @@ References .. _JLink Software: https://www.segger.com/downloads/jlink/ + +.. _phyCORE-i.MX 8M Plus BSP Manual: + https://phytec.github.io/doc-bsp-yocto/bsp/imx8/imx8mp/imx8mp.html diff --git a/boards/phytec/phyboard_electra/doc/index.rst b/boards/phytec/phyboard_electra/doc/index.rst index 4fe9c5afd55..9af3400555d 100644 --- a/boards/phytec/phyboard_electra/doc/index.rst +++ b/boards/phytec/phyboard_electra/doc/index.rst @@ -84,7 +84,7 @@ GPIO ---- The phyCORE-AM64x has a heartbeat LED connected to gpio6. It's configured -to build and run the `basic/blinky` sample. +to build and run the :zephyr:code-sample:`blinky` sample. SD Card ******* @@ -104,16 +104,18 @@ The Linux running on the A53 uses the remoteproc framework to manage the M4F co- Therefore, the testing requires the binary to be copied to the SD card to allow the A53 cores to load it while booting using remoteproc. -To test the M4F core, we build the :ref:`hello_world` sample with the following command. +To test the M4F core, we build the :zephyr:code-sample:`hello_world` sample with the following command. .. zephyr-app-commands:: :board: phyboard_electra/am6442/m4 :zephyr-app: samples/hello_world :goals: build -This builds the program and the binary is present in the `build/zephyr` directory as `zephyr.elf`. +This builds the program and the binary is present in the :file:`build/zephyr` directory as +:file:`zephyr.elf`. -We now copy this binary onto the SD card in the `/lib/firmware` directory and name it as `am64-mcu-m4f0_0-fw`. +We now copy this binary onto the SD card in the :file:`/lib/firmware` directory and name it as +:file:`am64-mcu-m4f0_0-fw`. .. code-block:: console diff --git a/boards/phytec/phyboard_lyra/board.cmake b/boards/phytec/phyboard_lyra/board.cmake new file mode 100644 index 00000000000..5f42441db69 --- /dev/null +++ b/boards/phytec/phyboard_lyra/board.cmake @@ -0,0 +1,10 @@ +# PHYTEC phyBOARD-Lyra AM62x M4/A53 +# +# Copyright (c) 2024, PHYTEC Messtechnik GmbH +# +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_AM6234_M4) + board_runner_args(openocd "--no-init" "--no-halt" "--no-targets" "--gdb-client-port=3339") + include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +endif() diff --git a/boards/phytec/phyboard_lyra/doc/phyboard_lyra_am62xx_a53.rst b/boards/phytec/phyboard_lyra/doc/phyboard_lyra_am62xx_a53.rst index 410debfd9b7..9b6d2f42a3d 100644 --- a/boards/phytec/phyboard_lyra/doc/phyboard_lyra_am62xx_a53.rst +++ b/boards/phytec/phyboard_lyra/doc/phyboard_lyra_am62xx_a53.rst @@ -80,7 +80,7 @@ Building You can build an application in the usual way. Refer to :ref:`build_an_application` for more details. Here is an example for -:ref:`hello_world`. +:zephyr:code-sample:`hello_world`. .. zephyr-app-commands:: :board: phyboard_lyra/am6234/a53 diff --git a/boards/phytec/phyboard_lyra/doc/phyboard_lyra_am62xx_m4.rst b/boards/phytec/phyboard_lyra/doc/phyboard_lyra_am62xx_m4.rst index a8765c0fcc3..d0f61264890 100644 --- a/boards/phytec/phyboard_lyra/doc/phyboard_lyra_am62xx_m4.rst +++ b/boards/phytec/phyboard_lyra/doc/phyboard_lyra_am62xx_m4.rst @@ -96,16 +96,18 @@ The Linux running on the A53 uses the remoteproc framework to manage the M4F co- Therefore, the testing requires the binary to be copied to the SD card to allow the A53 cores to load it while booting using remoteproc. -To test the M4F core, we build the `hello_world` sample with the following command. +To test the M4F core, we build the :zephyr:code-sample:`hello_world` sample with the following command. .. code-block:: console # From the root of the Zephyr repository west build -p -b phyboard_lyra/am6234/m4 samples/hello_world -This builds the program and the binary is present in the `build/zephyr` directory as `zephyr.elf`. +This builds the program and the binary is present in the :file:`build/zephyr` directory as +:file:`zephyr.elf`. -We now copy this binary onto the SD card in the `/lib/firmware` directory and name it as `am62-mcu-m4f0_0-fw`. +We now copy this binary onto the SD card in the :file:`/lib/firmware` directory and name it as +:file:`am62-mcu-m4f0_0-fw`. .. code-block:: console @@ -131,6 +133,22 @@ The board should boot into Linux and the binary will run and print Hello world t port. +Debugging +********* + +The board is equipped with an XDS110 JTAG debugger. To debug a binary, utilize the ``debug`` build +target: + +.. zephyr-app-commands:: + :app: + :board: phyboard_lyra/am6234/m4 + :maybe-skip-config: + :goals: debug + +.. hint:: + To utilize this feature, you'll need OpenOCD version 0.12 or higher. Due to the possibility of + older versions being available in package feeds, it's advisable to `build OpenOCD from source`_. + .. _PHYTEC AM62x Product Page: https://www.phytec.com/product/phycore-am62x/ @@ -143,3 +161,6 @@ port. .. _phyBOARD SD Card Booting Essentials: https://docs.phytec.com/projects/yocto-phycore-am62x/en/bsp-yocto-ampliphy-am62x-pd23.2.1/bootingessentials/sdcard.html + +.. _build OpenOCD from source: + https://docs.u-boot.org/en/latest/board/ti/k3.html#building-openocd-from-source diff --git a/boards/phytec/phyboard_lyra/support/openocd.cfg b/boards/phytec/phyboard_lyra/support/openocd.cfg new file mode 100644 index 00000000000..39eed02c401 --- /dev/null +++ b/boards/phytec/phyboard_lyra/support/openocd.cfg @@ -0,0 +1,7 @@ +# PHYTEC phyBOARD-Lyra AM62x M4/A53 +# +# Copyright (c) 2024, PHYTEC Messtechnik GmbH +# +# SPDX-License-Identifier: Apache-2.0 + +source [find board/ti_am625evm.cfg] diff --git a/boards/phytec/reel_board/Kconfig b/boards/phytec/reel_board/Kconfig deleted file mode 100644 index 7c826262404..00000000000 --- a/boards/phytec/reel_board/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# reel board configuration - -# Copyright (c) 2018-2019 PHYTEC Messtechnik GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_REEL_BOARD diff --git a/boards/phytec/reel_board/doc/index.rst b/boards/phytec/reel_board/doc/index.rst index 79001a009e5..d468a6c559a 100644 --- a/boards/phytec/reel_board/doc/index.rst +++ b/boards/phytec/reel_board/doc/index.rst @@ -497,7 +497,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. @@ -528,7 +528,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/phytec/reel_board/dts/reel_board.dtsi b/boards/phytec/reel_board/dts/reel_board.dtsi index 028a5d86a78..daa61da1c56 100644 --- a/boards/phytec/reel_board/dts/reel_board.dtsi +++ b/boards/phytec/reel_board/dts/reel_board.dtsi @@ -4,6 +4,8 @@ * * SPDX-License-Identifier: Apache-2.0 */ + +#include #include "reel_board-pinctrl.dtsi" #include @@ -94,6 +96,10 @@ }; }; +®1 { + regulator-initial-mode = ; +}; + &uicr { gpio-as-nreset; }; @@ -174,46 +180,6 @@ arduino_spi: &spi3 { pinctrl-names = "default", "sleep"; }; -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000C000>; - }; - slot0_partition: partition@c000 { - label = "image-0"; - reg = <0x0000C000 0x00067000>; - }; - slot1_partition: partition@73000 { - label = "image-1"; - reg = <0x00073000 0x00067000>; - }; - scratch_partition: partition@da000 { - label = "image-scratch"; - reg = <0x000da000 0x0001e000>; - }; - - /* - * The flash starting at 0x000f8000 and ending at - * 0x000fffff is reserved for use by the application. - */ - - /* - * Storage partition will be used by FCB/LittleFS/NVS - * if enabled. - */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; - zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; diff --git a/boards/phytec/reel_board/reel_board.dts b/boards/phytec/reel_board/reel_board.dts index c20cf01c0ef..59c671bc121 100644 --- a/boards/phytec/reel_board/reel_board.dts +++ b/boards/phytec/reel_board/reel_board.dts @@ -46,6 +46,54 @@ pwm-led3 = &back_pwm_led; watchdog0 = &wdt0; }; + + mipi_dbi { + compatible = "zephyr,mipi-dbi-spi"; + spi-dev = <&spi1>; + reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + ssd16xx: ssd16xxfb@0 { + compatible = "gooddisplay,gdeh0213b1", "solomon,ssd1673"; + mipi-max-frequency = <4000000>; + reg = <0>; + width = <250>; + height = <122>; + busy-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + + full { + gdv = [10 0a]; + sdv = [19]; + vcom = <0xa8>; + border-waveform = <0x71>; + dummy-line = <0x1a>; + gate-line-width = <0x08>; + lut = [ + 22 55 AA 55 AA 55 AA 11 + 00 00 00 00 00 00 00 00 + 1E 1E 1E 1E 1E 1E 1E 1E + 01 00 00 00 00 + ]; + }; + + partial { + gdv = [10 0a]; + sdv = [19]; + vcom = <0xa8>; + border-waveform = <0x71>; + dummy-line = <0x1a>; + gate-line-width = <0x08>; + lut = [ + 18 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 0F 01 00 00 00 00 00 00 + 00 00 00 00 00 + ]; + }; + }; + }; }; &spi1 { @@ -56,44 +104,4 @@ pinctrl-0 = <&spi1_default>; pinctrl-1 = <&spi1_sleep>; pinctrl-names = "default", "sleep"; - ssd16xx: ssd16xxfb@0 { - compatible = "gooddisplay,gdeh0213b1", "solomon,ssd1673"; - spi-max-frequency = <4000000>; - reg = <0>; - width = <250>; - height = <122>; - reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; - dc-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; - busy-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - - full { - gdv = [10 0a]; - sdv = [19]; - vcom = <0xa8>; - border-waveform = <0x71>; - dummy-line = <0x1a>; - gate-line-width = <0x08>; - lut = [ - 22 55 AA 55 AA 55 AA 11 - 00 00 00 00 00 00 00 00 - 1E 1E 1E 1E 1E 1E 1E 1E - 01 00 00 00 00 - ]; - }; - - partial { - gdv = [10 0a]; - sdv = [19]; - vcom = <0xa8>; - border-waveform = <0x71>; - dummy-line = <0x1a>; - gate-line-width = <0x08>; - lut = [ - 18 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 0F 01 00 00 00 00 00 00 - 00 00 00 00 00 - ]; - }; - }; }; diff --git a/boards/phytec/reel_board/reel_board_1.yaml b/boards/phytec/reel_board/reel_board_1.yaml index 07b5087b6c6..b357f545511 100644 --- a/boards/phytec/reel_board/reel_board_1.yaml +++ b/boards/phytec/reel_board/reel_board_1.yaml @@ -13,7 +13,6 @@ supported: - spi - gpio - usb_device - - usb_cdc - ble - pwm - arduino_i2c diff --git a/boards/phytec/reel_board/reel_board_nrf52840_2.overlay b/boards/phytec/reel_board/reel_board_nrf52840_2.overlay index b6652cbf4e8..1e7c0ff529d 100644 --- a/boards/phytec/reel_board/reel_board_nrf52840_2.overlay +++ b/boards/phytec/reel_board/reel_board_nrf52840_2.overlay @@ -27,6 +27,91 @@ aliases { watchdog0 = &wdt0; }; + + mipi_dbi { + compatible = "zephyr,mipi-dbi-spi"; + spi-dev = <&spi1>; + reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + ssd16xx: ssd16xxfb@0 { + compatible = "gooddisplay,gdeh0213b72", "solomon,ssd1675a"; + mipi-max-frequency = <4000000>; + reg = <0>; + width = <250>; + height = <122>; + busy-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + + full { + gdv = [15]; + sdv = [41 a8 32]; + vcom = <0x26>; + border-waveform = <0x03>; + dummy-line = <0x30>; + gate-line-width = <0x0a>; + lut = [ + /* + * Waveform Composition + * + * There are 7 Voltage Source (VS) Level groups + * n = {0,1,2...6}, each group contains + * 4 phases x = {A,B,C,D}. + * 2 bits represent the voltage in a phase: + * 00 – VSS, 01 – VSH1, 10 – VSL, 11 - VSH2 + * + * For example 0x80 represents sequence VSL-VSS-VSS-VSS, + */ + 80 60 40 00 00 00 00 /* LUT0: BB: VS 0..6 */ + 10 60 20 00 00 00 00 /* LUT1: BW: VS 0..6 */ + 80 60 40 00 00 00 00 /* LUT2: WB: VS 0..6 */ + 10 60 20 00 00 00 00 /* LUT3: WW: VS 0..6 */ + 00 00 00 00 00 00 00 /* LUT4: VCOM: VS 0..6 */ + /* + * TPnx determines the length of each phase, + * and RPn repeat count of a sequence. + * TPnA, TPnB, TPnC, TPnD, RPn + * + * For example TP0A=3, TP0B=3, and RP0=2: + * VS sequence : VSL-VSS-VSS-VSS + * number of Gate Pulses (length) : 3 3 0 0 + * repeat count : 2 + */ + 03 03 00 00 02 /* TP0A TP0B TP0C TP0D RP0 */ + 09 09 00 00 02 /* TP1A TP1B TP1C TP1D RP1 */ + 03 03 00 00 02 /* TP2A TP2B TP2C TP2D RP2 */ + 00 00 00 00 00 /* TP3A TP3B TP3C TP3D RP3 */ + 00 00 00 00 00 /* TP4A TP4B TP4C TP4D RP4 */ + 00 00 00 00 00 /* TP5A TP5B TP5C TP5D RP5 */ + 00 00 00 00 00 /* TP6A TP6B TP6C TP6D RP6 */ + ]; + }; + + partial { + gdv = [15]; + sdv = [41 a8 32]; + vcom = <0x26>; + border-waveform = <0x01>; + dummy-line = <0x30>; + gate-line-width = <0x0a>; + lut = [ + 00 00 00 00 00 00 00 /* LUT0: BB: VS0..6 */ + 80 00 00 00 00 00 00 /* LUT1: BW: VS0..6 */ + 40 00 00 00 00 00 00 /* LUT2: WB: VS0..6 */ + 80 00 00 00 00 00 00 /* LUT3: WW: VS0..6 */ + 00 00 00 00 00 00 00 /* LUT4: VCOM: VS0..6 */ + 0A 00 00 00 04 /* TP0A TP0B TP0C TP0D RP0 */ + 00 00 00 00 00 /* TP1A TP1B TP1C TP1D RP1 */ + 00 00 00 00 00 /* TP2A TP2B TP2C TP2D RP2 */ + 00 00 00 00 00 /* TP3A TP3B TP3C TP3D RP3 */ + 00 00 00 00 00 /* TP4A TP4B TP4C TP4D RP4 */ + 00 00 00 00 00 /* TP5A TP5B TP5C TP5D RP5 */ + 00 00 00 00 00 /* TP6A TP6B TP6C TP6D RP6 */ + ]; + }; + }; + }; }; &spi1 { @@ -37,81 +122,4 @@ pinctrl-0 = <&spi1_default>; pinctrl-1 = <&spi1_sleep>; pinctrl-names = "default", "sleep"; - ssd16xx: ssd16xxfb@0 { - compatible = "gooddisplay,gdeh0213b72", "solomon,ssd1675a"; - spi-max-frequency = <4000000>; - reg = <0>; - width = <250>; - height = <122>; - reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; - dc-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; - busy-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - - full { - gdv = [15]; - sdv = [41 a8 32]; - vcom = <0x26>; - border-waveform = <0x03>; - dummy-line = <0x30>; - gate-line-width = <0x0a>; - lut = [ - /* - * Waveform Composition - * - * There are 7 Voltage Source (VS) Level groups - * n = {0,1,2...6}, each group contains - * 4 phases x = {A,B,C,D}. - * 2 bits represent the voltage in a phase: - * 00 – VSS, 01 – VSH1, 10 – VSL, 11 - VSH2 - * - * For example 0x80 represents sequence VSL-VSS-VSS-VSS, - */ - 80 60 40 00 00 00 00 /* LUT0: BB: VS 0..6 */ - 10 60 20 00 00 00 00 /* LUT1: BW: VS 0..6 */ - 80 60 40 00 00 00 00 /* LUT2: WB: VS 0..6 */ - 10 60 20 00 00 00 00 /* LUT3: WW: VS 0..6 */ - 00 00 00 00 00 00 00 /* LUT4: VCOM: VS 0..6 */ - /* - * TPnx determines the length of each phase, - * and RPn repeat count of a sequence. - * TPnA, TPnB, TPnC, TPnD, RPn - * - * For example TP0A=3, TP0B=3, and RP0=2: - * VS sequence : VSL-VSS-VSS-VSS - * number of Gate Pulses (length) : 3 3 0 0 - * repeat count : 2 - */ - 03 03 00 00 02 /* TP0A TP0B TP0C TP0D RP0 */ - 09 09 00 00 02 /* TP1A TP1B TP1C TP1D RP1 */ - 03 03 00 00 02 /* TP2A TP2B TP2C TP2D RP2 */ - 00 00 00 00 00 /* TP3A TP3B TP3C TP3D RP3 */ - 00 00 00 00 00 /* TP4A TP4B TP4C TP4D RP4 */ - 00 00 00 00 00 /* TP5A TP5B TP5C TP5D RP5 */ - 00 00 00 00 00 /* TP6A TP6B TP6C TP6D RP6 */ - ]; - }; - - partial { - gdv = [15]; - sdv = [41 a8 32]; - vcom = <0x26>; - border-waveform = <0x01>; - dummy-line = <0x30>; - gate-line-width = <0x0a>; - lut = [ - 00 00 00 00 00 00 00 /* LUT0: BB: VS0..6 */ - 80 00 00 00 00 00 00 /* LUT1: BW: VS0..6 */ - 40 00 00 00 00 00 00 /* LUT2: WB: VS0..6 */ - 80 00 00 00 00 00 00 /* LUT3: WW: VS0..6 */ - 00 00 00 00 00 00 00 /* LUT4: VCOM: VS0..6 */ - 0A 00 00 00 04 /* TP0A TP0B TP0C TP0D RP0 */ - 00 00 00 00 00 /* TP1A TP1B TP1C TP1D RP1 */ - 00 00 00 00 00 /* TP2A TP2B TP2C TP2D RP2 */ - 00 00 00 00 00 /* TP3A TP3B TP3C TP3D RP3 */ - 00 00 00 00 00 /* TP4A TP4B TP4C TP4D RP4 */ - 00 00 00 00 00 /* TP5A TP5B TP5C TP5D RP5 */ - 00 00 00 00 00 /* TP6A TP6B TP6C TP6D RP6 */ - ]; - }; - }; }; diff --git a/boards/phytec/reel_board/reel_board_nrf52840_2.yaml b/boards/phytec/reel_board/reel_board_nrf52840_2.yaml index 7112c3fde8e..e98f366b969 100644 --- a/boards/phytec/reel_board/reel_board_nrf52840_2.yaml +++ b/boards/phytec/reel_board/reel_board_nrf52840_2.yaml @@ -13,7 +13,6 @@ supported: - spi - gpio - usb_device - - usb_cdc - ble - pwm - arduino_i2c diff --git a/boards/pine64/pinetime_devkit0/pinetime_devkit0.dts b/boards/pine64/pinetime_devkit0/pinetime_devkit0.dts index 207c8934880..7bdf52d79e4 100644 --- a/boards/pine64/pinetime_devkit0/pinetime_devkit0.dts +++ b/boards/pine64/pinetime_devkit0/pinetime_devkit0.dts @@ -12,6 +12,7 @@ #include #include "pinetime_devkit0-pinctrl.dtsi" #include +#include / { model = "Pine64 PineTime DevKit0"; @@ -77,6 +78,42 @@ output-ohms = <1000000>; full-ohms = <(1000000 + 1000000)>; }; + + mipi_dbi { + compatible = "zephyr,mipi-dbi-spi"; + spi-dev = <&spi1>; + dc-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; /* DET */ + reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; /* RESX reset */ + write-only; + #address-cells = <1>; + #size-cells = <0>; + /* Sitronix ST7789V LCD */ + st7789v: st7789v@1 { + compatible = "sitronix,st7789v"; + reg = <1>; + mipi-max-frequency = <8000000>; /* 8MHz */ + width = <240>; + height = <240>; + x-offset = <0>; + y-offset = <0>; + vcom = <0x19>; + gctrl = <0x35>; + vrhs = <0x12>; + vdvs = <0x20>; + mdac = <0x00>; + gamma = <0x01>; + colmod = <0x05>; + lcm = <0x2c>; + porch-param = [0c 0c 00 33 33]; + cmd2en-param = [5a 69 02 01]; + pwctrl1-param = [a4 a1]; + pvgam-param = [D0 04 0D 11 13 2B 3F 54 4C 18 0D 0B 1F 23]; + nvgam-param = [D0 04 0C 11 13 2C 3F 44 51 2F 1F 1F 20 23]; + ram-param = [00 F0]; + rgb-param = [CD 08 14]; + mipi-mode = ; + }; + }; }; &adc { @@ -178,34 +215,6 @@ }; }; }; - - /* Sitronix ST7789V LCD */ - st7789v: st7789v@1 { - compatible = "sitronix,st7789v"; - reg = <1>; - spi-max-frequency = <8000000>; /* 8MHz */ - cmd-data-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; /* DET */ - reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; /* RESX reset */ - width = <240>; - height = <240>; - x-offset = <0>; - y-offset = <0>; - vcom = <0x19>; - gctrl = <0x35>; - vrhs = <0x12>; - vdvs = <0x20>; - mdac = <0x00>; - gamma = <0x01>; - colmod = <0x05>; - lcm = <0x2c>; - porch-param = [0c 0c 00 33 33]; - cmd2en-param = [5a 69 02 01]; - pwctrl1-param = [a4 a1]; - pvgam-param = [D0 04 0D 11 13 2B 3F 54 4C 18 0D 0B 1F 23]; - nvgam-param = [D0 04 0C 11 13 2C 3F 44 51 2F 1F 1F 20 23]; - ram-param = [00 F0]; - rgb-param = [CD 08 14]; - }; }; &flash0 { diff --git a/boards/pjrc/teensy4/doc/index.rst b/boards/pjrc/teensy4/doc/index.rst index b02acd16616..f9644699d68 100644 --- a/boards/pjrc/teensy4/doc/index.rst +++ b/boards/pjrc/teensy4/doc/index.rst @@ -146,9 +146,9 @@ Pin mappings from Teensy to MIMXRT1062 SoC. +-----+------------+-------------------------------------+ | 25 | AD_B0_13 | GPIO1_13 / UART1_RX / I2C4_SDA | +-----+------------+-------------------------------------+ -| 26 | AD_B1_14 | GPIO1_30 | +| 26 | AD_B1_14 | GPIO1_30 / SPI3_MOSI | +-----+------------+-------------------------------------+ -| 27 | AD_B1_15 | GPIO1_31 | +| 27 | AD_B1_15 | GPIO1_31 / SPI3_SCK | +-----+------------+-------------------------------------+ | 28 | EMC_32 | GPIO3_18 / UART7_RX | +-----+------------+-------------------------------------+ @@ -190,9 +190,9 @@ Only Teensy 4.1: +-----+------------+-------------------------------------+ | 37 | B1_03 | GPIO2_19 | +-----+------------+-------------------------------------+ -| 38 | AD_B1_12 | GPIO1_28 | +| 38 | AD_B1_12 | GPIO1_28 / SPI3_CS | +-----+------------+-------------------------------------+ -| 39 | AD_B1_13 | GPIO1_29 | +| 39 | AD_B1_13 | GPIO1_29 / SPI3_MISO | +-----+------------+-------------------------------------+ | 40 | AD_B1_04 | GPIO1_20 | +-----+------------+-------------------------------------+ diff --git a/boards/pjrc/teensy4/teensy4-pinctrl.dtsi b/boards/pjrc/teensy4/teensy4-pinctrl.dtsi index 4d9964bb521..430020f5098 100644 --- a/boards/pjrc/teensy4/teensy4-pinctrl.dtsi +++ b/boards/pjrc/teensy4/teensy4-pinctrl.dtsi @@ -129,9 +129,9 @@ pinmux_lpspi3: pinmux_lpspi3 { group0 { pinmux = <&iomuxc_gpio_ad_b1_12_lpspi3_pcs0>, - <&iomuxc_gpio_ad_b0_00_lpspi3_sck>, - <&iomuxc_gpio_ad_b0_02_lpspi3_sdi>, - <&iomuxc_gpio_ad_b0_01_lpspi3_sdo>; + <&iomuxc_gpio_ad_b1_15_lpspi3_sck>, + <&iomuxc_gpio_ad_b1_13_lpspi3_sdi>, + <&iomuxc_gpio_ad_b1_14_lpspi3_sdo>; drive-strength = "r0-6"; slew-rate = "slow"; nxp,speed = "100-mhz"; diff --git a/boards/qemu/x86/CMakeLists.txt b/boards/qemu/x86/CMakeLists.txt index 1f37a49df8c..1ee70f9f48a 100644 --- a/boards/qemu/x86/CMakeLists.txt +++ b/boards/qemu/x86/CMakeLists.txt @@ -5,7 +5,7 @@ if(CONFIG_BOARD_QEMU_X86_64 AND CONFIG_BUILD_OUTPUT_EFI) set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py -c ${CMAKE_C_COMPILER} - -i ${ZEPHYR_BASE}/include + -i ${ZEPHYR_BASE}/include ${PROJECT_BINARY_DIR}/include/generated -o ${CMAKE_OBJCOPY} -f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf $<$:--verbose> diff --git a/boards/qemu/x86/qemu_x86_tiny.ld b/boards/qemu/x86/qemu_x86_tiny.ld index 623a11fb416..548e5fbdcb0 100644 --- a/boards/qemu/x86/qemu_x86_tiny.ld +++ b/boards/qemu/x86/qemu_x86_tiny.ld @@ -6,7 +6,7 @@ */ #include -#include +#include #include #include #include @@ -25,7 +25,7 @@ * the same as its physical location, although an identity mapping for RAM * is still supported by setting CONFIG_KERNEL_VM_BASE=CONFIG_SRAM_BASE_ADDRESS. */ -#ifdef Z_VM_KERNEL +#ifdef K_MEM_IS_VM_KERNEL #define KERNEL_BASE_ADDR \ (CONFIG_KERNEL_VM_BASE + CONFIG_KERNEL_VM_OFFSET) @@ -55,7 +55,7 @@ MEMORY { -#if defined(Z_VM_KERNEL) +#if defined(K_MEM_IS_VM_KERNEL) ROM (rx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = PHYS_RAM_AVAIL #endif RAM (wx) : ORIGIN = KERNEL_BASE_ADDR, LENGTH = KERNEL_RAM_SIZE @@ -75,7 +75,7 @@ MEMORY IDT_LIST : ORIGIN = 0xFFFF1000, LENGTH = 2K } -#if defined(Z_VM_KERNEL) +#if defined(K_MEM_IS_VM_KERNEL) #define ROMABLE_REGION ROM #define RAMABLE_REGION RAM #else @@ -245,7 +245,7 @@ MEMORY *mpsc_pbuf.c.obj(.##lsect) \ *mpsc_pbuf.c.obj(.##lsect.*) -epoint = Z_MEM_PHYS_ADDR(CONFIG_KERNEL_ENTRY); +epoint = K_MEM_PHYS_ADDR(CONFIG_KERNEL_ENTRY); ENTRY(epoint) /* SECTIONS definitions */ @@ -254,6 +254,10 @@ SECTIONS #include +#ifdef CONFIG_LLEXT +#include +#endif + /DISCARD/ : { *(.plt) @@ -416,6 +420,10 @@ SECTIONS lnkr_pinned_rodata_start = .; #include +/* Located in generated directory. This file is populated by calling + * zephyr_linker_sources(ROM_SECTIONS ...). Useful for grouping iterable RO structs. + */ +#include #include SECTION_PROLOGUE(pinned.rodata,,) @@ -645,6 +653,10 @@ SECTIONS #ifndef CONFIG_LINKER_USE_PINNED_SECTION #include +/* Located in generated directory. This file is populated by calling + * zephyr_linker_sources(ROM_SECTIONS ...). Useful for grouping iterable RO structs. + */ +#include #include #endif diff --git a/boards/qorvo/decawave_dwm1001_dev/Kconfig b/boards/qorvo/decawave_dwm1001_dev/Kconfig deleted file mode 100644 index 6fe393cd80c..00000000000 --- a/boards/qorvo/decawave_dwm1001_dev/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# DecaWave DWM1001 DEV board configuration - -# Copyright (c) 2019 Stéphane D'Alu -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_DECAWAVE_DWM1001_DEV diff --git a/boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev.dts b/boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev.dts index a1c415fc299..2e33c21082d 100644 --- a/boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev.dts +++ b/boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev.dts @@ -80,6 +80,10 @@ }; +® { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; diff --git a/boards/qorvo/decawave_dwm1001_dev/doc/index.rst b/boards/qorvo/decawave_dwm1001_dev/doc/index.rst index 4699de8c381..93966edb739 100644 --- a/boards/qorvo/decawave_dwm1001_dev/doc/index.rst +++ b/boards/qorvo/decawave_dwm1001_dev/doc/index.rst @@ -31,7 +31,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/quicklogic/qomu/doc/index.rst b/boards/quicklogic/qomu/doc/index.rst index 7eff3a26e8e..57505aebe91 100644 --- a/boards/quicklogic/qomu/doc/index.rst +++ b/boards/quicklogic/qomu/doc/index.rst @@ -41,7 +41,7 @@ Below are steps to run Qomu sample application: #. Build the sample in an usual way: .. zephyr-app-commands:: - :zephyr-app: samples/boards/qomu + :zephyr-app: samples/boards/quicklogic/qomu :board: qomu :goals: build diff --git a/boards/rak/rak11720/Kconfig.rak11720 b/boards/rak/rak11720/Kconfig.rak11720 new file mode 100644 index 00000000000..a91bc261d33 --- /dev/null +++ b/boards/rak/rak11720/Kconfig.rak11720 @@ -0,0 +1,6 @@ +# Copyright (c) 2024 RAKwireless Technology Co., Ltd. +# Sercan Erat +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RAK11720 + select SOC_APOLLO3_BLUE diff --git a/boards/rak/rak11720/board.cmake b/boards/rak/rak11720/board.cmake new file mode 100644 index 00000000000..026b5a25115 --- /dev/null +++ b/boards/rak/rak11720/board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2024 RAKwireless Technology Co., Ltd. +# Sercan Erat +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=AMA3B1KK-KBR" "--iface=swd" "--speed=1000") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/rak/rak11720/board.yml b/boards/rak/rak11720/board.yml new file mode 100644 index 00000000000..827beef7e76 --- /dev/null +++ b/boards/rak/rak11720/board.yml @@ -0,0 +1,5 @@ +board: + name: rak11720 + vendor: rakwireless + socs: + - name: apollo3_blue diff --git a/boards/rak/rak11720/doc/img/rak11720.webp b/boards/rak/rak11720/doc/img/rak11720.webp new file mode 100644 index 00000000000..4c513024c78 Binary files /dev/null and b/boards/rak/rak11720/doc/img/rak11720.webp differ diff --git a/boards/rak/rak11720/doc/index.rst b/boards/rak/rak11720/doc/index.rst new file mode 100644 index 00000000000..238ba6d8303 --- /dev/null +++ b/boards/rak/rak11720/doc/index.rst @@ -0,0 +1,122 @@ +.. _rak11720: + +RAK11720 +######## + +The RAK11720 is a WisBlock Core module for RAK WisBlock. +It is based on the powerful ultra-low power Apollo3 Blue SoC (AMA3B1KK-KBR-B0) +from Ambiq together with a Semtech SX1262 LoRa® transceiver. + +The AMA3B1KK-KBR-B0 has an integrated Bluetooth Low Energy transceiver +that enhances the communication capabilities. The RAK11720 stamp module +comes in the same size and footprint as our RAK3172 module which gives +you the opportunity to enhance your existing designs +with BLE without designing a new PCB. + +.. image:: img/rak11720.webp + :align: center + :alt: RAK11720 + +Hardware +******** + +The easiset way to use a RAK11720, is the WisBlock Modular system. +A WisBlock Base board (RAK19007) which provides the power +supply and programming/debug interface is the base to plug a +RAK11722 (WisBlock Core module with the RAK11720) in. + +- Apollo3 Blue SoC with up to 96 MHz operating frequency +- ARM® Cortex® M4F core +- 16 kB 2-way Associative/Direct-Mapped Cache per core +- Up to 1 MB of flash memory for code/data +- Up to 384 KB of low leakage / low power RAM for code/data +- Integrated Bluetooth 5 Low-energy controller +- Semtech SX1262 low power high range LoRa transceiver +- iPEX connectors for the LORA antenna and BLE antenna. +- 2 user LEDs on RAK19007 WisBlock Base board +- Powered by either Micro USB, 3.7V rechargeable battery or a 5V Solar Panel Port + +For more information about the RAK11720 stamp module: + +- `WisDuo RAK11720 Website`_ +- `WisBlock RAK11722 Website`_ + +Supported Features +================== + +The RAK11720 module configuration supports the following hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+----------------------+ +| STIMER | on-chip | stimer | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ +| RADIO | on-chip | bluetooth | ++-----------+------------+----------------------+ +| RADIO | on-board | LoRa (SX1262) | ++-----------+------------+----------------------+ + +The default configuration can be found in the defconfig file: +``boards/rak/rak11720/rak11720_defconfig``. + +Programming and Debugging +========================= + +The RAK11720 board shall be connected to a Segger Embedded Debugger Unit +`J-Link OB `_. This provides a debug +interface to the Apollo3 Blue chip. You can use JLink to communicate with +the Apollo3 Blue. + +Flashing an application +----------------------- + +Connect your device to your host computer using the JLINK USB port. +The sample application :zephyr:code-sample:`hello_world` is used for this example. +Build the Zephyr kernel and application, then flash it to the device: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rak11720 + :goals: flash + +.. note:: + ``west flash`` requires `SEGGER J-Link software`_ and `pylink`_ Python module + to be installed on you host computer. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you should be able to see on the corresponding Serial Port +the following message: + +.. code-block:: console + + Hello World! rak11720/apollo3_blue + +.. _WisDuo RAK11720 Website: + https://docs.rakwireless.com/Product-Categories/WisDuo/RAK11720-Module/Overview/#product-description + +.. _WisBlock RAK11722 Website: + https://docs.rakwireless.com/Product-Categories/WisBlock/RAK11722/Overview/#product-description + +.. _SEGGER J-Link software: + https://www.segger.com/downloads/jlink + +.. _pylink: + https://github.com/Square/pylink diff --git a/boards/rak/rak11720/rak11720.dts b/boards/rak/rak11720/rak11720.dts new file mode 100644 index 00000000000..4f4f75d7ff2 --- /dev/null +++ b/boards/rak/rak11720/rak11720.dts @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2024 RAKwireless Technology Co., Ltd. + * Sercan Erat + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include "rak11720_apollo3-pinctrl.dtsi" + +/ { + model = "RAKwireless RAK11720 WisBlock LPWAN Module"; + compatible = "ambiq,rak11720"; + + chosen { + zephyr,itcm = &tcm; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,uart-pipe = &uart0; + zephyr,flash-controller = &flash; + zephyr,bt_hci = &bt_hci_apollo; + }; + + aliases { + watchdog0 = &wdt0; + led0 = &blue_led; + led1 = &green_led; + lora0 = &lora; + }; + + leds { + compatible = "gpio-leds"; + blue_led: led_2 { + gpios = <&gpio32_63 13 GPIO_ACTIVE_HIGH>; + label = "Blue LED"; + }; + green_led: led_1 { + gpios = <&gpio32_63 12 GPIO_ACTIVE_HIGH>; + label = "Green LED"; + }; + }; +}; + +&flash0 { + erase-block-size = <8192>; + write-block-size = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Set 16KB of storage at the end of the 976KB of flash */ + storage_partition: partition@f0000 { + label = "storage"; + reg = <0x000f0000 0x4000>; + }; + }; +}; + +&bleif { + pinctrl-0 = <&bleif_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart0 { + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&i2c2 { + compatible = "ambiq,i2c"; + pinctrl-0 = <&i2c2_default>; + pinctrl-names = "default"; + clock-frequency = ; + status = "okay"; +}; + +&spi0 { + compatible = "ambiq,spi"; + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; + cs-gpios = <&gpio0_31 1 GPIO_ACTIVE_LOW>; + clock-frequency = ; + status = "okay"; +}; + +&spi1 { + compatible = "ambiq,spi"; + status = "okay"; + pinctrl-0 = <&spi1_default>; + pinctrl-names = "default"; + clock-frequency = ; + cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>; + + lora: lora@0 { + compatible = "semtech,sx1262"; + reg = <0>; + reset-gpios = <&gpio0_31 17 GPIO_ACTIVE_LOW>; + busy-gpios = <&gpio0_31 16 GPIO_ACTIVE_HIGH>; + dio1-gpios = <&gpio0_31 15 GPIO_ACTIVE_HIGH>; + antenna-enable-gpios = <&gpio0_31 18 GPIO_ACTIVE_LOW>; + dio2-tx-enable; + dio3-tcxo-voltage = ; + tcxo-power-startup-delay-ms = <5>; + spi-max-frequency = ; + }; +}; + +&counter0 { + status = "okay"; +}; + +&counter1 { + status = "okay"; +}; + +&counter2 { + status = "okay"; +}; + +&counter3 { + status = "okay"; +}; + +&counter4 { + status = "okay"; +}; + +&counter5 { + status = "okay"; +}; + +&counter6 { + status = "okay"; +}; + +&counter7 { + status = "okay"; +}; + +&gpio0_31 { + status = "okay"; +}; + +&gpio32_63 { + status = "okay"; +}; diff --git a/boards/rak/rak11720/rak11720.yaml b/boards/rak/rak11720/rak11720.yaml new file mode 100644 index 00000000000..43efd09ce87 --- /dev/null +++ b/boards/rak/rak11720/rak11720.yaml @@ -0,0 +1,21 @@ +identifier: rak11720 +name: RAK11720 +type: mcu +arch: arm +ram: 384 +flash: 976 +toolchain: + - zephyr + - gnuarmemb +supported: + - uart + - watchdog + - counter + - gpio + - spi + - i2c + - lora +testing: + ignore_tags: + - net +vendor: rak diff --git a/boards/rak/rak11720/rak11720_apollo3-pinctrl.dtsi b/boards/rak/rak11720/rak11720_apollo3-pinctrl.dtsi new file mode 100644 index 00000000000..dbfd0ab8796 --- /dev/null +++ b/boards/rak/rak11720/rak11720_apollo3-pinctrl.dtsi @@ -0,0 +1,126 @@ +/* + * Copyright (c) 2024 RAKwireless Technology Co., Ltd. + * Sercan Erat + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + i2c0_default: i2c0_default { + group1 { + pinmux = , ; + drive-open-drain; + drive-strength = "0.5"; + bias-pull-up; + }; + }; + i2c1_default: i2c1_default { + group1 { + pinmux = , ; + drive-open-drain; + drive-strength = "0.5"; + bias-pull-up; + }; + }; + i2c2_default: i2c2_default { + group1 { + pinmux = , ; + drive-open-drain; + drive-strength = "0.5"; + bias-pull-up; + }; + }; + i2c3_default: i2c3_default { + group1 { + pinmux = , ; + drive-open-drain; + drive-strength = "0.5"; + bias-pull-up; + }; + }; + i2c4_default: i2c4_default { + group1 { + pinmux = , ; + drive-open-drain; + drive-strength = "0.5"; + bias-pull-up; + }; + }; + i2c5_default: i2c5_default { + group1 { + pinmux = , ; + drive-open-drain; + drive-strength = "0.5"; + bias-pull-up; + }; + }; + + spi0_default: spi0_default { + group1 { + pinmux = , , ; + }; + }; + spi1_default: spi1_default { + group1 { + pinmux = , , ; + }; + }; + spi2_default: spi2_default { + group1 { + pinmux = , , ; + }; + }; + spi3_default: spi3_default { + group1 { + pinmux = , , ; + }; + }; + spi4_default: spi4_default { + group1 { + pinmux = , , ; + }; + }; + spi5_default: spi5_default { + group1 { + pinmux = , , ; + }; + }; + + mspi0_default: mspi0_default{ + group1 { + pinmux = , + , + , + , + ; + }; + group2 { + pinmux = ; + drive-push-pull; + drive-strength = "0.5"; + ambiq,iom-nce-module = <0>; + ambiq,iom-num = <6>; + }; + }; + + bleif_default: bleif_default{ + group1 { + pinmux = , + , + , + , + , + ; + }; + }; +}; diff --git a/boards/rak/rak11720/rak11720_defconfig b/boards/rak/rak11720/rak11720_defconfig new file mode 100644 index 00000000000..33690ff2720 --- /dev/null +++ b/boards/rak/rak11720/rak11720_defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 RAKwireless Technology Co., Ltd. +# Sercan Erat +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/rak/rak4631/Kconfig b/boards/rak/rak4631/Kconfig deleted file mode 100644 index b313c721fb6..00000000000 --- a/boards/rak/rak4631/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -# RAKWIRELESS RAK4631 Board configuration - -# Copyright (c) 2024 Kelly Helmut Lord -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RAK4631 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF52X_HV - default y - -endif # BOARD_RAK4631 diff --git a/boards/rak/rak4631/doc/index.rst b/boards/rak/rak4631/doc/index.rst index ffa39ca8265..14c6c912976 100644 --- a/boards/rak/rak4631/doc/index.rst +++ b/boards/rak/rak4631/doc/index.rst @@ -121,7 +121,7 @@ Flashing - Stop bits: 1 #. Connect the RAK4631 board to your host computer using the USB debug port. - Then build and flash the :ref:`hello_world` application. + Then build and flash the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -134,7 +134,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/rak/rak4631/rak4631_nrf52840.dts b/boards/rak/rak4631/rak4631_nrf52840.dts index 454c4bb84b1..de485c86bc1 100644 --- a/boards/rak/rak4631/rak4631_nrf52840.dts +++ b/boards/rak/rak4631/rak4631_nrf52840.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include #include "rak4631_nrf52840-pinctrl.dtsi" @@ -19,9 +20,6 @@ zephyr,uart-mcumgr = &uart1; zephyr,bt-mon-uart = &uart1; zephyr,bt-c2h-uart = &uart1; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; }; leds { @@ -44,6 +42,14 @@ }; }; +®0 { + status = "okay"; +}; + +®1 { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; @@ -129,46 +135,6 @@ pinctrl-names = "default", "sleep"; }; -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000C000>; - }; - slot0_partition: partition@c000 { - label = "image-0"; - reg = <0x0000C000 0x00067000>; - }; - slot1_partition: partition@73000 { - label = "image-1"; - reg = <0x00073000 0x00067000>; - }; - scratch_partition: partition@da000 { - label = "image-scratch"; - reg = <0x000da000 0x0001e000>; - }; - - /* - * The flash starting at 0x000f8000 and ending at - * 0x000fffff is reserved for use by the application. - */ - - /* - * Storage partition will be used by FCB/LittleFS/NVS - * if enabled. - */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; - zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; diff --git a/boards/rak/rak4631/rak4631_nrf52840.yaml b/boards/rak/rak4631/rak4631_nrf52840.yaml index 42c638ac35c..f8b3e235826 100644 --- a/boards/rak/rak4631/rak4631_nrf52840.yaml +++ b/boards/rak/rak4631/rak4631_nrf52840.yaml @@ -15,7 +15,6 @@ supported: - gpio - i2c - pwm - - usb_cdc - usb_device - watchdog - lora diff --git a/boards/rak/rak5010/board.cmake b/boards/rak/rak5010/board.cmake index 1bf111421e2..d91b58c847d 100644 --- a/boards/rak/rak5010/board.cmake +++ b/boards/rak/rak5010/board.cmake @@ -7,3 +7,4 @@ include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd-nrf5.board.cmake) +include(${ZEPHYR_BASE}/boards/common/blackmagicprobe.board.cmake) diff --git a/boards/rak/rak5010/doc/index.rst b/boards/rak/rak5010/doc/index.rst index fac00cf72df..851d8924842 100644 --- a/boards/rak/rak5010/doc/index.rst +++ b/boards/rak/rak5010/doc/index.rst @@ -126,7 +126,7 @@ Flashing - Stop bits: 1 #. Connect the RAK5010 board to your host computer using the USB debug port. - Then build and flash the :ref:`hello_world` application. + Then build and flash the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -139,7 +139,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/rak/rak5010/rak5010_nrf52840.dts b/boards/rak/rak5010/rak5010_nrf52840.dts index eeba2a5e20b..22d95ed90ba 100644 --- a/boards/rak/rak5010/rak5010_nrf52840.dts +++ b/boards/rak/rak5010/rak5010_nrf52840.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include "rak5010_nrf52840-pinctrl.dtsi" / { @@ -18,9 +19,6 @@ zephyr,uart-mcumgr = &uart1; zephyr,bt-mon-uart = &uart1; zephyr,bt-c2h-uart = &uart1; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; }; leds { @@ -125,46 +123,6 @@ }; }; -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000C000>; - }; - slot0_partition: partition@c000 { - label = "image-0"; - reg = <0x0000C000 0x00067000>; - }; - slot1_partition: partition@73000 { - label = "image-1"; - reg = <0x00073000 0x00067000>; - }; - scratch_partition: partition@da000 { - label = "image-scratch"; - reg = <0x000da000 0x0001e000>; - }; - - /* - * The flash starting at 0x000f8000 and ending at - * 0x000fffff is reserved for use by the application. - */ - - /* - * Storage partition will be used by FCB/LittleFS/NVS - * if enabled. - */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; - zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; diff --git a/boards/rak/rak5010/rak5010_nrf52840.yaml b/boards/rak/rak5010/rak5010_nrf52840.yaml index 21b8e122970..2b947436b26 100644 --- a/boards/rak/rak5010/rak5010_nrf52840.yaml +++ b/boards/rak/rak5010/rak5010_nrf52840.yaml @@ -15,7 +15,6 @@ supported: - gpio - i2c - pwm - - usb_cdc - usb_device - watchdog vendor: rak diff --git a/boards/raspberrypi/rpi_5/doc/index.rst b/boards/raspberrypi/rpi_5/doc/index.rst index c22c695a405..fd0ad27df0a 100644 --- a/boards/raspberrypi/rpi_5/doc/index.rst +++ b/boards/raspberrypi/rpi_5/doc/index.rst @@ -1,4 +1,4 @@ -.. rpi_5: +.. _rpi_5: Raspberry Pi 5 (Cortex-A76) ########################### @@ -69,7 +69,7 @@ In brief, * `bcm2712-rpi-5.dtb`_ 3. Insert the Micro SD card and power on the Raspberry Pi 5. -then, You will see the Raspberry Pi 5 running the `zephyr.bin`. +then, You will see the Raspberry Pi 5 running the :file:`zephyr.bin`. config.txt ---------- @@ -83,14 +83,15 @@ config.txt zephyr.bin ---------- -Build an app `samples/basic/blinky` +Build an app, for example :zephyr:code-sample:`blinky` .. zephyr-app-commands:: :zephyr-app: samples/basic/blinky :board: rpi_5 :goals: build -Copy `zephyr.bin` from `build/zephyr` directory to the root directory of the Micro SD card. +Copy :file:`zephyr.bin` from :file:`build/zephyr` directory to the root directory of the Micro SD +card. Insert the Micro SD card and power on the Raspberry Pi 5. And then, the STAT LED will start to blink. @@ -125,14 +126,14 @@ config.txt zephyr.bin ---------- -Build an app `samples/hello_world` +Build an app, for example :zephyr:code-sample:`hello_world`: .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: rpi_5 :goals: build -Copy `zephyr.bin` from `build/zephyr` directory to the root directory of the Micro SD card. +Copy :file:`zephyr.bin` from :file:`build/zephyr` directory to the root directory of the Micro SD card. Insert the Micro SD card into your Raspberry Pi 5. diff --git a/boards/raspberrypi/rpi_pico/doc/index.rst b/boards/raspberrypi/rpi_pico/doc/index.rst index 8db18d96f04..b2af4693b01 100644 --- a/boards/raspberrypi/rpi_pico/doc/index.rst +++ b/boards/raspberrypi/rpi_pico/doc/index.rst @@ -121,8 +121,8 @@ Default Zephyr Peripheral Mapping: - UART0_RX : P1 - I2C0_SDA : P4 - I2C0_SCL : P5 -- I2C1_SDA : P14 -- I2C1_SCL : P15 +- I2C1_SDA : P6 +- I2C1_SCL : P7 - SPI0_RX : P16 - SPI0_CSN : P17 - SPI0_SCK : P18 @@ -137,11 +137,11 @@ Programmable I/O (PIO) The RP2040 SoC comes with two PIO periherals. These are two simple co-processors that are designed for I/O operations. The PIOs run a custom instruction set, generated from a custom assembly language. -PIO programs are assembled using `pioasm`, a tool provided by Raspberry Pi. +PIO programs are assembled using :command:`pioasm`, a tool provided by Raspberry Pi. Zephyr does not (currently) assemble PIO programs. Rather, they should be manually assembled and embedded in source code. An example of how this is done -can be found at `drivers/serial/uart_rpi_pico_pio.c`. +can be found at :zephyr_file:`drivers/serial/uart_rpi_pico_pio.c`. Sample: SPI via PIO ==================== @@ -179,7 +179,7 @@ Here is an example of building and flashing the :zephyr:code-sample:`blinky` app Using OpenOCD ------------- -To use PicoProbe, You must configure **udev**. +To use CMSIS-DAP, You must configure **udev**. Create a file in /etc/udev.rules.d with any name, and write the line below. @@ -187,7 +187,7 @@ Create a file in /etc/udev.rules.d with any name, and write the line below. ATTRS{idVendor}=="2e8a", ATTRS{idProduct}=="000c", MODE="660", GROUP="plugdev", TAG+="uaccess" -This example is valid for the case that the user joins to `plugdev` groups. +This example is valid for the case that the user joins to ``plugdev`` groups. The Raspberry Pi Pico has an SWD interface that can be used to program and debug the on board RP2040. This interface can be utilized by OpenOCD. @@ -206,24 +206,25 @@ Here is an example of building and flashing the :zephyr:code-sample:`blinky` app :zephyr-app: samples/basic/blinky :board: rpi_pico :goals: build flash - :gen-args: -DOPENOCD=/usr/local/bin/openocd -DOPENOCD_DEFAULT_PATH=/usr/local/share/openocd/scripts -DRPI_PICO_DEBUG_ADAPTER=picoprobe + :gen-args: -DOPENOCD=/usr/local/bin/openocd -DOPENOCD_DEFAULT_PATH=/usr/local/share/openocd/scripts -DRPI_PICO_DEBUG_ADAPTER=cmsis-dap -Set the environment variables **OPENOCD** to `/usr/local/bin/openocd` -and **OPENOCD_DEFAULT_PATH** to `/usr/local/share/openocd/scripts`. This should work +Set the environment variables **OPENOCD** to :file:`/usr/local/bin/openocd` +and **OPENOCD_DEFAULT_PATH** to :file:`/usr/local/share/openocd/scripts`. This should work with the OpenOCD that was installed with the default configuration. This configuration also works with an environment that is set up by the `pico_setup.sh`_ script. **RPI_PICO_DEBUG_ADAPTER** specifies what debug adapter is used for debugging. -If **RPI_PICO_DEBUG_ADAPTER** was not assigned, `picoprobe` is used by default. -The other supported adapters are `raspberrypi-swd`, `jlink` and `blackmagicprobe`. -How to connect `picoprobe` and `raspberrypi-swd` is described in `Getting Started with Raspberry Pi Pico`_. +If **RPI_PICO_DEBUG_ADAPTER** was not assigned, ``cmsis-dap`` is used by default. +The other supported adapters are ``raspberrypi-swd``, ``jlink`` and ``blackmagicprobe``. +How to connect ``cmsis-dap`` and ``raspberrypi-swd`` is described in `Getting Started with Raspberry Pi Pico`_. Any other SWD debug adapter maybe also work with this configuration. The value of **RPI_PICO_DEBUG_ADAPTER** is cached, so it can be omitted from -`west flash` and `west debug` if it was previously set while running `west build`. +``west flash`` and ``west debug`` if it was previously set while running +``west build``. -**RPI_PICO_DEBUG_ADAPTER** is used in an argument to OpenOCD as `"source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]"`. +**RPI_PICO_DEBUG_ADAPTER** is used in an argument to OpenOCD as ``"source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]"``. Thus, **RPI_PICO_DEBUG_ADAPTER** needs to be assigned the file name of the debug adapter. You can also flash the board with the following @@ -238,7 +239,7 @@ Using UF2 If you don't have an SWD adapter, you can flash the Raspberry Pi Pico with a UF2 file. By default, building an app for this board will generate a -`build/zephyr/zephyr.uf2` file. If the Pico is powered on with the `BOOTSEL` +:file:`build/zephyr/zephyr.uf2` file. If the Pico is powered on with the ``BOOTSEL`` button pressed, it will appear on the host as a mass storage device. The UF2 file should be drag-and-dropped to the device, which will flash the Pico. @@ -270,7 +271,7 @@ Here is an example for debugging the :zephyr:code-sample:`blinky` application. :gen-args: -DOPENOCD=/usr/local/bin/openocd -DOPENOCD_DEFAULT_PATH=/usr/local/share/openocd/scripts -DRPI_PICO_DEBUG_ADAPTER=raspberrypi-swd As with flashing, you can specify the debug adapter by specifying **RPI_PICO_DEBUG_ADAPTER** -at `west build` time. No needs to specify it at `west debug` time. +at ``west build`` time. No needs to specify it at ``west debug`` time. You can also debug with OpenOCD and gdb launching from command-line. Run the following command: diff --git a/boards/raspberrypi/rpi_pico/rpi_pico.yaml b/boards/raspberrypi/rpi_pico/rpi_pico.yaml index ada56d84480..80de519dad5 100644 --- a/boards/raspberrypi/rpi_pico/rpi_pico.yaml +++ b/boards/raspberrypi/rpi_pico/rpi_pico.yaml @@ -21,3 +21,4 @@ supported: - dma - counter - clock + - usbd diff --git a/boards/raytac/mdbt50q_db_33/Kconfig b/boards/raytac/mdbt50q_db_33/Kconfig deleted file mode 100644 index 33290b29c1f..00000000000 --- a/boards/raytac/mdbt50q_db_33/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Raytac MDBT50Q-DB-33 nRF52833 board configuration - -# Copyright (c) 2019 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_RAYTAC_MDBT50Q_DB_33 diff --git a/boards/raytac/mdbt50q_db_33/doc/index.rst b/boards/raytac/mdbt50q_db_33/doc/index.rst index b078dd2984e..8089b7b5e48 100644 --- a/boards/raytac/mdbt50q_db_33/doc/index.rst +++ b/boards/raytac/mdbt50q_db_33/doc/index.rst @@ -147,7 +147,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Use a USB to TTL converter to connect the computer and raytac_mdbt50q_db_33/nrf52833 J10 connector. Then run your favorite terminal program to listen for output. diff --git a/boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833.dts b/boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833.dts index a3ada26e811..c440759815d 100644 --- a/boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833.dts +++ b/boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833.dts @@ -89,6 +89,10 @@ }; }; +®1 { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; diff --git a/boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833.yaml b/boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833.yaml index 673705fa123..e0698628e71 100644 --- a/boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833.yaml +++ b/boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833.yaml @@ -21,7 +21,6 @@ supported: - ieee802154 - pwm - spi - - usb_cdc - usb_device - watchdog - netif:openthread diff --git a/boards/raytac/mdbt50q_db_40/Kconfig b/boards/raytac/mdbt50q_db_40/Kconfig deleted file mode 100644 index bb2c5c4ad77..00000000000 --- a/boards/raytac/mdbt50q_db_40/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -# Raytac MDBT50Q-DB-40 nRF52840 board configuration - -# Copyright (c) 2022 Raytac Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RAYTAC_MDBT50Q_DB_40 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF52X_HV - default y - -endif # BOARD_RAYTAC_MDBT50Q_DB_40 diff --git a/boards/raytac/mdbt50q_db_40/doc/index.rst b/boards/raytac/mdbt50q_db_40/doc/index.rst index f9d79818f6a..269b42bb9d5 100644 --- a/boards/raytac/mdbt50q_db_40/doc/index.rst +++ b/boards/raytac/mdbt50q_db_40/doc/index.rst @@ -149,7 +149,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Use a USB to TTL converter to connect the computer and raytac_mdbt50q_db_40/nrf52840 J10 connector. Then run your favorite terminal program to listen for output. diff --git a/boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840.dts b/boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840.dts index bd1a2f06855..025b8e7ec85 100644 --- a/boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840.dts +++ b/boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include "raytac_mdbt50q_db_40_nrf52840-pinctrl.dtsi" #include @@ -19,9 +20,6 @@ zephyr,uart-mcumgr = &uart0; zephyr,bt-mon-uart = &uart0; zephyr,bt-c2h-uart = &uart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; zephyr,ieee802154 = &ieee802154; }; @@ -89,6 +87,14 @@ }; }; +®0 { + status = "okay"; +}; + +®1 { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; @@ -187,42 +193,6 @@ status = "okay"; }; -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000C000>; - }; - slot0_partition: partition@c000 { - label = "image-0"; - reg = <0x0000C000 0x00076000>; - }; - slot1_partition: partition@82000 { - label = "image-1"; - reg = <0x00082000 0x00076000>; - }; - - /* - * The flash starting at 0x000f8000 and ending at - * 0x000fffff is reserved for use by the application. - */ - - /* - * Storage partition will be used by FCB/LittleFS/NVS - * if enabled. - */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; - zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; diff --git a/boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840.yaml b/boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840.yaml index 15ba012594e..cc99eab1a53 100644 --- a/boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840.yaml +++ b/boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840.yaml @@ -23,7 +23,6 @@ supported: - ieee802154 - pwm - spi - - usb_cdc - usb_device - watchdog - netif:openthread diff --git a/boards/raytac/mdbt53_db_40/CMakeLists.txt b/boards/raytac/mdbt53_db_40/CMakeLists.txt deleted file mode 100644 index 44bcab2993e..00000000000 --- a/boards/raytac/mdbt53_db_40/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if((CONFIG_BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP OR CONFIG_BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS) - AND CONFIG_BOARD_ENABLE_CPUNET) - zephyr_library() - zephyr_library_sources(raytac_mdbt53_db_40_nrf5340_cpunet_reset.c) -endif() diff --git a/boards/raytac/mdbt53_db_40/Kconfig b/boards/raytac/mdbt53_db_40/Kconfig index a436b55cfb4..d7591656a26 100644 --- a/boards/raytac/mdbt53_db_40/Kconfig +++ b/boards/raytac/mdbt53_db_40/Kconfig @@ -5,41 +5,9 @@ if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS -config BOARD_ENABLE_DCDC_APP - bool "Application MCU DCDC converter" - select SOC_DCDC_NRF53X_APP - default y - -config BOARD_ENABLE_DCDC_NET - bool "Network MCU DCDC converter" - select SOC_DCDC_NRF53X_NET - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF53X_HV - default y - -config BOARD_ENABLE_CPUNET - bool "NRF53 Network MCU" - select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ - $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) - help - This option enables releasing the Network 'force off' signal, which - as a consequence will power up the Network MCU during system boot. - Additionally, the option allocates GPIO pins that will be used by UARTE - of the Network MCU. - Note: GPIO pin allocation can only be configured by the secure Application - MCU firmware, so when this option is used with the non-secure version of - the board, the application needs to take into consideration, that the - secure firmware image must already have configured GPIO allocation for the - Network MCU. - default y if (BT || NRF_802154_SER_HOST) - config DOMAIN_CPUNET_BOARD string default "raytac_mdbt53_db_40/nrf5340/cpunet" - depends on BOARD_ENABLE_CPUNET help The board which will be used for CPUNET domain when creating a multi image application where one or more images should be located on diff --git a/boards/raytac/mdbt53_db_40/Kconfig.defconfig b/boards/raytac/mdbt53_db_40/Kconfig.defconfig index bb53d3ae8f4..dbbe13da493 100644 --- a/boards/raytac/mdbt53_db_40/Kconfig.defconfig +++ b/boards/raytac/mdbt53_db_40/Kconfig.defconfig @@ -62,12 +62,6 @@ config HEAP_MEM_POOL_ADD_SIZE_BOARD endif # BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS -config IPM_NRFX - default IPM - -config MBOX_NRFX_IPC - default MBOX - if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET config BT_CTLR diff --git a/boards/raytac/mdbt53_db_40/doc/index.rst b/boards/raytac/mdbt53_db_40/doc/index.rst index a57fc5225dc..9ddb5b77c5d 100644 --- a/boards/raytac/mdbt53_db_40/doc/index.rst +++ b/boards/raytac/mdbt53_db_40/doc/index.rst @@ -225,7 +225,7 @@ applications as usual (see :ref:`build_an_application` and If you are flashing with :ref:`west `, run this command for more details on the related ``--recover`` option: -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Use a USB to TTL converter to connect the computer and raytac_mdbt53_db_40_nrf5340 J10 connector. Then run your favorite terminal program to listen for output. diff --git a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp.yaml b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp.yaml index f962784606b..44596dc8a5b 100644 --- a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp.yaml +++ b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp.yaml @@ -17,6 +17,5 @@ supported: - spi - uart - watchdog - - usb_cdc - usb_device - netif:openthread diff --git a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_common.dts b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_common.dts index 62a49e52069..bd89fa1664f 100644 --- a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_common.dts +++ b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_common.dts @@ -96,6 +96,18 @@ }; }; +&vregmain { + regulator-initial-mode = ; +}; + +&vregradio { + regulator-initial-mode = ; +}; + +&vregh { + status = "okay"; +}; + &adc { status = "okay"; }; @@ -180,32 +192,6 @@ pinctrl-names = "default", "sleep"; }; -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x00010000>; - }; - slot0_partition: partition@10000 { - label = "image-0"; - }; - slot0_ns_partition: partition@50000 { - label = "image-0-nonsecure"; - }; - slot1_partition: partition@80000 { - label = "image-1"; - }; - slot1_ns_partition: partition@c0000 { - label = "image-1-nonsecure"; - }; - }; -}; - &ieee802154 { status = "okay"; }; @@ -215,26 +201,5 @@ zephyr_udc0: &usbd { status = "okay"; }; -/ { - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_image: image@20000000 { - /* Zephyr image(s) memory */ - }; - - sram0_s: image_s@20000000 { - /* Secure image memory */ - }; - - sram0_ns: image_ns@20040000 { - /* Non-Secure image memory */ - }; - }; -}; - -/* Include partition configuration file */ -#include "raytac_mdbt53_db_40_nrf5340_cpuapp_partition_conf.dts" +/* Include default memory partition configuration file */ +#include diff --git a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.dts b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.dts index 541de94d8cc..de907f029e7 100644 --- a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.dts +++ b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.dts @@ -13,7 +13,7 @@ compatible = "raytac,raytac-mdbt53-db-40-cpuapp"; chosen { - zephyr,sram = &sram0_ns; + zephyr,sram = &sram0_ns_app; zephyr,flash = &flash0; zephyr,code-partition = &slot0_ns_partition; }; diff --git a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.yaml b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.yaml index 46fbe1ea192..d77e8d5c8f0 100644 --- a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.yaml +++ b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.yaml @@ -15,7 +15,6 @@ supported: - watchdog - spi - uart - - usb_cdc - usb_device - netif:openthread - gpio diff --git a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_partition_conf.dts b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_partition_conf.dts deleted file mode 100644 index 74788769f01..00000000000 --- a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_partition_conf.dts +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (c) 2023 Raytac Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* - * Default Flash planning for raytac_mdbt53_db_40_nrf5340 CPUAPP (Application MCU). - * - * Zephyr build for nRF5340 with ARM TrustZone-M support, - * implies building Secure and Non-Secure Zephyr images. - * - * Secure image will be placed, by default, in flash0 - * (or in slot0, if MCUboot is present). - * Secure image will use sram0 for system memory. - * - * Non-Secure image will be placed in slot0_ns, and use - * sram0_ns for system memory. - * - * Note that the Secure image only requires knowledge of - * the beginning of the Non-Secure image (not its size). - */ - -&slot0_partition { - reg = <0x00010000 0x40000>; -}; - -&slot0_ns_partition { - reg = <0x00050000 0x30000>; -}; - -&slot1_partition { - reg = <0x00080000 0x40000>; -}; - -&slot1_ns_partition { - reg = <0x000c0000 0x30000>; -}; - -/* Default SRAM planning when building for nRF5340 with - * ARM TrustZone-M support - * - Lowest 256 kB SRAM allocated to Secure image (sram0_s) - * - Middle 192 kB allocated to Non-Secure image (sram0_ns) - * - Upper 64 kB SRAM allocated as Shared memory (sram0_shared) - * (see raytac_mdbt53_db_40_nrf5340_shared_sram_planning_conf.dts) - */ -&sram0_image { - reg = <0x20000000 DT_SIZE_K(448)>; -}; - -&sram0_s { - reg = <0x20000000 0x40000>; -}; - -&sram0_ns { - reg = <0x20040000 0x30000>; -}; - -/* Include shared RAM configuration file */ -#include "raytac_mdbt53_db_40_nrf5340_shared_sram_planning_conf.dts" diff --git a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_common.dts b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_common.dts index c04101e11c1..c5242550baa 100644 --- a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_common.dts +++ b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_common.dts @@ -56,5 +56,5 @@ }; }; -/* Include shared RAM configuration file */ -#include "raytac_mdbt53_db_40_nrf5340_shared_sram_planning_conf.dts" +/* Include default shared RAM configuration file */ +#include diff --git a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_reset.c b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_reset.c deleted file mode 100644 index 9596b3453be..00000000000 --- a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_reset.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2019-2021 Nordic Semiconductor ASA. - * Copyright (c) 2023 Raytac Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -#include -#include - -LOG_MODULE_REGISTER(raytac_mdbt53_db_40_nrf5340_cpuapp, CONFIG_LOG_DEFAULT_LEVEL); - -#if defined(CONFIG_BT_CTLR_DEBUG_PINS_CPUAPP) -#include <../subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/debug.h> -#else -#define DEBUG_SETUP() -#endif - -static void remoteproc_mgr_config(void) -{ -#if !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) || defined(CONFIG_BUILD_WITH_TFM) - /* Route Bluetooth Controller Debug Pins */ - DEBUG_SETUP(); -#endif /* !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) || defined(CONFIG_BUILD_WITH_TFM) */ - -#if !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) - /* Retain nRF5340 Network MCU in Secure domain (bus - * accesses by Network MCU will have Secure attribute set). - */ - NRF_SPU->EXTDOMAIN[0].PERM = 1 << 4; -#endif /* !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) */ -} - -static int remoteproc_mgr_boot(const struct device *dev) -{ - - /* Secure domain may configure permissions for the Network MCU. */ - remoteproc_mgr_config(); - -#if !defined(CONFIG_TRUSTED_EXECUTION_SECURE) - /* - * Building Zephyr with CONFIG_TRUSTED_EXECUTION_SECURE=y implies - * building also a Non-Secure image. The Non-Secure image will, in - * this case do the remainder of actions to properly configure and - * boot the Network MCU. - */ - - /* Release the Network MCU, 'Release force off signal' */ - nrf_reset_network_force_off(NRF_RESET, false); - - LOG_DBG("Network MCU released."); -#endif /* !CONFIG_TRUSTED_EXECUTION_SECURE */ - - return 0; -} - -SYS_INIT(remoteproc_mgr_boot, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); diff --git a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_shared_sram_planning_conf.dts b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_shared_sram_planning_conf.dts deleted file mode 100644 index aa162f85a5a..00000000000 --- a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_shared_sram_planning_conf.dts +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2023 Raytac Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* Default shared SRAM planning when building for nRF5340. - * This file is included by both nRF5340 CPUAPP (Application MCU) - * and nRF5340 CPUNET (Network MCU). - * - 64 kB SRAM allocated as Shared memory (sram0_shared) - * - Region defined after the image SRAM of Application MCU - */ - -/ { - chosen { - /* shared memory reserved for the inter-processor communication */ - zephyr,ipc_shm = &sram0_shared; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_shared: memory@20070000 { - /* SRAM allocated to shared memory */ - reg = <0x20070000 0x10000>; - }; - }; -}; diff --git a/boards/raytac/mdbt53v_db_40/CMakeLists.txt b/boards/raytac/mdbt53v_db_40/CMakeLists.txt deleted file mode 100644 index b31ed4ce0f2..00000000000 --- a/boards/raytac/mdbt53v_db_40/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if((CONFIG_BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP OR CONFIG_BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS) - AND CONFIG_BOARD_ENABLE_CPUNET) - zephyr_library() - zephyr_library_sources(raytac_mdbt53v_db_40_nrf5340_cpunet_reset.c) -endif() diff --git a/boards/raytac/mdbt53v_db_40/Kconfig b/boards/raytac/mdbt53v_db_40/Kconfig index fb688bae818..da05da70267 100644 --- a/boards/raytac/mdbt53v_db_40/Kconfig +++ b/boards/raytac/mdbt53v_db_40/Kconfig @@ -5,41 +5,9 @@ if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS -config BOARD_ENABLE_DCDC_APP - bool "Application MCU DCDC converter" - select SOC_DCDC_NRF53X_APP - default y - -config BOARD_ENABLE_DCDC_NET - bool "Network MCU DCDC converter" - select SOC_DCDC_NRF53X_NET - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF53X_HV - default y - -config BOARD_ENABLE_CPUNET - bool "NRF53 Network MCU" - select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ - $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) - help - This option enables releasing the Network 'force off' signal, which - as a consequence will power up the Network MCU during system boot. - Additionally, the option allocates GPIO pins that will be used by UARTE - of the Network MCU. - Note: GPIO pin allocation can only be configured by the secure Application - MCU firmware, so when this option is used with the non-secure version of - the board, the application needs to take into consideration, that the - secure firmware image must already have configured GPIO allocation for the - Network MCU. - default y if (BT || NRF_802154_SER_HOST) - config DOMAIN_CPUNET_BOARD string default "raytac_mdbt53v_db_40/nrf5340/cpunet" - depends on BOARD_ENABLE_CPUNET help The board which will be used for CPUNET domain when creating a multi image application where one or more images should be located on diff --git a/boards/raytac/mdbt53v_db_40/Kconfig.defconfig b/boards/raytac/mdbt53v_db_40/Kconfig.defconfig index 9573720773d..b3f4fb77c5b 100644 --- a/boards/raytac/mdbt53v_db_40/Kconfig.defconfig +++ b/boards/raytac/mdbt53v_db_40/Kconfig.defconfig @@ -62,12 +62,6 @@ config HEAP_MEM_POOL_ADD_SIZE_BOARD endif # BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS -config IPM_NRFX - default IPM - -config MBOX_NRFX_IPC - default MBOX - if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET config BT_CTLR diff --git a/boards/raytac/mdbt53v_db_40/doc/index.rst b/boards/raytac/mdbt53v_db_40/doc/index.rst index ca38f03a781..27a2aeee345 100644 --- a/boards/raytac/mdbt53v_db_40/doc/index.rst +++ b/boards/raytac/mdbt53v_db_40/doc/index.rst @@ -218,7 +218,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Use a USB to TTL converter to connect the computer and raytac_mdbt53v_db_40_nrf5340 J13 connector pin 8(RX), 9(TX) and GND. Then run your favorite terminal program to listen for output. diff --git a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts index 3c1b42307a6..71811564df1 100644 --- a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts +++ b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts @@ -75,6 +75,18 @@ }; }; +&vregmain { + regulator-initial-mode = ; +}; + +&vregradio { + regulator-initial-mode = ; +}; + +&vregh { + status = "okay"; +}; + &adc { status = "okay"; }; @@ -138,61 +150,9 @@ pinctrl-names = "default", "sleep"; }; -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x00010000>; - }; - slot0_partition: partition@10000 { - label = "image-0"; - }; - slot0_ns_partition: partition@50000 { - label = "image-0-nonsecure"; - }; - slot1_partition: partition@80000 { - label = "image-1"; - }; - slot1_ns_partition: partition@c0000 { - label = "image-1-nonsecure"; - }; - /* 0xf0000 to 0xf7fff reserved for TF-M partitions */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; - &ieee802154 { status = "okay"; }; -/ { - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_image: image@20000000 { - /* Zephyr image(s) memory */ - }; - - sram0_s: image_s@20000000 { - /* Secure image memory */ - }; - - sram0_ns: image_ns@20040000 { - /* Non-Secure image memory */ - }; - }; -}; - -/* Include partition configuration file */ -#include "raytac_mdbt53v_db_40_nrf5340_cpuapp_partition_conf.dts" +/* Include default memory partition configuration file */ +#include diff --git a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.dts b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.dts index 0713304bc15..df5af5e9c3a 100644 --- a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.dts +++ b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.dts @@ -13,7 +13,7 @@ compatible = "raytac,raytac-mdbt53v-db-40-nrf5340-cpuapp"; chosen { - zephyr,sram = &sram0_ns; + zephyr,sram = &sram0_ns_app; zephyr,flash = &flash0; zephyr,code-partition = &slot0_ns_partition; }; diff --git a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_partition_conf.dts b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_partition_conf.dts deleted file mode 100644 index 207d58f4e75..00000000000 --- a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_partition_conf.dts +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (c) 2023 Raytac Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* - * Default Flash planning for raytac_mdbt53v_db_40_nrf5340 CPUAPP (Application MCU). - * - * Zephyr build for nRF5340 with ARM TrustZone-M support, - * implies building Secure and Non-Secure Zephyr images. - * - * Secure image will be placed, by default, in flash0 - * (or in slot0, if MCUboot is present). - * Secure image will use sram0 for system memory. - * - * Non-Secure image will be placed in slot0_ns, and use - * sram0_ns for system memory. - * - * Note that the Secure image only requires knowledge of - * the beginning of the Non-Secure image (not its size). - */ - -&slot0_partition { - reg = <0x00010000 0x40000>; -}; - -&slot0_ns_partition { - reg = <0x00050000 0x30000>; -}; - -&slot1_partition { - reg = <0x00080000 0x40000>; -}; - -&slot1_ns_partition { - reg = <0x000c0000 0x30000>; -}; - -/* Default SRAM planning when building for nRF5340 with - * ARM TrustZone-M support - * - Lowest 256 kB SRAM allocated to Secure image (sram0_s) - * - Middle 192 kB allocated to Non-Secure image (sram0_ns) - * - Upper 64 kB SRAM allocated as Shared memory (sram0_shared) - * (see raytac_mdbt53v_db_40_nrf5340_shared_sram_planning_conf.dts) - */ -&sram0_image { - reg = <0x20000000 DT_SIZE_K(448)>; -}; - -&sram0_s { - reg = <0x20000000 0x40000>; -}; - -&sram0_ns { - reg = <0x20040000 0x30000>; -}; - -/* Include shared RAM configuration file */ -#include "raytac_mdbt53v_db_40_nrf5340_shared_sram_planning_conf.dts" diff --git a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_common.dts b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_common.dts index 643bebf6e38..c5242550baa 100644 --- a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_common.dts +++ b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_common.dts @@ -56,5 +56,5 @@ }; }; -/* Include shared RAM configuration file */ -#include "raytac_mdbt53v_db_40_nrf5340_shared_sram_planning_conf.dts" +/* Include default shared RAM configuration file */ +#include diff --git a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_reset.c b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_reset.c deleted file mode 100644 index 31b8bf5a75e..00000000000 --- a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_reset.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (c) 2019-2021 Nordic Semiconductor ASA. - * Copyright (c) 2023 Raytac Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -#include - -LOG_MODULE_REGISTER(raytac_mdbt53v_db_40_nrf5340_cpuapp, CONFIG_LOG_DEFAULT_LEVEL); - -#if defined(CONFIG_BT_CTLR_DEBUG_PINS_CPUAPP) -#include <../subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/debug.h> -#else -#define DEBUG_SETUP() -#endif - -static void remoteproc_mgr_config(void) -{ -#if !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) || defined(CONFIG_BUILD_WITH_TFM) - /* Route Bluetooth Controller Debug Pins */ - DEBUG_SETUP(); -#endif /* !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) || defined(CONFIG_BUILD_WITH_TFM) */ - -#if !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) - /* Retain nRF5340 Network MCU in Secure domain (bus - * accesses by Network MCU will have Secure attribute set). - */ - NRF_SPU->EXTDOMAIN[0].PERM = 1 << 4; -#endif /* !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) */ -} - -static int remoteproc_mgr_boot(const struct device *dev) -{ - - /* Secure domain may configure permissions for the Network MCU. */ - remoteproc_mgr_config(); - -#if !defined(CONFIG_TRUSTED_EXECUTION_SECURE) - /* - * Building Zephyr with CONFIG_TRUSTED_EXECUTION_SECURE=y implies - * building also a Non-Secure image. The Non-Secure image will, in - * this case do the remainder of actions to properly configure and - * boot the Network MCU. - */ - - /* Release the Network MCU, 'Release force off signal' */ - nrf_reset_network_force_off(NRF_RESET, false); - - LOG_DBG("Network MCU released."); -#endif /* !CONFIG_TRUSTED_EXECUTION_SECURE */ - - return 0; -} - -SYS_INIT(remoteproc_mgr_boot, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); diff --git a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_shared_sram_planning_conf.dts b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_shared_sram_planning_conf.dts deleted file mode 100644 index aa162f85a5a..00000000000 --- a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_shared_sram_planning_conf.dts +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2023 Raytac Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* Default shared SRAM planning when building for nRF5340. - * This file is included by both nRF5340 CPUAPP (Application MCU) - * and nRF5340 CPUNET (Network MCU). - * - 64 kB SRAM allocated as Shared memory (sram0_shared) - * - Region defined after the image SRAM of Application MCU - */ - -/ { - chosen { - /* shared memory reserved for the inter-processor communication */ - zephyr,ipc_shm = &sram0_shared; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_shared: memory@20070000 { - /* SRAM allocated to shared memory */ - reg = <0x20070000 0x10000>; - }; - }; -}; diff --git a/boards/renesas/da14695_dk_usb/da14695_dk_usb-pinctrl.dtsi b/boards/renesas/da14695_dk_usb/da14695_dk_usb-pinctrl.dtsi index d16ad945fa8..fbdf787a88e 100644 --- a/boards/renesas/da14695_dk_usb/da14695_dk_usb-pinctrl.dtsi +++ b/boards/renesas/da14695_dk_usb/da14695_dk_usb-pinctrl.dtsi @@ -44,6 +44,15 @@ }; }; + /omit-if-no-ref/ i2c_sleep: i2c_sleep { + group1 { + pinmux = , + ; + bias-pull-up; + + }; + }; + i2c2_default: i2c2_default { group1 { pinmux = , @@ -52,6 +61,22 @@ }; }; + /omit-if-no-ref/ i2c2_sleep: i2c2_sleep { + group1 { + pinmux = , + ; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ spi_sleep: spi_sleep { + group1 { + pinmux = , + , + ; + }; + }; + spi_controller: spi_controller { group1 { pinmux = < SMARTBOND_PINMUX(SPI_CLK, 0, 21) >, @@ -64,6 +89,14 @@ }; }; + /omit-if-no-ref/ spi2_sleep: spi2_sleep { + group1 { + pinmux = , + , + ; + }; + }; + spi2_controller: spi2_controller { group1 { pinmux = < SMARTBOND_PINMUX(SPI2_CLK, 1, 3) >, diff --git a/boards/renesas/da14695_dk_usb/da14695_dk_usb.dts b/boards/renesas/da14695_dk_usb/da14695_dk_usb.dts index eff5299dcff..0c38c829db1 100644 --- a/boards/renesas/da14695_dk_usb/da14695_dk_usb.dts +++ b/boards/renesas/da14695_dk_usb/da14695_dk_usb.dts @@ -189,25 +189,29 @@ zephyr_udc0: &usbd { &i2c { status = "okay"; pinctrl-0 = <&i2c_default>; - pinctrl-names = "default"; + pinctrl-1 = <&i2c_sleep>; + pinctrl-names = "default", "sleep"; }; &i2c2 { status = "okay"; pinctrl-0 = <&i2c2_default>; - pinctrl-names = "default"; + pinctrl-1 = <&i2c2_sleep>; + pinctrl-names = "default", "sleep"; }; &spi { status = "okay"; pinctrl-0 = <&spi_controller>; - pinctrl-names = "default"; + pinctrl-1 = <&spi_sleep>; + pinctrl-names = "default", "sleep"; }; &spi2 { status = "okay"; pinctrl-0 = <&spi2_controller>; - pinctrl-names = "default"; + pinctrl-1 = <&spi2_sleep>; + pinctrl-names = "default", "sleep"; }; mikrobus_1_i2c: &i2c {}; diff --git a/boards/renesas/da1469x_dk_pro/Kconfig.defconfig b/boards/renesas/da1469x_dk_pro/Kconfig.defconfig index 5590a9550e4..496044aa9b6 100644 --- a/boards/renesas/da1469x_dk_pro/Kconfig.defconfig +++ b/boards/renesas/da1469x_dk_pro/Kconfig.defconfig @@ -5,6 +5,9 @@ if BOARD_DA1469X_DK_PRO +config I2C_CALLBACK + default y if I2C_SMARTBOND + if LVGL config LV_Z_BITS_PER_PIXEL @@ -34,7 +37,7 @@ config LV_Z_POINTER_INPUT_MSGQ_COUNT endif # INPUT -#if PM || PM_DEVICE || PM_DEVICE_RUNTIME +if PM || PM_DEVICE || PM_DEVICE_RUNTIME # Increase stack size to avoid raising usage-fault # exceptions due to stack overflow. @@ -46,7 +49,7 @@ config IDLE_STACK_SIZE config SERIAL_INIT_PRIORITY default KERNEL_INIT_PRIORITY_DEFAULT -#endif # PM || PM_DEVICE +endif # PM || PM_DEVICE if BT diff --git a/boards/renesas/da1469x_dk_pro/da1469x_dk_pro-pinctrl.dtsi b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro-pinctrl.dtsi index 0a90af9a63c..50396701632 100644 --- a/boards/renesas/da1469x_dk_pro/da1469x_dk_pro-pinctrl.dtsi +++ b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro-pinctrl.dtsi @@ -24,6 +24,15 @@ }; }; + /omit-if-no-ref/ i2c_sleep: i2c_sleep { + group1 { + pinmux = , + ; + bias-pull-up; + + }; + }; + i2c2_default: i2c2_default { group1 { pinmux = , @@ -32,6 +41,14 @@ }; }; + /omit-if-no-ref/ i2c2_sleep: i2c2_sleep { + group1 { + pinmux = , + ; + bias-pull-up; + }; + }; + display_controller_default: display_controller_default { group1 { pinmux = , @@ -62,6 +79,14 @@ }; }; + /omit-if-no-ref/ spi_sleep: spi_sleep { + group1 { + pinmux = , + , + ; + }; + }; + spi_controller: spi_controller { group1 { pinmux = , @@ -74,6 +99,14 @@ }; }; + /omit-if-no-ref/ spi2_sleep: spi2_sleep { + group1 { + pinmux = , + , + ; + }; + }; + spi2_controller: spi2_controller { group1 { pinmux = < SMARTBOND_PINMUX(SPI2_CLK, 1, 3) >, diff --git a/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.dts b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.dts index 4691a206f57..f866df49a85 100644 --- a/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.dts +++ b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.dts @@ -140,6 +140,14 @@ zephyr_udc0: &usbd { status = "okay"; }; +/* + * On board level we switch to XTAL32K and + * so RCX can be disabled. + */ +&rcx { + status = "disabled"; +}; + &lp_clk { clock-src = <&xtal32k>; }; @@ -148,31 +156,28 @@ zephyr_udc0: &usbd { clock-src = <&xtal32m>; }; -&pll { - status = "okay"; -}; &i2c { - status = "okay"; pinctrl-0 = <&i2c_default>; - pinctrl-names = "default"; + pinctrl-1 = <&i2c_sleep>; + pinctrl-names = "default", "sleep"; }; &i2c2 { - status = "okay"; pinctrl-0 = <&i2c2_default>; - pinctrl-names = "default"; + pinctrl-1 = <&i2c2_sleep>; + pinctrl-names = "default", "sleep"; }; &spi { - status = "okay"; pinctrl-0 = <&spi_controller>; - pinctrl-names = "default"; + pinctrl-1 = <&spi_sleep>; + pinctrl-names = "default", "sleep"; }; &spi2 { - status = "okay"; pinctrl-0 = <&spi2_controller>; - pinctrl-names = "default"; + pinctrl-1 = <&spi2_sleep>; + pinctrl-names = "default", "sleep"; }; &bt_hci_da1469x { diff --git a/boards/renesas/da1469x_dk_pro/da1469x_dk_pro_defconfig b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro_defconfig index e31b6eb8457..9ce790fe46b 100644 --- a/boards/renesas/da1469x_dk_pro/da1469x_dk_pro_defconfig +++ b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro_defconfig @@ -9,6 +9,3 @@ CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_BUILD_OUTPUT_HEX=n - -CONFIG_I2C=y -CONFIG_I2C_CALLBACK=y diff --git a/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_lcdc.overlay b/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_lcdc.overlay index 197882b5536..94346ea39e7 100644 --- a/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_lcdc.overlay +++ b/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_lcdc.overlay @@ -8,77 +8,74 @@ #include / { - chosen { - zephyr,display = &lcdc; - }; + chosen { + zephyr,display = &lcdc; + }; - lvgl_pointer { - input = <&display_touch>; - status = "okay"; - swap-xy; - }; -}; - -&dma { - status = "okay"; + lvgl_pointer { + input = <&display_touch>; + status = "okay"; + swap-xy; + }; }; &pinctrl { - i2c2_default: i2c2_default { - group1 { - pinmux = , - ; - bias-pull-up; - }; - }; + i2c2_default: i2c2_default { + group1 { + pinmux = , + ; + bias-pull-up; + }; + }; - i2c2_sleep: i2c2_sleep { - group1 { - pinmux = , - ; - bias-pull-down; - }; - }; + i2c2_sleep: i2c2_sleep { + group1 { + pinmux = , + ; + bias-pull-up; + }; + }; }; &i2c2 { - clock-frequency = <400000>; + clock-frequency = <400000>; + status = "okay"; - display_touch: ft6206@38 { - compatible = "focaltech,ft5336"; - status = "okay"; - reg = <0x38>; - int-gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; - }; + display_touch: ft6206@38 { + compatible = "focaltech,ft5336"; + status = "okay"; + reg = <0x38>; + int-gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; + }; }; &lcdc { - status = "okay"; - pinctrl-0 = <&display_controller_default>; - pinctrl-1 = <&display_controller_sleep>; - pinctrl-names = "default", "sleep"; - width = <480>; - height = <272>; - disp-gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; - pixel-format = ; + status = "okay"; + pinctrl-0 = <&display_controller_default>; + pinctrl-1 = <&display_controller_sleep>; + pinctrl-names = "default", "sleep"; + width = <480>; + height = <272>; + disp-gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; + pixel-format = ; - /* - * Panel settings for the NHD-4.3-480272EF-ASXP-CTP - * display panel model which integrates the SC7283 - * driver IC. - */ - display-timings { - compatible = "zephyr,panel-timing"; - hsync-len = <2>; - hfront-porch = <2>; - hback-porch = <3>; - vsync-len = <2>; - vfront-porch = <2>; - vback-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - clock-frequency = <12000000>; - }; + /* + * Panel settings for the NHD-4.3-480272EF-ASXP-CTP + * display panel model which integrates the SC7283 + * driver IC. + */ + display-timings { + compatible = "zephyr,panel-timing"; + hsync-len = <2>; + hfront-porch = <2>; + hback-porch = <3>; + vsync-len = <2>; + vfront-porch = <2>; + vback-porch = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + clock-frequency = <12000000>; + }; }; diff --git a/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_mipi_dbi.overlay b/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_mipi_dbi.overlay index 81dbc363d62..6612d290f5d 100644 --- a/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_mipi_dbi.overlay +++ b/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_mipi_dbi.overlay @@ -8,50 +8,50 @@ #include / { - chosen { - zephyr,display = &ili9340; - }; + chosen { + zephyr,display = &ili9340; + }; - lvgl_pointer { - input = <&display_touch>; - status = "okay"; - swap-xy; - invert-x; - invert-y; - }; + lvgl_pointer { + input = <&display_touch>; + status = "okay"; + swap-xy; + invert-x; + invert-y; + }; }; &i2c2 { - clock-frequency = <400000>; + clock-frequency = <400000>; + status = "okay"; - display_touch: ft6206@38 { - compatible = "focaltech,ft5336"; - status = "okay"; - reg = <0x38>; - int-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; - }; + display_touch: ft6206@38 { + compatible = "focaltech,ft5336"; + status = "okay"; + reg = <0x38>; + int-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; + }; }; &lcdc { - compatible = "renesas,smartbond-mipi-dbi"; - status = "okay"; - reset-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; - spi-dev = <&spi2>; - pinctrl-0 = <&mipi_dbi_default>; - pinctrl-1 = <&mipi_dbi_read>; - pinctrl-2 = <&mipi_dbi_sleep>; - pinctrl-names = "default", "read", "sleep"; - #address-cells = <1>; - #size-cells = <0>; + compatible = "renesas,smartbond-mipi-dbi"; + status = "okay"; + reset-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&mipi_dbi_default>; + pinctrl-1 = <&mipi_dbi_read>; + pinctrl-2 = <&mipi_dbi_sleep>; + pinctrl-names = "default", "read", "sleep"; + #address-cells = <1>; + #size-cells = <0>; - ili9340: ili9340@0 { - compatible = "ilitek,ili9340"; - mipi-max-frequency = <48000000>; - status = "okay"; - reg = <0>; - width = <240>; - height = <320>; - pixel-format = ; - rotation = <0>; - }; + ili9340: ili9340@0 { + compatible = "ilitek,ili9340"; + mipi-max-frequency = <48000000>; + status = "okay"; + reg = <0>; + width = <240>; + height = <320>; + pixel-format = ; + rotation = <0>; + }; }; diff --git a/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_psram.overlay b/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_psram.overlay index 5707f111d97..e44f1484bc5 100644 --- a/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_psram.overlay +++ b/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_psram.overlay @@ -4,12 +4,16 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { +/ { aliases { sram-ext = &memc; }; }; +&psram { + status = "okay"; +}; + /* QSPIC settings for the APS6404L-3SQR QSPI PSRAM memory in QPI mode. */ &memc { status = "okay"; diff --git a/boards/renesas/ek_ra2a1/Kconfig.ek_ra2a1 b/boards/renesas/ek_ra2a1/Kconfig.ek_ra2a1 new file mode 100644 index 00000000000..5eaad77c79c --- /dev/null +++ b/boards/renesas/ek_ra2a1/Kconfig.ek_ra2a1 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EK_RA2A1 + select SOC_R7FA2A1AB3CFM diff --git a/boards/renesas/ek_ra2a1/board.cmake b/boards/renesas/ek_ra2a1/board.cmake new file mode 100644 index 00000000000..98ad18aa9bb --- /dev/null +++ b/boards/renesas/ek_ra2a1/board.cmake @@ -0,0 +1,9 @@ +# Copyright (c) 2024 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R7FA2A1AB") + +board_runner_args(pyocd "--target=r7fa2a1ab") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/renesas/ek_ra2a1/board.yml b/boards/renesas/ek_ra2a1/board.yml new file mode 100644 index 00000000000..82c498850aa --- /dev/null +++ b/boards/renesas/ek_ra2a1/board.yml @@ -0,0 +1,5 @@ +board: + name: ek_ra2a1 + vendor: renesas + socs: + - name: r7fa2a1ab3cfm diff --git a/boards/renesas/ek_ra2a1/doc/index.rst b/boards/renesas/ek_ra2a1/doc/index.rst new file mode 100644 index 00000000000..060f1627d2c --- /dev/null +++ b/boards/renesas/ek_ra2a1/doc/index.rst @@ -0,0 +1,105 @@ +.. _ek_ra2a1: + +RA2A1 Evaluation Kit +#################### + +Overview +******** + +The EK-RA2A1 is an evaluation kit for Renesas RA2A1 Microcontroller Group. + +Renesas RA2A1 Microcontroller Group has following features + +- 48MHz, Arm Cortex-M23 core +- 256kB Code Flash, 8kB Data Flash, 32kB SRAM +- USB 2.0 Full-Sppeed +- SCI x 3 +- SPI x 2 +- I2C x 2 +- CAN x 1 +- 16-bit A/D Converter +- 24-bit Sigma-Delta A/D Converter +- 12-bit D/A Converter +- 8-bit D/A Converter x 2 +- High-Speed Analog Comparator +- Low-Power Analog Comparator +- OPAMP x 3 +- Temperature Sensor +- General PWM Timer 32-bit x 1 +- General PWM Timer 16-bit x 6 +- Low Power Asynchronous General-Purpose Timer x 2 +- Watchdog Timer +- 49 Input/Output pins + +Hardware +******** + +EK-RA2A1 has following features. + +- Native pin access through 4x 40-pin male headers +- MCU current measurement points +- SEGGER J-Link on-board programmer and debugger +- Two Digilent Pmod (SPI and UART) +- User LED +- Mechanical user button +- Capacitive user button + +Supported Features +================== + +The Renesas EK-RA2A1 board configuration supports the following +hardware features: + ++-----------+------------+-------------------------------+ +| Interface | Controller | Driver/components | ++===========+============+===============================+ +| PINCTRL | on-chip | pinctrl | ++-----------+------------+-------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------+ +| UART | on-chip | uart | ++-----------+------------+-------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/renesas/ek_ra2a1/ek_ra2a1_defconfig` + + +Programming and debugging +************************* + +Building & Flashing +=================== + +You can build and flash an application with onboard J-Link debug adapter. +:ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for building and flashing the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: ek_ra2a1 + :goals: build flash + + +Debugging +========= + +Debugging also can be done with onboard J-Link debug adapter. +The following command is debugging the :zephyr:code-sample:`blinky` application. +Also, see the instructions specific to the debug server that you use. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: ek_ra2a1 + :maybe-skip-config: + :goals: debug + + +References +********** + +.. EK-RA2A1 Web site: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra2a1-evaluation-kit-ra2a1-mcu-group diff --git a/boards/renesas/ek_ra2a1/ek_ra2a1-pinctrl.dtsi b/boards/renesas/ek_ra2a1/ek_ra2a1-pinctrl.dtsi new file mode 100644 index 00000000000..cded3e5f655 --- /dev/null +++ b/boards/renesas/ek_ra2a1/ek_ra2a1-pinctrl.dtsi @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2024 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci0_default: sci0_default { + group1 { + /* rx */ + psels = ; + }; + group2 { + /* tx */ + psels = ; + drive-strength = "medium"; + }; + }; +}; diff --git a/boards/renesas/ek_ra2a1/ek_ra2a1.dts b/boards/renesas/ek_ra2a1/ek_ra2a1.dts new file mode 100644 index 00000000000..eb14660f8ac --- /dev/null +++ b/boards/renesas/ek_ra2a1/ek_ra2a1.dts @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2024 TOKITA Hiroshi + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +#include "ek_ra2a1-pinctrl.dtsi" + +/ { + model = "Renesas EK-RA2A1"; + compatible = "renesas,ra2a1", "renesas,ra2"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + leds { + compatible = "gpio-leds"; + led1: led1 { + gpios = <&ioport2 5 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + }; + + aliases { + led0 = &led1; + }; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&ioport2 { + status = "okay"; +}; + +&sci0 { + pinctrl-0 = <&sci0_default>; + pinctrl-names = "default"; + status = "okay"; + uart0: uart { + current-speed = <115200>; + status = "okay"; + }; +}; diff --git a/boards/renesas/ek_ra2a1/ek_ra2a1.yaml b/boards/renesas/ek_ra2a1/ek_ra2a1.yaml new file mode 100644 index 00000000000..78000823a98 --- /dev/null +++ b/boards/renesas/ek_ra2a1/ek_ra2a1.yaml @@ -0,0 +1,12 @@ +identifier: ek_ra2a1 +name: Renesas EK-RA2A1 +type: mcu +arch: arm +ram: 32 +flash: 256 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - uart diff --git a/boards/renesas/ek_ra2a1/ek_ra2a1_defconfig b/boards/renesas/ek_ra2a1/ek_ra2a1_defconfig new file mode 100644 index 00000000000..6058aa5eb98 --- /dev/null +++ b/boards/renesas/ek_ra2a1/ek_ra2a1_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 + +# Enable GPIO +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/ek_ra4e2/Kconfig.ek_ra4e2 b/boards/renesas/ek_ra4e2/Kconfig.ek_ra4e2 new file mode 100644 index 00000000000..418e3597cd7 --- /dev/null +++ b/boards/renesas/ek_ra4e2/Kconfig.ek_ra4e2 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EK_RA4E2 + select SOC_R7FA4E2B93CFM diff --git a/boards/renesas/ek_ra4e2/board.cmake b/boards/renesas/ek_ra4e2/board.cmake new file mode 100644 index 00000000000..18c2bdf71e9 --- /dev/null +++ b/boards/renesas/ek_ra4e2/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R7FA4E2B9") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/ek_ra4e2/board.yml b/boards/renesas/ek_ra4e2/board.yml new file mode 100644 index 00000000000..8baa0819ff2 --- /dev/null +++ b/boards/renesas/ek_ra4e2/board.yml @@ -0,0 +1,5 @@ +board: + name: ek_ra4e2 + vendor: renesas + socs: + - name: r7fa4e2b93cfm diff --git a/boards/renesas/ek_ra4e2/doc/ek-ra4e2-board.webp b/boards/renesas/ek_ra4e2/doc/ek-ra4e2-board.webp new file mode 100644 index 00000000000..4b3e56075c3 Binary files /dev/null and b/boards/renesas/ek_ra4e2/doc/ek-ra4e2-board.webp differ diff --git a/boards/renesas/ek_ra4e2/doc/index.rst b/boards/renesas/ek_ra4e2/doc/index.rst new file mode 100644 index 00000000000..0bf90ed5464 --- /dev/null +++ b/boards/renesas/ek_ra4e2/doc/index.rst @@ -0,0 +1,165 @@ +.. _ek_ra4e2: + +RA4E2 Evaluation Kit +#################### + +Overview +******** + +The RA4E2 Group delivers up to 100 MHz of CPU performance using an Arm® Cortex®-M33 core +with 128 KB of code flash memory, 4 KB of data flash memory, and 40 KB of SRAM. RA4E2 MCUs +offer high-performance and optimized peripheral functions along with the smallest package +options, including space-saving 36-pin BGA and 32-pin QFN packages. The RA4E2 +Group offers a wide set of peripherals, including USB Full Speed, CANFD, I3C, and ADC. + +The MCU in this series incorporates a high-performance Arm Cortex®-M33 core running up to +100 MHz with the following features: + +**MCU Native Pin Access** +- R7FA4E2B93CFM MCU (referred to as RA MCU) +- 100 MHz, Arm® Cortex®-M33 core +- 128 kB Code Flash, 40 kB SRAM +- 64 pins, LQFP package +- Native pin access through 2 x 14-pin and 1 x 40-pin male headers +- MCU current measurement points for precision current consumption measurement +- Multiple clock sources - RA MCU oscillator and sub-clock oscillator crystals, providing precision +20.000 MHz and 32,768 Hz reference clock. Additional low-precision clocks are available internal to the +RA MCU + +**System Control and Ecosystem Access** +- USB Full Speed Device (micro-AB connector) +- Three 5 V input sources + + - USB (Debug, Full Speed) + - External power supply (using surface mount clamp test points and J31 through holes) + +- Three Debug modes + + - Debug on-board (SWD) + - Debug in (SWD) + - Debug out (JTAG, SWD) + +- User LEDs and buttons + + - Three User LEDs (red, blue, green) + - Power LED (white) indicating availability of regulated power + - Debug LED (yellow) indicating the debug connection + - Two User buttons + - One Reset button + +- Five most popular ecosystems expansions + + - 2 Seeed Grove® system (I3C/Analog) connectors + - SparkFun® Qwiic® connector + - 2 Digilent PmodTM (SPI and UART) connectors + - ArduinoTM (Uno R3) connector + - MikroElektronikaTM mikroBUS connector + +- MCU boot configuration jumper + +**Special Feature Access** + +- CAN FD (3-pin header) + +.. figure:: ek-ra4e2-board.webp + :align: center + :alt: RA4E2 Evaluation Kit + + EK-RA4E2 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) + +Hardware +******** +Detail Hardware feature for the RA4E2 MCU group can be found at `RA4E2 Group User's Manual Hardware`_ + +.. figure:: ra4e2-block-diagram.webp + :width: 442px + :align: center + :alt: RA4E2 MCU group feature + + RA4E2 Block diagram (Credit: Renesas Electronics Corporation) + +Detail Hardware feature for the EK-RA4E2 MCU can be found at `EK-RA4E2 - User's Manual`_ + +Supported Features +================== + +The below features are currently supported on Zephyr OS for EK-RA4E2 board: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock control | ++-----------+------------+----------------------+ + +Other hardware features are currently not supported by the port. + +Programming and Debugging +************************* + +Applications for the ``ek_ra4e2`` board target configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +Program can be flashed to EK-RA4E2 via the on-board SEGGER J-Link debugger. +SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ + +To flash the program to board + + 1. Connect to J-Link OB via USB port to host PC + + 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA4E2 - User's Manual`_ + + 3. Execute west command + + .. code-block:: console + + west flash -r jlink + +Debugging +========= + +You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface + +Once downloaded and installed, open Segger Ozone and configure the debug project +like so: + +* Target Device: R7FA4E2B9 +* Target Interface: SWD +* Target Interface Speed: 4 MHz +* Host Interface: USB +* Program File: + +**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later +version of Segger Ozone + +References +********** +- `EK-RA4E2 Website`_ +- `RA4E2 MCU group Website`_ + +.. _EK-RA4E2 Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra4e2-evaluation-kit-ra4e2-mcu-group + +.. _RA4E2 MCU group Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra4e2-entry-line-100mhz-arm-cortex-m33-general-purpose-microcontroller + +.. _EK-RA4E2 - User's Manual: + https://www.renesas.com/us/en/document/mat/ek-ra4e2-v1-users-manual + +.. _RA4E2 Group User's Manual Hardware: + https://www.renesas.com/us/en/document/mah/ra4e2-group-users-manual-hardware + +.. _Segger Ozone Download: + https://www.segger.com/downloads/jlink#Ozone diff --git a/boards/renesas/ek_ra4e2/doc/ra4e2-block-diagram.webp b/boards/renesas/ek_ra4e2/doc/ra4e2-block-diagram.webp new file mode 100644 index 00000000000..d214ac7dba8 Binary files /dev/null and b/boards/renesas/ek_ra4e2/doc/ra4e2-block-diagram.webp differ diff --git a/boards/renesas/ek_ra4e2/ek_ra4e2-pinctrl.dtsi b/boards/renesas/ek_ra4e2/ek_ra4e2-pinctrl.dtsi new file mode 100644 index 00000000000..851d8543bee --- /dev/null +++ b/boards/renesas/ek_ra4e2/ek_ra4e2-pinctrl.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci0_default: sci0_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; diff --git a/boards/renesas/ek_ra4e2/ek_ra4e2.dts b/boards/renesas/ek_ra4e2/ek_ra4e2.dts new file mode 100644 index 00000000000..e371198e6ed --- /dev/null +++ b/boards/renesas/ek_ra4e2/ek_ra4e2.dts @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include "ek_ra4e2-pinctrl.dtsi" + +/ { + model = "Renesas EK-RA4E2"; + compatible = "renesas,ra4e2", "renesas,ra"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + leds { + compatible = "gpio-leds"; + led1: led1 { + gpios = <&ioport2 7 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + led2: led2 { + gpios = <&ioport1 4 GPIO_ACTIVE_HIGH>; + label = "LED2"; + }; + led3: led3 { + gpios = <&ioport1 12 GPIO_ACTIVE_HIGH>; + label = "LED3"; + }; + }; + + aliases { + led0 = &led1; + }; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&pll { + source = ; + div = ; + mul = <10 0>; + status = "okay"; +}; + +&sci0 { + pinctrl-0 = <&sci0_default>; + pinctrl-names = "default"; + status = "okay"; + uart0: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&ioport1 { + status = "okay"; +}; + +&ioport2 { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra4e2/ek_ra4e2.yaml b/boards/renesas/ek_ra4e2/ek_ra4e2.yaml new file mode 100644 index 00000000000..bceab6ca960 --- /dev/null +++ b/boards/renesas/ek_ra4e2/ek_ra4e2.yaml @@ -0,0 +1,12 @@ +identifier: ek_ra4e2 +name: Renesas EK-RA4E2 +type: mcu +arch: arm +ram: 40 +flash: 128 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - uart diff --git a/boards/renesas/ek_ra4e2/ek_ra4e2_defconfig b/boards/renesas/ek_ra4e2/ek_ra4e2_defconfig new file mode 100644 index 00000000000..ceaa9b32580 --- /dev/null +++ b/boards/renesas/ek_ra4e2/ek_ra4e2_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=100000000 + +# Enable GPIO +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_UART_CONSOLE=y +CONFIG_CONSOLE=y + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/ek_ra4m2/Kconfig.ek_ra4m2 b/boards/renesas/ek_ra4m2/Kconfig.ek_ra4m2 new file mode 100644 index 00000000000..bd762fb2bd9 --- /dev/null +++ b/boards/renesas/ek_ra4m2/Kconfig.ek_ra4m2 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EK_RA4M2 + select SOC_R7FA4M2AD3CFP diff --git a/boards/renesas/ek_ra4m2/board.cmake b/boards/renesas/ek_ra4m2/board.cmake new file mode 100644 index 00000000000..f0faf6c179a --- /dev/null +++ b/boards/renesas/ek_ra4m2/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R7FA4M2AD") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/ek_ra4m2/board.yml b/boards/renesas/ek_ra4m2/board.yml new file mode 100644 index 00000000000..c19484eff8a --- /dev/null +++ b/boards/renesas/ek_ra4m2/board.yml @@ -0,0 +1,5 @@ +board: + name: ek_ra4m2 + vendor: renesas + socs: + - name: r7fa4m2ad3cfp diff --git a/boards/renesas/ek_ra4m2/doc/ek-ra4m2-board.webp b/boards/renesas/ek_ra4m2/doc/ek-ra4m2-board.webp new file mode 100644 index 00000000000..6f83ef7274a Binary files /dev/null and b/boards/renesas/ek_ra4m2/doc/ek-ra4m2-board.webp differ diff --git a/boards/renesas/ek_ra4m2/doc/index.rst b/boards/renesas/ek_ra4m2/doc/index.rst new file mode 100644 index 00000000000..833768d6d16 --- /dev/null +++ b/boards/renesas/ek_ra4m2/doc/index.rst @@ -0,0 +1,165 @@ +.. _ek_ra4m2: + +RA4M2 Evaluation Kit +#################### + +Overview +******** + +The Renesas RA4M2 group of 32-bit microcontrollers (MCUs) uses the high-performance Arm +Cortex®-M33 core. In concert with the secure crypto engine, it offers secure element +functionality. The RA4M2 is built on a highly efficient 40nm process, built on FreeRTOS—and +is expandable to use other RTOSes and middleware. The RA4M2 is suitable for IoT applications +requiring vast communication options, future proof security, large embedded RAM, and low +active power consumption down to 81µA/MHz running the CoreMark® algorithm from Flash. + +The MCU in this series incorporates a high-performance Arm Cortex®-M33 core running up to +100 MHz with the following features: + +**Renesas RA4M2 Microcontroller Group** +- R7FA4M2AD3CFP +- 100-pin LQFP package +- 100 MHz Arm® Cortex®-M33 core +- 512 kB Code Flash, 128 KB SRAM +- Native pin access through 4 x 28-pin male headers +- MCU current measurement points for precision current consumption measurement +- Multiple clock sources - RA MCU oscillator and sub-clock oscillator crystals, providing +precision 24.000 MHz and 32,768 Hz reference clock. Additional low-precision clocks are +available internal to the RA MCU + +**System Control and Ecosystem Access** +- USB Full Speed Host and Device (micro AB connector) +- Three 5 V input sources + + - USB (Debug, Full Speed) + - External power supply (using surface mount clamp test points and power input vias) + +- Three Debug modes + + - Debug on-board (SWD) + - Debug in (ETM, SWD, and JTAG) + - Debug out (SWD) + +- User LEDs and buttons + + - Three User LEDs (red, blue, green) + - Power LED (white) indicating availability of regulated power + - Debug LED (yellow) indicating the debug connection + - Two User buttons + - One Reset button + +- Five most popular ecosystems expansions + + - 2 Seeed Grove® system (I2C/Analog) connectors + - SparkFun® Qwiic® connector + - 2 Digilent PmodTM (SPI and UART) connectors + - ArduinoTM (Uno R3) connector + - MikroElektronikaTM mikroBUS connector + +- MCU boot configuration jumper + +**Special Feature Access** +- 32 MB (256 Mb) External Quad-SPI Flash + +.. figure:: ek-ra4m2-board.webp + :align: center + :alt: RA4M2 Evaluation Kit + + EK-RA4M2 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) + +Hardware +******** +Detail Hardware feature for the RA4M2 MCU group can be found at `RA4M2 Group User's Manual Hardware`_ + +.. figure:: ra4m2-block-diagram.webp + :width: 442px + :align: center + :alt: RA4M2 MCU group feature + + RA4M2 Block diagram (Credit: Renesas Electronics Corporation) + +Detail Hardware feature for the EK-RA4M2 MCU can be found at `EK-RA4M2 - User's Manual`_ + +Supported Features +================== + +The below features are currently supported on Zephyr OS for EK-RA4M2 board: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock control | ++-----------+------------+----------------------+ + +Other hardware features are currently not supported by the port. + +Programming and Debugging +************************* + +Applications for the ``ek_ra4m2`` board target configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +Program can be flashed to EK-RA4M2 via the on-board SEGGER J-Link debugger. +SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ + +To flash the program to board + + 1. Connect to J-Link OB via USB port to host PC + + 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA4M2 - User's Manual`_ + + 3. Execute west command + + .. code-block:: console + + west flash -r jlink + +Debugging +========= + +You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface + +Once downloaded and installed, open Segger Ozone and configure the debug project +like so: + +* Target Device: R7FA4M2AD +* Target Interface: SWD +* Target Interface Speed: 4 MHz +* Host Interface: USB +* Program File: + +**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later +version of Segger Ozone + +References +********** +- `EK-RA4M2 Website`_ +- `RA4M2 MCU group Website`_ + +.. _EK-RA4M2 Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra4m2-evaluation-kit-ra4m2-mcu-group + +.. _RA4M2 MCU group Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra4m2-100mhz-arm-cortex-m33-trustzone-high-integration-lowest-active-power-consumption + +.. _EK-RA4M2 - User's Manual: + https://www.renesas.com/us/en/document/mat/ek-ra4m2-v1-users-manual + +.. _RA4M2 Group User's Manual Hardware: + https://www.renesas.com/us/en/document/man/ra4m2-group-users-manual-hardware + +.. _Segger Ozone Download: + https://www.segger.com/downloads/jlink#Ozone diff --git a/boards/renesas/ek_ra4m2/doc/ra4m2-block-diagram.webp b/boards/renesas/ek_ra4m2/doc/ra4m2-block-diagram.webp new file mode 100644 index 00000000000..c902d3d4d3f Binary files /dev/null and b/boards/renesas/ek_ra4m2/doc/ra4m2-block-diagram.webp differ diff --git a/boards/renesas/ek_ra4m2/ek_ra4m2-pinctrl.dtsi b/boards/renesas/ek_ra4m2/ek_ra4m2-pinctrl.dtsi new file mode 100644 index 00000000000..851d8543bee --- /dev/null +++ b/boards/renesas/ek_ra4m2/ek_ra4m2-pinctrl.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci0_default: sci0_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; diff --git a/boards/renesas/ek_ra4m2/ek_ra4m2.dts b/boards/renesas/ek_ra4m2/ek_ra4m2.dts new file mode 100644 index 00000000000..49f35db2e83 --- /dev/null +++ b/boards/renesas/ek_ra4m2/ek_ra4m2.dts @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include "ek_ra4m2-pinctrl.dtsi" + +/ { + model = "Renesas EK-RA4M2"; + compatible = "renesas,ra4m2", "renesas,ra"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + leds { + compatible = "gpio-leds"; + led1: led1 { + gpios = <&ioport4 15 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + led2: led2 { + gpios = <&ioport4 4 GPIO_ACTIVE_HIGH>; + label = "LED2"; + }; + led3: led3 { + gpios = <&ioport4 5 GPIO_ACTIVE_HIGH>; + label = "LED3"; + }; + }; + + aliases { + led0 = &led1; + }; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&pll { + source = ; + div = ; + mul = <25 0>; + status = "okay"; +}; + +&sci0 { + pinctrl-0 = <&sci0_default>; + pinctrl-names = "default"; + status = "okay"; + uart0: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&ioport4 { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra4m2/ek_ra4m2.yaml b/boards/renesas/ek_ra4m2/ek_ra4m2.yaml new file mode 100644 index 00000000000..d61c6bf05fe --- /dev/null +++ b/boards/renesas/ek_ra4m2/ek_ra4m2.yaml @@ -0,0 +1,12 @@ +identifier: ek_ra4m2 +name: Renesas EK-RA4M2 +type: mcu +arch: arm +ram: 128 +flash: 512 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - uart diff --git a/boards/renesas/ek_ra4m2/ek_ra4m2_defconfig b/boards/renesas/ek_ra4m2/ek_ra4m2_defconfig new file mode 100644 index 00000000000..ceaa9b32580 --- /dev/null +++ b/boards/renesas/ek_ra4m2/ek_ra4m2_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=100000000 + +# Enable GPIO +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_UART_CONSOLE=y +CONFIG_CONSOLE=y + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/ek_ra4m3/Kconfig.ek_ra4m3 b/boards/renesas/ek_ra4m3/Kconfig.ek_ra4m3 new file mode 100644 index 00000000000..5060f6a325e --- /dev/null +++ b/boards/renesas/ek_ra4m3/Kconfig.ek_ra4m3 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EK_RA4M3 + select SOC_R7FA4M3AF3CFB diff --git a/boards/renesas/ek_ra4m3/board.cmake b/boards/renesas/ek_ra4m3/board.cmake new file mode 100644 index 00000000000..98f1f87f5b7 --- /dev/null +++ b/boards/renesas/ek_ra4m3/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R7FA4M3AF") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/ek_ra4m3/board.yml b/boards/renesas/ek_ra4m3/board.yml new file mode 100644 index 00000000000..30b3b39ac4e --- /dev/null +++ b/boards/renesas/ek_ra4m3/board.yml @@ -0,0 +1,5 @@ +board: + name: ek_ra4m3 + vendor: renesas + socs: + - name: r7fa4m3af3cfb diff --git a/boards/renesas/ek_ra4m3/doc/ek-ra4m3-board.webp b/boards/renesas/ek_ra4m3/doc/ek-ra4m3-board.webp new file mode 100644 index 00000000000..998092d8171 Binary files /dev/null and b/boards/renesas/ek_ra4m3/doc/ek-ra4m3-board.webp differ diff --git a/boards/renesas/ek_ra4m3/doc/index.rst b/boards/renesas/ek_ra4m3/doc/index.rst new file mode 100644 index 00000000000..07db2061617 --- /dev/null +++ b/boards/renesas/ek_ra4m3/doc/index.rst @@ -0,0 +1,167 @@ +.. _ek_ra4m3: + +RA4M3 Evaluation Kit +#################### + +Overview +******** + +The Renesas RA4M3 group of 32-bit microcontrollers (MCUs) uses the high-performance +Arm® Cortex®-M33 core with TrustZone. In concert with the secure crypto engine, it +offers secure element functionality. The RA4M3 is built on a highly efficient 40nm +process, built on FreeRTOS—and is expandable to use other RTOSes and middleware. +The RA4M3 is suitable for IoT applications requiring vast communication options, future +proof security, large embedded RAM, and low active power consumption down to 119µA/MHz +running the CoreMark® algorithm from Flash. + +The MCU in this series incorporates a high-performance Arm Cortex®-M33 core running up to +100 MHz with the following features: + +**MCU Native Pin Access** +- R7FA4M3AF3CFB +- 100-pin LQFP package +- 100 MHz Arm® Cortex®-M33 core +- 1 MB Code Flash, 128 KB SRAM +- 144 pins, LQFP package +- Native pin access through 4 x 40-pin male headers +- MCU and USB current measurement points for precision current consumption measurement +- Multiple clock sources - RA MCU oscillator and sub-clock oscillator crystals, providing precision +24.000 MHz and 32,768 Hz reference clock. Additional low-precision clocks are available internal to the +RA MCU + +**System Control and Ecosystem Access** +- USB Full Speed Host and Device (micro AB connector) +- Three 5 V input sources + + - USB (Debug, Full Speed) + - External power supply (using surface mount clamp test points and power input vias) + + Three Debug modes + + - Debug on-board (SWD) + - Debug in (ETM, SWD, and JTAG) + - Debug out (SWD) + + User LEDs and buttons + + - Three User LEDs (red, blue, green) + - Power LED (white) indicating availability of regulated power + - Debug LED (yellow) indicating the debug connection + - Two User buttons + - One Reset button + +- Five most popular ecosystems expansions + + - 2 Seeed Grove® system (I2C/Analog) connectors + - SparkFun® Qwiic® connector + - 2 Digilent PmodTM (SPI and UART) connectors + - ArduinoTM (Uno R3) connector + - MikroElektronikaTM mikroBUS connector + +- MCU boot configuration jumper + +**Special Feature Access** +- 32 MB (256 Mb) External Quad-SPI Flash + +.. figure:: ek-ra4m3-board.webp + :align: center + :alt: RA4M3 Evaluation Kit + + EK-RA4M3 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) + +Hardware +******** +Detail Hardware feature for the RA4M3 MCU group can be found at `RA4M3 Group User's Manual Hardware`_ + +.. figure:: ra4m3-block-diagram.webp + :width: 442px + :align: center + :alt: RA4M3 MCU group feature + + RA4M3 Block diagram (Credit: Renesas Electronics Corporation) + +Detail Hardware feature for the EK-RA4M3 MCU can be found at `EK-RA4M3 - User's Manual`_ + +Supported Features +================== + +The below features are currently supported on Zephyr OS for EK-RA4M3 board: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock control | ++-----------+------------+----------------------+ + +Other hardware features are currently not supported by the port. + +Programming and Debugging +************************* + +Applications for the ``ek_ra4m3`` board target configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +Program can be flashed to EK-RA4M3 via the on-board SEGGER J-Link debugger. +SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ + +To flash the program to board + + 1. Connect to J-Link OB via USB port to host PC + + 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA4M3 - User's Manual`_ + + 3. Execute west command + + .. code-block:: console + + west flash -r jlink + +Debugging +========= + +You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface + +Once downloaded and installed, open Segger Ozone and configure the debug project +like so: + +* Target Device: R7FA4M3AD +* Target Interface: SWD +* Target Interface Speed: 4 MHz +* Host Interface: USB +* Program File: + +**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later +version of Segger Ozone + +References +********** +- `EK-RA4M3 Website`_ +- `RA4M3 MCU group Website`_ + +.. _EK-RA4M3 Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra4m3-evaluation-kit-ra4m3-mcu-group + +.. _RA4M3 MCU group Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra4m3-100mhz-arm-cortex-m33-trustzone-high-integration-rich-connectivity + +.. _EK-RA4M3 - User's Manual: + https://www.renesas.com/us/en/document/mat/ek-ra4m3-v1-users-manual + +.. _RA4M3 Group User's Manual Hardware: + https://www.renesas.com/us/en/document/man/ra4m3-group-users-manual-hardware + +.. _Segger Ozone Download: + https://www.segger.com/downloads/jlink#Ozone diff --git a/boards/renesas/ek_ra4m3/doc/ra4m3-block-diagram.webp b/boards/renesas/ek_ra4m3/doc/ra4m3-block-diagram.webp new file mode 100644 index 00000000000..d3d70ebcd38 Binary files /dev/null and b/boards/renesas/ek_ra4m3/doc/ra4m3-block-diagram.webp differ diff --git a/boards/renesas/ek_ra4m3/ek_ra4m3-pinctrl.dtsi b/boards/renesas/ek_ra4m3/ek_ra4m3-pinctrl.dtsi new file mode 100644 index 00000000000..851d8543bee --- /dev/null +++ b/boards/renesas/ek_ra4m3/ek_ra4m3-pinctrl.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci0_default: sci0_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; diff --git a/boards/renesas/ek_ra4m3/ek_ra4m3.dts b/boards/renesas/ek_ra4m3/ek_ra4m3.dts new file mode 100644 index 00000000000..f076510018e --- /dev/null +++ b/boards/renesas/ek_ra4m3/ek_ra4m3.dts @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include "ek_ra4m3-pinctrl.dtsi" + +/ { + model = "Renesas EK-RA4M3"; + compatible = "renesas,ra4m3", "renesas,ra"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + leds { + compatible = "gpio-leds"; + led1: led1 { + gpios = <&ioport4 15 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + led2: led2 { + gpios = <&ioport4 4 GPIO_ACTIVE_HIGH>; + label = "LED2"; + }; + led3: led3 { + gpios = <&ioport4 0 GPIO_ACTIVE_HIGH>; + label = "LED3"; + }; + }; + + aliases { + led0 = &led1; + }; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&pll { + source = ; + div = ; + mul = <25 0>; + status = "okay"; +}; + +&sci0 { + pinctrl-0 = <&sci0_default>; + pinctrl-names = "default"; + status = "okay"; + uart0: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&ioport4 { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra4m3/ek_ra4m3.yaml b/boards/renesas/ek_ra4m3/ek_ra4m3.yaml new file mode 100644 index 00000000000..e05b8e804da --- /dev/null +++ b/boards/renesas/ek_ra4m3/ek_ra4m3.yaml @@ -0,0 +1,12 @@ +identifier: ek_ra4m3 +name: Renesas EK-RA4M3 +type: mcu +arch: arm +ram: 128 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - uart diff --git a/boards/renesas/ek_ra4m3/ek_ra4m3_defconfig b/boards/renesas/ek_ra4m3/ek_ra4m3_defconfig new file mode 100644 index 00000000000..ceaa9b32580 --- /dev/null +++ b/boards/renesas/ek_ra4m3/ek_ra4m3_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=100000000 + +# Enable GPIO +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_UART_CONSOLE=y +CONFIG_CONSOLE=y + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/ek_ra4w1/Kconfig.ek_ra4w1 b/boards/renesas/ek_ra4w1/Kconfig.ek_ra4w1 new file mode 100644 index 00000000000..a2f855a2b3c --- /dev/null +++ b/boards/renesas/ek_ra4w1/Kconfig.ek_ra4w1 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EK_RA4W1 + select SOC_R7FA4W1AD2CNG diff --git a/boards/renesas/ek_ra4w1/board.cmake b/boards/renesas/ek_ra4w1/board.cmake new file mode 100644 index 00000000000..6a1b1617cb8 --- /dev/null +++ b/boards/renesas/ek_ra4w1/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R7FA4W1AD") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/ek_ra4w1/board.yml b/boards/renesas/ek_ra4w1/board.yml new file mode 100644 index 00000000000..709a8435475 --- /dev/null +++ b/boards/renesas/ek_ra4w1/board.yml @@ -0,0 +1,5 @@ +board: + name: ek_ra4w1 + vendor: renesas + socs: + - name: r7fa4w1ad2cng diff --git a/boards/renesas/ek_ra4w1/doc/ek-ra4w1-board.webp b/boards/renesas/ek_ra4w1/doc/ek-ra4w1-board.webp new file mode 100644 index 00000000000..9a1e2b9be43 Binary files /dev/null and b/boards/renesas/ek_ra4w1/doc/ek-ra4w1-board.webp differ diff --git a/boards/renesas/ek_ra4w1/doc/index.rst b/boards/renesas/ek_ra4w1/doc/index.rst new file mode 100644 index 00000000000..d20c5c27390 --- /dev/null +++ b/boards/renesas/ek_ra4w1/doc/index.rst @@ -0,0 +1,157 @@ +.. _ek_ra4w1: + +RA4W1 Evaluation Kit +#################### + +Overview +******** + +The Renesas RA4W1 is the first Bluetooth® 5.0 Low Energy fully compliant with 2Mbit High-Throughput +(HT) and Long Range support in a single chip MCU of Renesas RA4 product series for IoT applications +that require a high-performance Arm® Cortex®-M4 core at a very attractive price point. The RA4W1 MCU +has full function support for Bluetooth 5.0 Low Energy long-range and mesh networking, and provides +excellent reception performance. RA4W1 is geared towards IoT application requiring Security, large +embedded RAM and low power consumption. + +**MCU Native Pin Access** +- R7FA4W1AD2CNG +- QFN-56 package +- On-chip memory: 512-KB ROM, 96-KB RAM, 8-KB data flash memory + +**Power-supply voltage** +- USB connector: 5-V input +- Power-supply IC: 5-V input, 3.3-V output +- External power-supply header*1: 3.3-V input, 2 pins x 1 + +**Main clock** +- Crystal oscillator (surface-mount technology (SMT)) for the main system clock +- Crystal oscillator or ceramic resonator (lead type) for the main system clock + +**Sub-clock** +- Crystal oscillator (SMT) for the sub-clock + +**Bluetooth Low Energy** +- Bluetooth Low Energy (BLE) circuit x1 +- Range of frequency: 2402 to 2480 MHz +- Maximum transmission output power: 4 dBm (in 4-dBm output mode) +- Output variation: +2 dB + +**Push switches** +- Reset switch x 1 +- User switch x 1 + +**LED** +- Power indicator: green x 1 +- User: green x 2 +- ACT LED: green x 1 + +**Conetivity** +- Connector for an on-board emulator: USB Micro-B +- Connector for a USB serial-conversion interface: USB Micro-B +- Pmod™ connector: Angle type, 12 pins +- Arduino™ UNO connectors + +- Emulator reset switch + +.. figure:: ek-ra4w1-board.webp + :align: center + :alt: RA4W1 Evaluation Kit + + EK-RA4W1 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) + +Hardware +******** +Detail Hardware feature for the RA4W1 MCU group can be found at `RA4W1 Group User's Manual Hardware`_ + +.. figure:: ra4w1-block-diagram.webp + :width: 442px + :align: center + :alt: RA4W1 MCU group feature + + RA4W1 Block diagram (Credit: Renesas Electronics Corporation) + +Detail Hardware feature for the EK-RA4W1 MCU can be found at `EK-RA4W1 - User's Manual`_ + +Supported Features +================== + +The below features are currently supported on Zephyr OS for EK-RA4W1 board: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock control | ++-----------+------------+----------------------+ + +Other hardware features are currently not supported by the port. + +Programming and Debugging +************************* + +Applications for the ``ek_ra4w1`` board target configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +Program can be flashed to EK-RA4W1 via the on-board SEGGER J-Link debugger. +SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ + +To flash the program to board + + 1. Connect to J-Link OB via USB port to host PC + + 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA4W1 - User's Manual`_ + + 3. Execute west command + + .. code-block:: console + + west flash -r jlink + +Debugging +========= + +You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface + +Once downloaded and installed, open Segger Ozone and configure the debug project +like so: + +* Target Device: R7FA4W1AD +* Target Interface: SWD +* Target Interface Speed: 4 MHz +* Host Interface: USB +* Program File: + +**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later +version of Segger Ozone + +References +********** +- `EK-RA4W1 Website`_ +- `RA4W1 MCU group Website`_ + +.. _EK-RA4W1 Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra4w1-evaluation-kit-ra4w1-mcu-group + +.. _RA4W1 MCU group Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra4w1-low-energy-single-chip-32-bit-microcontrollers-48mhz-bluetooth-50 + +.. _EK-RA4W1 - User's Manual: + https://www.renesas.com/us/en/document/man/ek-ra4w1-users-manual + +.. _RA4W1 Group User's Manual Hardware: + https://www.renesas.com/us/en/document/man/renesas-ra4w1-group-users-manual-hardware + +.. _Segger Ozone Download: + https://www.segger.com/downloads/jlink#Ozone diff --git a/boards/renesas/ek_ra4w1/doc/ra4w1-block-diagram.webp b/boards/renesas/ek_ra4w1/doc/ra4w1-block-diagram.webp new file mode 100644 index 00000000000..d569b021488 Binary files /dev/null and b/boards/renesas/ek_ra4w1/doc/ra4w1-block-diagram.webp differ diff --git a/boards/renesas/ek_ra4w1/ek_ra4w1-pinctrl.dtsi b/boards/renesas/ek_ra4w1/ek_ra4w1-pinctrl.dtsi new file mode 100644 index 00000000000..3c01cb6bec4 --- /dev/null +++ b/boards/renesas/ek_ra4w1/ek_ra4w1-pinctrl.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci0_default: sci0_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; diff --git a/boards/renesas/ek_ra4w1/ek_ra4w1.dts b/boards/renesas/ek_ra4w1/ek_ra4w1.dts new file mode 100644 index 00000000000..7d764631e03 --- /dev/null +++ b/boards/renesas/ek_ra4w1/ek_ra4w1.dts @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include "ek_ra4w1-pinctrl.dtsi" + +/ { + model = "Renesas EK-RA4W1"; + compatible = "renesas,ra4w1", "renesas,ra"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + leds { + compatible = "gpio-leds"; + led1: led1 { + gpios = <&ioport1 6 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + + led2: led2 { + gpios = <&ioport4 4 GPIO_ACTIVE_HIGH>; + label = "LED2"; + }; + }; + + aliases { + led0 = &led1; + }; +}; + +&subclk { + status = "okay"; +}; + +&sci0 { + pinctrl-0 = <&sci0_default>; + pinctrl-names = "default"; + status = "okay"; + uart0: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&ioport1 { + status = "okay"; +}; + +&ioport4 { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra4w1/ek_ra4w1.yaml b/boards/renesas/ek_ra4w1/ek_ra4w1.yaml new file mode 100644 index 00000000000..f31bcd0a7bc --- /dev/null +++ b/boards/renesas/ek_ra4w1/ek_ra4w1.yaml @@ -0,0 +1,12 @@ +identifier: ek_ra4w1 +name: Renesas EK-RA4W1 +type: mcu +arch: arm +ram: 96 +flash: 512 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - uart diff --git a/boards/renesas/ek_ra4w1/ek_ra4w1_defconfig b/boards/renesas/ek_ra4w1/ek_ra4w1_defconfig new file mode 100644 index 00000000000..92542b8ab9c --- /dev/null +++ b/boards/renesas/ek_ra4w1/ek_ra4w1_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32000000 + +# Enable GPIO +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_UART_CONSOLE=y +CONFIG_CONSOLE=y + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/ek_ra6e2/Kconfig.ek_ra6e2 b/boards/renesas/ek_ra6e2/Kconfig.ek_ra6e2 new file mode 100644 index 00000000000..06f6e754a08 --- /dev/null +++ b/boards/renesas/ek_ra6e2/Kconfig.ek_ra6e2 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EK_RA6E2 + select SOC_R7FA6E2BB3CFM diff --git a/boards/renesas/ek_ra6e2/board.cmake b/boards/renesas/ek_ra6e2/board.cmake new file mode 100644 index 00000000000..368e10209f9 --- /dev/null +++ b/boards/renesas/ek_ra6e2/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R7FA6E2BB") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/ek_ra6e2/board.yml b/boards/renesas/ek_ra6e2/board.yml new file mode 100644 index 00000000000..972476c9b2e --- /dev/null +++ b/boards/renesas/ek_ra6e2/board.yml @@ -0,0 +1,5 @@ +board: + name: ek_ra6e2 + vendor: renesas + socs: + - name: r7fa6e2bb3cfm diff --git a/boards/renesas/ek_ra6e2/doc/ek-ra6e2-board.webp b/boards/renesas/ek_ra6e2/doc/ek-ra6e2-board.webp new file mode 100644 index 00000000000..56ebb4c77e7 Binary files /dev/null and b/boards/renesas/ek_ra6e2/doc/ek-ra6e2-board.webp differ diff --git a/boards/renesas/ek_ra6e2/doc/index.rst b/boards/renesas/ek_ra6e2/doc/index.rst new file mode 100644 index 00000000000..aad21a93ea4 --- /dev/null +++ b/boards/renesas/ek_ra6e2/doc/index.rst @@ -0,0 +1,165 @@ +.. _ek_ra6e2: + +RA6E2 Evaluation Kit +#################### + +Overview +******** + +The EK-RA6E2, an Evaluation Kit for RA6E2 MCU Group, enables users to +seamlessly evaluate the features of the RA6E2 MCU group and develop +embedded systems applications using Flexible Software Package (FSP) +and e2 studio IDE. The users can use rich on-board features along with +their choice of popular ecosystems add-ons to bring their big ideas to life + +The key features of the EK-RA6E2 board are categorized in three groups as follow: + +**MCU Native Pin Access** + +- 200MHz Arm Cortex-M33 based RA6E2 MCU in 64 pins, LQFP package +- 256 kB Code Flash, 40 kB SRAM +- Native pin access through 2 x 14-pin and 1 x 40-pin male headers +- MCU current measurement points for precision current consumption measurement +- Multiple clock sources - RA6E2 MCU oscillator and sub-clock oscillator crystals, + providing precision 20.000 MHz and 32,768 Hz reference clock. + Additional low precision clocks are avaialbe internal to the RA6E2 MCU + +**System Control and Ecosystem Access** + +- USB Full Speed Host and Device (micro-AB connector) +- Three 5V input sources + + - USB (Debug, Full Speed) + - External power supply (using surface mount clamp test points and J31 through holes) + +- Three Debug modes + + - Debug on-board (SWD) + - Debug in (SWD) + - Debug out (JTAG, SWD) + +- User LEDs and buttons + + - Three User LEDs (red, blue, green) + - Power LED (white) indicating availability of regulated power + - Debug LED (yellow) indicating the debug connection + - Two User buttons + - One Reset button + +- Five most popular ecosystems expansions + + - Two Seeed Grove system (I3C/Analog) connectors + - One SparkFun Qwiic connector + - Two Digilent Pmod (SPI and UART) connectors + - Arduino (Uno R3) connector + - MikroElektronika mikroBUS connector + +- MCU boot configuration jumper + +**Special Feature Access** + +- 16 Mb (128 Mb) External Quad-SPI Flash +- CAN (3-pin header) + +.. figure:: ek-ra6e2-board.webp + :align: center + :alt: RA6E2 Evaluation Kit + + EK-RA6E2 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) + +Hardware +******** +Detailed hardware feature for the RA6E2 MCU group can be found at `RA6E2 Group User's Manual Hardware`_ + +.. figure:: ra6e2-block-diagram.webp + :width: 442px + :align: center + :alt: RA6E2 MCU group feature + + RA6E2 Block diagram (Credit: Renesas Electronics Corporation) + +Detailed hardware feature for the EK-RA6E2 MCU can be found at `EK-RA6E2 - User's Manual`_ + +Supported Features +================== + +The below features are currently supported on Zephyr OS for EK-RA6E2 board: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock control | ++-----------+------------+----------------------+ + +Other hardware features are currently not supported by the port. + +Programming and Debugging +************************* + +Applications for the ``ek_ra6e2`` board target configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +Program can be flashed to EK-RA6E2 via the on-board SEGGER J-Link debugger. +SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ + +To flash the program to board + + 1. Connect to J-Link OB via USB port to host PC + + 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6E2 - User's Manual`_ + + 3. Execute west command + + .. code-block:: console + + west flash -r jlink + +Debugging +========= + +You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface + +Once downloaded and installed, open Segger Ozone and configure the debug project +like so: + +* Target Device: R7FA6E2BB +* Target Interface: SWD +* Target Interface Speed: 4 MHz +* Host Interface: USB +* Program File: + +**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later +version of Segger Ozone + +References +********** +- `EK-RA6E2 Website`_ +- `RA6E2 MCU group Website`_ + +.. _EK-RA6E2 Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6e2-evaluation-kit-ra6e2-mcu-group + +.. _RA6E2 MCU group Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra6e2-entry-line-200mhz-arm-cortex-m33-general-purpose-microcontroller + +.. _EK-RA6E2 - User's Manual: + https://www.renesas.com/us/en/document/mat/ek-ra6e2-v1-users-manual + +.. _RA6E2 Group User's Manual Hardware: + https://www.renesas.com/us/en/document/mah/ra6e2-group-users-manual-hardware + +.. _Segger Ozone Download: + https://www.segger.com/downloads/jlink#Ozone diff --git a/boards/renesas/ek_ra6e2/doc/ra6e2-block-diagram.webp b/boards/renesas/ek_ra6e2/doc/ra6e2-block-diagram.webp new file mode 100644 index 00000000000..7eeb1bc516f Binary files /dev/null and b/boards/renesas/ek_ra6e2/doc/ra6e2-block-diagram.webp differ diff --git a/boards/renesas/ek_ra6e2/ek_ra6e2-pinctrl.dtsi b/boards/renesas/ek_ra6e2/ek_ra6e2-pinctrl.dtsi new file mode 100644 index 00000000000..851d8543bee --- /dev/null +++ b/boards/renesas/ek_ra6e2/ek_ra6e2-pinctrl.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci0_default: sci0_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; diff --git a/boards/renesas/ek_ra6e2/ek_ra6e2.dts b/boards/renesas/ek_ra6e2/ek_ra6e2.dts new file mode 100644 index 00000000000..682aafcd006 --- /dev/null +++ b/boards/renesas/ek_ra6e2/ek_ra6e2.dts @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +#include "ek_ra6e2-pinctrl.dtsi" + +/ { + model = "Renesas EK-RA6E2"; + compatible = "renesas,ra6e2", "renesas,ra"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + leds { + compatible = "gpio-leds"; + led1: led1 { + gpios = <&ioport2 7 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + led2: led2 { + gpios = <&ioport4 0 GPIO_ACTIVE_HIGH>; + label = "LED2"; + }; + led3: led3 { + gpios = <&ioport1 13 GPIO_ACTIVE_HIGH>; + label = "LED3"; + }; + }; + + aliases { + led0 = &led1; + }; +}; + +&sci0 { + pinctrl-0 = <&sci0_default>; + pinctrl-names = "default"; + status = "okay"; + uart0: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&ioport1 { + status = "okay"; +}; + +&ioport2 { + status = "okay"; +}; + +&ioport4 { + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "application"; + reg = <0x00000000 DT_SIZE_K(128)>; + }; + + storage_partition: partition@20000 { + label = "storage"; + reg = <0x20000 DT_SIZE_K(128)>; + }; + }; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&pll { + source = ; + div = ; + mul = <10 0>; + status = "okay"; +}; diff --git a/boards/renesas/ek_ra6e2/ek_ra6e2.yaml b/boards/renesas/ek_ra6e2/ek_ra6e2.yaml new file mode 100644 index 00000000000..dcb71bda519 --- /dev/null +++ b/boards/renesas/ek_ra6e2/ek_ra6e2.yaml @@ -0,0 +1,11 @@ +identifier: ek_ra6e2 +name: Renesas EK-RA6E2 +type: mcu +arch: arm +ram: 40 +flash: 256 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio diff --git a/boards/renesas/ek_ra6e2/ek_ra6e2_defconfig b/boards/renesas/ek_ra6e2/ek_ra6e2_defconfig new file mode 100644 index 00000000000..92bb425cfa8 --- /dev/null +++ b/boards/renesas/ek_ra6e2/ek_ra6e2_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000 + +# Enable GPIO +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_UART_CONSOLE=y +CONFIG_CONSOLE=y + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/ek_ra6m1/Kconfig.ek_ra6m1 b/boards/renesas/ek_ra6m1/Kconfig.ek_ra6m1 new file mode 100644 index 00000000000..c21e240aeaa --- /dev/null +++ b/boards/renesas/ek_ra6m1/Kconfig.ek_ra6m1 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EK_RA6M1 + select SOC_R7FA6M1AD3CFP diff --git a/boards/renesas/ek_ra6m1/board.cmake b/boards/renesas/ek_ra6m1/board.cmake new file mode 100644 index 00000000000..1a34ff99958 --- /dev/null +++ b/boards/renesas/ek_ra6m1/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R7FA6M1AD") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/ek_ra6m1/board.yml b/boards/renesas/ek_ra6m1/board.yml new file mode 100644 index 00000000000..db68eb8a068 --- /dev/null +++ b/boards/renesas/ek_ra6m1/board.yml @@ -0,0 +1,5 @@ +board: + name: ek_ra6m1 + vendor: renesas + socs: + - name: r7fa6m1ad3cfp diff --git a/boards/renesas/ek_ra6m1/doc/ek-ra6m1-board.webp b/boards/renesas/ek_ra6m1/doc/ek-ra6m1-board.webp new file mode 100644 index 00000000000..438d21dc19b Binary files /dev/null and b/boards/renesas/ek_ra6m1/doc/ek-ra6m1-board.webp differ diff --git a/boards/renesas/ek_ra6m1/doc/index.rst b/boards/renesas/ek_ra6m1/doc/index.rst new file mode 100644 index 00000000000..955c87ac32b --- /dev/null +++ b/boards/renesas/ek_ra6m1/doc/index.rst @@ -0,0 +1,161 @@ +.. _ek_ra6m1: + +RA6M1 Evaluation Kit +#################### + +Overview +******** + +The Renesas RA6M1 microcontroller is the entry point to the Renesas RA6 product +series for applications that require a high-performance Arm® Cortex®-M4 core at +a very attractive price point. The RA6M1 is built on a highly efficient 40nm process +and is supported by an open and flexible ecosystem concept—the Flexible Software +Package (FSP), built on FreeRTOS—and is expandable to use other RTOSes and middleware. +The RA6M1 is suitable for IoT applications requiring security, large embedded RAM and +low power consumption. + +The key features of the EK-RA6M1 board are categorized in three groups as follow: + +**MCU Native Pin Access** +- R7FA6M1AD3CFP +- 100-pin LQFP package +- 120 MHz Arm® Cortex®-M4 core with Floating Point Unit (FPU) +- 256 KB SRAM +- 512 KB code flash memory +- 8 KB data flash memory + +**Connectivity** +- A Device USB connector for the Main MCU +- S124 MCU-based SEGGER J-Link® On-Board interface for debugging and programming of the +RA6M1 MCU. A 10-pin JTAG/SWD interface is also provided for connecting optional external +debuggers and programmers. +- Two PMOD connectors, allowing use of appropriate PMOD compliant peripheral plug-in modules for +rapid prototyping +- Pin headers for access to power and signals for the Main MCU + +**Multiple clock sources** +- Main MCU oscillator crystals, providing precision 12.000 MHz and 32,768 Hz external reference +clocks +- Additional low-precision clocks are available internal to the Main MCU + +**General purpose I/O ports** +- One jumper to allow measuring of Main MCU current +- Copper jumpers on PCB bottom side for configuration and access to selected MCU signals +**Operating voltage** +- External 5 V input through the Debug USB connector supplies the on-board power regulator to power +logic and interfaces on the board. External 5 V or 3.3 V may be also supplied through alternate +locations on the board. +- A two-color board status LED indicating availability of regulated power and connection status of the J-Link +interface. +- A red User LED, controlled by the Main MCU firmware +- A User Push-Button switch, User Capacitive Touch Button sensor, and an optional User Potentiometer, +all of which are controlled by the Main MCU firmware +- MCU reset push-button switch +- MCU boot configuration jumper + +**Special Feature Access** + +- USB Full Speed Debug and Device (micro-AB connector) + +.. figure:: ek-ra6m1-board.webp + :align: center + :alt: RA6M1 Evaluation Kit + + EK-RA6M1 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) + +Hardware +******** +Detailed hardware feature for the RA6M1 MCU group can be found at `RA6M1 Group User's Manual Hardware`_ + +.. figure:: ra6m1-block-diagram.webp + :width: 442px + :align: center + :alt: RA6M1 MCU group feature + + RA6M1 Block diagram (Credit: Renesas Electronics Corporation) + +Detailed hardware feature for the EK-RA6M1 MCU can be found at `EK-RA6M1 - User's Manual`_ + +Supported Features +================== + +The below features are currently supported on Zephyr OS for EK-RA6M1 board: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock control | ++-----------+------------+----------------------+ + +Other hardware features are currently not supported by the port. + +Programming and Debugging +************************* + +Applications for the ``ek_ra6m1`` board target configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +Program can be flashed to EK-RA6M1 via the on-board SEGGER J-Link debugger. +SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ + +To flash the program to board + + 1. Connect to J-Link OB via USB port to host PC + + 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M1 - User's Manual`_ + + 3. Execute west command + + .. code-block:: console + + west flash -r jlink + +Debugging +========= + +You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface + +Once downloaded and installed, open Segger Ozone and configure the debug project +like so: + +* Target Device: R7FA6M1AD +* Target Interface: SWD +* Target Interface Speed: 4 MHz +* Host Interface: USB +* Program File: + +**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later +version of Segger Ozone + +References +********** +- `EK-RA6M1 Website`_ +- `RA6M1 MCU group Website`_ + +.. _EK-RA6M1 Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6m1-evaluation-kit-ra6m1-mcu-group + +.. _RA6M1 MCU group Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra6m1-32-bit-microcontrollers-120mhz-optimized-entry-point-ra6-series + +.. _EK-RA6M1 - User's Manual: + https://www.renesas.com/us/en/document/mat/ek-ra6m1-v1-users-manual + +.. _RA6M1 Group User's Manual Hardware: + https://www.renesas.com/us/en/document/mah/renesas-ra6m1-group-users-manual-hardware?r=1054156 + +.. _Segger Ozone Download: + https://www.segger.com/downloads/jlink#Ozone diff --git a/boards/renesas/ek_ra6m1/doc/ra6m1-block-diagram.webp b/boards/renesas/ek_ra6m1/doc/ra6m1-block-diagram.webp new file mode 100644 index 00000000000..2f9511bf9a5 Binary files /dev/null and b/boards/renesas/ek_ra6m1/doc/ra6m1-block-diagram.webp differ diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1-pinctrl.dtsi b/boards/renesas/ek_ra6m1/ek_ra6m1-pinctrl.dtsi new file mode 100644 index 00000000000..56fa3e26b6a --- /dev/null +++ b/boards/renesas/ek_ra6m1/ek_ra6m1-pinctrl.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci8_default: sci8_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1.dts b/boards/renesas/ek_ra6m1/ek_ra6m1.dts new file mode 100644 index 00000000000..f82d0659112 --- /dev/null +++ b/boards/renesas/ek_ra6m1/ek_ra6m1.dts @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +#include "ek_ra6m1-pinctrl.dtsi" + +/ { + model = "Renesas EK-RA6M1"; + compatible = "renesas,ra6m1", "renesas,ra"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart8; + zephyr,shell-uart = &uart8; + }; + + leds { + compatible = "gpio-leds"; + led1: led1 { + gpios = <&ioport1 12 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + }; + + aliases { + led0 = &led1; + }; +}; + +&sci8 { + pinctrl-0 = <&sci8_default>; + pinctrl-names = "default"; + status = "okay"; + uart8: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&ioport1 { + status = "okay"; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&pll { + source = ; + div = ; + mul = <20 0>; + status = "okay"; +}; diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1.yaml b/boards/renesas/ek_ra6m1/ek_ra6m1.yaml new file mode 100644 index 00000000000..92e8d569db2 --- /dev/null +++ b/boards/renesas/ek_ra6m1/ek_ra6m1.yaml @@ -0,0 +1,12 @@ +identifier: ek_ra6m1 +name: Renesas EK-RA6M1 +type: mcu +arch: arm +ram: 256 +flash: 512 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - uart diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1_defconfig b/boards/renesas/ek_ra6m1/ek_ra6m1_defconfig new file mode 100644 index 00000000000..00adc77146e --- /dev/null +++ b/boards/renesas/ek_ra6m1/ek_ra6m1_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000 + +# Enable GPIO +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_CLOCK_CONTROL=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y diff --git a/boards/renesas/ek_ra6m2/Kconfig.ek_ra6m2 b/boards/renesas/ek_ra6m2/Kconfig.ek_ra6m2 new file mode 100644 index 00000000000..106137b4c4b --- /dev/null +++ b/boards/renesas/ek_ra6m2/Kconfig.ek_ra6m2 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EK_RA6M2 + select SOC_R7FA6M2AF3CFB diff --git a/boards/renesas/ek_ra6m2/board.cmake b/boards/renesas/ek_ra6m2/board.cmake new file mode 100644 index 00000000000..4ebea5664ca --- /dev/null +++ b/boards/renesas/ek_ra6m2/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R7FA6M2AF") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/ek_ra6m2/board.yml b/boards/renesas/ek_ra6m2/board.yml new file mode 100644 index 00000000000..325b1601c9a --- /dev/null +++ b/boards/renesas/ek_ra6m2/board.yml @@ -0,0 +1,5 @@ +board: + name: ek_ra6m2 + vendor: renesas + socs: + - name: r7fa6m2af3cfb diff --git a/boards/renesas/ek_ra6m2/doc/ek-ra6m2-board.webp b/boards/renesas/ek_ra6m2/doc/ek-ra6m2-board.webp new file mode 100644 index 00000000000..e58a8a11914 Binary files /dev/null and b/boards/renesas/ek_ra6m2/doc/ek-ra6m2-board.webp differ diff --git a/boards/renesas/ek_ra6m2/doc/index.rst b/boards/renesas/ek_ra6m2/doc/index.rst new file mode 100644 index 00000000000..2a5cb68d16b --- /dev/null +++ b/boards/renesas/ek_ra6m2/doc/index.rst @@ -0,0 +1,155 @@ +.. _ek_ra6m2: + +RA6M2 Evaluation Kit +#################### + +Overview +******** + +The Renesas RA6M2 microcontroller is the entry point to the Renesas RA6 product series +for applications that require a high-performance Arm® Cortex®-M4 core at a very attractive +price point. The RA6M2 is suitable for IoT applications requiring security, large embedded +RAM and low power consumption. + +The key features of the EK-RA6M2 board are categorized in three groups as follow: + +**MCU Native Pin Access** + +- 120MHz Arm Cortex-M4 based RA6M2 MCU in 144 pins, LQFP package +- Native pin access through 4 x 40-pin male headers +- MCU and USB current measurement points for precision current consumption measurement +- Multiple clock sources - RA6M2 MCU oscillator and sub-clock oscillator crystals, + providing precision 12.000 MHz and 32,768 Hz reference clock. + Additional low precision clocks are avaialbe internal to the RA6M2 MCU + +**System Control and Ecosystem Access** + +- USB Full Speed device +- 5V input through USB debug + +- Three Debug modes + + - Debug on-board (SWD) + - Debug in (SWD and JTAG) + - Debug out (SWD) + +- User LEDs and buttons + + - One User LEDs + - One User buttons + - One Reset button + +- Three most popular ecosystems expansions + + - Two Digilent Pmod (SPI and UART) connectors + - Arduino (Uno R3) connector + - MikroElektronika mikroBUS connector + +- MCU boot configuration jumper + +**Special Feature Access** + +- USB Full Speed Host and Device (micro-AB connector) + +.. figure:: ek-ra6m2-board.webp + :align: center + :alt: RA6M2 Evaluation Kit + + EK-RA6M2 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) + +Hardware +******** +Detailed hardware feature for the RA6M2 MCU group can be found at `RA6M2 Group User's Manual Hardware`_ + +.. figure:: ra6m2-block-diagram.webp + :width: 871px + :align: center + :alt: RA6M2 MCU group feature + + RA6M2 Block diagram (Credit: Renesas Electronics Corporation) + +Detailed hardware feature for the EK-RA6M2 MCU can be found at `EK-RA6M2 - User's Manual`_ + +Supported Features +================== + +The below features are currently supported on Zephyr OS for EK-RA6M2 board: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock control | ++-----------+------------+----------------------+ + +Other hardware features are currently not supported by the port. + +Programming and Debugging +************************* + +Applications for the ``ek_ra6m2`` board target configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +Program can be flashed to EK-RA6M2 via the on-board SEGGER J-Link debugger. +SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ + +To flash the program to board + + 1. Connect to J-Link OB via USB port to host PC + + 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M2 - User's Manual`_ + + 3. Execute west command + + .. code-block:: console + + west flash -r jlink + +Debugging +========= + +You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface + +Once downloaded and installed, open Segger Ozone and configure the debug project +like so: + +* Target Device: R7FA6M2AD +* Target Interface: SWD +* Target Interface Speed: 4 MHz +* Host Interface: USB +* Program File: + +**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later +version of Segger Ozone + +References +********** +- `EK-RA6M2 Website`_ +- `RA6M2 MCU group Website`_ + +.. _EK-RA6M2 Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6m2-evaluation-kit-ra6m2-mcu-group + +.. _RA6M2 MCU group Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra6m2-32-bit-microcontrollers-120mhz-medium-size-memory-integration-and-ethernet + +.. _EK-RA6M2 - User's Manual: + https://www.renesas.com/us/en/document/mat/ek-ra6m2-v1-users-manual-0 + +.. _RA6M2 Group User's Manual Hardware: + https://www.renesas.com/us/en/document/mah/renesas-ra6m2-group-users-manual-hardware + +.. _Segger Ozone Download: + https://www.segger.com/downloads/jlink#Ozone diff --git a/boards/renesas/ek_ra6m2/doc/ra6m2-block-diagram.webp b/boards/renesas/ek_ra6m2/doc/ra6m2-block-diagram.webp new file mode 100644 index 00000000000..5b7256380b5 Binary files /dev/null and b/boards/renesas/ek_ra6m2/doc/ra6m2-block-diagram.webp differ diff --git a/boards/renesas/ek_ra6m2/ek_ra6m2-pinctrl.dtsi b/boards/renesas/ek_ra6m2/ek_ra6m2-pinctrl.dtsi new file mode 100644 index 00000000000..69d920e7eda --- /dev/null +++ b/boards/renesas/ek_ra6m2/ek_ra6m2-pinctrl.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci7_default: sci7_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; diff --git a/boards/renesas/ek_ra6m2/ek_ra6m2.dts b/boards/renesas/ek_ra6m2/ek_ra6m2.dts new file mode 100644 index 00000000000..78407352e72 --- /dev/null +++ b/boards/renesas/ek_ra6m2/ek_ra6m2.dts @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +#include "ek_ra6m2-pinctrl.dtsi" + +/ { + model = "Renesas EK-RA6M2"; + compatible = "renesas,ra6m2", "renesas,ra"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart7; + zephyr,shell-uart = &uart7; + }; + + leds { + compatible = "gpio-leds"; + led1: led1 { + gpios = <&ioport1 6 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + }; + + aliases { + led0 = &led1; + }; +}; + +&sci7 { + pinctrl-0 = <&sci7_default>; + pinctrl-names = "default"; + status = "okay"; + uart7: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&ioport1 { + status = "okay"; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&pll { + source = ; + div = ; + mul = <20 0>; + status = "okay"; +}; diff --git a/boards/renesas/ek_ra6m2/ek_ra6m2.yaml b/boards/renesas/ek_ra6m2/ek_ra6m2.yaml new file mode 100644 index 00000000000..3f3c049c5e5 --- /dev/null +++ b/boards/renesas/ek_ra6m2/ek_ra6m2.yaml @@ -0,0 +1,11 @@ +identifier: ek_ra6m2 +name: Renesas EK-RA6M2 +type: mcu +arch: arm +ram: 384 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio diff --git a/boards/renesas/ek_ra6m2/ek_ra6m2_defconfig b/boards/renesas/ek_ra6m2/ek_ra6m2_defconfig new file mode 100644 index 00000000000..00adc77146e --- /dev/null +++ b/boards/renesas/ek_ra6m2/ek_ra6m2_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000 + +# Enable GPIO +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_CLOCK_CONTROL=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y diff --git a/boards/renesas/ek_ra6m3/Kconfig.ek_ra6m3 b/boards/renesas/ek_ra6m3/Kconfig.ek_ra6m3 new file mode 100644 index 00000000000..eb3f5510d45 --- /dev/null +++ b/boards/renesas/ek_ra6m3/Kconfig.ek_ra6m3 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EK_RA6M3 + select SOC_R7FA6M3AH3CFC diff --git a/boards/renesas/ek_ra6m3/board.cmake b/boards/renesas/ek_ra6m3/board.cmake new file mode 100644 index 00000000000..a395cf75494 --- /dev/null +++ b/boards/renesas/ek_ra6m3/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R7FA6M3AH") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/ek_ra6m3/board.yml b/boards/renesas/ek_ra6m3/board.yml new file mode 100644 index 00000000000..2bf115b0a18 --- /dev/null +++ b/boards/renesas/ek_ra6m3/board.yml @@ -0,0 +1,5 @@ +board: + name: ek_ra6m3 + vendor: renesas + socs: + - name: r7fa6m3ah3cfc diff --git a/boards/renesas/ek_ra6m3/doc/ek-ra6m3-board.webp b/boards/renesas/ek_ra6m3/doc/ek-ra6m3-board.webp new file mode 100644 index 00000000000..9aa1acf04da Binary files /dev/null and b/boards/renesas/ek_ra6m3/doc/ek-ra6m3-board.webp differ diff --git a/boards/renesas/ek_ra6m3/doc/index.rst b/boards/renesas/ek_ra6m3/doc/index.rst new file mode 100644 index 00000000000..bb468d9d1f5 --- /dev/null +++ b/boards/renesas/ek_ra6m3/doc/index.rst @@ -0,0 +1,163 @@ +.. _ek_ra6m3: + +RA6M3 Evaluation Kit +#################### + +Overview +******** + +The Renesas RA6M3 group uses the high-performance Arm® Cortex®-M4 core and +offers a TFT controller with 2D accelerator and JPEG decoder. The RA6M3 is +suitable for IoT applications requiring TFT, Ethernet, security, large +embedded RAM, and USB High Speed (HS). + +The key features of the EK-RA6M3 board are categorized in three groups as follow: + +**MCU Native Pin Access** + +- 120MHz Arm Cortex-M4 based RA6M3 MCU in 176 pins, LQFP package +- Native pin access through 4 x 40-pin male headers +- MCU and USB current measurement points for precision current consumption measurement +- Multiple clock sources - RA6M3 MCU oscillator and sub-clock oscillator crystals, + providing precision 24.000 MHz and 32,768 Hz reference clock. + Additional low precision clocks are avaialbe internal to the RA6M3 MCU + +**System Control and Ecosystem Access** + +- USB Full Speed Host and Device (micro AB connector) +- Four 5V input sources + + - USB (Debug, Full Speed, High Speed) + - External power supply (using surface mount clamp test points and power input vias) + +- Three Debug modes + + - Debug on-board (SWD) + - Debug in (ETM, SWD and JTAG) + - Debug out (SWD) + +- User LEDs and buttons + + - Three User LEDs (red, blue, green) + - Power LED (white) indicating availability of regulated power + - Debug LED (yellow) indicating the debug connection + - Two User buttons + - One Reset button + +- Four most popular ecosystems expansions + + - Two Seeed Grove system (I2C) connectors + - Two Digilent Pmod (SPI and UART) connectors + - Arduino (Uno R3) connector + - MikroElektronika mikroBUS connector + +- MCU boot configuration jumper + +**Special Feature Access** + +- Ethernet (RJ45 RMII interface) +- USB High Speed Host and Device (micro-AB connector) +- 32 Mb (256 Mb) External Quad-SPI Flash + +.. figure:: ek-ra6m3-board.webp + :align: center + :alt: RA6M3 Evaluation Kit + + EK-RA6M3 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) + +Hardware +******** +Detailed hardware feature for the RA6M3 MCU group can be found at `RA6M3 Group User's Manual Hardware`_ + +.. figure:: ra6m3-block-diagram.webp + :width: 442px + :align: center + :alt: RA6M3 MCU group feature + + RA6M3 Block diagram (Credit: Renesas Electronics Corporation) + +Detail hardware feature for the EK-RA6M3 MCU can be found at `EK-RA6M3 - User's Manual`_ + +Supported Features +================== + +The below features are currently supported on Zephyr OS for EK-RA6M3 board: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock control | ++-----------+------------+----------------------+ + +Other hardware features are currently not supported by the port. + +Programming and Debugging +************************* + +Applications for the ``ek_ra6m3`` board target configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +Program can be flashed to EK-RA6M3 via the on-board SEGGER J-Link debugger. +SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ + +To flash the program to board + + 1. Connect to J-Link OB via USB port to host PC + + 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M3 - User's Manual`_ + + 3. Execute west command + + .. code-block:: console + + west flash -r jlink + +Debugging +========= + +You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface + +Once downloaded and installed, open Segger Ozone and configure the debug project +like so: + +* Target Device: R7FA6M3AH +* Target Interface: SWD +* Target Interface Speed: 4 MHz +* Host Interface: USB +* Program File: + +**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later +version of Segger Ozone + +References +********** +- `EK-RA6M3 Website`_ +- `RA6M3 MCU group Website`_ + +.. _EK-RA6M3 Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6m3-evaluation-kit-ra6m3-mcu-group + +.. _RA6M3 MCU group Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra6m3-32-bit-microcontrollers-120mhz-usb-high-speed-ethernet-and-tft-controller + +.. _EK-RA6M3 - User's Manual: + https://www.renesas.com/us/en/document/mat/ek-ra6m3-v1-users-manual + +.. _RA6M3 Group User's Manual Hardware: + https://www.renesas.com/us/en/document/mah/ra6m3-group-users-manual-hardware + +.. _Segger Ozone Download: + https://www.segger.com/downloads/jlink#Ozone diff --git a/boards/renesas/ek_ra6m3/doc/ra6m3-block-diagram.webp b/boards/renesas/ek_ra6m3/doc/ra6m3-block-diagram.webp new file mode 100644 index 00000000000..e95bf93ee05 Binary files /dev/null and b/boards/renesas/ek_ra6m3/doc/ra6m3-block-diagram.webp differ diff --git a/boards/renesas/ek_ra6m3/ek_ra6m3-pinctrl.dtsi b/boards/renesas/ek_ra6m3/ek_ra6m3-pinctrl.dtsi new file mode 100644 index 00000000000..56fa3e26b6a --- /dev/null +++ b/boards/renesas/ek_ra6m3/ek_ra6m3-pinctrl.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci8_default: sci8_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; diff --git a/boards/renesas/ek_ra6m3/ek_ra6m3.dts b/boards/renesas/ek_ra6m3/ek_ra6m3.dts new file mode 100644 index 00000000000..0cd4de22aa1 --- /dev/null +++ b/boards/renesas/ek_ra6m3/ek_ra6m3.dts @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +#include "ek_ra6m3-pinctrl.dtsi" + +/ { + model = "Renesas EK-RA6M3"; + compatible = "renesas,ra6m3", "renesas,ra"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart8; + zephyr,shell-uart = &uart8; + zephyr,flash = &flash0; + }; + + leds { + compatible = "gpio-leds"; + led1: led1 { + gpios = <&ioport4 3 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + led2: led2 { + gpios = <&ioport4 0 GPIO_ACTIVE_HIGH>; + label = "LED2"; + }; + led3: led3 { + gpios = <&ioport1 0 GPIO_ACTIVE_HIGH>; + label = "LED3"; + }; + }; + + aliases { + led0 = &led1; + }; +}; + +&ioport1 { + status = "okay"; +}; + +&ioport4 { + status = "okay"; +}; + +&sci8 { + pinctrl-0 = <&sci8_default>; + pinctrl-names = "default"; + status = "okay"; + uart8: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&pll { + source = ; + div = ; + mul = <20 0>; + status = "okay"; +}; diff --git a/boards/renesas/ek_ra6m3/ek_ra6m3.yaml b/boards/renesas/ek_ra6m3/ek_ra6m3.yaml new file mode 100644 index 00000000000..50cc8737e92 --- /dev/null +++ b/boards/renesas/ek_ra6m3/ek_ra6m3.yaml @@ -0,0 +1,11 @@ +identifier: ek_ra6m3 +name: Renesas EK-RA6M3 +type: mcu +arch: arm +ram: 640 +flash: 2048 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio diff --git a/boards/renesas/ek_ra6m3/ek_ra6m3_defconfig b/boards/renesas/ek_ra6m3/ek_ra6m3_defconfig new file mode 100644 index 00000000000..31c2fa759e4 --- /dev/null +++ b/boards/renesas/ek_ra6m3/ek_ra6m3_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000 + +# Enable GPIO +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/ek_ra6m4/Kconfig.ek_ra6m4 b/boards/renesas/ek_ra6m4/Kconfig.ek_ra6m4 new file mode 100644 index 00000000000..28ed45ff14b --- /dev/null +++ b/boards/renesas/ek_ra6m4/Kconfig.ek_ra6m4 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EK_RA6M4 + select SOC_R7FA6M4AF3CFB diff --git a/boards/renesas/ek_ra6m4/board.cmake b/boards/renesas/ek_ra6m4/board.cmake new file mode 100644 index 00000000000..66f79828a34 --- /dev/null +++ b/boards/renesas/ek_ra6m4/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R7FA6M4AF") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/ek_ra6m4/board.yml b/boards/renesas/ek_ra6m4/board.yml new file mode 100644 index 00000000000..5c7e34ff180 --- /dev/null +++ b/boards/renesas/ek_ra6m4/board.yml @@ -0,0 +1,5 @@ +board: + name: ek_ra6m4 + vendor: renesas + socs: + - name: r7fa6m4af3cfb diff --git a/boards/renesas/ek_ra6m4/doc/ek-ra6m4-board.webp b/boards/renesas/ek_ra6m4/doc/ek-ra6m4-board.webp new file mode 100644 index 00000000000..b146b233ba7 Binary files /dev/null and b/boards/renesas/ek_ra6m4/doc/ek-ra6m4-board.webp differ diff --git a/boards/renesas/ek_ra6m4/doc/index.rst b/boards/renesas/ek_ra6m4/doc/index.rst new file mode 100644 index 00000000000..82549000d63 --- /dev/null +++ b/boards/renesas/ek_ra6m4/doc/index.rst @@ -0,0 +1,168 @@ +.. _ek_ra6m4: + +RA6M4 Evaluation Kit +#################### + +Overview +******** + +The Renesas RA6M4 group uses the high-performance Arm® Cortex®-M33 +core with TrustZone®. Secure element functionality providing better +performance, unlimited secure key storage, key management, and lower +BOM cost, as well as the integrated Ethernet MAC with individual DMA +ensures high data throughput. The RA6M4 is suitable for IoT applications +requiring Ethernet, future proof security, large embedded RAM, and low +active power consumption down to 99uA/MHz running the CoreMark® +algorithm from Flash. + +The key features of the EK-RA6M4 board are categorized in three groups as follow: + +**MCU Native Pin Access** + +- 200MHz Arm Cortex-M33 based RA6M4 MCU in 144 pins, LQFP package +- Native pin access through 4 x 40-pin male headers +- MCU current measurement points for precision current consumption measurement +- Multiple clock sources - RA6M4 MCU oscillator and sub-clock oscillator crystals, + providing precision 24.000 MHz and 32,768 Hz reference clock. + Additional low precision clocks are avaialbe internal to the RA6M4 MCU + +**System Control and Ecosystem Access** + +- USB Full Speed Host and Device (micro-AB connector) +- Three 5 V input sources + + - USB (Debug, Full Speed) + - External power supply (using surface mount clamp test points and power input vias) + +- Three Debug modes + + - Debug on-board (SWD) + - Debug in (ETM, SWD and JTAG) + - Debug out (SWD) + +- User LEDs and buttons + + - Three User LEDs (red, blue, green) + - Power LED (white) indicating availability of regulated power + - Debug LED (yellow) indicating the debug connection + - Two User buttons + - One Reset button + +- Five most popular ecosystems expansions + + - Two Seeed Grove system (I2C/Analog) connectors + - One SparkFun Qwiic connector + - Two Digilent Pmod (SPI and UART) connectors + - Arduino (Uno R3) connector + - MikroElektronika mikroBUS connector + +- MCU boot configuration jumper + +**Special Feature Access** + +- Ethernet (RJ45 RMII interface) +- 32 Mb (256 Mb) External Quad-SPI Flash +- 64 Mb (512 Mb) External Octo-SPI Flash + +.. figure:: ek-ra6m4-board.webp + :align: center + :alt: RA6M4 Evaluation Kit + + EK-RA6M4 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) + +Hardware +******** +Detailed hardware feature for the RA6M4 MCU group can be found at `RA6M4 Group User's Manual Hardware`_ + +.. figure:: ra6m4-block-diagram.webp + :width: 442px + :align: center + :alt: RA6M4 MCU group feature + + RA6M4 Block diagram (Credit: Renesas Electronics Corporation) + +Detailed hardware feature for the EK-RA6M4 MCU can be found at `EK-RA6M4 - User's Manual`_ + +Supported Features +================== + +The below features are currently supported on Zephyr OS for EK-RA6M4 board: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock control | ++-----------+------------+----------------------+ + +Other hardware features are currently not supported by the port. + +Programming and Debugging +************************* + +Applications for the ``ek_ra6m4`` board target configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +Program can be flashed to EK-RA6M4 via the on-board SEGGER J-Link debugger. +SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ + +To flash the program to board + + 1. Connect to J-Link OB via USB port to host PC + + 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M4 - User's Manual`_ + + 3. Execute west command + + .. code-block:: console + + west flash -r jlink + +Debugging +========= + +You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface + +Once downloaded and installed, open Segger Ozone and configure the debug project +like so: + +* Target Device: R7FA6M4AF +* Target Interface: SWD +* Target Interface Speed: 4 MHz +* Host Interface: USB +* Program File: + +**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later +version of Segger Ozone + +References +********** +- `EK-RA6M4 Website`_ +- `RA6M4 MCU group Website`_ + +.. _EK-RA6M4 Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6m4-evaluation-kit-ra6m4-mcu-group + +.. _RA6M4 MCU group Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra6m4-200mhz-arm-cortex-m33-trustzone-high-integration-ethernet-and-octaspi + +.. _EK-RA6M4 - User's Manual: + https://www.renesas.com/us/en/document/man/ek-ra6m4-v1-users-manual + +.. _RA6M4 Group User's Manual Hardware: + https://www.renesas.com/us/en/document/man/ra6m4-group-user-s-manual-hardware?r=1333976 + +.. _Segger Ozone Download: + https://www.segger.com/downloads/jlink#Ozone diff --git a/boards/renesas/ek_ra6m4/doc/ra6m4-block-diagram.webp b/boards/renesas/ek_ra6m4/doc/ra6m4-block-diagram.webp new file mode 100644 index 00000000000..3bf83cf0a59 Binary files /dev/null and b/boards/renesas/ek_ra6m4/doc/ra6m4-block-diagram.webp differ diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4-pinctrl.dtsi b/boards/renesas/ek_ra6m4/ek_ra6m4-pinctrl.dtsi new file mode 100644 index 00000000000..851d8543bee --- /dev/null +++ b/boards/renesas/ek_ra6m4/ek_ra6m4-pinctrl.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci0_default: sci0_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4.dts b/boards/renesas/ek_ra6m4/ek_ra6m4.dts new file mode 100644 index 00000000000..f0f447eede7 --- /dev/null +++ b/boards/renesas/ek_ra6m4/ek_ra6m4.dts @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +#include "ek_ra6m4-pinctrl.dtsi" + +/ { + model = "Renesas EK-RA6M4"; + compatible = "renesas,ra6m4", "renesas,ra"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + leds { + compatible = "gpio-leds"; + led1: led1 { + gpios = <&ioport4 15 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + led2: led2 { + gpios = <&ioport4 4 GPIO_ACTIVE_HIGH>; + label = "LED2"; + }; + led3: led3 { + gpios = <&ioport4 0 GPIO_ACTIVE_HIGH>; + label = "LED3"; + }; + }; + + aliases { + led0 = &led1; + }; +}; + +&sci0 { + pinctrl-0 = <&sci0_default>; + pinctrl-names = "default"; + status = "okay"; + uart0: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&ioport4 { + status = "okay"; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&pll { + source = ; + div = ; + mul = <25 0>; + status = "okay"; +}; + +&pclka { + clk-src = ; + clk-div = ; + status = "okay"; +}; diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4.yaml b/boards/renesas/ek_ra6m4/ek_ra6m4.yaml new file mode 100644 index 00000000000..d9488b99e81 --- /dev/null +++ b/boards/renesas/ek_ra6m4/ek_ra6m4.yaml @@ -0,0 +1,11 @@ +identifier: ek_ra6m4 +name: Renesas EK-RA6M4 +type: mcu +arch: arm +ram: 256 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4_defconfig b/boards/renesas/ek_ra6m4/ek_ra6m4_defconfig new file mode 100644 index 00000000000..45a5a73366a --- /dev/null +++ b/boards/renesas/ek_ra6m4/ek_ra6m4_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000 + +# Enable GPIO +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/ek_ra6m5/Kconfig.ek_ra6m5 b/boards/renesas/ek_ra6m5/Kconfig.ek_ra6m5 new file mode 100644 index 00000000000..fccd13875b9 --- /dev/null +++ b/boards/renesas/ek_ra6m5/Kconfig.ek_ra6m5 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EK_RA6M5 + select SOC_R7FA6M5BH3CFC diff --git a/boards/renesas/ek_ra6m5/board.cmake b/boards/renesas/ek_ra6m5/board.cmake new file mode 100644 index 00000000000..5aabef8bb75 --- /dev/null +++ b/boards/renesas/ek_ra6m5/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R7FA6M5BH") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/ek_ra6m5/board.yml b/boards/renesas/ek_ra6m5/board.yml new file mode 100644 index 00000000000..826e64f943e --- /dev/null +++ b/boards/renesas/ek_ra6m5/board.yml @@ -0,0 +1,5 @@ +board: + name: ek_ra6m5 + vendor: renesas + socs: + - name: r7fa6m5bh3cfc diff --git a/boards/renesas/ek_ra6m5/doc/ek-ra6m5-board.webp b/boards/renesas/ek_ra6m5/doc/ek-ra6m5-board.webp new file mode 100644 index 00000000000..073a0493daa Binary files /dev/null and b/boards/renesas/ek_ra6m5/doc/ek-ra6m5-board.webp differ diff --git a/boards/renesas/ek_ra6m5/doc/index.rst b/boards/renesas/ek_ra6m5/doc/index.rst new file mode 100644 index 00000000000..bc94a155e11 --- /dev/null +++ b/boards/renesas/ek_ra6m5/doc/index.rst @@ -0,0 +1,166 @@ +.. _ek_ra6m5: + +RA6M5 Evaluation Kit +#################### + +Overview +******** + +The Renesas RA6M5 group uses the high-performance Arm® Cortex®-M33 core with +TrustZone®. The RA6M5 is suitable for IoT applications requiring Ethernet, future +proof security, large embedded RAM, and low active power consumption down +to 107uA/MHz running the CoreMark® algorithm from Flash. + +The key features of the EK-RA6M5 board are categorized in three groups as follow: + +**MCU Native Pin Access** + +- 200MHz Arm Cortex-M33 based RA6M5 MCU in 176 pins, LQFP package +- Native pin access through 4 x 40-pin male headers +- MCU current measurement points for precision current consumption measurement +- Multiple clock sources - RA6M5 MCU oscillator and sub-clock oscillator crystals, + providing precision 24.000 MHz and 32,768 Hz reference clock. + Additional low precision clocks are avaialbe internal to the RA6M5 MCU + +**System Control and Ecosystem Access** + +- USB Full Speed Host and Device (micro-AB connector) +- Four 5V input sources + + - USB (Debug, Full Speed, High Speed) + - External power supply (using surface mount clamp test points and power input vias) + +- Three Debug modes + + - Debug on-board (SWD) + - Debug in (ETM, SWD and JTAG) + - Debug out (SWD) + +- User LEDs and buttons + + - Three User LEDs (red, blue, green) + - Power LED (white) indicating availability of regulated power + - Debug LED (yellow) indicating the debug connection + - Two User buttons + - One Reset button + +- Five most popular ecosystems expansions + + - Two Seeed Grove system (I2C/Analog) connectors + - One SparkFun Qwiic connector + - Two Digilent Pmod (SPI and UART) connectors + - Arduino (Uno R3) connector + - MikroElektronika mikroBUS connector + +- MCU boot configuration jumper + +**Special Feature Access** + +- Ethernet (RJ45 RMII interface) +- USB High Speed Host and Device (micro-AB connector) +- 32 Mb (256 Mb) External Quad-SPI Flash +- 64 Mb (512 Mb) External Octo-SPI Flash +- CAN (3-pin header) + +.. figure:: ek-ra6m5-board.webp + :align: center + :alt: RA6M5 Evaluation Kit + + EK-RA6M5 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) + +Hardware +******** +Detailed hardware feature for the RA6M5 MCU group can be found at `RA6M5 Group User's Manual Hardware`_ + +.. figure:: ra6m5-block-diagram.webp + :width: 442px + :align: center + :alt: RA6M5 MCU group feature + + RA6M5 Block diagram (Credit: Renesas Electronics Corporation) + +Detailed hardware feature for the EK-RA6M5 MCU can be found at `EK-RA6M5 - User's Manual`_ + +Supported Features +================== + +The below features are currently supported on Zephyr OS for EK-RA6M5 board: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock control | ++-----------+------------+----------------------+ + +Other hardware features are currently not supported by the port. + +Programming and Debugging +************************* + +Applications for the ``ek_ra6m5`` board target configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +Program can be flashed to EK-RA6M5 via the on-board SEGGER J-Link debugger. +SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ + +To flash the program to board + + 1. Connect to J-Link OB via USB port to host PC + + 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M5 - User's Manual`_ + + 3. Execute west command + + .. code-block:: console + + west flash -r jlink + +Debugging +========= + +You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface + +Once downloaded and installed, open Segger Ozone and configure the debug project +like so: + +* Target Device: R7FA6M5BH +* Target Interface: SWD +* Target Interface Speed: 4 MHz +* Host Interface: USB +* Program File: + +**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later +version of Segger Ozone + +References +********** +- `EK-RA6M5 Website`_ +- `RA6M5 MCU group Website`_ + +.. _EK-RA6M5 Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6m5-evaluation-kit-ra6m5-mcu-group + +.. _RA6M5 MCU group Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra6m5-200mhz-arm-cortex-m33-trustzone-highest-integration-ethernet-and-can-fd + +.. _EK-RA6M5 - User's Manual: + https://www.renesas.com/us/en/document/man/ek-ra6m5-v1-users-manual + +.. _RA6M5 Group User's Manual Hardware: + https://www.renesas.com/us/en/document/man/ra6m5-group-users-manual-hardware + +.. _Segger Ozone Download: + https://www.segger.com/downloads/jlink#Ozone diff --git a/boards/renesas/ek_ra6m5/doc/ra6m5-block-diagram.webp b/boards/renesas/ek_ra6m5/doc/ra6m5-block-diagram.webp new file mode 100644 index 00000000000..456726a8446 Binary files /dev/null and b/boards/renesas/ek_ra6m5/doc/ra6m5-block-diagram.webp differ diff --git a/boards/renesas/ek_ra6m5/ek_ra6m5-pinctrl.dtsi b/boards/renesas/ek_ra6m5/ek_ra6m5-pinctrl.dtsi new file mode 100644 index 00000000000..851d8543bee --- /dev/null +++ b/boards/renesas/ek_ra6m5/ek_ra6m5-pinctrl.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci0_default: sci0_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; diff --git a/boards/renesas/ek_ra6m5/ek_ra6m5.dts b/boards/renesas/ek_ra6m5/ek_ra6m5.dts new file mode 100644 index 00000000000..ad84e26a167 --- /dev/null +++ b/boards/renesas/ek_ra6m5/ek_ra6m5.dts @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +#include "ek_ra6m5-pinctrl.dtsi" + +/ { + model = "Renesas EK-RA6M5"; + compatible = "renesas,ra6m5", "renesas,ra"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + leds { + compatible = "gpio-leds"; + led1: led1 { + gpios = <&ioport0 6 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + led2: led2 { + gpios = <&ioport0 7 GPIO_ACTIVE_HIGH>; + label = "LED2"; + }; + led3: led3 { + gpios = <&ioport0 8 GPIO_ACTIVE_HIGH>; + label = "LED3"; + }; + }; + + aliases { + led0 = &led1; + }; +}; + +&sci0 { + pinctrl-0 = <&sci0_default>; + pinctrl-names = "default"; + status = "okay"; + uart0: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&ioport0 { + status = "okay"; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&pll { + source = ; + div = ; + mul = <25 0>; + status = "okay"; +}; diff --git a/boards/renesas/ek_ra6m5/ek_ra6m5.yaml b/boards/renesas/ek_ra6m5/ek_ra6m5.yaml new file mode 100644 index 00000000000..2f65bfb229d --- /dev/null +++ b/boards/renesas/ek_ra6m5/ek_ra6m5.yaml @@ -0,0 +1,11 @@ +identifier: ek_ra6m5 +name: Renesas EK-RA6M5 +type: mcu +arch: arm +ram: 512 +flash: 2048 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio diff --git a/boards/renesas/ek_ra6m5/ek_ra6m5_defconfig b/boards/renesas/ek_ra6m5/ek_ra6m5_defconfig new file mode 100644 index 00000000000..4b5534eb1ff --- /dev/null +++ b/boards/renesas/ek_ra6m5/ek_ra6m5_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000 + +# Enable GPIO +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_CLOCK_CONTROL=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y diff --git a/boards/renesas/ek_ra8d1/Kconfig.ek_ra8d1 b/boards/renesas/ek_ra8d1/Kconfig.ek_ra8d1 new file mode 100644 index 00000000000..fa18d111ee9 --- /dev/null +++ b/boards/renesas/ek_ra8d1/Kconfig.ek_ra8d1 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EK_RA8D1 + select SOC_R7FA8D1BHECBD diff --git a/boards/renesas/ek_ra8d1/board.cmake b/boards/renesas/ek_ra8d1/board.cmake new file mode 100644 index 00000000000..ee93597a92c --- /dev/null +++ b/boards/renesas/ek_ra8d1/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R7FA8D1BH") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/ek_ra8d1/board.yml b/boards/renesas/ek_ra8d1/board.yml new file mode 100644 index 00000000000..9b48ea9b942 --- /dev/null +++ b/boards/renesas/ek_ra8d1/board.yml @@ -0,0 +1,5 @@ +board: + name: ek_ra8d1 + vendor: renesas + socs: + - name: r7fa8d1bhecbd diff --git a/boards/renesas/ek_ra8d1/doc/ek-ra8d1-board.jpg b/boards/renesas/ek_ra8d1/doc/ek-ra8d1-board.jpg new file mode 100644 index 00000000000..a97d241a4fb Binary files /dev/null and b/boards/renesas/ek_ra8d1/doc/ek-ra8d1-board.jpg differ diff --git a/boards/renesas/ek_ra8d1/doc/index.rst b/boards/renesas/ek_ra8d1/doc/index.rst new file mode 100644 index 00000000000..79a5dde2d90 --- /dev/null +++ b/boards/renesas/ek_ra8d1/doc/index.rst @@ -0,0 +1,174 @@ +.. _ek_ra8d1: + +RA8D1 Evaluation Kit +#################### + +Overview +******** + +The EK-RA8D1 is an Evaluation Kit for Renesas RA8D1 MCU Group which are the industry’s first 32-bit +graphics-enabled MCUs based on the Arm Cortex-M85 (CM85) core, delivering breakthrough performance +of over 3000 Coremark points at 480 MHz and superior graphics capabilities that enable high-resolution +displays and Vision AI applications. + +The key features of the EK-RA8D1 board are categorized in three groups as follow: + +**MCU Native Pin Access** + +- 480MHz Arm Cortex-M85 based RA8D1 MCU in 224 pins, BGA package +- Native pin acces througgh 2 x 50-pin, and 2 x 40-pin male headers +- MCU current measurement points for precision current consumption measurement +- Multiple clock sources - RA8D1 MCU oscillator and sub-clock oscillator crystals, + providing precision 20.000MHz and 32,768 Hz refeence clocks. + Additional low precision clocks are avaialbe internal to the RA8D1 MCU + +**System Control and Ecosystem Access** + +- USB Full Speed Host and Device (micro-AB connector) +- Four 5V input sources + + - USB (Debug, Full Speed, High Speed) + - External power supply (using surface mount clamp test points and power input vias) + +- Three Debug modes + + - Debug on-board (SWD) + - Debug in (ETM, SWD and JTAG) + - Debug out (SWD) + +- User LEDs and buttons + + - Three User LEDs (red, blue, green) + - Power LED (white) indicating availability of regulated power + - Debug LED (yellow) indicating the debug connection + - Two User buttons + - One Reset button + +- Five most popular ecosystems expansions + + - Two Seeed Grove system (I2C/I3C) connectors + - One SparkFun Qwiic connector + - Two Digilent Pmod (SPI, UART and I2C/I3C) connectors + - Arduino (Uno R3) connector + - MikroElektronika mikroBUS connector + +- MCU boot configuration jumper + +**Special Feature Access** + +- Ethernet (RJ45 RMII interface) +- USB High Speed Host and Device (micro-AB connector) +- 512 Mb (64 MB) External Octo-SPI Flash (present in the MCU Native Pin Access area of the EK-RA8D1 board) +- CAN FD (3-pin header) + +.. figure:: ek-ra8d1-board.jpg + :align: center + :alt: RA8D1 Evaluation Kit + + EK-RA8D1 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) + +Hardware +******** +Detail Hardware feature for the RA8D1 MCU group can be found at `RA8D1 Group User's Manual Hardware`_ + +.. figure:: ra8d1-block-diagram.png + :width: 442px + :align: center + :alt: RA8D1 MCU group feature + + RA8D1 Block diagram (Credit: Renesas Electronics Corporation) + +Detail Hardware feature for the EK-RA8D1 MCU can be found at `EK-RA8D1 - User's Manual`_ + +Supported Features +================== + +The below features are currently supported on Zephyr OS for EK-RA8D1 board: + ++--------------+------------+------------------+ +| Interface | Controller | Driver/Component | ++==============+============+==================+ +| GPIO | on-chip | gpio | ++--------------+------------+------------------+ +| MPU | on-chip | arch/arm | ++--------------+------------+------------------+ +| NVIC | on-chip | arch/arm | ++--------------+------------+------------------+ +| UART | on-chip | serial | ++--------------+------------+------------------+ +| CLOCK | on-chip | clock control | ++--------------+------------+------------------+ +| ENTROPY | on-chip | entropy | ++--------------+------------+------------------+ +| SPI | on-chip | spi | ++--------------+------------+------------------+ +| FLASH | on-chip | flash | ++--------------+------------+------------------+ + +Other hardware features are currently not supported by the port. + +Programming and Debugging +************************* + +Applications for the ``ek_ra8d1`` board configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +**Note:** Only support from SDK v0.16.6 in which GCC for Cortex Arm-M85 was available. +To build for EK-RA8M1 user need to get and install GNU Arm Embedded toolchain from https://github.com/zephyrproject-rtos/sdk-ng/releases/tag/v0.16.6 + +Flashing +======== + +Program can be flashed to EK-RA8D1 via the on-board SEGGER J-Link debugger. +SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ + +To flash the program to board + + 1. Connect to J-Link OB via USB port to host PC + + 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA8D1 - User's Manual`_ + + 3. Execute west command + + .. code-block:: console + + west flash -r jlink + +Debugging +========= + +You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface + +Once downloaded and installed, open Segger Ozone and configure the debug project +like so: + +* Target Device: R7FA8D1BH +* Target Interface: SWD +* Target Interface Speed: 4 MHz +* Host Interface: USB +* Program File: + +**Note:** It's verified that debug is OK on Segger Ozone v3.30d so please use this or later +version of Segger Ozone + +References +********** +- `EK-RA8D1 Website`_ +- `RA8D1 MCU group Website`_ + +.. _EK-RA8D1 Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra8d1-evaluation-kit-ra8d1-mcu-group + +.. _RA8D1 MCU group Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra8d1-480-mhz-arm-cortex-m85-based-graphics-microcontroller-helium-and-trustzone + +.. _EK-RA8D1 - User's Manual: + https://www.renesas.com/us/en/document/mat/ek-ra8d1-v1-user-manual + +.. _RA8D1 Group User's Manual Hardware: + https://www.renesas.com/us/en/document/mah/ra8d1-group-users-manual-hardware + +.. _Segger Ozone Download: + https://www.segger.com/downloads/jlink#Ozone diff --git a/boards/renesas/ek_ra8d1/doc/ra8d1-block-diagram.png b/boards/renesas/ek_ra8d1/doc/ra8d1-block-diagram.png new file mode 100644 index 00000000000..c4739871fcb Binary files /dev/null and b/boards/renesas/ek_ra8d1/doc/ra8d1-block-diagram.png differ diff --git a/boards/renesas/ek_ra8d1/ek_ra8d1-pinctrl.dtsi b/boards/renesas/ek_ra8d1/ek_ra8d1-pinctrl.dtsi new file mode 100644 index 00000000000..57a0e064fba --- /dev/null +++ b/boards/renesas/ek_ra8d1/ek_ra8d1-pinctrl.dtsi @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci9_default: sci9_default { + group1 { + /* tx */ + psels = ; + drive-strength = "medium"; + }; + group2 { + /* rx */ + psels = ; + }; + }; + + spi0_default: spi0_default { + group1 { + /* MISO MOSI RSPCK SSL */ + psels = , + , + , + ; + }; + }; +}; diff --git a/boards/renesas/ek_ra8d1/ek_ra8d1.dts b/boards/renesas/ek_ra8d1/ek_ra8d1.dts new file mode 100644 index 00000000000..698e90e631c --- /dev/null +++ b/boards/renesas/ek_ra8d1/ek_ra8d1.dts @@ -0,0 +1,126 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +#include "ek_ra8d1-pinctrl.dtsi" + +/ { + model = "Renesas EK-RA8D1"; + compatible = "renesas,ra8d1", "renesas,ra8"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart9; + zephyr,shell-uart = &uart9; + zephyr,entropy = &trng; + zephyr,flash-controller = &flash1; + }; + + leds { + compatible = "gpio-leds"; + led1: led1 { + gpios = <&ioport6 0 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + led2: led2 { + gpios = <&ioport4 14 GPIO_ACTIVE_HIGH>; + label = "LED2"; + }; + led3: led3 { + gpios = <&ioport1 7 GPIO_ACTIVE_HIGH>; + label = "LED3"; + }; + }; + + aliases { + led0 = &led1; + }; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&pll { + source = ; + div = ; + mul = <96 0>; + divp = ; + freqp = ; + divq = ; + freqq = ; + divr = ; + freqr = ; + status = "okay"; +}; + +&sciclk { + clk-src = ; + clk-div = ; + status = "okay"; +}; + +&ioport1 { + status = "okay"; +}; + +&ioport4 { + status = "okay"; +}; + +&ioport6 { + status = "okay"; +}; + +&sci0 { + /* sci0 and spi0 cannot be enabled together */ + pinctrl-0 = <&sci9_default>; + pinctrl-names = "default"; +}; + +&sci9 { + pinctrl-0 = <&sci9_default>; + pinctrl-names = "default"; + status = "okay"; + uart9: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&trng { + status = "okay"; +}; + +&spi0 { + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&flash1 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@0 { + label = "storage"; + reg = <0X0 DT_SIZE_K(12)>; + }; + }; +}; diff --git a/boards/renesas/ek_ra8d1/ek_ra8d1.yaml b/boards/renesas/ek_ra8d1/ek_ra8d1.yaml new file mode 100644 index 00000000000..2432f8ed657 --- /dev/null +++ b/boards/renesas/ek_ra8d1/ek_ra8d1.yaml @@ -0,0 +1,12 @@ +identifier: ek_ra8d1 +name: Renesas EK-RA8D1 +type: mcu +arch: arm +ram: 1024 +flash: 2048 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - uart diff --git a/boards/renesas/ek_ra8d1/ek_ra8d1_defconfig b/boards/renesas/ek_ra8d1/ek_ra8d1_defconfig new file mode 100644 index 00000000000..daa9e38c77b --- /dev/null +++ b/boards/renesas/ek_ra8d1/ek_ra8d1_defconfig @@ -0,0 +1,20 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=480000000 + +# Enable GPIO +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_CLOCK_CONTROL=y + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_NO_GAP_FILL=y + +CONFIG_FLASH=y diff --git a/boards/renesas/ek_ra8m1/Kconfig.ek_ra8m1 b/boards/renesas/ek_ra8m1/Kconfig.ek_ra8m1 new file mode 100644 index 00000000000..f47278e2877 --- /dev/null +++ b/boards/renesas/ek_ra8m1/Kconfig.ek_ra8m1 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EK_RA8M1 + select SOC_R7FA8M1AHECBD diff --git a/boards/renesas/ek_ra8m1/board.cmake b/boards/renesas/ek_ra8m1/board.cmake new file mode 100644 index 00000000000..839e642d478 --- /dev/null +++ b/boards/renesas/ek_ra8m1/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R7FA8M1AH") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/ek_ra8m1/board.yml b/boards/renesas/ek_ra8m1/board.yml new file mode 100644 index 00000000000..136846ecc81 --- /dev/null +++ b/boards/renesas/ek_ra8m1/board.yml @@ -0,0 +1,5 @@ +board: + name: ek_ra8m1 + vendor: renesas + socs: + - name: r7fa8m1ahecbd diff --git a/boards/renesas/ek_ra8m1/doc/ek-ra8m1-board.jpg b/boards/renesas/ek_ra8m1/doc/ek-ra8m1-board.jpg new file mode 100644 index 00000000000..92233d3bffd Binary files /dev/null and b/boards/renesas/ek_ra8m1/doc/ek-ra8m1-board.jpg differ diff --git a/boards/renesas/ek_ra8m1/doc/index.rst b/boards/renesas/ek_ra8m1/doc/index.rst new file mode 100644 index 00000000000..84b168eb23e --- /dev/null +++ b/boards/renesas/ek_ra8m1/doc/index.rst @@ -0,0 +1,179 @@ +.. _ek_ra8m1: + +RA8M1 Evaluation Kit +#################### + +Overview +******** + +The EK-RA8M1 is an Evaluation Kit for Renesas RA8M1 MCU Group which is the first +32-bits MCUs based on new Arm Cortex-M85. The kit offer multiple external interface +and peripherals set optimized on board allows user to seamlessly evaluate the features +of the RA8M1 MCU and develop embedded system application in various field. + +The key features of the EK-RA8M1 board are categorized in three groups as follow: + +**MCU Native Pin Access** + +- 480MHz Arm Cortex-M85 based RA8M1 MCU in 224 pins, BGA package +- Native pin acces througgh 2 x 50-pin, and 2 x 40-pin male headers +- MCU current measurement points for precision current consumption measurement +- Multiple clock sources - RA8M1 MCU oscillator and sub-clock oscillator crystals, + providing precision 20.000MHz and 32,768 Hz refeence clocks. + Additional low precision clocks are avaialbe internal to the RA8M1 MCU + +**System Control and Ecosystem Access** + +- USB Full Speed Host and Device (micro-AB connector) +- Four 5V input sources + + - USB (Debug, Full Speed, High Speed) + - External power supply (using surface mount clamp test points and power input vias) + +- Three Debug modes + + - Debug on-board (SWD) + - Debug in (ETM, SWD and JTAG) + - Debug out (SWD) + +- User LEDs and buttons + + - Three User LEDs (red, blue, green) + - Power LED (white) indicating availability of regulated power + - Debug LED (yellow) indicating the debug connection + - Two User buttons + - One Reset button + +- Five most popular ecosystems expansions + + - Two Seeed Grove system (I2C/I3C) connectors + - One SparkFun Qwiic connector + - Two Digilent Pmod (SPI, UART and I2C/I3C) connectors + - Arduino (Uno R3) connector + - MikroElektronika mikroBUS connector + +- MCU boot configuration jumper + +**Special Feature Access** + +- Ethernet (RJ45 RMII interface) +- USB High Speed Host and Device (micro-AB connector) +- 512 Mb (64 MB) External Octo-SPI Flash (present in the MCU Native Pin Access area of the EK-RA8M1 board) +- CAN FD (3-pin header) + +.. figure:: ek-ra8m1-board.jpg + :align: center + :alt: RA8M1 Evaluation Kit + + EK-RA8M1 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) + +Hardware +******** +Detail Hardware feature for the RA8M1 MCU group can be found at `RA8M1 Group User's Manual Hardware`_ + +.. figure:: ra8m1-block-diagram.jpg + :width: 442px + :align: center + :alt: RA8M1 MCU group feature + + RA8M1 Block diagram (Credit: Renesas Electronics Corporation) + +Detail Hardware feature for the EK-RA8M1 MCU can be found at `EK-RA8M1 - User's Manual`_ + +Supported Features +================== + +The below features are currently supported on Zephyr OS for EK-RA8M1 board: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock control | ++-----------+------------+----------------------+ +| I2C | on-chip | i2c | ++-----------+------------+----------------------+ +| ENTROPY | on-chip | entropy | ++-----------+------------+----------------------+ +| SPI | on-chip | spi | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ + +Other hardware features are currently not supported by the port. + +Programming and Debugging +************************* + +Applications for the ``ek_ra8m1`` board configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +**Note:** Only support from SDK v0.16.6 in which GCC for Cortex Arm-M85 was available. +To build for EK-RA8M1 user need to get and install GNU Arm Embedded toolchain from https://github.com/zephyrproject-rtos/sdk-ng/releases/tag/v0.16.6 + +Flashing +======== + +Program can be flashed to EK-RA8M1 via the on-board SEGGER J-Link debugger. +SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ + +To flash the program to board + + 1. Connect to J-Link OB via USB port to host PC + + 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA8M1 - User's Manual`_ + + 3. Execute west command + + .. code-block:: console + + west flash -r jlink + +Debugging +========= + +You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface + +Once downloaded and installed, open Segger Ozone and configure the debug project +like so: + +* Target Device: R7FA8M1AH +* Target Interface: SWD +* Target Interface Speed: 4 MHz +* Host Interface: USB +* Program File: + +**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later +version of Segger Ozone + +References +********** +- `EK-RA8M1 Website`_ +- `RA8M1 MCU group Website`_ + +.. _EK-RA8M1 Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra8m1-evaluation-kit-ra8m1-mcu-group + +.. _RA8M1 MCU group Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra8m1-480-mhz-arm-cortex-m85-based-microcontroller-helium-and-trustzone + +.. _EK-RA8M1 - User's Manual: + https://www.renesas.com/us/en/document/mat/ek-ra8m1-users-manual + +.. _RA8M1 Group User's Manual Hardware: + https://www.renesas.com/us/en/document/mah/ra8m1-group-users-manual-hardware + +.. _Segger Ozone Download: + https://www.segger.com/downloads/jlink#Ozone + +.. _zephyr-sdk-0.16.5-6-ge895c4e_linux-x86_64: + https://github.com/zephyrproject-rtos/sdk-ng/suites/22342313531/artifacts/1379111922 diff --git a/boards/renesas/ek_ra8m1/doc/ra8m1-block-diagram.jpg b/boards/renesas/ek_ra8m1/doc/ra8m1-block-diagram.jpg new file mode 100644 index 00000000000..81d4a0b7913 Binary files /dev/null and b/boards/renesas/ek_ra8m1/doc/ra8m1-block-diagram.jpg differ diff --git a/boards/renesas/ek_ra8m1/ek_ra8m1-pinctrl.dtsi b/boards/renesas/ek_ra8m1/ek_ra8m1-pinctrl.dtsi new file mode 100644 index 00000000000..b43c4be60ab --- /dev/null +++ b/boards/renesas/ek_ra8m1/ek_ra8m1-pinctrl.dtsi @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci3_default: sci3_default { + group1 { + /* tx */ + psels = ; + drive-strength = "medium"; + }; + group2 { + /* rx */ + psels = ; + }; + }; + + sci9_default: sci9_default { + group1 { + /* tx */ + psels = ; + drive-strength = "medium"; + }; + group2 { + /* rx */ + psels = ; + }; + }; + + iic1_default: iic1_default { + group1 { + /* SCL1 SDA1*/ + psels = ,; + drive-strength = "medium"; + }; + }; + + adc0_default: adc0_default { + group1 { + /* input */ + psels = ; + renesas,analog-enable; + }; + }; + + spi1_default: spi1_default { + group1 { + /* MISO MOSI RSPCK SSL*/ + psels = , + , + , + ; + }; + }; +}; diff --git a/boards/renesas/ek_ra8m1/ek_ra8m1.dts b/boards/renesas/ek_ra8m1/ek_ra8m1.dts new file mode 100644 index 00000000000..de64b9ecf25 --- /dev/null +++ b/boards/renesas/ek_ra8m1/ek_ra8m1.dts @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include "ek_ra8m1-pinctrl.dtsi" + +/ { + model = "Renesas EK-RA8M1"; + compatible = "renesas,ra8m1", "renesas,ra8"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash-controller = &flash1; + zephyr,flash = &flash0; + zephyr,console = &uart9; + zephyr,shell-uart = &uart9; + zephyr,entropy = &trng; + }; + + leds { + compatible = "gpio-leds"; + led1: led1 { + gpios = <&ioport6 0 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + led2: led2 { + gpios = <&ioport4 14 GPIO_ACTIVE_HIGH>; + label = "LED2"; + }; + led3: led3 { + gpios = <&ioport1 7 GPIO_ACTIVE_HIGH>; + label = "LED3"; + }; + }; + + mikrobus_header: mikrobus-connector { + compatible = "mikro-bus"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &ioport0 4 0>, /* AN */ + <1 0 &ioport5 2 0>, /* RST */ + <2 0 &ioport4 13 0>, /* CS */ + <3 0 &ioport4 12 0>, /* SCK */ + <4 0 &ioport4 10 0>, /* MISO */ + <5 0 &ioport4 11 0>, /* MOSI */ + /* +3.3V */ + /* GND */ + <6 0 &ioport9 7 0>, /* PWM */ + <7 0 &ioport0 10 0>, /* INT */ + <8 0 &ioport3 9 0>, /* RX */ + <9 0 &ioport3 10 0>, /* TX */ + <10 0 &ioport4 0 0>, /* SCL */ + <11 0 &ioport4 1 0>; /* SDA */ + /* +5V */ + /* GND */ + }; + + aliases { + led0 = &led1; + }; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&pll { + source = ; + div = ; + mul = <96 0>; + divp = ; + freqp = ; + divq = ; + freqq = ; + divr = ; + freqr = ; + status = "okay"; +}; + +&sciclk { + clk-src = ; + clk-div = ; + status = "okay"; +}; + +&ioport0 { + status = "okay"; +}; + +&ioport1 { + status = "okay"; +}; + +&ioport3 { + status = "okay"; +}; + +&ioport4 { + status = "okay"; +}; + +&ioport5 { + status = "okay"; +}; + +&ioport6 { + status = "okay"; +}; + +&ioport9 { + status = "okay"; +}; + +&sci3 { + pinctrl-0 = <&sci3_default>; + pinctrl-names = "default"; + status = "okay"; + uart3: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&sci9 { + pinctrl-0 = <&sci9_default>; + pinctrl-names = "default"; + status = "okay"; + uart9: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +mikrobus_serial: &uart3 {}; + +&iic1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + pinctrl-0 = <&iic1_default>; + pinctrl-names = "default"; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; +}; + +&trng { + status = "okay"; +}; + +&spi1 { + pinctrl-0 = <&spi1_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&flash1 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@0 { + label = "storage"; + reg = <0X0 DT_SIZE_K(12)>; + }; + }; +}; diff --git a/boards/renesas/ek_ra8m1/ek_ra8m1.yaml b/boards/renesas/ek_ra8m1/ek_ra8m1.yaml new file mode 100644 index 00000000000..28c7aa4296b --- /dev/null +++ b/boards/renesas/ek_ra8m1/ek_ra8m1.yaml @@ -0,0 +1,12 @@ +identifier: ek_ra8m1 +name: Renesas EK-RA8M1 +type: mcu +arch: arm +ram: 1024 +flash: 2048 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - uart diff --git a/boards/renesas/ek_ra8m1/ek_ra8m1_defconfig b/boards/renesas/ek_ra8m1/ek_ra8m1_defconfig new file mode 100644 index 00000000000..dca93f2b9e0 --- /dev/null +++ b/boards/renesas/ek_ra8m1/ek_ra8m1_defconfig @@ -0,0 +1,20 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=480000000 + +# Enable GPIO +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_CLOCK_CONTROL=y + +CONFIG_FLASH=y diff --git a/boards/renesas/fpb_ra6e1/Kconfig.fpb_ra6e1 b/boards/renesas/fpb_ra6e1/Kconfig.fpb_ra6e1 new file mode 100644 index 00000000000..03c2ffd080a --- /dev/null +++ b/boards/renesas/fpb_ra6e1/Kconfig.fpb_ra6e1 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FPB_RA6E1 + select SOC_R7FA6E10F2CFP diff --git a/boards/renesas/fpb_ra6e1/board.cmake b/boards/renesas/fpb_ra6e1/board.cmake new file mode 100644 index 00000000000..f4e7c1669a5 --- /dev/null +++ b/boards/renesas/fpb_ra6e1/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R7FA6E10F") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/fpb_ra6e1/board.yml b/boards/renesas/fpb_ra6e1/board.yml new file mode 100644 index 00000000000..ed1e0a18bfd --- /dev/null +++ b/boards/renesas/fpb_ra6e1/board.yml @@ -0,0 +1,5 @@ +board: + name: fpb_ra6e1 + vendor: renesas + socs: + - name: r7fa6e10f2cfp diff --git a/boards/renesas/fpb_ra6e1/doc/fpb-ra6e1-board.webp b/boards/renesas/fpb_ra6e1/doc/fpb-ra6e1-board.webp new file mode 100644 index 00000000000..f11bcf13039 Binary files /dev/null and b/boards/renesas/fpb_ra6e1/doc/fpb-ra6e1-board.webp differ diff --git a/boards/renesas/fpb_ra6e1/doc/index.rst b/boards/renesas/fpb_ra6e1/doc/index.rst new file mode 100644 index 00000000000..17332f0c5e2 --- /dev/null +++ b/boards/renesas/fpb_ra6e1/doc/index.rst @@ -0,0 +1,150 @@ +.. _fpb_ra6e1: + +RA6E1 Fast Prototyping Board +############################ + +Overview +******** + +The Renesas RA6E1 group uses the high-performance Arm® Cortex®-M33 core with +TrustZone®. The RA6E1 is suitable for entry IoT applications requiring streamlined +feature and connectivity integration including Ethernet, and unprecedented performance +with 790.75 CoreMark, which are 3.95CoreMark / Mhz. + +The key features of the FPB-RA6E1 board are categorized in three groups as follow: + +**MCU Native Pin Access** + +- 200MHz Arm Cortex-M33 based RA6E1 MCU in 100 pins, LQFP package +- Native pin access through 2 x 50-pin male headers (not fitted) +- MCU current measurement point for precision current consumption measurement +- Multiple clock sources - Low-precision (~1%) clocks are available internal to + the RA MCU. RA MCU oscillator and sub-clock oscillator crystals, providing + precision 24.000 MHz (not fitted) and 32,768 Hz reference clocks are also available + +**System Control and Ecosystem Access** + +- Two 5V input sources + + - USB (Debug, Full Speed, High Speed) + - External power supply (using 2-pin header) (not fitted) + +- Built-in SEGGER J-Link Emulator On-Board programmer/debugger (SWD) + +- User LEDs and buttons + + - Two User LEDs (green) + - Power LED (green) (not fitted) indicating availability of regulated power + - Debug/power LED (yellow) indicating power and the debug connection + - One User button + - One Reset button + +- Two popular ecosystems expansions + + - Two Digilent PmodTM (SPI, UART) connectors (not fitted) + - Arduino (Uno R3) connector + +- MCU boot configuration jumper + +.. figure:: fpb-ra6e1-board.webp + :align: center + :alt: RA6E1 Evaluation Kit + + FPB-RA6E1 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) + +Hardware +******** +Detailed hardware feature for the RA6E1 MCU group can be found at `RA6E1 Group User's Manual Hardware`_ + +.. figure:: ra6e1-block-diagram.webp + :width: 442px + :align: center + :alt: RA6E1 MCU group feature + + RA6E1 Block diagram (Credit: Renesas Electronics Corporation) + +Detailed hardware feature for the FPB-RA6E1 MCU can be found at `FPB-RA6E1 - User's Manual`_ + +Supported Features +================== + +The below features are currently supported on Zephyr OS for FPB-RA6E1 board: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ + +Other hardware features are currently not supported by the port. + +Programming and Debugging +************************* + +Applications for the ``fpb_ra6e1`` board target configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +Program can be flashed to FPB-RA6E1 via the on-board SEGGER J-Link debugger. +SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ + +To flash the program to board + + 1. Connect to J-Link OB via USB port to host PC + + 2. Make sure J-Link OB jumper is in default configuration as describe in `FPB-RA6E1 - User's Manual`_ + + 3. Execute west command + + .. code-block:: console + + west flash -r jlink + +Debugging +========= + +You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface + +Once downloaded and installed, open Segger Ozone and configure the debug project +like so: + +* Target Device: R7FA6E10F +* Target Interface: SWD +* Target Interface Speed: 4 MHz +* Host Interface: USB +* Program File: + +**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later +version of Segger Ozone + +References +********** +- `FPB-RA6E1 Website`_ +- `RA6E1 MCU group Website`_ + +.. _FPB-RA6E1 Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/fpb-ra6e1-fast-prototyping-board-ra6e1-mcu-group#overview + +.. _RA6E1 MCU group Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra6e1-200mhz-arm-cortex-m33-entry-line-high-performance-streamlined-connectivity + +.. _FPB-RA6E1 - User's Manual: + https://www.renesas.com/us/en/document/mat/fpb-ra6e1-users-manual + +.. _RA6E1 Group User's Manual Hardware: + https://www.renesas.com/us/en/document/mah/ra6e1-group-users-manual-hardware + +.. _Segger Ozone Download: + https://www.segger.com/downloads/jlink#Ozone diff --git a/boards/renesas/fpb_ra6e1/doc/ra6e1-block-diagram.webp b/boards/renesas/fpb_ra6e1/doc/ra6e1-block-diagram.webp new file mode 100644 index 00000000000..b6f70e68ab8 Binary files /dev/null and b/boards/renesas/fpb_ra6e1/doc/ra6e1-block-diagram.webp differ diff --git a/boards/renesas/fpb_ra6e1/fpb_ra6e1-pinctrl.dtsi b/boards/renesas/fpb_ra6e1/fpb_ra6e1-pinctrl.dtsi new file mode 100644 index 00000000000..3c01cb6bec4 --- /dev/null +++ b/boards/renesas/fpb_ra6e1/fpb_ra6e1-pinctrl.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci0_default: sci0_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; diff --git a/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts b/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts new file mode 100644 index 00000000000..6f734989539 --- /dev/null +++ b/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +#include "fpb_ra6e1-pinctrl.dtsi" + +/ { + model = "Renesas FPB-RA6E1"; + compatible = "renesas,ra6e1", "renesas,ra"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + leds { + compatible = "gpio-leds"; + led1: led1 { + gpios = <&ioport4 7 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + led2: led2 { + gpios = <&ioport4 8 GPIO_ACTIVE_HIGH>; + label = "LED2"; + }; + }; + + aliases { + led0 = &led1; + }; +}; + +&sci0 { + pinctrl-0 = <&sci0_default>; + pinctrl-names = "default"; + status = "okay"; + uart0: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&ioport4 { + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&pll { + source = ; + div = ; + mul = <20 0>; + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "application"; + reg = <0x00000000 DT_SIZE_K(512)>; + }; + + storage_partition: partition@80000 { + label = "storage"; + reg = <0x80000 DT_SIZE_K(512)>; + }; + }; +}; diff --git a/boards/renesas/fpb_ra6e1/fpb_ra6e1.yaml b/boards/renesas/fpb_ra6e1/fpb_ra6e1.yaml new file mode 100644 index 00000000000..8942834aca5 --- /dev/null +++ b/boards/renesas/fpb_ra6e1/fpb_ra6e1.yaml @@ -0,0 +1,11 @@ +identifier: fpb_ra6e1 +name: Renesas FPB-RA6E1 +type: mcu +arch: arm +ram: 256 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio diff --git a/boards/renesas/fpb_ra6e1/fpb_ra6e1_defconfig b/boards/renesas/fpb_ra6e1/fpb_ra6e1_defconfig new file mode 100644 index 00000000000..fa7ef716d3f --- /dev/null +++ b/boards/renesas/fpb_ra6e1/fpb_ra6e1_defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000 + +# Enable GPIO +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_NO_GAP_FILL=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_UART_CONSOLE=y +CONFIG_CONSOLE=y + +CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/fpb_ra6e2/Kconfig.fpb_ra6e2 b/boards/renesas/fpb_ra6e2/Kconfig.fpb_ra6e2 new file mode 100644 index 00000000000..d23cc0e3b6d --- /dev/null +++ b/boards/renesas/fpb_ra6e2/Kconfig.fpb_ra6e2 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FPB_RA6E2 + select SOC_R7FA6E2BB3CFM diff --git a/boards/renesas/fpb_ra6e2/board.cmake b/boards/renesas/fpb_ra6e2/board.cmake new file mode 100644 index 00000000000..368e10209f9 --- /dev/null +++ b/boards/renesas/fpb_ra6e2/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R7FA6E2BB") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/fpb_ra6e2/board.yml b/boards/renesas/fpb_ra6e2/board.yml new file mode 100644 index 00000000000..0d28094c404 --- /dev/null +++ b/boards/renesas/fpb_ra6e2/board.yml @@ -0,0 +1,5 @@ +board: + name: fpb_ra6e2 + vendor: renesas + socs: + - name: r7fa6e2bb3cfm diff --git a/boards/renesas/fpb_ra6e2/doc/fpb-ra6e2-board.webp b/boards/renesas/fpb_ra6e2/doc/fpb-ra6e2-board.webp new file mode 100644 index 00000000000..705203f3ec3 Binary files /dev/null and b/boards/renesas/fpb_ra6e2/doc/fpb-ra6e2-board.webp differ diff --git a/boards/renesas/fpb_ra6e2/doc/index.rst b/boards/renesas/fpb_ra6e2/doc/index.rst new file mode 100644 index 00000000000..21acb93f869 --- /dev/null +++ b/boards/renesas/fpb_ra6e2/doc/index.rst @@ -0,0 +1,152 @@ +.. _fpb_ra6e2: + +RA6E2 Fast Prototyping Board +############################ + +Overview +******** + +The FPB-RA6E2, a Fast Prototyping Board for RA6E2 MCU Group, based on +the 200 MHz Arm® Cortex®-M33 core with TrustZone, enables users to +seamlessly evaluate the features of the RA6E2 MCU group and develop +embedded systems applications using Flexible Software Package (FSP) +and e2 studio IDE. The users can use rich on-board features along with +their choice of popular ecosystems add-ons to bring their big ideas to life. + +The key features of the FPB-RA6E2 board are categorized in three groups as follow: + +**MCU Native Pin Access** + +- 200MHz Arm Cortex-M33 based RA6E2 MCU in 64 pins, LQFP package +- 256 kB Code Flash, 40 kB SRAM +- Native pin access through 2 x 32-pin male headers +- MCU current measurement point for precision current consumption measurement +- Multiple clock sources - RA6E2 MCU oscillator and sub-clock oscillator crystals, + providing precision 24.000 MHz and 32,768 Hz reference clock. + Additional low precision clocks are avaialbe internal to the RA6E2 MCU + +**System Control and Ecosystem Access** + +- USB Full Speed Host and Device (micro-AB connector) +- Two 5V input sources + + - USB (Debug, Full Speed) + - External power supply (using 2-pin header) + +- On-board debugger (SWD) + +- User LEDs and buttons + + - Two User LEDs (green) + - Power LED (green) indicating availability of regulated power + - Debug/power LED (yellow) indicating power and the debug connection + - One User button + - One Reset button + +- Two popular ecosystem expansions + + - Two Digilent PmodTM (SPI, UART and I3C) connectors + - Arduino (Uno R3) connectors + +- MCU boot configuration jumper + +.. figure:: fpb-ra6e2-board.webp + :align: center + :alt: RA6E2 Fast Prototyping Board + + FPB-RA6E2 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) + +Hardware +******** +Detailed hardware feature for the RA6E2 MCU group can be found at `RA6E2 Group User's Manual Hardware`_ + +.. figure:: ra6e2-block-diagram.webp + :width: 442px + :align: center + :alt: RA6E2 MCU group feature + + RA6E2 Block diagram (Credit: Renesas Electronics Corporation) + +Detailed hardware feature for the FPB-RA6E2 MCU can be found at `FPB-RA6E2 - User's Manual`_ + +Supported Features +================== + +The below features are currently supported on Zephyr OS for FPB-RA6E2 board: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ + +Other hardware features are currently not supported by the port. + +Programming and Debugging +************************* + +Applications for the ``fpb_ra6e2`` board target configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +Program can be flashed to fpb-RA6E2 via the on-board SEGGER J-Link debugger. +SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ + +To flash the program to board + + 1. Connect to J-Link OB via USB port to host PC + + 2. Make sure J-Link OB jumper is in default configuration as describe in `FPB-RA6E2 - User's Manual`_ + + 3. Execute west command + + .. code-block:: console + + west flash -r jlink + +Debugging +========= + +You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface + +Once downloaded and installed, open Segger Ozone and configure the debug project +like so: + +* Target Device: R7FA6E2BB +* Target Interface: SWD +* Target Interface Speed: 4 MHz +* Host Interface: USB +* Program File: + +**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later +version of Segger Ozone + +References +********** +- `FPB-RA6E2 Website`_ +- `RA6E2 MCU group Website`_ + +.. _FPB-RA6E2 Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/fpb-ra6e2-fast-prototyping-board-ra6e2-mcu-group + +.. _RA6E2 MCU group Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra6e2-entry-line-200mhz-arm-cortex-m33-general-purpose-microcontroller + +.. _FPB-RA6E2 - User's Manual: + https://www.renesas.com/us/en/document/mat/fpb-ra6e2-v1-users-manual + +.. _RA6E2 Group User's Manual Hardware: + https://www.renesas.com/us/en/document/mah/ra6e2-group-users-manual-hardware + +.. _Segger Ozone Download: + https://www.segger.com/downloads/jlink#Ozone diff --git a/boards/renesas/fpb_ra6e2/doc/ra6e2-block-diagram.webp b/boards/renesas/fpb_ra6e2/doc/ra6e2-block-diagram.webp new file mode 100644 index 00000000000..7eeb1bc516f Binary files /dev/null and b/boards/renesas/fpb_ra6e2/doc/ra6e2-block-diagram.webp differ diff --git a/boards/renesas/fpb_ra6e2/fpb_ra6e2-pinctrl.dtsi b/boards/renesas/fpb_ra6e2/fpb_ra6e2-pinctrl.dtsi new file mode 100644 index 00000000000..851d8543bee --- /dev/null +++ b/boards/renesas/fpb_ra6e2/fpb_ra6e2-pinctrl.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci0_default: sci0_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; +}; diff --git a/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts b/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts new file mode 100644 index 00000000000..bc7baa6c5ce --- /dev/null +++ b/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +#include "fpb_ra6e2-pinctrl.dtsi" + +/ { + model = "Renesas FPB-RA6E2"; + compatible = "renesas,ra6e2", "renesas,ra"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + leds { + compatible = "gpio-leds"; + led1: led1 { + gpios = <&ioport2 7 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + led2: led2 { + gpios = <&ioport2 6 GPIO_ACTIVE_HIGH>; + label = "LED2"; + }; + }; + + aliases { + led0 = &led1; + led1 = &led2; + }; +}; + +&sci0 { + pinctrl-0 = <&sci0_default>; + pinctrl-names = "default"; + status = "okay"; + uart0: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&ioport2 { + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "application"; + reg = <0x00000000 DT_SIZE_K(128)>; + }; + + storage_partition: partition@20000 { + label = "storage"; + reg = <0x20000 DT_SIZE_K(128)>; + }; + }; +}; + +&subclk { + status = "okay"; +}; + +&pll { + source = ; + div = ; + mul = <10 0>; + status = "okay"; +}; diff --git a/boards/renesas/fpb_ra6e2/fpb_ra6e2.yaml b/boards/renesas/fpb_ra6e2/fpb_ra6e2.yaml new file mode 100644 index 00000000000..edd2002b2a3 --- /dev/null +++ b/boards/renesas/fpb_ra6e2/fpb_ra6e2.yaml @@ -0,0 +1,11 @@ +identifier: fpb_ra6e2 +name: Renesas FPB-RA6E2 +type: mcu +arch: arm +ram: 40 +flash: 256 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio diff --git a/boards/renesas/fpb_ra6e2/fpb_ra6e2_defconfig b/boards/renesas/fpb_ra6e2/fpb_ra6e2_defconfig new file mode 100644 index 00000000000..92bb425cfa8 --- /dev/null +++ b/boards/renesas/fpb_ra6e2/fpb_ra6e2_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000 + +# Enable GPIO +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_UART_CONSOLE=y +CONFIG_CONSOLE=y + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/mck_ra8t1/Kconfig.mck_ra8t1 b/boards/renesas/mck_ra8t1/Kconfig.mck_ra8t1 new file mode 100644 index 00000000000..49674f30ac2 --- /dev/null +++ b/boards/renesas/mck_ra8t1/Kconfig.mck_ra8t1 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MCK_RA8T1 + select SOC_R7FA8T1AHECBD diff --git a/boards/renesas/mck_ra8t1/board.cmake b/boards/renesas/mck_ra8t1/board.cmake new file mode 100644 index 00000000000..17d45a20094 --- /dev/null +++ b/boards/renesas/mck_ra8t1/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R7FA8T1AH") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/mck_ra8t1/board.yml b/boards/renesas/mck_ra8t1/board.yml new file mode 100644 index 00000000000..d7227163611 --- /dev/null +++ b/boards/renesas/mck_ra8t1/board.yml @@ -0,0 +1,5 @@ +board: + name: mck_ra8t1 + vendor: renesas + socs: + - name: r7fa8t1ahecbd diff --git a/boards/renesas/mck_ra8t1/doc/index.rst b/boards/renesas/mck_ra8t1/doc/index.rst new file mode 100644 index 00000000000..f223004c969 --- /dev/null +++ b/boards/renesas/mck_ra8t1/doc/index.rst @@ -0,0 +1,184 @@ +.. _mcb_ra8t1: + +RA8T1 Evaluation Kit +#################### + +Overview +******** + +The **MCK-RA8T1** is a development kit that enables easy evaluation of motor control using permanent magnet synchronous +motors (brushless DC motors). More detailed information about the features of this toolkit and it's applications can be +found here: `MCK-RA8T1 Website`_ + +MCK-RA8T1 kit includes the items below: + +- RA8T1 CPU board (`MCB-RA8T1`_) +- Inverter board (`MCI-LV-1`_) +- Communication board (`MC-COM`_) +- Permanent magnet synchronous motors +- Accessories (cables, standoffs, etc.) + +.. figure:: mck-ra8t1-product-contents.jpg + :align: center + :alt: RA8T1 Evaluation Kit + + MCK-RA8T1 product contents (Credit: Renesas Electronics Corporation) + +**MCB-RA8T1** is a CPU board for motor control equipped with RA8T1. Motor control using RA8T1 can be easily realized by +using it in combination with a supported inverter board. The RA8T1 MCU can be evaluated using this board alone. + +By using a supported communication board, the CPU board can be electrically isolated from the PC for safe motor control +evaluation and debugging. + +The specifications of the CPU board are shown below: + +**MCU specifications** + +- 480MHz Arm Cortex-M85 based RA8T1 MCU in 224 pins, BGA package +- ROM/RAM size: 2MB/1MB +- MCU input clock: 24MHz (Generate with external crystal oscillator) +- Power supply: DC 5V, select one way automatically from the below: + + - Power is supplied from compatible inverter board + - Power is supplied from USB connector + +**Connector** + +- Inverter board connector (2 pair) +- USB connector for J-Link OB +- USB connector for RA8T1 +- SCI connector for Renesas Motor Workbench communication +- Through hole for CAN communication +- 20 pin through hole for Arm debugger +- Pmod connectors (Type6A + Type2A/3A) +- Ethrnet connector +- microSD card connector + +.. figure:: ra8t1-cpu-board-block-diagram.jpg + :align: center + :alt: RA8T1 Evaluation Kit + + CPU Board Layout (Credit: Renesas Electronics Corporation) + +**Onboard debugger** + +This product has the onboard debugger circuit, J-Link On-Board (hereinafter called “J-Link-OB”). You can +write a program (firmware) of RA8T1 with it. + +Hardware +******** +Detail Hardware feature for the RA8T1 MCU group can be found at `RA8T1 Group User's Manual Hardware`_ + +.. figure:: ra8t1-block-diagram.png + :width: 442px + :align: center + :alt: RA8T1 MCU group feature + + RA8T1 Block diagram (Credit: Renesas Electronics Corporation) + +Detail Hardware feature for the MCB-RA8T1 board can be found at `MCB-RA8T1 - User's Manual`_ + +Supported Features +================== + +The below features are currently supported on Zephyr OS for MCB-RA8T1 board: + ++--------------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++==============+============+======================+ +| GPIO | on-chip | gpio | ++--------------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++--------------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++--------------+------------+----------------------+ +| UART | on-chip | serial | ++--------------+------------+----------------------+ +| CLOCK | on-chip | clock control | ++--------------+------------+----------------------+ +| ENTROPY | on-chip | entropy | ++--------------+------------+----------------------+ +| SPI | on-chip | spi | ++--------------+------------+----------------------+ +| FLASH | on-chip | flash | ++--------------+------------+----------------------+ + +Other hardware features are currently not supported by the port. + +Programming and Debugging +************************* + +Applications for the ``mcb_ra8t1`` board configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +**Note:** Only support from SDK v0.16.6 in which GCC for Cortex Arm-M85 was available. +To build for EK-RA8M1 user need to get and install GNU Arm Embedded toolchain from https://github.com/zephyrproject-rtos/sdk-ng/releases/tag/v0.16.6 + +Flashing +======== + +Program can be flashed to MCB-RA8T1 via the on-board SEGGER J-Link debugger. +SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ + +To flash the program to board + + 1. Connect to J-Link OB via USB port to host PC + + 2. Make sure J-Link OB jumper is in default configuration as describe in `MCB-RA8T1 - User's Manual`_ + + 3. Execute west command + + .. code-block:: console + + west flash -r jlink + +Debugging +========= + +You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface + +Once downloaded and installed, open Segger Ozone and configure the debug project +like so: + +* Target Device: R7FA8T1AH +* Target Interface: SWD +* Target Interface Speed: 4 MHz +* Host Interface: USB +* Program File: + +**Note:** It's verified that debug is OK on Segger Ozone v3.30d so please use this or later +version of Segger Ozone + +References +********** +- `MCB-RA8T1 Website`_ +- `RA8T1 MCU group Website`_ + +.. _MCB-RA8T1 Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/rtk0ema5k0c00000bj-mcb-ra8t1-cpu-board-ra8t1-mcu-group + +.. _RA8T1 MCU group Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra8t1-480-mhz-arm-cortex-m85-based-motor-control-microcontroller-helium-and-trustzone + +.. _MCB-RA8T1 - User's Manual: + https://www.renesas.com/us/en/document/mat/mcb-ra8t1-users-manual?r=25466356 + +.. _RA8T1 Group User's Manual Hardware: + https://www.renesas.com/us/en/document/mah/ra8t1-group-users-manual-hardware?r=25463106 + +.. _Segger Ozone Download: + https://www.segger.com/downloads/jlink#Ozone + +.. _MCK-RA8T1 Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/rtk0ema5k0s00020bj-mck-ra8t1-renesas-flexible-motor-control-kit-ra8t1-mcu-group + +.. _MCB-RA8T1: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/rtk0ema5k0c00000bj-mcb-ra8t1-cpu-board-ra8t1-mcu-group + +.. _MCI-LV-1: + https://www.renesas.com/us/en/products/power-power-management/fet-motor-drivers/rtk0em0000s04020bj-mci-lv-1-renesas-flexible-motor-control-inverter-board-low-voltage-48v10a-three-phase-bldcpmsm-motor + +.. _MC-COM: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rx-32-bit-performance-efficiency-mcus/rtk0emxc90s00000bj-mc-com-renesas-flexible-motor-control-communication-board diff --git a/boards/renesas/mck_ra8t1/doc/mck-ra8t1-product-contents.jpg b/boards/renesas/mck_ra8t1/doc/mck-ra8t1-product-contents.jpg new file mode 100644 index 00000000000..987f43ae789 Binary files /dev/null and b/boards/renesas/mck_ra8t1/doc/mck-ra8t1-product-contents.jpg differ diff --git a/boards/renesas/mck_ra8t1/doc/ra8t1-block-diagram.png b/boards/renesas/mck_ra8t1/doc/ra8t1-block-diagram.png new file mode 100644 index 00000000000..65cc7e554cd Binary files /dev/null and b/boards/renesas/mck_ra8t1/doc/ra8t1-block-diagram.png differ diff --git a/boards/renesas/mck_ra8t1/doc/ra8t1-cpu-board-block-diagram.jpg b/boards/renesas/mck_ra8t1/doc/ra8t1-cpu-board-block-diagram.jpg new file mode 100644 index 00000000000..9e16a7364d5 Binary files /dev/null and b/boards/renesas/mck_ra8t1/doc/ra8t1-cpu-board-block-diagram.jpg differ diff --git a/boards/renesas/mck_ra8t1/mck_ra8t1-pinctrl.dtsi b/boards/renesas/mck_ra8t1/mck_ra8t1-pinctrl.dtsi new file mode 100644 index 00000000000..c8183975f37 --- /dev/null +++ b/boards/renesas/mck_ra8t1/mck_ra8t1-pinctrl.dtsi @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci3_default: sci3_default { + group1 { + /* tx */ + psels = ; + drive-strength = "medium"; + }; + group2 { + /* rx */ + psels = ; + }; + }; + + spi0_default: spi0_default { + group1 { + /* MISO MOSI RSPCK SSL*/ + psels = , + , + , + ; + }; + }; +}; diff --git a/boards/renesas/mck_ra8t1/mck_ra8t1.dts b/boards/renesas/mck_ra8t1/mck_ra8t1.dts new file mode 100644 index 00000000000..f7046d49149 --- /dev/null +++ b/boards/renesas/mck_ra8t1/mck_ra8t1.dts @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +#include "mck_ra8t1-pinctrl.dtsi" + +/ { + model = "Renesas MCK-RA8T1"; + compatible = "renesas,ra8t1", "renesas,ra8"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart3; + zephyr,shell-uart = &uart3; + zephyr,entropy = &trng; + zephyr,flash-controller = &flash1; + }; + + leds { + compatible = "gpio-leds"; + led1: led1 { + gpios = <&ioporta 12 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + led2: led2 { + gpios = <&ioporta 14 GPIO_ACTIVE_HIGH>; + label = "LED2"; + }; + led3: led3 { + gpios = <&ioport6 6 GPIO_ACTIVE_HIGH>; + label = "LED3"; + }; + led4: led4 { + gpios = <&ioporta 6 GPIO_ACTIVE_HIGH>; + label = "LED4"; + }; + }; + + aliases { + led0 = &led1; + }; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&pll { + source = ; + div = ; + mul = <80 0>; + divp = ; + freqp = ; + divq = ; + freqq = ; + divr = ; + freqr = ; + status = "okay"; +}; + +&sciclk { + clk-src = ; + clk-div = ; + status = "okay"; +}; + +&ioport6 { + status = "okay"; +}; + +&ioporta { + status = "okay"; +}; + +&sci3 { + pinctrl-0 = <&sci3_default>; + pinctrl-names = "default"; + status = "okay"; + uart3: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&trng { + status = "okay"; +}; + +&spi0 { + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&flash1 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@0 { + label = "storage"; + reg = <0X0 DT_SIZE_K(12)>; + }; + }; +}; diff --git a/boards/renesas/mck_ra8t1/mck_ra8t1.yaml b/boards/renesas/mck_ra8t1/mck_ra8t1.yaml new file mode 100644 index 00000000000..52ef233d98f --- /dev/null +++ b/boards/renesas/mck_ra8t1/mck_ra8t1.yaml @@ -0,0 +1,12 @@ +identifier: mck_ra8t1 +name: Renesas MCK-RA8T1 +type: mcu +arch: arm +ram: 1024 +flash: 2048 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - uart diff --git a/boards/renesas/mck_ra8t1/mck_ra8t1_defconfig b/boards/renesas/mck_ra8t1/mck_ra8t1_defconfig new file mode 100644 index 00000000000..29889ab9ae6 --- /dev/null +++ b/boards/renesas/mck_ra8t1/mck_ra8t1_defconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=480000000 + +# Enable GPIO +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y + +CONFIG_CLOCK_CONTROL=y + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_NO_GAP_FILL=y + +CONFIG_FLASH=y diff --git a/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_r7.rst b/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_r7.rst index 5fcd4fa0909..f77c16196fa 100644 --- a/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_r7.rst +++ b/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_r7.rst @@ -224,7 +224,7 @@ Debugging First of all, open your serial terminal. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57-pinctrl.dtsi b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57-pinctrl.dtsi index 6dc65b03313..37c6c099176 100644 --- a/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57-pinctrl.dtsi +++ b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57-pinctrl.dtsi @@ -15,44 +15,126 @@ pin = ; }; + sd0_clk: sd0_clk { + pin = ; + power-source = ; + }; + + sd0_cmd: sd0_cmd { + pin = ; + power-source = ; + }; + + sd0_data0: sd0_data0 { + pin = ; + power-source = ; + }; + + sd0_data1: sd0_data1 { + pin = ; + power-source = ; + }; + + sd0_data2: sd0_data2 { + pin = ; + power-source = ; + }; + + sd0_data3: sd0_data3 { + pin = ; + power-source = ; + }; + + sd0_clk_uhs: sd0_clk_uhs { + pin = ; + power-source = ; + }; + + sd0_cmd_uhs: sd0_cmd_uhs { + pin = ; + power-source = ; + }; + + sd0_data0_uhs: sd0_data0_uhs { + pin = ; + power-source = ; + }; + + sd0_data1_uhs: sd0_data1_uhs { + pin = ; + power-source = ; + }; + + sd0_data2_uhs: sd0_data2_uhs { + pin = ; + power-source = ; + }; + + sd0_data3_uhs: sd0_data3_uhs { + pin = ; + power-source = ; + }; + + /* note: CD pin is fixed at 3.3V */ + sd0_cd: sd0_cd { + pin = ; + power-source = ; + }; + + /* note: WP pin is fixed at 3.3V */ + sd0_wp: sd0_wp { + pin = ; + power-source = ; + }; + emmc2_clk: emmc2_clk { pin = ; + power-source = ; }; emmc2_cmd: emmc2_cmd { pin = ; + power-source = ; }; emmc2_data0: emmc2_data0 { pin = ; + power-source = ; }; emmc2_data1: emmc2_data1 { pin = ; + power-source = ; }; emmc2_data2: emmc2_data2 { pin = ; + power-source = ; }; emmc2_data3: emmc2_data3 { pin = ; + power-source = ; }; emmc2_data4: emmc2_data4 { pin = ; + power-source = ; }; emmc2_data5: emmc2_data5 { pin = ; + power-source = ; }; emmc2_data6: emmc2_data6 { pin = ; + power-source = ; }; emmc2_data7: emmc2_data7 { pin = ; + power-source = ; }; emmc2_ds: emmc2_ds { diff --git a/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57.dts b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57.dts index 599a0f25314..117b6bb4e74 100644 --- a/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57.dts +++ b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57.dts @@ -8,6 +8,7 @@ /dts-v1/; #include #include +#include #include "rcar_h3ulcb_r8a77951_a57-pinctrl.dtsi" / { @@ -28,6 +29,52 @@ aliases { sdhc0 = &emmc2; }; + + vcc_sd0: regulator-vcc-sd0 { + compatible = "regulator-fixed"; + + regulator-name = "SD0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + enable-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; + }; + + vccq_sd0: regulator-vccq-sd0 { + compatible = "regulator-gpio"; + + regulator-name = "SD0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + states = <3300000 1>, <1800000 0>; + + regulator-always-on; + }; +}; + +&gpio5 { + status = "okay"; +}; + +&sd0 { + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp + &sd0_data0 &sd0_data1 &sd0_data2 &sd0_data3>; + pinctrl-1 = <&sd0_clk_uhs &sd0_cmd_uhs &sd0_cd &sd0_wp + &sd0_data0_uhs &sd0_data1_uhs &sd0_data2_uhs &sd0_data3_uhs>; + pinctrl-names = "default", "uhs"; + disk { + compatible = "zephyr,sdmmc-disk"; + status = "okay"; + }; + + vmmc-supply = <&vcc_sd0>; + vqmmc-supply = <&vccq_sd0>; + + bus-width = <4>; + mmc-sdr104-support; + status = "okay"; }; &scif2 { diff --git a/boards/renesas/rcar_salvator_x/doc/rcar_salvator_x.rst b/boards/renesas/rcar_salvator_x/doc/rcar_salvator_x.rst index e95049a42c4..3e7b5772944 100644 --- a/boards/renesas/rcar_salvator_x/doc/rcar_salvator_x.rst +++ b/boards/renesas/rcar_salvator_x/doc/rcar_salvator_x.rst @@ -147,7 +147,7 @@ Debugging First of all, open your serial terminal. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/renesas/rcar_salvator_xs/rcar_salvator_xs-pinctrl.dtsi b/boards/renesas/rcar_salvator_xs/rcar_salvator_xs-pinctrl.dtsi index b563a720079..f23f4b3c1b1 100644 --- a/boards/renesas/rcar_salvator_xs/rcar_salvator_xs-pinctrl.dtsi +++ b/boards/renesas/rcar_salvator_xs/rcar_salvator_xs-pinctrl.dtsi @@ -17,42 +17,52 @@ emmc2_clk: emmc2_clk { pin = ; + power-source = ; }; emmc2_cmd: emmc2_cmd { pin = ; + power-source = ; }; emmc2_data0: emmc2_data0 { pin = ; + power-source = ; }; emmc2_data1: emmc2_data1 { pin = ; + power-source = ; }; emmc2_data2: emmc2_data2 { pin = ; + power-source = ; }; emmc2_data3: emmc2_data3 { pin = ; + power-source = ; }; emmc2_data4: emmc2_data4 { pin = ; + power-source = ; }; emmc2_data5: emmc2_data5 { pin = ; + power-source = ; }; emmc2_data6: emmc2_data6 { pin = ; + power-source = ; }; emmc2_data7: emmc2_data7 { pin = ; + power-source = ; }; emmc2_ds: emmc2_ds { diff --git a/boards/renesas/rcar_spider_s4/doc/rcar_spider_a55.rst b/boards/renesas/rcar_spider_s4/doc/rcar_spider_a55.rst index 2f45cf1521e..b66975af164 100644 --- a/boards/renesas/rcar_spider_s4/doc/rcar_spider_a55.rst +++ b/boards/renesas/rcar_spider_s4/doc/rcar_spider_a55.rst @@ -63,7 +63,7 @@ One of the ways to load Zephyr is shown below. tftp 0x48000000 booti 0x48000000 -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/renesas/rcar_spider_s4/doc/rcar_spider_r52.rst b/boards/renesas/rcar_spider_s4/doc/rcar_spider_r52.rst index d7fec18e036..9c7be4d8f99 100644 --- a/boards/renesas/rcar_spider_s4/doc/rcar_spider_r52.rst +++ b/boards/renesas/rcar_spider_s4/doc/rcar_spider_r52.rst @@ -161,7 +161,7 @@ Debugging First of all, open your serial terminal. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/renesas/rcar_spider_s4/rcar_spider_s4_r8a779f0_a55-pinctrl.dtsi b/boards/renesas/rcar_spider_s4/rcar_spider_s4_r8a779f0_a55-pinctrl.dtsi index 50739a237be..9d99d8cb89c 100644 --- a/boards/renesas/rcar_spider_s4/rcar_spider_s4_r8a779f0_a55-pinctrl.dtsi +++ b/boards/renesas/rcar_spider_s4/rcar_spider_s4_r8a779f0_a55-pinctrl.dtsi @@ -14,4 +14,58 @@ hscif0_data_rx_default: hscif0_data_rx_default { pin = ; }; + + mmc_clk: mmc_clk { + pin = ; + power-source = ; + }; + + mmc_cmd: mmc_cmd { + pin = ; + power-source = ; + }; + + mmc_data0: mmc_data0 { + pin = ; + power-source = ; + }; + + mmc_data1: mmc_data1 { + pin = ; + power-source = ; + }; + + mmc_data2: mmc_data2 { + pin = ; + power-source = ; + }; + + mmc_data3: mmc_data3 { + pin = ; + power-source = ; + }; + + mmc_data4: mmc_data4 { + pin = ; + power-source = ; + }; + + mmc_data5: mmc_data5 { + pin = ; + power-source = ; + }; + + mmc_data6: mmc_data6 { + pin = ; + power-source = ; + }; + + mmc_data7: mmc_data7 { + pin = ; + power-source = ; + }; + + mmc_ds: mmc_ds { + pin = ; + }; }; diff --git a/boards/renesas/rcar_spider_s4/rcar_spider_s4_r8a779f0_a55.dts b/boards/renesas/rcar_spider_s4/rcar_spider_s4_r8a779f0_a55.dts index 2075b90495c..3a7b5c4eb82 100644 --- a/boards/renesas/rcar_spider_s4/rcar_spider_s4_r8a779f0_a55.dts +++ b/boards/renesas/rcar_spider_s4/rcar_spider_s4_r8a779f0_a55.dts @@ -30,3 +30,22 @@ current-speed = <1843200>; status = "okay"; }; + +&mmc0 { + pinctrl-0 = <&mmc_clk &mmc_cmd &mmc_ds + &mmc_data0 &mmc_data1 &mmc_data2 &mmc_data3 + &mmc_data4 &mmc_data5 &mmc_data6 &mmc_data7>; + pinctrl-1 = <&mmc_clk &mmc_cmd &mmc_ds + &mmc_data0 &mmc_data1 &mmc_data2 &mmc_data3 + &mmc_data4 &mmc_data5 &mmc_data6 &mmc_data7>; + pinctrl-names = "default", "uhs"; + disk { + compatible = "zephyr,mmc-disk"; + status = "okay"; + }; + bus-width = <8>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + non-removable; + status = "okay"; +}; diff --git a/boards/renesas/rzt2m_starterkit/doc/index.rst b/boards/renesas/rzt2m_starterkit/doc/index.rst index 72dc6615f64..eecaa1bc3c6 100644 --- a/boards/renesas/rzt2m_starterkit/doc/index.rst +++ b/boards/renesas/rzt2m_starterkit/doc/index.rst @@ -67,7 +67,7 @@ By default, the board is configured for use with: * UART0 connected to the USB serial port (pins K18, K19), * UART3 connected to the PMOD Header (J25, pins H16, G20), -* LEDs defined as `led0`, `led1`, `led2` and `led3`, +* LEDs defined as ``led0``, ``led1``, ``led2`` and ``led3``, The Zephyr console uses UART0. @@ -78,7 +78,7 @@ Debugging ========= Connect to the board using the J-Link On-board USB connector. -Use `west` to start the debug server: +Use ``west`` to start the debug server: .. code-block:: console diff --git a/boards/renode/riscv32_virtual/riscv32_virtual.yaml b/boards/renode/riscv32_virtual/riscv32_virtual.yaml index 600a5679f7e..64cab1f32ba 100644 --- a/boards/renode/riscv32_virtual/riscv32_virtual.yaml +++ b/boards/renode/riscv32_virtual/riscv32_virtual.yaml @@ -12,5 +12,8 @@ testing: ignore_tags: - net - bluetooth + renode: + uart: sysbus.uart0 + resc: boards/renode/riscv32_virtual/support/riscv32_virtual.resc supported: - uart diff --git a/boards/renode/riscv32_virtual/support/riscv32_virtual.resc b/boards/renode/riscv32_virtual/support/riscv32_virtual.resc index 87e327287b6..dedbc699078 100644 --- a/boards/renode/riscv32_virtual/support/riscv32_virtual.resc +++ b/boards/renode/riscv32_virtual/support/riscv32_virtual.resc @@ -12,6 +12,6 @@ cpu PerformanceInMips 4 macro reset """ - sysbus LoadELF $bin + sysbus LoadELF $elf """ runMacro $reset diff --git a/boards/ronoth/lodev/ronoth_lodev_defconfig b/boards/ronoth/lodev/ronoth_lodev_defconfig index ccccd7ca20f..ffeb9e887ac 100644 --- a/boards/ronoth/lodev/ronoth_lodev_defconfig +++ b/boards/ronoth/lodev/ronoth_lodev_defconfig @@ -14,9 +14,3 @@ CONFIG_UART_CONSOLE=y # GPIO Controller CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/ruuvi/ruuvitag/Kconfig b/boards/ruuvi/ruuvitag/Kconfig deleted file mode 100644 index 5e6b96e1a5b..00000000000 --- a/boards/ruuvi/ruuvitag/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Ruuvi-RuuviTag board configuration - -# Copyright (c) 2020 Ruuvi Innovations Ltd (Oy) -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_RUUVI_RUUVITAG diff --git a/boards/ruuvi/ruuvitag/ruuvi_ruuvitag.dts b/boards/ruuvi/ruuvitag/ruuvi_ruuvitag.dts index 1170759c24a..7b61f1f0e46 100644 --- a/boards/ruuvi/ruuvitag/ruuvi_ruuvitag.dts +++ b/boards/ruuvi/ruuvitag/ruuvi_ruuvitag.dts @@ -55,6 +55,10 @@ }; }; +® { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; diff --git a/boards/sc/scobc_module1/doc/index.rst b/boards/sc/scobc_module1/doc/index.rst index fd6f82e0b8e..260a062692f 100644 --- a/boards/sc/scobc_module1/doc/index.rst +++ b/boards/sc/scobc_module1/doc/index.rst @@ -73,7 +73,7 @@ Flashing Here is an example for building and flashing the \`hello\_world\` application for the board: -Here is an example for building and flashing the :ref:`hello_world` application +Here is an example for building and flashing the :zephyr:code-sample:`hello_world` application for the default design: .. zephyr-app-commands:: @@ -94,7 +94,7 @@ above steps. It was merely written to internal RAM in the FPGA. Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/seagate/faze/support/openocd.cfg b/boards/seagate/faze/support/openocd.cfg index d7dc6d82c0d..770d566fadd 100644 --- a/boards/seagate/faze/support/openocd.cfg +++ b/boards/seagate/faze/support/openocd.cfg @@ -36,4 +36,4 @@ $_TARGETNAME configure -event reset-end { # Enable Zephyr thread awareness. $_TARGETNAME configure -rtos Zephyr -adapter_khz 100 +adapter speed 100 diff --git a/boards/seagate/legend/legend.dts b/boards/seagate/legend/legend.dts index 245d2c8de7d..d230345dd07 100644 --- a/boards/seagate/legend/legend.dts +++ b/boards/seagate/legend/legend.dts @@ -21,7 +21,6 @@ aliases { watchdog0 = &iwdg; - spi-flash0 = &spi_nor; led-strip = &led_strip_spi; }; diff --git a/boards/seagate/legend/legend_defconfig b/boards/seagate/legend/legend_defconfig index 8bb683ce992..c60dfffbc3b 100644 --- a/boards/seagate/legend/legend_defconfig +++ b/boards/seagate/legend/legend_defconfig @@ -10,9 +10,3 @@ CONFIG_UART_CONSOLE=y # GPIO Controller CONFIG_GPIO=y - -# Clock Control -CONFIG_CLOCK_CONTROL=y - -# Enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/seco/stm32f3_seco_d23/doc/index.rst b/boards/seco/stm32f3_seco_d23/doc/index.rst index 90981205b5b..bc2626767f0 100644 --- a/boards/seco/stm32f3_seco_d23/doc/index.rst +++ b/boards/seco/stm32f3_seco_d23/doc/index.rst @@ -194,7 +194,9 @@ Flashing an application to SECO SBC-3.5-PX30 First, connect the SECO SBC-3.5-PX30 to your host computer using CN56 connector to an ST-Link. + The pinout is (1-8): + - VDD - UART1_TX - UART1_RX @@ -206,7 +208,7 @@ The pinout is (1-8): Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/seco/stm32f3_seco_d23/stm32f3_seco_d23_defconfig b/boards/seco/stm32f3_seco_d23/stm32f3_seco_d23_defconfig index 9432c4e8149..9a2864e7202 100644 --- a/boards/seco/stm32f3_seco_d23/stm32f3_seco_d23_defconfig +++ b/boards/seco/stm32f3_seco_d23/stm32f3_seco_d23_defconfig @@ -19,11 +19,5 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y -# clock configuration -CONFIG_CLOCK_CONTROL=y - # enable regulators CONFIG_REGULATOR=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/seeed/lora_e5_dev_board/doc/lora_e5_dev_board.rst b/boards/seeed/lora_e5_dev_board/doc/lora_e5_dev_board.rst index e2683c5489d..ca234210734 100644 --- a/boards/seeed/lora_e5_dev_board/doc/lora_e5_dev_board.rst +++ b/boards/seeed/lora_e5_dev_board/doc/lora_e5_dev_board.rst @@ -112,6 +112,7 @@ features: Other hardware features are not yet supported on this Zephyr port. The default configuration can be found in: + - :zephyr_file:`boards/seeed/lora_e5_dev_board/lora_e5_dev_board_defconfig` - :zephyr_file:`boards/seeed/lora_e5_dev_board/lora_e5_dev_board.dts` @@ -241,7 +242,7 @@ Flashing an application to LoRa-E5 Dev board Connect the LoRa-E5 to your host computer using the external debug probe. Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your board: Per default the console on ``usart1`` is available on the USB Type C connector diff --git a/boards/seeed/lora_e5_dev_board/lora_e5_dev_board_defconfig b/boards/seeed/lora_e5_dev_board/lora_e5_dev_board_defconfig index 17aa77ac7f8..4f46dab5612 100644 --- a/boards/seeed/lora_e5_dev_board/lora_e5_dev_board_defconfig +++ b/boards/seeed/lora_e5_dev_board/lora_e5_dev_board_defconfig @@ -7,9 +7,6 @@ CONFIG_SERIAL=y # Enable GPIO CONFIG_GPIO=y -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - # Console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y @@ -22,6 +19,3 @@ CONFIG_HW_STACK_PROTECTION=y # Enable regulator for the power-rails CONFIG_REGULATOR=y - -# Enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/seeed/lora_e5_mini/doc/index.rst b/boards/seeed/lora_e5_mini/doc/index.rst index 7f36a92e7d6..78227fcb62b 100644 --- a/boards/seeed/lora_e5_mini/doc/index.rst +++ b/boards/seeed/lora_e5_mini/doc/index.rst @@ -178,7 +178,7 @@ Flashing an application to LoRa-E5 mini Connect the LoRa-E5 to your host computer using the external debug probe. Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your board: Per default the console on ``usart1`` is available on the USB Type C connector diff --git a/boards/seeed/lora_e5_mini/lora_e5_mini_defconfig b/boards/seeed/lora_e5_mini/lora_e5_mini_defconfig index 0d6dc9f80d3..8b09bb0775d 100644 --- a/boards/seeed/lora_e5_mini/lora_e5_mini_defconfig +++ b/boards/seeed/lora_e5_mini/lora_e5_mini_defconfig @@ -4,9 +4,6 @@ CONFIG_SERIAL=y # enable GPIO CONFIG_GPIO=y -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - # console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y @@ -16,6 +13,3 @@ CONFIG_ARM_MPU=y # Enable HW stack protection CONFIG_HW_STACK_PROTECTION=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/seeed/seeeduino_xiao/doc/index.rst b/boards/seeed/seeeduino_xiao/doc/index.rst index aa11b812c38..8f3614918f6 100644 --- a/boards/seeed/seeeduino_xiao/doc/index.rst +++ b/boards/seeed/seeeduino_xiao/doc/index.rst @@ -120,7 +120,7 @@ will be entered automatically when you run :code:`west flash`. Flashing ======== -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/seeed/wio_terminal/support/openocd.cfg b/boards/seeed/wio_terminal/support/openocd.cfg index ce9baa8012f..6b329e98de8 100644 --- a/boards/seeed/wio_terminal/support/openocd.cfg +++ b/boards/seeed/wio_terminal/support/openocd.cfg @@ -8,7 +8,7 @@ set CHIPNAME atsamd51p19 source [find target/atsame5x.cfg] -adapter_khz 500 +adapter speed 500 reset_config srst_only $_TARGETNAME configure -event gdb-attach { diff --git a/boards/seeed/wio_terminal/wio_terminal.yaml b/boards/seeed/wio_terminal/wio_terminal.yaml index e78e041719b..66a97ebefc0 100644 --- a/boards/seeed/wio_terminal/wio_terminal.yaml +++ b/boards/seeed/wio_terminal/wio_terminal.yaml @@ -16,7 +16,6 @@ supported: - i2c - pwm - spi - - usb_cdc - usb_device - watchdog vendor: seeed diff --git a/boards/seeed/xiao_ble/Kconfig b/boards/seeed/xiao_ble/Kconfig deleted file mode 100644 index 0250a94850e..00000000000 --- a/boards/seeed/xiao_ble/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -# XIAO BLE board configuration - -# Copyright (c) 2022 Marcin Niestroj -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_XIAO_BLE - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF52X_HV - default y - -endif # BOARD_XIAO_BLE diff --git a/boards/seeed/xiao_ble/doc/index.rst b/boards/seeed/xiao_ble/doc/index.rst index eda1476149e..c33d786e024 100644 --- a/boards/seeed/xiao_ble/doc/index.rst +++ b/boards/seeed/xiao_ble/doc/index.rst @@ -92,9 +92,9 @@ UF2 Flashing To enter the bootloader, connect the USB port of the XIAO BLE to your host, and double tap the reset botton to the left of the USB connector. A mass storage -device named `XIAO BLE` should appear on the host. Using the command line, or -your file manager copy the `zephyr/zephyr.uf2` file from your build to the base -of the `XIAO BLE` mass storage device. The XIAO BLE will automatically reset +device named ``XIAO BLE`` should appear on the host. Using the command line, or +your file manager copy the :file:`zephyr/zephyr.uf2` file from your build to the base +of the ``XIAO BLE`` mass storage device. The XIAO BLE will automatically reset and launch the newly flashed application. External Debugger @@ -117,7 +117,7 @@ BlackMagic Probe). Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/seeed/xiao_ble/xiao_ble-pinctrl.dtsi b/boards/seeed/xiao_ble/xiao_ble-pinctrl.dtsi index ea8cd0ed513..2931a283e87 100644 --- a/boards/seeed/xiao_ble/xiao_ble-pinctrl.dtsi +++ b/boards/seeed/xiao_ble/xiao_ble-pinctrl.dtsi @@ -132,9 +132,13 @@ , , , - , - ; + ; + low-power-enable; + }; + group2 { + psels = ; low-power-enable; + bias-pull-up; }; }; }; diff --git a/boards/seeed/xiao_ble/xiao_ble.yaml b/boards/seeed/xiao_ble/xiao_ble.yaml index f8dfa743a86..3351b8f609e 100644 --- a/boards/seeed/xiao_ble/xiao_ble.yaml +++ b/boards/seeed/xiao_ble/xiao_ble.yaml @@ -17,7 +17,6 @@ supported: - i2s - pwm - spi - - usb_cdc - usb_device - watchdog - netif:openthread diff --git a/boards/seeed/xiao_ble/xiao_ble_common.dtsi b/boards/seeed/xiao_ble/xiao_ble_common.dtsi index d031ce4b5b3..db00fbf1368 100644 --- a/boards/seeed/xiao_ble/xiao_ble_common.dtsi +++ b/boards/seeed/xiao_ble/xiao_ble_common.dtsi @@ -54,10 +54,17 @@ bootloader-led0 = &led0; mcuboot-led0 = &led0; watchdog0 = &wdt0; - spi-flash0 = &p25q16h; }; }; +®0 { + status = "okay"; +}; + +®1 { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; diff --git a/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense.yaml b/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense.yaml index dfb8bc4e8af..9de9481776a 100644 --- a/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense.yaml +++ b/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense.yaml @@ -17,7 +17,6 @@ supported: - i2s - pwm - spi - - usb_cdc - usb_device - watchdog - netif:openthread diff --git a/boards/seeed/xiao_esp32c3/doc/index.rst b/boards/seeed/xiao_esp32c3/doc/index.rst index dc86a6c20ca..48ce9ddae0d 100644 --- a/boards/seeed/xiao_esp32c3/doc/index.rst +++ b/boards/seeed/xiao_esp32c3/doc/index.rst @@ -94,7 +94,7 @@ MCUboot bootloader ================== User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. +must be built (and flashed) at least once. There are two options to be used when building an application: @@ -105,9 +105,10 @@ There are two options to be used when building an application: User can select the MCUboot bootloader by adding the following line to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y Sysbuild ======== @@ -119,7 +120,7 @@ To build the sample application using sysbuild use the command: .. zephyr-app-commands:: :tool: west - :app: samples/hello_world + :zephyr-app: samples/hello_world :board: xiao_esp32c3 :goals: build :west-args: --sysbuild @@ -155,7 +156,7 @@ Manual build ============ During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. +For that reason, images can be built one at a time using traditional build. The instructions following are relevant for both manual build and sysbuild. The only difference is the structure of the build directory. @@ -171,7 +172,7 @@ For the :code:`Hello, world!` application, follow the instructions below. :board: xiao_esp32c3 :goals: build flash -Since the Zephyr console is by default on the `usb_serial` device, we use +Since the Zephyr console is by default on the ``usb_serial`` device, we use the espressif monitor to view. .. code-block:: console @@ -191,13 +192,13 @@ Debugging As with much custom hardware, the ESP32 modules require patches to OpenOCD that are not upstreamed yet. Espressif maintains their own fork of -the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_. The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the ``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` parameter when building. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -205,7 +206,7 @@ Here is an example for building the :ref:`hello_world` application. :goals: build flash :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/seeed/xiao_esp32c3/support/openocd.cfg b/boards/seeed/xiao_esp32c3/support/openocd.cfg index 02754ff2a73..7421637880c 100644 --- a/boards/seeed/xiao_esp32c3/support/openocd.cfg +++ b/boards/seeed/xiao_esp32c3/support/openocd.cfg @@ -3,4 +3,4 @@ set ESP_RTOS none source [find interface/esp_usb_jtag.cfg] source [find target/esp32c3.cfg] -adapter_khz 5000 +adapter speed 5000 diff --git a/boards/seeed/xiao_esp32c3/xiao_esp32c3.dts b/boards/seeed/xiao_esp32c3/xiao_esp32c3.dts index 38a53f0ad9d..68687958b8a 100644 --- a/boards/seeed/xiao_esp32c3/xiao_esp32c3.dts +++ b/boards/seeed/xiao_esp32c3/xiao_esp32c3.dts @@ -30,10 +30,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - &uart0 { status = "okay"; current-speed = <115200>; diff --git a/boards/seeed/xiao_esp32s3/doc/index.rst b/boards/seeed/xiao_esp32s3/doc/index.rst index bbb1bf528ae..4c029bd5d64 100644 --- a/boards/seeed/xiao_esp32s3/doc/index.rst +++ b/boards/seeed/xiao_esp32s3/doc/index.rst @@ -38,7 +38,6 @@ Current Zephyr's XIAO ESP32S3 board supports the following features: +------------+------------+-------------------------------------+ | Interface | Controller | Driver/Component | +============+============+=====================================+ -+------------+------------+-------------------------------------+ | UART | on-chip | serial port | +------------+------------+-------------------------------------+ | GPIO | on-chip | gpio | @@ -110,7 +109,7 @@ MCUboot bootloader ================== User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. +must be built (and flashed) at least once. There are two options to be used when building an application: @@ -121,9 +120,10 @@ There are two options to be used when building an application: User can select the MCUboot bootloader by adding the following line to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y Sysbuild ======== @@ -135,7 +135,7 @@ To build the sample application using sysbuild use the command: .. zephyr-app-commands:: :tool: west - :app: samples/hello_world + :zephyr-app: samples/hello_world :board: xiao_esp32s3 :goals: build :west-args: --sysbuild @@ -171,7 +171,7 @@ Manual build ============ During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. +For that reason, images can be built one at a time using traditional build. The instructions following are relevant for both manual build and sysbuild. The only difference is the structure of the build directory. @@ -189,7 +189,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``xiao_esp32s3`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -214,33 +214,29 @@ message in the monitor: Debugging ********* -ESP32-S3 support on OpenOCD is available upstream as of version 0.12.0. -Download and install OpenOCD from `OpenOCD`_. +ESP32-S3 support on OpenOCD is available at `OpenOCD ESP32`_. ESP32-S3 has a built-in JTAG circuitry and can be debugged without any additional chip. Only an USB cable connected to the D+/D- pins is necessary. -Further documentation can be obtained from the SoC vendor in `JTAG debugging -for ESP32-S3`_. +Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32-S3`_. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: xiao_esp32s3/esp32/procpu :goals: build flash -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: xiao_esp32s3/esp32/procpu :goals: debug -.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ -.. _`OpenOCD`: https://github.com/openocd-org/openocd References ********** -.. target-notes:: - .. _`Seeed Studio XIAO ESP32S3`: https://wiki.seeedstudio.com/xiao_esp32s3_getting_started/ +.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/seeed/xiao_esp32s3/xiao_esp32s3_appcpu.dts b/boards/seeed/xiao_esp32s3/xiao_esp32s3_appcpu.dts index 672c52a5cba..f2cf95742ac 100644 --- a/boards/seeed/xiao_esp32s3/xiao_esp32s3_appcpu.dts +++ b/boards/seeed/xiao_esp32s3/xiao_esp32s3_appcpu.dts @@ -17,14 +17,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &trng0 { status = "okay"; }; diff --git a/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu.dts b/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu.dts index 831c878d432..2c1349b735c 100644 --- a/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu.dts +++ b/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu.dts @@ -39,14 +39,6 @@ }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &usb_serial { status = "okay"; }; diff --git a/boards/seeed/xiao_rp2040/Kconfig.defconfig b/boards/seeed/xiao_rp2040/Kconfig.defconfig new file mode 100644 index 00000000000..e2af832cdca --- /dev/null +++ b/boards/seeed/xiao_rp2040/Kconfig.defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2023 Seeed Studio inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_XIAO_RP2040 + +config RP2_FLASH_W25Q080 + default y + +if I2C_DW + +config I2C_DW_CLOCK_SPEED + default 125 + +endif # I2C_DW + +config USB_SELF_POWERED + default n + +endif # BOARD_XIAO_RP2040 diff --git a/boards/seeed/xiao_rp2040/Kconfig.xiao_rp2040 b/boards/seeed/xiao_rp2040/Kconfig.xiao_rp2040 new file mode 100644 index 00000000000..8bd3d0d2d15 --- /dev/null +++ b/boards/seeed/xiao_rp2040/Kconfig.xiao_rp2040 @@ -0,0 +1,7 @@ +# XIAO RP2040 board configuration + +# Copyright (c) 2023 Seeed Studio inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_XIAO_RP2040 + select SOC_RP2040 diff --git a/boards/seeed/xiao_rp2040/board.cmake b/boards/seeed/xiao_rp2040/board.cmake new file mode 100644 index 00000000000..4103e36e635 --- /dev/null +++ b/boards/seeed/xiao_rp2040/board.cmake @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(uf2 "--board-id=RPI-RP2") + +include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake) diff --git a/boards/seeed/xiao_rp2040/board.yml b/boards/seeed/xiao_rp2040/board.yml new file mode 100644 index 00000000000..7eaca915972 --- /dev/null +++ b/boards/seeed/xiao_rp2040/board.yml @@ -0,0 +1,5 @@ +board: + name: xiao_rp2040 + vendor: seeed + socs: + - name: rp2040 diff --git a/boards/seeed/xiao_rp2040/doc/img/xiao_rp2040.webp b/boards/seeed/xiao_rp2040/doc/img/xiao_rp2040.webp new file mode 100644 index 00000000000..5233046000a Binary files /dev/null and b/boards/seeed/xiao_rp2040/doc/img/xiao_rp2040.webp differ diff --git a/boards/seeed/xiao_rp2040/doc/img/xiao_rp2040_pinout.webp b/boards/seeed/xiao_rp2040/doc/img/xiao_rp2040_pinout.webp new file mode 100644 index 00000000000..cb295b073d4 Binary files /dev/null and b/boards/seeed/xiao_rp2040/doc/img/xiao_rp2040_pinout.webp differ diff --git a/boards/seeed/xiao_rp2040/doc/index.rst b/boards/seeed/xiao_rp2040/doc/index.rst new file mode 100644 index 00000000000..7206e9be07f --- /dev/null +++ b/boards/seeed/xiao_rp2040/doc/index.rst @@ -0,0 +1,138 @@ +.. _xiao_rp2040: + +XIAO RP2040 +########### + +Overview +******** + +The XIAO RP2040 is an IoT mini development board from Seeed Studio. +It is equipped with an RP2040 SoC, an on-board WS2812 addressable +LED, and USB connector. The USB bootloader allows it +to be flashed without any adapter, in a drag-and-drop manner. + +For more details see the `Seeed Studio XIAO RP2040`_ wiki page. + +.. figure:: img/xiao_rp2040.webp + :align: center + :alt: XIAO RP2040 + + XIAO RP2040 + +Hardware +******** + +The Seeed Studio XIAO RP2040 is a low-power microcontroller that +carries the powerful Dual-core RP2040 processor with a flexible +clock running up to 133 MHz. There is also 264KB of SRAM, and 2MB of +on-board Flash memory. + +There are 14 GPIO PINs on Seeed Studio XIAO RP2040, on which there +are 11 digital pins, 4 analog pins, 11 PWM Pins,1 I2C interface, +1 UART interface, 1 SPI interface, 1 SWD Bonding pad interface. + +Supported Features +================== + +The ``xiao_rp2040`` board target supports the following hardware +features: + +.. list-table:: + :header-rows: 1 + + * - Peripheral + - Kconfig option + - Devicetree compatible + * - NVIC + - N/A + - :dtcompatible:`arm,v6m-nvic` + * - UART + - :kconfig:option:`CONFIG_SERIAL` + - :dtcompatible:`raspberrypi,pico-uart` + * - GPIO + - :kconfig:option:`CONFIG_GPIO` + - :dtcompatible:`raspberrypi,pico-gpio` + * - ADC + - :kconfig:option:`CONFIG_ADC` + - :dtcompatible:`raspberrypi,pico-adc` + * - I2C + - :kconfig:option:`CONFIG_I2C` + - :dtcompatible:`snps,designware-i2c` + * - SPI + - :kconfig:option:`CONFIG_SPI` + - :dtcompatible:`raspberrypi,pico-spi` + * - USB Device + - :kconfig:option:`CONFIG_USB_DEVICE_STACK` + - :dtcompatible:`raspberrypi,pico-usbd` + * - HWINFO + - :kconfig:option:`CONFIG_HWINFO` + - N/A + * - Watchdog Timer (WDT) + - :kconfig:option:`CONFIG_WATCHDOG` + - :dtcompatible:`raspberrypi,pico-watchdog` + * - PWM + - :kconfig:option:`CONFIG_PWM` + - :dtcompatible:`raspberrypi,pico-pwm` + * - Flash + - :kconfig:option:`CONFIG_FLASH` + - :dtcompatible:`raspberrypi,pico-flash-controller` + * - Clock controller + - :kconfig:option:`CONFIG_CLOCK_CONTROL` + - :dtcompatible:`raspberrypi,pico-clock-controller` + * - UART (PIO) + - :kconfig:option:`CONFIG_SERIAL` + - :dtcompatible:`raspberrypi,pico-uart-pio` + +Pin Mapping +=========== + +The peripherals of the RP2040 SoC can be routed to various pins on the board. +The configuration of these routes can be modified through DTS. Please refer to +the datasheet to see the possible routings for each peripheral. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +.. rst-class:: rst-columns + +- UART0_TX : P0 +- UART0_RX : P1 +- I2C1_SDA : P6 +- I2C1_SCL : P7 +- SPI0_RX : P4 +- SPI0_SCK : P2 +- SPI0_TX : P3 + +Connections and IOs +=================== + +The board uses a standard XIAO pinout, the default pin mapping is the following: + +.. figure:: img/xiao_rp2040_pinout.webp + :align: center + :alt: XIAO RP2040 Pinout + + XIAO RP2040 Pinout + +Programming and Debugging +************************* + +Flashing +======== + +Using UF2 +--------- + +You can flash the Xiao RP2040 with a UF2 file. +By default, building an app for this board will generate a +:file:`build/zephyr/zephyr.uf2` file. If the Xiao RP2040 is powered on with +the ``BOOTSEL`` button pressed, it will appear on the host as a mass storage +device. The UF2 file should be copied to the device, which will +flash the Xiao RP2040. + +References +********** + +.. target-notes:: + +.. _`Seeed Studio XIAO RP2040`: https://wiki.seeedstudio.com/XIAO-RP2040/ diff --git a/boards/seeed/xiao_rp2040/seeed_xiao_connector.dtsi b/boards/seeed/xiao_rp2040/seeed_xiao_connector.dtsi new file mode 100644 index 00000000000..d0e9152cefd --- /dev/null +++ b/boards/seeed/xiao_rp2040/seeed_xiao_connector.dtsi @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2023 Seeed Studio inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + xiao_d: connector { + compatible = "seeed,xiao-gpio"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map + = <0 0 &gpio0 26 0> /* D0 */ + , <1 0 &gpio0 27 0> /* D1 */ + , <2 0 &gpio0 28 0> /* D2 */ + , <3 0 &gpio0 29 0> /* D3 */ + , <4 0 &gpio0 6 0> /* D4 */ + , <5 0 &gpio0 7 0> /* D5 */ + , <6 0 &gpio0 0 0> /* D6 */ + , <7 0 &gpio0 1 0> /* D7 */ + , <8 0 &gpio0 2 0> /* D8 */ + , <9 0 &gpio0 4 0> /* D9 */ + , <10 0 &gpio0 3 0> /* D10 */ + ; + }; +}; + +xiao_i2c: &i2c1 { +}; +xiao_spi: &spi0 { +}; +xiao_serial: &uart0 { +}; diff --git a/boards/seeed/xiao_rp2040/xiao_rp2040-pinctrl.dtsi b/boards/seeed/xiao_rp2040/xiao_rp2040-pinctrl.dtsi new file mode 100644 index 00000000000..0e235884bf2 --- /dev/null +++ b/boards/seeed/xiao_rp2040/xiao_rp2040-pinctrl.dtsi @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2021 Yonatan Schachter + * Copyright (c) 2023 Seeed Studio inc. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + + i2c1_default: i2c1_default { + group1 { + pinmux = ; + input-enable; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + + pwm_ch4b_default: pwm_ch4b_default { + group1 { + pinmux = ; + }; + }; + + spi0_default: spi0_default { + group1 { + pinmux = ; + }; + group2 { + pinmux = ; + input-enable; + }; + group3 { + pinmux = ; + }; + }; + + adc_default: adc_default { + group1 { + pinmux = , + , + , + ; + input-enable; + }; + }; + + clocks_default: clocks_default { + }; + + ws2812_pio0_default: ws2812_pio0_default { + ws2812 { + pinmux = ; + }; + }; +}; diff --git a/boards/seeed/xiao_rp2040/xiao_rp2040.dts b/boards/seeed/xiao_rp2040/xiao_rp2040.dts new file mode 100644 index 00000000000..0a52f47d672 --- /dev/null +++ b/boards/seeed/xiao_rp2040/xiao_rp2040.dts @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2021 Yonatan Schachter + * Copyright (c) 2023 Seeed Studio inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "xiao_rp2040-pinctrl.dtsi" +#include "seeed_xiao_connector.dtsi" +#include +#include +#include + +/ { + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,flash-controller = &ssi; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,code-partition = &code_partition; + }; + + aliases { + watchdog0 = &wdt0; + led-strip = &ws2812; + pwm-led0 = &pwm_led0; + led0 = &blue_led; + led1 = &green_led; + led2 = &red_led; + }; + + pwm_leds { + compatible = "pwm-leds"; + status = "disabled"; + pwm_led0: pwm_led_0 { + pwms = <&pwm 9 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + label = "PWM_LED"; + }; + }; + + leds { + compatible = "gpio-leds"; + + blue_led: blue_led { + gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + label = "BLUE_LED"; + }; + + green_led: green_led { + gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; + label = "GREEN_LED"; + }; + + red_led: red_led { + gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + label = "RED_LED"; + }; + }; +}; + +&pwm { + pinctrl-0 = <&pwm_ch4b_default>; + pinctrl-names = "default"; + divider-int-0 = <255>; +}; + +&flash0 { + /* + * 2MB of flash minus the 0x100 used for the second stage bootloader + */ + reg = <0x10000000 DT_SIZE_M(2)>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + code_partition: partition@100 { + label = "code"; + reg = <0x100 (DT_SIZE_M(2) - 0x100)>; + read-only; + }; + }; +}; + +&clocks { + pinctrl-0 = <&clocks_default>; + pinctrl-names = "default"; +}; + +&timer { + status = "okay"; +}; + +&uart0 { + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&i2c1 { + status = "okay"; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; + clock-frequency = ; +}; + +&spi0 { + status = "okay"; + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; + clock-frequency = ; +}; + +&gpio0 { + status = "okay"; + + /* + * The neopixel on this board has its positive side hooked up to a GPIO pin + * rather than a positive voltage rail to save on power. This will enable + * the LED on board initialization. + */ + neopixel-power-enable { + gpio-hog; + gpios = <11 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&wdt0 { + status = "okay"; +}; + +&adc { + status = "okay"; + pinctrl-0 = <&adc_default>; + pinctrl-names = "default"; +}; + +&pio0 { + status = "okay"; + + pio-ws2812 { + compatible = "worldsemi,ws2812-rpi_pico-pio"; + status = "okay"; + pinctrl-0 = <&ws2812_pio0_default>; + pinctrl-names = "default"; + bit-waveform = <3>, <3>, <4>; + + ws2812: ws2812 { + status = "okay"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + chain-length = <1>; + color-mapping = ; + reset-delay = <280>; + frequency = <800000>; + }; + }; +}; + +zephyr_udc0: &usbd { + status = "okay"; +}; + +&vreg { + regulator-always-on; + regulator-allowed-modes = ; +}; diff --git a/boards/seeed/xiao_rp2040/xiao_rp2040.yaml b/boards/seeed/xiao_rp2040/xiao_rp2040.yaml new file mode 100644 index 00000000000..b2852757aa3 --- /dev/null +++ b/boards/seeed/xiao_rp2040/xiao_rp2040.yaml @@ -0,0 +1,24 @@ +identifier: xiao_rp2040 +name: XIAO RP2040 +type: mcu +arch: arm +flash: 2048 +ram: 256 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - uart + - gpio + - adc + - i2c + - spi + - hwinfo + - watchdog + - pwm + - flash + - dma + - counter + - clock +vendor: seeed diff --git a/boards/seeed/xiao_rp2040/xiao_rp2040_defconfig b/boards/seeed/xiao_rp2040/xiao_rp2040_defconfig new file mode 100644 index 00000000000..ef4e863884a --- /dev/null +++ b/boards/seeed/xiao_rp2040/xiao_rp2040_defconfig @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=125000000 +CONFIG_RESET=y + +# Enable UART driver +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable clock control by default +CONFIG_CLOCK_CONTROL=y + +# Code partition needed to target the correct flash range +CONFIG_USE_DT_CODE_PARTITION=y + +# Output UF2 by default, native bootloader supports it. +CONFIG_BUILD_OUTPUT_UF2=y diff --git a/boards/segger/trb_stm32f407/segger_trb_stm32f407_defconfig b/boards/segger/trb_stm32f407/segger_trb_stm32f407_defconfig index 9e96c29aafd..189741d27e8 100644 --- a/boards/segger/trb_stm32f407/segger_trb_stm32f407_defconfig +++ b/boards/segger/trb_stm32f407/segger_trb_stm32f407_defconfig @@ -17,9 +17,3 @@ CONFIG_SERIAL=n # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/sensry/ganymed_bob/Kconfig.ganymed_bob b/boards/sensry/ganymed_bob/Kconfig.ganymed_bob new file mode 100644 index 00000000000..bc5dfc46a84 --- /dev/null +++ b/boards/sensry/ganymed_bob/Kconfig.ganymed_bob @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2024 sensry.io + +config BOARD_GANYMED_BOB + select SOC_SY120_GBM if BOARD_GANYMED_BOB_SY120_GBM + select SOC_SY120_GEN1 if BOARD_GANYMED_BOB_SY120_GEN1 diff --git a/boards/sensry/ganymed_bob/board.yml b/boards/sensry/ganymed_bob/board.yml new file mode 100644 index 00000000000..cc6591f6253 --- /dev/null +++ b/boards/sensry/ganymed_bob/board.yml @@ -0,0 +1,9 @@ +# Copyright (c) 2024 sensry.io +# SPDX-License-Identifier: Apache-2.0 + +board: + name: ganymed_bob + vendor: sensry + socs: + - name: sy120_gbm + - name: sy120_gen1 diff --git a/boards/sensry/ganymed_bob/doc/img/ganymed_bob_sy120_gbm.webp b/boards/sensry/ganymed_bob/doc/img/ganymed_bob_sy120_gbm.webp new file mode 100644 index 00000000000..e6d081f79af Binary files /dev/null and b/boards/sensry/ganymed_bob/doc/img/ganymed_bob_sy120_gbm.webp differ diff --git a/boards/sensry/ganymed_bob/doc/img/ganymed_bob_sy120_gen1.webp b/boards/sensry/ganymed_bob/doc/img/ganymed_bob_sy120_gen1.webp new file mode 100644 index 00000000000..852e9661dd9 Binary files /dev/null and b/boards/sensry/ganymed_bob/doc/img/ganymed_bob_sy120_gen1.webp differ diff --git a/boards/sensry/ganymed_bob/doc/index.rst b/boards/sensry/ganymed_bob/doc/index.rst new file mode 100644 index 00000000000..d8fdbee20ee --- /dev/null +++ b/boards/sensry/ganymed_bob/doc/index.rst @@ -0,0 +1,144 @@ +.. _ganymed_bob: + +Ganymed Break-Out-Board (BOB) +############################# + +Overview +******** + +.. note:: + + All software for the Ganymed Break-Out-Board (BOB) is experimental and hardware availability + is restricted to the participants in the limited sampling program. + +The Ganymed board hardware provides support for the Ganymed sy1xx series IoT multicore +RISC-V SoC with optional sensor level. + +The SoC has the following core features: + +* 32-Bit RSIC-V 1+8-core processor, up to 500MHz + + * 1x Data Acquisition Unit + * 8x Data Processing Unit + * Event Bus + * MicroDMA + +* 4096 KB Global SRAM +* 64 KB Secure SRAM +* 512 KB Global MRAM +* 512 KB Secure MRAM +* CLOCK +* RAM +* :abbr:`32x GPIO (General Purpose Input Output)` +* :abbr:`4x TWIM (I2C-compatible two-wire interface with MicroDMA)` +* 4x I2S +* :abbr:`7x SPI (Serial Peripheral Interface with MicroDMA)` +* :abbr:`3x UART (Universal receiver-transmitter with MicroDMA)` +* :abbr:`1x TSN (Time sensitive networking ethernet MAC with MicroDMA)` +* 1x CAN-FD +* 3x ADC + +.. figure:: img/ganymed_bob_sy120_gbm.webp + :align: center + :alt: Ganymed Break-Out-Board (BOB) equipped with SY120 GBM + + Ganymed Break-Out-Board (BOB) equipped with SY120 GBM (Credit: Sensry) + +.. figure:: img/ganymed_bob_sy120_gen1.webp + :align: center + :alt: Ganymed Break-Out-Board (BOB) equipped with SY120 GEN1 + + Ganymed Break-Out-Board (BOB) equipped with SY120 GEN1 (Credit: Sensry) + +Hardware +******** + +The Ganymed BOB has: + +* Assembly options for the SoC include + + * SY120-GBM - Generic Base Module without top level sensors + * SY120-GEN1 - Generic Module type 1 with top level sensors (Bosch BME680 - SPI1 , Bosch BMA456 - SPI0, Bosch BMG250 - SPI2, STMicro MIS2DH - I2C0) + +* power section for on-board power generation and power measurement (selectable) +* 40-pin JTAG connector (compatible to Olimex ARM-JTAG-OCD-H) +* USB over FTDI (connected to UART0) +* Header for I/Os and additional configuration + +Supported Features +================== + +The ``ganymed-bob/sy120-gbm`` board supports the following hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| SAADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| MRAM | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| TWIM | on-chip | i2c | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| GRTC | on-chip | counter | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| TSN | on-chip | ethernet MAC | ++-----------+------------+----------------------+ +| CAN | on-chip | CAN | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +The ``ganymed-bob/sy120-gen1`` board includes all hardware features of the ``ganymed-bob/sy120-gbm`` board and comes additionally +with these features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| BME680 | on-chip | environment sensor | ++-----------+------------+----------------------+ +| BMA456 | on-chip | acceleration sensor | ++-----------+------------+----------------------+ +| BMG250 | on-chip | gyrosope sensor | ++-----------+------------+----------------------+ +| MIS2DH | on-chip | vibration sensor | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Power +***** + +* USB type-C +* external 5V power source + +Programming and Debugging +************************* + +Applications for the ``ganymed-bob/sy120-gbm`` board can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Testing the Ganymed BreakOut Board +********************************** + +Test the Ganymed with a :zephyr:code-sample:`blinky` sample. +The sample output should be: + +.. code-block:: console + + Hello World! ganymed-bob/sy120-gbm diff --git a/boards/sensry/ganymed_bob/ganymed_bob_sy120_gbm.dts b/boards/sensry/ganymed_bob/ganymed_bob_sy120_gbm.dts new file mode 100644 index 00000000000..f0c4e8c30bf --- /dev/null +++ b/boards/sensry/ganymed_bob/ganymed_bob_sy120_gbm.dts @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 sensry.io */ +/* SPDX-License-Identifier: Apache-2.0 */ + +/dts-v1/; + +#include + +/ { + + chosen { + zephyr,code-partition = &l2_ram_text; + zephyr,sram = &l2_ram_data; + + zephyr,console = &uart0; + }; + +}; diff --git a/boards/sensry/ganymed_bob/ganymed_bob_sy120_gbm.yaml b/boards/sensry/ganymed_bob/ganymed_bob_sy120_gbm.yaml new file mode 100644 index 00000000000..9dd2c6e5d22 --- /dev/null +++ b/boards/sensry/ganymed_bob/ganymed_bob_sy120_gbm.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2024 sensry.io +# SPDX-License-Identifier: Apache-2.0 + +identifier: ganymed_bob/sy120_gbm +vendor: sensry +name: Ganymed family breakout board with SY120_GBM chip equipped +type: mcu +arch: riscv +toolchain: + - zephyr +supported: + - gpio + - uart + - spi + - i2c diff --git a/boards/sensry/ganymed_bob/ganymed_bob_sy120_gbm_defconfig b/boards/sensry/ganymed_bob/ganymed_bob_sy120_gbm_defconfig new file mode 100644 index 00000000000..04f3794d632 --- /dev/null +++ b/boards/sensry/ganymed_bob/ganymed_bob_sy120_gbm_defconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 sensry.io +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/sensry/ganymed_bob/ganymed_bob_sy120_gen1.dts b/boards/sensry/ganymed_bob/ganymed_bob_sy120_gen1.dts new file mode 100644 index 00000000000..f0c4e8c30bf --- /dev/null +++ b/boards/sensry/ganymed_bob/ganymed_bob_sy120_gen1.dts @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 sensry.io */ +/* SPDX-License-Identifier: Apache-2.0 */ + +/dts-v1/; + +#include + +/ { + + chosen { + zephyr,code-partition = &l2_ram_text; + zephyr,sram = &l2_ram_data; + + zephyr,console = &uart0; + }; + +}; diff --git a/boards/sensry/ganymed_bob/ganymed_bob_sy120_gen1.yaml b/boards/sensry/ganymed_bob/ganymed_bob_sy120_gen1.yaml new file mode 100644 index 00000000000..1e45a8c297f --- /dev/null +++ b/boards/sensry/ganymed_bob/ganymed_bob_sy120_gen1.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2024 sensry.io +# SPDX-License-Identifier: Apache-2.0 + +identifier: ganymed_bob/sy120_gen1 +vendor: sensry +name: Ganymed family breakout board with SY120_GBM chip equipped +type: mcu +arch: riscv +toolchain: + - zephyr +supported: + - gpio + - uart + - spi + - i2c diff --git a/boards/sensry/ganymed_bob/ganymed_bob_sy120_gen1_defconfig b/boards/sensry/ganymed_bob/ganymed_bob_sy120_gen1_defconfig new file mode 100644 index 00000000000..04f3794d632 --- /dev/null +++ b/boards/sensry/ganymed_bob/ganymed_bob_sy120_gen1_defconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 sensry.io +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/sensry/index.rst b/boards/sensry/index.rst new file mode 100644 index 00000000000..93151a9da0d --- /dev/null +++ b/boards/sensry/index.rst @@ -0,0 +1,10 @@ +.. _boards-sensry: + +Sensry +###### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/shields/CMakeLists.txt b/boards/shields/CMakeLists.txt new file mode 100644 index 00000000000..b1448739482 --- /dev/null +++ b/boards/shields/CMakeLists.txt @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Shield directories may contain multiple shields. Filter out duplicate +# directories to avoid including the same CMakeLists.txt file multiple times +set(unique_shield_dirs ${SHIELD_DIRS}) +list(REMOVE_DUPLICATES unique_shield_dirs) + +foreach(shield_dir ${unique_shield_dirs}) + # To avoid a lot of empty CMakeLists.txt files we assume it is not an + # error if it is missing + if(EXISTS ${shield_dir}/CMakeLists.txt) + # Out-of-tree shield directories will not be a subdirectory, + # use the filename portion of the shield directory path as a + # relative cmake binary_dir + cmake_path(GET shield_dir FILENAME binary_dir) + add_subdirectory(${shield_dir} ${binary_dir}) + endif() +endforeach() diff --git a/boards/shields/adafruit_2_8_tft_touch_v2/boards/rd_rw612_bga.overlay b/boards/shields/adafruit_2_8_tft_touch_v2/boards/rd_rw612_bga.overlay index 59136c9b45b..8c44347e63f 100644 --- a/boards/shields/adafruit_2_8_tft_touch_v2/boards/rd_rw612_bga.overlay +++ b/boards/shields/adafruit_2_8_tft_touch_v2/boards/rd_rw612_bga.overlay @@ -16,6 +16,7 @@ * directly and does not require the MIPI DBI SPI node */ /delete-node/ mipi_dbi; + /delete-node/ adafruit_2_8_tft_touch_v2_mipi_dbi; }; &lcdic { diff --git a/boards/shields/adafruit_2_8_tft_touch_v2/doc/index.rst b/boards/shields/adafruit_2_8_tft_touch_v2/doc/index.rst index 209b3029389..3d418ac6d90 100644 --- a/boards/shields/adafruit_2_8_tft_touch_v2/doc/index.rst +++ b/boards/shields/adafruit_2_8_tft_touch_v2/doc/index.rst @@ -57,7 +57,7 @@ GPIO interfaces (see :ref:`shields` for more details). Programming *********** -Set ``-DSHIELD=adafruit_2_8_tft_touch_v2`` when you invoke ``west build``. For example: +Set ``--shield adafruit_2_8_tft_touch_v2`` when you invoke ``west build``. For example: .. zephyr-app-commands:: :zephyr-app: samples/subsys/display/lvgl @@ -66,7 +66,7 @@ Set ``-DSHIELD=adafruit_2_8_tft_touch_v2`` when you invoke ``west build``. For e :goals: build If the shield is connected to a board which has Arduino Nano connector, -set ``-DSHIELD=adafruit_2_8_tft_touch_v2_nano`` when you invoke ``west build``. +set ``--shield adafruit_2_8_tft_touch_v2_nano`` when you invoke ``west build``. .. zephyr-app-commands:: :zephyr-app: samples/subsys/display/lvgl diff --git a/boards/shields/adafruit_2_8_tft_touch_v2/dts/adafruit_2_8_tft_touch_v2.dtsi b/boards/shields/adafruit_2_8_tft_touch_v2/dts/adafruit_2_8_tft_touch_v2.dtsi index 9413a7834d9..9a8d5069c37 100644 --- a/boards/shields/adafruit_2_8_tft_touch_v2/dts/adafruit_2_8_tft_touch_v2.dtsi +++ b/boards/shields/adafruit_2_8_tft_touch_v2/dts/adafruit_2_8_tft_touch_v2.dtsi @@ -19,7 +19,7 @@ invert-y; }; - adafruit_2_8_tft_touch_v2_mipi_dbi { + adafruit_2_8_tft_touch_v2_mipi_dbi: adafruit_2_8_tft_touch_v2_mipi_dbi { compatible = "zephyr,mipi-dbi-spi"; spi-dev = <&arduino_spi>; dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */ diff --git a/boards/shields/adafruit_data_logger/adafruit_data_logger.overlay b/boards/shields/adafruit_data_logger/adafruit_data_logger.overlay index 3d63ba6cd89..00d4876736d 100644 --- a/boards/shields/adafruit_data_logger/adafruit_data_logger.overlay +++ b/boards/shields/adafruit_data_logger/adafruit_data_logger.overlay @@ -12,17 +12,17 @@ leds { compatible = "gpio-leds"; /* - * LED1 connection must be manually established using a jumper between - * pins "L1" and "Digital I/O 3". - */ + * LED1 connection must be manually established using a jumper between + * pins "L1" and "Digital I/O 3". + */ green_led_adafruit_data_logger: led_1__adafruit_data_logger { gpios = <&arduino_header 9 GPIO_ACTIVE_HIGH>; /* D3 */ label = "User LED1"; }; /* - * LED2 connection must be manually established using a jumper between - * pins "L2" and "Digital I/O 4". - */ + * LED2 connection must be manually established using a jumper between + * pins "L2" and "Digital I/O 4". + */ red_led_adafruit_data_logger: led_2_adafruit_data_logger { gpios = <&arduino_header 10 GPIO_ACTIVE_HIGH>; /* D4 */ label = "User LED2"; @@ -57,9 +57,9 @@ alarms-count = <1>; battery-switch-over = "standard"; /* - * Interrupt connection must be manually established using a jumper wire between - * pins "SQ" and "Digital I/O 7". - */ + * Interrupt connection must be manually established using a jumper wire between + * pins "SQ" and "Digital I/O 7". + */ int1-gpios = <&arduino_header 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* D7 */ status = "okay"; }; diff --git a/boards/shields/adafruit_data_logger/doc/index.rst b/boards/shields/adafruit_data_logger/doc/index.rst index 833b00fa8d3..c445773142c 100644 --- a/boards/shields/adafruit_data_logger/doc/index.rst +++ b/boards/shields/adafruit_data_logger/doc/index.rst @@ -62,7 +62,7 @@ defines node aliases for SPI and GPIO interfaces (see :ref:`shields` for more de Programming *********** -Set ``-DSHIELD=adafruit_data_logger`` when you invoke ``west build``. For example: +Set ``--shield adafruit_data_logger`` when you invoke ``west build``. For example: .. zephyr-app-commands:: :zephyr-app: tests/drivers/rtc/rtc_api diff --git a/boards/shields/adafruit_neopixel_grid_bff/doc/index.rst b/boards/shields/adafruit_neopixel_grid_bff/doc/index.rst index 24e6762e1d6..8e9db54e190 100644 --- a/boards/shields/adafruit_neopixel_grid_bff/doc/index.rst +++ b/boards/shields/adafruit_neopixel_grid_bff/doc/index.rst @@ -36,10 +36,10 @@ Programming LED Strip Example ================= -Set ``-DSHIELD=adafruit_neopixel_grid_bff`` when you invoke ``west build``. For example: +Set ``--shield adafruit_neopixel_grid_bff`` when you invoke ``west build``. For example: .. zephyr-app-commands:: - :zephyr-app: samples/drivers/led_strip + :zephyr-app: samples/drivers/led/led_strip :board: adafruit_qt_py_rp2040 :shield: adafruit_neopixel_grid_bff :goals: build @@ -57,7 +57,7 @@ LED Display Matrix Example recommended if all of the LEDs are fully on for any significant amount of time. -Set ``-DSHIELD=adafruit_neopixel_grid_bff_display`` when you invoke ``west build``. For example: +Set ``--shield adafruit_neopixel_grid_bff_display`` when you invoke ``west build``. For example: .. zephyr-app-commands:: :zephyr-app: samples/drivers/display diff --git a/boards/shields/adafruit_pca9685/doc/index.rst b/boards/shields/adafruit_pca9685/doc/index.rst index ee6f1649fce..e1d3a43ebf9 100644 --- a/boards/shields/adafruit_pca9685/doc/index.rst +++ b/boards/shields/adafruit_pca9685/doc/index.rst @@ -27,11 +27,11 @@ Pins Assignments Programming *********** -Set ``-DSHIELD=adafruit_pca9685`` when you invoke ``west build``. +Set ``--shield adafruit_pca9685`` when you invoke ``west build``. For example: .. zephyr-app-commands:: - :zephyr-app: samples/drivers/led_pwm + :zephyr-app: samples/drivers/led/pwm :board: nrf52840dk/nrf52840 :shield: adafruit_pca9685 :goals: build diff --git a/boards/shields/adafruit_winc1500/doc/index.rst b/boards/shields/adafruit_winc1500/doc/index.rst index f780ba0a920..1a9f9055213 100644 --- a/boards/shields/adafruit_winc1500/doc/index.rst +++ b/boards/shields/adafruit_winc1500/doc/index.rst @@ -53,7 +53,7 @@ for Arduino connectors and defines node aliases for SPI and GPIO interfaces Programming *********** -Set ``-DSHIELD=adafruit_winc1500`` when you invoke ``west build``. For example: +Set ``--shield adafruit_winc1500`` when you invoke ``west build``. For example: .. zephyr-app-commands:: :zephyr-app: samples/net/wifi diff --git a/boards/shields/amg88xx/doc/index.rst b/boards/shields/amg88xx/doc/index.rst index 36630e296de..166b64dd5e2 100644 --- a/boards/shields/amg88xx/doc/index.rst +++ b/boards/shields/amg88xx/doc/index.rst @@ -145,7 +145,7 @@ The ``samples/sensor/amg88xx`` application demonstrates the basic usage of the Panasonic Grid-EYE sensor. If you want to build the application you have to use the -``-DSHIELD=amg88xx_grid_eye_eval_shield`` shield designation accordingly when +``--shield amg88xx_grid_eye_eval_shield`` shield designation accordingly when you invoke ``west build``. When using the PAN1780 evaluation board the build invocation looks like this: diff --git a/boards/shields/arceli_eth_w5500/doc/index.rst b/boards/shields/arceli_eth_w5500/doc/index.rst index 467559be881..4b1e13e75da 100644 --- a/boards/shields/arceli_eth_w5500/doc/index.rst +++ b/boards/shields/arceli_eth_w5500/doc/index.rst @@ -6,7 +6,7 @@ ARCELI W5500 ETH Overview ******** -ARCELI W5500 etherner is breakout board with SPI bus access over 10 pin header. +ARCELI W5500 Ethernet is breakout board with SPI bus access over 10 pin header. `W5500`_ is 10/100 MBPS stand alone Ethernet controller with on-board MAC & PHY, 16 KiloBytes for FIFO buffer and SPI serial interface. @@ -39,7 +39,7 @@ Arduino header or custom header (by adjusting the overlay). Programming *********** -Set ``-DSHIELD=arceli_eth_w5500`` when you invoke ``west build``. For example: +Set ``--shield arceli_eth_w5500`` when you invoke ``west build``. For example: .. zephyr-app-commands:: :zephyr-app: samples/net/dhcpv4_client @@ -53,4 +53,4 @@ References .. target-notes:: .. _W5500: - https://www.wiznet.io/product-item/w5500/ + https://wiznet.io/products/iethernet-chips/w5500 diff --git a/boards/shields/arduino_uno_click/boards/nrf9160dk_nrf9160.overlay b/boards/shields/arduino_uno_click/boards/nrf9160dk_nrf9160.overlay new file mode 100644 index 00000000000..539c112fd63 --- /dev/null +++ b/boards/shields/arduino_uno_click/boards/nrf9160dk_nrf9160.overlay @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2024 Golioth, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "nrf9160dk_nrf9160_arduino_uno_click_common.dtsi" diff --git a/boards/shields/arduino_uno_click/boards/nrf9160dk_nrf9160_arduino_uno_click_common.dtsi b/boards/shields/arduino_uno_click/boards/nrf9160dk_nrf9160_arduino_uno_click_common.dtsi new file mode 100644 index 00000000000..925a4c41e48 --- /dev/null +++ b/boards/shields/arduino_uno_click/boards/nrf9160dk_nrf9160_arduino_uno_click_common.dtsi @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2024 Golioth, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + /* + * The original Arduino Uno provides the same SCL/SDA on two sets of + * pins, but the nRF9160 DK maps these pins to two different pairs of + * GPIO. When using the Arduino Uno Click Shield board with the nRF9160 + * DK, the P0.18/P0.19 pair must be used. + */ + i2c2_default: i2c2_default { + group1 { + psels = , + ; + }; + }; + + i2c2_sleep: i2c2_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + /* + * The default pin group for the nRF9160 DK includes RTS/CTS HW flow + * control, but the Arduino Uno Click Shield board does not connect + * these pins (only TX/RX are connected on the shield). This keeps RX/TX + * on the same pins, but just removes RTS/CTS from the pin groups. + */ + uart1_default: uart1_default { + group1 { + psels = , + ; + }; + }; + + uart1_sleep: uart1_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; +}; diff --git a/boards/shields/arduino_uno_click/boards/nrf9160dk_nrf9160_ns.overlay b/boards/shields/arduino_uno_click/boards/nrf9160dk_nrf9160_ns.overlay new file mode 100644 index 00000000000..539c112fd63 --- /dev/null +++ b/boards/shields/arduino_uno_click/boards/nrf9160dk_nrf9160_ns.overlay @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2024 Golioth, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "nrf9160dk_nrf9160_arduino_uno_click_common.dtsi" diff --git a/boards/shields/arduino_uno_click/doc/index.rst b/boards/shields/arduino_uno_click/doc/index.rst index 4e260a7db43..6c3ec052bbe 100644 --- a/boards/shields/arduino_uno_click/doc/index.rst +++ b/boards/shields/arduino_uno_click/doc/index.rst @@ -38,7 +38,7 @@ socket is assigned the ``mikrobus_header`` node label. Programming *********** -Include ``-DSHIELD=arduino_uno_click`` when you invoke ``west build`` with +Include ``--shield arduino_uno_click`` when you invoke ``west build`` with other mikroBUS shields. For example: .. zephyr-app-commands:: @@ -46,7 +46,7 @@ other mikroBUS shields. For example: :host-os: unix :board: sam_v71_xult/samv71q21 :gen-args: -DOVERLAY_CONFIG=overlay-802154.conf - :shield: "arduino_uno_click atmel_rf2xx_mikrobus" + :shield: arduino_uno_click,atmel_rf2xx_mikrobus :goals: build References diff --git a/boards/shields/atmel_rf2xx/doc/index.rst b/boards/shields/atmel_rf2xx/doc/index.rst index 31670bf936d..14c389e4701 100644 --- a/boards/shields/atmel_rf2xx/doc/index.rst +++ b/boards/shields/atmel_rf2xx/doc/index.rst @@ -289,7 +289,7 @@ config file. See :zephyr:code-sample:`sockets-echo-server` and Build and Programming ********************* -Set ``-DSHIELD=`` when you invoke ``west build``. +Set ``--shield `` when you invoke ``west build``. .. zephyr-app-commands:: :zephyr-app: samples/net/sockets/echo_server diff --git a/boards/shields/boostxl_ulpsense/doc/index.rst b/boards/shields/boostxl_ulpsense/doc/index.rst index d90717814e4..3521ff47c26 100644 --- a/boards/shields/boostxl_ulpsense/doc/index.rst +++ b/boards/shields/boostxl_ulpsense/doc/index.rst @@ -23,7 +23,7 @@ BoosterPack connectors. Programming *********** -Set ``-DSHIELD=boostxl_ulpsense`` when you invoke ``west build``. For example: +Set ``--shield boostxl_ulpsense`` when you invoke ``west build``. For example: .. zephyr-app-commands:: :zephyr-app: samples/sensor/accel_polling/ diff --git a/boards/shields/buydisplay_2_8_tft_touch_arduino/doc/index.rst b/boards/shields/buydisplay_2_8_tft_touch_arduino/doc/index.rst index ccd4fd1b410..dca664a3585 100644 --- a/boards/shields/buydisplay_2_8_tft_touch_arduino/doc/index.rst +++ b/boards/shields/buydisplay_2_8_tft_touch_arduino/doc/index.rst @@ -56,7 +56,7 @@ for Arduino connectors and defines node aliases for SPI and GPIO interfaces Programming *********** -Set ``-DSHIELD=buydisplay_2_8_tft_touch_arduino`` when you invoke +Set ``--shield buydisplay_2_8_tft_touch_arduino`` when you invoke ``west build``. For example: .. zephyr-app-commands:: diff --git a/boards/shields/buydisplay_3_5_tft_touch_arduino/doc/index.rst b/boards/shields/buydisplay_3_5_tft_touch_arduino/doc/index.rst index bd8a505339f..10c6877f969 100644 --- a/boards/shields/buydisplay_3_5_tft_touch_arduino/doc/index.rst +++ b/boards/shields/buydisplay_3_5_tft_touch_arduino/doc/index.rst @@ -58,7 +58,7 @@ for Arduino connectors and defines node aliases for SPI and GPIO interfaces Programming *********** -Set ``-DSHIELD=buydisplay_3_5_tft_touch_arduino`` when you invoke +Set ``--shield buydisplay_3_5_tft_touch_arduino`` when you invoke ``west build``. For example: .. zephyr-app-commands:: diff --git a/boards/shields/dvp_fpc24_mt9m114/Kconfig.shield b/boards/shields/dvp_fpc24_mt9m114/Kconfig.shield new file mode 100644 index 00000000000..187fbec05cb --- /dev/null +++ b/boards/shields/dvp_fpc24_mt9m114/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_DVP_FPC24_MT9M114 + def_bool $(shields_list_contains,DVP_FPC24_MT9M114) diff --git a/boards/shields/dvp_fpc24_mt9m114/boards/mimxrt1060_evkb.overlay b/boards/shields/dvp_fpc24_mt9m114/boards/mimxrt1060_evkb.overlay new file mode 100644 index 00000000000..a4aa7a27308 --- /dev/null +++ b/boards/shields/dvp_fpc24_mt9m114/boards/mimxrt1060_evkb.overlay @@ -0,0 +1,9 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&dvp_fpc24_interface { + source = <&mt9m114>; +}; diff --git a/boards/shields/dvp_fpc24_mt9m114/boards/mimxrt1064_evk.overlay b/boards/shields/dvp_fpc24_mt9m114/boards/mimxrt1064_evk.overlay new file mode 100644 index 00000000000..a4aa7a27308 --- /dev/null +++ b/boards/shields/dvp_fpc24_mt9m114/boards/mimxrt1064_evk.overlay @@ -0,0 +1,9 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&dvp_fpc24_interface { + source = <&mt9m114>; +}; diff --git a/boards/shields/dvp_fpc24_mt9m114/doc/index.rst b/boards/shields/dvp_fpc24_mt9m114/doc/index.rst new file mode 100644 index 00000000000..0470da7a589 --- /dev/null +++ b/boards/shields/dvp_fpc24_mt9m114/doc/index.rst @@ -0,0 +1,92 @@ +.. _dvp_fpc24_mt9m114: + +DVP FPC-24 MT9M114 Camera Module +################################ + +Overview +******** + +This shield supports mt9m114 camera modules which use a 24-pin FPC connector and a DVP +(Digital Video Port), aka parallel interface. These camera modules are compatible and provided +together with the i.MX RT1050, RT1060 and RT1064 EVKs as specified here `Camera iMXRT`_. + +Pins assignment of the DVP FPC-24 MT9M114 camera module +======================================================= + ++-------------------+--------------+ +| FPC Connector Pin | Function | ++===================+==============+ +| 1 | NC | ++-------------------+--------------+ +| 2 | AGND | ++-------------------+--------------+ +| 3 | SDA | ++-------------------+--------------+ +| 4 | AVDD | ++-------------------+--------------+ +| 5 | SCL | ++-------------------+--------------+ +| 6 | Reset | ++-------------------+--------------+ +| 7 | Vsync | ++-------------------+--------------+ +| 8 | Powerdown | ++-------------------+--------------+ +| 9 | Hsync | ++-------------------+--------------+ +| 10 | DVDD | ++-------------------+--------------+ +| 11 | DOVDD | ++-------------------+--------------+ +| 12 | Data 9 | ++-------------------+--------------+ +| 13 | Master Clock | ++-------------------+--------------+ +| 14 | Data 8 | ++-------------------+--------------+ +| 15 | DGND | ++-------------------+--------------+ +| 16 | Data 7 | ++-------------------+--------------+ +| 17 | Pixel Clock | ++-------------------+--------------+ +| 18 | Data 6 | ++-------------------+--------------+ +| 19 | Data 2 | ++-------------------+--------------+ +| 20 | Data 5 | ++-------------------+--------------+ +| 21 | Data 3 | ++-------------------+--------------+ +| 22 | Data 4 | ++-------------------+--------------+ +| 23 | Data 1 | ++-------------------+--------------+ +| 24 | Data 0 | ++-------------------+--------------+ + + +Requirements +************ + +This shield can only be used with a board which provides a configuration for a 24-pins FPC +connector with DVP (parallel) interface, such as the i.MX RT1050, RT1060, RT1064 EVKs. + +Programming +*********** + +Set ``--shield dvp_fpc24_mt9m114`` when you invoke ``west build``. For example: + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/video/capture + :board: mimxrt1064_evk + :shield: dvp_fpc24_mt9m114 + :goals: build + +References +********** + +.. target-notes:: + +.. _Camera iMXRT: + https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Connecting-camera-and-LCD-to-i-MX-RT-EVKs/ta-p/1122183 diff --git a/boards/shields/dvp_fpc24_mt9m114/dvp_fpc24_mt9m114.overlay b/boards/shields/dvp_fpc24_mt9m114/dvp_fpc24_mt9m114.overlay new file mode 100644 index 00000000000..52988535182 --- /dev/null +++ b/boards/shields/dvp_fpc24_mt9m114/dvp_fpc24_mt9m114.overlay @@ -0,0 +1,34 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/{ + chosen { + zephyr,camera = &dvp_fpc24_interface; + }; +}; + +&dvp_fpc24_i2c { + mt9m114: mt9m114@48 { + compatible = "aptina,mt9m114"; + reg = <0x48>; + + port { + mt9m114_ep_out: endpoint { + remote-endpoint = <&dfi_ep_in>; + }; + }; + }; +}; + +&dvp_fpc24_interface { + status = "okay"; + + port { + dfi_ep_in: endpoint { + remote-endpoint = <&mt9m114_ep_out>; + }; + }; +}; diff --git a/boards/shields/esp_8266/boards/numaker_pfm_m467.overlay b/boards/shields/esp_8266/boards/numaker_pfm_m467.overlay index f28bf527c9a..7ccc7ac4879 100644 --- a/boards/shields/esp_8266/boards/numaker_pfm_m467.overlay +++ b/boards/shields/esp_8266/boards/numaker_pfm_m467.overlay @@ -5,14 +5,14 @@ */ &pinctrl { - uart2_esp8266: uart2_esp8266 { - group0 { - pinmux = , - , - , - ; + uart2_esp8266: uart2_esp8266 { + group0 { + pinmux = , + , + , + ; + }; }; - }; }; &uart2 { @@ -27,7 +27,7 @@ compatible = "espressif,esp-at"; reset-gpios = <&gpioc 4 GPIO_ACTIVE_LOW>; status = "okay"; - }; + }; }; &gpioc { diff --git a/boards/shields/esp_8266/doc/index.rst b/boards/shields/esp_8266/doc/index.rst index 5d3acf6911e..43cb8a39542 100644 --- a/boards/shields/esp_8266/doc/index.rst +++ b/boards/shields/esp_8266/doc/index.rst @@ -110,7 +110,7 @@ configurations should be used based on the board standard headers available. Build and Programming ********************* -Set ``-DSHIELD=`` when you invoke ``west build``. +Set ``--shield `` when you invoke ``west build``. To build shield with specific overlay: diff --git a/boards/shields/frdm_cr20a/doc/index.rst b/boards/shields/frdm_cr20a/doc/index.rst index 99d14af8438..1e24e6ed2c2 100644 --- a/boards/shields/frdm_cr20a/doc/index.rst +++ b/boards/shields/frdm_cr20a/doc/index.rst @@ -52,10 +52,10 @@ For more information about the MCR20A SoC and FRDM-CR20A board: Programming *********** -Set ``-DSHIELD=frdm_cr20a`` when you invoke ``west build``. For example: +Set ``--shield frdm_cr20a`` when you invoke ``west build``. For example: .. zephyr-app-commands:: - :zephyr-app: samples/net/wpanusb + :zephyr-app: samples/net/wpan_serial :board: frdm_k64f :shield: frdm_cr20a :goals: build diff --git a/boards/shields/frdm_kw41z/doc/index.rst b/boards/shields/frdm_kw41z/doc/index.rst index 7314d1944bd..ad9f784bcae 100644 --- a/boards/shields/frdm_kw41z/doc/index.rst +++ b/boards/shields/frdm_kw41z/doc/index.rst @@ -55,7 +55,7 @@ host controller interface (HCI): #. Attach the FRDM-KW41Z to the Arduino header on your selected main board, such as :ref:`mimxrt1050_evk` or :ref:`frdm_k64f`. -#. Set ``-DSHIELD=frdm_kw41z`` when you invoke ``west build`` in +#. Set ``--shield frdm_kw41z`` when you invoke ``west build`` in your Zephyr bluetooth application. For example, .. zephyr-app-commands:: diff --git a/boards/shields/frdm_stbc_agm01/doc/index.rst b/boards/shields/frdm_stbc_agm01/doc/index.rst index d4f983671bb..7879c169061 100644 --- a/boards/shields/frdm_stbc_agm01/doc/index.rst +++ b/boards/shields/frdm_stbc_agm01/doc/index.rst @@ -43,8 +43,8 @@ Pin Assignment of the FRDM-STBC-AGM01 Shield For more information about the FXOS8700, FXAS21002, and FRDM-STBC-AGM01 board: -- :ref:`fxos8700` -- :ref:`fxas21002` +- :zephyr:code-sample:`fxos8700` +- :zephyr:code-sample:`fxas21002` - `FRDM-STBC-AGM01 Website`_ - `FRDM-STBC-AGM01 Quick Reference Card`_ - `FRDM-STBC-AGM01 Schematics`_ @@ -52,7 +52,7 @@ board: Programming *********** -Set ``-DSHIELD=frdm_stbc_agm01`` when you invoke ``west build``. For example: +Set ``--shield frdm_stbc_agm01`` when you invoke ``west build``. For example: .. zephyr-app-commands:: :zephyr-app: samples/sensor/fxas21002 diff --git a/boards/shields/ftdi_vm800c/doc/index.rst b/boards/shields/ftdi_vm800c/doc/index.rst index b1d2ab2d765..241590cca7e 100644 --- a/boards/shields/ftdi_vm800c/doc/index.rst +++ b/boards/shields/ftdi_vm800c/doc/index.rst @@ -75,7 +75,7 @@ See :zephyr:code-sample:`ft800` sample for details. Build and Programming ********************* -Set ``-DSHIELD=`` when you invoke ``west build``. +Set ``--shield `` when you invoke ``west build``. .. zephyr-app-commands:: :zephyr-app: samples/drivers/misc/ft800 diff --git a/boards/shields/g1120b0mipi/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay b/boards/shields/g1120b0mipi/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay new file mode 100644 index 00000000000..e3e6f797cc2 --- /dev/null +++ b/boards/shields/g1120b0mipi/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay @@ -0,0 +1,12 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&rm67162_g1120b0mipi { + /* R414 is not populated on this board, so LPTE signal is not + * connected. remove the property from the display. + */ + /delete-property/ te-gpios; +}; diff --git a/boards/shields/g1120b0mipi/doc/index.rst b/boards/shields/g1120b0mipi/doc/index.rst index d13a4b49edc..8f23e7e43b5 100644 --- a/boards/shields/g1120b0mipi/doc/index.rst +++ b/boards/shields/g1120b0mipi/doc/index.rst @@ -1,7 +1,7 @@ .. _g1120b0mipi: -G1120B0MIPI MIPI Display -########################## +NXP G1120B0MIPI MIPI Display +############################ Overview ******** @@ -50,7 +50,7 @@ for the 40 pin FPC interface Programming *********** -Set ``-DSHIELD=g1120b0mipi`` when you invoke ``west build``. For +Set ``--shield g1120b0mipi`` when you invoke ``west build``. For example: .. zephyr-app-commands:: diff --git a/boards/shields/inventek_eswifi/doc/index.rst b/boards/shields/inventek_eswifi/doc/index.rst index 9b0d9a46e1d..54473467db5 100644 --- a/boards/shields/inventek_eswifi/doc/index.rst +++ b/boards/shields/inventek_eswifi/doc/index.rst @@ -147,7 +147,7 @@ connect and send ping. Build and Programming ********************* -Set ``-DSHIELD=`` when you invoke ``west build``. +Set ``--shield `` when you invoke ``west build``. .. zephyr-app-commands:: :zephyr-app: samples/net/wifi diff --git a/boards/shields/lcd_par_s035/Kconfig.defconfig b/boards/shields/lcd_par_s035/Kconfig.defconfig new file mode 100644 index 00000000000..8e375f8b1a8 --- /dev/null +++ b/boards/shields/lcd_par_s035/Kconfig.defconfig @@ -0,0 +1,31 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SHIELD_LCD_PAR_S035 +if LVGL + +# Enable double buffering +config LV_Z_DOUBLE_VDB + default y + +config LV_Z_BITS_PER_PIXEL + default 16 + +choice LV_COLOR_DEPTH + default LV_COLOR_DEPTH_16 +endchoice + +# VDB size is 10% of the full screen size +config LV_Z_VDB_SIZE + default 10 + +# Configure LVGL to use touchscreen +config INPUT + default y + +config INPUT_GT911_INTERRUPT + default y + +endif # LVGL + +endif # SHIELD_LCD_PAR_S035 diff --git a/boards/shields/lcd_par_s035/Kconfig.shield b/boards/shields/lcd_par_s035/Kconfig.shield new file mode 100644 index 00000000000..4dba938831b --- /dev/null +++ b/boards/shields/lcd_par_s035/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_LCD_PAR_S035 + def_bool $(shields_list_contains,lcd_par_s035_8080) diff --git a/boards/shields/lcd_par_s035/doc/index.rst b/boards/shields/lcd_par_s035/doc/index.rst new file mode 100644 index 00000000000..6e29a798b5d --- /dev/null +++ b/boards/shields/lcd_par_s035/doc/index.rst @@ -0,0 +1,40 @@ +.. _lcd_par_s035: + +NXP LCD_PAR_S035 TFT LCD Module +############################### + +Overview +******** + +The LCD-PAR-S035 is a 3.5” 480x320 IPS TFT LCD module with wide viewing angle +and 5-point capacitive touch functionality. The LCD module can be controlled +through either SPI or parallel (8/16bit) 8080/6800. +More information about the shield can be found +at the `LCD-PAR-S035 product page`_. + +Requirements +************ + +This shield can only be used with FRDM-X evaluation kits with a parallel LCD +connector or a PMOD connector. Currently only the parallel LCD connector is +enabled. + +Programming +*********** + +Set ``--shield lcd_par_s035_8080`` when you invoke ``west build``. For +example: + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/display + :board: frdm_mcxn947/mcxn947/cpu0 + :shield: lcd_par_s035_8080 + :goals: build + +References +********** + +.. target-notes:: + +.. _LCD-PAR-S035 product page: + https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/3-5-480x320-ips-tft-lcd-module:LCD-PAR-S035 diff --git a/boards/shields/lcd_par_s035/lcd_par_s035_8080.overlay b/boards/shields/lcd_par_s035/lcd_par_s035_8080.overlay new file mode 100644 index 00000000000..9306610bc1f --- /dev/null +++ b/boards/shields/lcd_par_s035/lcd_par_s035_8080.overlay @@ -0,0 +1,58 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/{ + chosen { + zephyr,display = &st7796s; + }; + + lvgl_pointer { + compatible = "zephyr,lvgl-pointer-input"; + input = <>911_lcd_par_s035>; + swap-xy; + invert-y; + }; +}; + +&nxp_8080_touch_panel_i2c { + status = "okay"; + gt911_lcd_par_s035: gt911-lcd_par_s035@5d { + compatible = "goodix,gt911"; + reg = <0x5d>; + alt-addr = <0x14>; + irq-gpios = <&nxp_lcd_8080_connector 9 GPIO_ACTIVE_HIGH>; + }; +}; + +&nxp_flexio_lcd { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + st7796s: st7796s@0 { + compatible = "sitronix,st7796s"; + reg = <0>; + /* Baud rate on each pin is 1MHz */ + mipi-max-frequency = <10000000>; + mipi-mode = ; + height = <320>; + width = <480>; + invert-mode = "1-dot"; + frmctl1 = [80 10]; + bpc = [1F 50 00 20]; + dfc = [8A 07 3B]; + pwr1 = [80 64]; + pwr2 = <0x13>; + pwr3 = <0xA7>; + vcmpctl = <0x09>; + doca = [40 8A 00 00 29 19 A5 33]; + pgc = [F0 06 0B 07 06 05 2E 33 47 3A 17 16 2E 31]; + ngc = [F0 09 0D 09 08 23 2E 33 46 38 13 13 2C 32]; + madctl = <0x28>; + color-invert; + }; +}; diff --git a/boards/shields/link_board_eth/doc/index.rst b/boards/shields/link_board_eth/doc/index.rst index 51a68bf022c..9fac7b526d8 100644 --- a/boards/shields/link_board_eth/doc/index.rst +++ b/boards/shields/link_board_eth/doc/index.rst @@ -102,7 +102,7 @@ For more information about the link board ETH and ENC424J600: Programming *********** -Set ``-DSHIELD=link_board_eth`` when you invoke ``west build`` or ``cmake`` in your +Set ``--shield link_board_eth`` when you invoke ``west build`` or ``cmake`` in your Zephyr application. For example: .. zephyr-app-commands:: diff --git a/boards/shields/lmp90100_evb/doc/index.rst b/boards/shields/lmp90100_evb/doc/index.rst index f3a1ff36ed3..f93b0e550ef 100644 --- a/boards/shields/lmp90100_evb/doc/index.rst +++ b/boards/shields/lmp90100_evb/doc/index.rst @@ -41,7 +41,7 @@ Zephyr RTOS includes one sample targeting the LMP90100 EVB: Programming *********** -Set ``-DSHIELD=lmp90100_evb`` when you invoke ``west build``. For example: +Set ``--shield lmp90100_evb`` when you invoke ``west build``. For example: .. zephyr-app-commands:: :zephyr-app: samples/shields/lmp90100_evb/rtd @@ -50,7 +50,7 @@ Set ``-DSHIELD=lmp90100_evb`` when you invoke ``west build``. For example: :goals: build .. _LMP90100 Sensor AFE Evaluation Board User's Guide: - http://www.ti.com/lit/pdf/snau028 + https://www.farnell.com/datasheets/1604987.pdf .. _LMP90100 Multi-Channel, Low Power 24-Bit Sensor AFE: http://www.ti.com/product/LMP90100 diff --git a/boards/shields/lmp90100_evb/lmp90100_evb.overlay b/boards/shields/lmp90100_evb/lmp90100_evb.overlay index 7271c9c7c3d..e30840dd10b 100644 --- a/boards/shields/lmp90100_evb/lmp90100_evb.overlay +++ b/boards/shields/lmp90100_evb/lmp90100_evb.overlay @@ -32,7 +32,7 @@ status = "okay"; eeprom0_lmp90100_evb: eeprom@57 { - compatible = "atmel,at24"; + compatible = "atmel,at24c02", "atmel,at24"; reg = <0x57>; size = <256>; pagesize = <8>; diff --git a/boards/shields/ls0xx_generic/doc/index.rst b/boards/shields/ls0xx_generic/doc/index.rst index 415dbb0227c..665aaa07180 100644 --- a/boards/shields/ls0xx_generic/doc/index.rst +++ b/boards/shields/ls0xx_generic/doc/index.rst @@ -88,7 +88,7 @@ for Arduino connectors and defines node aliases for SPI and GPIO interfaces Programming *********** -Set ``-DSHIELD=ls013b7dh03`` when you invoke ``west build``. For example: +Set ``--shield ls013b7dh03`` when you invoke ``west build``. For example: .. zephyr-app-commands:: :zephyr-app: samples/subsys/display/lvgl diff --git a/boards/shields/m5stack_core2_ext/doc/index.rst b/boards/shields/m5stack_core2_ext/doc/index.rst index 9fdcf5bd0a0..c5a91c9838f 100644 --- a/boards/shields/m5stack_core2_ext/doc/index.rst +++ b/boards/shields/m5stack_core2_ext/doc/index.rst @@ -38,7 +38,7 @@ Pins Assignments Programming *********** -Set ``-DSHIELD=m5stack_core2_ext`` when you invoke ``west build``. +Set ``--shield m5stack_core2_ext`` when you invoke ``west build``. For example: .. zephyr-app-commands:: diff --git a/boards/shields/max3421e/doc/index.rst b/boards/shields/max3421e/doc/index.rst index 3ff216365c2..86eff193778 100644 --- a/boards/shields/max3421e/doc/index.rst +++ b/boards/shields/max3421e/doc/index.rst @@ -54,5 +54,5 @@ Pins Assignment of the Shield Connector Programming *********** -Set ``-DSHIELD=sparkfun_max3421e`` when you invoke ``west build`` or ``cmake`` +Set ``--shield sparkfun_max3421e`` when you invoke ``west build`` or ``cmake`` in your Zephyr application. diff --git a/boards/shields/max7219/doc/index.rst b/boards/shields/max7219/doc/index.rst index 8cc10554503..46175ce487e 100644 --- a/boards/shields/max7219/doc/index.rst +++ b/boards/shields/max7219/doc/index.rst @@ -31,7 +31,7 @@ for Arduino connectors and defines a node alias for the SPI interface Programming *********** -Set ``-DSHIELD=max7219_8x8`` when you invoke ``west build``. For example: +Set ``--shield max7219_8x8`` when you invoke ``west build``. For example: .. zephyr-app-commands:: :zephyr-app: samples/drivers/display/ diff --git a/boards/shields/mcp2515/doc/index.rst b/boards/shields/mcp2515/doc/index.rst index c989f05368a..3ea59df4686 100644 --- a/boards/shields/mcp2515/doc/index.rst +++ b/boards/shields/mcp2515/doc/index.rst @@ -339,8 +339,8 @@ For more information about the Adafruit PiCowbell CAN Bus shield: Programming *********** -Set ``-DSHIELD=dfrobot_can_bus_v2_0`` or ``-DSHIELD=keyestudio_can_bus_ks0411`` -or ``-DSHIELD=adafruit_can_picowbell`` when you invoke ``west build`` or ``cmake`` in your Zephyr application. For +Set ``--shield dfrobot_can_bus_v2_0`` or ``--shield keyestudio_can_bus_ks0411`` +or ``--shield adafruit_can_picowbell`` when you invoke ``west build`` or ``cmake`` in your Zephyr application. For example: .. zephyr-app-commands:: diff --git a/boards/shields/mikroe_accel13_click/doc/index.rst b/boards/shields/mikroe_accel13_click/doc/index.rst index 24d6a69443a..4290dfa2138 100644 --- a/boards/shields/mikroe_accel13_click/doc/index.rst +++ b/boards/shields/mikroe_accel13_click/doc/index.rst @@ -34,11 +34,11 @@ see the following documentation: Programming *********** -Set ``-DSHIELD=mikro_accel13_click`` when you invoke ``west build``. For +Set ``--shield mikro_accel13_click`` when you invoke ``west build``. For example: .. zephyr-app-commands:: - :zephyr-app: test/boards/board_shell + :zephyr-app: samples/sensor/sensor_shell :board: lpcxpresso55s69 :shield: mikroe_accel13_click :goals: build diff --git a/boards/shields/mikroe_adc_click/doc/index.rst b/boards/shields/mikroe_adc_click/doc/index.rst index 8157863d7d4..c75d322a334 100644 --- a/boards/shields/mikroe_adc_click/doc/index.rst +++ b/boards/shields/mikroe_adc_click/doc/index.rst @@ -31,11 +31,11 @@ see the following documentation: Programming *********** -Set ``-DSHIELD=mikro_adc_click`` when you invoke ``west build``. For +Set ``--shield mikro_adc_click`` when you invoke ``west build``. For example: .. zephyr-app-commands:: - :zephyr-app: + :app: :board: lpcxpresso55s16 :shield: mikroe_adc_click :goals: build diff --git a/boards/shields/mikroe_ble_tiny_click/Kconfig.defconfig b/boards/shields/mikroe_ble_tiny_click/Kconfig.defconfig new file mode 100644 index 00000000000..db63d94f3c5 --- /dev/null +++ b/boards/shields/mikroe_ble_tiny_click/Kconfig.defconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Ian Morris +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BT_HCI=y +CONFIG_BT_HCI_ACL_FLOW_CONTROL=n +CONFIG_BT_CTLR=n diff --git a/boards/shields/mikroe_ble_tiny_click/Kconfig.shield b/boards/shields/mikroe_ble_tiny_click/Kconfig.shield new file mode 100644 index 00000000000..c560f6dc95e --- /dev/null +++ b/boards/shields/mikroe_ble_tiny_click/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Ian Morris +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_MIKROE_BLE_TINY_CLICK + def_bool $(shields_list_contains,mikroe_ble_tiny_click) diff --git a/boards/shields/mikroe_ble_tiny_click/doc/ble-tiny-click.webp b/boards/shields/mikroe_ble_tiny_click/doc/ble-tiny-click.webp new file mode 100644 index 00000000000..f18b1d6adcc Binary files /dev/null and b/boards/shields/mikroe_ble_tiny_click/doc/ble-tiny-click.webp differ diff --git a/boards/shields/mikroe_ble_tiny_click/doc/da14531-hci-binary.webp b/boards/shields/mikroe_ble_tiny_click/doc/da14531-hci-binary.webp new file mode 100644 index 00000000000..abac88b1bea Binary files /dev/null and b/boards/shields/mikroe_ble_tiny_click/doc/da14531-hci-binary.webp differ diff --git a/boards/shields/mikroe_ble_tiny_click/doc/index.rst b/boards/shields/mikroe_ble_tiny_click/doc/index.rst new file mode 100644 index 00000000000..ffa721f2450 --- /dev/null +++ b/boards/shields/mikroe_ble_tiny_click/doc/index.rst @@ -0,0 +1,91 @@ +.. _mikroe_ble_tiny_click_shield: + +MikroElektronika BLE TINY Click +############################### + +Overview +******** + +The MikroElektronika BLE TINY Click carries the Renesas `DA14531MOD`_ Bluetooth +LE module in a `mikroBUS`_ |trade| form factor. + +.. figure:: ble-tiny-click.webp + :align: center + :alt: MikroElektronika BLE TINY Click + + MikroElektronika BLE TINY Click (Credit: MikroElektronika) + +Requirements +************ + +This shield can only be used with a board that provides a mikroBUS |trade| +socket and defines the ``mikrobus_serial`` node label (see :ref:`shields` +for more details). + +.. note:: + + The reset input on the DA14531 Module is active high and is connected to + the RST pin on the mikroBUS socket. On many host boards this RST pin is + connected to a system reset signal that is active low. This results in the + host system unintentionally holding the DA14531 Module in reset. This issue + can be overcome by removing resistor R3 on the BLE TINY Click board, see + the `BLE TINY Click Schematic`_ for further details. + +The DA14531 Module contained on the shield must be programmed with a binary +file that supports the HCI interface over UART, without hardware flow control +as these signals are not supported on the Click footprint. + +The `Renesas SmartBond Flash Programmer`_ tool can be used to download a +suitable binary and then program it into the DA14531 via the SWD header +present on the Click board. Once the tool has been installed, open it and +press the "Search Online" button. The required binary file can be selected +for download as follows: + +.. figure:: da14531-hci-binary.webp + :align: center + :alt: DA14531 HCI Binary File Selection + + Selecting the DA14531 HCI Binary File for Download + +Press the "Program" button to program the binary file into the DA14531 Module. + +For more information about interfacing to the DA14531 and the BLE TINY Click, +see the following documentation: + +- `DA14531MOD Datasheet`_ +- `BLE TINY Click`_ + +Programming +*********** + +Set ``--shield mikroe_ble_tiny_click`` when you invoke ``west build``. For +example: + +.. zephyr-app-commands:: + :zephyr-app: samples/bluetooth/beacon + :board: ek-ra8m1 + :shield: mikroe_ble_tiny_click + :goals: build + +References +********** + +.. target-notes:: + +.. _DA14531MOD: + https://www.renesas.com/us/en/products/wireless-connectivity/bluetooth-low-energy/da14531mod-smartbond-tiny-bluetooth-low-energy-module + +.. _mikroBUS: + https://www.mikroe.com/mikrobus + +.. _DA14531MOD Datasheet: + https://www.renesas.com/us/en/document/dst/da14531-module-datasheet?r=1601921 + +.. _BLE TINY Click: + https://www.mikroe.com/ble-tiny-click + +.. _BLE TINY Click Schematic: + https://download.mikroe.com/documents/add-on-boards/click/ble_tiny_click/BLE_TINY_click_v102_Schematic.pdf + +.. _Renesas SmartBond Flash Programmer: + https://www.renesas.com/us/en/software-tool/smartbond-flash-programmer diff --git a/boards/shields/mikroe_ble_tiny_click/mikroe_ble_tiny_click.overlay b/boards/shields/mikroe_ble_tiny_click/mikroe_ble_tiny_click.overlay new file mode 100644 index 00000000000..6f3e7b53f42 --- /dev/null +++ b/boards/shields/mikroe_ble_tiny_click/mikroe_ble_tiny_click.overlay @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2024 Ian Morris + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,bt-hci = &bt_hci_uart; + }; +}; + +&mikrobus_serial { + status = "okay"; + + bt_hci_uart: bt_hci_uart { + compatible = "zephyr,bt-hci-uart"; + }; +}; diff --git a/boards/shields/mikroe_eth_click/doc/index.rst b/boards/shields/mikroe_eth_click/doc/index.rst index 3344765fa6d..328eac5d028 100644 --- a/boards/shields/mikroe_eth_click/doc/index.rst +++ b/boards/shields/mikroe_eth_click/doc/index.rst @@ -41,7 +41,7 @@ for Mikro-BUS connectors and defines node aliases for SPI and GPIO interfaces Programming *********** -Set ``-DSHIELD=mikroe_eth_click`` when you invoke ``west build``. For example: +Set ``--shield mikroe_eth_click`` when you invoke ``west build``. For example: .. zephyr-app-commands:: :zephyr-app: samples/net/dhcpv4_client diff --git a/boards/shields/mikroe_mcp2518fd_click/doc/index.rst b/boards/shields/mikroe_mcp2518fd_click/doc/index.rst index 79ac2b441c3..e54bf7509c7 100644 --- a/boards/shields/mikroe_mcp2518fd_click/doc/index.rst +++ b/boards/shields/mikroe_mcp2518fd_click/doc/index.rst @@ -16,14 +16,14 @@ Requirements ************ The shield uses a mikroBUS interface. The target board must define -a `mikrobus_spi` and `mikrobus_header` node labels +a ``mikrobus_spi`` and ``mikrobus_header`` node labels (see :ref:`shields` for more details). The target board must also support level triggered interrupts. Programming *********** -Set ``-DSHIELD=mikroe_mcp2518fd_click`` when you invoke ``west build``, +Set ``--shield mikroe_mcp2518fd_click`` when you invoke ``west build``, for example: .. zephyr-app-commands:: diff --git a/boards/shields/mikroe_weather_click/doc/index.rst b/boards/shields/mikroe_weather_click/doc/index.rst index a11f55e6027..3042ff87521 100644 --- a/boards/shields/mikroe_weather_click/doc/index.rst +++ b/boards/shields/mikroe_weather_click/doc/index.rst @@ -1,4 +1,4 @@ -.. _mikroe_weather_click_shield: +.. _mikroe_weather_click: MikroElektronika Weather Click ############################## @@ -34,7 +34,7 @@ documentation: Programming *********** -Set ``-DSHIELD=mikroe_weather_click`` when you invoke ``west build``. For +Set ``--shield mikroe_weather_click`` when you invoke ``west build``. For example: .. zephyr-app-commands:: diff --git a/boards/shields/mikroe_wifi_bt_click/doc/index.rst b/boards/shields/mikroe_wifi_bt_click/doc/index.rst index 07ba1ce29b3..550590c87f6 100644 --- a/boards/shields/mikroe_wifi_bt_click/doc/index.rst +++ b/boards/shields/mikroe_wifi_bt_click/doc/index.rst @@ -89,7 +89,7 @@ initial log and last message should be the version of the AT firmware flashed. Build and Programming ********************* -Set ``-DSHIELD=`` when you invoke ``west build``. +Set ``--shield `` when you invoke ``west build``. See the example below for lpcxpresso55s69 board using Mikrobus serial: diff --git a/boards/shields/npm1100_ek/doc/index.rst b/boards/shields/npm1100_ek/doc/index.rst index a05b38f346f..e0df0cf301f 100644 --- a/boards/shields/npm1100_ek/doc/index.rst +++ b/boards/shields/npm1100_ek/doc/index.rst @@ -33,8 +33,8 @@ supports the Arduino connector. The connections are: Usage ***** -The shield can be used in any application by setting ``SHIELD`` to -``npm1100_ek``. +The shield can be used in any application by setting ``--shield npm1100_ek`` +when invoking ``west build``. References ********** diff --git a/boards/shields/npm1300_ek/doc/index.rst b/boards/shields/npm1300_ek/doc/index.rst index 44ca20fc820..f46a8cf47a0 100644 --- a/boards/shields/npm1300_ek/doc/index.rst +++ b/boards/shields/npm1300_ek/doc/index.rst @@ -21,9 +21,9 @@ supports the Arduino connector. Usage ***** -The shield can be used in any application by setting ``SHIELD`` to -``npm1300_ek``. You can check :ref:`npm1300_ek_sample` for a comprehensive -sample. +The shield can be used in any application by setting ``--shield npm1300_ek`` +when invoking ``west build``. You can check :ref:`npm1300_ek_sample` for a +comprehensive sample. References ********** diff --git a/boards/shields/npm6001_ek/doc/index.rst b/boards/shields/npm6001_ek/doc/index.rst index 18e41e74cf3..bc982d7f436 100644 --- a/boards/shields/npm6001_ek/doc/index.rst +++ b/boards/shields/npm6001_ek/doc/index.rst @@ -27,9 +27,9 @@ supports the Arduino connector. Usage ***** -The shield can be used in any application by setting ``SHIELD`` to -``npm6001_ek``. You can check :ref:`npm6001_ek_sample` for a comprehensive -sample. +The shield can be used in any application by setting ``--shield npm6001_ek`` +when invoking ``west build``. You can check :ref:`npm6001_ek_sample` for a +comprehensive sample. References ********** diff --git a/boards/shields/nrf7002eb/Kconfig.shield b/boards/shields/nrf7002eb/Kconfig.shield new file mode 100644 index 00000000000..e369cfe3de4 --- /dev/null +++ b/boards/shields/nrf7002eb/Kconfig.shield @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_NRF7002EB + def_bool $(shields_list_contains,nrf7002eb) + +config SHIELD_NRF7002EB_COEX + def_bool $(shields_list_contains,nrf7002eb_coex) diff --git a/boards/shields/nrf7002eb/boards/thingy53_nrf5340_cpuapp.overlay b/boards/shields/nrf7002eb/boards/thingy53_nrf5340_cpuapp.overlay new file mode 100644 index 00000000000..ee052ec68ae --- /dev/null +++ b/boards/shields/nrf7002eb/boards/thingy53_nrf5340_cpuapp.overlay @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * This uses gpio0 pin 8 which conflicts with STATUS pin of Wi-Fi SR coex + */ +&npm1100_force_pwm_mode { + status = "disabled"; +}; + +/* + * Pins P0.9, P0.10, P0.11, P0.12 conflict with SPI4 and nrf7002 host irq + */ +&uart0 { + status = "disabled"; +}; diff --git a/boards/shields/nrf7002eb/doc/index.rst b/boards/shields/nrf7002eb/doc/index.rst new file mode 100644 index 00000000000..e93c778f87c --- /dev/null +++ b/boards/shields/nrf7002eb/doc/index.rst @@ -0,0 +1,72 @@ +.. _nrf7002eb: + +nRF7002 EB +########## + +Overview +******** + +The nRF7002 EB is a versatile evaluation kit in the form of a thumbstick shield which connects to +compatible Nordic host boards, like the Thingy53, using the Nordic edge-connector. + +The nRF7002 EB unlocks low-power Wi-Fi 6 capabilities for your host device. It support dual-band Wi-Fi +2.4GHz and 5GHz, and is based on the nRF7002 SoC. +Seamlessly connect to Wi-Fi networks and leverage Wi-Fi-based locationing, enabling advanced +features such as SSID sniffing of local Wi-Fi hubs + +.. figure:: nrf7002eb.jpg + :alt: nRF7002 EB + :align: center + + nRF7002 EB + +Requirements +************ + +The nRF7002 EB board is designed to fit straight into a Nordic edge-connector and uses SPI as the +communication interface. Any host board that supports the Nordic edge-connector can be used with +the nRF7002 EB. + +Prerequisites +------------- + +the nRF70 driver requires firmware binary blobs for Wi-Fi operation. Run the command +below to retrieve those files. + +.. code-block:: console + + west update + west blobs fetch hal_nordic + +Usage +***** + +The shield can be used in any application by setting ``--shield nrf7002eb`` when invoking ``west build``. + +Shield Variants +############### + +The nRF7002 EK has a variant which includes the COEX pins. These pins are not be routed to the +edge-connector on some boards, like earlier revisions of the Thingy53 than v1.0.0. + +- ``nrf7002ek``: The default variant. +- ``nrf7002ek_coex``: Variant which includes the COEX pins. + +SR Co-existence +############### + +The nRF7002 EK supports SR co-existence provided the host board supports it. The SR co-existence +pins are connected to the host board's GPIO pins. + +Two Kconfig options are available to enable SR co-existence: + +- :kconfig:option:`CONFIG_NRF70_SR_COEX`: Enables SR co-existence. +- :kconfig:option:`CONFIG_NRF70_SR_COEX_RF_SWITCH`: Control SR side RF switch. + +References +********** + +- `Developing with nRF7002 EB `_ +- `nRF7002 EB product specification `_ +- `nRF7002 product specification `_ +- `nRF7002 Co-existence `_ diff --git a/boards/shields/nrf7002eb/doc/nrf7002eb.jpg b/boards/shields/nrf7002eb/doc/nrf7002eb.jpg new file mode 100644 index 00000000000..a8afd674135 Binary files /dev/null and b/boards/shields/nrf7002eb/doc/nrf7002eb.jpg differ diff --git a/boards/shields/nrf7002eb/nrf7002eb.overlay b/boards/shields/nrf7002eb/nrf7002eb.overlay new file mode 100644 index 00000000000..d580a2efb8c --- /dev/null +++ b/boards/shields/nrf7002eb/nrf7002eb.overlay @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + chosen { + zephyr,wifi = &wlan0; + }; +}; + +&edge_connector_spi { + status = "okay"; + + nrf70: nrf7002@0 { + compatible = "nordic,nrf7002-spi"; + status = "okay"; + reg = <0>; + spi-max-frequency = ; + + bucken-gpios = <&edge_connector 9 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; + iovdd-ctrl-gpios = <&edge_connector 9 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; + host-irq-gpios = <&edge_connector 19 GPIO_ACTIVE_HIGH>; + + wlan0: wlan0 { + compatible = "nordic,wlan"; + }; + + wifi-max-tx-pwr-2g-dsss = <21>; + wifi-max-tx-pwr-2g-mcs0 = <16>; + wifi-max-tx-pwr-2g-mcs7 = <16>; + wifi-max-tx-pwr-5g-low-mcs0 = <13>; + wifi-max-tx-pwr-5g-low-mcs7 = <13>; + wifi-max-tx-pwr-5g-mid-mcs0 = <13>; + wifi-max-tx-pwr-5g-mid-mcs7 = <13>; + wifi-max-tx-pwr-5g-high-mcs0 = <12>; + wifi-max-tx-pwr-5g-high-mcs7 = <12>; + }; +}; diff --git a/boards/shields/nrf7002eb/nrf7002eb_coex.overlay b/boards/shields/nrf7002eb/nrf7002eb_coex.overlay new file mode 100644 index 00000000000..a8925c25567 --- /dev/null +++ b/boards/shields/nrf7002eb/nrf7002eb_coex.overlay @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "nrf7002eb.overlay" + +&nrf70 { + status0-gpios = <&edge_connector 5 GPIO_ACTIVE_HIGH>; + req-gpios = <&edge_connector 6 GPIO_ACTIVE_HIGH>; + grant-gpios = <&edge_connector 15 (GPIO_PULL_DOWN | GPIO_ACTIVE_LOW)>; +}; diff --git a/boards/shields/nrf7002ek/Kconfig.shield b/boards/shields/nrf7002ek/Kconfig.shield new file mode 100644 index 00000000000..7627ff96dbd --- /dev/null +++ b/boards/shields/nrf7002ek/Kconfig.shield @@ -0,0 +1,11 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_NRF7002EK + def_bool $(shields_list_contains,nrf7002ek) + +config SHIELD_NRF7002EK_NRF7001 + def_bool $(shields_list_contains,nrf7002ek_nrf7001) + +config SHIELD_NRF7002EK_NRF7000 + def_bool $(shields_list_contains,nrf7002ek_nrf7000) diff --git a/boards/shields/nrf7002ek/boards/nrf5340dk_nrf5340_cpuapp.overlay b/boards/shields/nrf7002ek/boards/nrf5340dk_nrf5340_cpuapp.overlay new file mode 100644 index 00000000000..ada3a5c61d2 --- /dev/null +++ b/boards/shields/nrf7002ek/boards/nrf5340dk_nrf5340_cpuapp.overlay @@ -0,0 +1,15 @@ +/* Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* This node by default forwards the UART1 pins to CPUNET, but as UART1 uses + * same pins as bucken and iovdd-ctrl, we need these pins to be controlled by + * the CPUAPP. Since a child node of gpio_fwd cannot be disabled, hence + * the entire node is disabled. If the application needs to forward other pins + * to the CPUNET, it should create a separate instance of nrf-gpio-forwarder + * and use it instead. + */ +&gpio_fwd { + status = "disabled"; +}; diff --git a/boards/shields/nrf7002ek/boards/nrf9151dk_nrf9151.overlay b/boards/shields/nrf7002ek/boards/nrf9151dk_nrf9151.overlay new file mode 100644 index 00000000000..70b5f088a8f --- /dev/null +++ b/boards/shields/nrf7002ek/boards/nrf9151dk_nrf9151.overlay @@ -0,0 +1,6 @@ +/* Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/boards/shields/nrf7002ek/boards/nrf9151dk_nrf9151_ns.overlay b/boards/shields/nrf7002ek/boards/nrf9151dk_nrf9151_ns.overlay new file mode 100644 index 00000000000..70b5f088a8f --- /dev/null +++ b/boards/shields/nrf7002ek/boards/nrf9151dk_nrf9151_ns.overlay @@ -0,0 +1,6 @@ +/* Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/boards/shields/nrf7002ek/boards/nrf9160dk_nrf9160_ns.overlay b/boards/shields/nrf7002ek/boards/nrf9160dk_nrf9160_ns.overlay new file mode 100644 index 00000000000..410408d5ba7 --- /dev/null +++ b/boards/shields/nrf7002ek/boards/nrf9160dk_nrf9160_ns.overlay @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Disabled because of conflicts on P0.00 and P0.01 - Arduino pins D0 and D1 + * (iovdd-ctrl-gpios and bucken-gpios in nrf7002ek, respectively). + */ +&uart1 { + status = "disabled"; +}; + +/* Typically we use GPIO extender to resolve these conflicts but the + * GPIO pin used by extender itself conflicts with Wi-Fi (0.6), so, + * disable LEDs and Button0/1. + */ +&led0 { + status = "disabled"; +}; + +&led1 { + status = "disabled"; +}; + +&led2 { + status = "disabled"; +}; + +&led3 { + status = "disabled"; +}; + +&button0 { + status = "disabled"; +}; + +&button1 { + status = "disabled"; +}; diff --git a/boards/shields/nrf7002ek/boards/nrf9161dk_nrf9161.overlay b/boards/shields/nrf7002ek/boards/nrf9161dk_nrf9161.overlay new file mode 100644 index 00000000000..77cc7f91507 --- /dev/null +++ b/boards/shields/nrf7002ek/boards/nrf9161dk_nrf9161.overlay @@ -0,0 +1,6 @@ +/* Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/boards/shields/nrf7002ek/boards/nrf9161dk_nrf9161_ns.overlay b/boards/shields/nrf7002ek/boards/nrf9161dk_nrf9161_ns.overlay new file mode 100644 index 00000000000..77cc7f91507 --- /dev/null +++ b/boards/shields/nrf7002ek/boards/nrf9161dk_nrf9161_ns.overlay @@ -0,0 +1,6 @@ +/* Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/boards/shields/nrf7002ek/doc/index.rst b/boards/shields/nrf7002ek/doc/index.rst new file mode 100644 index 00000000000..9f247be3501 --- /dev/null +++ b/boards/shields/nrf7002ek/doc/index.rst @@ -0,0 +1,74 @@ +.. _nrf7002ek: + +nRF7002 EK +########## + +Overview +******** + +The nRF7002 EK is a versatile evaluation kit in the form of an Arduino shield that can be used in +Nordic and non-Nordic host boards. + +The nRF7002 EK unlocks low-power Wi-Fi 6 capabilities for your host device. It support dual-band Wi-Fi +2.4GHz and 5GHz, and is based on the nRF7002 SoC. +Seamlessly connect to Wi-Fi networks and leverage Wi-Fi-based locationing, enabling advanced +features such as SSID sniffing of local Wi-Fi hubs + +.. figure:: nrf7002ek.png + :alt: nRF7002 EK + :align: center + + nRF7002 EK + +Requirements +************ + +The nRF7002 EK board is designed to fit straight into an Arduino connector and uses SPI as the +communication interface. Any host board that supports the Arduino connector can be used with +the nRF7002 EK. + +Prerequisites +------------- + +the nRF70 driver requires firmware binary blobs for Wi-Fi operation. Run the command +below to retrieve those files. + +.. code-block:: console + + west update + west blobs fetch hal_nordic + +Usage +***** + +The shield can be used in any application by setting ``--shield nrf7002ek`` when invoking ``west build``. + +SR Co-existence +############### + +The nRF7002 EK supports SR co-existence provided the host board supports it. The SR co-existence +pins are connected to the host board's GPIO pins. + +Two Kconfig options are available to enable SR co-existence: + +- :kconfig:option:`CONFIG_NRF70_SR_COEX`: Enables SR co-existence. +- :kconfig:option:`CONFIG_NRF70_SR_COEX_RF_SWITCH`: Control SR side RF switch. + +Shield Variants +############### + +The nRF7002 EK is available in three variants: + +- ``nrf7002ek``: The default variant. +- ``nrf7002ek_nrf7001``: Variant for the nRF7001 SoC or nRF7002 SoC emulating nRF7001 + that supports only 2.4GHz Wi-Fi. +- ``nrf7002ek_nrf7000``: Variant for the nRF7000 SoC or nRF7002 SoC emulating nRF7000 + that supports only 2.4GHz Wi-Fi. + + +References +********** + +- `nRF7002 EK product page `_ +- `nRF7002 product specification `_ +- `nRF7002 EK Co-existence `_ diff --git a/boards/shields/nrf7002ek/doc/nrf7002ek.png b/boards/shields/nrf7002ek/doc/nrf7002ek.png new file mode 100644 index 00000000000..9b4b0975371 Binary files /dev/null and b/boards/shields/nrf7002ek/doc/nrf7002ek.png differ diff --git a/boards/shields/nrf7002ek/nrf7002ek.overlay b/boards/shields/nrf7002ek/nrf7002ek.overlay new file mode 100644 index 00000000000..2a0f09bd955 --- /dev/null +++ b/boards/shields/nrf7002ek/nrf7002ek.overlay @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include + +/ { + chosen { + zephyr,wifi = &wlan0; + }; +}; + +&arduino_spi { + status = "okay"; + + nrf70: nrf7002-spi@0 { + compatible = "nordic,nrf7002-spi"; + status = "okay"; + reg = <0>; + spi-max-frequency = ; + + /* Include common nRF70 overlays */ + #include "nrf7002ek_common.dtsi" + #include "nrf7002ek_common_5g.dtsi" + }; +}; diff --git a/boards/shields/nrf7002ek/nrf7002ek_common.dtsi b/boards/shields/nrf7002ek/nrf7002ek_common.dtsi new file mode 100644 index 00000000000..102e0078d5f --- /dev/null +++ b/boards/shields/nrf7002ek/nrf7002ek_common.dtsi @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Common assignments for any nRF70 shield */ + +/* D0 */ +iovdd-ctrl-gpios = <&arduino_header 6 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; +/* D1 */ +bucken-gpios = <&arduino_header 7 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; +/* D7 */ +host-irq-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; +/* Short-range (SR) co-existence */ +/* D2 */ +status0-gpios = <&arduino_header 8 GPIO_ACTIVE_HIGH>; +/* D3 */ +req-gpios = <&arduino_header 9 GPIO_ACTIVE_HIGH>; +/* D4 */ +grant-gpios = <&arduino_header 10 (GPIO_PULL_DOWN | GPIO_ACTIVE_LOW)>; +/* D6 */ +swctrl1-gpios = <&arduino_header 12 GPIO_ACTIVE_HIGH>; +/* D8 */ +srrf-switch-gpios = <&arduino_header 14 GPIO_ACTIVE_HIGH>; + +/* Maximum TX power limits for 2.4 GHz */ +wifi-max-tx-pwr-2g-dsss = <21>; +wifi-max-tx-pwr-2g-mcs0 = <16>; +wifi-max-tx-pwr-2g-mcs7 = <16>; + +/* List of interfaces */ +wlan0: wlan0 { + compatible = "nordic,wlan"; +}; diff --git a/boards/shields/nrf7002ek/nrf7002ek_common_5g.dtsi b/boards/shields/nrf7002ek/nrf7002ek_common_5g.dtsi new file mode 100644 index 00000000000..8faa9b945fe --- /dev/null +++ b/boards/shields/nrf7002ek/nrf7002ek_common_5g.dtsi @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +wifi-max-tx-pwr-5g-low-mcs0 = <13>; +wifi-max-tx-pwr-5g-low-mcs7 = <13>; +wifi-max-tx-pwr-5g-mid-mcs0 = <13>; +wifi-max-tx-pwr-5g-mid-mcs7 = <13>; +wifi-max-tx-pwr-5g-high-mcs0 = <12>; +wifi-max-tx-pwr-5g-high-mcs7 = <12>; diff --git a/boards/shields/nrf7002ek/nrf7002ek_nrf7000.overlay b/boards/shields/nrf7002ek/nrf7002ek_nrf7000.overlay new file mode 100644 index 00000000000..28a3662f1d6 --- /dev/null +++ b/boards/shields/nrf7002ek/nrf7002ek_nrf7000.overlay @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include + +/ { + chosen { + zephyr,wifi = &wlan0; + }; +}; + +&arduino_spi { + status = "okay"; + + nrf70: nrf7002-spi@0 { + compatible = "nordic,nrf7000-spi"; + status = "okay"; + reg = <0>; + spi-max-frequency = ; + + /* Include common nRF70 overlays */ + #include "nrf7002ek_common.dtsi" + #include "nrf7002ek_common_5g.dtsi" + }; +}; diff --git a/boards/shields/nrf7002ek/nrf7002ek_nrf7001.overlay b/boards/shields/nrf7002ek/nrf7002ek_nrf7001.overlay new file mode 100644 index 00000000000..a3b84d1761d --- /dev/null +++ b/boards/shields/nrf7002ek/nrf7002ek_nrf7001.overlay @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include + +/ { + chosen { + zephyr,wifi = &wlan0; + }; +}; + +&arduino_spi { + status = "okay"; + + nrf70: nrf7001-spi@0 { + compatible = "nordic,nrf7001-spi"; + status = "okay"; + reg = <0>; + spi-max-frequency = ; + + /* Include common nRF70 overlays */ + #include "nrf7002ek_common.dtsi" + }; +}; diff --git a/boards/shields/nxp_btb44_ov5640/Kconfig.shield b/boards/shields/nxp_btb44_ov5640/Kconfig.shield new file mode 100644 index 00000000000..608188a2c54 --- /dev/null +++ b/boards/shields/nxp_btb44_ov5640/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_NXP_BTB44_OV5640 + def_bool $(shields_list_contains,nxp_btb44_ov5640) diff --git a/boards/shields/nxp_btb44_ov5640/doc/index.rst b/boards/shields/nxp_btb44_ov5640/doc/index.rst new file mode 100644 index 00000000000..07a7d24e7d1 --- /dev/null +++ b/boards/shields/nxp_btb44_ov5640/doc/index.rst @@ -0,0 +1,134 @@ +.. _nxp_btb44_ov5640: + +NXP BTB-44 OV5640 Camera Module +############################### + +Overview +******** + +This shield supports ov5640 camera modules which use a 44-pin board-to-board connector and +a MIPI CSI or DVP (parallel) interface. These camera modules are made specifically for and +provided together with NXP's i.MX RT1160 and RT1170 EVK boards. + +More information about this OV5640 camera module can be found at `Camera iMXRT`_. + +Pins assignment of the NXP board-to-board 44-pin OV5640 camera module +====================================================================== + ++----------------------+--------------------+ +| Camera Connector Pin | Function | ++======================+====================+ +| 1 | AGND | ++----------------------+--------------------+ +| 2 | AF_GND | ++----------------------+--------------------+ +| 3 | STROBE | ++----------------------+--------------------+ +| 4 | AF_VCC | ++----------------------+--------------------+ +| 5 | SDA | ++----------------------+--------------------+ +| 6 | VCMSINK | ++----------------------+--------------------+ +| 7 | SCL | ++----------------------+--------------------+ +| 8 | AVDD | ++----------------------+--------------------+ +| 9 | RESETB | ++----------------------+--------------------+ +| 10 | GPIO1 | ++----------------------+--------------------+ +| 11 | PCLK | ++----------------------+--------------------+ +| 12 | GPIO0 | ++----------------------+--------------------+ +| 13 | VSYNC | ++----------------------+--------------------+ +| 14 | FREX | ++----------------------+--------------------+ +| 15 | HREF | ++----------------------+--------------------+ +| 16 | MIPI_CSI_DP1 / D9 | ++----------------------+--------------------+ +| 17 | PWDN | ++----------------------+--------------------+ +| 18 | MIPI_CSI_DN1 / D8 | ++----------------------+--------------------+ +| 19 | MIPI_CSI_DP1 / D9 | ++----------------------+--------------------+ +| 20 | DGND | ++----------------------+--------------------+ +| 21 | MIPI_CSI_DN1 / D8 | ++----------------------+--------------------+ +| 22 | MIPI_CSI_CLKP / D7 | ++----------------------+--------------------+ +| 23 | MIPI_CSI_CLKP / D7 | ++----------------------+--------------------+ +| 24 | MIPI_CSI_CLKN / D6 | ++----------------------+--------------------+ +| 25 | MIPI_CSI_CLKN / D6 | ++----------------------+--------------------+ +| 26 | DGND | ++----------------------+--------------------+ +| 27 | MIPI_CSI_DP0 / D5 | ++----------------------+--------------------+ +| 28 | MIPI_CSI_DP0 / D5 | ++----------------------+--------------------+ +| 29 | MIPI_CSI_DN0 / D4 | ++----------------------+--------------------+ +| 30 | MIPI_CSI_DN0 / D4 | ++----------------------+--------------------+ +| 31 | D3 | ++----------------------+--------------------+ +| 32 | DGND | ++----------------------+--------------------+ +| 33 | D2 | ++----------------------+--------------------+ +| 34 | XCLK | ++----------------------+--------------------+ +| 35 | D1 | ++----------------------+--------------------+ +| 36 | DVDD | ++----------------------+--------------------+ +| 37 | D0 | ++----------------------+--------------------+ +| 38 | DOVDD | ++----------------------+--------------------+ +| 39 | DGND | ++----------------------+--------------------+ +| 40 | DGND | ++----------------------+--------------------+ +| 41 | GND | ++----------------------+--------------------+ +| 42 | GND | ++----------------------+--------------------+ +| 43 | GND | ++----------------------+--------------------+ +| 44 | AF_GND | ++----------------------+--------------------+ + +Requirements +************ + +This shield can only be used with a board which provides a 44-pin board-to-board +connector with MIPI CSI or DVP (parallel) interface where the pinouts are defined +as above, such as i.MX RT1160 and RT1170 EVK boards. + +Programming +*********** + +Set ``--shield nxp_btb44_ov5640`` when you invoke ``west build``. For example: + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/video/capture + :board: mimxrt1170_evk/mimxrt1176/cm7 + :shield: nxp_btb44_ov5640 + :goals: build + +References +********** + +.. target-notes:: + +.. _Camera iMXRT: + https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Connecting-camera-and-LCD-to-i-MX-RT-EVKs/ta-p/1122183 diff --git a/boards/shields/nxp_btb44_ov5640/nxp_btb44_ov5640.overlay b/boards/shields/nxp_btb44_ov5640/nxp_btb44_ov5640.overlay new file mode 100644 index 00000000000..e7c179f5d23 --- /dev/null +++ b/boards/shields/nxp_btb44_ov5640/nxp_btb44_ov5640.overlay @@ -0,0 +1,48 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/{ + chosen { + zephyr,camera = &nxp_csi; + }; +}; + +&nxp_cam_i2c { + status = "okay"; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + reset-gpios = <&nxp_cam_connector 9 GPIO_ACTIVE_LOW>; + powerdown-gpios = <&nxp_cam_connector 17 GPIO_ACTIVE_HIGH>; + + port { + ov5640_ep_out: endpoint { + remote-endpoint = <&mipi_csi2rx_ep_in>; + }; + }; + }; +}; + +&nxp_mipi_csi { + status = "okay"; + + sensor = <&ov5640>; + + ports { + port@1 { + reg = <1>; + + mipi_csi2rx_ep_in: endpoint { + remote-endpoint = <&ov5640_ep_out>; + }; + }; + }; +}; + +&nxp_csi { + status = "okay"; +}; diff --git a/boards/shields/pmod_acl/Kconfig.shield b/boards/shields/pmod_acl/Kconfig.shield new file mode 100644 index 00000000000..033dffd5d66 --- /dev/null +++ b/boards/shields/pmod_acl/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_PMOD_ACL + def_bool $(shields_list_contains,pmod_acl) diff --git a/boards/shields/pmod_acl/boards/apard32690_max32690_m4.overlay b/boards/shields/pmod_acl/boards/apard32690_max32690_m4.overlay new file mode 100644 index 00000000000..283feab0877 --- /dev/null +++ b/boards/shields/pmod_acl/boards/apard32690_max32690_m4.overlay @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + accel0 = &adxl345_pmod_acl; + }; +}; diff --git a/boards/shields/pmod_acl/doc/index.rst b/boards/shields/pmod_acl/doc/index.rst new file mode 100644 index 00000000000..7a635f435ad --- /dev/null +++ b/boards/shields/pmod_acl/doc/index.rst @@ -0,0 +1,52 @@ +.. pmod_acl: + +Digilent Pmod ACL +################# + +Overview +******** + +The Digilent Pmod ACL is a 3-axis digital accelerometer module powered by the +Analog Devices ADXL345. + +Programming +*********** + +Set ``--shield pmod_acl`` when you invoke ``west build``. For example: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/sensor_shell + :board: apard32690/max32690/m4 + :shield: pmod_acl + :goals: build + +Requirements +************ + +This shield can only be used with a board which provides a configuration +for Pmod connectors and defines node aliases for SPI and GPIO interfaces +(see :ref:`shields` for more details). + +References +********** + +- `Pmod ACL product page`_ +- `Pmod ACL reference manual`_ +- `Pmod ACL schematic`_ +- `ADXL345 product page`_ +- `ADXL345 data sheet`_ + +.. _Pmod ACL product page: + https://digilent.com/shop/pmod-acl-3-axis-accelerometer/ + +.. _Pmod ACL reference manual: + https://digilent.com/reference/pmod/pmodacl/reference-manual + +.. _Pmod ACL schematic: + https://digilent.com/reference/_media/reference/pmod/pmodacl/pmodacl_sch.pdf + +.. _ADXL345 product page: + https://www.analog.com/en/products/adxl345.html + +.. _ADXL345 data sheet: + https://www.analog.com/media/en/technical-documentation/data-sheets/adxl345.pdf diff --git a/boards/shields/pmod_acl/pmod_acl.overlay b/boards/shields/pmod_acl/pmod_acl.overlay new file mode 100644 index 00000000000..935655b1971 --- /dev/null +++ b/boards/shields/pmod_acl/pmod_acl.overlay @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pmod_spi { + status = "okay"; + + adxl345_pmod_acl: adxl345@0 { + compatible = "adi,adxl345"; + reg = <0x0>; + spi-max-frequency = ; + status = "okay"; + }; +}; diff --git a/boards/shields/reyax_lora/Kconfig.shield b/boards/shields/reyax_lora/Kconfig.shield new file mode 100644 index 00000000000..c82a3eacc27 --- /dev/null +++ b/boards/shields/reyax_lora/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2024 David Ullmann +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_REYAX_LORA + def_bool $(shields_list_contains,reyax_lora) diff --git a/boards/shields/reyax_lora/boards/cy8ckit_062s4.conf b/boards/shields/reyax_lora/boards/cy8ckit_062s4.conf new file mode 100644 index 00000000000..30752249749 --- /dev/null +++ b/boards/shields/reyax_lora/boards/cy8ckit_062s4.conf @@ -0,0 +1,6 @@ +# Copyright (c) 2024 David Ullmann +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_LORA=y +CONFIG_LORA_RYLRXXX=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/shields/reyax_lora/boards/cy8ckit_062s4.overlay b/boards/shields/reyax_lora/boards/cy8ckit_062s4.overlay new file mode 100644 index 00000000000..d45be1daa41 --- /dev/null +++ b/boards/shields/reyax_lora/boards/cy8ckit_062s4.overlay @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2024 David Ullmann + * SPDX-License-Identifier: Apache-2.0 + */ + + +&p0_2_scb0_uart_rx { + input-enable; +}; + +&p0_3_scb0_uart_tx { + drive-push-pull; +}; + +&arduino_serial { + pinctrl-0 = <&p0_2_scb0_uart_rx &p0_3_scb0_uart_tx>; + pinctrl-names = "default"; +}; + +&gpio_prt0 { + status = "okay"; +}; + +&gpio_prt2 { + status = "okay"; +}; diff --git a/boards/shields/reyax_lora/doc/index.rst b/boards/shields/reyax_lora/doc/index.rst new file mode 100644 index 00000000000..b16f95bc7bd --- /dev/null +++ b/boards/shields/reyax_lora/doc/index.rst @@ -0,0 +1,29 @@ +.. _reyax_lora: + +Reyax LoRa RYLR896 and RYLR915 Modules +###################################### + +Overview +******** + +These modules expose a simple uart interface for the Semtech SX1276 chip,which implements the LoRa PHY. + +More information about the board can be found at the +`Reyax RYLR page`_. + +Hardware Description +******************** +The Module contains 4 pins + +- VDD: Power Supply +- NRST: Active low reset +- RXD: Serial data input +- TXD: Serial data output +- GND: Ground + +References +********** + +.. target-notes:: +.. _Reyax RYLR page: + https://reyax.com/products/RYLR896 diff --git a/boards/shields/reyax_lora/reyax_lora.overlay b/boards/shields/reyax_lora/reyax_lora.overlay new file mode 100644 index 00000000000..080d78d92d0 --- /dev/null +++ b/boards/shields/reyax_lora/reyax_lora.overlay @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2024 David Ullmann + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/{ + aliases { + lora0 = &rylr_lora_modem; + }; +}; + + +&arduino_serial { + current-speed = <115200>; + status = "okay"; + rylr_lora_modem: rylr_lora_modem { + compatible = "reyax,rylrxxx"; + status = "okay"; + reset-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; + }; +}; diff --git a/boards/shields/rk043fn02h_ct/Kconfig.defconfig b/boards/shields/rk043fn02h_ct/Kconfig.defconfig new file mode 100644 index 00000000000..f2b199d9169 --- /dev/null +++ b/boards/shields/rk043fn02h_ct/Kconfig.defconfig @@ -0,0 +1,47 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SHIELD_RK043FN02H_CT + +if LVGL + +config INPUT + default y + +config INPUT_FT5336_INTERRUPT + default y + +# LVGL should allocate buffers equal to size of display +config LV_Z_VDB_SIZE + default 100 + +# Enable double buffering +config LV_Z_DOUBLE_VDB + default y + +# Force full refresh. This prevents memory copy associated with partial +# display refreshes, which is not necessary for the eLCDIF driver +config LV_Z_FULL_REFRESH + default y + +config LV_Z_BITS_PER_PIXEL + default 16 + +config LV_DPI_DEF + default 128 + +# Use offloaded render thread +config LV_Z_FLUSH_THREAD + default y + +choice LV_COLOR_DEPTH + default LV_COLOR_DEPTH_16 +endchoice + +# Force display buffers to be aligned to cache line size (32 bytes) +config LV_Z_VDB_ALIGN + default 32 + +endif # LVGL + +endif # SHIELD_RK043FN02H_CT diff --git a/boards/shields/rk043fn02h_ct/Kconfig.shield b/boards/shields/rk043fn02h_ct/Kconfig.shield new file mode 100644 index 00000000000..4cf0c812ae8 --- /dev/null +++ b/boards/shields/rk043fn02h_ct/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_RK043FN02H_CT + def_bool $(shields_list_contains,rk043fn02h_ct) diff --git a/boards/shields/rk043fn02h_ct/doc/index.rst b/boards/shields/rk043fn02h_ct/doc/index.rst new file mode 100644 index 00000000000..6b80c91f72c --- /dev/null +++ b/boards/shields/rk043fn02h_ct/doc/index.rst @@ -0,0 +1,105 @@ +.. _rk043fn02h_ct: + +NXP RK043FN02H-CT Parallel Display +################################## + +Overview +******** + +RK043FN02H-CT is a 4.3 inch TFT 480*272 pixels with LED backlight and +capacitive touch panel from Rocktech. This LCD panel can work with several i.MX +RT EVKs and LPC MCUs for evaluation of applications with display. + +More information about the shield can be found at the `RK043FN02H-CT product +page`_. + +This display uses a 40 pin parallel FPC interface plus 6 pin I2C interface, +available on many NXP EVKs. Note that this parallel FPC interface is not +compatible with the MIPI FPC interface present on other NXP EVKs. + +Pins Assignment of the Rocktech RK043FN02H-CT Parallel Display +============================================================== + ++-----------------------+------------------------+ +| Parallel FPC Pin | Function | ++=======================+========================+ +| 1 | LED backlight cathode | ++-----------------------+------------------------+ +| 2 | LED backlight anode | ++-----------------------+------------------------+ +| 3 | GND | ++-----------------------+------------------------+ +| 4 | VDD (3v3) | ++-----------------------+------------------------+ +| 5-7 | GND | ++-----------------------+------------------------+ +| 8-12 | LCD D11-D15 | ++-----------------------+------------------------+ +| 13-14 | GND | ++-----------------------+------------------------+ +| 15-20 | LCD D5-D10 | ++-----------------------+------------------------+ +| 21-23 | GND | ++-----------------------+------------------------+ +| 24-28 | LCD D0-D4 | ++-----------------------+------------------------+ +| 29 | GND | ++-----------------------+------------------------+ +| 30 | LCD CLK | ++-----------------------+------------------------+ +| 31 | LCD DISP | ++-----------------------+------------------------+ +| 32 | LCD HSYNC | ++-----------------------+------------------------+ +| 33 | LCD VSYNC | ++-----------------------+------------------------+ +| 34 | LCD DE | ++-----------------------+------------------------+ +| 35 | NC | ++-----------------------+------------------------+ +| 36 | GND | ++-----------------------+------------------------+ +| 37-40 | NC | ++-----------------------+------------------------+ + ++-----------------------+------------------------+ +| I2C Connector Pin | Function | ++=======================+========================+ +| 1 | VDD (3v3) | ++-----------------------+------------------------+ +| 2 | LCD Touch Reset | ++-----------------------+------------------------+ +| 3 | LCD Touch Interrupt | ++-----------------------+------------------------+ +| 4 | LCD I2C SCL | ++-----------------------+------------------------+ +| 5 | LCD I2C SDA | ++-----------------------+------------------------+ +| 6 | GND | ++-----------------------+------------------------+ + +Requirements +************ + +This shield can only be used with a board which provides a configuration +for the 40+6 pin parallel/I2C FPC interface + +Programming +*********** + +Set ``--shield rk043fn02h_ct`` when you invoke ``west build``. For +example: + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/display + :board: mimxrt1060_evk + :shield: rk043fn02h_ct + :goals: build + +References +********** + +.. target-notes:: + +.. _RK043FN02H-CT product page: + https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/4-3-lcd-panel:RK043FN02H-CT diff --git a/boards/shields/rk043fn02h_ct/rk043fn02h_ct.overlay b/boards/shields/rk043fn02h_ct/rk043fn02h_ct.overlay new file mode 100644 index 00000000000..ab0b10d70af --- /dev/null +++ b/boards/shields/rk043fn02h_ct/rk043fn02h_ct.overlay @@ -0,0 +1,50 @@ +/* + * Copyright 2024, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/{ + chosen { + zephyr,display = &zephyr_lcdif; + }; + + lvgl_pointer { + compatible = "zephyr,lvgl-pointer-input"; + input = <&ft5336_rk043fn02h_ct>; + }; +}; + +&nxp_touch_i2c { + status = "okay"; + ft5336_rk043fn02h_ct: ft5336@38 { + compatible = "focaltech,ft5336"; + reg = <0x38>; + int-gpios = <&nxp_i2c_touch_fpc 2 GPIO_ACTIVE_LOW>; + }; +}; + +&zephyr_lcdif { + status = "okay"; + width = <480>; + height = <272>; + display-timings { + compatible = "zephyr,panel-timing"; + hsync-len = <41>; + hfront-porch = <4>; + hback-porch = <8>; + vsync-len = <10>; + vfront-porch = <4>; + vback-porch = <2>; + de-active= <1>; + pixelclk-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + clock-frequency = <9210240>; + }; + pixel-format = ; + data-bus-width = "16-bit"; + backlight-gpios = <&nxp_parallel_lcd_connector 0 GPIO_ACTIVE_HIGH>; +}; diff --git a/boards/shields/rk043fn66hs_ctg/Kconfig.defconfig b/boards/shields/rk043fn66hs_ctg/Kconfig.defconfig new file mode 100644 index 00000000000..58e4b93b088 --- /dev/null +++ b/boards/shields/rk043fn66hs_ctg/Kconfig.defconfig @@ -0,0 +1,47 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SHIELD_RK043FN66HS_CTG + +if LVGL + +config INPUT + default y + +config INPUT_GT911_INTERRUPT + default y + +# LVGL should allocate buffers equal to size of display +config LV_Z_VDB_SIZE + default 100 + +# Enable double buffering +config LV_Z_DOUBLE_VDB + default y + +# Force full refresh. This prevents memory copy associated with partial +# display refreshes, which is not necessary for the eLCDIF driver +config LV_Z_FULL_REFRESH + default y + +config LV_Z_BITS_PER_PIXEL + default 16 + +config LV_DPI_DEF + default 128 + +# Use offloaded render thread +config LV_Z_FLUSH_THREAD + default y + +choice LV_COLOR_DEPTH + default LV_COLOR_DEPTH_16 +endchoice + +# Force display buffers to be aligned to cache line size (32 bytes) +config LV_Z_VDB_ALIGN + default 32 + +endif # LVGL + +endif # SHIELD_RK043FN66HS_CTG diff --git a/boards/shields/rk043fn66hs_ctg/Kconfig.shield b/boards/shields/rk043fn66hs_ctg/Kconfig.shield new file mode 100644 index 00000000000..02a15503e4c --- /dev/null +++ b/boards/shields/rk043fn66hs_ctg/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_RK043FN66HS_CTG + def_bool $(shields_list_contains,rk043fn66hs_ctg) diff --git a/boards/shields/rk043fn66hs_ctg/doc/index.rst b/boards/shields/rk043fn66hs_ctg/doc/index.rst new file mode 100644 index 00000000000..b600afedc30 --- /dev/null +++ b/boards/shields/rk043fn66hs_ctg/doc/index.rst @@ -0,0 +1,105 @@ +.. _rk043fn66hs_ctg: + +NXP RK043FN66HS-CTG Parallel Display +#################################### + +Overview +******** + +RK043FN66HS-CTG is a 4.3 inch TFT 480*272 pixels with LED backlight and +capacitive touch panel from Rocktech. This LCD panel can work with several i.MX +RT EVKs and LPC MCUs for evaluation of applications with display. + +More information about the shield can be found at the `RK043FN66HS-CTG product +page`_. + +This display uses a 40 pin parallel FPC interface plus 6 pin I2C interface, +available on many NXP EVKs. Note that this parallel FPC interface is not +compatible with the MIPI FPC interface present on other NXP EVKs. + +Pins Assignment of the Rocktech RK043FN66HS-CTG Parallel Display +================================================================ + ++-----------------------+------------------------+ +| Parallel FPC Pin | Function | ++=======================+========================+ +| 1 | LED backlight cathode | ++-----------------------+------------------------+ +| 2 | LED backlight anode | ++-----------------------+------------------------+ +| 3 | GND | ++-----------------------+------------------------+ +| 4 | VDD (3v3) | ++-----------------------+------------------------+ +| 5-7 | GND | ++-----------------------+------------------------+ +| 8-12 | LCD D11-D15 | ++-----------------------+------------------------+ +| 13-14 | GND | ++-----------------------+------------------------+ +| 15-20 | LCD D5-D10 | ++-----------------------+------------------------+ +| 21-23 | GND | ++-----------------------+------------------------+ +| 24-28 | LCD D0-D4 | ++-----------------------+------------------------+ +| 29 | GND | ++-----------------------+------------------------+ +| 30 | LCD CLK | ++-----------------------+------------------------+ +| 31 | LCD DISP | ++-----------------------+------------------------+ +| 32 | LCD HSYNC | ++-----------------------+------------------------+ +| 33 | LCD VSYNC | ++-----------------------+------------------------+ +| 34 | LCD DE | ++-----------------------+------------------------+ +| 35 | NC | ++-----------------------+------------------------+ +| 36 | GND | ++-----------------------+------------------------+ +| 37-40 | NC | ++-----------------------+------------------------+ + ++-----------------------+------------------------+ +| I2C Connector Pin | Function | ++=======================+========================+ +| 1 | VDD (3v3) | ++-----------------------+------------------------+ +| 2 | LCD Touch Reset | ++-----------------------+------------------------+ +| 3 | LCD Touch Interrupt | ++-----------------------+------------------------+ +| 4 | LCD I2C SCL | ++-----------------------+------------------------+ +| 5 | LCD I2C SDA | ++-----------------------+------------------------+ +| 6 | GND | ++-----------------------+------------------------+ + +Requirements +************ + +This shield can only be used with a board which provides a configuration +for the 40+6 pin parallel/I2C FPC interface + +Programming +*********** + +Set ``--shield rk043fn66hs_ctg`` when you invoke ``west build``. For +example: + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/display + :board: mimxrt1060_evk + :shield: rk043fn66hs_ctg + :goals: build + +References +********** + +.. target-notes:: + +.. _RK043FN66HS-CTG product page: + https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/4-3-lcd-panel:RK043FN66HS-CTG diff --git a/boards/shields/rk043fn66hs_ctg/rk043fn66hs_ctg.overlay b/boards/shields/rk043fn66hs_ctg/rk043fn66hs_ctg.overlay new file mode 100644 index 00000000000..b992ec932b8 --- /dev/null +++ b/boards/shields/rk043fn66hs_ctg/rk043fn66hs_ctg.overlay @@ -0,0 +1,51 @@ +/* + * Copyright 2024, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/{ + chosen { + zephyr,display = &zephyr_lcdif; + }; + + lvgl_pointer { + compatible = "zephyr,lvgl-pointer-input"; + input = <>911_rk043fn66hs_ctg>; + }; +}; + +&nxp_touch_i2c { + status = "okay"; + gt911_rk043fn66hs_ctg: gt911@5d { + compatible = "goodix,gt911"; + reg = <0x5d>; + irq-gpios = <&nxp_i2c_touch_fpc 2 GPIO_ACTIVE_HIGH>; + reset-gpios = <&nxp_i2c_touch_fpc 1 GPIO_ACTIVE_LOW>; + }; +}; + +&zephyr_lcdif { + status = "okay"; + width = <480>; + height = <272>; + display-timings { + compatible = "zephyr,panel-timing"; + hsync-len = <4>; + hfront-porch = <8>; + hback-porch = <43>; + vsync-len = <4>; + vfront-porch = <8>; + vback-porch = <12>; + de-active= <1>; + pixelclk-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + clock-frequency = <9210240>; + }; + pixel-format = ; + data-bus-width = "16-bit"; + backlight-gpios = <&nxp_parallel_lcd_connector 0 GPIO_ACTIVE_HIGH>; +}; diff --git a/boards/shields/rk055hdmipi4m/doc/index.rst b/boards/shields/rk055hdmipi4m/doc/index.rst index 03b50e31f06..32975c5c962 100644 --- a/boards/shields/rk055hdmipi4m/doc/index.rst +++ b/boards/shields/rk055hdmipi4m/doc/index.rst @@ -1,7 +1,7 @@ .. _rk055hdmipi4m: -RK055HDMIPI4M MIPI Display -########################## +NXP RK055HDMIPI4M MIPI Display +############################## Overview ******** @@ -50,7 +50,7 @@ for the 40 pin FPC interface Programming *********** -Set ``-DSHIELD=rk055hdmipi4m`` when you invoke ``west build``. For +Set ``--shield rk055hdmipi4m`` when you invoke ``west build``. For example: .. zephyr-app-commands:: diff --git a/boards/shields/rk055hdmipi4ma0/doc/index.rst b/boards/shields/rk055hdmipi4ma0/doc/index.rst index 887a70fb246..a5d93b454e6 100644 --- a/boards/shields/rk055hdmipi4ma0/doc/index.rst +++ b/boards/shields/rk055hdmipi4ma0/doc/index.rst @@ -1,7 +1,7 @@ .. _rk055hdmipi4ma0: -RK055HDMIPI4MA0 MIPI Display -############################ +NXP RK055HDMIPI4MA0 MIPI Display +################################ Overview ******** @@ -50,7 +50,7 @@ for the 40 pin FPC interface Programming *********** -Set ``-DSHIELD=rk055hdmipi4ma0`` when you invoke ``west build``. For +Set ``--shield rk055hdmipi4ma0`` when you invoke ``west build``. For example: .. zephyr-app-commands:: diff --git a/boards/shields/rpi_pico_uno_flexypin/doc/index.rst b/boards/shields/rpi_pico_uno_flexypin/doc/index.rst index 3ac57cfaa38..f7d19831e6e 100644 --- a/boards/shields/rpi_pico_uno_flexypin/doc/index.rst +++ b/boards/shields/rpi_pico_uno_flexypin/doc/index.rst @@ -6,12 +6,13 @@ RaspberryPi Pico to UNO FlexyPin Adapter Overview ******** -Raspberry Pi Pico to Uno `FlexyPin Adapter` is a converter-PCB to Arduino UNO form-factor -from Raspberry Pi Pico that is released in Open Source Hardware. -This board design to use with `FlexyPin`. +The Raspberry Pi Pico to Uno FlexyPin Adapter is an open-source hardware converter PCB that adapts +the Raspberry Pi Pico to the Arduino UNO form factor +This board is designed to be use with FlexyPin connector pins. The FlexyPin holds Pico and contacts to castellated through-hole. -With simple soldering, it can also be used as a board to convert the RapsberryPi Pico -o the Arduino UNO form factor. + +With simple soldering, it can also be used as a board to convert the Rapsberry Pi Pico +to the Arduino UNO form factor. .. image:: img/rpi_pico_uno_flexypin.png :align: center @@ -71,7 +72,7 @@ Pins Assignment of the RaspberryPi Pico to UNO FlexyPin Adapter Programming *********** -Set ``-DSHIELD=rpi_pico_uno_flexypin`` when you invoke ``west build``. +Set ``--shield rpi_pico_uno_flexypin`` when you invoke ``west build``. This shield is just a converter, so it is usually used with other Arduino shield. For example, @@ -79,7 +80,7 @@ For example, .. zephyr-app-commands:: :zephyr-app: samples/net/wifi :board: rpi_pico - :shield: 'rpi_pico_uno_flexypin;esp_8266_arduino' + :shield: rpi_pico_uno_flexypin,esp_8266_arduino :goals: build References diff --git a/boards/shields/seeed_xiao_expansion_board/doc/index.rst b/boards/shields/seeed_xiao_expansion_board/doc/index.rst index d7ad1a2044b..05db6618219 100644 --- a/boards/shields/seeed_xiao_expansion_board/doc/index.rst +++ b/boards/shields/seeed_xiao_expansion_board/doc/index.rst @@ -53,7 +53,7 @@ Programming LED Button Sample ================= -Set ``-DSHIELD=seeed_xiao_expansion_board`` when you invoke ``west build``. For example: +Set ``--shield seeed_xiao_expansion_board`` when you invoke ``west build``. For example: .. zephyr-app-commands:: :zephyr-app: samples/basic/button @@ -64,7 +64,7 @@ Set ``-DSHIELD=seeed_xiao_expansion_board`` when you invoke ``west build``. For LVGL Basic Sample ========================== -Set ``-DSHIELD=seeed_xiao_expansion_board`` when you invoke ``west build``. For example: +Set ``--shield seeed_xiao_expansion_board`` when you invoke ``west build``. For example: .. zephyr-app-commands:: :zephyr-app: samples/subsys/display/lvgl diff --git a/boards/shields/seeed_xiao_round_display/doc/index.rst b/boards/shields/seeed_xiao_round_display/doc/index.rst index de079248746..97125cec386 100644 --- a/boards/shields/seeed_xiao_round_display/doc/index.rst +++ b/boards/shields/seeed_xiao_round_display/doc/index.rst @@ -23,7 +23,7 @@ More information can be found on `the Getting Started page`_ Programming *********** -Set ``-DSHIELD=seeed_xiao_round_display`` when you invoke ``west build``. +Set ``--shield seeed_xiao_round_display`` when you invoke ``west build``. LVGL Basic Sample ================= diff --git a/boards/shields/seeed_xiao_round_display/seeed_xiao_round_display.overlay b/boards/shields/seeed_xiao_round_display/seeed_xiao_round_display.overlay index dab060bb604..d4a3ad1329e 100644 --- a/boards/shields/seeed_xiao_round_display/seeed_xiao_round_display.overlay +++ b/boards/shields/seeed_xiao_round_display/seeed_xiao_round_display.overlay @@ -27,6 +27,26 @@ aliases { rtc = &pcf8563_xiao_round_display; }; + + xiao_round_display_mipi_dbi { + compatible = "zephyr,mipi-dbi-spi"; + spi-dev = <&xiao_spi>; + dc-gpios = <&xiao_d 3 GPIO_ACTIVE_HIGH>; + write-only; + #address-cells = <1>; + #size-cells = <0>; + + gc9a01_xiao_round_display: gc9a01@0 { + status = "okay"; + compatible = "galaxycore,gc9x01x"; + reg = <0>; + mipi-max-frequency = ; + pixel-format = ; + width = <240>; + height = <240>; + display-inversion; + }; + }; }; &xiao_adc { @@ -62,18 +82,6 @@ status = "okay"; cs-gpios = <&xiao_d 1 GPIO_ACTIVE_LOW>, <&xiao_d 2 GPIO_ACTIVE_LOW>; - gc9a01_xiao_round_display: gc9a01@0 { - status = "okay"; - compatible = "galaxycore,gc9x01x"; - reg = <0>; - spi-max-frequency = ; - cmd-data-gpios = <&xiao_d 3 GPIO_ACTIVE_HIGH>; - pixel-format = ; - width = <240>; - height = <240>; - display-inversion; - }; - sdhc_xiao_round_display: sdhc@1 { compatible = "zephyr,sdhc-spi-slot"; reg = <1>; diff --git a/boards/shields/semtech_sx1262mb2das/doc/index.rst b/boards/shields/semtech_sx1262mb2das/doc/index.rst index f241bd9deda..50d54a7239b 100644 --- a/boards/shields/semtech_sx1262mb2das/doc/index.rst +++ b/boards/shields/semtech_sx1262mb2das/doc/index.rst @@ -47,7 +47,7 @@ for Arduino connectors (see :ref:`shields` for more details). Programming *********** -Set ``-DSHIELD=semtech_sx1262mb2das`` when you invoke ``west build``. For +Set ``--shield semtech_sx1262mb2das`` when you invoke ``west build``. For example: .. zephyr-app-commands:: diff --git a/boards/shields/semtech_sx1272mb2das/doc/index.rst b/boards/shields/semtech_sx1272mb2das/doc/index.rst index 8dcea32f3a5..2aa9de07c3e 100644 --- a/boards/shields/semtech_sx1272mb2das/doc/index.rst +++ b/boards/shields/semtech_sx1272mb2das/doc/index.rst @@ -50,7 +50,7 @@ for Arduino connectors and defines node aliases for SPI and GPIO interfaces Programming *********** -Set ``-DSHIELD=semtech_sx1272mb2das`` when you invoke ``west build``. For +Set ``--shield semtech_sx1272mb2das`` when you invoke ``west build``. For example: .. zephyr-app-commands:: diff --git a/boards/shields/semtech_sx1276mb1mas/doc/index.rst b/boards/shields/semtech_sx1276mb1mas/doc/index.rst index bdf85d4d3c1..d4b7d07c454 100644 --- a/boards/shields/semtech_sx1276mb1mas/doc/index.rst +++ b/boards/shields/semtech_sx1276mb1mas/doc/index.rst @@ -58,7 +58,7 @@ Arduino connectors and defines node aliases for SPI and GPIO interfaces (see Programming *********** -Set ``-DSHIELD=semtech_sx1271mb1mas`` when you invoke ``west build``. For +Set ``--shield semtech_sx1271mb1mas`` when you invoke ``west build``. For example: .. zephyr-app-commands:: diff --git a/boards/shields/sparkfun_carrier_asset_tracker/Kconfig.defconfig b/boards/shields/sparkfun_carrier_asset_tracker/Kconfig.defconfig new file mode 100644 index 00000000000..da44e62a05f --- /dev/null +++ b/boards/shields/sparkfun_carrier_asset_tracker/Kconfig.defconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2024 Jerónimo Agulló +# SPDX-License-Identifier: Apache-2.0 + +if SHIELD_SPARKFUN_CARRIER_ASSET_TRACKER + +config SERIAL + default y + +config UART_INTERRUPT_DRIVEN + default y + +config UART_ASYNC_API + default y + +config I2C + default y + +config SPI + default y + +endif # SHIELD_SPARKFUN_CARRIER_ASSET_TRACKER diff --git a/boards/shields/sparkfun_carrier_asset_tracker/Kconfig.shield b/boards/shields/sparkfun_carrier_asset_tracker/Kconfig.shield new file mode 100644 index 00000000000..71cff267351 --- /dev/null +++ b/boards/shields/sparkfun_carrier_asset_tracker/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Jerónimo Agulló +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_SPARKFUN_CARRIER_ASSET_TRACKER + def_bool $(shields_list_contains,sparkfun_carrier_asset_tracker) diff --git a/boards/shields/sparkfun_carrier_asset_tracker/doc/img/sparkfun_carrier_asset_tracker.webp b/boards/shields/sparkfun_carrier_asset_tracker/doc/img/sparkfun_carrier_asset_tracker.webp new file mode 100644 index 00000000000..a76682a0cef Binary files /dev/null and b/boards/shields/sparkfun_carrier_asset_tracker/doc/img/sparkfun_carrier_asset_tracker.webp differ diff --git a/boards/shields/sparkfun_carrier_asset_tracker/doc/index.rst b/boards/shields/sparkfun_carrier_asset_tracker/doc/index.rst new file mode 100644 index 00000000000..00aea7b9bb1 --- /dev/null +++ b/boards/shields/sparkfun_carrier_asset_tracker/doc/index.rst @@ -0,0 +1,117 @@ +.. _sparkfun_carrier_asset_tracker: + +Sparkfun SparkFun MicroMod Asset Tracker Shield +############################################### + +Overview +******** + +The SparkFun MicroMod Asset Tracker Carrier Shield is part of the Sparkfun +Micromod standard, a modular interface ecosystem that uses the M.2 standard +to mix and match your choice of processor with specific Functions Boards. + +The Asset Tracker Carrier Shield is built around the u-blox SARA-R510M8S +module, which offers Secure Cloud LTE-M and NB-IoT data communication for +multi-regional use and GNSS capabilities via an integrated u-blox M8 GNSS +receiver for accurate positioning information. + +Besides, this shield has an integrated ICM-20948 Inertial Measurement Unit +(IMU) for Nine Degree-Of-Freedom, a built-in micro-SD card socket for data +logging as well as a nano SIM card port. + +.. figure:: img/sparkfun_carrier_asset_tracker.webp + :align: center + :alt: Sparkfun SparkFun MicroMod Asset Tracker Shield + + Sparkfun SparkFun MicroMod Asset Tracker Shield (Credit: Sparkfun) + +More information about the shield can be found at the `SparkFun MicroMod +Asset Tracker guide website`_. + +Pins Assignment of Sparkfun SparkFun MicroMod Asset Tracker Shield +================================================================== + +The SparkFun MicroMod Asset Tracker Carrier Shield uses a 76 pins M.2 +connector. The following table depicts the interfaces and pins supported: +by Zephyr: ++-----------------------+---------------------------------+ +| Shield Connector Pin | Function | ++=======================+=================================+ +| micromod_1_uart alias | UART 1 (with CTS and RTS pins) | ++-----------------------+---------------------------------+ +| micromod_2_uart alias | UART 2 | ++-----------------------+---------------------------------+ +| micromod_0_i2c alias | i2c 0 | ++-----------------------+---------------------------------+ +| micromod_1_i2c alias | i2c 1 | ++-----------------------+---------------------------------+ +| micromod_0_spi alias | SPI 0 | ++-----------------------+---------------------------------+ +| A0 | Analog pin | ++-----------------------+---------------------------------+ +| A1 | Analog pin | ++-----------------------+---------------------------------+ +| D0 | Digital pin | ++-----------------------+---------------------------------+ +| D1/CAM_TRIG | Digital pin | ++-----------------------+---------------------------------+ +| I2C_INT# | i2c interrupt pin | ++-----------------------+---------------------------------+ +| G0/BUS0 | General purpose pin | ++-----------------------+---------------------------------+ +| G1/BUS1 | General purpose pin | ++-----------------------+---------------------------------+ +| G2/BUS2 | General purpose pin | ++-----------------------+---------------------------------+ +| G3/BUS3 | General purpose pin | ++-----------------------+---------------------------------+ +| G4/BUS4 | General purpose pin | ++-----------------------+---------------------------------+ +| G5/BUS5 | General purpose pin | ++-----------------------+---------------------------------+ +| G6/BUS6 | General purpose pin | ++-----------------------+---------------------------------+ +| G7/BUS7 | General purpose pin | ++-----------------------+---------------------------------+ +| G8 | General purpose pin | ++-----------------------+---------------------------------+ +| G9/ADC_D-/CAM_HSYNC | General purpose pin | ++-----------------------+---------------------------------+ +| G10/ADC_D+/CAM_VSYNC | General purpose pin | ++-----------------------+---------------------------------+ +| G11/SWO | General purpose pin | ++-----------------------+---------------------------------+ +| SPI_CS | General purpose pin | ++-----------------------+---------------------------------+ + +A detailed definition of the Micromod standard can be found on the +`Micromod specification website`_ + +Requirements +************ + +This shield can only be used with a board which provides a configuration for +Micromod connectors and defines node aliases for UART, I2C and SPI interfaces (see +:ref:`shields` for more details). + +Programming +*********** + +Set ``--shield sparkfun_carrier_asset_tracker`` when you invoke ``west build``. For +example: + +.. zephyr-app-commands:: + :zephyr-app: samples/net/cellular_modem/ + :board: micromod/nrf52840 + :shield: sparkfun_carrier_asset_tracker + :goals: build + +References +********** + +.. target-notes:: + +.. _SparkFun MicroMod Asset Tracker guide website: + https://learn.sparkfun.com/tutorials/micromod-asset-tracker-carrier-board-hookup-guide +.. _Micromod specification website: + https://www.sparkfun.com/micromod diff --git a/boards/shields/sparkfun_carrier_asset_tracker/sparkfun_carrier_asset_tracker.overlay b/boards/shields/sparkfun_carrier_asset_tracker/sparkfun_carrier_asset_tracker.overlay new file mode 100644 index 00000000000..6c7a9383c27 --- /dev/null +++ b/boards/shields/sparkfun_carrier_asset_tracker/sparkfun_carrier_asset_tracker.overlay @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2024 Jerónimo Agulló + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + modem-uart = µmod_1_uart; + modem = &modem; + }; +}; + +µmod_1_uart { + current-speed = <115200>; + hw-flow-control; + status = "okay"; + + modem: sara_r5 { + compatible = "u-blox,sara-r5"; + mdm-power-gpios = <µmod_header 7 0>; /* G2 */ + mdm-reset-gpios = <µmod_header 12 0>; /* D6 */ + status = "okay"; + }; +}; + +µmod_0_spi { + status = "okay"; + /* G0 (SD_CS) */ + cs-gpios = <µmod_header 5 GPIO_ACTIVE_LOW>; + + sdhc0: sdhc@0 { + compatible = "zephyr,sdhc-spi-slot"; + reg = <0>; + status = "okay"; + mmc { + compatible = "zephyr,sdmmc-disk"; + status = "okay"; + }; + spi-max-frequency = ; + }; +}; + +µmod_0_i2c { + max17048: max17048@36 { + compatible = "maxim,max17048"; + reg = <0x36>; + status = "okay"; + }; +}; diff --git a/boards/shields/ssd1306/boards/reel_board.overlay b/boards/shields/ssd1306/boards/reel_board.overlay index a6834a5419e..fd22bde3145 100644 --- a/boards/shields/ssd1306/boards/reel_board.overlay +++ b/boards/shields/ssd1306/boards/reel_board.overlay @@ -1,3 +1,3 @@ &arduino_i2c { - compatible = "nordic,nrf-twi"; + compatible = "nordic,nrf-twi"; }; diff --git a/boards/shields/ssd1306/doc/index.rst b/boards/shields/ssd1306/doc/index.rst index ca1b5ad1f98..5184493141a 100644 --- a/boards/shields/ssd1306/doc/index.rst +++ b/boards/shields/ssd1306/doc/index.rst @@ -38,7 +38,7 @@ for Arduino connectors and defines a node alias for the I2C interface Programming *********** -Set ``-DSHIELD=ssd1306_128x64`` when you invoke ``west build``. For example: +Set ``--shield ssd1306_128x64`` when you invoke ``west build``. For example: .. zephyr-app-commands:: :zephyr-app: samples/subsys/display/lvgl diff --git a/boards/shields/st7735r/doc/index.rst b/boards/shields/st7735r/doc/index.rst index 3004fde6163..cee6162c502 100644 --- a/boards/shields/st7735r/doc/index.rst +++ b/boards/shields/st7735r/doc/index.rst @@ -50,7 +50,7 @@ for Arduino connectors and defines node aliases for SPI and GPIO interfaces Programming *********** -Set ``-DSHIELD=st7735r_ada_160x128`` when you invoke ``west build``. For example: +Set ``--shield st7735r_ada_160x128`` when you invoke ``west build``. For example: .. zephyr-app-commands:: :zephyr-app: samples/subsys/display/lvgl diff --git a/boards/shields/st7789v_generic/doc/index.rst b/boards/shields/st7789v_generic/doc/index.rst index d9282b60bf9..e6f92e63a7c 100644 --- a/boards/shields/st7789v_generic/doc/index.rst +++ b/boards/shields/st7789v_generic/doc/index.rst @@ -53,7 +53,7 @@ for Arduino connectors and defines node aliases for SPI and GPIO interfaces Programming *********** -Set ``-DSHIELD=st7789v_tl019fqv01`` when you invoke ``west build``. For example: +Set ``--shield st7789v_tl019fqv01`` when you invoke ``west build``. For example: .. zephyr-app-commands:: :zephyr-app: samples/subsys/display/lvgl diff --git a/boards/shields/st7789v_generic/st7789v_tl019fqv01.overlay b/boards/shields/st7789v_generic/st7789v_tl019fqv01.overlay index c12ee45515b..46c863b5ac8 100644 --- a/boards/shields/st7789v_generic/st7789v_tl019fqv01.overlay +++ b/boards/shields/st7789v_generic/st7789v_tl019fqv01.overlay @@ -3,41 +3,51 @@ * * SPDX-License-Identifier: Apache-2.0 */ +#include / { chosen { zephyr,display = &st7789v_st7789v_tl019fqv01; }; + + mipi_dbi_st7789v_tl019fqv01 { + compatible = "zephyr,mipi-dbi-spi"; + spi-dev = <&arduino_spi>; + dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */ + reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */ + write-only; + #address-cells = <1>; + #size-cells = <0>; + + st7789v_st7789v_tl019fqv01: st7789v@0 { + compatible = "sitronix,st7789v"; + mipi-max-frequency = <20000000>; + reg = <0>; + width = <320>; + height = <170>; + x-offset = <0>; + y-offset = <35>; + vcom = <0x2b>; + gctrl = <0x35>; + vrhs = <0x0f>; + vdvs = <0x20>; + mdac = <0x60>; + gamma = <0x01>; + colmod = <0x55>; + lcm = <0x2c>; + porch-param = [0c 0c 00 33 33]; + cmd2en-param = [5a 69 02 01]; + pwctrl1-param = [52 a1]; + pvgam-param = [D0 00 02 07 0B 1A 31 54 40 29 12 12 12 17]; + nvgam-param = [D0 00 02 07 05 15 2D 44 44 1C 18 16 1C 1D]; + ram-param = [00 F8]; + rgb-param = [CD 08 14]; + mipi-mode = ; + }; + }; }; &arduino_spi { status = "okay"; cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */ - - st7789v_st7789v_tl019fqv01: st7789v@0 { - compatible = "sitronix,st7789v"; - spi-max-frequency = <20000000>; - reg = <0>; - cmd-data-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>; /* D9 */ - reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */ - width = <320>; - height = <170>; - x-offset = <0>; - y-offset = <35>; - vcom = <0x2b>; - gctrl = <0x35>; - vrhs = <0x0f>; - vdvs = <0x20>; - mdac = <0x60>; - gamma = <0x01>; - colmod = <0x55>; - lcm = <0x2c>; - porch-param = [0c 0c 00 33 33]; - cmd2en-param = [5a 69 02 01]; - pwctrl1-param = [52 a1]; - pvgam-param = [D0 00 02 07 0B 1A 31 54 40 29 12 12 12 17]; - nvgam-param = [D0 00 02 07 05 15 2D 44 44 1C 18 16 1C 1D]; - ram-param = [00 F8]; - rgb-param = [CD 08 14]; - }; }; diff --git a/boards/shields/st7789v_generic/st7789v_waveshare_240x240.overlay b/boards/shields/st7789v_generic/st7789v_waveshare_240x240.overlay index 3c7205ce287..0a92937a982 100644 --- a/boards/shields/st7789v_generic/st7789v_waveshare_240x240.overlay +++ b/boards/shields/st7789v_generic/st7789v_waveshare_240x240.overlay @@ -5,40 +5,51 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { chosen { zephyr,display = &st7789v_st7789v_waveshare_240x240; }; + + mipi_dbi_st7789v_waveshare_240x240 { + compatible = "zephyr,mipi-dbi-spi"; + spi-dev = <&arduino_spi>; + dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */ + reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */ + write-only; + #address-cells = <1>; + #size-cells = <0>; + + st7789v_st7789v_waveshare_240x240: st7789v@0 { + compatible = "sitronix,st7789v"; + mipi-max-frequency = <20000000>; + reg = <0>; + width = <240>; + height = <240>; + x-offset = <0>; + y-offset = <0>; + vcom = <0x19>; + gctrl = <0x35>; + vrhs = <0x12>; + vdvs = <0x20>; + mdac = <0x00>; + gamma = <0x01>; + colmod = <0x05>; + lcm = <0x2c>; + porch-param = [0c 0c 00 33 33]; + cmd2en-param = [5a 69 02 01]; + pwctrl1-param = [a4 a1]; + pvgam-param = [D0 04 0D 11 13 2B 3F 54 4C 18 0D 0B 1F 23]; + nvgam-param = [D0 04 0C 11 13 2C 3F 44 51 2F 1F 1F 20 23]; + ram-param = [00 F0]; + rgb-param = [CD 08 14]; + mipi-mode = ; + }; + }; }; &arduino_spi { status = "okay"; cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */ - - st7789v_st7789v_waveshare_240x240: st7789v@0 { - compatible = "sitronix,st7789v"; - spi-max-frequency = <20000000>; - reg = <0>; - cmd-data-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>; /* D9 */ - reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */ - width = <240>; - height = <240>; - x-offset = <0>; - y-offset = <0>; - vcom = <0x19>; - gctrl = <0x35>; - vrhs = <0x12>; - vdvs = <0x20>; - mdac = <0x00>; - gamma = <0x01>; - colmod = <0x05>; - lcm = <0x2c>; - porch-param = [0c 0c 00 33 33]; - cmd2en-param = [5a 69 02 01]; - pwctrl1-param = [a4 a1]; - pvgam-param = [D0 04 0D 11 13 2B 3F 54 4C 18 0D 0B 1F 23]; - nvgam-param = [D0 04 0C 11 13 2C 3F 44 51 2F 1F 1F 20 23]; - ram-param = [00 F0]; - rgb-param = [CD 08 14]; - }; }; diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_stm32h747xx_m7.conf b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_stm32h747xx_m7.conf index 6b946eca8f1..ecbb0543249 100644 --- a/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_stm32h747xx_m7.conf +++ b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_stm32h747xx_m7.conf @@ -2,5 +2,5 @@ # SPDX-License-Identifier: Apache-2.0 CONFIG_MEMC=y -CONFIG_STM32_LTDC_RGB888=y +CONFIG_STM32_LTDC_ARGB8888=y CONFIG_HEAP_MEM_POOL_SIZE=65536 diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/doc/index.rst b/boards/shields/st_b_lcd40_dsi1_mb1166/doc/index.rst index 4bc150e0c0f..2713d49a2e2 100644 --- a/boards/shields/st_b_lcd40_dsi1_mb1166/doc/index.rst +++ b/boards/shields/st_b_lcd40_dsi1_mb1166/doc/index.rst @@ -1,4 +1,4 @@ -.. _st_b_lcd40_dsi1_mb1166_shield: +.. _st_b_lcd40_dsi1_mb1166: ST B-LCD40-DSI1 ############### @@ -107,7 +107,7 @@ The shield can be used in any application by setting ``SHIELD`` to ``st_b_lcd40_dsi1_mb1166`` or ``st_b_lcd40_dsi1_mb1166_a09`` and adding the necessary device tree properties. -Set ``-DSHIELD="st_b_lcd40_dsi1_mb1166"`` when you invoke ``west build``. For example: +Set ``--shield "st_b_lcd40_dsi1_mb1166"`` when you invoke ``west build``. For example: .. zephyr-app-commands:: :zephyr-app: samples/drivers/display diff --git a/boards/shields/tcan4550evm/doc/index.rst b/boards/shields/tcan4550evm/doc/index.rst index 73e167dcc49..67cbdb851d6 100644 --- a/boards/shields/tcan4550evm/doc/index.rst +++ b/boards/shields/tcan4550evm/doc/index.rst @@ -53,7 +53,7 @@ Pin Assignments Programming *********** -Set ``-DSHIELD=tcan4550evm`` when you invoke ``west build``. For example: +Set ``--shield tcan4550evm`` when you invoke ``west build``. For example: .. zephyr-app-commands:: :zephyr-app: tests/drivers/can/api diff --git a/boards/shields/waveshare_epaper/Kconfig.defconfig b/boards/shields/waveshare_epaper/Kconfig.defconfig index 5f7f13a0b16..6087880f4f3 100644 --- a/boards/shields/waveshare_epaper/Kconfig.defconfig +++ b/boards/shields/waveshare_epaper/Kconfig.defconfig @@ -5,8 +5,7 @@ # SPDX-License-Identifier: Apache-2.0 # -if SHIELD_WAVESHARE_EPAPER_GDEH029A1 || SHIELD_WAVESHARE_EPAPER_GDEH0213B1 || SHIELD_WAVESHARE_EPAPER_GDEH0213B72 || SHIELD_WAVESHARE_EPAPER_GDEW075T7 || SHIELD_WAVESHARE_EPAPER_GDEH0154A07 || SHIELD_WAVESHARE_EPAPER_GDEW042T2 || SHIELD_WAVESHARE_EPAPER_GDEW042T2_P - +if SHIELD_WAVESHARE_EPAPER_GDEH029A1 || SHIELD_WAVESHARE_EPAPER_GDEH0213B1 || SHIELD_WAVESHARE_EPAPER_GDEH0213B72 || SHIELD_WAVESHARE_EPAPER_GDEW075T7 || SHIELD_WAVESHARE_EPAPER_GDEH0154A07 || SHIELD_WAVESHARE_EPAPER_GDEW042T2 || SHIELD_WAVESHARE_EPAPER_GDEW042T2_P || SHIELD_WAVESHARE_EPAPER_GDEY0213B74 if DISPLAY diff --git a/boards/shields/waveshare_epaper/Kconfig.shield b/boards/shields/waveshare_epaper/Kconfig.shield index 863059e5784..b3fe949cb3a 100644 --- a/boards/shields/waveshare_epaper/Kconfig.shield +++ b/boards/shields/waveshare_epaper/Kconfig.shield @@ -21,3 +21,6 @@ config SHIELD_WAVESHARE_EPAPER_GDEW042T2 config SHIELD_WAVESHARE_EPAPER_GDEW042T2_P def_bool $(shields_list_contains,waveshare_epaper_gdew042t2-p) + +config SHIELD_WAVESHARE_EPAPER_GDEY0213B74 + def_bool $(shields_list_contains,waveshare_epaper_gdey0213b74) diff --git a/boards/shields/waveshare_epaper/doc/index.rst b/boards/shields/waveshare_epaper/doc/index.rst index 876ba1d107e..2e96db4a139 100644 --- a/boards/shields/waveshare_epaper/doc/index.rst +++ b/boards/shields/waveshare_epaper/doc/index.rst @@ -1,4 +1,4 @@ -.. _waveshare_e_paper_raw_panel_shield: +.. _waveshare_epaper: WAVESHARE e-Paper Raw Panel Shield ################################## @@ -65,6 +65,9 @@ Current supported displays | Good Display | WFT0420CZ15 | UC8176 / | waveshare_epaper_gdew042t2 | | GDEW042T2 | | gd7965 | waveshare_epaper_gdew042t2-p | +--------------+-----------------+--------------+------------------------------+ +| Good Display | FPC-A002 | SSD1680 / | waveshare_epaper_gdey0213b74 | +| GDEY0213B74 | | ssd16xx | | ++--------------+-----------------+--------------+------------------------------+ Requirements diff --git a/boards/shields/waveshare_epaper/waveshare_epaper_gdeh0154a07.overlay b/boards/shields/waveshare_epaper/waveshare_epaper_gdeh0154a07.overlay index 7a4dc21f0b7..6a877a0b08d 100644 --- a/boards/shields/waveshare_epaper/waveshare_epaper_gdeh0154a07.overlay +++ b/boards/shields/waveshare_epaper/waveshare_epaper_gdeh0154a07.overlay @@ -10,27 +10,32 @@ chosen { zephyr,display = &ssd16xx_waveshare_epaper_gdeh0154a07; }; -}; -&arduino_spi { - ssd16xx_waveshare_epaper_gdeh0154a07: ssd16xxfb@0 { - compatible = "gooddisplay,gdeh0154a07", "solomon,ssd1681"; - spi-max-frequency = <4000000>; - reg = <0>; - width = <200>; - height = <200>; - dc-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>; /* D9 */ + mipi_dbi_waveshare_epaper_gdeh0154a07 { + compatible = "zephyr,mipi-dbi-spi"; + spi-dev = <&arduino_spi>; + dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */ reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */ - busy-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; /* D7 */ + #address-cells = <1>; + #size-cells = <0>; - tssv = <0x80>; + ssd16xx_waveshare_epaper_gdeh0154a07: ssd16xxfb@0 { + compatible = "gooddisplay,gdeh0154a07", "solomon,ssd1681"; + mipi-max-frequency = <4000000>; + reg = <0>; + width = <200>; + height = <200>; + busy-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; /* D7 */ - full { - border-waveform = <0x05>; - }; + tssv = <0x80>; + + full { + border-waveform = <0x05>; + }; - partial { - border-waveform = <0x3c>; + partial { + border-waveform = <0x3c>; + }; }; }; }; diff --git a/boards/shields/waveshare_epaper/waveshare_epaper_gdeh0213b1.overlay b/boards/shields/waveshare_epaper/waveshare_epaper_gdeh0213b1.overlay index d7c873df0c3..1936b48d16a 100644 --- a/boards/shields/waveshare_epaper/waveshare_epaper_gdeh0213b1.overlay +++ b/boards/shields/waveshare_epaper/waveshare_epaper_gdeh0213b1.overlay @@ -10,47 +10,52 @@ chosen { zephyr,display = &ssd16xx_waveshare_epaper_gdeh0213b1; }; -}; -&arduino_spi { - ssd16xx_waveshare_epaper_gdeh0213b1: ssd16xxfb@0 { - compatible = "gooddisplay,gdeh0213b1", "solomon,ssd1673"; - spi-max-frequency = <4000000>; - reg = <0>; - width = <250>; - height = <120>; - dc-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>; /* D9 */ + mipi_dbi_waveshare_epaper_gdeh0213b1 { + compatible = "zephyr,mipi-dbi-spi"; + spi-dev = <&arduino_spi>; + dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */ reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */ - busy-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; /* D7 */ + #address-cells = <1>; + #size-cells = <0>; - full { - gdv = [10 0a]; - sdv = [19]; - vcom = <0xa8>; - border-waveform = <0x71>; - dummy-line = <0x1a>; - gate-line-width = <0x08>; - lut = [ - 22 55 AA 55 AA 55 AA 11 - 00 00 00 00 00 00 00 00 - 1E 1E 1E 1E 1E 1E 1E 1E - 01 00 00 00 00 - ]; - }; + ssd16xx_waveshare_epaper_gdeh0213b1: ssd16xxfb@0 { + compatible = "gooddisplay,gdeh0213b1", "solomon,ssd1673"; + mipi-max-frequency = <4000000>; + reg = <0>; + width = <250>; + height = <120>; + busy-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; /* D7 */ + + full { + gdv = [10 0a]; + sdv = [19]; + vcom = <0xa8>; + border-waveform = <0x71>; + dummy-line = <0x1a>; + gate-line-width = <0x08>; + lut = [ + 22 55 AA 55 AA 55 AA 11 + 00 00 00 00 00 00 00 00 + 1E 1E 1E 1E 1E 1E 1E 1E + 01 00 00 00 00 + ]; + }; - partial { - gdv = [10 0a]; - sdv = [19]; - vcom = <0xa8>; - border-waveform = <0x71>; - dummy-line = <0x1a>; - gate-line-width = <0x08>; - lut = [ - 18 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 0F 01 00 00 00 00 00 00 - 00 00 00 00 00 - ]; + partial { + gdv = [10 0a]; + sdv = [19]; + vcom = <0xa8>; + border-waveform = <0x71>; + dummy-line = <0x1a>; + gate-line-width = <0x08>; + lut = [ + 18 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 0F 01 00 00 00 00 00 00 + 00 00 00 00 00 + ]; + }; }; }; }; diff --git a/boards/shields/waveshare_epaper/waveshare_epaper_gdeh0213b72.overlay b/boards/shields/waveshare_epaper/waveshare_epaper_gdeh0213b72.overlay index 37954c57cf1..362e0905079 100644 --- a/boards/shields/waveshare_epaper/waveshare_epaper_gdeh0213b72.overlay +++ b/boards/shields/waveshare_epaper/waveshare_epaper_gdeh0213b72.overlay @@ -10,63 +10,68 @@ chosen { zephyr,display = &ssd16xx_waveshare_epaper_gdeh0213b72; }; -}; -&arduino_spi { - ssd16xx_waveshare_epaper_gdeh0213b72: ssd16xxfb@0 { - compatible = "gooddisplay,gdeh0213b72", "solomon,ssd1675a"; - spi-max-frequency = <4000000>; - reg = <0>; - width = <250>; - height = <120>; - dc-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>; /* D9 */ + mipi_dbi_waveshare_epaper_gdeh0213b72 { + compatible = "zephyr,mipi-dbi-spi"; + spi-dev = <&arduino_spi>; + dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */ reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */ - busy-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; /* D7 */ + #address-cells = <1>; + #size-cells = <0>; - full { - gdv = [15]; - sdv = [41 a8 32]; - vcom = <0x55>; - border-waveform = <0x03>; - dummy-line = <0x30>; - gate-line-width = <0x0a>; - lut = [ - 80 60 40 00 00 00 00 - 10 60 20 00 00 00 00 - 80 60 40 00 00 00 00 - 10 60 20 00 00 00 00 - 00 00 00 00 00 00 00 - 03 03 00 00 02 - 09 09 00 00 02 - 03 03 00 00 02 - 00 00 00 00 00 - 00 00 00 00 00 - 00 00 00 00 00 - 00 00 00 00 00 - ]; - }; + ssd16xx_waveshare_epaper_gdeh0213b72: ssd16xxfb@0 { + compatible = "gooddisplay,gdeh0213b72", "solomon,ssd1675a"; + mipi-max-frequency = <4000000>; + reg = <0>; + width = <250>; + height = <120>; + busy-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; /* D7 */ + + full { + gdv = [15]; + sdv = [41 a8 32]; + vcom = <0x55>; + border-waveform = <0x03>; + dummy-line = <0x30>; + gate-line-width = <0x0a>; + lut = [ + 80 60 40 00 00 00 00 + 10 60 20 00 00 00 00 + 80 60 40 00 00 00 00 + 10 60 20 00 00 00 00 + 00 00 00 00 00 00 00 + 03 03 00 00 02 + 09 09 00 00 02 + 03 03 00 00 02 + 00 00 00 00 00 + 00 00 00 00 00 + 00 00 00 00 00 + 00 00 00 00 00 + ]; + }; - partial { - gdv = [15]; - sdv = [41 a8 32]; - vcom = <0x26>; - border-waveform = <0x01>; - dummy-line = <0x30>; - gate-line-width = <0x0a>; - lut = [ - 00 00 00 00 00 00 00 - 80 00 00 00 00 00 00 - 40 00 00 00 00 00 00 - 80 00 00 00 00 00 00 - 00 00 00 00 00 00 00 - 0A 00 00 00 04 - 00 00 00 00 00 - 00 00 00 00 00 - 00 00 00 00 00 - 00 00 00 00 00 - 00 00 00 00 00 - 00 00 00 00 00 - ]; + partial { + gdv = [15]; + sdv = [41 a8 32]; + vcom = <0x26>; + border-waveform = <0x01>; + dummy-line = <0x30>; + gate-line-width = <0x0a>; + lut = [ + 00 00 00 00 00 00 00 + 80 00 00 00 00 00 00 + 40 00 00 00 00 00 00 + 80 00 00 00 00 00 00 + 00 00 00 00 00 00 00 + 0A 00 00 00 04 + 00 00 00 00 00 + 00 00 00 00 00 + 00 00 00 00 00 + 00 00 00 00 00 + 00 00 00 00 00 + 00 00 00 00 00 + ]; + }; }; }; }; diff --git a/boards/shields/waveshare_epaper/waveshare_epaper_gdeh029a1.overlay b/boards/shields/waveshare_epaper/waveshare_epaper_gdeh029a1.overlay index 0b1b6f4d14f..734786fcc80 100644 --- a/boards/shields/waveshare_epaper/waveshare_epaper_gdeh029a1.overlay +++ b/boards/shields/waveshare_epaper/waveshare_epaper_gdeh029a1.overlay @@ -10,45 +10,50 @@ chosen { zephyr,display = &ssd16xx_waveshare_epaper_gdeh029a1; }; -}; -&arduino_spi { - ssd16xx_waveshare_epaper_gdeh029a1: ssd16xxfb@0 { - compatible = "gooddisplay,gdeh029a1", "solomon,ssd1608"; - spi-max-frequency = <4000000>; - reg = <0>; - width = <296>; - height = <128>; - dc-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>; /* D9 */ + mipi_dbi_waveshare_epaper_gdeh029a1 { + compatible = "zephyr,mipi-dbi-spi"; + spi-dev = <&arduino_spi>; + dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */ reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */ - busy-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; /* D7 */ + #address-cells = <1>; + #size-cells = <0>; - softstart = [d7 d6 9d]; + ssd16xx_waveshare_epaper_gdeh029a1: ssd16xxfb@0 { + compatible = "gooddisplay,gdeh029a1", "solomon,ssd1608"; + mipi-max-frequency = <4000000>; + reg = <0>; + width = <296>; + height = <128>; + busy-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; /* D7 */ - full { - vcom = <0x9a>; - border-waveform = <0x33>; - dummy-line = <0x1a>; - gate-line-width = <0x08>; - lut = [ - 50 AA 55 AA 11 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 FF FF 1F 00 - 00 00 00 00 00 00 - ]; - }; + softstart = [d7 d6 9d]; + + full { + vcom = <0x9a>; + border-waveform = <0x33>; + dummy-line = <0x1a>; + gate-line-width = <0x08>; + lut = [ + 50 AA 55 AA 11 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 FF FF 1F 00 + 00 00 00 00 00 00 + ]; + }; - partial { - vcom = <0xa8>; - border-waveform = <0x01>; - dummy-line = <0x1a>; - gate-line-width = <0x08>; - lut = [ - 10 18 18 08 18 18 08 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 13 14 44 12 - 00 00 00 00 00 00 - ]; + partial { + vcom = <0xa8>; + border-waveform = <0x01>; + dummy-line = <0x1a>; + gate-line-width = <0x08>; + lut = [ + 10 18 18 08 18 18 08 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 13 14 44 12 + 00 00 00 00 00 00 + ]; + }; }; }; }; diff --git a/boards/shields/waveshare_epaper/waveshare_epaper_gdew042t2-p.overlay b/boards/shields/waveshare_epaper/waveshare_epaper_gdew042t2-p.overlay index 35f96d940e2..2a1024ece0d 100644 --- a/boards/shields/waveshare_epaper/waveshare_epaper_gdew042t2-p.overlay +++ b/boards/shields/waveshare_epaper/waveshare_epaper_gdew042t2-p.overlay @@ -8,87 +8,93 @@ / { chosen { - zephyr,display = &uc8176_waveshare_epaper_gdew042t2-p; + zephyr,display = &uc8176_waveshare_epaper_gdew042t2_p; }; -}; -&arduino_spi { - /* - * GoodDisplay GDEW042T2 with fast partial refresh. Based on - * configuration from GoodDisplay's Arduino example. - */ - uc8176_waveshare_epaper_gdew042t2-p: uc8176@0 { - compatible = "gooddisplay,gdew042t2", "ultrachip,uc8176"; - spi-max-frequency = <4000000>; - reg = <0>; - width = <400>; - height = <300>; - dc-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>; /* D9 */ + mipi_dbi_waveshare_epaper_gdew042t2-p { + compatible = "zephyr,mipi-dbi-spi"; + spi-dev = <&arduino_spi>; + dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */ reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */ - busy-gpios = <&arduino_header 13 GPIO_ACTIVE_LOW>; /* D7 */ + write-only; + #address-cells = <1>; + #size-cells = <0>; - softstart = [ 17 17 17 ]; + /* + * GoodDisplay GDEW042T2 with fast partial refresh. Based on + * configuration from GoodDisplay's Arduino example. + */ + uc8176_waveshare_epaper_gdew042t2_p: uc8176@0 { + compatible = "gooddisplay,gdew042t2", "ultrachip,uc8176"; + mipi-max-frequency = <4000000>; + reg = <0>; + width = <400>; + height = <300>; + busy-gpios = <&arduino_header 13 GPIO_ACTIVE_LOW>; /* D7 */ - full { - cdi = <0x07>; - }; + softstart = [ 17 17 17 ]; + + full { + cdi = <0x07>; + }; - partial { - pwr = [ 03 02 2b 2b ]; - cdi = <0x07>; - pll = <0x3c>; - vdcs = <0x08>; + partial { + pwr = [ 03 02 2b 2b ]; + cdi = <0x07>; + pll = <0x3c>; + vdcs = <0x08>; - lutc = [ - 00 01 0E 00 00 01 - 00 00 00 00 00 00 - 00 00 00 00 00 00 - 00 00 00 00 00 00 - 00 00 00 00 00 00 - 00 00 00 00 00 00 - 00 00 00 00 00 00 - 00 00 - ]; + lutc = [ + 00 01 0E 00 00 01 + 00 00 00 00 00 00 + 00 00 00 00 00 00 + 00 00 00 00 00 00 + 00 00 00 00 00 00 + 00 00 00 00 00 00 + 00 00 00 00 00 00 + 00 00 + ]; - lutww = [ - 00 01 0E 00 00 01 - 00 00 00 00 00 00 - 00 00 00 00 00 00 - 00 00 00 00 00 00 - 00 00 00 00 00 00 - 00 00 00 00 00 00 - 00 00 00 00 00 00 - ]; + lutww = [ + 00 01 0E 00 00 01 + 00 00 00 00 00 00 + 00 00 00 00 00 00 + 00 00 00 00 00 00 + 00 00 00 00 00 00 + 00 00 00 00 00 00 + 00 00 00 00 00 00 + ]; - lutkw = [ - 20 01 0E 00 00 01 - 00 00 00 00 00 00 - 00 00 00 00 00 00 - 00 00 00 00 00 00 - 00 00 00 00 00 00 - 00 00 00 00 00 00 - 00 00 00 00 00 00 - ]; + lutkw = [ + 20 01 0E 00 00 01 + 00 00 00 00 00 00 + 00 00 00 00 00 00 + 00 00 00 00 00 00 + 00 00 00 00 00 00 + 00 00 00 00 00 00 + 00 00 00 00 00 00 + ]; - lutwk = [ - 10 01 0E 00 00 01 - 00 00 00 00 00 00 - 00 00 00 00 00 00 - 00 00 00 00 00 00 - 00 00 00 00 00 00 - 00 00 00 00 00 00 - 00 00 00 00 00 00 - ]; + lutwk = [ + 10 01 0E 00 00 01 + 00 00 00 00 00 00 + 00 00 00 00 00 00 + 00 00 00 00 00 00 + 00 00 00 00 00 00 + 00 00 00 00 00 00 + 00 00 00 00 00 00 + ]; - lutkk = [ - 00 01 0E 00 00 01 - 00 00 00 00 00 00 - 00 00 00 00 00 00 - 00 00 00 00 00 00 - 00 00 00 00 00 00 - 00 00 00 00 00 00 - 00 00 00 00 00 00 - ]; + lutkk = [ + 00 01 0E 00 00 01 + 00 00 00 00 00 00 + 00 00 00 00 00 00 + 00 00 00 00 00 00 + 00 00 00 00 00 00 + 00 00 00 00 00 00 + 00 00 00 00 00 00 + ]; + }; }; }; }; diff --git a/boards/shields/waveshare_epaper/waveshare_epaper_gdew042t2.overlay b/boards/shields/waveshare_epaper/waveshare_epaper_gdew042t2.overlay index 0b8f994c97b..035110ea5dc 100644 --- a/boards/shields/waveshare_epaper/waveshare_epaper_gdew042t2.overlay +++ b/boards/shields/waveshare_epaper/waveshare_epaper_gdew042t2.overlay @@ -9,25 +9,31 @@ chosen { zephyr,display = &uc8176_waveshare_epaper_gdew042t2; }; -}; -&arduino_spi { - uc8176_waveshare_epaper_gdew042t2: uc8176@0 { - compatible = "gooddisplay,gdew042t2", "ultrachip,uc8176"; - spi-max-frequency = <4000000>; - reg = <0>; - width = <400>; - height = <300>; - dc-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>; /* D9 */ + mipi_dbi_waveshare_epaper_gdew042t2 { + compatible = "zephyr,mipi-dbi-spi"; + spi-dev = <&arduino_spi>; + dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */ reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */ - busy-gpios = <&arduino_header 13 GPIO_ACTIVE_LOW>; /* D7 */ + write-only; + #address-cells = <1>; + #size-cells = <0>; + + uc8176_waveshare_epaper_gdew042t2: uc8176@0 { + compatible = "gooddisplay,gdew042t2", "ultrachip,uc8176"; + mipi-max-frequency = <4000000>; + reg = <0>; + width = <400>; + height = <300>; + busy-gpios = <&arduino_header 13 GPIO_ACTIVE_LOW>; /* D7 */ - softstart = [17 17 17]; + softstart = [17 17 17]; - full { - pwr = [03 00 26 26 09]; - cdi = <0xd7>; - tcon = <0x22>; + full { + pwr = [03 00 26 26 09]; + cdi = <0xd7>; + tcon = <0x22>; + }; }; }; }; diff --git a/boards/shields/waveshare_epaper/waveshare_epaper_gdew075t7.overlay b/boards/shields/waveshare_epaper/waveshare_epaper_gdew075t7.overlay index cccee41faaa..8c8cbd9d636 100644 --- a/boards/shields/waveshare_epaper/waveshare_epaper_gdew075t7.overlay +++ b/boards/shields/waveshare_epaper/waveshare_epaper_gdew075t7.overlay @@ -10,25 +10,31 @@ chosen { zephyr,display = &uc8179_waveshare_epaper_gdew075t7; }; -}; -&arduino_spi { - uc8179_waveshare_epaper_gdew075t7: uc8179@0 { - compatible = "gooddisplay,gdew075t7", "ultrachip,uc8179"; - spi-max-frequency = <4000000>; - reg = <0>; - width = <800>; - height = <480>; - dc-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>; /* D9 */ + mipi_dbi_waveshare_epaper_gdew075t7 { + compatible = "zephyr,mipi-dbi-spi"; + spi-dev = <&arduino_spi>; + dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */ reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */ - busy-gpios = <&arduino_header 13 GPIO_ACTIVE_LOW>; /* D7 */ + write-only; + #address-cells = <1>; + #size-cells = <0>; + + uc8179_waveshare_epaper_gdew075t7: uc8179@0 { + compatible = "gooddisplay,gdew075t7", "ultrachip,uc8179"; + mipi-max-frequency = <4000000>; + reg = <0>; + width = <800>; + height = <480>; + busy-gpios = <&arduino_header 13 GPIO_ACTIVE_LOW>; /* D7 */ - softstart = [17 17 17 17]; + softstart = [17 17 17 17]; - full { - pwr = [07 07 3f 3f]; - cdi = <07>; - tcon = <0x22>; + full { + pwr = [07 07 3f 3f]; + cdi = <07>; + tcon = <0x22>; + }; }; }; }; diff --git a/boards/shields/waveshare_epaper/waveshare_epaper_gdey0213b74.overlay b/boards/shields/waveshare_epaper/waveshare_epaper_gdey0213b74.overlay new file mode 100644 index 00000000000..8299b724274 --- /dev/null +++ b/boards/shields/waveshare_epaper/waveshare_epaper_gdey0213b74.overlay @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2024, Kelly Helmut Lord + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "waveshare_epaper_common.dtsi" + +/ { + chosen { + zephyr,display = &ssd16xx_waveshare_epaper_gdey0213b74; + }; + + mipi_dbi_waveshare_epaper_gdey0213b74 { + compatible = "zephyr,mipi-dbi-spi"; + spi-dev = <&arduino_spi>; + dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */ + reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */ + #address-cells = <1>; + #size-cells = <0>; + + ssd16xx_waveshare_epaper_gdey0213b74: ssd16xxfb@0 { + compatible = "gooddisplay,gdey0213b74", "solomon,ssd1680"; + mipi-max-frequency = <4000000>; + reg = <0>; + width = <250>; + height = <122>; + busy-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; /* D7 */ + + tssv = <0x80>; + + full { + border-waveform = <0x05>; + }; + + partial { + border-waveform = <0x3c>; + }; + }; + }; +}; diff --git a/boards/shields/waveshare_ups/boards/rpi_pico.overlay b/boards/shields/waveshare_ups/boards/rpi_pico.overlay index e8fe6525af1..f758012a7cb 100644 --- a/boards/shields/waveshare_ups/boards/rpi_pico.overlay +++ b/boards/shields/waveshare_ups/boards/rpi_pico.overlay @@ -6,13 +6,13 @@ &pinctrl { - i2c1_default: i2c1_default { - group1 { - bias-pull-up; - }; - }; + i2c1_default: i2c1_default { + group1 { + bias-pull-up; + }; + }; }; &pico_i2c1 { - status = "okay"; + status = "okay"; }; diff --git a/boards/shields/waveshare_ups/doc/index.rst b/boards/shields/waveshare_ups/doc/index.rst index 4fc35403b46..49493db298f 100644 --- a/boards/shields/waveshare_ups/doc/index.rst +++ b/boards/shields/waveshare_ups/doc/index.rst @@ -121,7 +121,7 @@ For more information about the Waveshare Pico UPS-B: Programming *********** -Set ``-DSHIELD=waveshare_pico_ups_b`` when you invoke ``west build`` or ``cmake`` in your Zephyr application. For +Set ``--shield waveshare_pico_ups_b`` when you invoke ``west build`` or ``cmake`` in your Zephyr application. For example: .. zephyr-app-commands:: diff --git a/boards/shields/waveshare_ups/waveshare_pico_ups_b.overlay b/boards/shields/waveshare_ups/waveshare_pico_ups_b.overlay index 381bce67c74..341927d1dd1 100644 --- a/boards/shields/waveshare_ups/waveshare_pico_ups_b.overlay +++ b/boards/shields/waveshare_ups/waveshare_pico_ups_b.overlay @@ -10,10 +10,10 @@ compatible = "ti,ina219"; reg = <0x43>; brng = <1>; - pg = <3>; - sadc = <12>; - badc = <12>; - shunt-milliohm = <100>; - lsb-microamp = <20>; + pg = <3>; + sadc = <12>; + badc = <12>; + shunt-milliohm = <100>; + lsb-microamp = <20>; }; }; diff --git a/boards/shields/x_nucleo_53l0a1/doc/index.rst b/boards/shields/x_nucleo_53l0a1/doc/index.rst index 75f1a76dbcc..1055a89818a 100644 --- a/boards/shields/x_nucleo_53l0a1/doc/index.rst +++ b/boards/shields/x_nucleo_53l0a1/doc/index.rst @@ -58,7 +58,7 @@ External links Samples ******* -The sample :ref:`vl53l0x` demonstrates how to use the ranging sensor VL53L0X +The sample :zephyr:code-sample:`vl53l0x` demonstrates how to use the ranging sensor VL53L0X using the center sensor only. The sample :zephyr:code-sample:`x-nucleo-53l0a1` sample demonstrates how to use the three @@ -67,7 +67,7 @@ sensors (soldered + 2 satellites) and the 7 segments display. Programming *********** -Set ``-DSHIELD=x_nucleo_53l0a1`` when you invoke ``west build``. For example: +Set ``--shield x_nucleo_53l0a1`` when you invoke ``west build``. For example: .. zephyr-app-commands:: :zephyr-app: samples/sensor/vl53l0x diff --git a/boards/shields/x_nucleo_bnrg2a1/doc/index.rst b/boards/shields/x_nucleo_bnrg2a1/doc/index.rst index ddc9cf83819..411c4982818 100644 --- a/boards/shields/x_nucleo_bnrg2a1/doc/index.rst +++ b/boards/shields/x_nucleo_bnrg2a1/doc/index.rst @@ -1,4 +1,4 @@ -.. _x-nucleo-bnrg2a1: +.. _x_nucleo_bnrg2a1: X-NUCLEO-BNRG2A1: BLE expansion board ##################################### @@ -64,11 +64,11 @@ Programming You can use the X-NUCLEO-BNRG2A1 as a Bluetooth Low-Energy controller shield with an SPI host controller interface (HCI-SPI). Activate the presence -of the shield for the project build by adding the ``-DSHIELD`` arg to the +of the shield for the project build by adding the ``--shield`` arg to the build command: .. zephyr-app-commands:: - :zephyr-app: your_app + :app: your_app :board: your_board_name :shield: x_nucleo_bnrg2a1 :goals: build diff --git a/boards/shields/x_nucleo_bnrg2a1/x_nucleo_bnrg2a1.overlay b/boards/shields/x_nucleo_bnrg2a1/x_nucleo_bnrg2a1.overlay index 535373ea307..14f9a1548ba 100644 --- a/boards/shields/x_nucleo_bnrg2a1/x_nucleo_bnrg2a1.overlay +++ b/boards/shields/x_nucleo_bnrg2a1/x_nucleo_bnrg2a1.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { +/ { chosen { zephyr,bt-hci = &hci_spi; }; diff --git a/boards/shields/x_nucleo_eeprma2/doc/index.rst b/boards/shields/x_nucleo_eeprma2/doc/index.rst index 248260b3657..50613fb180c 100644 --- a/boards/shields/x_nucleo_eeprma2/doc/index.rst +++ b/boards/shields/x_nucleo_eeprma2/doc/index.rst @@ -58,7 +58,7 @@ which can be overwritten to use the other EEPROM devices instead. Programming *********** -Set ``-DSHIELD=x_nucleo_eeprma2`` when you invoke ``west build``. For example: +Set ``--shield x_nucleo_eeprma2`` when you invoke ``west build``. For example: .. zephyr-app-commands:: :zephyr-app: samples/drivers/eeprom/ diff --git a/boards/shields/x_nucleo_eeprma2/x_nucleo_eeprma2.overlay b/boards/shields/x_nucleo_eeprma2/x_nucleo_eeprma2.overlay index a1c7c6813dc..84f1cda1a3c 100644 --- a/boards/shields/x_nucleo_eeprma2/x_nucleo_eeprma2.overlay +++ b/boards/shields/x_nucleo_eeprma2/x_nucleo_eeprma2.overlay @@ -20,7 +20,7 @@ eeprom0_x_nucleo_eeprma2: eeprom@54 { /* M24C02-FMC6TG aka U1 (2 kbit eeprom in DFN8 package) */ - compatible = "st,m24xxx", "atmel,at24"; + compatible = "st,m24c02", "st,m24xxx", "atmel,at24"; reg = <0x54>; size = <256>; pagesize = <16>; @@ -33,7 +33,7 @@ eeprom1_x_nucleo_eeprma2: eeprom@55 { /* M24256-DFDW6TP aka U2 (256 kbit eeprom in TSSOP package) */ - compatible = "st,m24xxx", "atmel,at24"; + compatible = "st,m24256", "st,m24xxx", "atmel,at24"; reg = <0x55>; size = ; pagesize = <64>; @@ -46,7 +46,7 @@ eeprom2_x_nucleo_eeprma2: eeprom@56 { /* M24M01-DFMN6TP aka U3 (1 Mbit eeprom in SO8N package) */ - compatible = "st,m24xxx", "atmel,at24"; + compatible = "st,m24m01", "st,m24xxx", "atmel,at24"; reg = <0x56>; size = ; pagesize = <256>; @@ -82,7 +82,7 @@ eeprom4_x_nucleo_eeprma2: eeprom_m95040@0 { /* M95040-RMC6TG aka U5 (4 kbit eeprom in DFN8 package) */ - compatible = "st,m95xxx", "atmel,at25"; + compatible = "st,m95040", "st,m95xxx", "atmel,at25"; reg = <0x00>; size = <512>; pagesize = <16>; @@ -96,7 +96,7 @@ eeprom5_x_nucleo_eeprma2: eeprom_m95256@1 { /* M95256-DFDW6TP aka U6 (256 kbit eeprom in TSSOP package) */ - compatible = "st,m95xxx", "atmel,at25"; + compatible = "st,m95256", "st,m95xxx", "atmel,at25"; reg = <0x01>; size = ; pagesize = <64>; @@ -110,7 +110,7 @@ eeprom6_x_nucleo_eeprma2: eeprom_m95m04@2 { /* M95M04-DRMN6TP aka U7 (4 Mbit eeprom in SON8 package) */ - compatible = "st,m95xxx", "atmel,at25"; + compatible = "st,m95m04", "st,m95xxx", "atmel,at25"; reg = <0x02>; size = ; pagesize = <512>; diff --git a/boards/shields/x_nucleo_idb05a1/doc/index.rst b/boards/shields/x_nucleo_idb05a1/doc/index.rst index d2c6f006f77..57e23ae92e8 100644 --- a/boards/shields/x_nucleo_idb05a1/doc/index.rst +++ b/boards/shields/x_nucleo_idb05a1/doc/index.rst @@ -74,11 +74,11 @@ Programming You can use the X-NUCLEO-IDB05A1 as a Bluetooth Low-Energy controller shield with an SPI host controller interface (HCI-SPI). Activate the presence -of the shield for the project build by adding the ``-DSHIELD`` arg to the +of the shield for the project build by adding the ``--shield`` arg to the build command: .. zephyr-app-commands:: - :zephyr-app: your_app + :app: your_app :board: your_board_name :shield: x_nucleo_idb05a1 :goals: build diff --git a/boards/shields/x_nucleo_idb05a1/x_nucleo_idb05a1.overlay b/boards/shields/x_nucleo_idb05a1/x_nucleo_idb05a1.overlay index f508f0b26a0..9991e70665d 100644 --- a/boards/shields/x_nucleo_idb05a1/x_nucleo_idb05a1.overlay +++ b/boards/shields/x_nucleo_idb05a1/x_nucleo_idb05a1.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { +/ { chosen { zephyr,bt-hci = &spbtle_rf_x_nucleo_idb05a1; }; diff --git a/boards/shields/x_nucleo_wb05kn1/Kconfig.defconfig b/boards/shields/x_nucleo_wb05kn1/Kconfig.defconfig new file mode 100644 index 00000000000..9ca34477181 --- /dev/null +++ b/boards/shields/x_nucleo_wb05kn1/Kconfig.defconfig @@ -0,0 +1,33 @@ +# Copyright (c) 2024 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +if SHIELD_X_NUCLEO_WB05KN1_UART || SHIELD_X_NUCLEO_WB05KN1_SPI + +if BT + +config SPI + default y + depends on SHIELD_X_NUCLEO_WB05KN1_SPI + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +config BT_SPI + default y + depends on DT_HAS_ST_HCI_SPI_V2_ENABLED + +config BT_H4 + default y + depends on DT_HAS_ZEPHYR_BT_HCI_UART_ENABLED + +config BT_BLUENRG_ACI + default y + +# Disable Flow control +config BT_HCI_ACL_FLOW_CONTROL + default n + +endif # BT + +endif # SHIELD_X_NUCLEO_WB05KN1_UART || SHIELD_X_NUCLEO_WB05KN1_SPI diff --git a/boards/shields/x_nucleo_wb05kn1/Kconfig.shield b/boards/shields/x_nucleo_wb05kn1/Kconfig.shield new file mode 100644 index 00000000000..2beed10e746 --- /dev/null +++ b/boards/shields/x_nucleo_wb05kn1/Kconfig.shield @@ -0,0 +1,8 @@ +# Copyright (c) 2024 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_X_NUCLEO_WB05KN1_UART + def_bool $(shields_list_contains,x_nucleo_wb05kn1_uart) + +config SHIELD_X_NUCLEO_WB05KN1_SPI + def_bool $(shields_list_contains,x_nucleo_wb05kn1_spi) diff --git a/boards/shields/x_nucleo_wb05kn1/boards/nucleo_h563zi.overlay b/boards/shields/x_nucleo_wb05kn1/boards/nucleo_h563zi.overlay new file mode 100644 index 00000000000..3c16686fd63 --- /dev/null +++ b/boards/shields/x_nucleo_wb05kn1/boards/nucleo_h563zi.overlay @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&spi1_sck_pa5 { + /delete-property/ bias-pull-down; + bias-pull-up; +}; + +&spi1_miso_pg9 { + slew-rate = "high-speed"; +}; + +&spi1_mosi_pb5 { + slew-rate = "high-speed"; +}; + +/ { + chosen { + zephyr,bt-c2h-uart = &usart3; + }; +}; diff --git a/boards/shields/x_nucleo_wb05kn1/boards/nucleo_u575zi_q.overlay b/boards/shields/x_nucleo_wb05kn1/boards/nucleo_u575zi_q.overlay new file mode 100644 index 00000000000..f6ff77a52c7 --- /dev/null +++ b/boards/shields/x_nucleo_wb05kn1/boards/nucleo_u575zi_q.overlay @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&spi1_sck_pa5 { + /delete-property/ bias-pull-down; + bias-pull-up; +}; + +&spi1_miso_pa6 { + slew-rate = "high-speed"; +}; + +&spi1_mosi_pa7 { + slew-rate = "high-speed"; +}; + +&arduino_spi { + pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>; +}; + +/ { + chosen { + zephyr,bt-c2h-uart = &usart1; + }; +}; diff --git a/boards/shields/x_nucleo_wb05kn1/doc/img/x-nucleo-wb05kn1.webp b/boards/shields/x_nucleo_wb05kn1/doc/img/x-nucleo-wb05kn1.webp new file mode 100644 index 00000000000..a9e58836e5c Binary files /dev/null and b/boards/shields/x_nucleo_wb05kn1/doc/img/x-nucleo-wb05kn1.webp differ diff --git a/boards/shields/x_nucleo_wb05kn1/doc/index.rst b/boards/shields/x_nucleo_wb05kn1/doc/index.rst new file mode 100644 index 00000000000..5247294f5f3 --- /dev/null +++ b/boards/shields/x_nucleo_wb05kn1/doc/index.rst @@ -0,0 +1,99 @@ +.. _x-nucleo-wb05kn1: + +X-NUCLEO-WB05KN1: BLE expansion board +##################################### + +Overview +******** +The X-NUCLEO-WB05KN1 is a Bluetooth Low Energy evaluation board which allows the +expansion of the STM32 Nucleo boards. +The RF module is FCC (FCC ID: YCP-MB203202) and IC certified (IC: 8976A-MB203202). + +The X-NUCLEO-WB05KN1 is compatible out of the box with the Arduino UNO R3 connector. +The board interfaces with the host microcontroller via UART (default) or SPI peripheral. + +.. image:: img/x-nucleo-wb05kn1.webp + :align: center + :alt: X-NUCLEO-WB05KN1 + +More information about the board can be found at the +`X-NUCLEO-WB05KN1 website`_. + +Configurations +************** + +X-NUCLEO-WB05KN1 can be utilized as a Bluetooth Low-Energy controller shield +with a UART or SPI host controller interface (HCI-UART/HCI-SPI). + +The UART default settings are: + +* Baudrate: 921600 bps +* 8 bits, no parity, 1 stop bit + ++----------+-----------------------+ +| UART Pin | Arduino Connector Pin | ++==========+=======================+ +| RX | D0 | ++----------+-----------------------+ +| TX | D1 | ++----------+-----------------------+ + +.. note:: + Please, bear in mind in order to use SPI interface you need to change the shield firmware + to ``DTM_SPI_WITH_UPDATER_CONTROLLER`` according to the SDK provided by ST at `X-CUBE-WB05N`_. + +IRQ and reset pins are also necessary in addition to SPI pins. + ++----------------+-----------------------+ +| SPI Config Pin | Arduino Connector Pin | ++================+=======================+ +| SCK | D13 | ++----------------+-----------------------+ +| MISO | D12 | ++----------------+-----------------------+ +| MOSI | D11 | ++----------------+-----------------------+ +| CS | D10 | ++----------------+-----------------------+ +| IRQ | A0 | ++----------------+-----------------------+ +| RESET | D7 | ++----------------+-----------------------+ + +More information about X-NUCLEO-WB05KN1 can be found here: + - `X-NUCLEO-WB05KN1 datasheet`_ + +Programming +*********** + +Activate the presence of the shield for the project build by adding the +``--shield x_nucleo_wb05kn1_uart`` or ``--shield x_nucleo_wb05kn1_spi`` when you invoke +``west build`` based on UART or SPI interface: + + .. zephyr-app-commands:: + :app: your_app + :board: your_board_name + :shield: x_nucleo_wb05kn1_uart + :goals: build + +or + + .. zephyr-app-commands:: + :app: your_app + :board: your_board_name + :shield: x_nucleo_wb05kn1_spi + :goals: build + +References +********** + +.. target-notes:: + +.. _X-NUCLEO-WB05KN1 website: + https://www.st.com/en/evaluation-tools/x-nucleo-wb05kn1.html + +.. _X-CUBE-WB05N: + https://www.st.com/en/embedded-software/x-cube-wb05n.html + +.. _X-NUCLEO-WB05KN1 datasheet: + https://www.st.com/resource/en/datasheet/stm32wb05kn.pdf diff --git a/boards/shields/x_nucleo_wb05kn1/x_nucleo_wb05kn1_spi.overlay b/boards/shields/x_nucleo_wb05kn1/x_nucleo_wb05kn1_spi.overlay new file mode 100644 index 00000000000..43cf2be0d2a --- /dev/null +++ b/boards/shields/x_nucleo_wb05kn1/x_nucleo_wb05kn1_spi.overlay @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,bt-hci = &hci_spi; + }; +}; + +&arduino_spi { + cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */ + + hci_spi: wb05n@0 { + compatible = "st,hci-spi-v2"; + reg = <0>; + reset-gpios = <&arduino_header 13 GPIO_ACTIVE_LOW>; /* D7 */ + irq-gpios = <&arduino_header 0 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* A0 */ + spi-cpol; /* CPOL=1 */ + spi-cpha; /* CPHA=1 */ + spi-hold-cs; + spi-max-frequency = ; /* the maximum supported SPI speed */ + reset-assert-duration-ms = <6>; + status = "okay"; + }; +}; diff --git a/boards/shields/x_nucleo_wb05kn1/x_nucleo_wb05kn1_uart.overlay b/boards/shields/x_nucleo_wb05kn1/x_nucleo_wb05kn1_uart.overlay new file mode 100644 index 00000000000..a0ae0ca0e8b --- /dev/null +++ b/boards/shields/x_nucleo_wb05kn1/x_nucleo_wb05kn1_uart.overlay @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,bt-hci = &bt_hci_uart; + }; +}; + +&arduino_serial { + current-speed = <921600>; + + bt_hci_uart: bt_hci_uart { + compatible = "zephyr,bt-hci-uart"; + status = "okay"; + }; +}; diff --git a/boards/sifive/hifive1/board.cmake b/boards/sifive/hifive1/board.cmake index 4f39320870c..93a6487d6c8 100644 --- a/boards/sifive/hifive1/board.cmake +++ b/boards/sifive/hifive1/board.cmake @@ -28,3 +28,8 @@ elseif("${BOARD_REVISION}" STREQUAL "B") board_runner_args(jlink "--tool-opt=-autoconnect 1") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) endif() + +set_ifndef(BOARD_SIM_RUNNER renode) +set_ifndef(BOARD_ROBOT_RUNNER renode-robot) +include(${ZEPHYR_BASE}/boards/common/renode.board.cmake) +include(${ZEPHYR_BASE}/boards/common/renode_robot.board.cmake) diff --git a/boards/sifive/hifive1/hifive1.yaml b/boards/sifive/hifive1/hifive1.yaml index 345768fb279..99463674324 100644 --- a/boards/sifive/hifive1/hifive1.yaml +++ b/boards/sifive/hifive1/hifive1.yaml @@ -19,4 +19,7 @@ testing: - bluetooth - flash - newlib + renode: + uart: sysbus.uart0 + resc: boards/sifive/hifive1/support/hifive1.resc vendor: sifive diff --git a/boards/sifive/hifive1/hifive1_fe310_B.overlay b/boards/sifive/hifive1/hifive1_fe310_B.overlay index e4afe2eef67..626a6a9c84e 100644 --- a/boards/sifive/hifive1/hifive1_fe310_B.overlay +++ b/boards/sifive/hifive1/hifive1_fe310_B.overlay @@ -14,6 +14,10 @@ current-speed = <115200>; }; +&spi0 { + reg = <0x10014000 0x1000 0x20010000 0x3c0900>; +}; + &spi2 { status = "okay"; pinctrl-0 = <&spi1_cs2_default diff --git a/boards/sifive/hifive1/support/hifive1.resc b/boards/sifive/hifive1/support/hifive1.resc index e9aaa1be62d..bbe5f26c8ad 100644 --- a/boards/sifive/hifive1/support/hifive1.resc +++ b/boards/sifive/hifive1/support/hifive1.resc @@ -23,6 +23,6 @@ showAnalyzer uart0 macro reset """ - sysbus LoadELF $bin + sysbus LoadELF $elf """ runMacro $reset diff --git a/boards/sifive/hifive_unleashed/hifive_unleashed.yaml b/boards/sifive/hifive_unleashed/hifive_unleashed.yaml index 749c62f4dca..1fb91e4c2e0 100644 --- a/boards/sifive/hifive_unleashed/hifive_unleashed.yaml +++ b/boards/sifive/hifive_unleashed/hifive_unleashed.yaml @@ -14,6 +14,9 @@ testing: - flash - newlib - crypto + renode: + uart: sysbus.uart0 + resc: boards/sifive/hifive_unleashed/support/hifive_unleashed.resc supported: - gpio - spi diff --git a/boards/sifive/hifive_unleashed/support/hifive_unleashed.resc b/boards/sifive/hifive_unleashed/support/hifive_unleashed.resc index a46d377d7c2..4d06081c5c9 100644 --- a/boards/sifive/hifive_unleashed/support/hifive_unleashed.resc +++ b/boards/sifive/hifive_unleashed/support/hifive_unleashed.resc @@ -20,6 +20,6 @@ showAnalyzer uart0 macro reset """ - sysbus LoadELF $bin + sysbus LoadELF $elf """ runMacro $reset diff --git a/boards/sifive/hifive_unmatched/hifive_unmatched.yaml b/boards/sifive/hifive_unmatched/hifive_unmatched.yaml index 0743a9cc0f5..6fbfb696ce1 100644 --- a/boards/sifive/hifive_unmatched/hifive_unmatched.yaml +++ b/boards/sifive/hifive_unmatched/hifive_unmatched.yaml @@ -11,6 +11,9 @@ testing: ignore_tags: - net - bluetooth + renode: + uart: sysbus.uart0 + resc: boards/sifive/hifive_unmatched/support/hifive_unmatched.resc supported: - spi - memc diff --git a/boards/sifive/hifive_unmatched/support/hifive_unmatched.resc b/boards/sifive/hifive_unmatched/support/hifive_unmatched.resc index 535bb06c69c..4d18a9b86dd 100644 --- a/boards/sifive/hifive_unmatched/support/hifive_unmatched.resc +++ b/boards/sifive/hifive_unmatched/support/hifive_unmatched.resc @@ -20,6 +20,6 @@ showAnalyzer uart0 macro reset """ - sysbus LoadELF $bin + sysbus LoadELF $elf """ runMacro $reset diff --git a/boards/silabs/dev_kits/index.rst b/boards/silabs/dev_kits/index.rst new file mode 100644 index 00000000000..4a0cf90ce33 --- /dev/null +++ b/boards/silabs/dev_kits/index.rst @@ -0,0 +1,10 @@ +.. _dev_kits: + +Dev Kits and Thunderboards +########################## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/silabs/dev_kits/sim3u1xx_dk/Kconfig.sim3u1xx_dk b/boards/silabs/dev_kits/sim3u1xx_dk/Kconfig.sim3u1xx_dk new file mode 100644 index 00000000000..e519114331b --- /dev/null +++ b/boards/silabs/dev_kits/sim3u1xx_dk/Kconfig.sim3u1xx_dk @@ -0,0 +1,6 @@ +# Copyright (c) 2024 GARDENA GmbH +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SIM3U1XX_DK + select SOC_PART_NUMBER_SIM3U167AGQ diff --git a/boards/silabs/dev_kits/sim3u1xx_dk/board.cmake b/boards/silabs/dev_kits/sim3u1xx_dk/board.cmake new file mode 100644 index 00000000000..60f466d5539 --- /dev/null +++ b/boards/silabs/dev_kits/sim3u1xx_dk/board.cmake @@ -0,0 +1,8 @@ +# Copyright (c) 2024 GARDENA GmbH +# +# SPDX-License-Identifier: Apache-2.0 + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) + +board_runner_args(jlink "--device=SiM3U167") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/silabs/dev_kits/sim3u1xx_dk/board.yml b/boards/silabs/dev_kits/sim3u1xx_dk/board.yml new file mode 100644 index 00000000000..c70d5420483 --- /dev/null +++ b/boards/silabs/dev_kits/sim3u1xx_dk/board.yml @@ -0,0 +1,9 @@ +# Copyright (c) 2024 GARDENA GmbH +# +# SPDX-License-Identifier: Apache-2.0 + +board: + name: sim3u1xx_dk + vendor: silabs + socs: + - name: sim3u167 diff --git a/boards/silabs/dev_kits/sim3u1xx_dk/doc/index.rst b/boards/silabs/dev_kits/sim3u1xx_dk/doc/index.rst new file mode 100644 index 00000000000..67284c4b782 --- /dev/null +++ b/boards/silabs/dev_kits/sim3u1xx_dk/doc/index.rst @@ -0,0 +1,132 @@ +.. _sim3u1xx_dk: + +Silicon Labs SiM3U1xx 32-bit MCU USB Development Kit +#################################################### + +Overview +******** + +This is a `development kit`_ that is used to develop software for the SiM3U1xx MCUs. + +.. figure:: sim3u1xx_dk.webp + :align: center + +Hardware +******** + +- Silicon Labs SiM3U167-B-GM SoC +- CPU core: ARM Cortex®-M3 +- Flash memory: 256 kB +- RAM: 32 kB +- IO: + + - 2x user LEDs + - 2x user push buttons + - 2x power LEDs + - Reset push button + - Potentiometer + - Analog terminals + - Capacitive sensing slider and button + - USB virtual COM port + +For more information about the SiM3U167 SoC and the SiM3U1xx board, refer to these documents: + +- Silicon Labs SiM3U1xx_ +- Silicon Labs SiM3U167-B-GM_ +- Silicon Labs SiM3U1xx-B-DK_ +- Silicon Labs SiM3U1xx-B-DK MCU card `user's guide`_ +- Silicon Labs SiM3U1xx and SiM3C1xx Revision B Errata_ + +.. _SiM3U1xx: https://www.silabs.com/mcu/32-bit-microcontrollers/precision32-sim3u1xx +.. _SiM3U167-B-GM: https://www.silabs.com/mcu/32-bit-microcontrollers/precision32-sim3u1xx/device.sim3u167-b-gm +.. _SiM3U1xx-B-DK: https://www.silabs.com/development-tools/mcu/32-bit/sim3u1xx-development-kit +.. _user's guide: https://www.silabs.com/documents/public/user-guides/UPMU-M3U160.pdf +.. _Errata: https://www.silabs.com/documents/public/errata/SiM3U1xx-SiM3C1xxErrata.pdf + +Supported Features +================== + +The board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | dma | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ + +Connections and IOs +=================== + ++--------+--------------------------+----------------------------------------------------+ +| Pin | Name | Note | ++========+==========================+====================================================+ +| PB1.12 | TX (O) | Serial connection to host via USB virtual COM port | ++--------+--------------------------+ | +| PB1.13 | RX (I) | | ++--------+--------------------------+ | +| PB1.14 | RTS (O) | | ++--------+--------------------------+ | +| PB1.15 | CTS (I) | | ++--------+--------------------------+----------------------------------------------------+ +| PB2.8 | Push button switch (SW2) | | ++--------+--------------------------+----------------------------------------------------+ +| PB2.9 | Push button switch (SW3) | | ++--------+--------------------------+----------------------------------------------------+ +| PB2.10 | Red LED (DS3) | | ++--------+--------------------------+----------------------------------------------------+ +| PB2.11 | Yellow LED (DS4) | | ++--------+--------------------------+----------------------------------------------------+ +| PB1.5 | Potentiometer | | ++--------+--------------------------+----------------------------------------------------+ +| PB2.12 | Potentiometer bias | | ++--------+--------------------------+----------------------------------------------------+ + +Programming and Debugging +************************* + +Flashing +======== + +The sample application :zephyr:code-sample:`hello_world` is used for this example. Build the Zephyr kernel and +application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sim3u1xx_dk + :goals: build + +Connect the sim3u1xx_dk to your host computer using both USB port and you should see a USB serial +connection. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you'll see the following message on the corresponding serial port +terminal session: + +.. code-block:: console + + Hello World! sim3u1xx_dk/sim3u167 + +References +********** + +.. target-notes:: + +.. _development kit: + https://www.silabs.com/development-tools/mcu/32-bit/sim3u1xx-development-kit diff --git a/boards/silabs/dev_kits/sim3u1xx_dk/doc/sim3u1xx_dk.webp b/boards/silabs/dev_kits/sim3u1xx_dk/doc/sim3u1xx_dk.webp new file mode 100644 index 00000000000..56ad9e6877c Binary files /dev/null and b/boards/silabs/dev_kits/sim3u1xx_dk/doc/sim3u1xx_dk.webp differ diff --git a/boards/silabs/dev_kits/sim3u1xx_dk/sim3u1xx_dk-pinctrl.dtsi b/boards/silabs/dev_kits/sim3u1xx_dk/sim3u1xx_dk-pinctrl.dtsi new file mode 100644 index 00000000000..08d3b0176e7 --- /dev/null +++ b/boards/silabs/dev_kits/sim3u1xx_dk/sim3u1xx_dk-pinctrl.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2024 GARDENA GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + usart0_default: usart0_default { + group1 { + pinmux = , + ; + output-enable; + }; + group2 { + pinmux = , + ; + input-enable; + }; + }; +}; diff --git a/boards/silabs/dev_kits/sim3u1xx_dk/sim3u1xx_dk.dts b/boards/silabs/dev_kits/sim3u1xx_dk/sim3u1xx_dk.dts new file mode 100644 index 00000000000..f55f5a667f9 --- /dev/null +++ b/boards/silabs/dev_kits/sim3u1xx_dk/sim3u1xx_dk.dts @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2024 GARDENA GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "sim3u1xx_dk-pinctrl.dtsi" +#include + +/ { + model = "Silicon Labs SiM3U1xx-B-DK"; + compatible = "gardena,sim3u1xx-dk", "silabs,sim3u167","silabs,sim3u"; + + aliases { + led0 = &led_yellow; + led1 = &led_red; + sw0 = &user_button_sw2; + sw1 = &user_button_sw3; + }; + + chosen { + zephyr,console = &usart0; + zephyr,flash = &flash0; + zephyr,shell-uart = &usart0; + zephyr,sram = &sram0; + }; + + leds { + compatible = "gpio-leds"; + + led_red: led_2_10 { + label = "Red LED (DS3)"; + gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + }; + led_yellow: led_2_11 { + label = "Yellow LED (DS4)"; + gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_button_sw2: button_0 { + label = "Push button switch (SW2)"; + gpios = <&gpio2 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + user_button_sw3: button_1 { + label = "Push button switch (SW3)"; + gpios = <&gpio2 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + }; +}; + +&cpu0 { + clock-frequency = <76953600>; +}; + +&pll0 { + status = "okay"; +}; + +&clk_ahb { + clocks = <&pll0>; + status = "okay"; +}; + +&clk_apb { + divider = <2>; + status = "okay"; +}; + +&usart0 { + current-speed = <115200>; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; + hw-flow-control; + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + slot0_partition: partition@0 { + label = "image-0"; + reg = <0x00000000 DT_SIZE_K(192)>; + }; + + storage_partition: partition@30000 { + label = "storage"; + reg = <0x00030000 DT_SIZE_K(64)>; + }; + }; +}; diff --git a/boards/silabs/dev_kits/sim3u1xx_dk/sim3u1xx_dk.yaml b/boards/silabs/dev_kits/sim3u1xx_dk/sim3u1xx_dk.yaml new file mode 100644 index 00000000000..3555255ae42 --- /dev/null +++ b/boards/silabs/dev_kits/sim3u1xx_dk/sim3u1xx_dk.yaml @@ -0,0 +1,21 @@ +# Copyright (c) 2024 GARDENA GmbH +# +# SPDX-License-Identifier: Apache-2.0 + +identifier: sim3u1xx_dk +name: Silicon Labs SiM3U development kit +type: mcu +arch: arm +ram: 32 +flash: 256 +toolchain: + - gnuarmemb + - xtools + - zephyr +supported: + - dma + - flash + - gpio + - nvs + - uart +vendor: gardena diff --git a/boards/silabs/dev_kits/sim3u1xx_dk/sim3u1xx_dk_defconfig b/boards/silabs/dev_kits/sim3u1xx_dk/sim3u1xx_dk_defconfig new file mode 100644 index 00000000000..e7d47535289 --- /dev/null +++ b/boards/silabs/dev_kits/sim3u1xx_dk/sim3u1xx_dk_defconfig @@ -0,0 +1,9 @@ +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y diff --git a/boards/silabs/dev_kits/sim3u1xx_dk/support/openocd.cfg b/boards/silabs/dev_kits/sim3u1xx_dk/support/openocd.cfg new file mode 100644 index 00000000000..87aca7aab60 --- /dev/null +++ b/boards/silabs/dev_kits/sim3u1xx_dk/support/openocd.cfg @@ -0,0 +1,24 @@ +# Copyright (c) 2024 GARDENA GmbH +# +# SPDX-License-Identifier: Apache-2.0 + +source [find interface/ftdi/olimex-arm-usb-ocd-h.cfg] +source [find interface/ftdi/olimex-arm-jtag-swd.cfg] + +source [find target/sim3x.cfg] + +# On SiM3U1xx, doing a chip reset also takes down the debug port. For this reason, we disable the +# chip reset and instead only reset the Cortex M via the AIRCR SYSRESETREQ bit, as suggested in the +# chip's errata: https://www.silabs.com/documents/public/errata/SiM3U1xx-SiM3C1xxErrata.pdf +cortex_m reset_config sysresetreq + +$_TARGETNAME configure -event gdb-attach { + echo "Debugger attaching: halting execution" + reset halt + gdb_breakpoint_override hard +} + +$_TARGETNAME configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} diff --git a/boards/silabs/efr32mg_sltb004a/CMakeLists.txt b/boards/silabs/dev_kits/sltb004a/CMakeLists.txt similarity index 100% rename from boards/silabs/efr32mg_sltb004a/CMakeLists.txt rename to boards/silabs/dev_kits/sltb004a/CMakeLists.txt diff --git a/boards/silabs/dev_kits/sltb004a/Kconfig.defconfig b/boards/silabs/dev_kits/sltb004a/Kconfig.defconfig new file mode 100644 index 00000000000..3a9256b44e1 --- /dev/null +++ b/boards/silabs/dev_kits/sltb004a/Kconfig.defconfig @@ -0,0 +1,14 @@ +# EFR32MG SLTB004A board + +# Copyright (c) 2018, Diego Sueiro +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_SLTB004A + +config CMU_HFXO_FREQ + default 40000000 + +config CMU_LFXO_FREQ + default 32768 + +endif # BOARD_SLTB004A diff --git a/boards/silabs/dev_kits/sltb004a/Kconfig.sltb004a b/boards/silabs/dev_kits/sltb004a/Kconfig.sltb004a new file mode 100644 index 00000000000..58f4485dd4e --- /dev/null +++ b/boards/silabs/dev_kits/sltb004a/Kconfig.sltb004a @@ -0,0 +1,7 @@ +# EFR32MG SLTB004A board + +# Copyright (c) 2018, Diego Sueiro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SLTB004A + select SOC_PART_NUMBER_EFR32MG12P332F1024GL125 diff --git a/boards/silabs/efr32mg_sltb004a/board.c b/boards/silabs/dev_kits/sltb004a/board.c similarity index 100% rename from boards/silabs/efr32mg_sltb004a/board.c rename to boards/silabs/dev_kits/sltb004a/board.c diff --git a/boards/silabs/efr32mg_sltb004a/board.cmake b/boards/silabs/dev_kits/sltb004a/board.cmake similarity index 100% rename from boards/silabs/efr32mg_sltb004a/board.cmake rename to boards/silabs/dev_kits/sltb004a/board.cmake diff --git a/boards/silabs/dev_kits/sltb004a/board.yml b/boards/silabs/dev_kits/sltb004a/board.yml new file mode 100644 index 00000000000..2141aa3817d --- /dev/null +++ b/boards/silabs/dev_kits/sltb004a/board.yml @@ -0,0 +1,5 @@ +board: + name: sltb004a + vendor: silabs + socs: + - name: efr32mg12p332f1024gl125 diff --git a/boards/silabs/dev_kits/sltb004a/doc/index.rst b/boards/silabs/dev_kits/sltb004a/doc/index.rst new file mode 100644 index 00000000000..e11145365fb --- /dev/null +++ b/boards/silabs/dev_kits/sltb004a/doc/index.rst @@ -0,0 +1,211 @@ +.. _sltb004a: + +EFR32MG12 Thunderboard (SLTB004A) +################################# + +Overview +******** + +The EFR32MG12 Thunderboard (a.k.a Thunderboard Sense 2) contains an MCU +from the EFR32MG12 family built on ARM® Cortex®-M4F processor with low +power capabilities. + +.. image:: sltb004a.jpg + :align: center + :alt: EFR32MG12 SLTB004A + +Hardware +******** + +- EFR32MG12 Mighty Gecko Wireless SoC with 38.4 MHz operating frequency +- ARM® Cortex® M4 core with 256 kB RAM and 1024 kB Flash +- Macronix ultra low power 8-Mbit SPI flash (MX25R8035F) +- 2.4 GHz ceramic antenna for wireless transmission +- Silicon Labs Si7021 relative humidity and temperature sensor +- Silicon Labs Si1133 UV index and ambient light sensor +- Silicon Labs Si7210 hall effect sensor +- Bosch Sensortec BMP280 barometric pressure sensor +- ams CCS811 indoor air quality gas sensor +- TDK InvenSense ICM-20648 6-axis inertial sensor +- TDK InvenSense ICS-43434 MEMS microphone +- Four high brightness RGB LEDs from Broadcom Limited (ASMT-YTB7-0AA02) +- One bi-color LED and two push buttons +- Power enable signals for fine grained power-control +- On-board SEGGER J-Link debugger for easy programming and debugging, which + includes a USB virtual COM port +- Mini Simplicity connector for access to energy profiling and advanced wireless + network debugging +- Breakout pads for GPIO access and connection to external hardware +- Reset button +- Automatic switch-over between USB and battery power +- CR2032 coin cell holder and external battery connector + +For more information about the EFR32MG12 SoC and Thunderboard Sense 2 board: + +- `EFR32MG12 Datasheet`_ +- `EFR32MG12 Reference Manual`_ +- `SLTB004A User Guide`_ +- `SLTB004A Schematics`_ + +Supported Features +================== + +The sltb004a board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtcc | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c port-polling | ++-----------+------------+-------------------------------------+ +| SPI(M) | on-chip | spi port-polling | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | true random number generator | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/dev_kits/sltb004a/sltb004a_defconfig` + +Other hardware features are currently not supported by the port. + +Connections and IOs +=================== + +The EFR32MG12 SoC has eight gpio controllers (PORTA, PORTB, PORTC, PORTD, +PORTF, PORTI, PORTJ and PORTK). + +In the following table, the column Name contains Pin names. For example, PE2 +means Pin number 2 on PORTE and #27 represents the location bitfield , as used +in the board's and microcontroller's datasheets and manuals. + ++------+-------------+-----------------------------------+ +| Name | Function | Usage | ++======+=============+===================================+ +| PD8 | GPIO | LED0 (RED) | ++------+-------------+-----------------------------------+ +| PD9 | GPIO | LED1 (GREEN) | ++------+-------------+-----------------------------------+ +| PD14 | GPIO | SW0 Push Button PB0 | ++------+-------------+-----------------------------------+ +| PD15 | GPIO | Push Button PB1 | ++------+-------------+-----------------------------------+ +| PA0 | UART_TX | UART TX Console VCOM_TX US0_TX #0 | ++------+-------------+-----------------------------------+ +| PA1 | UART_RX | UART RX Console VCOM_RX US0_RX #0 | ++------+-------------+-----------------------------------+ +| PF3 | UART_TX | EXP12_UART_TX LEU0_TX #27 | ++------+-------------+-----------------------------------+ +| PF4 | UART_RX | EXP14_UART_RX LEU0_RX #27 | ++------+-------------+-----------------------------------+ +| PC10 | I2C_SDA | EXP16_I2C_SDA I2C0_SDA #15 | ++------+-------------+-----------------------------------+ +| PC11 | I2C_SCL | EXP15_I2C_SCL I2C0_SCL #15 | ++------+-------------+-----------------------------------+ +| PB6 | I2C_SDA | CCS811_I2C_SDA I2C1_SDA #6 | ++------+-------------+-----------------------------------+ +| PB7 | I2C_SCL | CCS811_I2C_SCL I2C1_SCL #6 | ++------+-------------+-----------------------------------+ +| PK0 | SPI_MOSI | Flash MOSI US2_TX #29 | ++------+-------------+-----------------------------------+ +| PK2 | SPI_MISO | Flash MISO US2_RX #30 | ++------+-------------+-----------------------------------+ +| PF7 | SPI_SCLK | Flash SCLK US2_CLK #18 | ++------+-------------+-----------------------------------+ +| PK1 | SPI_CS | Flash Chip Select (GPIO) | ++------+-------------+-----------------------------------+ + +System Clock +============ + +The EFR32MG12 SoC is configured to use the 38.4 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFR32MG12 SoC has four USARTs and one Low Energy UARTs (LEUART with 9600 +maximum baudrate). USART0 is configured as the Zephyr console and is connected +to the On-Board J-Link Debugger that presents a virtual COM port for general +purpose application serial data transfer with this interface. + +Programming and Debugging +************************* + +.. note:: + Before using the kit the first time, you should update the J-Link firmware + from `J-Link-Downloads`_ + +Flashing +======== + +The SLTB004A includes an `J-Link`_ serial and debug adaptor built into the +board. The adaptor provides: + +- A USB connection to the host computer, which exposes a Mass Storage and a + USB Serial Port. +- A Serial Flash device, which implements the USB flash disk file storage. +- A physical UART connection which is relayed over interface USB Serial port. + +Flashing an application to SLTB004A +----------------------------------- + +The sample application :zephyr:code-sample:`hello_world` is used for this example. +Build the Zephyr kernel and application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sltb004a + :goals: build + +Connect the SLTB004A to your host computer using the USB port and you +should see a USB connection which exposes a Mass Storage (TB004) and a +USB Serial Port. Copy the generated zephyr.bin in the SLTB004A drive. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you should be able to see on the corresponding Serial Port +the following message: + +.. code-block:: console + + Hello World! sltb004a + + +.. _SLTB004A User Guide: + https://www.silabs.com/documents/public/user-guides/ug309-sltb004a-user-guide.pdf + +.. _SLTB004A Schematics: + https://www.silabs.com/documents/public/schematic-files/BRD4166A-D00-schematic.pdf + +.. _EFR32MG12 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efr32mg12-datasheet.pdf + +.. _EFR32MG12 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efr32xg12-rm.pdf + +.. _J-Link: + https://www.segger.com/jlink-debug-probes.html + +.. _J-Link-Downloads: + https://www.segger.com/downloads/jlink diff --git a/boards/silabs/efr32mg_sltb004a/doc/efr32mg_sltb004a.jpg b/boards/silabs/dev_kits/sltb004a/doc/sltb004a.jpg similarity index 100% rename from boards/silabs/efr32mg_sltb004a/doc/efr32mg_sltb004a.jpg rename to boards/silabs/dev_kits/sltb004a/doc/sltb004a.jpg diff --git a/boards/silabs/efr32_radio/pre_dt_board.cmake b/boards/silabs/dev_kits/sltb004a/pre_dt_board.cmake similarity index 100% rename from boards/silabs/efr32_radio/pre_dt_board.cmake rename to boards/silabs/dev_kits/sltb004a/pre_dt_board.cmake diff --git a/boards/silabs/dev_kits/sltb004a/sltb004a-pinctrl.dtsi b/boards/silabs/dev_kits/sltb004a/sltb004a-pinctrl.dtsi new file mode 100644 index 00000000000..e500e3b18bd --- /dev/null +++ b/boards/silabs/dev_kits/sltb004a/sltb004a-pinctrl.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2022 Silicon Labs + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + /* configuration for uart0 device, default state */ + usart0_default: usart0_default { + group1 { + /* configure PA.1 as UART_RX */ + psels = , + ; + }; + group2 { + /* configure PA.0 as UART_TX */ + psels = , + ; + }; + }; +}; diff --git a/boards/silabs/dev_kits/sltb004a/sltb004a.dts b/boards/silabs/dev_kits/sltb004a/sltb004a.dts new file mode 100644 index 00000000000..033984be007 --- /dev/null +++ b/boards/silabs/dev_kits/sltb004a/sltb004a.dts @@ -0,0 +1,233 @@ +/* + * Copyright (c) 2018 Diego Sueiro + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "sltb004a-pinctrl.dtsi" +#include + +/ { + model = "Silabs EFR32MG12 SLTB004A board (aka Thunderboard Sense 2)"; + compatible = "silabs,sltb004a", "silabs,efr32mg"; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + led1 = &led1; + pwm-led0 = &pwm_led0; + sw0 = &button0; + sw1 = &button1; + watchdog0 = &wdog0; + watchdog1 = &wdog1; + }; + + chosen { + zephyr,console = &usart0; + zephyr,shell-uart = &usart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpiod 8 0>; + label = "LED 0"; + }; + led1: led_1 { + gpios = <&gpiod 9 0>; + label = "LED 1"; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + /* gpio flags need validation */ + gpios = <&gpiod 14 GPIO_ACTIVE_LOW>; + label = "User Push Button 0"; + zephyr,code = ; + }; + button1: button_1 { + /* gpio flags need validation */ + gpios = <&gpiod 15 GPIO_ACTIVE_LOW>; + label = "User Push Button 1"; + zephyr,code = ; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + status = "okay"; + pwm_led0: pwm_led0 { + pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + }; + }; +}; + +&cpu0 { + clock-frequency = <38400000>; +}; + +&usart0 { + current-speed = <115200>; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usart2 { + compatible = "silabs,gecko-spi-usart"; + + #address-cells = <1>; + #size-cells = <0>; + + location-rx = ; + location-tx = ; + location-clk = ; + + cs-gpios = <&gpiok 1 GPIO_ACTIVE_LOW>; + + status = "okay"; + + mx25r80: mx25r8035f@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + size = <0x800000>; + jedec-id = [c2 28 14]; + sfdp-bfp = [ + e5 20 f1 ff ff ff 7f 00 44 eb 08 6b 08 3b 04 bb + ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 + 10 d8 00 ff 23 72 f5 00 82 ed 04 b7 44 83 38 44 + 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff + ]; + }; +}; + +&leuart0 { + current-speed = <9600>; + location-rx = ; + location-tx = ; + status = "okay"; +}; + +&pinctrl { + i2c0_default: i2c0_default { + group1 { + psels = , + , + , + ; + }; + }; + + i2c1_default: i2c1_default { + group1 { + psels = , + , + , + ; + }; + }; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c1 { + /* This set selects for CCS811_I2C supporting CCS811 */ + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; + status = "okay"; + + ccs811: ccs811@5a { + compatible = "ams,ccs811"; + reg = <0x5a>; + supply-gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>; + irq-gpios = <&gpiof 13 GPIO_ACTIVE_LOW>; + wake-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>; + }; + + /* This set selects for ENV_I2C supporting Si7021, Si11330, BMP280 */ + /* + location-sda = ; + location-scl = ; + */ + + /* This set selects for HALL_I2C supporting Si7210 */ + /* + location-sda = ; + location-scl = ; + */ +}; + +&rtcc0 { + prescaler = <1>; + status = "okay"; +}; + +&timer0 { + status = "okay"; + + pwm0: pwm { + status = "okay"; + pin-location = ; + prescaler = <1024>; + }; +}; + +&gpio { + location-swo = <0>; + status = "okay"; +}; + +&gpioa { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&gpiof { + status = "okay"; +}; + +&gpiok { + status = "okay"; +}; + +&wdog0 { + status = "okay"; +}; + +&wdog1 { + status = "okay"; +}; + +&flash0 { + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Set 6Kb of storage at the end of the 1024Kb of flash */ + storage_partition: partition@fe800 { + label = "storage"; + reg = <0x000fe800 0x00001800>; + }; + + }; +}; + +&trng0 { + status = "okay"; +}; diff --git a/boards/silabs/dev_kits/sltb004a/sltb004a.yaml b/boards/silabs/dev_kits/sltb004a/sltb004a.yaml new file mode 100644 index 00000000000..a610e85fdee --- /dev/null +++ b/boards/silabs/dev_kits/sltb004a/sltb004a.yaml @@ -0,0 +1,21 @@ +identifier: sltb004a +name: Thunderboard Sense 2 (SLTB004A, BRD4166A) +type: mcu +arch: arm +ram: 256 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - i2c + - nvs + - spi + - watchdog +testing: + ignore_tags: + - net + - bluetooth +vendor: silabs diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32bg13p632f512gm48_defconfig b/boards/silabs/dev_kits/sltb004a/sltb004a_defconfig similarity index 100% rename from boards/silabs/efr32_radio/efr32_radio_efr32bg13p632f512gm48_defconfig rename to boards/silabs/dev_kits/sltb004a/sltb004a_defconfig diff --git a/boards/silabs/dev_kits/sltb009a/Kconfig.defconfig b/boards/silabs/dev_kits/sltb009a/Kconfig.defconfig new file mode 100644 index 00000000000..6c21d423607 --- /dev/null +++ b/boards/silabs/dev_kits/sltb009a/Kconfig.defconfig @@ -0,0 +1,20 @@ +# EFM32GG SLTB009A default board configuration +# Copyright (c) 2023 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_SLTB009A + +config CMU_HFXO_FREQ + default 50000000 + +config CMU_HFRCO_FREQ + default 72000000 + +config CMU_LFXO_FREQ + default 32768 + +config LOG_BACKEND_SWO_FREQ_HZ + default 875000 + depends on LOG_BACKEND_SWO + +endif # BOARD_SLTB009A diff --git a/boards/silabs/dev_kits/sltb009a/Kconfig.sltb009a b/boards/silabs/dev_kits/sltb009a/Kconfig.sltb009a new file mode 100644 index 00000000000..d486de84769 --- /dev/null +++ b/boards/silabs/dev_kits/sltb009a/Kconfig.sltb009a @@ -0,0 +1,6 @@ +# EFM32GG SLTB009A board configuration +# Copyright (c) 2023 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SLTB009A + select SOC_PART_NUMBER_EFM32GG12B810F1024GM64 diff --git a/boards/silabs/efm32gg_sltb009a/board.cmake b/boards/silabs/dev_kits/sltb009a/board.cmake similarity index 100% rename from boards/silabs/efm32gg_sltb009a/board.cmake rename to boards/silabs/dev_kits/sltb009a/board.cmake diff --git a/boards/silabs/dev_kits/sltb009a/board.yml b/boards/silabs/dev_kits/sltb009a/board.yml new file mode 100644 index 00000000000..af69758728d --- /dev/null +++ b/boards/silabs/dev_kits/sltb009a/board.yml @@ -0,0 +1,5 @@ +board: + name: sltb009a + vendor: silabs + socs: + - name: efm32gg12b810f1024gm64 diff --git a/boards/silabs/dev_kits/sltb009a/doc/index.rst b/boards/silabs/dev_kits/sltb009a/doc/index.rst new file mode 100644 index 00000000000..9366a7d2649 --- /dev/null +++ b/boards/silabs/dev_kits/sltb009a/doc/index.rst @@ -0,0 +1,166 @@ +.. _efm32gg_sltb009a: + +EFM32GG12 Thunderboard (SLTB009A) +################################# + +Overview +******** + +The EFM32GG12 Thunderboard Kit (SLTB009A) is an evaluation platform for the +EFM32GG12 Giant Gecko Microcontroller, featuring an ARM Cortex-M4 with FPU, +1024kB flash, and 192kB RAM. + +.. figure:: sltb009a.jpg + :align: center + :alt: SLTB009A + + SLTB009A (Credit: Silicon Labs) + +Hardware +******** + +- PDM stereo microphones +- USB connectivity +- On-board Segger J-Link USB debugger +- 2 user buttons and 2 LEDs +- USB C connector + +For more information about the WGM160P and SLTB009A board: + +- `SLTB009A Website`_ +- `SLTB009A User Guide`_ +- `EFM32GG12 Datasheet`_ +- `EFM32GG12 Reference Manual`_ + +Supported Features +================== + +The efm32gg_sltb009a board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtcc | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c port-polling | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/dev_kits/sltb009a/sltb009a_defconfig` + +Connections and IOs +=================== + +The EFM32GG12 MCU has six GPIO controllers (PORTA to PORTF), all of which are +currently enabled for the SLTB009A board. + +In the following table, the column **Name** contains pin names. For example, PE1 +means pin number 1 on PORTE, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Name | Function | Usage | ++=======+=============+=====================================+ +| PE12 | GPIO | LED0 | ++-------+-------------+-------------------------------------+ +| PA13 | GPIO | LED1 | ++-------+-------------+-------------------------------------+ +| PD5 | GPIO | Push Button PB0 | ++-------+-------------+-------------------------------------+ +| PD8 | GPIO | Push Button PB1 | ++-------+-------------+-------------------------------------+ +| PE7 | UART_TX | UART TX Console VCOM_TX US0_TX #1 | ++-------+-------------+-------------------------------------+ +| PE6 | UART_RX | UART RX Console VCOM_RX US0_RX #1 | ++-------+-------------+-------------------------------------+ +| PC0 | I2C_SDA | SENSOR_I2C_SDA I2C0_SDA #1 | ++-------+-------------+-------------------------------------+ +| PC1 | I2C_SCL | SENSOR_I2C_SCL I2C0_SCL #1 | ++-------+-------------+-------------------------------------+ +| PC4 | I2C_SDA | SENSOR_I2C_SDA I2C1_SDA #1 | ++-------+-------------+-------------------------------------+ +| PC5 | I2C_SCL | SENSOR_I2C_SCL I2C1_SCL #1 | ++-------+-------------+-------------------------------------+ + + +System Clock +============ + +The EFM32GG12 MCU is configured to work at 72 MHz. + +Serial Port +=========== + +The EFM32GG12 SoC has five USARTs, two UARTs and two Low Energy UARTs (LEUART). +USART0 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +.. note:: + Before using the kit the first time, you should update the J-Link firmware + from `J-Link-Downloads`_ + +Flashing +======== + +The SLTB009A includes an `J-Link`_ serial and debug adaptor built into the +board. The adaptor provides: + +- A USB connection to the host computer +- A physical UART connection which is relayed over interface USB serial port. + +Flashing an application to SLTB009A +----------------------------------- + +Connect the SLTB009A to your host computer using the USB port. + +Here is an example to build and flash the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sltb009a + :goals: flash + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you'll see the following message on the corresponding serial port +terminal session: + +.. code-block:: console + + Hello World! sltb009a + +.. _SLTB009A Website: + https://www.silabs.com/development-tools/thunderboard/thunderboard-gg12-kit + +.. _SLTB009A User Guide: + https://www.silabs.com/documents/public/user-guides/ug371-sltb009a-user-guide.pdf + +.. _EFM32GG12 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efm32gg12-datasheet.pdf + +.. _EFM32GG12 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efm32gg12-rm.pdf + +.. _J-Link: + https://www.segger.com/jlink-debug-probes.html + +.. _J-Link-Downloads: + https://www.segger.com/downloads/jlink diff --git a/boards/silabs/efm32gg_sltb009a/doc/efm32gg12-thunderboard-kit.jpg b/boards/silabs/dev_kits/sltb009a/doc/sltb009a.jpg similarity index 100% rename from boards/silabs/efm32gg_sltb009a/doc/efm32gg12-thunderboard-kit.jpg rename to boards/silabs/dev_kits/sltb009a/doc/sltb009a.jpg diff --git a/boards/silabs/efm32gg_sltb009a/efm32gg_sltb009a-pinctrl.dtsi b/boards/silabs/dev_kits/sltb009a/sltb009a-pinctrl.dtsi similarity index 100% rename from boards/silabs/efm32gg_sltb009a/efm32gg_sltb009a-pinctrl.dtsi rename to boards/silabs/dev_kits/sltb009a/sltb009a-pinctrl.dtsi diff --git a/boards/silabs/dev_kits/sltb009a/sltb009a.dts b/boards/silabs/dev_kits/sltb009a/sltb009a.dts new file mode 100644 index 00000000000..1c36fb59f21 --- /dev/null +++ b/boards/silabs/dev_kits/sltb009a/sltb009a.dts @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2023 Antmicro + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include "sltb009a-pinctrl.dtsi" + +/ { + model = "Silicon Labs EFM32GG12 SLTB009A board"; + compatible = "silabs,sltb009a"; + + chosen { + zephyr,console = &usart0; + zephyr,shell-uart = &usart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + led1 = &led1; + sw0 = &button0; + sw1 = &button1; + watchdog0 = &wdog0; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpioe 12 GPIO_ACTIVE_HIGH>; + label = "LED 0"; + }; + led1: led_1 { + gpios = <&gpioa 13 GPIO_ACTIVE_HIGH>; + label = "LED 1"; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpiod 5 GPIO_ACTIVE_HIGH>; + label = "User Push Button 0"; + zephyr,code = ; + }; + button1: button_1 { + gpios = <&gpiod 8 GPIO_ACTIVE_HIGH>; + label = "User Push Button 1"; + zephyr,code = ; + }; + }; +}; + +&usart0 { + current-speed = <115200>; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usart4 { + current-speed = <115200>; + location-rx = ; + location-tx = ; + status = "okay"; +}; + +&leuart0 { + current-speed = <9600>; + location-rx = ; + location-tx = ; + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rtcc0 { + prescaler = <1>; + status = "okay"; +}; + +&gpioa { + status = "okay"; + board-controller-enable { + // VCOM Isolation. Set PA15 to HIGH to enable VCOM_{RX,TX}. + gpio-hog; + gpios = <15 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&gpio { + location-swo = <0>; + status = "okay"; +}; + +&gpiob { + status = "okay"; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&gpioe { + status = "okay"; +}; + +&gpiof { + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Set 12Kb of storage at the end of the 2048Kb of flash */ + storage_partition: partition@1fd000 { + label = "storage"; + reg = <0x001fd000 0x00003000>; + }; + }; +}; + +&wdog0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&cpu0 { + clock-frequency = <72000000>; +}; diff --git a/boards/silabs/dev_kits/sltb009a/sltb009a.yaml b/boards/silabs/dev_kits/sltb009a/sltb009a.yaml new file mode 100644 index 00000000000..468b6b48d56 --- /dev/null +++ b/boards/silabs/dev_kits/sltb009a/sltb009a.yaml @@ -0,0 +1,16 @@ +identifier: sltb009a +name: Thunderboard EFM32GG12 (SLTB009A, BRD2207A) +type: mcu +arch: arm +ram: 192 +flash: 1024 +toolchain: + - zephyr +supported: + - i2c + - gpio + - nvs +testing: + ignore_tags: + - bluetooth +vendor: silabs diff --git a/boards/silabs/efm32gg_sltb009a/efm32gg_sltb009a_defconfig b/boards/silabs/dev_kits/sltb009a/sltb009a_defconfig similarity index 100% rename from boards/silabs/efm32gg_sltb009a/efm32gg_sltb009a_defconfig rename to boards/silabs/dev_kits/sltb009a/sltb009a_defconfig diff --git a/boards/silabs/efr32_thunderboard/CMakeLists.txt b/boards/silabs/dev_kits/sltb010a/CMakeLists.txt similarity index 100% rename from boards/silabs/efr32_thunderboard/CMakeLists.txt rename to boards/silabs/dev_kits/sltb010a/CMakeLists.txt diff --git a/boards/silabs/dev_kits/sltb010a/Kconfig b/boards/silabs/dev_kits/sltb010a/Kconfig new file mode 100644 index 00000000000..6fdb24720ae --- /dev/null +++ b/boards/silabs/dev_kits/sltb010a/Kconfig @@ -0,0 +1,8 @@ +# EFR32 Thunderboard-style boards + +# Copyright (c) 2022, Silicon Labs +# SPDX-License-Identifier: Apache-2.0 + +module = BOARD_SLTB010A +module-str = Board Control +source "subsys/logging/Kconfig.template.log_config" diff --git a/boards/silabs/dev_kits/sltb010a/Kconfig.defconfig b/boards/silabs/dev_kits/sltb010a/Kconfig.defconfig new file mode 100644 index 00000000000..9b45efccc90 --- /dev/null +++ b/boards/silabs/dev_kits/sltb010a/Kconfig.defconfig @@ -0,0 +1,34 @@ +# Thunderboard-style boards + +# Copyright (c) 2023 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config CMU_HFXO_FREQ + default 38400000 + +config CMU_LFXO_FREQ + default 32768 + +if SOC_GECKO_USE_RAIL + +config FPU + default y + +endif # SOC_GECKO_USE_RAIL + +if BT + +config FPU + default y + +config COMMON_LIBC_MALLOC_ARENA_SIZE + default 8192 + +config MAIN_STACK_SIZE + default 3072 if PM + default 2304 + +endif # BT + +config REGULATOR + default y if SI7210 diff --git a/boards/silabs/dev_kits/sltb010a/Kconfig.sltb010a b/boards/silabs/dev_kits/sltb010a/Kconfig.sltb010a new file mode 100644 index 00000000000..43710c25408 --- /dev/null +++ b/boards/silabs/dev_kits/sltb010a/Kconfig.sltb010a @@ -0,0 +1,7 @@ +# EFR32BG SLTB010A board + +# Copyright (c) 2021, Sateesh Kotapati +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SLTB010A + select SOC_PART_NUMBER_EFR32BG22C224F512IM40 diff --git a/boards/silabs/dev_kits/sltb010a/board.c b/boards/silabs/dev_kits/sltb010a/board.c new file mode 100644 index 00000000000..7572f0fad39 --- /dev/null +++ b/boards/silabs/dev_kits/sltb010a/board.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2021 Sateesh Kotapati + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#ifdef CONFIG_SOC_GECKO_DEV_INIT +#include "em_cmu.h" +#endif + + +LOG_MODULE_REGISTER(thunderboard, CONFIG_BOARD_SLTB010A_LOG_LEVEL); + +static int thunderboard_init_clocks(void); + +static int thunderboard_init(void) +{ + int ret; + +#ifdef CONFIG_SOC_GECKO_DEV_INIT + thunderboard_init_clocks(); +#endif + static struct gpio_dt_spec wake_up_gpio_dev = + GPIO_DT_SPEC_GET(DT_NODELABEL(wake_up_trigger), gpios); + + + if (!gpio_is_ready_dt(&wake_up_gpio_dev)) { + LOG_ERR("Wake-up GPIO device was not found!\n"); + return -ENODEV; + } + ret = gpio_pin_configure_dt(&wake_up_gpio_dev, GPIO_OUTPUT_ACTIVE); + if (ret < 0) { + return ret; + } + + return 0; +} + +#ifdef CONFIG_SOC_GECKO_DEV_INIT +static int thunderboard_init_clocks(void) +{ + CMU_ClockSelectSet(cmuClock_SYSCLK, cmuSelect_HFRCODPLL); +#if defined(_CMU_EM01GRPACLKCTRL_MASK) + CMU_ClockSelectSet(cmuClock_EM01GRPACLK, cmuSelect_HFRCODPLL); +#endif +#if defined(_CMU_EM01GRPBCLKCTRL_MASK) + CMU_ClockSelectSet(cmuClock_EM01GRPBCLK, cmuSelect_HFRCODPLL); +#endif + CMU_ClockSelectSet(cmuClock_EM23GRPACLK, cmuSelect_LFRCO); +#if defined(RTCC_PRESENT) + CMU_ClockSelectSet(cmuClock_RTCC, cmuSelect_LFRCO); +#endif + CMU_ClockSelectSet(cmuClock_WDOG0, cmuSelect_LFRCO); + + return 0; +} +#endif + +/* needs to be done after GPIO driver init */ +SYS_INIT(thunderboard_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); diff --git a/boards/silabs/dev_kits/sltb010a/board.cmake b/boards/silabs/dev_kits/sltb010a/board.cmake new file mode 100644 index 00000000000..fdaebc0c844 --- /dev/null +++ b/boards/silabs/dev_kits/sltb010a/board.cmake @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Silicon Laboratories Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=EFR32BG22C224F512IM40" "--reset-after-load") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/silabs/dev_kits/sltb010a/board.yml b/boards/silabs/dev_kits/sltb010a/board.yml new file mode 100644 index 00000000000..4586a51ef72 --- /dev/null +++ b/boards/silabs/dev_kits/sltb010a/board.yml @@ -0,0 +1,11 @@ +boards: + - name: sltb010a + vendor: silabs + socs: + - name: efr32bg22c224f512im40 + revision: + format: number + default: "2" + revisions: + - name: "0" + - name: "2" diff --git a/boards/silabs/dev_kits/sltb010a/doc/index.rst b/boards/silabs/dev_kits/sltb010a/doc/index.rst new file mode 100644 index 00000000000..a335924359f --- /dev/null +++ b/boards/silabs/dev_kits/sltb010a/doc/index.rst @@ -0,0 +1,223 @@ +.. _sltb010a: + +EFR32BG22 Thunderboard (SLTB010A) +################################# + +SLTB010A is a development kit based on the EFR32BG22 SoC. Early revisions of +the kit (A00 and A01) use a slightly different PCB (BRD4184A) from later +revisions (BRD4184B). + +.. image:: ./sltb010a.jpg + :align: center + :alt: SLTB010A board + +Hardware +******** + +- EFR32BG22 Blue Gecko Wireless SoC with upto 76.8 MHz operating frequency +- ARM® Cortex® M33 core with 32 kB RAM and 512 kB Flash +- Macronix ultra low power 8-Mbit SPI flash (MX25R8035F) +- 2.4 GHz ceramic antenna for wireless transmission +- Silicon Labs Si7021 relative humidity and temperature sensor +- Silicon Labs Si1133 UV index and ambient light sensor (EFR32BG22-BRD4184A) +- Vishay VEML6035 ambient light sensor (EFR32BG22-BRD4184B) +- Silicon Labs Si7210 hall effect sensor +- TDK InvenSense ICM-20648 6-axis inertial sensor +- Two Knowles SPK0641HT4H-1 MEMS microphones with PDM output (EFR32BG22-BRD4184B) +- One LED and one push button +- Power enable signals and isolation switches for ultra low power operation +- On-board SEGGER J-Link debugger for easy programming and debugging, which + includes a USB virtual COM port and Packet Trace Interface (PTI) +- Mini Simplicity connector for access to energy profiling and advanced wireless + network debugging +- Breakout pads for GPIO access and connection to external hardware +- Reset button +- Automatic switch-over between USB and battery power +- CR2032 coin cell holder and external battery connector + +For more information about the EFR32BG SoC and Thunderboard EFR32BG22 board: + +- `EFR32BG22 Website`_ +- `EFR32BG22 Datasheet`_ +- `EFR32xG22 Reference Manual`_ +- `Thunderboard EFR32BG22 Website`_ +- `EFR32BG22-BRD4184A User Guide`_ +- `EFR32BG22-BRD4184B User Guide`_ +- `EFR32BG22-BRD4184A Schematics`_ +- `EFR32BG22-BRD4184B Schematics`_ + +Supported Features +================== + +The sltb010a board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | stimer | ++-----------+------------+-------------------------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | true random number generator | ++-----------+------------+-------------------------------------+ +| I2C(M/S) | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| RADIO | on-chip | bluetooth | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/dev_kits/sltb010a/sltb010a_defconfig`. + +Connections and IOs +=================== + +The EFR32BG22 SoC has four gpio controllers (PORTA, PORTB, PORTC and PORTD). + +There are two variants of this board, "A" and "B". Please take a look at your PCB, +to determine which one you have, as the GPIO pin bindings vary between those two. + +BRD4184A (SLTB010A revision A00 and A01): + ++------+-------------+-----------------------------------+ +| Pin | Function | Usage | ++======+=============+===================================+ +| PB0 | GPIO | LED0 (YELLOW) | ++------+-------------+-----------------------------------+ +| PB1 | GPIO | SW0 Push Button PB0 | ++------+-------------+-----------------------------------+ +| PA5 | UART_TX | UART TX Console VCOM_TX US1_TX #1 | ++------+-------------+-----------------------------------+ +| PA6 | UART_RX | UART RX Console VCOM_RX US1_RX #1 | ++------+-------------+-----------------------------------+ + +BRD4184B (SLTB010A revision A02 and newer): + ++------+-------------+-----------------------------------+ +| Pin | Function | Usage | ++======+=============+===================================+ +| PA4 | GPIO | LED0 (YELLOW) | ++------+-------------+-----------------------------------+ +| PB3 | GPIO | SW0 Push Button PB0 | ++------+-------------+-----------------------------------+ +| PA5 | UART_TX | UART TX Console VCOM_TX US1_TX #1 | ++------+-------------+-----------------------------------+ +| PA6 | UART_RX | UART RX Console VCOM_RX US1_RX #1 | ++------+-------------+-----------------------------------+ + +System Clock +============ + +The EFR32BG22 SoC is configured to use the 38.4 MHz external oscillator on the +board. + +Programming and Debugging +========================= + +Flashing an application +----------------------- + +Connect your device to your host computer using the USB port. +The sample application :zephyr:code-sample:`hello_world` is used for this example. +Build the Zephyr kernel and application, then flash it to the device: + +BRD4184A: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sltb010a@0 + :goals: flash + +BRD4184B: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sltb010a@2 + :goals: flash + +.. note:: + ``west flash`` requires `SEGGER J-Link software`_ to be installed on you host + computer. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you should be able to see on the corresponding Serial Port +the following message: + +.. code-block:: console + + Hello World! sltb010a + +Bluetooth +========= + +To use the BLE function, run the command below to retrieve necessary binary +blobs from the SiLabs HAL repository. + +.. code-block:: console + + west blobs fetch hal_silabs + +Then build the Zephyr kernel and a Bluetooth sample with the following +command. The :zephyr:code-sample:`bluetooth_observer` sample application is used in +this example. + +BRD4184A: + +.. zephyr-app-commands:: + :zephyr-app: samples/bluetooth/observer + :board: sltb010a@0 + :goals: build + +BRD4184B: + +.. zephyr-app-commands:: + :zephyr-app: samples/bluetooth/observer + :board: sltb010a@2 + :goals: build + + +.. _Thunderboard EFR32BG22 Website: + https://www.silabs.com/development-tools/thunderboard/thunderboard-bg22-kit + +.. _EFR32BG22-BRD4184A User Guide: + https://www.silabs.com/documents/public/user-guides/ug415-sltb010a-user-guide.pdf + +.. _EFR32BG22-BRD4184B User Guide: + https://www.silabs.com/documents/public/user-guides/ug464-brd4184b-user-guide.pdf + +.. _EFR32BG22-BRD4184A Schematics: + https://www.silabs.com/documents/public/schematic-files/BRD4184A-A01-schematic.pdf + +.. _EFR32BG22-BRD4184B Schematics: + https://www.silabs.com/documents/public/schematic-files/BRD4184B-A02-schematic.pdf + +.. _EFR32BG22 Website: + https://www.silabs.com/wireless/bluetooth/efr32bg22-series-2-socs + +.. _EFR32BG22 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efr32bg22-datasheet.pdf + +.. _EFR32xG22 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efr32xg22-rm.pdf + +.. _SEGGER J-Link software: + https://www.segger.com/downloads/jlink diff --git a/boards/silabs/efr32_thunderboard/doc/efr32bg_sltb010a.jpg b/boards/silabs/dev_kits/sltb010a/doc/sltb010a.jpg similarity index 100% rename from boards/silabs/efr32_thunderboard/doc/efr32bg_sltb010a.jpg rename to boards/silabs/dev_kits/sltb010a/doc/sltb010a.jpg diff --git a/boards/silabs/efr32_thunderboard/dts/bindings/silabs,gecko-wake-up-triggers.yaml b/boards/silabs/dev_kits/sltb010a/dts/bindings/silabs,gecko-wake-up-triggers.yaml similarity index 100% rename from boards/silabs/efr32_thunderboard/dts/bindings/silabs,gecko-wake-up-triggers.yaml rename to boards/silabs/dev_kits/sltb010a/dts/bindings/silabs,gecko-wake-up-triggers.yaml diff --git a/boards/silabs/efr32_thunderboard/pre_dt_board.cmake b/boards/silabs/dev_kits/sltb010a/pre_dt_board.cmake similarity index 100% rename from boards/silabs/efr32_thunderboard/pre_dt_board.cmake rename to boards/silabs/dev_kits/sltb010a/pre_dt_board.cmake diff --git a/boards/silabs/dev_kits/sltb010a/sltb010a.dts b/boards/silabs/dev_kits/sltb010a/sltb010a.dts new file mode 100644 index 00000000000..3f352ea6008 --- /dev/null +++ b/boards/silabs/dev_kits/sltb010a/sltb010a.dts @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2021 Sateesh Kotapati + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include "thunderboard.dtsi" + +/ { + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + sw0 = &button0; + spi0 = &usart0; + watchdog0 = &wdog0; + /* If enabled, MCUboot uses this for recovery mode entrance */ + mcuboot-led0 = &led0; + mcuboot-button0 = &button0; + }; + + chosen { + zephyr,code-partition = &slot0_partition; + zephyr,bt-hci = &bt_hci_silabs; + }; +}; + +&flash0 { + partitions { + /* Reserve 48 KiB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x0000c000>; + read-only; + }; + + /* Reserve 224 KiB for the application in slot 0 */ + slot0_partition: partition@c000 { + label = "image-0"; + reg = <0x0000c000 0x00038000>; + }; + + /* Reserve 224 KiB for the application in slot 1 */ + slot1_partition: partition@44000 { + label = "image-1"; + reg = <0x00044000 0x00038000>; + }; + + /* Set 16 KiB of storage at the end of the 512 KiB of flash */ + storage_partition: partition@7c000 { + label = "storage"; + reg = <0x0007c000 0x00004000>; + }; + }; +}; + +&sw_imu_enable { + enable-gpios = <&gpiob GECKO_PIN(4) GPIO_ACTIVE_HIGH>; +}; + +&bt_hci_silabs { + status = "okay"; +}; diff --git a/boards/silabs/dev_kits/sltb010a/sltb010a_0.overlay b/boards/silabs/dev_kits/sltb010a/sltb010a_0.overlay new file mode 100644 index 00000000000..c108c8e67db --- /dev/null +++ b/boards/silabs/dev_kits/sltb010a/sltb010a_0.overlay @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2021 Sateesh Kotapati + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + model = "Silicon Labs EFR32BG22 Thunderboard (SLTB010A) using BRD4184A"; + compatible = "silabs,efr32bg22c224f512im40", "silabs,sltb010a", + "silabs,efr32bg22"; +}; + +&sw_sensor_enable { + enable-gpios = <&gpioa GECKO_PIN(4) GPIO_ACTIVE_HIGH>; +}; + +&sw_mic_enable { + enable-gpios = <&gpioa GECKO_PIN(0) GPIO_ACTIVE_HIGH>; +}; diff --git a/boards/silabs/dev_kits/sltb010a/sltb010a_0.yaml b/boards/silabs/dev_kits/sltb010a/sltb010a_0.yaml new file mode 100644 index 00000000000..8cbf1832eac --- /dev/null +++ b/boards/silabs/dev_kits/sltb010a/sltb010a_0.yaml @@ -0,0 +1,18 @@ +identifier: sltb010a@0 +name: Thunderboard EFR32BG22 (SLTB010A, BRD4184A) +type: mcu +arch: arm +ram: 32 +flash: 512 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - bluetooth + - counter + - gpio + - uart + - i2c + - spi +vendor: silabs diff --git a/boards/silabs/dev_kits/sltb010a/sltb010a_2.overlay b/boards/silabs/dev_kits/sltb010a/sltb010a_2.overlay new file mode 100644 index 00000000000..224722da280 --- /dev/null +++ b/boards/silabs/dev_kits/sltb010a/sltb010a_2.overlay @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2021 Sateesh Kotapati + * Copyright (c) 2023 Piotr Dymacz + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + model = "Silicon Labs EFR32BG22 Thunderboard (SLTB010A) using BRD4184B"; + compatible = "silabs,efr32bg22c224f512im40", "silabs,sltb010a", + "silabs,efr32bg22"; +}; + +&button0 { + gpios = <&gpiob GECKO_PIN(3) GPIO_ACTIVE_LOW>; +}; + +&led0 { + gpios = <&gpioa GECKO_PIN(4) GPIO_ACTIVE_HIGH>; +}; + +&sw_sensor_enable { + enable-gpios = <&gpioc GECKO_PIN(6) GPIO_ACTIVE_HIGH>; +}; + +&sw_mic_enable { + enable-gpios = <&gpioc GECKO_PIN(7) GPIO_ACTIVE_HIGH>; +}; diff --git a/boards/silabs/dev_kits/sltb010a/sltb010a_2.yaml b/boards/silabs/dev_kits/sltb010a/sltb010a_2.yaml new file mode 100644 index 00000000000..2024a279aeb --- /dev/null +++ b/boards/silabs/dev_kits/sltb010a/sltb010a_2.yaml @@ -0,0 +1,18 @@ +identifier: sltb010a@2 +name: Thunderboard EFR32BG22 (SLTB010A, BRD4184B) +type: mcu +arch: arm +ram: 32 +flash: 512 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - bluetooth + - counter + - gpio + - uart + - i2c + - spi +vendor: silabs diff --git a/boards/silabs/efr32_thunderboard/efr32bg22_brd4184a_defconfig b/boards/silabs/dev_kits/sltb010a/sltb010a_defconfig similarity index 100% rename from boards/silabs/efr32_thunderboard/efr32bg22_brd4184a_defconfig rename to boards/silabs/dev_kits/sltb010a/sltb010a_defconfig diff --git a/boards/silabs/efr32_thunderboard/thunderboard.dtsi b/boards/silabs/dev_kits/sltb010a/thunderboard.dtsi similarity index 100% rename from boards/silabs/efr32_thunderboard/thunderboard.dtsi rename to boards/silabs/dev_kits/sltb010a/thunderboard.dtsi diff --git a/boards/silabs/dev_kits/xg24_dk2601b/Kconfig b/boards/silabs/dev_kits/xg24_dk2601b/Kconfig new file mode 100644 index 00000000000..f346dac95af --- /dev/null +++ b/boards/silabs/dev_kits/xg24_dk2601b/Kconfig @@ -0,0 +1,12 @@ +# EFR32XG24 DK2601B board + +# Copyright (c) 2022, Silicon Labs +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_XG24_DK2601B + +module = BOARD_EFR32MG24 +module-str = Board Control +source "subsys/logging/Kconfig.template.log_config" + +endif # BOARD_XG24_DK2601B diff --git a/boards/silabs/dev_kits/xg24_dk2601b/Kconfig.defconfig b/boards/silabs/dev_kits/xg24_dk2601b/Kconfig.defconfig new file mode 100644 index 00000000000..01e02d66d11 --- /dev/null +++ b/boards/silabs/dev_kits/xg24_dk2601b/Kconfig.defconfig @@ -0,0 +1,45 @@ +# EFR32XG24 DK2601B board + +# Copyright (c) 2021, Sateesh Kotapati +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_XG24_DK2601B + +config CMU_HFXO_FREQ + default 40000000 + +config CMU_LFXO_FREQ + default 32768 + +config FLASH_BASE_ADDRESS + hex + default 0x08000000 + +if SOC_GECKO_USE_RAIL + +config FPU + default y + +endif # SOC_GECKO_USE_RAIL + +if BT + +config FPU + default y + +config COMMON_LIBC_MALLOC_ARENA_SIZE + default 8192 + +config MAIN_STACK_SIZE + default 2304 + +if SHELL + +config SHELL_STACK_SIZE + default 4096 + +endif # SHELL + +endif # BT + +endif # BOARD_XG24_DK2601B diff --git a/boards/silabs/dev_kits/xg24_dk2601b/Kconfig.xg24_dk2601b b/boards/silabs/dev_kits/xg24_dk2601b/Kconfig.xg24_dk2601b new file mode 100644 index 00000000000..bf4ac3677f1 --- /dev/null +++ b/boards/silabs/dev_kits/xg24_dk2601b/Kconfig.xg24_dk2601b @@ -0,0 +1,7 @@ +# EFR32XG24 DK2601B board + +# Copyright (c) 2021, Sateesh Kotapati +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_XG24_DK2601B + select SOC_PART_NUMBER_EFR32MG24B310F1536IM48 diff --git a/boards/silabs/dev_kits/xg24_dk2601b/board.c b/boards/silabs/dev_kits/xg24_dk2601b/board.c new file mode 100644 index 00000000000..601b759b6ca --- /dev/null +++ b/boards/silabs/dev_kits/xg24_dk2601b/board.c @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2021 Sateesh Kotapati + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +#ifdef CONFIG_SOC_GECKO_DEV_INIT +#include "em_cmu.h" +#endif + +LOG_MODULE_REGISTER(efr32xg24_dk2601b, CONFIG_BOARD_EFR32MG24_LOG_LEVEL); + +static int efr32xg24_dk2601b_init_clocks(void); + +static int efr32xg24_dk2601b_init(void) +{ + int ret; + +#ifdef CONFIG_SOC_GECKO_DEV_INIT + efr32xg24_dk2601b_init_clocks(); +#endif + static struct gpio_dt_spec wake_up_gpio_dev = + GPIO_DT_SPEC_GET(DT_NODELABEL(wake_up_trigger), gpios); + + + if (!gpio_is_ready_dt(&wake_up_gpio_dev)) { + LOG_ERR("Wake-up GPIO device was not found!\n"); + return -ENODEV; + } + ret = gpio_pin_configure_dt(&wake_up_gpio_dev, GPIO_OUTPUT_ACTIVE); + if (ret < 0) { + return ret; + } + + return 0; +} + +#ifdef CONFIG_SOC_GECKO_DEV_INIT +static int efr32xg24_dk2601b_init_clocks(void) +{ + CMU_ClockSelectSet(cmuClock_SYSCLK, cmuSelect_HFRCODPLL); +#if defined(_CMU_EM01GRPACLKCTRL_MASK) + CMU_ClockSelectSet(cmuClock_EM01GRPACLK, cmuSelect_HFRCODPLL); +#endif +#if defined(_CMU_EM01GRPBCLKCTRL_MASK) + CMU_ClockSelectSet(cmuClock_EM01GRPBCLK, cmuSelect_HFRCODPLL); +#endif + CMU_ClockSelectSet(cmuClock_EM23GRPACLK, cmuSelect_LFRCO); + CMU_ClockSelectSet(cmuClock_EM4GRPACLK, cmuSelect_LFRCO); +#if defined(RTCC_PRESENT) + CMU_ClockSelectSet(cmuClock_RTCC, cmuSelect_LFRCO); +#endif +#if defined(SYSRTC_PRESENT) + CMU_ClockSelectSet(cmuClock_SYSRTC, cmuSelect_LFRCO); +#endif + CMU_ClockSelectSet(cmuClock_WDOG0, cmuSelect_LFRCO); +#if WDOG_COUNT > 1 + CMU_ClockSelectSet(cmuClock_WDOG1, cmuSelect_LFRCO); +#endif + + return 0; +} +#endif + +/* needs to be done after GPIO driver init */ +SYS_INIT(efr32xg24_dk2601b_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); diff --git a/boards/silabs/efr32xg24_dk2601b/board.cmake b/boards/silabs/dev_kits/xg24_dk2601b/board.cmake similarity index 100% rename from boards/silabs/efr32xg24_dk2601b/board.cmake rename to boards/silabs/dev_kits/xg24_dk2601b/board.cmake diff --git a/boards/silabs/dev_kits/xg24_dk2601b/board.yml b/boards/silabs/dev_kits/xg24_dk2601b/board.yml new file mode 100644 index 00000000000..f946744d228 --- /dev/null +++ b/boards/silabs/dev_kits/xg24_dk2601b/board.yml @@ -0,0 +1,5 @@ +board: + name: xg24_dk2601b + vendor: silabs + socs: + - name: efr32mg24b310f1536im48 diff --git a/boards/silabs/efr32xg24_dk2601b/doc/img/efr32xg24_dk2601b.jpg b/boards/silabs/dev_kits/xg24_dk2601b/doc/img/xg24_dk2601b.jpg similarity index 100% rename from boards/silabs/efr32xg24_dk2601b/doc/img/efr32xg24_dk2601b.jpg rename to boards/silabs/dev_kits/xg24_dk2601b/doc/img/xg24_dk2601b.jpg diff --git a/boards/silabs/dev_kits/xg24_dk2601b/doc/index.rst b/boards/silabs/dev_kits/xg24_dk2601b/doc/index.rst new file mode 100644 index 00000000000..069b1d8923f --- /dev/null +++ b/boards/silabs/dev_kits/xg24_dk2601b/doc/index.rst @@ -0,0 +1,184 @@ +.. _efr32mg24_dk2601b: + +EFR32xG24 Dev Kit (xG24-DK2601B) +################################ + +Overview +******** + +The EFR32MG24 Mighty Gecko Board dev kit contains +a Wireless System-On-Chip from the EFR32MG24 family built on an +ARM Cortex®-M33F processor with excellent low power capabilities. + +.. figure:: ./img/xg24_dk2601b.jpg + :height: 260px + :align: center + :alt: xG24-DK2601B Dev Kit board + + xG24-DK2601B (image courtesy of Silicon Labs) + +Hardware +******** + +- EFR32MG24B310F1536IM48-B Mighty Gecko SoC +- CPU core: ARM Cortex®-M33 with FPU +- Flash memory: 1536 kB +- RAM: 256 kB +- Transmit power: up to +20 dBm +- Operation frequency: 2.4 GHz +- Crystals for LFXO (32.768 kHz) and HFXO (38.4 MHz). +- On board sensors: + + - Silicon Labs Si7021 relative humidity & temperature sensor + - Silicon Labs Si7210 hall effect sensor + - 2x TDK InvenSense ICS-43434 MEMS microphones with I2S output + - TDK InvenSense ICM-20689 6-axis inertial measurement sensor + - Vishay VEML6035 ambient light sensor + - Bosch BMP384 pressure sensor with internal temperature sensor + +For more information about the EFR32MG24 SoC and BRD2601B board, refer to these +documents: + +- `EFR32MG24 Website`_ +- `EFR32MG24 Datasheet`_ +- `EFR32xG24 Reference Manual`_ +- `BRD2601B User Guide`_ + +Supported Features +================== + +The board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | stimer | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | semailbox | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| I2C(M/S) | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| RADIO | on-chip | bluetooth | ++-----------+------------+-------------------------------------+ + +Other hardware features are currently not supported by the port. + +Connections and IOs +=================== + +In the following table, the column **Name** contains Pin names. For example, PA2 +means Pin number 2 on PORTA, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Name | Function | Usage | ++=======+=============+=====================================+ +| PA4 | GPIO | LED0 | ++-------+-------------+-------------------------------------+ +| PB0 | GPIO | LED1 | ++-------+-------------+-------------------------------------+ +| PB2 | GPIO | Push Button 0 | ++-------+-------------+-------------------------------------+ +| PB3 | GPIO | Push Button 1 | ++-------+-------------+-------------------------------------+ +| PA5 | USART0_TX | UART Console VCOM_TX US0_TX | ++-------+-------------+-------------------------------------+ +| PA6 | USART0_RX | UART Console VCOM_RX US0_RX | ++-------+-------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b_defconfig` + +System Clock +============ + +The EFR32MG24 SoC is configured to use the 39 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFR32MG24 SoC has one USART and two EUSARTs. +USART0 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +.. note:: + Before using the kit the first time, you should update the J-Link firmware + from `J-Link-Downloads`_ + +Flashing +======== + +The sample application :zephyr:code-sample:`hello_world` is used for this example. +Build the Zephyr kernel and application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xg24_dk2601b + :goals: build + +Connect the xg24_dk2601b to your host computer using the USB port and you +should see a USB connection. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you'll see the following message on the corresponding serial port +terminal session: + +.. code-block:: console + + Hello World! xg24_dk2601b + +Bluetooth +========= + +To use the BLE function, run the command below to retrieve necessary binary +blobs from the SiLabs HAL repository. + +.. code-block:: console + + west blobs fetch hal_silabs + +Then build the Zephyr kernel and a Bluetooth sample with the following +command. The :zephyr:code-sample:`bluetooth_observer` sample application is used in +this example. + +.. zephyr-app-commands:: + :zephyr-app: samples/bluetooth/observer + :board: xg24_dk2601b + :goals: build + +.. _EFR32MG24 Website: + https://www.silabs.com/wireless/zigbee/efr32mg24-series-2-socs# + +.. _EFR32MG24 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efr32mg24-datasheet.pdf + +.. _EFR32xG24 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efr32xg24-rm.pdf + +.. _BRD2601B User Guide: + https://www.silabs.com/documents/public/user-guides/ug524-brd2601b-user-guide.pdf + +.. _J-Link-Downloads: + https://www.segger.com/downloads/jlink diff --git a/boards/silabs/efr32xg24_dk2601b/dts/bindings/silabs,gecko-wake-up-trigger.yaml b/boards/silabs/dev_kits/xg24_dk2601b/dts/bindings/silabs,gecko-wake-up-trigger.yaml similarity index 100% rename from boards/silabs/efr32xg24_dk2601b/dts/bindings/silabs,gecko-wake-up-trigger.yaml rename to boards/silabs/dev_kits/xg24_dk2601b/dts/bindings/silabs,gecko-wake-up-trigger.yaml diff --git a/boards/silabs/efr32mg_sltb004a/pre_dt_board.cmake b/boards/silabs/dev_kits/xg24_dk2601b/pre_dt_board.cmake similarity index 100% rename from boards/silabs/efr32mg_sltb004a/pre_dt_board.cmake rename to boards/silabs/dev_kits/xg24_dk2601b/pre_dt_board.cmake diff --git a/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.dts b/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.dts new file mode 100644 index 00000000000..ac03b32ff37 --- /dev/null +++ b/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.dts @@ -0,0 +1,184 @@ +/* + * Copyright (c) 2020 TriaGnoSys GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include + +/ { + model = "Silicon Labs BRD2601B (xG24 Dev Kit)"; + compatible = "silabs,xg24_brd2601b", "silabs,efr32mg24"; + + chosen { + zephyr,console = &usart0; + zephyr,shell-uart = &usart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,bt-hci = &bt_hci_silabs; + }; + + aliases { + led0 = &red_led; + led1 = &green_led; + led2 = &blue_led; + sw0 = &button0; + sw1 = &button1; + watchdog0 = &wdog0; + }; + + leds { + compatible = "gpio-leds"; + red_led: led_2 { + gpios = <&gpiod GECKO_PIN(2) GPIO_ACTIVE_LOW>; + }; + green_led: led_0 { + gpios = <&gpioa GECKO_PIN(4) GPIO_ACTIVE_LOW>; + }; + blue_led: led_1 { + gpios = <&gpiob GECKO_PIN(0) GPIO_ACTIVE_LOW>; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpiob GECKO_PIN(2) GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + button1: button_1 { + gpios = <&gpiob GECKO_PIN(3) GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; + + wake_up_trigger: gpio-wake-up { + compatible = "silabs,gecko-wake-up-trigger"; + gpios = <&gpioa GECKO_PIN(5) GPIO_ACTIVE_LOW>; + }; + + sensor_enable: gpio_switch_0 { + compatible = "regulator-fixed"; + regulator-name = "sensor_enable"; + enable-gpios = <&gpioc GECKO_PIN(9) GPIO_ACTIVE_HIGH>; + regulator-boot-on; + }; +}; + +&cpu0 { + clock-frequency = <78000000>; +}; + +&usart0 { + current-speed = <115200>; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + status = "okay"; + + veml6035: veml6035@29 { + compatible = "vishay,veml7700"; + reg = <0x29>; + status = "okay"; + }; + + si7210: si7210@30 { + compatible = "silabs,si7210"; + reg = <0x30>; + status = "okay"; + }; + + si7021: si7021@40 { + compatible = "silabs,si7006"; + reg = <0x40>; + status = "okay"; + }; +}; + +&gpio { + status = "okay"; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&wdog0 { + status = "okay"; +}; + +&se { + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 48 kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 0x0000c000>; + read-only; + }; + + /* Reserve 464 kB for the application in slot 0 */ + slot0_partition: partition@c000 { + label = "image-0"; + reg = <0x0000c000 0x00074000>; + }; + + /* Reserve 464 kB for the application in slot 1 */ + slot1_partition: partition@80000 { + label = "image-1"; + reg = <0x00080000 0x00074000>; + }; + + /* Reserve 32 kB for the scratch partition */ + scratch_partition: partition@f4000 { + label = "image-scratch"; + reg = <0x000f4000 0x00008000>; + }; + + /* Set 528Kb of storage at the end of the 1024Kb of flash */ + storage_partition: partition@fc000 { + label = "storage"; + reg = <0x000fc000 0x00084000>; + }; + }; +}; + +&adc0 { + status = "okay"; +}; + +&stimer0 { + status = "okay"; +}; + +&bt_hci_silabs { + status = "okay"; +}; diff --git a/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.yaml b/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.yaml new file mode 100644 index 00000000000..ed39649abe6 --- /dev/null +++ b/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.yaml @@ -0,0 +1,20 @@ +identifier: xg24_dk2601b +name: xG24 Dev Kit (xG24-DK2601B, BRD2601B) +type: mcu +arch: arm +ram: 256 +flash: 1536 +toolchain: + - zephyr + - gnuarmemb +supported: + - bluetooth + - counter + - gpio + - uart + - watchdog +testing: + ignore_tags: + - pm + - hwinfo +vendor: silabs diff --git a/boards/silabs/efr32xg24_dk2601b/efr32xg24_dk2601b_defconfig b/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b_defconfig similarity index 100% rename from boards/silabs/efr32xg24_dk2601b/efr32xg24_dk2601b_defconfig rename to boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b_defconfig diff --git a/boards/silabs/dev_kits/xg27_dk2602a/CMakeLists.txt b/boards/silabs/dev_kits/xg27_dk2602a/CMakeLists.txt new file mode 100644 index 00000000000..ca93e65ac91 --- /dev/null +++ b/boards/silabs/dev_kits/xg27_dk2602a/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2021 Sateesh Kotapati +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_UART_GECKO) + zephyr_library() + zephyr_library_sources(board.c) +endif() diff --git a/boards/silabs/dev_kits/xg27_dk2602a/Kconfig b/boards/silabs/dev_kits/xg27_dk2602a/Kconfig new file mode 100644 index 00000000000..965bfde207a --- /dev/null +++ b/boards/silabs/dev_kits/xg27_dk2602a/Kconfig @@ -0,0 +1,8 @@ +# EFR32 Thunderboard-style boards + +# Copyright (c) 2022, Silicon Labs +# SPDX-License-Identifier: Apache-2.0 + +module = BOARD_XG27_DK2602A +module-str = Board Control +source "subsys/logging/Kconfig.template.log_config" diff --git a/boards/silabs/dev_kits/xg27_dk2602a/Kconfig.defconfig b/boards/silabs/dev_kits/xg27_dk2602a/Kconfig.defconfig new file mode 100644 index 00000000000..850f2cd8538 --- /dev/null +++ b/boards/silabs/dev_kits/xg27_dk2602a/Kconfig.defconfig @@ -0,0 +1,32 @@ +# Copyright (c) 2023 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config CMU_HFXO_FREQ + default 38400000 + +config CMU_LFXO_FREQ + default 32768 + +if SOC_GECKO_USE_RAIL + +config FPU + default y + +endif # SOC_GECKO_USE_RAIL + +if BT + +config FPU + default y + +config COMMON_LIBC_MALLOC_ARENA_SIZE + default 8192 + +config MAIN_STACK_SIZE + default 3072 if PM + default 2304 + +endif # BT + +config REGULATOR + default y if SI7210 diff --git a/boards/silabs/dev_kits/xg27_dk2602a/Kconfig.xg27_dk2602a b/boards/silabs/dev_kits/xg27_dk2602a/Kconfig.xg27_dk2602a new file mode 100644 index 00000000000..d5f2945cdfd --- /dev/null +++ b/boards/silabs/dev_kits/xg27_dk2602a/Kconfig.xg27_dk2602a @@ -0,0 +1,7 @@ +# EFR32BG SLTB010A board + +# Copyright (c) 2021, Sateesh Kotapati +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_XG27_DK2602A + select SOC_PART_NUMBER_EFR32BG27C140F768IM40 diff --git a/boards/silabs/dev_kits/xg27_dk2602a/board.c b/boards/silabs/dev_kits/xg27_dk2602a/board.c new file mode 100644 index 00000000000..f26befcf508 --- /dev/null +++ b/boards/silabs/dev_kits/xg27_dk2602a/board.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2021 Sateesh Kotapati + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#ifdef CONFIG_SOC_GECKO_DEV_INIT +#include "em_cmu.h" +#endif + + +LOG_MODULE_REGISTER(dev_kit, CONFIG_BOARD_XG27_DK2602A_LOG_LEVEL); + +static int dev_kit_init_clocks(void); + +static int dev_kit_init(void) +{ + int ret; + +#ifdef CONFIG_SOC_GECKO_DEV_INIT + dev_kit_init_clocks(); +#endif + static struct gpio_dt_spec wake_up_gpio_dev = + GPIO_DT_SPEC_GET(DT_NODELABEL(wake_up_trigger), gpios); + + + if (!gpio_is_ready_dt(&wake_up_gpio_dev)) { + LOG_ERR("Wake-up GPIO device was not found!\n"); + return -ENODEV; + } + ret = gpio_pin_configure_dt(&wake_up_gpio_dev, GPIO_OUTPUT_ACTIVE); + if (ret < 0) { + return ret; + } + + return 0; +} + +#ifdef CONFIG_SOC_GECKO_DEV_INIT +static int dev_kit_init_clocks(void) +{ + CMU_ClockSelectSet(cmuClock_SYSCLK, cmuSelect_HFRCODPLL); +#if defined(_CMU_EM01GRPACLKCTRL_MASK) + CMU_ClockSelectSet(cmuClock_EM01GRPACLK, cmuSelect_HFRCODPLL); +#endif +#if defined(_CMU_EM01GRPBCLKCTRL_MASK) + CMU_ClockSelectSet(cmuClock_EM01GRPBCLK, cmuSelect_HFRCODPLL); +#endif + CMU_ClockSelectSet(cmuClock_EM23GRPACLK, cmuSelect_LFRCO); +#if defined(RTCC_PRESENT) + CMU_ClockSelectSet(cmuClock_RTCC, cmuSelect_LFRCO); +#endif + CMU_ClockSelectSet(cmuClock_WDOG0, cmuSelect_LFRCO); + + return 0; +} +#endif + +/* needs to be done after GPIO driver init */ +SYS_INIT(dev_kit_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); diff --git a/boards/silabs/dev_kits/xg27_dk2602a/board.cmake b/boards/silabs/dev_kits/xg27_dk2602a/board.cmake new file mode 100644 index 00000000000..a5086fdebd9 --- /dev/null +++ b/boards/silabs/dev_kits/xg27_dk2602a/board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Silicon Laboratories Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=EFR32BG27CxxxF768" "--reset-after-load") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +board_runner_args(silabs_commander "--device=EFR32BG27C140F768IM40") +include(${ZEPHYR_BASE}/boards/common/silabs_commander.board.cmake) diff --git a/boards/silabs/dev_kits/xg27_dk2602a/board.yml b/boards/silabs/dev_kits/xg27_dk2602a/board.yml new file mode 100644 index 00000000000..83a3037a1a7 --- /dev/null +++ b/boards/silabs/dev_kits/xg27_dk2602a/board.yml @@ -0,0 +1,5 @@ +boards: + - name: xg27_dk2602a + vendor: silabs + socs: + - name: efr32bg27c140f768im40 diff --git a/boards/silabs/dev_kits/xg27_dk2602a/doc/index.rst b/boards/silabs/dev_kits/xg27_dk2602a/doc/index.rst new file mode 100644 index 00000000000..273b78e60ba --- /dev/null +++ b/boards/silabs/dev_kits/xg27_dk2602a/doc/index.rst @@ -0,0 +1,143 @@ +.. _xg27_dk2602a: + +EFR32xG27 Dev Kit (xG27-DK2602A) +################################ + +Silicon Labs xG27-DK2602A is a Dev Kit using the EFR32BG27 SoC. The kit +consists of the EFR32BG27 +8 dBm Dev Kit Board (BRD2602A). + +.. figure:: ./xg27_dk2602a.png + :height: 260px + :align: center + :alt: xG27-DK2602A + + xG27-DK2602A (image courtesy of Silicon Labs) + +Hardware +******** + +- EFR32BG27 Blue Gecko Wireless SoC with up to 76.8 MHz operating frequency +- ARM® Cortex® M33 core with 64 kB RAM and 768 kB Flash +- Macronix ultra low power 8-Mbit SPI flash (MX25R8035F) +- 2.4 GHz ceramic antenna for wireless transmission +- Silicon Labs Si7021 relative humidity and temperature sensor +- Vishay VEML6035 low power, high sensitivity ambient light Sensor +- Silicon Labs Si7210 hall effect sensor +- TDK InvenSense ICM-20689 6-axis inertial sensor +- Pair of PDM microphones +- One LED and one push button +- Power enable signals and isolation switches for ultra low power operation +- On-board SEGGER J-Link debugger for easy programming and debugging, which + includes a USB virtual COM port and Packet Trace Interface (PTI) +- Mini Simplicity connector for access to energy profiling and advanced wireless + network debugging +- Breakout pads for GPIO access and connection to external hardware +- Reset button +- CR2032 coin cell holder and external battery connector + +For more information, refer to these documents: + +- `xG27 Dev Kit User's Guide`_ + +Supported Features +================== + +The xg27_dk2602a board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ + +Flashing +======== + +The xG27 Dev Kit includes an embedded `J-Link`_ adapter built around +EFM32GG12 microcontroller (not user-programmable). +The adapter provides: + +- SWD interface to EFR32BG27 for flashing and debugging. +- SWO trace interface to EFR32BG27 for tracing. +- UART interface to EFR32BG27 for console access. +- A USB connection to the host computer, which exposes CDC-ACM Serial Port + endpoints for access to the console UART interface and proprietary J-Link + endpoints for access to the SWD and SWO interfaces. + +UART functionality of the adapter is accessible via standard CDC-ACM USB driver +present in most desktop operating systems and any standard serial port terminal +program e.g. `picocom`_. + +SWD and SWO functionality is accessible via `Simplicity Commander`_. + +The simplest way to flash the board is by using West, which runs Simplicity +Commander in unattended mode and passes all the necessary arguments to it. + +- If Simplicity Commander is installed in the system and the directory in + which ``commander`` executable is located is present in the :envvar:`PATH` environment + variable: + + .. code-block:: console + + west flash + +- Otherwise, one should specify full path to the ``commander`` executable: + + .. code-block:: console + + west flash --commander /commander + +- In case several J-Link adapters are connected, you must specify serial number + of the adapter which should be used for flashing: + + .. code-block:: console + + west flash --dev-id + +Programming and Debugging +========================= + +The sample application :zephyr:code-sample:`hello_world` is used for this example. +Build the Zephyr kernel and application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xg27_dk2602a + :goals: build + +Connect your device to your host computer using the USB port and you +should see a USB connection. Use ``west``'s flash command + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you should be able to see on the corresponding Serial Port +the following message: + +.. code-block:: console + + Hello World! xg27_dk2602a + +.. _picocom: + https://github.com/npat-efault/picocom + +.. _J-Link: + https://www.segger.com/jlink-debug-probes.html + +.. _Simplicity Commander: + https://www.silabs.com/developers/mcu-programming-options + +.. _xG27 Dev Kit User's Guide: + https://www.silabs.com/documents/public/user-guides/ug554-brd2602a-user-guide.pdf diff --git a/boards/silabs/dev_kits/xg27_dk2602a/doc/xg27_dk2602a.png b/boards/silabs/dev_kits/xg27_dk2602a/doc/xg27_dk2602a.png new file mode 100644 index 00000000000..0bb9399b11b Binary files /dev/null and b/boards/silabs/dev_kits/xg27_dk2602a/doc/xg27_dk2602a.png differ diff --git a/boards/silabs/dev_kits/xg27_dk2602a/dts/bindings/silabs,gecko-wake-up-triggers.yaml b/boards/silabs/dev_kits/xg27_dk2602a/dts/bindings/silabs,gecko-wake-up-triggers.yaml new file mode 100644 index 00000000000..fd49c3732ca --- /dev/null +++ b/boards/silabs/dev_kits/xg27_dk2602a/dts/bindings/silabs,gecko-wake-up-triggers.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2022, Antmicro +# SPDX-License-Identifier: Apache-2.0 + +description: GPIO Wake Up Trigger for EFR32BG22/EFR32BG27 + +compatible: "silabs,gecko-wake-up-trigger" + +include: base.yaml + +properties: + gpios: + type: phandle-array + required: true + description: | + GPIO used as wake up trigger from EM4 sleep diff --git a/boards/silabs/efr32xg24_dk2601b/pre_dt_board.cmake b/boards/silabs/dev_kits/xg27_dk2602a/pre_dt_board.cmake similarity index 100% rename from boards/silabs/efr32xg24_dk2601b/pre_dt_board.cmake rename to boards/silabs/dev_kits/xg27_dk2602a/pre_dt_board.cmake diff --git a/boards/silabs/dev_kits/xg27_dk2602a/thunderboard.dtsi b/boards/silabs/dev_kits/xg27_dk2602a/thunderboard.dtsi new file mode 100644 index 00000000000..71979837476 --- /dev/null +++ b/boards/silabs/dev_kits/xg27_dk2602a/thunderboard.dtsi @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2023 Antmicro + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + chosen { + zephyr,bt-c2h-uart = &usart1; + zephyr,console = &usart1; + zephyr,shell-uart = &usart1; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpiob GECKO_PIN(0) GPIO_ACTIVE_HIGH>; + label = "LED 0"; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpiob GECKO_PIN(1) GPIO_ACTIVE_LOW>; + label = "User Push Button 0"; + zephyr,code = ; + }; + }; + + wake_up_trigger: gpio-wake-up { + compatible = "silabs,gecko-wake-up-trigger"; + gpios = <&gpioa GECKO_PIN(5) GPIO_ACTIVE_LOW>; + }; + + /* GPIOs that power up different sensors */ + sw_sensor_enable: gpio_switch_0 { + compatible = "regulator-fixed"; + status = "okay"; + regulator-name = "sw_sensor_enable"; + startup-delay-us = <100000>; + /* Always on since sensor drivers won't enable it automatically */ + regulator-always-on; + }; + + sw_mic_enable: gpio_switch_1 { + compatible = "regulator-fixed"; + status = "okay"; + regulator-name = "sw_mic_enable"; + startup-delay-us = <100000>; + }; + + sw_imu_enable: gpio_switch_2 { + compatible = "regulator-fixed"; + status = "okay"; + regulator-name = "sw_imu_enable"; + startup-delay-us = <100000>; + }; + +}; + +&cpu0 { + clock-frequency = <76800000>; +}; + +&pstate_em3 { + status = "disabled"; +}; + +&usart0 { + status = "okay"; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; + + cs-gpios = <&gpioc 3 GPIO_ACTIVE_LOW>; + + mx25r80: mx25r8035f@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + size = <0x800000>; + jedec-id = [c2 28 14]; + sfdp-bfp = [ + e5 20 f1 ff ff ff 7f 00 44 eb 08 6b 08 3b 04 bb + ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 + 10 d8 00 ff 23 72 f5 00 82 ed 04 b7 44 83 38 44 + 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff + ]; + }; +}; + +&usart1 { + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&usart1_default>; + pinctrl-names = "default"; +}; + +&wdog0 { + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&gpio { + location-swo = <0>; + status = "okay"; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; +}; + +&gpioc { + status = "okay"; +}; + +&burtc0 { + status = "okay"; +}; + +&stimer0 { + status = "okay"; +}; + +&trng { + status = "okay"; +}; + +&pinctrl { + i2c0_default: i2c0_default { + group1 { + psels = , + , + , + ; + }; + }; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + status = "okay"; + + si7210@30 { + compatible = "silabs,si7210"; + status = "okay"; + reg = <0x30>; + }; +}; + +&adc0 { + status = "okay"; +}; diff --git a/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.dts b/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.dts new file mode 100644 index 00000000000..6dba2bfa648 --- /dev/null +++ b/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.dts @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2023 Antmicro + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include "thunderboard.dtsi" + +/ { + model = "Silicon Labs xG27-DK2602A Dev Kit"; + compatible = "silabs,efr32bg27c140f768im40", "silabs,xg27_dk2602a", + "silabs,efr32bg27"; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + sw0 = &button0; + spi0 = &usart0; + watchdog0 = &wdog0; + /* If enabled, MCUboot uses this for recovery mode entrance */ + mcuboot-led0 = &led0; + mcuboot-button0 = &button0; + }; + + chosen { + zephyr,code-partition = &slot0_partition; + zephyr,bt-hci = &bt_hci_silabs; + }; +}; + +&flash0 { + partitions { + /* Reserve 48 KiB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x0000c000>; + read-only; + }; + + /* Reserve 328 KiB for the application in slot 0 */ + slot0_partition: partition@c000 { + label = "image-0"; + reg = <0x0000c000 0x00052000>; + }; + + /* Reserve 328 KiB for the application in slot 1 */ + slot1_partition: partition@5e000 { + label = "image-1"; + reg = <0x0005e000 0x00052000>; + }; + + /* Set 64 KiB of storage at the end of the 768 KiB of flash */ + storage_partition: partition@b0000 { + label = "storage"; + reg = <0x000b0000 0x00010000>; + }; + }; +}; + +&led0 { + gpios = <&gpioa GECKO_PIN(4) GPIO_ACTIVE_HIGH>; +}; + +&sw_sensor_enable { + enable-gpios = <&gpioc GECKO_PIN(6) GPIO_ACTIVE_HIGH>; +}; + + +&sw_mic_enable { + enable-gpios = <&gpioc GECKO_PIN(7) GPIO_ACTIVE_HIGH>; +}; + + +&sw_imu_enable { + enable-gpios = <&gpiob GECKO_PIN(4) GPIO_ACTIVE_HIGH>; +}; + +&button0 { + gpios = <&gpiob GECKO_PIN(3) GPIO_ACTIVE_LOW>; +}; + +&bt_hci_silabs { + status = "okay"; +}; diff --git a/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.yaml b/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.yaml new file mode 100644 index 00000000000..bb6a214b786 --- /dev/null +++ b/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.yaml @@ -0,0 +1,16 @@ +identifier: xg27_dk2602a +name: xG27 Dev Kit (xG27-DK2602A, BRD2602A) +type: mcu +arch: arm +ram: 64 +flash: 768 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - bluetooth + - counter + - gpio + - uart +vendor: silabs diff --git a/boards/silabs/efr32_thunderboard/efr32bg22_brd4184b_defconfig b/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a_defconfig similarity index 100% rename from boards/silabs/efr32_thunderboard/efr32bg22_brd4184b_defconfig rename to boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a_defconfig diff --git a/boards/silabs/efm32gg_sltb009a/Kconfig.defconfig b/boards/silabs/efm32gg_sltb009a/Kconfig.defconfig deleted file mode 100644 index a24eda68abd..00000000000 --- a/boards/silabs/efm32gg_sltb009a/Kconfig.defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# EFM32GG SLTB009A default board configuration -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EFM32GG_SLTB009A - -config CMU_HFXO_FREQ - default 50000000 - -config CMU_HFRCO_FREQ - default 72000000 - -config CMU_LFXO_FREQ - default 32768 - -config LOG_BACKEND_SWO_FREQ_HZ - default 875000 - depends on LOG_BACKEND_SWO - -endif # BOARD_EFM32GG_SLTB009A diff --git a/boards/silabs/efm32gg_sltb009a/Kconfig.efm32gg_sltb009a b/boards/silabs/efm32gg_sltb009a/Kconfig.efm32gg_sltb009a deleted file mode 100644 index e1f93ff9da9..00000000000 --- a/boards/silabs/efm32gg_sltb009a/Kconfig.efm32gg_sltb009a +++ /dev/null @@ -1,6 +0,0 @@ -# EFM32GG SLTB009A board configuration -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFM32GG_SLTB009A - select SOC_PART_NUMBER_EFM32GG12B810F1024GM64 diff --git a/boards/silabs/efm32gg_sltb009a/board.yml b/boards/silabs/efm32gg_sltb009a/board.yml deleted file mode 100644 index 388301f55e1..00000000000 --- a/boards/silabs/efm32gg_sltb009a/board.yml +++ /dev/null @@ -1,5 +0,0 @@ -board: - name: efm32gg_sltb009a - vendor: silabs - socs: - - name: efm32gg12b810f1024gm64 diff --git a/boards/silabs/efm32gg_sltb009a/doc/index.rst b/boards/silabs/efm32gg_sltb009a/doc/index.rst deleted file mode 100644 index e27fcc34ba0..00000000000 --- a/boards/silabs/efm32gg_sltb009a/doc/index.rst +++ /dev/null @@ -1,165 +0,0 @@ -.. _efm32gg_sltb009a: - -EFM32GG12 Thunderboard Kit -########################## - -Overview -******** - -The EFM32GG12 Thunderboard Kit (SLTB009A) is an evaluation platform for the EFM32GG12 GiantGecko Microcontroller, -featuring an ARM Cortex-M4 with FPU, 1024kB flash, and 192kB RAM. - -.. figure:: efm32gg12-thunderboard-kit.jpg - :align: center - :alt: SLTB009A - - SLTB009A (Credit: Silicon Labs) - -Hardware -******** - -- PDM stereo microphones -- USB connectivity -- On-board Segger J-Link USB debugger -- 2 user buttons and 2 LEDs -- USB C connector - -For more information about the WGM160P and SLTB009A board: - -- `SLTB009A Website`_ -- `SLTB009A User Guide`_ -- `EFM32GG12 Datasheet`_ -- `EFM32GG12 Reference Manual`_ - -Supported Features -================== - -The efm32gg_sltb009a board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtcc | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c port-polling | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in -:zephyr_file:`boards/silabs/efm32gg_sltb009a/efm32gg_sltb009a_defconfig` - -Connections and IOs -=================== - -The EFM32GG12 MCU has six GPIO controllers (PORTA to PORTF), all of which are -currently enabled for the SLTB009A board. - -In the following table, the column **Name** contains pin names. For example, PE1 -means pin number 1 on PORTE, as used in the board's datasheets and manuals. - -+-------+-------------+-------------------------------------+ -| Name | Function | Usage | -+=======+=============+=====================================+ -| PE12 | GPIO | LED0 | -+-------+-------------+-------------------------------------+ -| PA13 | GPIO | LED1 | -+-------+-------------+-------------------------------------+ -| PD5 | GPIO | Push Button PB0 | -+-------+-------------+-------------------------------------+ -| PD8 | GPIO | Push Button PB1 | -+-------+-------------+-------------------------------------+ -| PE7 | UART_TX | UART TX Console VCOM_TX US0_TX #1 | -+-------+-------------+-------------------------------------+ -| PE6 | UART_RX | UART RX Console VCOM_RX US0_RX #1 | -+-------+-------------+-------------------------------------+ -| PC0 | I2C_SDA | SENSOR_I2C_SDA I2C0_SDA #1 | -+-------+-------------+-------------------------------------+ -| PC1 | I2C_SCL | SENSOR_I2C_SCL I2C0_SCL #1 | -+-------+-------------+-------------------------------------+ -| PC4 | I2C_SDA | SENSOR_I2C_SDA I2C1_SDA #1 | -+-------+-------------+-------------------------------------+ -| PC5 | I2C_SCL | SENSOR_I2C_SCL I2C1_SCL #1 | -+-------+-------------+-------------------------------------+ - - -System Clock -============ - -The EFM32GG12 MCU is configured to work at 72 MHz. - -Serial Port -=========== - -The EFM32GG12 SoC has five USARTs, two UARTs and two Low Energy UARTs (LEUART). -USART0 is connected to the board controller and is used for the console. - -Programming and Debugging -************************* - -.. note:: - Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ - -Flashing -======== - -The SLTB009A includes an `J-Link`_ serial and debug adaptor built into the -board. The adaptor provides: - -- A USB connection to the host computer -- A physical UART connection which is relayed over interface USB serial port. - -Flashing an application to SLTB009A --------------------------------------- - -Connect the SLTB009A to your host computer using the USB port. - -Here is an example to build and flash the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efm32gg_stb009a - :goals: flash - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you'll see the following message on the corresponding serial port -terminal session: - -.. code-block:: console - - Hello World! efm32gg_sltb009a - -.. _SLTB009A Website: - https://www.silabs.com/development-tools/thunderboard/thunderboard-gg12-kit - -.. _SLTB009A User Guide: - https://www.silabs.com/documents/public/user-guides/ug371-sltb009a-user-guide.pdf - -.. _EFM32GG12 Datasheet: - https://www.silabs.com/documents/public/data-sheets/efm32gg12-datasheet.pdf - -.. _EFM32GG12 Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/efm32gg12-rm.pdf - -.. _J-Link: - https://www.segger.com/jlink-debug-probes.html - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/silabs/efm32gg_sltb009a/efm32gg_sltb009a.dts b/boards/silabs/efm32gg_sltb009a/efm32gg_sltb009a.dts deleted file mode 100644 index eac47f56123..00000000000 --- a/boards/silabs/efm32gg_sltb009a/efm32gg_sltb009a.dts +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright (c) 2023 Antmicro - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include -#include "efm32gg_sltb009a-pinctrl.dtsi" - -/ { - model = "Silicon Labs EFM32GG SLTB009A board"; - compatible = "silabs,efm32gg_sltb009a"; - - chosen { - zephyr,console = &usart0; - zephyr,shell-uart = &usart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0; - led1 = &led1; - sw0 = &button0; - sw1 = &button1; - watchdog0 = &wdog0; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpioe 12 GPIO_ACTIVE_HIGH>; - label = "LED 0"; - }; - led1: led_1 { - gpios = <&gpioa 13 GPIO_ACTIVE_HIGH>; - label = "LED 1"; - }; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - gpios = <&gpiod 5 GPIO_ACTIVE_HIGH>; - label = "User Push Button 0"; - zephyr,code = ; - }; - button1: button_1 { - gpios = <&gpiod 8 GPIO_ACTIVE_HIGH>; - label = "User Push Button 1"; - zephyr,code = ; - }; - }; -}; - -&usart0 { - current-speed = <115200>; - pinctrl-0 = <&usart0_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usart4 { - current-speed = <115200>; - location-rx = ; - location-tx = ; - status = "okay"; -}; - -&leuart0 { - current-speed = <9600>; - location-rx = ; - location-tx = ; - status = "okay"; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&rtcc0 { - prescaler = <1>; - status = "okay"; -}; - -&gpioa { - status = "okay"; - board-controller-enable { - // VCOM Isolation. Set PA15 to HIGH to enable VCOM_{RX,TX}. - gpio-hog; - gpios = <15 GPIO_ACTIVE_HIGH>; - output-high; - }; -}; - -&gpio { - location-swo = <0>; - status = "okay"; -}; - -&gpiob { - status = "okay"; -}; - -&gpioc { - status = "okay"; -}; - -&gpiod { - status = "okay"; -}; - -&gpioe { - status = "okay"; -}; - -&gpiof { - status = "okay"; -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Set 12Kb of storage at the end of the 2048Kb of flash */ - storage_partition: partition@1fd000 { - label = "storage"; - reg = <0x001fd000 0x00003000>; - }; - }; -}; - -&wdog0 { - status = "okay"; -}; - -&trng0 { - status = "okay"; -}; - -&cpu0 { - clock-frequency = <72000000>; -}; diff --git a/boards/silabs/efm32gg_sltb009a/efm32gg_sltb009a.yaml b/boards/silabs/efm32gg_sltb009a/efm32gg_sltb009a.yaml deleted file mode 100644 index ddea24692fa..00000000000 --- a/boards/silabs/efm32gg_sltb009a/efm32gg_sltb009a.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: efm32gg_sltb009a -name: EFM32GG-SLTB009A -type: mcu -arch: arm -ram: 192 -flash: 1024 -toolchain: - - zephyr -supported: - - i2c - - gpio - - nvs -testing: - ignore_tags: - - bluetooth -vendor: silabs diff --git a/boards/silabs/efm32gg_slwstk6121a/Kconfig.defconfig b/boards/silabs/efm32gg_slwstk6121a/Kconfig.defconfig deleted file mode 100644 index 33e5b1192c0..00000000000 --- a/boards/silabs/efm32gg_slwstk6121a/Kconfig.defconfig +++ /dev/null @@ -1,29 +0,0 @@ -# EFM32GG SLWSTK6121A default board configuration -# Copyright (c) 2019 Interay Solutions B.V. -# Copyright (c) 2019 Oane Kingma -# Copyright (c) 2020 Thorvald Natvig -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EFM32GG_SLWSTK6121A - -config CMU_HFXO_FREQ - default 50000000 - -config CMU_HFRCO_FREQ - default 72000000 - -config CMU_LFXO_FREQ - default 32768 - -config LOG_BACKEND_SWO_FREQ_HZ - default 875000 - depends on LOG_BACKEND_SWO - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_EFM32GG_SLWSTK6121A diff --git a/boards/silabs/efm32gg_slwstk6121a/Kconfig.efm32gg_slwstk6121a b/boards/silabs/efm32gg_slwstk6121a/Kconfig.efm32gg_slwstk6121a deleted file mode 100644 index 2e064a306f1..00000000000 --- a/boards/silabs/efm32gg_slwstk6121a/Kconfig.efm32gg_slwstk6121a +++ /dev/null @@ -1,8 +0,0 @@ -# EFM32GG SLWSTK6121A board configuration -# Copyright (c) 2019 Interay Solutions B.V. -# Copyright (c) 2019 Oane Kingma -# Copyright (c) 2020 Thorvald Natvig -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFM32GG_SLWSTK6121A - select SOC_PART_NUMBER_EFM32GG11B820F2048GM64 diff --git a/boards/silabs/efm32gg_slwstk6121a/board.yml b/boards/silabs/efm32gg_slwstk6121a/board.yml deleted file mode 100644 index 7f91de02759..00000000000 --- a/boards/silabs/efm32gg_slwstk6121a/board.yml +++ /dev/null @@ -1,5 +0,0 @@ -board: - name: efm32gg_slwstk6121a - vendor: silabs - socs: - - name: efm32gg11b820f2048gm64 diff --git a/boards/silabs/efm32gg_slwstk6121a/doc/index.rst b/boards/silabs/efm32gg_slwstk6121a/doc/index.rst deleted file mode 100644 index 47d2a5a93a1..00000000000 --- a/boards/silabs/efm32gg_slwstk6121a/doc/index.rst +++ /dev/null @@ -1,186 +0,0 @@ -.. _efm32gg_slwstk6121a: - -WGM160P Starter Kit -################### - -Overview -******** - -The WGM160P Starter Kit SLWSTK6121A comes with the BRD4321A radio board. -This radio boards contains a WGM160P module, which combines the WF200 Wi-Fi -transceiver with an EFM32GG11 microcontroller. - -.. figure:: wgm160p-starter-kit.jpg - :align: center - :alt: SLWSTK6121A - - SLWSTK6121A (image courtesy of Silicon Labs) - -Hardware -******** - -- Advanced Energy Monitoring provides real-time information about the energy - consumption of an application or prototype design. -- Ultra low power 128x128 pixel color Memory-LCD -- 2 user buttons and 2 LEDs -- Si7021 Humidity and Temperature Sensor -- On-board Segger J-Link USB and Ethernet debugger -- 10/100Base-TX ethernet PHY and RJ-45 jack (on included expansion board) -- MicroSD card slot -- USB Micro-AB connector - -For more information about the WGM160P and SLWSTK6121A board: - -- `WGM160P Website`_ -- `WGM160P Datasheet`_ -- `SLWSTK6121A Website`_ -- `SLWSTK6121A User Guide`_ -- `EFM32GG11 Datasheet`_ -- `EFM32GG11 Reference Manual`_ -- `WF200 Datasheet`_ - -Supported Features -================== - -The efm32gg_slwstk6121a board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtcc | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c port-polling | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in -:zephyr_file:`boards/silabs/efm32gg_slwstk6121a/efm32gg_slwstk6121a_defconfig` - -Other hardware features, including the WF200 WiFi transceiver, are -currently not supported by the port. - -Connections and IOs -=================== - -The WGM160P's EFM32GG11 SoC has six GPIO controllers (PORTA to PORTF), all of which are -currently enabled for the SLWSTK6121A board. - -In the following table, the column **Name** contains pin names. For example, PE1 -means pin number 1 on PORTE, as used in the board's datasheets and manuals. - -+-------+-------------+-------------------------------------+ -| Name | Function | Usage | -+=======+=============+=====================================+ -| PA4 | GPIO | LED0 | -+-------+-------------+-------------------------------------+ -| PA5 | GPIO | LED1 | -+-------+-------------+-------------------------------------+ -| PD6 | GPIO | Push Button PB0 | -+-------+-------------+-------------------------------------+ -| PD8 | GPIO | Push Button PB1 | -+-------+-------------+-------------------------------------+ -| PE7 | UART_TX | UART TX Console VCOM_TX US0_TX #1 | -+-------+-------------+-------------------------------------+ -| PE6 | UART_RX | UART RX Console VCOM_RX US0_RX #1 | -+-------+-------------+-------------------------------------+ -| PB11 | I2C_SDA | SENSOR_I2C_SDA I2C1_SDA #1 | -+-------+-------------+-------------------------------------+ -| PB12 | I2C_SCL | SENSOR_I2C_SCL I2C1_SCL #1 | -+-------+-------------+-------------------------------------+ - - -System Clock -============ - -The EFM32GG11 SoC is configured to use the 50 MHz external oscillator on the -board. - -Serial Port -=========== - -The EFM32GG11 SoC has four USARTs, two UARTs and two Low Energy UARTs (LEUART). -USART0 is connected to the board controller and is used for the console. - -Programming and Debugging -************************* - -.. note:: - Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ - -Flashing -======== - -The SLWSTK6121A includes an `J-Link`_ serial and debug adaptor built into the -board. The adaptor provides: - -- A USB connection to the host computer -- A physical UART connection which is relayed over interface USB serial port. - -Flashing an application to SLWSTK6121A --------------------------------------- - -Connect the SLWSTK6121A to your host computer using the USB port. - -Here is an example to build and flash the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efm32gg_slwstk6121a - :goals: flash - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you'll see the following message on the corresponding serial port -terminal session: - -.. code-block:: console - - Hello World! efm32gg_slwstk6121a - -.. _WGM160P Website: - https://www.silabs.com/wireless/wi-fi/wfm160-series-1-modules - -.. _WGM160P Datasheet: - https://www.silabs.com/documents/public/data-sheets/wgm160p-datasheet.pdf - -.. _SLWSTK6121A Website: - https://www.silabs.com/development-tools/wireless/wi-fi/wgm160p-wifi-module-starter-kit - -.. _SLWSTK6121A User Guide: - https://www.silabs.com/documents/public/user-guides/ug351-brd4321a-user-guide.pdf - -.. _EFM32GG11 Datasheet: - https://www.silabs.com/documents/public/data-sheets/efm32gg11-datasheet.pdf - -.. _EFM32GG11 Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/efm32gg11-rm.pdf - -.. _WF200 Datasheet: - https://www.silabs.com/documents/public/data-sheets/wf200-datasheet.pdf - -.. _J-Link: - https://www.segger.com/jlink-debug-probes.html - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/silabs/efm32gg_slwstk6121a/efm32gg_slwstk6121a.dts b/boards/silabs/efm32gg_slwstk6121a/efm32gg_slwstk6121a.dts deleted file mode 100644 index a82fa896722..00000000000 --- a/boards/silabs/efm32gg_slwstk6121a/efm32gg_slwstk6121a.dts +++ /dev/null @@ -1,169 +0,0 @@ -/* - * Copyright (c) 2019 Interay Solutions B.V. - * Copyright (c) 2019 Oane Kingma - * Copyright (c) 2020 Thorvald Natvig - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include -#include "efm32gg_slwstk6121a-pinctrl.dtsi" - -/ { - model = "Silicon Labs EFM32GG SLWSTK6121A board"; - compatible = "silabs,efm32gg_slwstk6121a", "silabs,efm32gg11b"; - - chosen { - zephyr,console = &usart0; - zephyr,shell-uart = &usart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0; - led1 = &led1; - sw0 = &button0; - sw1 = &button1; - watchdog0 = &wdog0; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpioa 4 0>; - label = "LED 0"; - }; - led1: led_1 { - gpios = <&gpioa 5 0>; - label = "LED 1"; - }; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - /* gpio flags need validation */ - gpios = <&gpiod 6 GPIO_ACTIVE_LOW>; - label = "User Push Button 0"; - zephyr,code = ; - }; - button1: button_1 { - /* gpio flags need validation */ - gpios = <&gpiod 8 GPIO_ACTIVE_LOW>; - label = "User Push Button 1"; - zephyr,code = ; - }; - }; -}; - -/* Connected to the WSTK VCOM */ -&usart0 { - current-speed = <115200>; - pinctrl-0 = <&usart0_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -/* i2c unit 0 is not used on the board, but must be defined for i2c unit 1 - * to work properly. - */ -&i2c0 { - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -/* Connected to Si7021 sensor on WSTK */ -&i2c1 { - pinctrl-0 = <&i2c1_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&rtcc0 { - prescaler = <1>; - status = "okay"; -}; - -&gpio { - location-swo = <0>; - status = "okay"; -}; - -&gpioa { - status = "okay"; -}; - -&gpiob { - status = "okay"; -}; - -&gpioc { - status = "okay"; -}; - -&gpiod { - status = "okay"; -}; - -&gpioe { - status = "okay"; -}; - -&gpiof { - status = "okay"; -}; - -ð0 { - /* PHY address = 0 */ - phy-address = <0>; - - /* PHY management pins */ - location-mdio = ; - location-phy_mdc = ; - location-phy_mdio = ; - - /* RMII interface pins */ - location-rmii = ; - location-rmii_refclk = ; - location-rmii_crs_dv = ; - location-rmii_txd0 = ; - location-rmii_txd1 = ; - location-rmii_tx_en = ; - location-rmii_rxd0 = ; - location-rmii_rxd1 = ; - location-rmii_rx_er = ; - - status = "okay"; -}; - -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Set 12Kb of storage at the end of the 2048Kb of flash */ - storage_partition: partition@1fd000 { - label = "storage"; - reg = <0x001fd000 0x00003000>; - }; - }; -}; - -&wdog0 { - status = "okay"; -}; - -&trng0 { - status = "okay"; -}; - -&cpu0 { - clock-frequency = <72000000>; -}; diff --git a/boards/silabs/efm32gg_slwstk6121a/efm32gg_slwstk6121a.yaml b/boards/silabs/efm32gg_slwstk6121a/efm32gg_slwstk6121a.yaml deleted file mode 100644 index 9e976e5ccaa..00000000000 --- a/boards/silabs/efm32gg_slwstk6121a/efm32gg_slwstk6121a.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: efm32gg_slwstk6121a -name: EFM32GG-SLWSTK6121A -type: mcu -arch: arm -ram: 512 -flash: 2048 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - counter - - i2c - - gpio - - netif:eth - - nvs - - uart -testing: - ignore_tags: - - bluetooth -vendor: silabs diff --git a/boards/silabs/efm32gg_stk3701a/Kconfig.defconfig b/boards/silabs/efm32gg_stk3701a/Kconfig.defconfig deleted file mode 100644 index c56b944202f..00000000000 --- a/boards/silabs/efm32gg_stk3701a/Kconfig.defconfig +++ /dev/null @@ -1,28 +0,0 @@ -# EFM32GG STK3701A default board configuration -# Copyright (c) 2019 Interay Solutions B.V. -# Copyright (c) 2019 Oane Kingma -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EFM32GG_STK3701A - -config CMU_HFXO_FREQ - default 50000000 - -config CMU_HFRCO_FREQ - default 72000000 - -config CMU_LFXO_FREQ - default 32768 - -config LOG_BACKEND_SWO_FREQ_HZ - default 875000 - depends on LOG_BACKEND_SWO - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_EFM32GG_STK3701A diff --git a/boards/silabs/efm32gg_stk3701a/Kconfig.efm32gg_stk3701a b/boards/silabs/efm32gg_stk3701a/Kconfig.efm32gg_stk3701a deleted file mode 100644 index 058ea533a21..00000000000 --- a/boards/silabs/efm32gg_stk3701a/Kconfig.efm32gg_stk3701a +++ /dev/null @@ -1,7 +0,0 @@ -# EFM32GG STK3701A board configuration -# Copyright (c) 2019 Interay Solutions B.V. -# Copyright (c) 2019 Oane Kingma -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFM32GG_STK3701A - select SOC_PART_NUMBER_EFM32GG11B820F2048GL192 diff --git a/boards/silabs/efm32gg_stk3701a/board.yml b/boards/silabs/efm32gg_stk3701a/board.yml deleted file mode 100644 index d69afebb60b..00000000000 --- a/boards/silabs/efm32gg_stk3701a/board.yml +++ /dev/null @@ -1,5 +0,0 @@ -board: - name: efm32gg_stk3701a - vendor: silabs - socs: - - name: efm32gg11b820f2048gl192 diff --git a/boards/silabs/efm32gg_stk3701a/doc/index.rst b/boards/silabs/efm32gg_stk3701a/doc/index.rst deleted file mode 100644 index ddb5a1f38d7..00000000000 --- a/boards/silabs/efm32gg_stk3701a/doc/index.rst +++ /dev/null @@ -1,200 +0,0 @@ -.. _efm32gg_stk3701a: - -EFM32 Giant Gecko GG11 Starter Kit -################################## - -Overview -******** - -The EFM32 Giant Gecko Starter Kit EFM32GG-STK3701A contains an MCU from the -EFM32GG Series 1 family built on an ARM® Cortex®-M4F processor with excellent -low power capabilities. - -.. figure:: efm32gg_stk3701a.jpg - :align: center - :alt: EFM32GG-SLSTK3701A - - EFM32GG-SLSTK3701A (image courtesy of Silicon Labs) - -Hardware -******** - -- Advanced Energy Monitoring provides real-time information about the energy - consumption of an application or prototype design. -- Ultra low power 128x128 pixel color Memory-LCD -- 2 user buttons, 2 LEDs and a touch slider -- Relative humidity, magnetic Hall Effect and inductive-capacitive metal sensor -- USB interface for Host/Device/OTG -- 32 Mb Quad-SPI Flash memory -- SD card slot -- RJ-45 Ethernet jack -- 2 digital microphones -- On-board Segger J-Link USB debugger - -For more information about the EFM32GG11 SoC and EFM32GG-STK3701A board: - -- `EFM32GG Series 1 Website`_ -- `EFM32GG11 Datasheet`_ -- `EFM32GG11 Reference Manual`_ -- `EFM32GG-STK3701A Website`_ -- `EFM32GG-STK3701A User Guide`_ -- `EFM32GG-STK3701A Schematics`_ - -Supported Features -================== - -The efm32gg_stk3701a board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtcc | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c port-polling | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in -:zephyr_file:`boards/silabs/efm32gg_stk3701a/efm32gg_stk3701a_defconfig` - -Other hardware features are currently not supported by the port. - -Connections and IOs -=================== - -The EFM32GG11 SoC has nine GPIO controllers (PORTA to PORTI), all of which are -currently enabled for the EFM32GG-STK3701A board. - -In the following table, the column **Name** contains pin names. For example, PE1 -means pin number 1 on PORTE, as used in the board's datasheets and manuals. - -+-------+-------------+-------------------------------------+ -| Name | Function | Usage | -+=======+=============+=====================================+ -| PH10 | GPIO | LED0 red | -+-------+-------------+-------------------------------------+ -| PH11 | GPIO | LED0 green | -+-------+-------------+-------------------------------------+ -| PH12 | GPIO | LED0 blue | -+-------+-------------+-------------------------------------+ -| PH13 | GPIO | LED1 red | -+-------+-------------+-------------------------------------+ -| PH14 | GPIO | LED1 green | -+-------+-------------+-------------------------------------+ -| PH15 | GPIO | LED1 blue | -+-------+-------------+-------------------------------------+ -| PC8 | GPIO | Push Button PB0 | -+-------+-------------+-------------------------------------+ -| PC9 | GPIO | Push Button PB1 | -+-------+-------------+-------------------------------------+ -| PE1 | GPIO | Board Controller Enable | -| | | EFM_BC_EN | -+-------+-------------+-------------------------------------+ -| PH4 | UART_TX | UART TX Console VCOM_TX US0_TX #4 | -+-------+-------------+-------------------------------------+ -| PH5 | UART_RX | UART RX Console VCOM_RX US0_RX #4 | -+-------+-------------+-------------------------------------+ -| PI4 | I2C_SDA | SENSOR_I2C_SDA I2C2_SDA #7 | -+-------+-------------+-------------------------------------+ -| PI5 | I2C_SCL | SENSOR_I2C_SCL I2C2_SCL #7 | -+-------+-------------+-------------------------------------+ - - -System Clock -============ - -The EFM32GG11 SoC is configured to use the 50 MHz external oscillator on the -board. - -Serial Port -=========== - -The EFM32GG11 SoC has six USARTs, two UARTs and two Low Energy UARTs (LEUART). -USART4 is connected to the board controller and is used for the console. - -Programming and Debugging -************************* - -.. note:: - Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ - -Flashing -======== - -The EFM32GG-STK3701A includes an `J-Link`_ serial and debug adaptor built into the -board. The adaptor provides: - -- A USB connection to the host computer, which exposes a mass storage device and a - USB serial port. -- A serial flash device, which implements the USB flash disk file storage. -- A physical UART connection which is relayed over interface USB serial port. - -Flashing an application to EFM32GG-STK3701A -------------------------------------------- - -The sample application :ref:`hello_world` is used for this example. -Build the Zephyr kernel and application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efm32gg_stk3701a - :goals: build - -Connect the EFM32GG-STK3701A to your host computer using the USB port and you -should see a USB connection which exposes a mass storage device(STK3701A) and -a USB Serial Port. Copy the generated zephyr.bin to the STK3701A drive. - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you'll see the following message on the corresponding serial port -terminal session: - -.. code-block:: console - - Hello World! efm32gg_stk3701a - - -.. _EFM32GG-STK3701A Website: - https://www.silabs.com/products/development-tools/mcu/32-bit/efm32-giant-gecko-gg11-starter-kit - -.. _EFM32GG-STK3701A User Guide: - https://www.silabs.com/documents/public/user-guides/ug287-stk3701.pdf - -.. _EFM32GG-STK3701A Schematics: - https://www.silabs.com/documents/public/schematic-files/BRD2204A-B00-schematic.pdf - -.. _EFM32GG Series 1 Website: - https://www.silabs.com/products/mcu/32-bit/efm32-giant-gecko-s1 - -.. _EFM32GG11 Datasheet: - https://www.silabs.com/documents/public/data-sheets/efm32gg11-datasheet.pdf - -.. _EFM32GG11 Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/efm32gg11-rm.pdf - -.. _J-Link: - https://www.segger.com/jlink-debug-probes.html - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/silabs/efm32gg_stk3701a/efm32gg_stk3701a.dts b/boards/silabs/efm32gg_stk3701a/efm32gg_stk3701a.dts deleted file mode 100644 index 39589b61855..00000000000 --- a/boards/silabs/efm32gg_stk3701a/efm32gg_stk3701a.dts +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright (c) 2019 Interay Solutions B.V. - * Copyright (c) 2019 Oane Kingma - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include -#include "efm32gg_stk3701a-pinctrl.dtsi" - -/ { - model = "Silicon Labs EFM32GG STK3701A board"; - compatible = "silabs,efm32gg_stk3701a", "silabs,efm32gg11b"; - - chosen { - zephyr,console = &usart4; - zephyr,shell-uart = &usart4; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0; - led1 = &led1; - sw0 = &button0; - sw1 = &button1; - watchdog0 = &wdog0; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpioh 10 0>; - label = "LED 0"; - }; - led1: led_1 { - gpios = <&gpioh 13 0>; - label = "LED 1"; - }; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - /* gpio flags need validation */ - gpios = <&gpioc 8 GPIO_ACTIVE_LOW>; - label = "User Push Button 0"; - zephyr,code = ; - }; - button1: button_1 { - /* gpio flags need validation */ - gpios = <&gpioc 9 GPIO_ACTIVE_LOW>; - label = "User Push Button 1"; - zephyr,code = ; - }; - }; -}; - -&usart0 { - current-speed = <115200>; - pinctrl-0 = <&usart0_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usart4 { - current-speed = <115200>; - pinctrl-0 = <&usart4_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&leuart0 { - current-speed = <9600>; - location-rx = ; - location-tx = ; - status = "okay"; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&rtcc0 { - prescaler = <1>; - status = "okay"; -}; - -&gpio { - location-swo = <0>; - status = "okay"; -}; - -&gpioa { - status = "okay"; -}; - -&gpiob { - status = "okay"; -}; - -&gpioc { - status = "okay"; -}; - -&gpiod { - status = "okay"; -}; - -&gpioe { - status = "okay"; - - board-controller-enable { - gpio-hog; - gpios = <1 GPIO_ACTIVE_HIGH>; - output-high; - }; -}; - -&gpiof { - status = "okay"; -}; - -&gpiog { - status = "okay"; -}; - -&gpioh { - status = "okay"; -}; - -&gpioi { - status = "okay"; -}; - -ð0 { - /* PHY address = 0 */ - phy-address = <0>; - - /* PHY management pins */ - location-mdio = ; - location-phy_mdc = ; - location-phy_mdio = ; - - /* RMII interface pins */ - location-rmii = ; - location-rmii_refclk = ; - location-rmii_crs_dv = ; - location-rmii_txd0 = ; - location-rmii_txd1 = ; - location-rmii_tx_en = ; - location-rmii_rxd0 = ; - location-rmii_rxd1 = ; - location-rmii_rx_er = ; - - status = "okay"; -}; - -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Set 12Kb of storage at the end of the 2048Kb of flash */ - storage_partition: partition@1fd000 { - label = "storage"; - reg = <0x001fd000 0x00003000>; - }; - }; -}; - -&wdog0 { - status = "okay"; -}; - -&trng0 { - status = "okay"; -}; - -&cpu0 { - clock-frequency = <72000000>; -}; diff --git a/boards/silabs/efm32gg_stk3701a/efm32gg_stk3701a.yaml b/boards/silabs/efm32gg_stk3701a/efm32gg_stk3701a.yaml deleted file mode 100644 index 426328eae97..00000000000 --- a/boards/silabs/efm32gg_stk3701a/efm32gg_stk3701a.yaml +++ /dev/null @@ -1,19 +0,0 @@ -identifier: efm32gg_stk3701a -name: EFM32GG-STK3701A -type: mcu -arch: arm -ram: 512 -flash: 2048 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - i2c - - gpio - - netif:eth - - nvs -testing: - ignore_tags: - - bluetooth -vendor: silabs diff --git a/boards/silabs/efm32hg_slstk3400a/Kconfig.defconfig b/boards/silabs/efm32hg_slstk3400a/Kconfig.defconfig deleted file mode 100644 index c15834e7229..00000000000 --- a/boards/silabs/efm32hg_slstk3400a/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# EFM32HG SLSTK3400A board - -# Copyright (c) 2018, Marcio Montenegro -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EFM32HG_SLSTK3400A - -config CMU_HFXO_FREQ - default 24000000 - -config CMU_LFXO_FREQ - default 32768 - -endif # BOARD_EFM32HG_SLSTK3400A diff --git a/boards/silabs/efm32hg_slstk3400a/Kconfig.efm32hg_slstk3400a b/boards/silabs/efm32hg_slstk3400a/Kconfig.efm32hg_slstk3400a deleted file mode 100644 index 3ab1289920f..00000000000 --- a/boards/silabs/efm32hg_slstk3400a/Kconfig.efm32hg_slstk3400a +++ /dev/null @@ -1,7 +0,0 @@ -# EFM32HG SLSTK3400A board - -# Copyright (c) 2018, Marcio Montenegro -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFM32HG_SLSTK3400A - select SOC_PART_NUMBER_EFM32HG322F64 diff --git a/boards/silabs/efm32hg_slstk3400a/board.yml b/boards/silabs/efm32hg_slstk3400a/board.yml deleted file mode 100644 index 8aae393fcae..00000000000 --- a/boards/silabs/efm32hg_slstk3400a/board.yml +++ /dev/null @@ -1,5 +0,0 @@ -board: - name: efm32hg_slstk3400a - vendor: silabs - socs: - - name: efm32hg322f64 diff --git a/boards/silabs/efm32hg_slstk3400a/doc/index.rst b/boards/silabs/efm32hg_slstk3400a/doc/index.rst deleted file mode 100644 index a1e0b84f16d..00000000000 --- a/boards/silabs/efm32hg_slstk3400a/doc/index.rst +++ /dev/null @@ -1,176 +0,0 @@ -.. _efm32hg_slstk3400a: - -EFM32HG-SLSTK3400A -################## - -Overview -******** - -The EFM32 Happy Gecko Starter Kit EFM32HG-SLSTK3400A contains a MCU from the -EFM32HG family built on ARM® Cortex®-M0+ processor with excellent low -power capabilities. - -.. figure:: efm32hg_slstk3400a.jpg - :align: center - :alt: EFM32HG-SLSTK3400A - - EFM32HG-SLSTK3400A (image courtesy of Silicon Labs) - -Hardware -******** - -- Advanced Energy Monitoring system for precise current tracking -- Real-time energy and power profiling -- ARM Cortex M0+ with 64 kB Flash and 8 kB RAM -- 128 X 128 pixel Memory LCD -- 2 user buttons, 2 user LEDs and 2 touch buttons -- 20 pin expansion header -- Silicon Labs Si7021 Relative Humidity/Temperature sensor -- USB device interface -- Integrated SEGGER J-Link USB debugger/emulator with debug out functionality - - -See these documents for more information - -- `EFM32HG Website`_ -- `EFM32HG Datasheet`_ -- `EFM32HG Reference Manual`_ -- `EFM32HG-SLSTK3400A Website`_ -- `EFM32HG-SLSTK3400A User Guide`_ -- `EFM32HG-SLSTK3400A Schematics`_ - -Supported Features -================== - -The efm32hg_slstk3400 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| USART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in -:zephyr_file:`boards/silabs/efm32hg_slstk3400a/efm32hg_slstk3400a_defconfig` - -Other hardware features are currently not supported by the port. - -Connections and IOs -=================== - -The EFM32HG SoC has six GPIO controllers (PORTA to PORTF), but only three are -currently enabled (PORTB, PORTE and PORTF) for the EFM32HG-SLSTK3400A board. - -In the following table, the column Name contains Pin names. For example, PF4 -means Pin number 4 on PORTF, as used in the board's datasheets and manuals. - -+-------+-------------+-------------------------------------+ -| Name | Function | Usage | -+=======+=============+=====================================+ -| PF4 | GPIO | LED0 | -+-------+-------------+-------------------------------------+ -| PF5 | GPIO | LED1 | -+-------+-------------+-------------------------------------+ -| PC9 | GPIO | Push Button PB0 | -+-------+-------------+-------------------------------------+ -| PC10 | GPIO | Push Button PB1 | -+-------+-------------+-------------------------------------+ -| PF7 | GPIO | Board Controller Enable | -| | | EFM_BC_EN | -+-------+-------------+-------------------------------------+ -| PF2 | USART0_TX | USART Console EFM_BC_TX U0_TX #4 | -+-------+-------------+-------------------------------------+ -| PA9 | USART0_RX | USART Console EFM_BC_RX U0_RX #4 | -+-------+-------------+-------------------------------------+ - -System Clock -============ - -The EFM32HG SoC is configured to use the 24 MHz external oscillator on the -board. - -Serial Port -=========== - -The EFM32HG SoC has two USARTs, two UARTs and two Low Energy UARTs (LEUART). -USART1 is connected to the board controller and is used for the console. - -Programming and Debugging -************************* - -.. note:: - Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ - -Flashing -======== - -The EFM32HG-SLSTK3400 includes an `J-Link`_ serial and debug adaptor built into the -board. The adaptor provides: - -- A USB connection to the host computer, which exposes a Mass Storage and a - USB Serial Port. -- A Serial Flash device, which implements the USB flash disk file storage. -- A physical UART connection which is relayed over interface USB Serial port. - -Flashing an application to EFM32-SLSTK3400A -------------------------------------------- - -The sample application :ref:`hello_world` is used for this example. -Build the Zephyr kernel and application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efm32hg_slstk3400a - :goals: build - -Connect the EFM32HG-SLSTK3400A to your host computer using the USB port and -you should see a USB connection that exposes a mass storage device (STK3400) -and a USB Serial Port. Copy the generated ``zephyr.bin`` in the STK3400 drive. - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you will see this message written to the serial port: - -.. code-block:: console - - Hello World! arm - - -.. _EFM32HG-SLSTK3400A Website: - https://www.silabs.com/products/development-tools/mcu/32-bit/efm32-happy-gecko-starter-kit - -.. _EFM32HG-SLSTK3400A User Guide: - https://www.silabs.com/documents/public/user-guides/ug255-stk3400-user-guide.pdf - -.. _EFM32HG-SLSTK3400A Schematics: - https://www.silabs.com/documents/public/schematic-files/BRD2012A-B01-schematic.pdf - -.. _EFM32HG Website: - https://www.silabs.com/products/mcu/32-bit/efm32-happy-gecko - -.. _EFM32HG Datasheet: - https://www.silabs.com/documents/public/data-sheets/EFM32HG322.pdf - -.. _EFM32HG Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/EFM32HG-RM.pdf - -.. _J-Link: - https://www.segger.com/jlink-debug-probes.html - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/silabs/efm32hg_slstk3400a/efm32hg_slstk3400a.dts b/boards/silabs/efm32hg_slstk3400a/efm32hg_slstk3400a.dts deleted file mode 100644 index 01c1f4d7766..00000000000 --- a/boards/silabs/efm32hg_slstk3400a/efm32hg_slstk3400a.dts +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Copyright (c) 2017 Christian Taedcke - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include - -/ { - model = "Silicon Labs EFM32HG SLSTK3400A board"; - compatible = "silabs,efm32hg_slstk3400a", "silabs,efm32hg"; - - chosen { - zephyr,console = &usart1; - zephyr,shell-uart = &usart1; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0; - led1 = &led1; - sw0 = &button0; - sw1 = &button1; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpiof 4 0>; - label = "LED 0"; - }; - led1: led_1 { - gpios = <&gpiof 5 0>; - label = "LED 1"; - }; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - /* gpio flags need validation */ - gpios = <&gpioc 9 GPIO_ACTIVE_LOW>; - label = "User Push Button 0"; - zephyr,code = ; - }; - button1: button_1 { - /* gpio flags need validation */ - gpios = <&gpioc 10 GPIO_ACTIVE_LOW>; - label = "User Push Button 1"; - zephyr,code = ; - }; - }; - -}; - -&cpu0 { - clock-frequency = <24000000>; -}; - -&gpioa { - status = "okay"; - - board-controller-enable { - gpio-hog; - gpios = <9 GPIO_ACTIVE_HIGH>; - output-high; - }; -}; - -&gpioc { - status = "okay"; -}; - -&gpiof { - status = "okay"; -}; - -&usart1 { - current-speed = <115200>; - location-rx = ; - location-tx = ; - status = "okay"; -}; - -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Set 4Kb of storage at the end of the 64Kb of flash */ - storage_partition: partition@f000 { - label = "storage"; - reg = <0x0000f000 0x00001000>; - }; - - }; -}; diff --git a/boards/silabs/efm32hg_slstk3400a/efm32hg_slstk3400a.yaml b/boards/silabs/efm32hg_slstk3400a/efm32hg_slstk3400a.yaml deleted file mode 100644 index d14ffbbd10a..00000000000 --- a/boards/silabs/efm32hg_slstk3400a/efm32hg_slstk3400a.yaml +++ /dev/null @@ -1,18 +0,0 @@ -identifier: efm32hg_slstk3400a -name: EFM32HG-SLSTK3400A -type: mcu -arch: arm -ram: 8 -flash: 64 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - gpio - - nvs -testing: - ignore_tags: - - net - - bluetooth -vendor: silabs diff --git a/boards/silabs/efm32pg_stk3401a/Kconfig.defconfig b/boards/silabs/efm32pg_stk3401a/Kconfig.defconfig deleted file mode 100644 index 9853bf434cc..00000000000 --- a/boards/silabs/efm32pg_stk3401a/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# EFM32PG STK3401A board - -# Copyright (c) 2020, Rafael Dias Menezes -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EFM32PG_STK3401A - -config CMU_HFXO_FREQ - default 40000000 - -config CMU_LFXO_FREQ - default 32768 - -endif # BOARD_EFM32PG_STK3401A diff --git a/boards/silabs/efm32pg_stk3401a/Kconfig.efm32pg_stk3401a b/boards/silabs/efm32pg_stk3401a/Kconfig.efm32pg_stk3401a deleted file mode 100644 index 42de02a430a..00000000000 --- a/boards/silabs/efm32pg_stk3401a/Kconfig.efm32pg_stk3401a +++ /dev/null @@ -1,7 +0,0 @@ -# EFM32PG STK3401A board - -# Copyright (c) 2020, Rafael Dias Menezes -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFM32PG_STK3401A - select SOC_PART_NUMBER_EFM32PG1B200F256GM48 diff --git a/boards/silabs/efm32pg_stk3401a/board.yml b/boards/silabs/efm32pg_stk3401a/board.yml deleted file mode 100644 index 636c7e8c562..00000000000 --- a/boards/silabs/efm32pg_stk3401a/board.yml +++ /dev/null @@ -1,5 +0,0 @@ -board: - name: efm32pg_stk3401a - vendor: silabs - socs: - - name: efm32pg1b200f256gm48 diff --git a/boards/silabs/efm32pg_stk3401a/doc/index.rst b/boards/silabs/efm32pg_stk3401a/doc/index.rst deleted file mode 100644 index a38930275a2..00000000000 --- a/boards/silabs/efm32pg_stk3401a/doc/index.rst +++ /dev/null @@ -1,188 +0,0 @@ -.. _efm32pg_stk3401a: - -EFM32 Pearl Gecko Starter Kit -############################# - -Overview -******** - -The EFM32 Pearl Gecko Starter Kit EFM32PG-STK3401A contains an MCU from the -EFM32PG family built on an ARM® Cortex®-M4F processor with excellent low -power capabilities. - -.. figure:: efm32pg_stk3401a.jpg - :align: center - :alt: EFM32PG-SLSTK3401A - - EFM32PG-SLSTK3401A (image courtesy of Silicon Labs) - -Hardware -******** - -- Advanced Energy Monitoring provides real-time information about the energy - consumption of an application or prototype design. -- Ultra low power 128x128 pixel Memory-LCD -- 2 user buttons, 2 LEDs and 2 capacitive buttons -- Humidity and temperature sensor -- On-board Segger J-Link USB debugger - -For more information about the EFM32PG SoC and EFM32PG-STK3401A board: - -- `EFM32PG Website`_ -- `EFM32PG1 Datasheet`_ -- `EFM32PG1 Reference Manual`_ -- `EFM32PG-STK3401A Website`_ -- `EFM32PG-STK3401A User Guide`_ - -Supported Features -================== - -The efm32pg_stk3401a board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtcc | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c port-polling | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in -:zephyr_file:`boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a_defconfig` - -Other hardware features are currently not supported by the port. - -Connections and IOs -=================== - -The EFM32PG1 SoC has five GPIO controllers (PORTA to PORTD and PORTF) and -all are enabled for the EFM32PG-STK3401A board. - -In the following table, the column **Name** contains pin names. For example, PF4 -means pin number 4 on PORTF, as used in the board's datasheets and manuals. - -+-------+-------------+-------------------------------------+ -| Name | Function | Usage | -+=======+=============+=====================================+ -| PF4 | GPIO | LED0 | -+-------+-------------+-------------------------------------+ -| PF5 | GPIO | LED1 | -+-------+-------------+-------------------------------------+ -| PF6 | GPIO | Push Button PB0 | -+-------+-------------+-------------------------------------+ -| PF7 | GPIO | Push Button PB1 | -+-------+-------------+-------------------------------------+ -| PA5 | GPIO | Board Controller Enable | -| | | EFM_BC_EN | -+-------+-------------+-------------------------------------+ -| PA0 | UART_TX | UART TX Console VCOM_TX US0_TX #0 | -+-------+-------------+-------------------------------------+ -| PA1 | UART_RX | UART RX Console VCOM_RX US0_RX #0 | -+-------+-------------+-------------------------------------+ -| PD10 | UART_TX | EXP12_UART_TX LEU0_TX #18 | -+-------+-------------+-------------------------------------+ -| PD11 | UART_RX | EXP14_UART_RX LEU0_RX #18 | -+-------+-------------+-------------------------------------+ -| PC10 | I2C_SDA | ENV_I2C_SDA I2C0_SDA #15 | -+-------+-------------+-------------------------------------+ -| PC11 | I2C_SCL | ENV_I2C_SCL I2C0_SCL #15 | -+-------+-------------+-------------------------------------+ - - -System Clock -============ - -The EFM32PG SoC is configured to use the 40 MHz external oscillator on the -board. - -Serial Port -=========== - -The EFM32PG SoC has two USARTs and one Low Energy UART (LEUART). - -Programming and Debugging -************************* - -.. note:: - Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ - -Flashing -======== - -The EFM32PG-STK3401A includes an `J-Link`_ serial and debug adaptor built into the -board. The adaptor provides: - -- A USB connection to the host computer, which exposes a mass storage device and a - USB serial port. -- A serial flash device, which implements the USB flash disk file storage. -- A physical UART connection which is relayed over interface USB serial port. - -Flashing an application to EFM32PG-STK3401A -------------------------------------------- - -The sample application :ref:`hello_world` is used for this example. -Build the Zephyr kernel and application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efm32pg_stk3401a - :goals: build - -Connect the EFM32PG-STK3401A to your host computer using the USB port and you -should see a USB connection which exposes a mass storage device(STK3401A). -Copy the generated zephyr.bin to the STK3401A drive. - -Use a USB-to-UART converter such as an FT232/CP2102 to connect to the UART on the -expansion header. - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you'll see the following message on the corresponding serial port -terminal session: - -.. code-block:: console - - Hello World! arm - - -.. _EFM32PG-STK3401A Website: - https://www.silabs.com/development-tools/mcu/32-bit/efm32pg1-starter-kit - -.. _EFM32PG-STK3401A User Guide: - https://www.silabs.com/documents/public/user-guides/ug154-stk3401-user-guide.pdf - -.. _EFM32PG Website: - https://www.silabs.com/products/mcu/32-bit/efm32-pearl-gecko - -.. _EFM32PG1 Datasheet: - https://www.silabs.com/documents/public/data-sheets/efm32pg1-datasheet.pdf - -.. _EFM32PG1 Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/efm32pg1-rm.pdf - -.. _J-Link: - https://www.segger.com/jlink-debug-probes.html - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a.dts b/boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a.dts deleted file mode 100644 index 1a7f9eddec4..00000000000 --- a/boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a.dts +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (c) 2020 Rafael Dias Menezes - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "efm32pg_stk3401a_common.dtsi" - -/ { - model = "Silicon Labs EFM32PG STK3401A board"; - compatible = "silabs,efm32pg_stk3401a", "silabs,efm32pg1b"; -}; diff --git a/boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a.yaml b/boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a.yaml deleted file mode 100644 index ee707a08caa..00000000000 --- a/boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a.yaml +++ /dev/null @@ -1,20 +0,0 @@ -identifier: efm32pg_stk3401a -name: EFM32PG-STK3401A -type: mcu -arch: arm -ram: 32 -flash: 256 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - i2c - - gpio - - nvs - - watchdog -testing: - ignore_tags: - - net - - bluetooth -vendor: silabs diff --git a/boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a_common.dtsi b/boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a_common.dtsi deleted file mode 100644 index 97427b85817..00000000000 --- a/boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a_common.dtsi +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Copyright (c) 2020 Rafael Dias Menezes - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include "efm32pg_stk3401a-pinctrl.dtsi" - -/ { - model = "Silicon Labs EFM32PG STK3401A board"; - - chosen { - zephyr,console = &usart0; - zephyr,shell-uart = &usart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0; - led1 = &led1; - sw0 = &button0; - sw1 = &button1; - watchdog0 = &wdog0; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpiof 4 0>; - label = "LED 0"; - }; - led1: led_1 { - gpios = <&gpiof 5 0>; - label = "LED 1"; - }; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - /* gpio flags need validation */ - gpios = <&gpiof 6 GPIO_ACTIVE_LOW>; - label = "User Push Button 0"; - zephyr,code = ; - }; - button1: button_1 { - /* gpio flags need validation */ - gpios = <&gpiof 7 GPIO_ACTIVE_LOW>; - label = "User Push Button 1"; - zephyr,code = ; - }; - }; -}; - -&cpu0 { - clock-frequency = <40000000>; -}; - -&usart0 { - current-speed = <115200>; - pinctrl-0 = <&usart0_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&leuart0 { - current-speed = <9600>; - location-rx = ; - location-tx = ; - status = "okay"; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&rtcc0 { - prescaler = <1>; - status = "okay"; -}; - -&gpio { - location-swo = <0>; - status = "okay"; -}; - -&gpioa { - status = "okay"; - - board-controller-enable { - gpio-hog; - gpios = <5 GPIO_ACTIVE_HIGH>; - output-high; - }; -}; - -&gpiob { - status = "okay"; -}; - -&gpioc { - status = "okay"; -}; - -&gpiod { - status = "okay"; -}; - -&gpiof { - status = "okay"; -}; - -&wdog0 { - status = "okay"; -}; - -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Set 6Kb of storage at the end of the 256Kb of flash */ - storage_partition: partition@fe800 { - label = "storage"; - reg = <0x0003e800 0x00001800>; - }; - - }; -}; diff --git a/boards/silabs/efm32pg_stk3402a/Kconfig.defconfig b/boards/silabs/efm32pg_stk3402a/Kconfig.defconfig deleted file mode 100644 index 3d9a498ecd5..00000000000 --- a/boards/silabs/efm32pg_stk3402a/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# EFM32PG STK3402A board - -# Copyright (c) 2018, Christian Taedcke -# Copyright (c) 2019 Lemonbeat GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EFM32PG_STK3402A - -config CMU_HFXO_FREQ - default 40000000 - -config CMU_LFXO_FREQ - default 32768 - -endif # BOARD_EFM32PG_STK3402A diff --git a/boards/silabs/efm32pg_stk3402a/Kconfig.efm32pg_stk3402a b/boards/silabs/efm32pg_stk3402a/Kconfig.efm32pg_stk3402a deleted file mode 100644 index 7f4bea41475..00000000000 --- a/boards/silabs/efm32pg_stk3402a/Kconfig.efm32pg_stk3402a +++ /dev/null @@ -1,9 +0,0 @@ -# EFM32PG STK3402A board - -# Copyright (c) 2018, Christian Taedcke -# Copyright (c) 2019 Lemonbeat GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFM32PG_STK3402A - select SOC_PART_NUMBER_EFM32PG12B500F1024GL125 if BOARD_EFM32PG_STK3402A_EFM32PG12B500F1024GL125 - select SOC_PART_NUMBER_EFM32JG12B500F1024GL125 if BOARD_EFM32PG_STK3402A_EFM32JG12B500F1024GL125 diff --git a/boards/silabs/efm32pg_stk3402a/board.yml b/boards/silabs/efm32pg_stk3402a/board.yml deleted file mode 100644 index 068aa663798..00000000000 --- a/boards/silabs/efm32pg_stk3402a/board.yml +++ /dev/null @@ -1,6 +0,0 @@ -board: - name: efm32pg_stk3402a - vendor: silabs - socs: - - name: efm32pg12b500f1024gl125 - - name: efm32jg12b500f1024gl125 diff --git a/boards/silabs/efm32pg_stk3402a/doc/index.rst b/boards/silabs/efm32pg_stk3402a/doc/index.rst deleted file mode 100644 index 8014f310b0c..00000000000 --- a/boards/silabs/efm32pg_stk3402a/doc/index.rst +++ /dev/null @@ -1,212 +0,0 @@ -.. _efm32pg_stk3402a: - -EFM32 Pearl Gecko Starter Kit -############################# - -Overview -******** - -The EFM32 Pearl Gecko Starter Kit EFM32PG-STK3402A contains an MCU from the -EFM32PG family built on an ARM® Cortex®-M4F processor with excellent low -power capabilities. - -.. figure:: efm32pg_stk3402a.jpg - :align: center - :alt: EFM32PG-SLSTK3402A - - EFM32PG-SLSTK3402A (image courtesy of Silicon Labs) - -Hardware -******** - -- Advanced Energy Monitoring provides real-time information about the energy - consumption of an application or prototype design. -- Ultra low power 128x128 pixel Memory-LCD -- 2 user buttons, 2 LEDs and a touch slider -- Humidity, temperature, and inductive-capacitive metal sensor -- On-board Segger J-Link USB debugger - -For more information about the EFM32PG SoC and EFM32PG-STK3402A board: - -- `EFM32PG Website`_ -- `EFM32PG12 Datasheet`_ -- `EFM32PG12 Reference Manual`_ -- `EFM32PG-STK3402A Website`_ -- `EFM32PG-STK3402A User Guide`_ -- `EFM32PG-STK3402A Schematics`_ - -Supported Features -================== - -The efm32pg_stk3402a board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtcc | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c port-polling | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | true random number generator | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in -:zephyr_file:`boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32pg12b500f1024gl125_defconfig` - -The default configuration when building for this EFM32JG12B SoC can be found in -:zephyr_file:`boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32jg12b500f1024gl125_defconfig` - -Other hardware features are currently not supported by the port. - -EFM32 Jade Gecko SoC --------------------- - -The EFM32 Pearl Gecko Starter Kit EFM32PG-STK3402A can also be used to evaluate -the EFM32 Jade Gecko SoC (EFM32JG12B). The only difference between the Pearl -Gecko and the Jade Gecko is their core. The Pearl Gecko contains an ARM® -Cortex®-M4F core, and the Jade Gecko an ARM® Cortex®-M3 core. Other features -such as memory and peripherals are the same. - -Code that is built for the Jade Gecko also runs on an equivalent Pearl Gecko. - -To build firmware for the Jade Gecko and run it on the EFM32 Pearl Gecko Starter -Kit, use the board ``efm32pg_stk3402a/efm32pg12b500f1024gl125`` instead of ``efm32pg_stk3402a/efm32jg12b500f1024gl125``. - -Connections and IOs -=================== - -The EFM32PG12 SoC has twelve GPIO controllers (PORTA to PORTL), but only four -are currently enabled (PORTA, PORTB, PORTD and PORTF) for the EFM32PG-STK3402A -board. - -In the following table, the column **Name** contains pin names. For example, PE2 -means pin number 2 on PORTE, as used in the board's datasheets and manuals. - -+-------+-------------+-------------------------------------+ -| Name | Function | Usage | -+=======+=============+=====================================+ -| PF4 | GPIO | LED0 | -+-------+-------------+-------------------------------------+ -| PF5 | GPIO | LED1 | -+-------+-------------+-------------------------------------+ -| PF6 | GPIO | Push Button PB0 | -+-------+-------------+-------------------------------------+ -| PF7 | GPIO | Push Button PB1 | -+-------+-------------+-------------------------------------+ -| PA5 | GPIO | Board Controller Enable | -| | | EFM_BC_EN | -+-------+-------------+-------------------------------------+ -| PA0 | UART_TX | UART TX Console VCOM_TX US0_TX #0 | -+-------+-------------+-------------------------------------+ -| PA1 | UART_RX | UART RX Console VCOM_RX US0_RX #0 | -+-------+-------------+-------------------------------------+ -| PD10 | UART_TX | EXP12_UART_TX LEU0_TX #18 | -+-------+-------------+-------------------------------------+ -| PD11 | UART_RX | EXP14_UART_RX LEU0_RX #18 | -+-------+-------------+-------------------------------------+ -| PC10 | I2C_SDA | ENV_I2C_SDA I2C0_SDA #15 | -+-------+-------------+-------------------------------------+ -| PC11 | I2C_SCL | ENV_I2C_SCL I2C0_SCL #15 | -+-------+-------------+-------------------------------------+ - - -System Clock -============ - -The EFM32PG SoC is configured to use the 40 MHz external oscillator on the -board. - -Serial Port -=========== - -The EFM32PG SoC has four USARTs and one Low Energy UART (LEUART). - -Programming and Debugging -************************* - -.. note:: - Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ - -Flashing -======== - -The EFM32PG-STK3402A includes an `J-Link`_ serial and debug adaptor built into the -board. The adaptor provides: - -- A USB connection to the host computer, which exposes a mass storage device and a - USB serial port. -- A serial flash device, which implements the USB flash disk file storage. -- A physical UART connection which is relayed over interface USB serial port. - -Flashing an application to EFM32PG-STK3402A -------------------------------------------- - -The sample application :ref:`hello_world` is used for this example. -Build the Zephyr kernel and application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efm32pg_stk3402a/efm32pg12b500f1024gl125 - :goals: build - -Connect the EFM32PG-STK3402A to your host computer using the USB port and you -should see a USB connection which exposes a mass storage device(STK3402A). -Copy the generated zephyr.bin to the STK3402A drive. - -Use a USB-to-UART converter such as an FT232/CP2102 to connect to the UART on the -expansion header. - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you'll see the following message on the corresponding serial port -terminal session: - -.. code-block:: console - - Hello World! arm - - -.. _EFM32PG-STK3402A Website: - https://www.silabs.com/products/development-tools/mcu/32-bit/efm32-pearl-gecko-pg12-starter-kit - -.. _EFM32PG-STK3402A User Guide: - https://www.silabs.com/documents/public/user-guides/ug257-stk3402-usersguide.pdf - -.. _EFM32PG-STK3402A Schematics: - https://www.silabs.com/documents/public/schematic-files/BRD2501A-A01-schematic.pdf - -.. _EFM32PG Website: - https://www.silabs.com/products/mcu/32-bit/efm32-pearl-gecko - -.. _EFM32PG12 Datasheet: - https://www.silabs.com/documents/public/data-sheets/efm32pg12-datasheet.pdf - -.. _EFM32PG12 Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/efm32pg12-rm.pdf - -.. _J-Link: - https://www.segger.com/jlink-debug-probes.html - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_common.dtsi b/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_common.dtsi deleted file mode 100644 index 05729334fcd..00000000000 --- a/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_common.dtsi +++ /dev/null @@ -1,166 +0,0 @@ -/* - * Copyright (c) 2017 Christian Taedcke - * Copyright (c) 2019 Lemonbeat GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "efm32pg_stk3402a-pinctrl.dtsi" -#include - -/ { - model = "Silicon Labs EFM32PG STK3402A board"; - - chosen { - zephyr,console = &usart0; - zephyr,shell-uart = &usart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0; - led1 = &led1; - pwm-led0 = &pwm_led0; - sw0 = &button0; - sw1 = &button1; - watchdog0 = &wdog0; - watchdog1 = &wdog1; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpiof 4 0>; - label = "LED 0"; - }; - led1: led_1 { - gpios = <&gpiof 5 0>; - label = "LED 1"; - }; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - /* gpio flags need validation */ - gpios = <&gpiof 6 GPIO_ACTIVE_LOW>; - label = "User Push Button 0"; - zephyr,code = ; - }; - button1: button_1 { - /* gpio flags need validation */ - gpios = <&gpiof 7 GPIO_ACTIVE_LOW>; - label = "User Push Button 1"; - zephyr,code = ; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - status = "okay"; - pwm_led0: pwm_led0 { - pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; - }; - }; -}; - -&cpu0 { - clock-frequency = <40000000>; -}; - -&usart0 { - current-speed = <115200>; - pinctrl-0 = <&usart0_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&leuart0 { - current-speed = <9600>; - location-rx = ; - location-tx = ; - status = "okay"; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&rtcc0 { - prescaler = <1>; - status = "okay"; -}; - -&timer0 { - status = "okay"; - - pwm0: pwm { - status = "okay"; - pin-location = ; - prescaler = <1024>; - }; -}; - -&gpio { - location-swo = <0>; - status = "okay"; -}; - -&gpioa { - status = "okay"; - - board-controller-enable { - gpio-hog; - gpios = <5 GPIO_ACTIVE_HIGH>; - output-high; - }; -}; - -&gpiob { - status = "okay"; -}; - -&gpiod { - status = "okay"; -}; - -&gpiof { - status = "okay"; -}; - -&wdog0 { - status = "okay"; -}; - -&wdog1 { - status = "okay"; -}; - - -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Set 6Kb of storage at the end of the 1024Kb of flash */ - storage_partition: partition@fe800 { - label = "storage"; - reg = <0x000fe800 0x00001800>; - }; - - }; -}; - -&trng0 { - status = "okay"; -}; - -&adc0 { - status = "okay"; -}; diff --git a/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32jg12b500f1024gl125.dts b/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32jg12b500f1024gl125.dts deleted file mode 100644 index 090b217e49a..00000000000 --- a/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32jg12b500f1024gl125.dts +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2019 Lemonbeat GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "efm32pg_stk3402a_common.dtsi" - -/ { - model = "Silicon Labs EFM32PG STK3402A board (JG)"; - compatible = "silabs,efm32pg_stk3402a_jg", "silabs,efm32jg12b"; - -}; diff --git a/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32jg12b500f1024gl125.yaml b/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32jg12b500f1024gl125.yaml deleted file mode 100644 index 7373e65edb2..00000000000 --- a/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32jg12b500f1024gl125.yaml +++ /dev/null @@ -1,19 +0,0 @@ -identifier: efm32pg_stk3402a/efm32jg12b500f1024gl125 -name: EFM32PG-STK3402A-JG -type: mcu -arch: arm -ram: 256 -flash: 1024 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - i2c - - gpio - - nvs -testing: - ignore_tags: - - net - - bluetooth -vendor: silabs diff --git a/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32pg12b500f1024gl125.dts b/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32pg12b500f1024gl125.dts deleted file mode 100644 index a4e98955ae3..00000000000 --- a/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32pg12b500f1024gl125.dts +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2017 Christian Taedcke - * Copyright (c) 2019 Lemonbeat GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "efm32pg_stk3402a_common.dtsi" - -/ { - model = "Silicon Labs EFM32PG STK3402A board"; - compatible = "silabs,efm32pg_stk3402a", "silabs,efm32pg12b"; -}; diff --git a/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32pg12b500f1024gl125.yaml b/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32pg12b500f1024gl125.yaml deleted file mode 100644 index 153ebae67ef..00000000000 --- a/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32pg12b500f1024gl125.yaml +++ /dev/null @@ -1,20 +0,0 @@ -identifier: efm32pg_stk3402a/efm32pg12b500f1024gl125 -name: EFM32PG-STK3402A -type: mcu -arch: arm -ram: 256 -flash: 1024 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - i2c - - gpio - - nvs - - watchdog -testing: - ignore_tags: - - net - - bluetooth -vendor: silabs diff --git a/boards/silabs/efm32wg_stk3800/doc/index.rst b/boards/silabs/efm32wg_stk3800/doc/index.rst deleted file mode 100644 index 30810f0d71e..00000000000 --- a/boards/silabs/efm32wg_stk3800/doc/index.rst +++ /dev/null @@ -1,177 +0,0 @@ -.. _efm32wg_stk3800: - -EFM32WG-STK3800 -############### - -Overview -******** - -The EFM32 Wonder Gecko Starter Kit EFM32WG-STK3800 contains a MCU from the -EFM32WG family built on ARM® Cortex®-M4F processor with excellent low -power capabilities. - -.. figure:: efm32wg_stk3800.jpg - :align: center - :alt: EFM32WG-STK3800 - - EFM32WG-STK3800 (image courtesy of Silicon Labs) - - -Hardware -******** - -- Advanced Energy Monitoring provides real-time information about the energy - consumption of an application or prototype design. -- 32MByte parallel NAND Flash -- 160 segment Energy Micro LCD -- 2 user buttons, 2 LEDs and a touch slider -- Ambient Light Sensor and Inductive-capacitive metal sensor -- On-board Segger J-Link USB debugger - -For more information about the EFM32WG SoC and EFM32WG-STK3800 board: - -- `EFM32WG Website`_ -- `EFM32WG Datasheet`_ -- `EFM32WG Reference Manual`_ -- `EFM32WG-STK3800 Website`_ -- `EFM32WG-STK3800 User Guide`_ -- `EFM32WG-STK3800 Schematics`_ - -Supported Features -================== - -The efm32wg_stk3800 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in -:zephyr_file:`boards/silabs/efm32wg_stk3800/efm32wg_stk3800_defconfig` - -Other hardware features are currently not supported by the port. - -Connections and IOs -=================== - -The EFM32WG SoC has six gpio controllers (PORTA to PORTF), but only three are -currently enabled (PORTB, PORTE and PORTF) for the EFM32WG-STK3800 board. - -In the following table, the column Name contains Pin names. For example, PE2 -means Pin number 2 on PORTE, as used in the board's datasheets and manuals. - -+-------+-------------+-------------------------------------+ -| Name | Function | Usage | -+=======+=============+=====================================+ -| PE2 | GPIO | LED0 | -+-------+-------------+-------------------------------------+ -| PE3 | GPIO | LED1 | -+-------+-------------+-------------------------------------+ -| PB9 | GPIO | Push Button PB0 | -+-------+-------------+-------------------------------------+ -| PB10 | GPIO | Push Button PB1 | -+-------+-------------+-------------------------------------+ -| PF7 | GPIO | Board Controller Enable | -| | | EFM_BC_EN | -+-------+-------------+-------------------------------------+ -| PE0 | UART0_TX | UART Console EFM_BC_TX U0_TX #1 | -+-------+-------------+-------------------------------------+ -| PE1 | UART0_RX | UART Console EFM_BC_RX U0_RX #1 | -+-------+-------------+-------------------------------------+ - -System Clock -============ - -The EFM32WG SoC is configured to use the 48 MHz external oscillator on the -board. - -Serial Port -=========== - -The EFM32WG SoC has three USARTs, two UARTs and two Low Energy UARTs (LEUART). -UART0 is connected to the board controller and is used for the console. - -Programming and Debugging -************************* - -.. note:: - Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ - -Flashing -======== - -The EFM32WG-STK3800 includes an `J-Link`_ serial and debug adaptor built into the -board. The adaptor provides: - -- A USB connection to the host computer, which exposes a Mass Storage and a - USB Serial Port. -- A Serial Flash device, which implements the USB flash disk file storage. -- A physical UART connection which is relayed over interface USB Serial port. - -Flashing an application to EFM32-STK3800 ----------------------------------------- - -The sample application :ref:`hello_world` is used for this example. -Build the Zephyr kernel and application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efm32wg_stk3800 - :goals: build - -Connect the EFM32WG-STK3800 to your host computer using the USB port and you -should see a USB connection which exposes a Mass Storage (STK3800) and a -USB Serial Port. Copy the generated zephyr.bin in the STK3800 drive. - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you should be able to see on the corresponding Serial Port -the following message: - -.. code-block:: console - - Hello World! arm - - -.. _EFM32WG-STK3800 Website: - http://www.silabs.com/products/development-tools/mcu/32-bit/efm32-wonder-gecko-starter-kit - -.. _EFM32WG-STK3800 User Guide: - http://www.silabs.com/documents/public/user-guides/efm32wg-stk3800-ug.pdf - -.. _EFM32WG-STK3800 Schematics: - http://www.silabs.com/documents/public/schematic-files/BRD2400A_A00.pdf - -.. _EFM32WG Website: - http://www.silabs.com/products/mcu/32-bit/efm32-wonder-gecko - -.. _EFM32WG Datasheet: - http://www.silabs.com/documents/public/data-sheets/EFM32WG990.pdf - -.. _EFM32WG Reference Manual: - http://www.silabs.com/documents/public/reference-manuals/EFM32WG-RM.pdf - -.. _J-Link: - https://www.segger.com/jlink-debug-probes.html - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/silabs/efr32_radio/Kconfig.defconfig b/boards/silabs/efr32_radio/Kconfig.defconfig deleted file mode 100644 index 90a2ab3dd02..00000000000 --- a/boards/silabs/efr32_radio/Kconfig.defconfig +++ /dev/null @@ -1,50 +0,0 @@ -# EFR32 radio board - -# Copyright (c) 2020 Piotr Mienkowski -# Copyright (c) 2020 TriaGnoSys GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EFR32_RADIO - -config CMU_HFXO_FREQ - default 39000000 if BOARD_EFR32_RADIO_EFR32MG24B220F1536IM48 - default 38400000 - -config CMU_LFXO_FREQ - default 32768 - -config FLASH_BASE_ADDRESS - hex - default 0x08000000 if BOARD_EFR32_RADIO_EFR32MG24B220F1536IM48 - default 0x0 - -config LOG_BACKEND_SWO_FREQ_HZ - default 875000 - depends on LOG_BACKEND_SWO - -if SOC_GECKO_USE_RAIL - -config FPU - default n if SOC_FAMILY_SILABS_S1 - default y - -endif # SOC_GECKO_USE_RAIL - -if BT - -config FPU - default y - -config MINIMAL_LIBC_MALLOC_ARENA_SIZE - default 8192 - -config MAIN_STACK_SIZE - default 3072 if PM - default 2304 - -config BT_SILABS_HCI - default y - -endif # BT - -endif # BOARD_EFR32_RADIO diff --git a/boards/silabs/efr32_radio/Kconfig.efr32_radio b/boards/silabs/efr32_radio/Kconfig.efr32_radio deleted file mode 100644 index 1ebc6a94455..00000000000 --- a/boards/silabs/efr32_radio/Kconfig.efr32_radio +++ /dev/null @@ -1,15 +0,0 @@ -# EFR32BG13 BRD4104A / EFR32MG21 BRD4180A / -# EFR32FG1P BRD4250B / EFR32FG13P BRD4255A board - -# Copyright (c) 2020 Piotr Mienkowski -# Copyright (c) 2020 TriaGnoSys GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFR32_RADIO - select SOC_PART_NUMBER_EFR32BG13P632F512GM48 if BOARD_EFR32_RADIO_EFR32BG13P632F512GM48 - select SOC_PART_NUMBER_EFR32MG12P433F1024GM68 if BOARD_EFR32_RADIO_EFR32MG12P433F1024GM68 - select SOC_PART_NUMBER_EFR32MG12P432F1024GL125 if BOARD_EFR32_RADIO_EFR32MG12P432F1024GL125 - select SOC_PART_NUMBER_EFR32FG1P133F256GM48 if BOARD_EFR32_RADIO_EFR32FG1P133F256GM48 - select SOC_PART_NUMBER_EFR32MG21A020F1024IM32 if BOARD_EFR32_RADIO_EFR32MG21A020F1024IM32 - select SOC_PART_NUMBER_EFR32MG24B220F1536IM48 if BOARD_EFR32_RADIO_EFR32MG24B220F1536IM48 - select SOC_PART_NUMBER_EFR32FG13P233F512GM48 if BOARD_EFR32_RADIO_EFR32FG13P233F512GM48 diff --git a/boards/silabs/efr32_radio/board.cmake b/boards/silabs/efr32_radio/board.cmake deleted file mode 100644 index 142165be8c7..00000000000 --- a/boards/silabs/efr32_radio/board.cmake +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(openocd) - -if(CONFIG_BOARD_EFR32_RADIO_EFR32BG13P632F512GM48) - board_runner_args(jlink "--device=EFR32BG13PxxxF512") -elseif(CONFIG_BOARD_EFR32_RADIO_EFR32FG1P133F256GM48) - board_runner_args(jlink "--device=EFR32FG1PxxxF256") -elseif(CONFIG_BOARD_EFR32_RADIO_EFR32MG12P433F1024GM68) - board_runner_args(jlink "--device=EFR32MG12PxxxF1024") -elseif(CONFIG_BOARD_EFR32_RADIO_EFR32MG12P432F1024GL125) - board_runner_args(jlink "--device=EFR32MG12PxxxF1024") -elseif(CONFIG_BOARD_EFR32_RADIO_EFR32MG21A020F1024IM32) - board_runner_args(jlink "--device=EFR32MG21AxxxF1024") -elseif(CONFIG_BOARD_EFR32_RADIO_EFR32MG24B220F1536IM48) - board_runner_args(jlink "--device=EFR32MG24BxxxF1536") -elseif(CONFIG_BOARD_EFR32_RADIO_EFR32FG13P233F512GM48) - board_runner_args(jlink "--device=EFR32FG13PxxxF512") -endif() - -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/silabs/efr32_radio/board.yml b/boards/silabs/efr32_radio/board.yml deleted file mode 100644 index 5e68cef3826..00000000000 --- a/boards/silabs/efr32_radio/board.yml +++ /dev/null @@ -1,10 +0,0 @@ -boards: - - name: efr32_radio - socs: - - name: efr32bg13p632f512gm48 - - name: efr32mg12p433f1024gm68 - - name: efr32mg12p432f1024gl125 - - name: efr32fg1p133f256gm48 - - name: efr32mg21a020f1024im32 - - name: efr32mg24b220f1536im48 - - name: efr32fg13p233f512gm48 diff --git a/boards/silabs/efr32_radio/doc/brd4104a.rst b/boards/silabs/efr32_radio/doc/brd4104a.rst deleted file mode 100644 index 7fa1336345c..00000000000 --- a/boards/silabs/efr32_radio/doc/brd4104a.rst +++ /dev/null @@ -1,122 +0,0 @@ -.. _efr32_radio_brd4104a: - -EFR32 BRD4104A (SLWRB4104A) -########################### - -Overview -******** - -The EFR32BG13 Blue Gecko Bluetooth® Low Energy Radio Board is one of the two -radio boards delivered with `SLWSTK6020B Bluetooth SoC Starter Kit`_. It -contains a Wireless System-On-Chip from the EFR32BG13 family built on an -ARM Cortex®-M4F processor with excellent low power capabilities. - -.. figure:: efr32bg13-slwrb4104a.jpg - :align: center - :alt: SLWRB4104A Blue Gecko Bluetooth® Low Energy Radio Board - - SLWRB4104A (image courtesy of Silicon Labs) - -The BRD4104A a.k.a. SLWRB4104A radio board plugs into the Wireless Starter Kit -Mainboard BRD4001A and is supported as one of :ref:`efr32_radio`. - -Hardware -******** - -- EFR32BG13P632F512GM48 Blue Gecko SoC -- CPU core: ARM Cortex®-M4 with FPU -- Flash memory: 512 kB -- RAM: 64 kB -- Transmit power: up to +10 dBm -- Operation frequency: 2.4 GHz -- 8Mbit SPI NOR Flash -- Crystals for LFXO (32.768 kHz) and HFXO (38.4 MHz). - -For more information about the EFR32BG13 SoC and BRD4104A board, refer to these -documents: - -- `EFR32BG13 Website`_ -- `EFR32BG13 Datasheet`_ -- `EFR32xG13 Reference Manual`_ -- `SLWSTK6020B Bluetooth SoC Starter Kit`_ -- `BRD4104A User Guide`_ -- `BRD4104A Reference Manual`_ -- `EFR32BG13-BRD4104A Schematics`_ - -Supported Features -================== - -Please refer to -:ref:`EFR32 Radio Board Supported Features ` -for details of the configuration and common features supported by the -``efr32_radio/efr32bg13p632f512gm48`` board. - -The default configuration can be found in -:zephyr_file:`boards/silabs/efr32_radio/efr32_radio_efr32bg13p632f512gm48_defconfig` - -System Clock -============ - -The EFR32BG13P SoC is configured to use the 38.4 MHz external oscillator on the -board. - -Serial Port -=========== - -The EFR32BG13P SoC has three USARTs and one Low Energy UARTs (LEUART). -USART0 is connected to the board controller and is used for the console. - -Programming and Debugging -************************* - -Please refer to -:ref:`Programming and Debugging EFR32 Radio Board ` -for details on the supported debug interfaces. - -Flashing -======== - -Connect the BRD4001A board with a mounted BRD4104A radio module to your host -computer using the USB port. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efr32_radio/efr32bg13p632f512gm48 - :goals: flash - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you should see the following message in the terminal: - -.. code-block:: console - - Hello World! efr32_radio - - -.. _EFR32BG13 Website: - https://www.silabs.com/wireless/bluetooth/efr32bg13-series-1-socs - -.. _EFR32BG13 Datasheet: - https://www.silabs.com/documents/public/data-sheets/efr32bg13-datasheet.pdf - -.. _EFR32xG13 Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/efr32xg13-rm.pdf - -.. _SLWSTK6020B Bluetooth SoC Starter Kit: - https://www.silabs.com/products/development-tools/wireless/bluetooth/blue-gecko-bluetooth-low-energy-soc-starter-kit - -.. _BRD4104A User Guide: - https://www.silabs.com/documents/public/user-guides/ug279-brd4104a-user-guide.pdf - -.. _BRD4104A Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/brd4104a-rm.pdf - -.. _EFR32BG13-BRD4104A Schematics: - https://www.silabs.com/documents/public/schematic-files/BRD4104A-A00-schematic.pdf diff --git a/boards/silabs/efr32_radio/doc/brd4161a.rst b/boards/silabs/efr32_radio/doc/brd4161a.rst deleted file mode 100644 index 992d5f7a4ac..00000000000 --- a/boards/silabs/efr32_radio/doc/brd4161a.rst +++ /dev/null @@ -1,108 +0,0 @@ -.. _efr32_radio_brd4161a: - -EFR32 BRD4161A (SLWRB4161A) -########################### - -Overview -******** - -The EFR32MG12 Mighty Gecko Radio Board contains a Wireless System-On-Chip -from the EFR32MG12 family built on an ARM Cortex®-M4F processor with excellent -low power capabilities. - -.. figure:: efr32mg12-slwrb4161a.jpeg - :align: center - :alt: SLWRB4161A Mighty Gecko Radio Board - - SLWRB4161A (image courtesy of Silicon Labs) - -The BRD4161A a.k.a. SLWRB4161A radio board plugs into the Wireless Starter Kit -Mainboard BRD4001A and is supported as one of :ref:`efr32_radio`. - -Hardware -******** - -- EFR32MG12P432F1024GL125 Mighty Gecko SoC -- CPU core: ARM Cortex®-M4 with FPU -- Flash memory: 1024 kB -- RAM: 256 kB -- Transmit power: up to +19 dBm -- Operation frequency: 2.4 GHz and Sub-Ghz -- Crystals for LFXO (32.768 kHz) and HFXO (38.4 MHz). - -For more information about the EFR32MG12 SoC and BRD4170A board, refer to these -documents: - -- `EFR32MG12 Website`_ -- `EFR32MG12 Datasheet`_ -- `EFR32xG12 Reference Manual`_ -- `BRD4161A User Guide`_ - -Supported Features -================== - -Please refer to -:ref:`EFR32 Radio Board Supported Features ` -for details of the configuration and common features supported by the -``efr32_radio/efr32mg12p432f1024gl125`` board. - -The default configuration can be found in -:zephyr_file:`boards/silabs/efr32_radio/efr32_radio_efr32mg12p432f1024gl125_defconfig` - -System Clock -============ - -The EFR32MG12P SoC is configured to use the 38.4 MHz external oscillator on the -board. - -Serial Port -=========== - -The EFR32MG12P SoC has four USARTs and one Low Energy UARTs (LEUART). -USART0 is connected to the board controller and is used for the console. - -Programming and Debugging -************************* - -Please refer to -:ref:`Programming and Debugging EFR32 Radio Board ` -for details on the supported debug interfaces. - -Flashing -======== - -Connect the BRD4001A board with a mounted BRD4170A radio module to your host -computer using the USB port. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efr32_radio/efr32mg12p432f1024gl125 - :goals: flash - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you should see the following message in the terminal: - -.. code-block:: console - - Hello World! efr32_radio - - -.. _EFR32MG12 Website: - https://www.silabs.com/wireless/zigbee/efr32mg12-series-1-socs - -.. _EFR32MG12 Datasheet: - https://www.silabs.com/documents/public/data-sheets/efr32mg12-datasheet.pdf - -.. _EFR32xG12 Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/efr32xg12-rm.pdf - -.. _BRD4161A User Guide: - https://www.silabs.com/documents/public/user-guides/ug260-brd4161a-user-guide.pdf diff --git a/boards/silabs/efr32_radio/doc/brd4170a.rst b/boards/silabs/efr32_radio/doc/brd4170a.rst deleted file mode 100644 index a1751424f37..00000000000 --- a/boards/silabs/efr32_radio/doc/brd4170a.rst +++ /dev/null @@ -1,108 +0,0 @@ -.. _efr32_radio_brd4170a: - -EFR32 BRD4170A (SLWRB4170A) -########################### - -Overview -******** - -The EFR32MG12 Mighty Gecko Radio Board contains a Wireless System-On-Chip -from the EFR32MG12 family built on an ARM Cortex®-M4F processor with excellent -low power capabilities. - -.. figure:: efr32mg12-slwrb4170a.jpg - :align: center - :alt: SLWRB4170A Mighty Gecko Radio Board - - SLWRB4170A (image courtesy of Silicon Labs) - -The BRD4170A a.k.a. SLWRB4170A radio board plugs into the Wireless Starter Kit -Mainboard BRD4001A and is supported as one of :ref:`efr32_radio`. - -Hardware -******** - -- EFR32MG12P433F1024GM68 Mighty Gecko SoC -- CPU core: ARM Cortex®-M4 with FPU -- Flash memory: 1024 kB -- RAM: 256 kB -- Transmit power: up to +19 dBm -- Operation frequency: 2.4 GHz and Sub-Ghz -- Crystals for LFXO (32.768 kHz) and HFXO (38.4 MHz). - -For more information about the EFR32MG12 SoC and BRD4170A board, refer to these -documents: - -- `EFR32MG12 Website`_ -- `EFR32MG12 Datasheet`_ -- `EFR32xG12 Reference Manual`_ -- `BRD4170A User Guide`_ - -Supported Features -================== - -Please refer to -:ref:`EFR32 Radio Board Supported Features ` -for details of the configuration and common features supported by the -``efr32_radio/efr32mg12p433f1024gm68`` board. - -The default configuration can be found in -:zephyr_file:`boards/silabs/efr32_radio/efr32_radio_efr32mg12p433f1024gm68_defconfig` - -System Clock -============ - -The EFR32MG12P SoC is configured to use the 38.4 MHz external oscillator on the -board. - -Serial Port -=========== - -The EFR32MG12P SoC has four USARTs and one Low Energy UARTs (LEUART). -USART0 is connected to the board controller and is used for the console. - -Programming and Debugging -************************* - -Please refer to -:ref:`Programming and Debugging EFR32 Radio Board ` -for details on the supported debug interfaces. - -Flashing -======== - -Connect the BRD4001A board with a mounted BRD4170A radio module to your host -computer using the USB port. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efr32_radio/efr32mg12p433f1024gm68 - :goals: flash - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you should see the following message in the terminal: - -.. code-block:: console - - Hello World! efr32_radio - - -.. _EFR32MG12 Website: - https://www.silabs.com/wireless/zigbee/efr32mg12-series-1-socs - -.. _EFR32MG12 Datasheet: - https://www.silabs.com/documents/public/data-sheets/efr32mg12-datasheet.pdf - -.. _EFR32xG12 Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/efr32xg12-rm.pdf - -.. _BRD4170A User Guide: - https://www.silabs.com/documents/public/user-guides/ug342-brd4170a-user-guide.pdf diff --git a/boards/silabs/efr32_radio/doc/brd4180a.rst b/boards/silabs/efr32_radio/doc/brd4180a.rst deleted file mode 100644 index 4998122bbcd..00000000000 --- a/boards/silabs/efr32_radio/doc/brd4180a.rst +++ /dev/null @@ -1,160 +0,0 @@ -.. _efr32_radio_brd4180a: - -EFR32 BRD4180A (SLWRB4180A) -########################### - -Overview -******** - -The EFR32MG21 Mighty Gecko Radio Board is one of the two -radio boards delivered with `EFR32-SLWSTK6006A Website`_. It contains -a Wireless System-On-Chip from the EFR32MG21 family built on an -ARM Cortex®-M33F processor with excellent low power capabilities. - -.. figure:: efr32mg21-slwrb4180a.jpg - :align: center - :alt: SLWRB4180A Mighty Gecko Radio Board - - SLWRB4180A (image courtesy of Silicon Labs) - -The BRD4180A a.k.a. SLWRB4180A radio board plugs into the Wireless Starter Kit -Mainboard BRD4001A and is supported as one of :ref:`efr32_radio`. - -Hardware -******** - -- EFR32MG21A020F1024IM32 Mighty Gecko SoC -- CPU core: ARM Cortex®-M33 with FPU -- Flash memory: 1024 kB -- RAM: 96 kB -- Transmit power: up to +20 dBm -- Operation frequency: 2.4 GHz -- Crystals for LFXO (32.768 kHz) and HFXO (38.4 MHz). - -For more information about the EFR32MG21 SoC and BRD4180A board, refer to these -documents: - -- `EFR32MG21 Website`_ -- `EFR32MG21 Datasheet`_ -- `EFR32xG21 Reference Manual`_ -- `EFR32-SLWSTK6006A Website`_ -- `BRD4180A User Guide`_ - -Supported Features -================== - -The board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtcc | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c port-polling | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ - -Other hardware features are currently not supported by the port. - -Connections and IOs -=================== - -In the following table, the column **Name** contains Pin names. For example, PA2 -means Pin number 2 on PORTA, as used in the board's datasheets and manuals. - -+-------+-------------+-------------------------------------+ -| Name | Function | Usage | -+=======+=============+=====================================+ -| PB0 | GPIO | LED0 | -+-------+-------------+-------------------------------------+ -| PB1 | GPIO | LED1 | -+-------+-------------+-------------------------------------+ -| PD2 | GPIO | Push Button PB0 | -+-------+-------------+-------------------------------------+ -| PD3 | GPIO | Push Button PB1 | -+-------+-------------+-------------------------------------+ -| PD4 | GPIO | Board Controller Enable | -| | | EFM_BC_EN | -+-------+-------------+-------------------------------------+ -| PA5 | USART1_TX | UART Console EFM_BC_TX US1_TX | -+-------+-------------+-------------------------------------+ -| PA6 | USART1_RX | UART Console EFM_BC_RX US1_RX | -+-------+-------------+-------------------------------------+ - -The default configuration can be found in -:zephyr_file:`boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32_defconfig` - -System Clock -============ - -The EFR32MG21 SoC is configured to use the 38.4 MHz external oscillator on the -board. - -Serial Port -=========== - -The EFR32MG21 SoC has three USARTs. -USART0 is connected to the board controller and is used for the console. - -Programming and Debugging -************************* - -Please refer to -:ref:`Programming and Debugging EFR32 Radio Board ` -for details on the supported debug interfaces. - -Flashing -======== - -Connect the BRD4001A board with a mounted BRD4180A radio module to your host -computer using the USB port. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efr32_radio/efr32mg21a020f1024im32 - :goals: flash - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you should see the following message in the terminal: - -.. code-block:: console - - Hello World! efr32_radio - - -.. _EFR32-SLWSTK6006A Website: - https://www.silabs.com/products/development-tools/wireless/efr32xg21-wireless-starter-kit - -.. _BRD4180A User Guide: - https://www.silabs.com/documents/public/user-guides/ug385-brd4180a-user-guide.pdf - -.. _EFR32MG21 Website: - https://www.silabs.com/products/wireless/mesh-networking/efr32mg21-series-2-socs - -.. _EFR32MG21 Datasheet: - https://www.silabs.com/documents/public/data-sheets/efr32mg21-datasheet.pdf - -.. _EFR32xG21 Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/efr32xg21-rm.pdf diff --git a/boards/silabs/efr32_radio/doc/brd4187c.rst b/boards/silabs/efr32_radio/doc/brd4187c.rst deleted file mode 100644 index f5a3cd808dd..00000000000 --- a/boards/silabs/efr32_radio/doc/brd4187c.rst +++ /dev/null @@ -1,161 +0,0 @@ -.. _efr32_radio_brd4187c: - -EFR32 BRD4187C (xG24-RB4187C) -############################# - -Overview -******** - -The EFR32MG24 Mighty Gecko Radio Board is one of the two -radio boards delivered with `xG24-PK6010A Website`_. It contains -a Wireless System-On-Chip from the EFR32MG24 family built on an -ARM Cortex®-M33F processor with excellent low power capabilities. - -.. figure:: efr32mg24-xg24-rb4187c.jpg - :align: center - :alt: xG24-RB4187C Mighty Gecko Radio Board - - xG24-RB4187C (image courtesy of Silicon Labs) - -The BRD4187C a.k.a. xG24-RB4187C radio board plugs into the Wireless Pro Kit -Mainboard BRD4002A and is supported as one of :ref:`efr32_radio`. - -Hardware -******** - -- EFR32MG24B220F1536IM48 Mighty Gecko SoC -- CPU core: ARM Cortex®-M33 with FPU -- Flash memory: 1536 kB -- RAM: 256 kB -- Transmit power: up to +20 dBm -- Operation frequency: 2.4 GHz -- Crystals for LFXO (32.768 kHz) and HFXO (39 MHz). - -For more information about the EFR32MG24 SoC and BRD4187C board, refer to these -documents: - -- `EFR32MG24 Website`_ -- `EFR32MG24 Datasheet`_ -- `EFR32xG24 Reference Manual`_ -- `xG24-PK6010A Website`_ -- `BRD4187C User Guide`_ - -Supported Features -================== - -The board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | stimer | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | semailbox | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ - -Other hardware features are currently not supported by the port. - -Connections and IOs -=================== - -In the following table, the column **Name** contains Pin names. For example, PA2 -means Pin number 2 on PORTA, as used in the board's datasheets and manuals. - -+-------+-------------+-------------------------------------+ -| Name | Function | Usage | -+=======+=============+=====================================+ -| PB2 | GPIO | LED0 | -+-------+-------------+-------------------------------------+ -| PB4 | GPIO | LED1 | -+-------+-------------+-------------------------------------+ -| PB1 | GPIO | Push Button 0 | -+-------+-------------+-------------------------------------+ -| PB3 | GPIO | Push Button 1 | -+-------+-------------+-------------------------------------+ -| PB0 | GPIO | Board Controller Enable | -| | | VCOM_ENABLE | -+-------+-------------+-------------------------------------+ -| PA8 | USART0_TX | UART Console VCOM_TX US0_TX | -+-------+-------------+-------------------------------------+ -| PA9 | USART0_RX | UART Console VCOM_RX US0_RX | -+-------+-------------+-------------------------------------+ - -The default configuration can be found in -:zephyr_file:`boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48_defconfig` - -System Clock -============ - -The EFR32MG24 SoC is configured to use the 39 MHz external oscillator on the -board. - -Serial Port -=========== - -The EFR32MG24 SoC has one USART and two EUSARTs. -USART0 is connected to the board controller and is used for the console. - -Programming and Debugging -************************* - -Please refer to -:ref:`Programming and Debugging EFR32 Radio Board ` -for details on the supported debug interfaces. - -Flashing -======== - -Connect the BRD4002A board with a mounted BRD4187C radio module to your host -computer using the USB port. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efr32_radio/efr32mg24b220f1536im48 - :goals: flash - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you should see the following message in the terminal: - -.. code-block:: console - - Hello World! efr32_radio - - -.. _xG24-PK6010A Website: - https://www.silabs.com/development-tools/wireless/efr32xg24-pro-kit-20-dbm - -.. _BRD4187C User Guide: - https://www.silabs.com/documents/public/user-guides/ug526-brd4187c-user-guide.pdf - -.. _EFR32MG24 Website: - https://www.silabs.com/wireless/zigbee/efr32mg24-series-2-socs - -.. _EFR32MG24 Datasheet: - https://www.silabs.com/documents/public/data-sheets/efr32mg24-datasheet.pdf - -.. _EFR32xG24 Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/brd4187c-rm.pdf diff --git a/boards/silabs/efr32_radio/doc/brd4250b.rst b/boards/silabs/efr32_radio/doc/brd4250b.rst deleted file mode 100644 index 6ccb4ca22ca..00000000000 --- a/boards/silabs/efr32_radio/doc/brd4250b.rst +++ /dev/null @@ -1,121 +0,0 @@ -.. _efr32_radio_brd4250b: - -EFR32 BRD4250B (SLWRB4250B) -########################### - -Overview -******** - -The EFR32FG1 Flex Gecko 2.4 GHz and 868 MHz Radio Board is delivered as part of -`SLWSTK6061B Proprietary Wireless Starter Kit`_. It contains a EFR32FG1 Wireless -SoC built on an ARM Cortex®-M4F processor with excellent low power capabilities. - -.. figure:: efr32fg1-slwrb4250b.jpg - :align: center - :alt: SLWRB4250B Flex Gecko 2.4 GHz and 868 MHz Radio Board - - SLWRB4250B (image courtesy of Silicon Labs) - -The BRD4250B a.k.a. SLWRB4250B radio board plugs into the Wireless Starter Kit -Mainboard BRD4001A and is supported as one of :ref:`efr32_radio`. - -Hardware -******** - -- EFR32FG1P133F256GM48 Flex Gecko SoC -- CPU core: ARM Cortex®-M4 with FPU -- Flash memory: 256 kB -- RAM: 32 kB -- Transmit power: up to +13 dBm -- Operation frequency: 2.4 GHz, 868 MHz -- 8Mbit SPI NOR Flash -- Crystals for LFXO (32.768 kHz) and HFXO (38.4 MHz). - -For more information about the EFR32FG1 SoC and BRD4250B board, refer to these -documents: - -- `EFR32FG1 Website`_ -- `EFR32FG1 Datasheet`_ -- `EFR32xG1 Reference Manual`_ -- `SLWSTK6061B Proprietary Wireless Starter Kit`_ -- `BRD4250B User Guide`_ -- `BRD4250B Reference Manual`_ -- `EFR32FG1-BRD4250B Schematics`_ - -Supported Features -================== - -Please refer to -:ref:`EFR32 Radio Board Supported Features ` -for details of the configuration and common features supported by the -``efr32_radio/efr32fg1p133f256gm48`` board. - -The default configuration can be found in -:zephyr_file:`boards/silabs/efr32_radio/efr32_radio_efr32fg1p133f256gm48_defconfig` - -System Clock -============ - -The EFR32FG1P SoC is configured to use the 38.4 MHz external oscillator on the -board. - -Serial Port -=========== - -The EFR32FG1P SoC has two USARTs and one Low Energy UARTs (LEUART). -USART0 is connected to the board controller and is used for the console. - -Programming and Debugging -************************* - -Please refer to -:ref:`Programming and Debugging EFR32 Radio Board ` -for details on the supported debug interfaces. - -Flashing -======== - -Connect the BRD4001A board with a mounted BRD4250B radio module to your host -computer using the USB port. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efr32_radio/efr32fg1p133f256gm48 - :goals: flash - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you should see the following message in the terminal: - -.. code-block:: console - - Hello World! efr32_radio - - -.. _EFR32FG1 Website: - https://www.silabs.com/wireless/proprietary/efr32fg1-series-1-sub-ghz-2-4-ghz-socs - -.. _EFR32FG1 Datasheet: - https://www.silabs.com/documents/public/data-sheets/efr32fg1-datasheet.pdf - -.. _EFR32xG1 Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/efr32xg1-rm.pdf - -.. _SLWSTK6061B Proprietary Wireless Starter Kit: - https://www.silabs.com/products/development-tools/wireless/proprietary/slwstk6061b-efr32-flex-gecko-868-mhz-2-4-ghz-and-sub-ghz-starter-kit - -.. _BRD4250B User Guide: - https://www.silabs.com/documents/public/user-guides/ug182-brd4250b-user-guide.pdf - -.. _BRD4250B Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/brd4250b-rm.pdf - -.. _EFR32FG1-BRD4250B Schematics: - https://www.silabs.com/documents/public/schematic-files/BRD4250B-B02-schematic.pdf diff --git a/boards/silabs/efr32_radio/doc/brd4255a.rst b/boards/silabs/efr32_radio/doc/brd4255a.rst deleted file mode 100644 index 60138f08610..00000000000 --- a/boards/silabs/efr32_radio/doc/brd4255a.rst +++ /dev/null @@ -1,111 +0,0 @@ -.. _efr32_radio_brd4255a: - -EFR32 BRD4255A (SLWRB4255A) -########################### - -Overview -******** - -The EFR32FG13P Flex Gecko 2.4 GHz and 915 MHz Radio Board is delivered as a -`standalone Proprietary Wireless radio board`_. It contains a EFR32FG13P Wireless -SoC built on an ARM Cortex®-M4F processor with excellent low power capabilities. - -.. figure:: efr32fg13-slwrb4255a.jpg - :align: center - :alt: SLWRB4255A Flex Gecko 2.4 GHz and 915 MHz Radio Board - - SLWRB4255A (image courtesy of Silicon Labs) - -The BRD4255A a.k.a. SLWRB4255A radio board plugs into the Wireless Starter Kit -Mainboard BRD4001A and is supported as one of :ref:`efr32_radio`. - -Hardware -******** - -- EFR32FG13P233F512GM48 Flex Gecko SoC -- CPU core: ARM Cortex®-M4 with FPU -- Flash memory: 512 kB -- RAM: 64 kB -- Transmit power: up to 19 dBm -- Operation frequency: 2.4 GHz, 915 MHz -- Crystals for LFXO (32.768 kHz) and HFXO (38.4 MHz). - -For more information about the EFR32FG13 SoC and BRD4255A board, refer to these -documents: - -- `EFR32FG13 Website`_ -- `EFR32FG13 Datasheet`_ -- `EFR32xG13 Reference Manual`_ -- `BRD4255A Reference Manual`_ - -Supported Features -================== - -Please refer to -:ref:`EFR32 Radio Board Supported Features ` -for details of the configuration and common features supported by the -``efr32_radio/efr32fg13p233f512gm48`` board. - -The default configuration can be found in -:zephyr_file:`boards/silabs/efr32_radio/efr32_radio_efr32fg13p233f512gm48_defconfig` - -System Clock -============ - -The EFR32FG13P SoC is configured to use the 38.4 MHz external oscillator on the -board. - -Serial Port -=========== - -The EFR32FG13P SoC has three USARTs and one Low Energy UARTs (LEUART). -USART0 is connected to the board controller and is used for the console. - -Programming and Debugging -************************* - -Please refer to -:ref:`Programming and Debugging EFR32 Radio Board ` -for details on the supported debug interfaces. - -Flashing -======== - -Connect the BRD4001A board with a mounted BRD4255A radio module to your host -computer using the USB port. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efr32_radio/efr32fg13p233f512gm48 - :goals: flash - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you should see the following message in the terminal: - -.. code-block:: console - - Hello World! efr32_radio - - -.. _EFR32FG13 Website: - https://www.silabs.com/wireless/proprietary/efr32fg13-series-1-sub-ghz-2-4-ghz-socs - -.. _EFR32FG13 Datasheet: - https://www.silabs.com/documents/public/data-sheets/efr32fg13-datasheet.pdf - -.. _EFR32xG13 Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/efr32xg13-rm.pdf - -.. _standalone Proprietary Wireless radio board: - https://www.silabs.com/development-tools/wireless/proprietary/slwrb4255a-efr32fg13-915-mhz-radio-board - -.. _BRD4255A Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/brd4255a-rm.pdf diff --git a/boards/silabs/efr32_radio/doc/efr32_slwstk6020b.jpg b/boards/silabs/efr32_radio/doc/efr32_slwstk6020b.jpg deleted file mode 100644 index 5a93d75ff94..00000000000 Binary files a/boards/silabs/efr32_radio/doc/efr32_slwstk6020b.jpg and /dev/null differ diff --git a/boards/silabs/efr32_radio/doc/index.rst b/boards/silabs/efr32_radio/doc/index.rst deleted file mode 100644 index 31f79df34e0..00000000000 --- a/boards/silabs/efr32_radio/doc/index.rst +++ /dev/null @@ -1,190 +0,0 @@ -.. _efr32_radio: - -EFR32 Radio Boards -################## - -.. toctree:: - :maxdepth: 1 - - brd4104a.rst - brd4170a.rst - brd4250b.rst - brd4180a.rst - brd4255a.rst - brd4187c.rst - -Overview -******** - -Support for EFR32 Radio boards is provided by one of the starter kits - -- `SLWSTK6020B Bluetooth SoC Starter Kit`_ -- `SLWSTK6000B Mighty Gecko Wireless Starter Kit`_ -- `SLWSTK6061B Proprietary Wireless Starter Kit`_ -- `SLWSTK6006A Mighty Gecko Wireless Starter Kit`_ - -.. figure:: efr32_slwstk6020b.jpg - :align: center - :alt: SLWSTK6020B Bluetooth SoC Starter Kit - - SLWSTK6020B (image courtesy of Silicon Labs) - -Hardware -******** - -Wireless Starter Kit Mainboard: - -- Advanced Energy Monitoring provides real-time information about the energy - consumption of an application or prototype design. -- Ultra-low power 128x128 pixel memory LCD -- 2 user buttons and 2 LEDs -- 20 pin expansion header -- Si7021 Humidity and Temperature Sensor -- On-board Segger J-Link USB and Ethernet debugger - -For more information about the BRD4001A board, refer to these documents: - -- `EFR32BG13 Blue Gecko Bluetooth Starter Kit User's Guide`_ -- `EFR32MG21 Mighty Gecko Wireless Starter Kit User's Guide`_ -- `WSTK Main Board BRD4001A Schematics`_ - -.. _efr32_radio_supported_features: - -Supported Features -================== - -The board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtcc | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| SPI(M) | on-chip | spi port-polling | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ - -Other hardware features are currently not supported by the port. - -Connections and IOs -=================== - -In the following table, the column **Name** contains Pin names. For example, PA2 -means Pin number 2 on PORTA, as used in the board's datasheets and manuals. - -+-------+-------------+-------------------------------------+ -| Name | Function | Usage | -+=======+=============+=====================================+ -| PF4 | GPIO | LED0 | -+-------+-------------+-------------------------------------+ -| PF5 | GPIO | LED1 | -+-------+-------------+-------------------------------------+ -| PF6 | GPIO | Push Button PB0 | -+-------+-------------+-------------------------------------+ -| PF7 | GPIO | Push Button PB1 | -+-------+-------------+-------------------------------------+ -| PA5 | GPIO | Board Controller Enable | -| | | EFM_BC_EN | -+-------+-------------+-------------------------------------+ -| PA0 | USART0_TX | UART Console EFM_BC_TX US0_TX #0 | -+-------+-------------+-------------------------------------+ -| PA1 | USART0_RX | UART Console EFM_BC_RX US0_RX #0 | -+-------+-------------+-------------------------------------+ -| PC6 | SPI_MOSI | Flash MOSI US1_TX #11 | -+-------+-------------+-------------------------------------+ -| PC7 | SPI_MISO | Flash MISO US1_RX #11 | -+-------+-------------+-------------------------------------+ -| PC8 | SPI_SCLK | Flash SCLK US1_CLK #11 | -+-------+-------------+-------------------------------------+ -| PA4 | SPI_CS | Flash Chip Select (GPIO) | -+-------+-------------+-------------------------------------+ - -.. _efr32_radio_programming: - -Programming and Debugging -************************* - -The BRD4001A includes an `J-Link`_ serial and debug adaptor built into the -board. The adaptor provides: - -- A USB connection to the host computer, which exposes a debug interface and a - USB Serial Port. -- A physical UART connection which is relayed over interface USB Serial port. -- An Ethernet connection to support remote debugging. - -It is compatible with the following host debug tools: - -- :ref:`openocd-debug-host-tools` -- :ref:`jlink-debug-host-tools` - -OpenOCD is included in the Zephyr SDK. Refer to the links above for information -on how to install required host debug tools if you are not using the Zephyr SDK. - -Flashing -======== - -Connect the BRD4001A main board with the mounted radio module to your host -computer using the USB port. - -Following example shows how to build the :ref:`hello_world` application for -BRD4104A radio module. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efr32_radio_brd4104a - :goals: flash - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you should see the following message in the terminal: - -.. code-block:: console - - Hello World! efr32_radio_brd4104a - - -.. _SLWSTK6020B Bluetooth SoC Starter Kit: - https://www.silabs.com/products/development-tools/wireless/bluetooth/blue-gecko-bluetooth-low-energy-soc-starter-kit - -.. _SLWSTK6000B Mighty Gecko Wireless Starter Kit: - https://www.silabs.com/products/development-tools/wireless/mesh-networking/mighty-gecko-starter-kit - -.. _SLWSTK6061B Proprietary Wireless Starter Kit: - https://www.silabs.com/products/development-tools/wireless/proprietary/slwstk6061b-efr32-flex-gecko-868-mhz-2-4-ghz-and-sub-ghz-starter-kit - -.. _SLWSTK6006A Mighty Gecko Wireless Starter Kit: - https://www.silabs.com/products/development-tools/wireless/efr32xg21-wireless-starter-kit - -.. _EFR32BG13 Blue Gecko Bluetooth Starter Kit User's Guide: - https://www.silabs.com/documents/public/user-guides/ug279-brd4104a-user-guide.pdf - -.. _EFR32MG21 Mighty Gecko Wireless Starter Kit User's Guide: - https://www.silabs.com/documents/public/user-guides/ug385-brd4180a-user-guide.pdf - -.. _EFR32MG24 Mighty Gecko Wireless Starter Kit User's Guide: - https://www.silabs.com/documents/public/user-guides/ug526-brd4187c-user-guide.pdf - -.. _WSTK Main Board BRD4001A Schematics: - https://www.silabs.com/documents/public/schematic-files/BRD4001A-A01-schematic.pdf - -.. _J-Link: - https://www.segger.com/jlink-debug-probes.html diff --git a/boards/silabs/efr32_radio/efr32_radio-pinctrl.dtsi b/boards/silabs/efr32_radio/efr32_radio-pinctrl.dtsi deleted file mode 100644 index ade31fddfd8..00000000000 --- a/boards/silabs/efr32_radio/efr32_radio-pinctrl.dtsi +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2023 Antmicro - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -&pinctrl { - /* configuration for usart0 device, default state - operating as UART */ - usart0_default: usart0_default { - group1 { - psels = , - , - , - ; - }; - }; -}; diff --git a/boards/silabs/efr32_radio/efr32_radio.dtsi b/boards/silabs/efr32_radio/efr32_radio.dtsi deleted file mode 100644 index 361b66b72df..00000000000 --- a/boards/silabs/efr32_radio/efr32_radio.dtsi +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright (c) 2020 Piotr Mienkowski - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include "efr32_radio-pinctrl.dtsi" - -/ { - chosen { - zephyr,console = &usart0; - zephyr,shell-uart = &usart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0; - led1 = &led1; - sw0 = &button0; - sw1 = &button1; - watchdog0 = &wdog0; - spi-flash0 = &mx25r80; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpiof 4 0>; - label = "LED 0"; - }; - led1: led_1 { - gpios = <&gpiof 5 0>; - label = "LED 1"; - }; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - /* gpio flags need validation */ - gpios = <&gpiof 6 GPIO_ACTIVE_LOW>; - label = "User Push Button 0"; - zephyr,code = ; - }; - button1: button_1 { - /* gpio flags need validation */ - gpios = <&gpiof 7 GPIO_ACTIVE_LOW>; - label = "User Push Button 1"; - zephyr,code = ; - }; - }; - -}; - -&usart0 { - current-speed = <115200>; - pinctrl-0 = <&usart0_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usart1 { - compatible = "silabs,gecko-spi-usart"; - - #address-cells = <1>; - #size-cells = <0>; - - location-rx = ; - location-tx = ; - location-clk = ; - - cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>; - - status = "okay"; - - mx25r80: mx25r8035f@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <33000000>; - size = <0x800000>; - jedec-id = [c2 28 14]; - }; -}; - -&rtcc0 { - prescaler = <1>; - status = "okay"; -}; - -&gpio { - location-swo = <0>; - status = "okay"; -}; - -&gpioa { - status = "okay"; - - board-controller-enable { - gpio-hog; - gpios = <5 GPIO_ACTIVE_HIGH>; - output-high; - }; -}; - -&gpiob { - status = "okay"; -}; - -&gpioc { - status = "okay"; -}; - -&gpiod { - status = "okay"; -}; - -&gpiof { - status = "okay"; -}; - -&wdog0 { - status = "okay"; -}; diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32bg13p632f512gm48.dts b/boards/silabs/efr32_radio/efr32_radio_efr32bg13p632f512gm48.dts deleted file mode 100644 index 9ded71ef559..00000000000 --- a/boards/silabs/efr32_radio/efr32_radio_efr32bg13p632f512gm48.dts +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2020 Piotr Mienkowski - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "efr32_radio.dtsi" - -/ { - model = "Silicon Labs BRD4104A (Blue Gecko Radio Board)"; - compatible = "silabs,efr32_radio_brd4104a", "silabs,efr32bg13p"; - - aliases { - spi-flash0 = &mx25r80; - }; -}; - -&cpu0 { - clock-frequency = <38400000>; -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 32 kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x0 0x00008000>; - read-only; - }; - - /* Reserve 220 kB for the application in slot 0 */ - slot0_partition: partition@8000 { - label = "image-0"; - reg = <0x00008000 0x00037000>; - }; - - /* Reserve 220 kB for the application in slot 1 */ - slot1_partition: partition@3f000 { - label = "image-1"; - reg = <0x0003f000 0x00037000>; - }; - - /* Reserve 32 kB for the scratch partition */ - scratch_partition: partition@76000 { - label = "image-scratch"; - reg = <0x00076000 0x00008000>; - }; - - /* Set 8Kb of storage at the end of the 512KB of flash */ - storage_partition: partition@7e000 { - label = "storage"; - reg = <0x0007e000 0x00002000>; - }; - - }; -}; diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32bg13p632f512gm48.yaml b/boards/silabs/efr32_radio/efr32_radio_efr32bg13p632f512gm48.yaml deleted file mode 100644 index 8edaadbadf7..00000000000 --- a/boards/silabs/efr32_radio/efr32_radio_efr32bg13p632f512gm48.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: efr32_radio/efr32bg13p632f512gm48 -name: BRD4104A -type: mcu -arch: arm -ram: 64 -flash: 512 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - counter - - gpio - - nvs - - spi - - uart - - watchdog -testing: - ignore_tags: - - net - - bluetooth -vendor: silabs diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32fg13p233f512gm48.dts b/boards/silabs/efr32_radio/efr32_radio_efr32fg13p233f512gm48.dts deleted file mode 100644 index cf146428322..00000000000 --- a/boards/silabs/efr32_radio/efr32_radio_efr32fg13p233f512gm48.dts +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (c) 2020 Piotr Mienkowski - * Copyright (c) 2021 Yonatan Schachter - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include -#include "efr32_radio.dtsi" - -/ { - model = "Silicon Labs BRD4255A (Flex Gecko Radio Board)"; - compatible = "silabs,efr32_radio_brd4255a", "silabs,efr32fg13p"; -}; - -&cpu0 { - clock-frequency = <38400000>; -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 32 kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x0 0x00008000>; - read-only; - }; - - /* Reserve 220 kB for the application in slot 0 */ - slot0_partition: partition@8000 { - label = "image-0"; - reg = <0x00008000 0x00037000>; - }; - - /* Reserve 220 kB for the application in slot 1 */ - slot1_partition: partition@3f000 { - label = "image-1"; - reg = <0x0003f000 0x00037000>; - }; - - /* Reserve 32 kB for the scratch partition */ - scratch_partition: partition@76000 { - label = "image-scratch"; - reg = <0x00076000 0x00008000>; - }; - - /* Set 8Kb of storage at the end of the 512KB of flash */ - storage_partition: partition@7e000 { - label = "storage"; - reg = <0x0007e000 0x00002000>; - }; - - }; -}; - -&usart0 { - current-speed = <115200>; - pinctrl-0 = <&usart0_default>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32fg13p233f512gm48.yaml b/boards/silabs/efr32_radio/efr32_radio_efr32fg13p233f512gm48.yaml deleted file mode 100644 index af096e1af9e..00000000000 --- a/boards/silabs/efr32_radio/efr32_radio_efr32fg13p233f512gm48.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: efr32_radio/efr32fg13p233f512gm48 -name: BRD4255A -type: mcu -arch: arm -ram: 64 -flash: 512 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - counter - - gpio - - nvs - - spi - - uart - - watchdog -testing: - ignore_tags: - - net - - bluetooth -vendor: silabs diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32fg1p133f256gm48.dts b/boards/silabs/efr32_radio/efr32_radio_efr32fg1p133f256gm48.dts deleted file mode 100644 index 2167b1b69b7..00000000000 --- a/boards/silabs/efr32_radio/efr32_radio_efr32fg1p133f256gm48.dts +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (c) 2020 Piotr Mienkowski - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include -#include "efr32_radio.dtsi" - -/ { - model = "Silicon Labs BRD4250B (Flex Gecko Radio Board)"; - compatible = "silabs,efr32_radio_brd4250b", "silabs,efr32fg1p"; - - pwmleds { - compatible = "pwm-leds"; - status = "okay"; - pwm_led0: pwm_led0 { - pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; - }; - }; - - aliases { - pwm-led0 = &pwm_led0; - spi-flash0 = &mx25r80; - }; -}; - -&cpu0 { - clock-frequency = <38400000>; -}; - -&timer0 { - status = "okay"; - - pwm0: pwm { - status = "okay"; - pin-location = ; - prescaler = <1024>; - }; -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 32 kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x0 0x00008000>; - read-only; - }; - - /* Reserve 94 kB for the application in slot 0 */ - slot0_partition: partition@8000 { - label = "image-0"; - reg = <0x00008000 0x00017800>; - }; - - /* Reserve 94 kB for the application in slot 1 */ - slot1_partition: partition@1f800 { - label = "image-1"; - reg = <0x0001f800 0x00017800>; - }; - - /* Reserve 30 kB for the scratch partition */ - scratch_partition: partition@37000 { - label = "image-scratch"; - reg = <0x00037000 0x00007800>; - }; - - /* Set 6Kb of storage at the end of the 256Kb of flash */ - storage_partition: partition@3e800 { - label = "storage"; - reg = <0x0003e800 0x00001800>; - }; - - }; -}; - -&usart0 { - current-speed = <115200>; - pinctrl-0 = <&usart0_default>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32fg1p133f256gm48.yaml b/boards/silabs/efr32_radio/efr32_radio_efr32fg1p133f256gm48.yaml deleted file mode 100644 index 356d959514c..00000000000 --- a/boards/silabs/efr32_radio/efr32_radio_efr32fg1p133f256gm48.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: efr32_radio/efr32fg1p133f256gm48 -name: BRD4250B -type: mcu -arch: arm -ram: 32 -flash: 256 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - counter - - gpio - - nvs - - spi - - uart - - watchdog -testing: - ignore_tags: - - net - - bluetooth -vendor: silabs diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32mg12p432f1024gl125.dts b/boards/silabs/efr32_radio/efr32_radio_efr32mg12p432f1024gl125.dts deleted file mode 100644 index 64b9dce560d..00000000000 --- a/boards/silabs/efr32_radio/efr32_radio_efr32mg12p432f1024gl125.dts +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (c) 2020 Piotr Mienkowski - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "efr32_radio.dtsi" - -/ { - model = "Silicon Labs BRD4161A (Mighty Gecko Radio Board)"; - compatible = "silabs,efr32_radio_brd4161a", "silabs,efr32mg12p"; - - aliases { - spi-flash0 = &mx25r80; - }; -}; - -&cpu0 { - clock-frequency = <38400000>; -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 32 kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x0 0x00008000>; - read-only; - }; - - /* Reserve 220 kB for the application in slot 0 */ - slot0_partition: partition@8000 { - label = "image-0"; - reg = <0x00008000 0x00037000>; - }; - - /* Reserve 220 kB for the application in slot 1 */ - slot1_partition: partition@3f000 { - label = "image-1"; - reg = <0x0003f000 0x00037000>; - }; - - /* Reserve 32 kB for the scratch partition */ - scratch_partition: partition@76000 { - label = "image-scratch"; - reg = <0x00076000 0x00008000>; - }; - - /* Set 8Kb of storage at the end of the 512KB of flash */ - storage_partition: partition@7e000 { - label = "storage"; - reg = <0x0007e000 0x00002000>; - }; - - }; -}; - -&pinctrl { - i2c0_default: i2c0_default { - group1 { - psels = , - , - , - ; - }; - }; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; - status = "okay"; - - si7021: si7021@40 { - compatible = "silabs,si7006"; - reg = <0x40>; - status = "okay"; - }; -}; diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32mg12p432f1024gl125.yaml b/boards/silabs/efr32_radio/efr32_radio_efr32mg12p432f1024gl125.yaml deleted file mode 100644 index 8092040c672..00000000000 --- a/boards/silabs/efr32_radio/efr32_radio_efr32mg12p432f1024gl125.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: efr32_radio/efr32mg12p432f1024gl125 -name: BRD4161A -type: mcu -arch: arm -ram: 256 -flash: 1024 -toolchain: - - zephyr - - gnuarmemb -supported: - - counter - - gpio - - nvs - - spi - - uart - - watchdog -testing: - ignore_tags: - - net - - bluetooth -vendor: silabs diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32mg12p433f1024gm68.dts b/boards/silabs/efr32_radio/efr32_radio_efr32mg12p433f1024gm68.dts deleted file mode 100644 index effd66a8515..00000000000 --- a/boards/silabs/efr32_radio/efr32_radio_efr32mg12p433f1024gm68.dts +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2020 Piotr Mienkowski - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "efr32_radio.dtsi" - -/ { - model = "Silicon Labs BRD4170A (Mighty Gecko Radio Board)"; - compatible = "silabs,efr32_radio_brd4170a", "silabs,efr32mg12p"; - - aliases { - spi-flash0 = &mx25r80; - }; -}; - -&cpu0 { - clock-frequency = <38400000>; -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 32 kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x0 0x00008000>; - read-only; - }; - - /* Reserve 220 kB for the application in slot 0 */ - slot0_partition: partition@8000 { - label = "image-0"; - reg = <0x00008000 0x00037000>; - }; - - /* Reserve 220 kB for the application in slot 1 */ - slot1_partition: partition@3f000 { - label = "image-1"; - reg = <0x0003f000 0x00037000>; - }; - - /* Reserve 32 kB for the scratch partition */ - scratch_partition: partition@76000 { - label = "image-scratch"; - reg = <0x00076000 0x00008000>; - }; - - /* Set 8Kb of storage at the end of the 512KB of flash */ - storage_partition: partition@7e000 { - label = "storage"; - reg = <0x0007e000 0x00002000>; - }; - - }; -}; diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32mg12p433f1024gm68.yaml b/boards/silabs/efr32_radio/efr32_radio_efr32mg12p433f1024gm68.yaml deleted file mode 100644 index ac0779d0d01..00000000000 --- a/boards/silabs/efr32_radio/efr32_radio_efr32mg12p433f1024gm68.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: efr32_radio/efr32mg12p433f1024gm68 -name: BRD4170A -type: mcu -arch: arm -ram: 256 -flash: 1024 -toolchain: - - zephyr - - gnuarmemb -supported: - - counter - - gpio - - nvs - - spi - - uart - - watchdog -testing: - ignore_tags: - - net - - bluetooth -vendor: silabs diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32.dts b/boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32.dts deleted file mode 100644 index 379fd031e22..00000000000 --- a/boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32.dts +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright (c) 2020 TriaGnoSys GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include -#include "efr32_radio_efr32mg21a020f1024im32-pinctrl.dtsi" - -/ { - model = "Silicon Labs BRD4180A (Mighty Gecko Radio Board)"; - compatible = "silabs,efr32mg21_brd4180a", "silabs,efr32mg21"; - - chosen { - zephyr,console = &usart0; - zephyr,shell-uart = &usart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0; - led1 = &led1; - sw0 = &button0; - sw1 = &button1; - watchdog0 = &wdog0; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpiob 0 0>; - label = "LED 0"; - }; - led1: led_1 { - gpios = <&gpiob 1 0>; - label = "LED 1"; - }; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - /* gpio flags need validation */ - gpios = <&gpiod 2 GPIO_ACTIVE_LOW>; - label = "User Push Button 0"; - zephyr,code = ; - }; - button1: button_1 { - /* gpio flags need validation */ - gpios = <&gpiod 3 GPIO_ACTIVE_LOW>; - label = "User Push Button 1"; - zephyr,code = ; - }; - }; - -}; - -&cpu0 { - clock-frequency = <38400000>; -}; - -&usart0 { - current-speed = <115200>; - pinctrl-0 = <&usart0_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&rtcc0 { - prescaler = <1>; - status = "okay"; -}; - -&gpio { - status = "okay"; -}; - -&gpioa { - status = "okay"; -}; - -&gpiob { - status = "okay"; -}; - -&gpioc { - status = "okay"; -}; - -&gpiod { - status = "okay"; - - board-controller-enable { - gpio-hog; - gpios = <4 GPIO_ACTIVE_HIGH>; - output-high; - }; -}; - -&wdog0 { - status = "okay"; -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 48 kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x0 0x0000c000>; - read-only; - }; - - /* Reserve 464 kB for the application in slot 0 */ - slot0_partition: partition@c000 { - label = "image-0"; - reg = <0x0000c000 0x00074000>; - }; - - /* Reserve 464 kB for the application in slot 1 */ - slot1_partition: partition@80000 { - label = "image-1"; - reg = <0x00080000 0x00074000>; - }; - - /* Reserve 32 kB for the scratch partition */ - scratch_partition: partition@f4000 { - label = "image-scratch"; - reg = <0x000f4000 0x00008000>; - }; - - /* Set 16Kb of storage at the end of the 1024Kb of flash */ - storage_partition: partition@fc000 { - label = "storage"; - reg = <0x000fc000 0x00004000>; - }; - - }; -}; diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32.yaml b/boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32.yaml deleted file mode 100644 index c6103f5336b..00000000000 --- a/boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: efr32_radio/efr32mg21a020f1024im32 -name: BRD4180A -type: mcu -arch: arm -ram: 96 -flash: 1024 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - counter - - gpio - - nvs - - uart - - watchdog -testing: - ignore_tags: - - net - - bluetooth -vendor: silabs diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48.dts b/boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48.dts deleted file mode 100644 index 0fb0b4becc3..00000000000 --- a/boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48.dts +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright (c) 2023 Fr. Sauter AG - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include -#include "efr32_radio_efr32mg24b220f1536im48-pinctrl.dtsi" - -/ { - model = "Silicon Labs BRD4187C (Mighty Gecko Radio Board)"; - compatible = "silabs,efr32mg24_brd4187c", "silabs,efr32mg24"; - - chosen { - zephyr,console = &usart0; - zephyr,shell-uart = &usart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0; - led1 = &led1; - sw0 = &button0; - sw1 = &button1; - watchdog0 = &wdog0; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpiob GECKO_PIN(2) GPIO_ACTIVE_HIGH>; - label = "LED 0"; - }; - led1: led_1 { - gpios = <&gpiob GECKO_PIN(4) GPIO_ACTIVE_HIGH>; - label = "LED 1"; - }; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - gpios = <&gpiob GECKO_PIN(1) GPIO_ACTIVE_LOW>; - label = "User Push Button 0"; - zephyr,code = ; - }; - button1: button_1 { - gpios = <&gpiob GECKO_PIN(3) GPIO_ACTIVE_LOW>; - label = "User Push Button 1"; - zephyr,code = ; - }; - }; - -}; - -&cpu0 { - clock-frequency = <39000000>; -}; - -&pstate_em3 { - status = "disabled"; -}; - -&usart0 { - current-speed = <115200>; - pinctrl-0 = <&usart0_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&gpio { - location-swo = <0>; - status = "okay"; -}; - -&gpioa { - status = "okay"; -}; - -&gpiob { - status = "okay"; - - board-controller-enable { - gpio-hog; - gpios = <0 GPIO_ACTIVE_HIGH>; - output-high; - }; -}; - -&gpioc { - status = "okay"; -}; - -&gpiod { - status = "okay"; -}; - -&wdog0 { - status = "okay"; -}; - -&burtc0 { - status = "okay"; -}; - -&stimer0 { - status = "okay"; -}; - -&se { - status = "okay"; -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 48 kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x0 DT_SIZE_K(48)>; - read-only; - }; - - /* Reserve 720 kB for the application in slot 0 */ - slot0_partition: partition@c000 { - label = "image-0"; - reg = <0x0000c000 0x000B4000>; - }; - - /* Reserve 720 kB for the application in slot 1 */ - slot1_partition: partition@C0000 { - label = "image-1"; - reg = <0x000C0000 0x000B4000>; - }; - - /* Reserve 32 kB for the scratch partition */ - scratch_partition: partition@174000 { - label = "image-scratch"; - reg = <0x00174000 DT_SIZE_K(32)>; - }; - - /* Set 16 kB of storage at the end of the 1536 kB of flash */ - storage_partition: partition@17c000 { - label = "storage"; - reg = <0x0017c000 DT_SIZE_K(16)>; - }; - }; -}; diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48.yaml b/boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48.yaml deleted file mode 100644 index 278f40a4866..00000000000 --- a/boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: efr32_radio/efr32mg24b220f1536im48 -name: BRD4187C -type: mcu -arch: arm -ram: 256 -flash: 1536 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - gpio - - uart - - watchdog -testing: - ignore_tags: - - net - - bluetooth - - pm - - hwinfo -vendor: silabs diff --git a/boards/silabs/efr32_thunderboard/Kconfig b/boards/silabs/efr32_thunderboard/Kconfig deleted file mode 100644 index f9cfc8b4499..00000000000 --- a/boards/silabs/efr32_thunderboard/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ -# EFR32 Thunderboard-style boards - -# Copyright (c) 2022, Silicon Labs -# SPDX-License-Identifier: Apache-2.0 - -module = BOARD_THUNDERBOARD -module-str = Board Control -source "subsys/logging/Kconfig.template.log_config" diff --git a/boards/silabs/efr32_thunderboard/Kconfig.defconfig b/boards/silabs/efr32_thunderboard/Kconfig.defconfig deleted file mode 100644 index e1c23189e31..00000000000 --- a/boards/silabs/efr32_thunderboard/Kconfig.defconfig +++ /dev/null @@ -1,37 +0,0 @@ -# Thunderboard-style boards - -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config CMU_HFXO_FREQ - default 38400000 - -config CMU_LFXO_FREQ - default 32768 - -if SOC_GECKO_USE_RAIL - -config FPU - default y - -endif # SOC_GECKO_USE_RAIL - -if BT - -config FPU - default y - -config COMMON_LIBC_MALLOC_ARENA_SIZE - default 8192 - -config MAIN_STACK_SIZE - default 3072 if PM - default 2304 - -config BT_SILABS_HCI - default y - -endif # BT - -config REGULATOR - default y if SI7210 diff --git a/boards/silabs/efr32_thunderboard/Kconfig.efr32bg22_brd4184a b/boards/silabs/efr32_thunderboard/Kconfig.efr32bg22_brd4184a deleted file mode 100644 index 2cbcd439761..00000000000 --- a/boards/silabs/efr32_thunderboard/Kconfig.efr32bg22_brd4184a +++ /dev/null @@ -1,7 +0,0 @@ -# EFR32BG SLTB010A board - -# Copyright (c) 2021, Sateesh Kotapati -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFR32BG22_BRD4184A - select SOC_PART_NUMBER_EFR32BG22C224F512IM40 diff --git a/boards/silabs/efr32_thunderboard/Kconfig.efr32bg22_brd4184b b/boards/silabs/efr32_thunderboard/Kconfig.efr32bg22_brd4184b deleted file mode 100644 index 48a8915cf5a..00000000000 --- a/boards/silabs/efr32_thunderboard/Kconfig.efr32bg22_brd4184b +++ /dev/null @@ -1,7 +0,0 @@ -# EFR32BG SLTB010A board - -# Copyright (c) 2021, Sateesh Kotapati -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFR32BG22_BRD4184B - select SOC_PART_NUMBER_EFR32BG22C224F512IM40 diff --git a/boards/silabs/efr32_thunderboard/Kconfig.efr32bg27_brd2602a b/boards/silabs/efr32_thunderboard/Kconfig.efr32bg27_brd2602a deleted file mode 100644 index 7bf2e70d455..00000000000 --- a/boards/silabs/efr32_thunderboard/Kconfig.efr32bg27_brd2602a +++ /dev/null @@ -1,7 +0,0 @@ -# EFR32BG SLTB010A board - -# Copyright (c) 2021, Sateesh Kotapati -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFR32BG27_BRD2602A - select SOC_PART_NUMBER_EFR32BG27C140F768IM40 diff --git a/boards/silabs/efr32_thunderboard/board.c b/boards/silabs/efr32_thunderboard/board.c deleted file mode 100644 index 508d0ee6837..00000000000 --- a/boards/silabs/efr32_thunderboard/board.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2021 Sateesh Kotapati - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -#ifdef CONFIG_SOC_GECKO_DEV_INIT -#include "em_cmu.h" -#endif - - -LOG_MODULE_REGISTER(thunderboard, CONFIG_BOARD_THUNDERBOARD_LOG_LEVEL); - -static int thunderboard_init_clocks(void); - -static int thunderboard_init(void) -{ - int ret; - -#ifdef CONFIG_SOC_GECKO_DEV_INIT - thunderboard_init_clocks(); -#endif - static struct gpio_dt_spec wake_up_gpio_dev = - GPIO_DT_SPEC_GET(DT_NODELABEL(wake_up_trigger), gpios); - - - if (!gpio_is_ready_dt(&wake_up_gpio_dev)) { - LOG_ERR("Wake-up GPIO device was not found!\n"); - return -ENODEV; - } - ret = gpio_pin_configure_dt(&wake_up_gpio_dev, GPIO_OUTPUT_ACTIVE); - if (ret < 0) - return ret; - - return 0; -} - -#ifdef CONFIG_SOC_GECKO_DEV_INIT -static int thunderboard_init_clocks(void) -{ - CMU_ClockSelectSet(cmuClock_SYSCLK, cmuSelect_HFRCODPLL); -#if defined(_CMU_EM01GRPACLKCTRL_MASK) - CMU_ClockSelectSet(cmuClock_EM01GRPACLK, cmuSelect_HFRCODPLL); -#endif -#if defined(_CMU_EM01GRPBCLKCTRL_MASK) - CMU_ClockSelectSet(cmuClock_EM01GRPBCLK, cmuSelect_HFRCODPLL); -#endif - CMU_ClockSelectSet(cmuClock_EM23GRPACLK, cmuSelect_LFRCO); -#if defined(RTCC_PRESENT) - CMU_ClockSelectSet(cmuClock_RTCC, cmuSelect_LFRCO); -#endif - CMU_ClockSelectSet(cmuClock_WDOG0, cmuSelect_LFRCO); - - return 0; -} -#endif - -/* needs to be done after GPIO driver init */ -SYS_INIT(thunderboard_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); diff --git a/boards/silabs/efr32_thunderboard/board.cmake b/boards/silabs/efr32_thunderboard/board.cmake deleted file mode 100644 index d27a7983eb1..00000000000 --- a/boards/silabs/efr32_thunderboard/board.cmake +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_BOARD_EFR32BG22_BRD4184A OR CONFIG_BOARD_EFR32BG22_BRD4184B) - board_runner_args(jlink "--device=EFR32BG22C224F512IM40" "--reset-after-load") - include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -elseif(CONFIG_BOARD_EFR32BG27_BRD2602A) - board_runner_args(silabs_commander "--device=EFR32BG27C140F768IM40") - include(${ZEPHYR_BASE}/boards/common/silabs_commander.board.cmake) -endif() diff --git a/boards/silabs/efr32_thunderboard/board.yml b/boards/silabs/efr32_thunderboard/board.yml deleted file mode 100644 index ebfe25a104c..00000000000 --- a/boards/silabs/efr32_thunderboard/board.yml +++ /dev/null @@ -1,13 +0,0 @@ -boards: - - name: efr32bg22_brd4184a - vendor: silabs - socs: - - name: efr32bg22c224f512im40 - - name: efr32bg22_brd4184b - vendor: silabs - socs: - - name: efr32bg22c224f512im40 - - name: efr32bg27_brd2602a - vendor: silabs - socs: - - name: efr32bg27c140f768im40 diff --git a/boards/silabs/efr32_thunderboard/doc/brd2602.rst b/boards/silabs/efr32_thunderboard/doc/brd2602.rst deleted file mode 100644 index a9569d66518..00000000000 --- a/boards/silabs/efr32_thunderboard/doc/brd2602.rst +++ /dev/null @@ -1,129 +0,0 @@ -.. _efr32BG27_brd2602: - -SiLabs EFR32BG27-BRD2602(A) (EFR32BG27 +8 dBm Dev Kit Board) -############################################################ - -BRD2602 is a board based on EFR32BG27 SoC and is one of -:ref:`efr32_thunderboard`. - -Hardware -******** - -- EFR32BG27 Blue Gecko Wireless SoC with up to 76.8 MHz operating frequency -- ARM® Cortex® M33 core with 64 kB RAM and 768 kB Flash -- Macronix ultra low power 8-Mbit SPI flash (MX25R8035F) -- 2.4 GHz ceramic antenna for wireless transmission -- Silicon Labs Si7021 relative humidity and temperature sensor -- Vishay VEML6035 low power, high sensitivity ambient light Sensor -- Silicon Labs Si7210 hall effect sensor -- TDK InvenSense ICM-20689 6-axis inertial sensor -- Pair of PDM microphones -- One LED and one push button -- Power enable signals and isolation switches for ultra low power operation -- On-board SEGGER J-Link debugger for easy programming and debugging, which - includes a USB virtual COM port and Packet Trace Interface (PTI) -- Mini Simplicity connector for access to energy profiling and advanced wireless - network debugging -- Breakout pads for GPIO access and connection to external hardware -- Reset button -- CR2032 coin cell holder and external battery connector - -Supported Features -================== - -The efr32bg27_brd2602 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ - -Flashing -======== - -The EFR32BG27-BRD2602A includes an embedded `J-Link`_ adapter built around -EFM32GG12 microcontroller (not user-programmable). -The adapter provides: - -- SWD interface to EFR32BG27 for flashing and debugging. -- SWO trace interface to EFR32BG27 for tracing. -- UART interface to EFR32BG27 for console access. -- A USB connection to the host computer, which exposes CDC-ACM Serial Port - endpoints for access to the console UART interface and proprietary J-Link - endpoints for access to the SWD and SWO interfaces. - -UART functionality of the adapter is accessible via standard CDC-ACM USB driver -present in most desktop operating systems and any standard serial port terminal -program e.g. `picocom`_. - -SWD and SWO functionality is accessible via `Simplicity Commander`_. - -The simplest way to flash the board is by using West, which runs Simplicity -Commander in unattended mode and passes all the necessary arguments to it. - -- If Simplicity Commander is installed in the system and the directory in - which `commander` executable is located is present in the `PATH` environment - variable: - - .. code-block:: console - - west flash - -- Otherwise, one should specify full path to the `commander` executable: - - .. code-block:: console - - west flash --commander /commander - -- In case several J-Link adapters are connected, you must specify serial number - of the adapter which should be used for flashing: - - .. code-block:: console - - west flash --dev-id - -Programming and Debugging -========================= - -The sample application :ref:`hello_world` is used for this example. -Build the Zephyr kernel and application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efr32bg27_brd2602a - :goals: build - -Connect your device to your host computer using the USB port and you -should see a USB connection. Use `west`'s flash command - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you should be able to see on the corresponding Serial Port -the following message: - -.. code-block:: console - - Hello World! efr32bg27_brd2602a - -.. _picocom: - https://github.com/npat-efault/picocom - -.. _J-Link: - https://www.segger.com/jlink-debug-probes.html - -.. _Simplicity Commander: - https://www.silabs.com/developers/mcu-programming-options diff --git a/boards/silabs/efr32_thunderboard/doc/brd4184.rst b/boards/silabs/efr32_thunderboard/doc/brd4184.rst deleted file mode 100644 index a6f1c281d3c..00000000000 --- a/boards/silabs/efr32_thunderboard/doc/brd4184.rst +++ /dev/null @@ -1,230 +0,0 @@ -.. _efr32bg22_brd4184: - -SiLabs EFR32BG22-BRD4184(A/B) (Thunderboard EFR32BG22) -###################################################### - -BRD4184 is a board based on EFR32BG22 SoC and is one of -:ref:`efr32_thunderboard`. It comes in two revisions, which differ from each -other slightly: BRD4184A and BRD4184B. - -.. image:: ./efr32bg_sltb010a.jpg - :align: center - :alt: EFR32BG-SLTB010A - -Hardware -******** - -- EFR32BG22 Blue Gecko Wireless SoC with upto 76.8 MHz operating frequency -- ARM® Cortex® M33 core with 32 kB RAM and 512 kB Flash -- Macronix ultra low power 8-Mbit SPI flash (MX25R8035F) -- 2.4 GHz ceramic antenna for wireless transmission -- Silicon Labs Si7021 relative humidity and temperature sensor -- Silicon Labs Si1133 UV index and ambient light sensor (EFR32BG22-BRD4184A) -- Vishay VEML6035 ambient light sensor (EFR32BG22-BRD4184B) -- Silicon Labs Si7210 hall effect sensor -- TDK InvenSense ICM-20648 6-axis inertial sensor -- Two Knowles SPK0641HT4H-1 MEMS microphones with PDM output (EFR32BG22-BRD4184B) -- One LED and one push button -- Power enable signals and isolation switches for ultra low power operation -- On-board SEGGER J-Link debugger for easy programming and debugging, which - includes a USB virtual COM port and Packet Trace Interface (PTI) -- Mini Simplicity connector for access to energy profiling and advanced wireless - network debugging -- Breakout pads for GPIO access and connection to external hardware -- Reset button -- Automatic switch-over between USB and battery power -- CR2032 coin cell holder and external battery connector - -For more information about the EFR32BG SoC and Thunderboard EFR32BG22 board: - -- `EFR32BG22 Website`_ -- `EFR32BG22 Datasheet`_ -- `EFR32xG22 Reference Manual`_ -- `Thunderboard EFR32BG22 Website`_ -- `EFR32BG22-BRD4184A User Guide`_ -- `EFR32BG22-BRD4184B User Guide`_ -- `EFR32BG22-BRD4184A Schematics`_ -- `EFR32BG22-BRD4184B Schematics`_ - -Supported Features -================== - -The efr32bg22_brd4184a/b board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | stimer | -+-----------+------------+-------------------------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | true random number generator | -+-----------+------------+-------------------------------------+ -| I2C(M/S) | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| RADIO | on-chip | bluetooth | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in -:zephyr_file:`boards/silabs/efr32_thunderboard/efr32bg22_brd4184a_defconfig` -and -:zephyr_file:`boards/silabs/efr32_thunderboard/efr32bg22_brd4184b_defconfig` - -Connections and IOs -=================== - -The EFR32BG SoC has six gpio controllers (PORTA, PORTB, PORTC, PORTD, -PORTE and PORTF). - -In the following tables, the column Name contains Pin names. For example, PE2 -means Pin number 2 on PORTE and #27 represents the location bitfield, as used -in the board's and microcontroller's datasheets and manuals. - -There are two variants of this board, "A" and "B". Please take a look at your PCB, -to determine which one you have, as the GPIO pin bindings vary between those two. - -BRD4184A: - -+------+-------------+-----------------------------------+ -| Name | Function | Usage | -+======+=============+===================================+ -| PB0 | GPIO | LED0 (YELLOW) | -+------+-------------+-----------------------------------+ -| PB1 | GPIO | SW0 Push Button PB0 | -+------+-------------+-----------------------------------+ -| PA5 | UART_TX | UART TX Console VCOM_TX US1_TX #1 | -+------+-------------+-----------------------------------+ -| PA6 | UART_RX | UART RX Console VCOM_RX US1_RX #1 | -+------+-------------+-----------------------------------+ - -BRD4184B: - -+------+-------------+-----------------------------------+ -| Name | Function | Usage | -+======+=============+===================================+ -| PA4 | GPIO | LED0 (YELLOW) | -+------+-------------+-----------------------------------+ -| PB3 | GPIO | SW0 Push Button PB0 | -+------+-------------+-----------------------------------+ -| PA5 | UART_TX | UART TX Console VCOM_TX US1_TX #1 | -+------+-------------+-----------------------------------+ -| PA6 | UART_RX | UART RX Console VCOM_RX US1_RX #1 | -+------+-------------+-----------------------------------+ - -System Clock -============ - -The EFR32BG SoC is configured to use the 38.4 MHz external oscillator on the -board. - -Programming and Debugging -========================= - -Flashing an application ------------------------ - -Connect your device to your host computer using the USB port. -The sample application :ref:`hello_world` is used for this example. -Build the Zephyr kernel and application, then flash it to the device: - -BRD4184A: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efr32bg22_brd4184a - :goals: flash - -BRD4184B: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efr32bg22_brd4184b - :goals: flash - -.. note:: - `west flash` requires `SEGGER J-Link software`_ to be installed on you host - computer. - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you should be able to see on the corresponding Serial Port -the following message: - -.. code-block:: console - - Hello World! efr32bg22_brd4184 - -Bluetooth -========= - -To use the BLE function, run the command below to retrieve necessary binary -blobs from the SiLabs HAL repository. - -.. code-block:: console - - west blobs fetch silabs - -Then build the Zephyr kernel and a Bluetooth sample with the following -command. The :ref:`bluetooth-observer-sample` sample application is used in -this example. - -BRD4184A: - -.. zephyr-app-commands:: - :zephyr-app: samples/bluetooth/observer - :board: efr32bg22_brd4184a - :goals: build - -BRD4184B: - -.. zephyr-app-commands:: - :zephyr-app: samples/bluetooth/observer - :board: efr32bg22_brd4184b - :goals: build - - -.. _Thunderboard EFR32BG22 Website: - https://www.silabs.com/development-tools/thunderboard/thunderboard-bg22-kit - -.. _EFR32BG22-BRD4184A User Guide: - https://www.silabs.com/documents/public/user-guides/ug415-sltb010a-user-guide.pdf - -.. _EFR32BG22-BRD4184B User Guide: - https://www.silabs.com/documents/public/user-guides/ug464-brd4184b-user-guide.pdf - -.. _EFR32BG22-BRD4184A Schematics: - https://www.silabs.com/documents/public/schematic-files/BRD4184A-A01-schematic.pdf - -.. _EFR32BG22-BRD4184B Schematics: - https://www.silabs.com/documents/public/schematic-files/BRD4184B-A02-schematic.pdf - -.. _EFR32BG22 Website: - https://www.silabs.com/wireless/bluetooth/efr32bg22-series-2-socs - -.. _EFR32BG22 Datasheet: - https://www.silabs.com/documents/public/data-sheets/efr32bg22-datasheet.pdf - -.. _EFR32xG22 Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/efr32xg22-rm.pdf - -.. _SEGGER J-Link software: - https://www.segger.com/downloads/jlink diff --git a/boards/silabs/efr32_thunderboard/doc/index.rst b/boards/silabs/efr32_thunderboard/doc/index.rst deleted file mode 100644 index ca9bbcf99bd..00000000000 --- a/boards/silabs/efr32_thunderboard/doc/index.rst +++ /dev/null @@ -1,68 +0,0 @@ -.. _efr32_thunderboard: - -EFR32 Thunderboard-style boards -############################### - -Overview -******** - -There are a couple of very similar boards, which we categorize as -"Thunderboard-style boards". The name can be seen on some of Silicon Labs products -that use boards of this style, such as EFR32™ Blue Gecko Starter Kit, -a.k.a Thunderboard EFR32BG22. - -Those boards contains an MCU from the EFR32BG family built on ARM® Cortex®-M33F -processor with low power capabilities. - -For an example of such board, refer to the following site: - -- `Thunderboard EFR32BG22 Website`_ - -Currently the following devices are considered "Thunderboard-style": - -.. toctree:: - :maxdepth: 1 - - brd4184.rst - brd2602.rst - -Serial Port -=========== - -The SoCs used on these boards have two USARTs. -USART1 is connected to the board controller and is used for the console. - -Programming and Debugging -************************* - -.. note:: - Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ - -Flashing -======== - -The Thunderboard boards include `J-Link`_ serial and debug adapters built into the -board. The adapter provides: - -- A USB connection to a host computer running `J-Link software`_ or `Silicon Labs - Simplicity Commander`_. -- A physical UART connection which is relayed over a USB Serial port interface. - -For detailed instructions regarding flashing, refer to documentation of a specific -device. - -.. _Thunderboard EFR32BG22 Website: - https://www.silabs.com/development-tools/thunderboard/thunderboard-bg22-kit - -.. _J-Link: - https://www.segger.com/jlink-debug-probes.html - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink - -.. _J-Link software: - https://www.segger.com/downloads/jlink - -.. _Silicon Labs Simplicity Commander: - https://www.silabs.com/developers/mcu-programming-options diff --git a/boards/silabs/efr32_thunderboard/efr32bg22_brd4184.dtsi b/boards/silabs/efr32_thunderboard/efr32bg22_brd4184.dtsi deleted file mode 100644 index 7badab45158..00000000000 --- a/boards/silabs/efr32_thunderboard/efr32bg22_brd4184.dtsi +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2021 Sateesh Kotapati - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "thunderboard.dtsi" - -/ { - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0; - sw0 = &button0; - spi-flash0 = &mx25r80; - spi0 = &usart0; - watchdog0 = &wdog0; - /* If enabled, MCUboot uses this for recovery mode entrance */ - mcuboot-led0 = &led0; - mcuboot-button0 = &button0; - }; - - chosen { - zephyr,code-partition = &slot0_partition; - }; -}; - -&flash0 { - partitions { - /* Reserve 48 KiB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000c000>; - read-only; - }; - - /* Reserve 224 KiB for the application in slot 0 */ - slot0_partition: partition@c000 { - label = "image-0"; - reg = <0x0000c000 0x00038000>; - }; - - /* Reserve 224 KiB for the application in slot 1 */ - slot1_partition: partition@44000 { - label = "image-1"; - reg = <0x00044000 0x00038000>; - }; - - /* Set 16 KiB of storage at the end of the 512 KiB of flash */ - storage_partition: partition@7c000 { - label = "storage"; - reg = <0x0007c000 0x00004000>; - }; - }; -}; - -&sw_imu_enable { - enable-gpios = <&gpiob GECKO_PIN(4) GPIO_ACTIVE_HIGH>; -}; diff --git a/boards/silabs/efr32_thunderboard/efr32bg22_brd4184a.dts b/boards/silabs/efr32_thunderboard/efr32bg22_brd4184a.dts deleted file mode 100644 index 48a59978911..00000000000 --- a/boards/silabs/efr32_thunderboard/efr32bg22_brd4184a.dts +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (c) 2021 Sateesh Kotapati - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include -#include "efr32bg22_brd4184.dtsi" - -/ { - model = "Silicon Labs EFR32BG BRD4184A (aka Thunderboard BG22)"; - compatible = "silabs,efr32bg22c224f512im40", "silabs,efr32bg_brd4184a", - "silabs,efr32bg22"; -}; - -&sw_sensor_enable { - enable-gpios = <&gpioa GECKO_PIN(4) GPIO_ACTIVE_HIGH>; -}; - -&sw_mic_enable { - enable-gpios = <&gpioa GECKO_PIN(0) GPIO_ACTIVE_HIGH>; -}; diff --git a/boards/silabs/efr32_thunderboard/efr32bg22_brd4184a.yaml b/boards/silabs/efr32_thunderboard/efr32bg22_brd4184a.yaml deleted file mode 100644 index 37bc5bed239..00000000000 --- a/boards/silabs/efr32_thunderboard/efr32bg22_brd4184a.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: efr32bg22_brd4184a -name: EFR32BG22-BRD4184A -type: mcu -arch: arm -ram: 32 -flash: 512 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - counter - - gpio - - uart - - i2c - - spi -testing: - ignore_tags: - - net - - bluetooth -vendor: silabs diff --git a/boards/silabs/efr32_thunderboard/efr32bg22_brd4184b.dts b/boards/silabs/efr32_thunderboard/efr32bg22_brd4184b.dts deleted file mode 100644 index 9dded5746bd..00000000000 --- a/boards/silabs/efr32_thunderboard/efr32bg22_brd4184b.dts +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2021 Sateesh Kotapati - * Copyright (c) 2023 Piotr Dymacz - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include -#include "efr32bg22_brd4184.dtsi" - -/ { - model = "Silicon Labs EFR32BG BRD4184B (aka Thunderboard BG22)"; - compatible = "silabs,efr32bg22c224f512im40", "silabs,efr32bg_brd4184b", - "silabs,efr32bg22"; -}; - -&button0 { - gpios = <&gpiob GECKO_PIN(3) GPIO_ACTIVE_LOW>; -}; - -&led0 { - gpios = <&gpioa GECKO_PIN(4) GPIO_ACTIVE_HIGH>; -}; - -&sw_sensor_enable { - enable-gpios = <&gpioc GECKO_PIN(6) GPIO_ACTIVE_HIGH>; -}; - -&sw_mic_enable { - enable-gpios = <&gpioc GECKO_PIN(7) GPIO_ACTIVE_HIGH>; -}; diff --git a/boards/silabs/efr32_thunderboard/efr32bg22_brd4184b.yaml b/boards/silabs/efr32_thunderboard/efr32bg22_brd4184b.yaml deleted file mode 100644 index 40c6377a277..00000000000 --- a/boards/silabs/efr32_thunderboard/efr32bg22_brd4184b.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: efr32bg22_brd4184b -name: EFR32BG22-BRD4184B -type: mcu -arch: arm -ram: 32 -flash: 512 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - counter - - gpio - - uart - - i2c - - spi -testing: - ignore_tags: - - net - - bluetooth -vendor: silabs diff --git a/boards/silabs/efr32_thunderboard/efr32bg27_brd2602a.dts b/boards/silabs/efr32_thunderboard/efr32bg27_brd2602a.dts deleted file mode 100644 index b267cd8356b..00000000000 --- a/boards/silabs/efr32_thunderboard/efr32bg27_brd2602a.dts +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright (c) 2023 Antmicro - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include -#include "thunderboard.dtsi" - -/ { - model = "Silicon Labs EFR32BG27C140F768IM40 Thunderboard-style board"; - compatible = "silabs,efr32bg27c140f768im40", "silabs,efr32bg27_brd2602a", - "silabs,efr32bg27"; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0; - sw0 = &button0; - spi-flash0 = &mx25r80; - spi0 = &usart0; - watchdog0 = &wdog0; - /* If enabled, MCUboot uses this for recovery mode entrance */ - mcuboot-led0 = &led0; - mcuboot-button0 = &button0; - }; - - chosen { - zephyr,code-partition = &slot0_partition; - }; -}; - -&flash0 { - partitions { - /* Reserve 48 KiB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000c000>; - read-only; - }; - - /* Reserve 328 KiB for the application in slot 0 */ - slot0_partition: partition@c000 { - label = "image-0"; - reg = <0x0000c000 0x00052000>; - }; - - /* Reserve 328 KiB for the application in slot 1 */ - slot1_partition: partition@5e000 { - label = "image-1"; - reg = <0x0005e000 0x00052000>; - }; - - /* Set 64 KiB of storage at the end of the 768 KiB of flash */ - storage_partition: partition@b0000 { - label = "storage"; - reg = <0x000b0000 0x00010000>; - }; - }; -}; - -&led0 { - gpios = <&gpioa GECKO_PIN(4) GPIO_ACTIVE_HIGH>; -}; - -&sw_sensor_enable { - enable-gpios = <&gpioc GECKO_PIN(6) GPIO_ACTIVE_HIGH>; -}; - - -&sw_mic_enable { - enable-gpios = <&gpioc GECKO_PIN(7) GPIO_ACTIVE_HIGH>; -}; - - -&sw_imu_enable { - enable-gpios = <&gpiob GECKO_PIN(4) GPIO_ACTIVE_HIGH>; -}; - -&button0 { - gpios = <&gpiob GECKO_PIN(3) GPIO_ACTIVE_LOW>; -}; diff --git a/boards/silabs/efr32_thunderboard/efr32bg27_brd2602a.yaml b/boards/silabs/efr32_thunderboard/efr32bg27_brd2602a.yaml deleted file mode 100644 index 844a48854d5..00000000000 --- a/boards/silabs/efr32_thunderboard/efr32bg27_brd2602a.yaml +++ /dev/null @@ -1,19 +0,0 @@ -identifier: efr32bg27_brd2602a -name: EFR32BG27_BRD2602A -type: mcu -arch: arm -ram: 64 -flash: 768 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - counter - - gpio - - uart -testing: - ignore_tags: - - net - - bluetooth -vendor: silabs diff --git a/boards/silabs/efr32_thunderboard/efr32bg27_brd2602a_defconfig b/boards/silabs/efr32_thunderboard/efr32bg27_brd2602a_defconfig deleted file mode 100644 index 50a14221ec9..00000000000 --- a/boards/silabs/efr32_thunderboard/efr32bg27_brd2602a_defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_ARM_MPU=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_SOC_GECKO_EMU_DCDC=y -CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y - -# Used if SysTick is enabled, ignored for BURTC -# (BURTC uses TIMER_READS_ITS_FREQUENCY_AT_RUNTIME) -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=76800000 - -# Use BURTC as system clock source -CONFIG_GECKO_BURTC_TIMER=y -CONFIG_CMU_BURTCCLK_LFXO=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=1024 diff --git a/boards/silabs/efr32mg_sltb004a/Kconfig.defconfig b/boards/silabs/efr32mg_sltb004a/Kconfig.defconfig deleted file mode 100644 index 5dd6c6417a7..00000000000 --- a/boards/silabs/efr32mg_sltb004a/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# EFR32MG SLTB004A board - -# Copyright (c) 2018, Diego Sueiro -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EFR32MG_SLTB004A - -config CMU_HFXO_FREQ - default 40000000 - -config CMU_LFXO_FREQ - default 32768 - -endif # BOARD_EFR32MG_SLTB004A diff --git a/boards/silabs/efr32mg_sltb004a/Kconfig.efr32mg_sltb004a b/boards/silabs/efr32mg_sltb004a/Kconfig.efr32mg_sltb004a deleted file mode 100644 index 3f2245d372e..00000000000 --- a/boards/silabs/efr32mg_sltb004a/Kconfig.efr32mg_sltb004a +++ /dev/null @@ -1,7 +0,0 @@ -# EFR32MG SLTB004A board - -# Copyright (c) 2018, Diego Sueiro -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFR32MG_SLTB004A - select SOC_PART_NUMBER_EFR32MG12P332F1024GL125 diff --git a/boards/silabs/efr32mg_sltb004a/board.yml b/boards/silabs/efr32mg_sltb004a/board.yml deleted file mode 100644 index cef6207cf03..00000000000 --- a/boards/silabs/efr32mg_sltb004a/board.yml +++ /dev/null @@ -1,5 +0,0 @@ -board: - name: efr32mg_sltb004a - vendor: silabs - socs: - - name: efr32mg12p332f1024gl125 diff --git a/boards/silabs/efr32mg_sltb004a/doc/index.rst b/boards/silabs/efr32mg_sltb004a/doc/index.rst deleted file mode 100644 index ae06df99fc5..00000000000 --- a/boards/silabs/efr32mg_sltb004a/doc/index.rst +++ /dev/null @@ -1,220 +0,0 @@ -.. _efr32mg_sltb004a: - -EFR32MG-SLTB004A -################ - -Overview -******** - -The EFR32™ Mighty Gecko Starter Kit EFR32MG-SLTB004A (a.k.a Thunderboard -Sense 2) contains a MCU from the EFR32MG family built on ARM® Cortex®-M4F -processor with low power capabilities. - -.. image:: efr32mg_sltb004a.jpg - :align: center - :alt: EFR32MG-SLTB004A - -Hardware -******** - -- EFR32MG12 Mighty Gecko Wireless SoC with 38.4 MHz operating frequency -- ARM® Cortex® M4 core with 256 kB RAM and 1024 kB Flash -- Macronix ultra low power 8-Mbit SPI flash (MX25R8035F) -- 2.4 GHz ceramic antenna for wireless transmission -- Silicon Labs Si7021 relative humidity and temperature sensor -- Silicon Labs Si1133 UV index and ambient light sensor -- Silicon Labs Si7210 hall effect sensor -- Bosch Sensortec BMP280 barometric pressure sensor -- ams CCS811 indoor air quality gas sensor -- TDK InvenSense ICM-20648 6-axis inertial sensor -- TDK InvenSense ICS-43434 MEMS microphone -- Four high brightness RGB LEDs from Broadcom Limited (ASMT-YTB7-0AA02) -- One bi-color LED and two push buttons -- Power enable signals for fine grained power-control -- On-board SEGGER J-Link debugger for easy programming and debugging, which - includes a USB virtual COM port -- Mini Simplicity connector for access to energy profiling and advanced wireless - network debugging -- Breakout pads for GPIO access and connection to external hardware -- Reset button -- Automatic switch-over between USB and battery power -- CR2032 coin cell holder and external battery connector - -For more information about the EFR32MG SoC and Thunderboard Sense 2 -(EFR32MG-SLTB004A) board: - -- `EFR32MG Website`_ -- `EFR32MG Datasheet`_ -- `EFR32MG Reference Manual`_ -- `EFR32MG-SLTB004A Website`_ -- `EFR32MG-SLTB004A User Guide`_ -- `EFR32MG-SLTB004A Schematics`_ - -Supported Features -================== - -The efr32mg_sltb004a board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtcc | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c port-polling | -+-----------+------------+-------------------------------------+ -| SPI(M) | on-chip | spi port-polling | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | true random number generator | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in -:zephyr_file:`boards/silabs/efr32mg_sltb004a/efr32mg_sltb004a_defconfig` - -Other hardware features are currently not supported by the port. - -Connections and IOs -=================== - -The EFR32MG SoC has eight gpio controllers (PORTA, PORTB, PORTC, PORTD, -PORTF, PORTI, PORTJ and PORTK). - -In the following table, the column Name contains Pin names. For example, PE2 -means Pin number 2 on PORTE and #27 represents the location bitfield , as used -in the board's and microcontroller's datasheets and manuals. - -+------+-------------+-----------------------------------+ -| Name | Function | Usage | -+======+=============+===================================+ -| PD8 | GPIO | LED0 (RED) | -+------+-------------+-----------------------------------+ -| PD9 | GPIO | LED1 (GREEN) | -+------+-------------+-----------------------------------+ -| PD14 | GPIO | SW0 Push Button PB0 | -+------+-------------+-----------------------------------+ -| PD15 | GPIO | Push Button PB1 | -+------+-------------+-----------------------------------+ -| PA0 | UART_TX | UART TX Console VCOM_TX US0_TX #0 | -+------+-------------+-----------------------------------+ -| PA1 | UART_RX | UART RX Console VCOM_RX US0_RX #0 | -+------+-------------+-----------------------------------+ -| PF3 | UART_TX | EXP12_UART_TX LEU0_TX #27 | -+------+-------------+-----------------------------------+ -| PF4 | UART_RX | EXP14_UART_RX LEU0_RX #27 | -+------+-------------+-----------------------------------+ -| PC10 | I2C_SDA | EXP16_I2C_SDA I2C0_SDA #15 | -+------+-------------+-----------------------------------+ -| PC11 | I2C_SCL | EXP15_I2C_SCL I2C0_SCL #15 | -+------+-------------+-----------------------------------+ -| PB6 | I2C_SDA | CCS811_I2C_SDA I2C1_SDA #6 | -+------+-------------+-----------------------------------+ -| PB7 | I2C_SCL | CCS811_I2C_SCL I2C1_SCL #6 | -+------+-------------+-----------------------------------+ -| PK0 | SPI_MOSI | Flash MOSI US2_TX #29 | -+------+-------------+-----------------------------------+ -| PK2 | SPI_MISO | Flash MISO US2_RX #30 | -+------+-------------+-----------------------------------+ -| PF7 | SPI_SCLK | Flash SCLK US2_CLK #18 | -+------+-------------+-----------------------------------+ -| PK1 | SPI_CS | Flash Chip Select (GPIO) | -+------+-------------+-----------------------------------+ - -System Clock -============ - -The EFR32MG SoC is configured to use the 38.4 MHz external oscillator on the -board. - -Serial Port -=========== - -The EFR32MG SoC has four USARTs and one Low Energy UARTs (LEUART with 9600 -maximum baudrate). USART0 is configured as the Zephyr console and is connected -to the On-Board J-Link Debugger that presents a virtual COM port for general -purpose application serial data transfer with this interface. - -Programming and Debugging -************************* - -.. note:: - Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ - -Flashing -======== - -The EFR32MG-SLTB004A includes an `J-Link`_ serial and debug adaptor built into the -board. The adaptor provides: - -- A USB connection to the host computer, which exposes a Mass Storage and a - USB Serial Port. -- A Serial Flash device, which implements the USB flash disk file storage. -- A physical UART connection which is relayed over interface USB Serial port. - -Flashing an application to EFR32-SLTB004A ------------------------------------------ - -The sample application :ref:`hello_world` is used for this example. -Build the Zephyr kernel and application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efr32mg_sltb004a - :goals: build - -Connect the EFR32MG-SLTB004A to your host computer using the USB port and you -should see a USB connection which exposes a Mass Storage (TB004) and a -USB Serial Port. Copy the generated zephyr.bin in the SLTB004A drive. - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you should be able to see on the corresponding Serial Port -the following message: - -.. code-block:: console - - Hello World! arm - - -.. _EFR32MG-SLTB004A Website: - https://www.silabs.com/products/development-tools/thunderboard/thunderboard-sense-two-kit - -.. _EFR32MG-SLTB004A User Guide: - https://www.silabs.com/documents/public/user-guides/ug309-sltb004a-user-guide.pdf - -.. _EFR32MG-SLTB004A Schematics: - https://www.silabs.com/documents/public/schematic-files/BRD4166A-D00-schematic.pdf - -.. _EFR32MG Website: - https://www.silabs.com/products/wireless/mesh-networking/efr32mg-mighty-gecko-zigbee-thread-soc - -.. _EFR32MG Datasheet: - https://www.silabs.com/documents/public/data-sheets/efr32mg12-datasheet.pdf - -.. _EFR32MG Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/efr32xg12-rm.pdf - -.. _J-Link: - https://www.segger.com/jlink-debug-probes.html - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/silabs/efr32mg_sltb004a/efr32mg_sltb004a.dts b/boards/silabs/efr32mg_sltb004a/efr32mg_sltb004a.dts deleted file mode 100644 index 3819bd6ca94..00000000000 --- a/boards/silabs/efr32mg_sltb004a/efr32mg_sltb004a.dts +++ /dev/null @@ -1,234 +0,0 @@ -/* - * Copyright (c) 2018 Diego Sueiro - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include -#include - -/ { - model = "Silabs EFR32MG SLTB004A board (aka Thunderboard Sense 2)"; - compatible = "silabs,efr32mg_sltb004a", "silabs,efr32mg"; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0; - led1 = &led1; - pwm-led0 = &pwm_led0; - sw0 = &button0; - sw1 = &button1; - watchdog0 = &wdog0; - watchdog1 = &wdog1; - spi-flash0 = &mx25r80; - }; - - chosen { - zephyr,console = &usart0; - zephyr,shell-uart = &usart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpiod 8 0>; - label = "LED 0"; - }; - led1: led_1 { - gpios = <&gpiod 9 0>; - label = "LED 1"; - }; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - /* gpio flags need validation */ - gpios = <&gpiod 14 GPIO_ACTIVE_LOW>; - label = "User Push Button 0"; - zephyr,code = ; - }; - button1: button_1 { - /* gpio flags need validation */ - gpios = <&gpiod 15 GPIO_ACTIVE_LOW>; - label = "User Push Button 1"; - zephyr,code = ; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - status = "okay"; - pwm_led0: pwm_led0 { - pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; - }; - }; -}; - -&cpu0 { - clock-frequency = <38400000>; -}; - -&usart0 { - current-speed = <115200>; - pinctrl-0 = <&usart0_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usart2 { - compatible = "silabs,gecko-spi-usart"; - - #address-cells = <1>; - #size-cells = <0>; - - location-rx = ; - location-tx = ; - location-clk = ; - - cs-gpios = <&gpiok 1 GPIO_ACTIVE_LOW>; - - status = "okay"; - - mx25r80: mx25r8035f@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <80000000>; - size = <0x800000>; - jedec-id = [c2 28 14]; - sfdp-bfp = [ - e5 20 f1 ff ff ff 7f 00 44 eb 08 6b 08 3b 04 bb - ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 - 10 d8 00 ff 23 72 f5 00 82 ed 04 b7 44 83 38 44 - 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff - ]; - }; -}; - -&leuart0 { - current-speed = <9600>; - location-rx = ; - location-tx = ; - status = "okay"; -}; - -&pinctrl { - i2c0_default: i2c0_default { - group1 { - psels = , - , - , - ; - }; - }; - - i2c1_default: i2c1_default { - group1 { - psels = , - , - , - ; - }; - }; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&i2c1 { - /* This set selects for CCS811_I2C supporting CCS811 */ - pinctrl-0 = <&i2c1_default>; - pinctrl-names = "default"; - status = "okay"; - - ccs811: ccs811@5a { - compatible = "ams,ccs811"; - reg = <0x5a>; - supply-gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>; - irq-gpios = <&gpiof 13 GPIO_ACTIVE_LOW>; - wake-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>; - }; - - /* This set selects for ENV_I2C supporting Si7021, Si11330, BMP280 */ - /* - location-sda = ; - location-scl = ; - */ - - /* This set selects for HALL_I2C supporting Si7210 */ - /* - location-sda = ; - location-scl = ; - */ -}; - -&rtcc0 { - prescaler = <1>; - status = "okay"; -}; - -&timer0 { - status = "okay"; - - pwm0: pwm { - status = "okay"; - pin-location = ; - prescaler = <1024>; - }; -}; - -&gpio { - location-swo = <0>; - status = "okay"; -}; - -&gpioa { - status = "okay"; -}; - -&gpiod { - status = "okay"; -}; - -&gpiof { - status = "okay"; -}; - -&gpiok { - status = "okay"; -}; - -&wdog0 { - status = "okay"; -}; - -&wdog1 { - status = "okay"; -}; - -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Set 6Kb of storage at the end of the 1024Kb of flash */ - storage_partition: partition@fe800 { - label = "storage"; - reg = <0x000fe800 0x00001800>; - }; - - }; -}; - -&trng0 { - status = "okay"; -}; diff --git a/boards/silabs/efr32mg_sltb004a/efr32mg_sltb004a.yaml b/boards/silabs/efr32mg_sltb004a/efr32mg_sltb004a.yaml deleted file mode 100644 index 3c8cbd773d0..00000000000 --- a/boards/silabs/efr32mg_sltb004a/efr32mg_sltb004a.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: efr32mg_sltb004a -name: EFR32MG-SLTB004A -type: mcu -arch: arm -ram: 256 -flash: 1024 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - gpio - - i2c - - nvs - - spi - - watchdog -testing: - ignore_tags: - - net - - bluetooth -vendor: silabs diff --git a/boards/silabs/efr32xg24_dk2601b/Kconfig b/boards/silabs/efr32xg24_dk2601b/Kconfig deleted file mode 100644 index c695033c2ff..00000000000 --- a/boards/silabs/efr32xg24_dk2601b/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -# EFR32XG24 DK2601B board - -# Copyright (c) 2022, Silicon Labs -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EFR32XG24_DK2601B - -module = BOARD_EFR32MG24 -module-str = Board Control -source "subsys/logging/Kconfig.template.log_config" - -endif # BOARD_EFR32XG24_DK2601B diff --git a/boards/silabs/efr32xg24_dk2601b/Kconfig.defconfig b/boards/silabs/efr32xg24_dk2601b/Kconfig.defconfig deleted file mode 100644 index 52d6391c03e..00000000000 --- a/boards/silabs/efr32xg24_dk2601b/Kconfig.defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# EFR32XG24 DK2601B board - -# Copyright (c) 2021, Sateesh Kotapati -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EFR32XG24_DK2601B - -config CMU_HFXO_FREQ - default 40000000 - -config CMU_LFXO_FREQ - default 32768 - -config FLASH_BASE_ADDRESS - hex - default 0x08000000 - -if SOC_GECKO_USE_RAIL - -config FPU - default y - -endif # SOC_GECKO_USE_RAIL - -if BT - -config FPU - default y - -config MINIMAL_LIBC_MALLOC_ARENA_SIZE - default 8192 - -config MAIN_STACK_SIZE - default 2304 - -config BT_SILABS_HCI - default y - -if SHELL - -config SHELL_STACK_SIZE - default 4096 - -endif # SHELL - -endif # BT - -endif # BOARD_EFR32XG24_DK2601B diff --git a/boards/silabs/efr32xg24_dk2601b/Kconfig.efr32xg24_dk2601b b/boards/silabs/efr32xg24_dk2601b/Kconfig.efr32xg24_dk2601b deleted file mode 100644 index 3826dc11b2a..00000000000 --- a/boards/silabs/efr32xg24_dk2601b/Kconfig.efr32xg24_dk2601b +++ /dev/null @@ -1,7 +0,0 @@ -# EFR32XG24 DK2601B board - -# Copyright (c) 2021, Sateesh Kotapati -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFR32XG24_DK2601B - select SOC_PART_NUMBER_EFR32MG24B310F1536IM48 diff --git a/boards/silabs/efr32xg24_dk2601b/board.c b/boards/silabs/efr32xg24_dk2601b/board.c deleted file mode 100644 index 5b138e864ca..00000000000 --- a/boards/silabs/efr32xg24_dk2601b/board.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2021 Sateesh Kotapati - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include - -#ifdef CONFIG_SOC_GECKO_DEV_INIT -#include "em_cmu.h" -#endif - -LOG_MODULE_REGISTER(efr32xg24_dk2601b, CONFIG_BOARD_EFR32MG24_LOG_LEVEL); - -static int efr32xg24_dk2601b_init_clocks(void); - -static int efr32xg24_dk2601b_init(void) -{ - int ret; - -#ifdef CONFIG_SOC_GECKO_DEV_INIT - efr32xg24_dk2601b_init_clocks(); -#endif - static struct gpio_dt_spec wake_up_gpio_dev = - GPIO_DT_SPEC_GET(DT_NODELABEL(wake_up_trigger), gpios); - - - if (!gpio_is_ready_dt(&wake_up_gpio_dev)) { - LOG_ERR("Wake-up GPIO device was not found!\n"); - return -ENODEV; - } - ret = gpio_pin_configure_dt(&wake_up_gpio_dev, GPIO_OUTPUT_ACTIVE); - if (ret < 0) - return ret; - - return 0; -} - -#ifdef CONFIG_SOC_GECKO_DEV_INIT -static int efr32xg24_dk2601b_init_clocks(void) -{ - CMU_ClockSelectSet(cmuClock_SYSCLK, cmuSelect_HFRCODPLL); -#if defined(_CMU_EM01GRPACLKCTRL_MASK) - CMU_ClockSelectSet(cmuClock_EM01GRPACLK, cmuSelect_HFRCODPLL); -#endif -#if defined(_CMU_EM01GRPBCLKCTRL_MASK) - CMU_ClockSelectSet(cmuClock_EM01GRPBCLK, cmuSelect_HFRCODPLL); -#endif - CMU_ClockSelectSet(cmuClock_EM23GRPACLK, cmuSelect_LFRCO); - CMU_ClockSelectSet(cmuClock_EM4GRPACLK, cmuSelect_LFRCO); -#if defined(RTCC_PRESENT) - CMU_ClockSelectSet(cmuClock_RTCC, cmuSelect_LFRCO); -#endif -#if defined(SYSRTC_PRESENT) - CMU_ClockSelectSet(cmuClock_SYSRTC, cmuSelect_LFRCO); -#endif - CMU_ClockSelectSet(cmuClock_WDOG0, cmuSelect_LFRCO); -#if WDOG_COUNT > 1 - CMU_ClockSelectSet(cmuClock_WDOG1, cmuSelect_LFRCO); -#endif - - return 0; -} -#endif - -/* needs to be done after GPIO driver init */ -SYS_INIT(efr32xg24_dk2601b_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); diff --git a/boards/silabs/efr32xg24_dk2601b/board.yml b/boards/silabs/efr32xg24_dk2601b/board.yml deleted file mode 100644 index d4efb7ba178..00000000000 --- a/boards/silabs/efr32xg24_dk2601b/board.yml +++ /dev/null @@ -1,5 +0,0 @@ -board: - name: efr32xg24_dk2601b - vendor: silabs - socs: - - name: efr32mg24b310f1536im48 diff --git a/boards/silabs/efr32xg24_dk2601b/doc/index.rst b/boards/silabs/efr32xg24_dk2601b/doc/index.rst deleted file mode 100644 index f6be0f82889..00000000000 --- a/boards/silabs/efr32xg24_dk2601b/doc/index.rst +++ /dev/null @@ -1,184 +0,0 @@ -.. _efr32mg24_dk2601b: - -xG24-DK2601B -########################### - -Overview -******** - -The EFR32MG24 Mighty Gecko Board dev kit contains -a Wireless System-On-Chip from the EFR32MG24 family built on an -ARM Cortex®-M33F processor with excellent low power capabilities. - -.. figure:: ./img/efr32xg24_dk2601b.jpg - :height: 260px - :align: center - :alt: SLWRB4180A Mighty Gecko Radio Board - - xG24-DK2601B (image courtesy of Silicon Labs) - -Hardware -******** - -- EFR32MG24B310F1536IM48-B Mighty Gecko SoC -- CPU core: ARM Cortex®-M33 with FPU -- Flash memory: 1536 kB -- RAM: 256 kB -- Transmit power: up to +20 dBm -- Operation frequency: 2.4 GHz -- Crystals for LFXO (32.768 kHz) and HFXO (38.4 MHz). -- On board sensors: - - - Silicon Labs Si7021 relative humidity & temperature sensor - - Silicon Labs Si7210 hall effect sensor - - 2x TDK InvenSense ICS-43434 MEMS microphones with I2S output - - TDK InvenSense ICM-20689 6-axis inertial measurement sensor - - Vishay VEML6035 ambient light sensor - - Bosch BMP384 pressure sensor with internal temperature sensor - -For more information about the EFR32MG24 SoC and BRD2601B board, refer to these -documents: - -- `EFR32MG24 Website`_ -- `EFR32MG24 Datasheet`_ -- `EFR32xG24 Reference Manual`_ -- `BRD2601B User Guide`_ - -Supported Features -================== - -The board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | stimer | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | semailbox | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| I2C(M/S) | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| RADIO | on-chip | bluetooth | -+-----------+------------+-------------------------------------+ - -Other hardware features are currently not supported by the port. - -Connections and IOs -=================== - -In the following table, the column **Name** contains Pin names. For example, PA2 -means Pin number 2 on PORTA, as used in the board's datasheets and manuals. - -+-------+-------------+-------------------------------------+ -| Name | Function | Usage | -+=======+=============+=====================================+ -| PA4 | GPIO | LED0 | -+-------+-------------+-------------------------------------+ -| PB0 | GPIO | LED1 | -+-------+-------------+-------------------------------------+ -| PB2 | GPIO | Push Button 0 | -+-------+-------------+-------------------------------------+ -| PB3 | GPIO | Push Button 1 | -+-------+-------------+-------------------------------------+ -| PA5 | USART0_TX | UART Console EFM_BC_TX US0_TX | -+-------+-------------+-------------------------------------+ -| PA6 | USART0_RX | UART Console EFM_BC_RX US0_RX | -+-------+-------------+-------------------------------------+ - -The default configuration can be found in -:zephyr_file:`boards/silabs/efr32xg24_dk2601b/efr32xg24_dk2601b_defconfig` - -System Clock -============ - -The EFR32MG24 SoC is configured to use the 39 MHz external oscillator on the -board. - -Serial Port -=========== - -The EFR32MG24 SoC has one USART and two EUSARTs. -USART0 is connected to the board controller and is used for the console. - -Programming and Debugging -************************* - -.. note:: - Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ - -Flashing -======== - -The sample application :ref:`hello_world` is used for this example. -Build the Zephyr kernel and application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efr32xg24_dk2601b - :goals: build - -Connect the efr32xg24_dk2601b to your host computer using the USB port and you -should see a USB connection. - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you'll see the following message on the corresponding serial port -terminal session: - -.. code-block:: console - - Hello World! efr32xg24_dk2601b - -Bluetooth -========= - -To use the BLE function, run the command below to retrieve necessary binary -blobs from the SiLabs HAL repository. - -.. code-block:: console - - west blobs fetch silabs - -Then build the Zephyr kernel and a Bluetooth sample with the following -command. The :ref:`bluetooth-observer-sample` sample application is used in -this example. - -.. zephyr-app-commands:: - :zephyr-app: samples/bluetooth/observer - :board: efr32xg24_dk2601b - :goals: build - -.. _EFR32MG24 Website: - https://www.silabs.com/wireless/zigbee/efr32mg24-series-2-socs# - -.. _EFR32MG24 Datasheet: - https://www.silabs.com/documents/public/data-sheets/efr32mg24-datasheet.pdf - -.. _EFR32xG24 Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/efr32xg24-rm.pdf - -.. _BRD2601B User Guide: - https://www.silabs.com/documents/public/user-guides/ug524-brd2601b-user-guide.pdf - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/silabs/efr32xg24_dk2601b/efr32xg24_dk2601b.dts b/boards/silabs/efr32xg24_dk2601b/efr32xg24_dk2601b.dts deleted file mode 100644 index ffa883da6f9..00000000000 --- a/boards/silabs/efr32xg24_dk2601b/efr32xg24_dk2601b.dts +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Copyright (c) 2020 TriaGnoSys GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include -#include - -/ { - model = "Silicon Labs BRD2601B (Mighty Gecko Radio Board)"; - compatible = "silabs,efr32mg24_brd2601b", "silabs,efr32mg24"; - - chosen { - zephyr,console = &usart0; - zephyr,shell-uart = &usart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; - - aliases { - led0 = &red_led; - led1 = &green_led; - led2 = &blue_led; - sw0 = &button0; - sw1 = &button1; - watchdog0 = &wdog0; - }; - - leds { - compatible = "gpio-leds"; - red_led: led_2 { - gpios = <&gpiod GECKO_PIN(2) GPIO_ACTIVE_LOW>; - }; - green_led: led_0 { - gpios = <&gpioa GECKO_PIN(4) GPIO_ACTIVE_LOW>; - }; - blue_led: led_1 { - gpios = <&gpiob GECKO_PIN(0) GPIO_ACTIVE_LOW>; - }; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - gpios = <&gpiob GECKO_PIN(2) GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - button1: button_1 { - gpios = <&gpiob GECKO_PIN(3) GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - }; - - wake_up_trigger: gpio-wake-up { - compatible = "silabs,gecko-wake-up-trigger"; - gpios = <&gpioa GECKO_PIN(5) GPIO_ACTIVE_LOW>; - }; - - sensor_enable: gpio_switch_0 { - compatible = "regulator-fixed"; - regulator-name = "sensor_enable"; - enable-gpios = <&gpioc GECKO_PIN(9) GPIO_ACTIVE_HIGH>; - regulator-boot-on; - }; -}; - -&cpu0 { - clock-frequency = <78000000>; -}; - -&usart0 { - current-speed = <115200>; - pinctrl-0 = <&usart0_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; - status = "okay"; - - veml6035: veml6035@29 { - compatible = "vishay,veml7700"; - reg = <0x29>; - status = "okay"; - }; - - si7210: si7210@30 { - compatible = "silabs,si7210"; - reg = <0x30>; - status = "okay"; - }; - - si7021: si7021@40 { - compatible = "silabs,si7006"; - reg = <0x40>; - status = "okay"; - }; -}; - -&gpio { - status = "okay"; -}; - -&gpioa { - status = "okay"; -}; - -&gpiob { - status = "okay"; -}; - -&gpioc { - status = "okay"; -}; - -&gpiod { - status = "okay"; -}; - -&wdog0 { - status = "okay"; -}; - -&se { - status = "okay"; -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 48 kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x0 0x0000c000>; - read-only; - }; - - /* Reserve 464 kB for the application in slot 0 */ - slot0_partition: partition@c000 { - label = "storage"; - reg = <0x0000c000 0x00074000>; - }; - - /* Reserve 464 kB for the application in slot 1 */ - slot1_partition: partition@80000 { - label = "image-0"; - reg = <0x00080000 0x00074000>; - }; - - /* Reserve 32 kB for the scratch partition */ - scratch_partition: partition@f4000 { - label = "image-1"; - reg = <0x000f4000 0x00008000>; - }; - - /* Set 528Kb of storage at the end of the 1024Kb of flash */ - storage_partition: partition@fc000 { - label = "image-scratch"; - reg = <0x000fc000 0x00084000>; - }; - }; -}; - -&adc0 { - status = "okay"; -}; - -&stimer0 { - status = "okay"; -}; diff --git a/boards/silabs/efr32xg24_dk2601b/efr32xg24_dk2601b.yaml b/boards/silabs/efr32xg24_dk2601b/efr32xg24_dk2601b.yaml deleted file mode 100644 index 522d945ce5a..00000000000 --- a/boards/silabs/efr32xg24_dk2601b/efr32xg24_dk2601b.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: efr32xg24_dk2601b -name: BRD4601B -type: mcu -arch: arm -ram: 256 -flash: 1536 -toolchain: - - zephyr - - gnuarmemb -supported: - - counter - - gpio - - uart - - watchdog -testing: - ignore_tags: - - net - - bluetooth - - pm - - hwinfo -vendor: silabs diff --git a/boards/silabs/index.rst b/boards/silabs/index.rst index 20a5d34136f..d4597d226ce 100644 --- a/boards/silabs/index.rst +++ b/boards/silabs/index.rst @@ -4,7 +4,26 @@ Silicon Labs ############ .. toctree:: - :maxdepth: 1 + :maxdepth: 2 + :titlesonly: :glob: - **/* + */* + +Silicon Labs development hardware is represented in Zephyr by mapping +Silicon Labs *kits* to Zephyr *boards*. The name used is the orderable product +number (OPN) of the kit, as found on the packaging and on the Silicon Labs +website. The board name in Zephyr is created by normalizing the OPN to lowercase +and replacing dashes with underscores. + +You may find multiple other number and letter sequences silk-screened or lasered +onto Silicon Labs boards, including a PCB* number and a BRD* number. In most +cases, the digits of these sequences correspond to the numerical part of the kit +OPN. For instance, the kit ``xg24_dk2601b``, which is a Dev Kit for the +EFR32xG24 SoC, uses board BRD2601B, which again uses PCB2601A. It is possible to +use the ``west boards`` command to search for board names if you have a PCB and +you don't know what board name to use: + + .. code-block:: console + + west boards -n 2601 diff --git a/boards/silabs/radio_boards/common/efr32-series1-common-pinctrl.dtsi b/boards/silabs/radio_boards/common/efr32-series1-common-pinctrl.dtsi new file mode 100644 index 00000000000..bb8f7802e6a --- /dev/null +++ b/boards/silabs/radio_boards/common/efr32-series1-common-pinctrl.dtsi @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2023 Antmicro + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + /* configuration for usart0 device, default state - operating as UART */ + usart0_default: usart0_default { + group1 { + psels = , + , + , + ; + }; + }; + + usart1_default: usart1_default { + group1 { + psels = , + , + , + , + , + ; + }; + }; + + usart2_default: usart2_default { + group1 { + psels = , + , + , + , + , + ; + }; + }; +}; diff --git a/boards/silabs/radio_boards/common/efr32-series1-common.dtsi b/boards/silabs/radio_boards/common/efr32-series1-common.dtsi new file mode 100644 index 00000000000..8ff361eccaa --- /dev/null +++ b/boards/silabs/radio_boards/common/efr32-series1-common.dtsi @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2020 Piotr Mienkowski + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "efr32-series1-common-pinctrl.dtsi" + +/ { + chosen { + zephyr,console = &usart0; + zephyr,shell-uart = &usart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + led1 = &led1; + sw0 = &button0; + sw1 = &button1; + watchdog0 = &wdog0; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpiof 4 0>; + label = "LED 0"; + }; + led1: led_1 { + gpios = <&gpiof 5 0>; + label = "LED 1"; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + /* gpio flags need validation */ + gpios = <&gpiof 6 GPIO_ACTIVE_LOW>; + label = "User Push Button 0"; + zephyr,code = ; + }; + button1: button_1 { + /* gpio flags need validation */ + gpios = <&gpiof 7 GPIO_ACTIVE_LOW>; + label = "User Push Button 1"; + zephyr,code = ; + }; + }; + +}; + +&usart0 { + current-speed = <115200>; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usart1 { + compatible = "silabs,gecko-spi-usart"; + + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&usart1_default>; + pinctrl-names = "default"; + + cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>; + + status = "okay"; + + mx25r80: mx25r8035f@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <33000000>; + size = <0x800000>; + jedec-id = [c2 28 14]; + }; +}; + +&rtcc0 { + prescaler = <1>; + status = "okay"; +}; + +&gpio { + location-swo = <0>; + status = "okay"; +}; + +&gpioa { + status = "okay"; + + board-controller-enable { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&gpiob { + status = "okay"; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&gpiof { + status = "okay"; +}; + +&wdog0 { + status = "okay"; +}; diff --git a/boards/silabs/radio_boards/index.rst b/boards/silabs/radio_boards/index.rst new file mode 100644 index 00000000000..a4928294fad --- /dev/null +++ b/boards/silabs/radio_boards/index.rst @@ -0,0 +1,60 @@ +.. _silabs_radio_boards: + +Radio Boards +############ + +.. toctree:: + :maxdepth: 1 + :titlesonly: + :glob: + + **/* + +Overview +******** + +Radio Boards are used together with a Wireless Mainboard, which is a +development platform for application development and debugging of wireless +products. + +There are two main variants of the Mainboard: + +- Wireless Starter Kit Mainboard (board BRD4001A, available standalone as SLWMB4001A) +- Wireless Pro Kit Mainboard (board BRD4002A, available standalone as Si-MB4002A) + +The Wireless Pro Kit Mainboard is a strict superset of the Wireless Starter Kit, +the two boards are pin compatible for all shared functionality. + +Wireless Starter Kits and Wireless Pro Kits are kits that bundle one or more +Radio Boards with one or more Mainboards. + +In Zephyr, Radio Boards are used as board targets, irrespective of whether the +board was acquired standalone or as part of a Starter Kit or Pro Kit. The kit +name of the standalone Radio Board is used as the board target. + +Hardware +******** + +Wireless Starter Kit Mainboard: + +- Advanced Energy Monitor providing real-time information about energy consumption at up to 10 ksps +- Packet Trace Interface +- Virtual COM port +- On-board Segger J-Link debugger with USB and Ethernet interfaces +- Ultra-low power 128x128 pixel memory LCD +- 2 user buttons and 2 LEDs +- 20 pin 2.54mm expansion header +- Si7021 Relative Humidity and Temperature Sensor +- Breakout pads for Wireless SoC I/O + +Wireless Pro Kit Mainboard: + +- Advanced Energy Monitor providing real-time information about energy consumption at up to 100 ksps +- Packet Trace Interface +- Virtual COM port +- On-board Segger J-Link debugger with USB and Ethernet interfaces +- Ultra-low power 128x128 pixel memory LCD +- 2 user buttons, joystick and 2 LEDs +- 20 pin 2.54mm expansion header +- Si7021 Relative Humidity and Temperature Sensor +- Breakout pads for Wireless SoC I/O diff --git a/boards/silabs/radio_boards/slwrb4104a/Kconfig.defconfig b/boards/silabs/radio_boards/slwrb4104a/Kconfig.defconfig new file mode 100644 index 00000000000..09a4f9906ae --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4104a/Kconfig.defconfig @@ -0,0 +1,44 @@ +# EFR32 radio board + +# Copyright (c) 2020 Piotr Mienkowski +# Copyright (c) 2020 TriaGnoSys GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_SLWRB4104A + +config CMU_HFXO_FREQ + default 38400000 + +config CMU_LFXO_FREQ + default 32768 + +config FLASH_BASE_ADDRESS + hex + default 0x0 + +config LOG_BACKEND_SWO_FREQ_HZ + default 875000 + depends on LOG_BACKEND_SWO + +if SOC_GECKO_USE_RAIL + +config FPU + default n + +endif # SOC_GECKO_USE_RAIL + +if BT + +config FPU + default y + +config COMMON_LIBC_MALLOC_ARENA_SIZE + default 8192 + +config MAIN_STACK_SIZE + default 3072 if PM + default 2304 + +endif # BT + +endif # BOARD_SLWRB4104A diff --git a/boards/silabs/radio_boards/slwrb4104a/Kconfig.slwrb4104a b/boards/silabs/radio_boards/slwrb4104a/Kconfig.slwrb4104a new file mode 100644 index 00000000000..179b7f02c0a --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4104a/Kconfig.slwrb4104a @@ -0,0 +1,8 @@ +# EFR32BG13 BRD4104A + +# Copyright (c) 2020 Piotr Mienkowski +# Copyright (c) 2020 TriaGnoSys GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SLWRB4104A + select SOC_PART_NUMBER_EFR32BG13P632F512GM48 diff --git a/boards/silabs/radio_boards/slwrb4104a/board.cmake b/boards/silabs/radio_boards/slwrb4104a/board.cmake new file mode 100644 index 00000000000..cf1d8ee0e75 --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4104a/board.cmake @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd) +board_runner_args(jlink "--device=EFR32BG13PxxxF512") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/silabs/radio_boards/slwrb4104a/board.yml b/boards/silabs/radio_boards/slwrb4104a/board.yml new file mode 100644 index 00000000000..5ca377b2c8f --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4104a/board.yml @@ -0,0 +1,4 @@ +boards: + - name: slwrb4104a + socs: + - name: efr32bg13p632f512gm48 diff --git a/boards/silabs/efr32_radio/doc/efr32bg13-slwrb4104a.jpg b/boards/silabs/radio_boards/slwrb4104a/doc/efr32bg13-slwrb4104a.jpg similarity index 100% rename from boards/silabs/efr32_radio/doc/efr32bg13-slwrb4104a.jpg rename to boards/silabs/radio_boards/slwrb4104a/doc/efr32bg13-slwrb4104a.jpg diff --git a/boards/silabs/radio_boards/slwrb4104a/doc/index.rst b/boards/silabs/radio_boards/slwrb4104a/doc/index.rst new file mode 100644 index 00000000000..3496421743c --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4104a/doc/index.rst @@ -0,0 +1,171 @@ +.. _slwrb4104a: + +EFR32BG13 2.4 GHz 10 dBm (SLWRB4104A) +##################################### + +Overview +******** + +The EFR32BG13 Blue Gecko Bluetooth® Low Energy Radio Board is one of the two +radio boards delivered with `SLWSTK6020B Bluetooth SoC Starter Kit`_. It +contains a Wireless System-On-Chip from the EFR32BG13 family built on an +ARM Cortex®-M4F processor with excellent low power capabilities. + +.. figure:: efr32bg13-slwrb4104a.jpg + :align: center + :alt: SLWRB4104A Blue Gecko Bluetooth® Low Energy Radio Board + + SLWRB4104A (image courtesy of Silicon Labs) + +The BRD4104A a.k.a. SLWRB4104A radio board plugs into the Wireless Starter Kit +Mainboard BRD4001A and is supported as one of :ref:`silabs_radio_boards`. + +Hardware +******** + +- EFR32BG13P632F512GM48 Blue Gecko SoC +- CPU core: ARM Cortex®-M4 with FPU +- Flash memory: 512 kB +- RAM: 64 kB +- Transmit power: up to +10 dBm +- Operation frequency: 2.4 GHz +- 8Mbit SPI NOR Flash +- Crystals for LFXO (32.768 kHz) and HFXO (38.4 MHz). + +For more information about the EFR32BG13 SoC and BRD4104A board, refer to these +documents: + +- `EFR32BG13 Website`_ +- `EFR32BG13 Datasheet`_ +- `EFR32xG13 Reference Manual`_ +- `SLWSTK6020B Bluetooth SoC Starter Kit`_ +- `BRD4104A User Guide`_ +- `BRD4104A Reference Manual`_ +- `EFR32BG13-BRD4104A Schematics`_ + +Supported Features +================== + +The board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtcc | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| SPI(M) | on-chip | spi port-polling | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/radio_boards/slwrb4104a/slwrb4104a_defconfig` + +Connections and IOs +=================== + +In the following table, the column **Pin** contains Pin names. For example, PA2 +means Pin number 2 on PORTA, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Pin | Function | Usage | ++=======+=============+=====================================+ +| PF4 | GPIO | LED0 | ++-------+-------------+-------------------------------------+ +| PF5 | GPIO | LED1 | ++-------+-------------+-------------------------------------+ +| PF6 | GPIO | Push Button PB0 | ++-------+-------------+-------------------------------------+ +| PF7 | GPIO | Push Button PB1 | ++-------+-------------+-------------------------------------+ +| PA5 | GPIO | Board Controller Enable | +| | | VCOM_ENABLE | ++-------+-------------+-------------------------------------+ +| PA0 | USART0_TX | UART Console VCOM_TX US0_TX #0 | ++-------+-------------+-------------------------------------+ +| PA1 | USART0_RX | UART Console VCOM_RX US0_RX #0 | ++-------+-------------+-------------------------------------+ +| PC6 | SPI_MOSI | Flash MOSI US1_TX #11 | ++-------+-------------+-------------------------------------+ +| PC7 | SPI_MISO | Flash MISO US1_RX #11 | ++-------+-------------+-------------------------------------+ +| PC8 | SPI_SCLK | Flash SCLK US1_CLK #11 | ++-------+-------------+-------------------------------------+ +| PA4 | SPI_CS | Flash Chip Select (GPIO) | ++-------+-------------+-------------------------------------+ + +System Clock +============ + +The EFR32BG13P SoC is configured to use the 38.4 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFR32BG13P SoC has three USARTs and one Low Energy UARTs (LEUART). +USART0 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +Flashing +======== + +Connect the BRD4001A board with a mounted BRD4104A radio module to your host +computer using the USB port. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: slwrb4104a + :goals: flash + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you should see the following message in the terminal: + +.. code-block:: console + + Hello World! slwrb4161a + + +.. _EFR32BG13 Website: + https://www.silabs.com/wireless/bluetooth/efr32bg13-series-1-socs + +.. _EFR32BG13 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efr32bg13-datasheet.pdf + +.. _EFR32xG13 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efr32xg13-rm.pdf + +.. _SLWSTK6020B Bluetooth SoC Starter Kit: + https://www.silabs.com/products/development-tools/wireless/bluetooth/blue-gecko-bluetooth-low-energy-soc-starter-kit + +.. _BRD4104A User Guide: + https://www.silabs.com/documents/public/user-guides/ug279-brd4104a-user-guide.pdf + +.. _BRD4104A Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/brd4104a-rm.pdf + +.. _EFR32BG13-BRD4104A Schematics: + https://www.silabs.com/documents/public/schematic-files/BRD4104A-A00-schematic.pdf diff --git a/boards/silabs/radio_boards/slwrb4104a/pre_dt_board.cmake b/boards/silabs/radio_boards/slwrb4104a/pre_dt_board.cmake new file mode 100644 index 00000000000..beb76b85552 --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4104a/pre_dt_board.cmake @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +# SPI is implemented via usart so node name isn't spi@... +list(APPEND EXTRA_DTC_FLAGS "-Wno-spi_bus_bridge") diff --git a/boards/silabs/radio_boards/slwrb4104a/slwrb4104a.dts b/boards/silabs/radio_boards/slwrb4104a/slwrb4104a.dts new file mode 100644 index 00000000000..bf52031a95b --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4104a/slwrb4104a.dts @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2020 Piotr Mienkowski + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "../common/efr32-series1-common.dtsi" + +/ { + model = "Silicon Labs BRD4104A (Blue Gecko 13 Radio Board)"; + compatible = "silabs,slwrb4104a", "silabs,efr32bg13p"; +}; + +&cpu0 { + clock-frequency = <38400000>; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 32 kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 0x00008000>; + read-only; + }; + + /* Reserve 220 kB for the application in slot 0 */ + slot0_partition: partition@8000 { + label = "image-0"; + reg = <0x00008000 0x00037000>; + }; + + /* Reserve 220 kB for the application in slot 1 */ + slot1_partition: partition@3f000 { + label = "image-1"; + reg = <0x0003f000 0x00037000>; + }; + + /* Reserve 32 kB for the scratch partition */ + scratch_partition: partition@76000 { + label = "image-scratch"; + reg = <0x00076000 0x00008000>; + }; + + /* Set 8Kb of storage at the end of the 512KB of flash */ + storage_partition: partition@7e000 { + label = "storage"; + reg = <0x0007e000 0x00002000>; + }; + + }; +}; diff --git a/boards/silabs/radio_boards/slwrb4104a/slwrb4104a.yaml b/boards/silabs/radio_boards/slwrb4104a/slwrb4104a.yaml new file mode 100644 index 00000000000..926a55f3150 --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4104a/slwrb4104a.yaml @@ -0,0 +1,22 @@ +identifier: slwrb4104a +name: EFR32BG13 2.4 GHz 10 dBm Radio Board (SLWRB4104A) +type: mcu +arch: arm +ram: 64 +flash: 512 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - counter + - gpio + - nvs + - spi + - uart + - watchdog +testing: + ignore_tags: + - net + - bluetooth +vendor: silabs diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32fg13p233f512gm48_defconfig b/boards/silabs/radio_boards/slwrb4104a/slwrb4104a_defconfig similarity index 100% rename from boards/silabs/efr32_radio/efr32_radio_efr32fg13p233f512gm48_defconfig rename to boards/silabs/radio_boards/slwrb4104a/slwrb4104a_defconfig diff --git a/boards/silabs/efr32_radio/support/openocd.cfg b/boards/silabs/radio_boards/slwrb4104a/support/openocd.cfg similarity index 100% rename from boards/silabs/efr32_radio/support/openocd.cfg rename to boards/silabs/radio_boards/slwrb4104a/support/openocd.cfg diff --git a/boards/silabs/radio_boards/slwrb4161a/Kconfig.defconfig b/boards/silabs/radio_boards/slwrb4161a/Kconfig.defconfig new file mode 100644 index 00000000000..bf950b922f9 --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4161a/Kconfig.defconfig @@ -0,0 +1,44 @@ +# EFR32 radio board + +# Copyright (c) 2020 Piotr Mienkowski +# Copyright (c) 2020 TriaGnoSys GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_SLWRB4161A + +config CMU_HFXO_FREQ + default 38400000 + +config CMU_LFXO_FREQ + default 32768 + +config FLASH_BASE_ADDRESS + hex + default 0x0 + +config LOG_BACKEND_SWO_FREQ_HZ + default 875000 + depends on LOG_BACKEND_SWO + +if SOC_GECKO_USE_RAIL + +config FPU + default n + +endif # SOC_GECKO_USE_RAIL + +if BT + +config FPU + default y + +config COMMON_LIBC_MALLOC_ARENA_SIZE + default 8192 + +config MAIN_STACK_SIZE + default 3072 if PM + default 2304 + +endif # BT + +endif # BOARD_SLWRB4161A diff --git a/boards/silabs/radio_boards/slwrb4161a/Kconfig.slwrb4161a b/boards/silabs/radio_boards/slwrb4161a/Kconfig.slwrb4161a new file mode 100644 index 00000000000..67291857e9f --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4161a/Kconfig.slwrb4161a @@ -0,0 +1,8 @@ +# EFR32MG12 BRD4161A + +# Copyright (c) 2020 Piotr Mienkowski +# Copyright (c) 2020 TriaGnoSys GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SLWRB4161A + select SOC_PART_NUMBER_EFR32MG12P432F1024GL125 diff --git a/boards/silabs/radio_boards/slwrb4161a/board.cmake b/boards/silabs/radio_boards/slwrb4161a/board.cmake new file mode 100644 index 00000000000..be43109892d --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4161a/board.cmake @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd) +board_runner_args(jlink "--device=EFR32MG12PxxxF1024") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/silabs/radio_boards/slwrb4161a/board.yml b/boards/silabs/radio_boards/slwrb4161a/board.yml new file mode 100644 index 00000000000..a05542a40d8 --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4161a/board.yml @@ -0,0 +1,4 @@ +boards: + - name: slwrb4161a + socs: + - name: efr32mg12p432f1024gl125 diff --git a/boards/silabs/efr32_radio/doc/efr32mg12-slwrb4161a.jpeg b/boards/silabs/radio_boards/slwrb4161a/doc/efr32mg12-slwrb4161a.jpeg similarity index 100% rename from boards/silabs/efr32_radio/doc/efr32mg12-slwrb4161a.jpeg rename to boards/silabs/radio_boards/slwrb4161a/doc/efr32mg12-slwrb4161a.jpeg diff --git a/boards/silabs/radio_boards/slwrb4161a/doc/index.rst b/boards/silabs/radio_boards/slwrb4161a/doc/index.rst new file mode 100644 index 00000000000..927e27c20ae --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4161a/doc/index.rst @@ -0,0 +1,156 @@ +.. _slwrb4161a: + +EFR32MG12 2.4 GHz 19 dBm (SLWRB4161A) +##################################### + +Overview +******** + +The EFR32MG12 Mighty Gecko Radio Board contains a Wireless System-On-Chip +from the EFR32MG12 family built on an ARM Cortex®-M4F processor with excellent +low power capabilities. + +.. figure:: efr32mg12-slwrb4161a.jpeg + :align: center + :alt: SLWRB4161A Mighty Gecko Radio Board + + SLWRB4161A (image courtesy of Silicon Labs) + +The BRD4161A a.k.a. SLWRB4161A radio board plugs into the Wireless Starter Kit +Mainboard BRD4001A and is supported as one of :ref:`silabs_radio_boards`. + +Hardware +******** + +- EFR32MG12P432F1024GL125 Mighty Gecko SoC +- CPU core: ARM Cortex®-M4 with FPU +- Flash memory: 1024 kB +- RAM: 256 kB +- Transmit power: up to +19 dBm +- Operation frequency: 2.4 GHz and Sub-Ghz +- Crystals for LFXO (32.768 kHz) and HFXO (38.4 MHz). + +For more information about the EFR32MG12 SoC and BRD4170A board, refer to these +documents: + +- `EFR32MG12 Website`_ +- `EFR32MG12 Datasheet`_ +- `EFR32xG12 Reference Manual`_ +- `BRD4161A User Guide`_ + +Supported Features +================== + +The board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtcc | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| SPI(M) | on-chip | spi port-polling | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/radio_boards/slwrb4161a/slwrb4161a_defconfig` + +Connections and IOs +=================== + +In the following table, the column **Pin** contains Pin names. For example, PA2 +means Pin number 2 on PORTA, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Pin | Function | Usage | ++=======+=============+=====================================+ +| PF4 | GPIO | LED0 | ++-------+-------------+-------------------------------------+ +| PF5 | GPIO | LED1 | ++-------+-------------+-------------------------------------+ +| PF6 | GPIO | Push Button PB0 | ++-------+-------------+-------------------------------------+ +| PF7 | GPIO | Push Button PB1 | ++-------+-------------+-------------------------------------+ +| PA5 | GPIO | Board Controller Enable VCOM_ENABLE | ++-------+-------------+-------------------------------------+ +| PA0 | USART0_TX | UART Console VCOM_TX US0_TX #0 | ++-------+-------------+-------------------------------------+ +| PA1 | USART0_RX | UART Console VCOM_RX US0_RX #0 | ++-------+-------------+-------------------------------------+ +| PC6 | SPI_MOSI | Flash MOSI US1_TX #11 | ++-------+-------------+-------------------------------------+ +| PC7 | SPI_MISO | Flash MISO US1_RX #11 | ++-------+-------------+-------------------------------------+ +| PC8 | SPI_SCLK | Flash SCLK US1_CLK #11 | ++-------+-------------+-------------------------------------+ +| PA4 | SPI_CS | Flash Chip Select (GPIO) | ++-------+-------------+-------------------------------------+ + +System Clock +============ + +The EFR32MG12P SoC is configured to use the 38.4 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFR32MG12P SoC has four USARTs and one Low Energy UARTs (LEUART). +USART0 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +Flashing +======== + +Connect the BRD4001A board with a mounted BRD4161A radio module to your host +computer using the USB port. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: slwrb4161a + :goals: flash + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you should see the following message in the terminal: + +.. code-block:: console + + Hello World! slwrb4161a + + +.. _EFR32MG12 Website: + https://www.silabs.com/wireless/zigbee/efr32mg12-series-1-socs + +.. _EFR32MG12 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efr32mg12-datasheet.pdf + +.. _EFR32xG12 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efr32xg12-rm.pdf + +.. _BRD4161A User Guide: + https://www.silabs.com/documents/public/user-guides/ug260-brd4161a-user-guide.pdf diff --git a/boards/silabs/radio_boards/slwrb4161a/pre_dt_board.cmake b/boards/silabs/radio_boards/slwrb4161a/pre_dt_board.cmake new file mode 100644 index 00000000000..beb76b85552 --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4161a/pre_dt_board.cmake @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +# SPI is implemented via usart so node name isn't spi@... +list(APPEND EXTRA_DTC_FLAGS "-Wno-spi_bus_bridge") diff --git a/boards/silabs/radio_boards/slwrb4161a/slwrb4161a.dts b/boards/silabs/radio_boards/slwrb4161a/slwrb4161a.dts new file mode 100644 index 00000000000..90787898290 --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4161a/slwrb4161a.dts @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2020 Piotr Mienkowski + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "../common/efr32-series1-common.dtsi" + +/ { + model = "Silicon Labs BRD4161A (Mighty Gecko 12 Radio Board)"; + compatible = "silabs,slwrb4161a", "silabs,efr32mg12p"; +}; + +&cpu0 { + clock-frequency = <38400000>; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 32 kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 0x00008000>; + read-only; + }; + + /* Reserve 220 kB for the application in slot 0 */ + slot0_partition: partition@8000 { + label = "image-0"; + reg = <0x00008000 0x00037000>; + }; + + /* Reserve 220 kB for the application in slot 1 */ + slot1_partition: partition@3f000 { + label = "image-1"; + reg = <0x0003f000 0x00037000>; + }; + + /* Reserve 32 kB for the scratch partition */ + scratch_partition: partition@76000 { + label = "image-scratch"; + reg = <0x00076000 0x00008000>; + }; + + /* Set 8Kb of storage at the end of the 512KB of flash */ + storage_partition: partition@7e000 { + label = "storage"; + reg = <0x0007e000 0x00002000>; + }; + + }; +}; + +&pinctrl { + i2c0_default: i2c0_default { + group1 { + psels = , + , + , + ; + }; + }; +}; + +&usart2 { + compatible = "silabs,gecko-spi-usart"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&usart2_default>; + pinctrl-names = "default"; + cs-gpios = <&gpioa 9 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + status = "okay"; + + si7021: si7021@40 { + compatible = "silabs,si7006"; + reg = <0x40>; + status = "okay"; + }; +}; diff --git a/boards/silabs/radio_boards/slwrb4161a/slwrb4161a.yaml b/boards/silabs/radio_boards/slwrb4161a/slwrb4161a.yaml new file mode 100644 index 00000000000..6f46897683e --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4161a/slwrb4161a.yaml @@ -0,0 +1,21 @@ +identifier: slwrb4161a +name: EFR32MG12 2.4 GHz 19 dBm Radio Board (SLWRB4161A) +type: mcu +arch: arm +ram: 256 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb +supported: + - counter + - gpio + - nvs + - spi + - uart + - watchdog +testing: + ignore_tags: + - net + - bluetooth +vendor: silabs diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32fg1p133f256gm48_defconfig b/boards/silabs/radio_boards/slwrb4161a/slwrb4161a_defconfig similarity index 100% rename from boards/silabs/efr32_radio/efr32_radio_efr32fg1p133f256gm48_defconfig rename to boards/silabs/radio_boards/slwrb4161a/slwrb4161a_defconfig diff --git a/boards/silabs/radio_boards/slwrb4161a/support/openocd.cfg b/boards/silabs/radio_boards/slwrb4161a/support/openocd.cfg new file mode 100644 index 00000000000..38409eb70ad --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4161a/support/openocd.cfg @@ -0,0 +1,25 @@ +if {[info exists env(OPENOCD_INTERFACE)]} { + set INTERFACE $env(OPENOCD_INTERFACE) +} else { + # By default connect over Debug USB port using the J-Link interface + set INTERFACE "jlink" +} + +source [find interface/$INTERFACE.cfg] + +transport select swd + +set CHIPNAME efr32 + +source [find target/efm32.cfg] + +$_TARGETNAME configure -event gdb-attach { + echo "Debugger attaching: halting execution" + reset halt + gdb_breakpoint_override hard +} + +$_TARGETNAME configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} diff --git a/boards/silabs/radio_boards/slwrb4170a/Kconfig.defconfig b/boards/silabs/radio_boards/slwrb4170a/Kconfig.defconfig new file mode 100644 index 00000000000..35a05e59ea5 --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4170a/Kconfig.defconfig @@ -0,0 +1,44 @@ +# EFR32 radio board + +# Copyright (c) 2020 Piotr Mienkowski +# Copyright (c) 2020 TriaGnoSys GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_SLWRB4170A + +config CMU_HFXO_FREQ + default 38400000 + +config CMU_LFXO_FREQ + default 32768 + +config FLASH_BASE_ADDRESS + hex + default 0x0 + +config LOG_BACKEND_SWO_FREQ_HZ + default 875000 + depends on LOG_BACKEND_SWO + +if SOC_GECKO_USE_RAIL + +config FPU + default n + +endif # SOC_GECKO_USE_RAIL + +if BT + +config FPU + default y + +config COMMON_LIBC_MALLOC_ARENA_SIZE + default 8192 + +config MAIN_STACK_SIZE + default 3072 if PM + default 2304 + +endif # BT + +endif # BOARD_SLWRB4170A diff --git a/boards/silabs/radio_boards/slwrb4170a/Kconfig.slwrb4170a b/boards/silabs/radio_boards/slwrb4170a/Kconfig.slwrb4170a new file mode 100644 index 00000000000..6ae34218fc3 --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4170a/Kconfig.slwrb4170a @@ -0,0 +1,8 @@ +# EFR32MG12 BRD4170A + +# Copyright (c) 2020 Piotr Mienkowski +# Copyright (c) 2020 TriaGnoSys GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SLWRB4170A + select SOC_PART_NUMBER_EFR32MG12P433F1024GM68 diff --git a/boards/silabs/radio_boards/slwrb4170a/board.cmake b/boards/silabs/radio_boards/slwrb4170a/board.cmake new file mode 100644 index 00000000000..be43109892d --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4170a/board.cmake @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd) +board_runner_args(jlink "--device=EFR32MG12PxxxF1024") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/silabs/radio_boards/slwrb4170a/board.yml b/boards/silabs/radio_boards/slwrb4170a/board.yml new file mode 100644 index 00000000000..3137d819edb --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4170a/board.yml @@ -0,0 +1,4 @@ +boards: + - name: slwrb4170a + socs: + - name: efr32mg12p433f1024gm68 diff --git a/boards/silabs/efr32_radio/doc/efr32mg12-slwrb4170a.jpg b/boards/silabs/radio_boards/slwrb4170a/doc/efr32mg12-slwrb4170a.jpg similarity index 100% rename from boards/silabs/efr32_radio/doc/efr32mg12-slwrb4170a.jpg rename to boards/silabs/radio_boards/slwrb4170a/doc/efr32mg12-slwrb4170a.jpg diff --git a/boards/silabs/radio_boards/slwrb4170a/doc/index.rst b/boards/silabs/radio_boards/slwrb4170a/doc/index.rst new file mode 100644 index 00000000000..ccc2b7248ea --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4170a/doc/index.rst @@ -0,0 +1,156 @@ +.. _slwrb4170a: + +EFR32MG12 2400/868-915 MHz 19 dBm Dual Band (SLWRB4170A) +######################################################## + +Overview +******** + +The EFR32MG12 Mighty Gecko Radio Board contains a Wireless System-On-Chip +from the EFR32MG12 family built on an ARM Cortex®-M4F processor with excellent +low power capabilities. + +.. figure:: efr32mg12-slwrb4170a.jpg + :align: center + :alt: SLWRB4170A Mighty Gecko Radio Board + + SLWRB4170A (image courtesy of Silicon Labs) + +The BRD4170A a.k.a. SLWRB4170A radio board plugs into the Wireless Starter Kit +Mainboard BRD4001A and is supported as one of :ref:`silabs_radio_boards`. + +Hardware +******** + +- EFR32MG12P433F1024GM68 Mighty Gecko SoC +- CPU core: ARM Cortex®-M4 with FPU +- Flash memory: 1024 kB +- RAM: 256 kB +- Transmit power: up to +19 dBm +- Operation frequency: 2.4 GHz and Sub-Ghz +- Crystals for LFXO (32.768 kHz) and HFXO (38.4 MHz). + +For more information about the EFR32MG12 SoC and BRD4170A board, refer to these +documents: + +- `EFR32MG12 Website`_ +- `EFR32MG12 Datasheet`_ +- `EFR32xG12 Reference Manual`_ +- `BRD4170A User Guide`_ + +Supported Features +================== + +The board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtcc | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| SPI(M) | on-chip | spi port-polling | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/radio_boards/slwrb4170a/slwrb4170a_defconfig` + +Connections and IOs +=================== + +In the following table, the column **Pin** contains Pin names. For example, PA2 +means Pin number 2 on PORTA, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Pin | Function | Usage | ++=======+=============+=====================================+ +| PF4 | GPIO | LED0 | ++-------+-------------+-------------------------------------+ +| PF5 | GPIO | LED1 | ++-------+-------------+-------------------------------------+ +| PF6 | GPIO | Push Button PB0 | ++-------+-------------+-------------------------------------+ +| PF7 | GPIO | Push Button PB1 | ++-------+-------------+-------------------------------------+ +| PA5 | GPIO | Board Controller Enable VCOM_ENABLE | ++-------+-------------+-------------------------------------+ +| PA0 | USART0_TX | UART Console VCOM_TX US0_TX #0 | ++-------+-------------+-------------------------------------+ +| PA1 | USART0_RX | UART Console VCOM_RX US0_RX #0 | ++-------+-------------+-------------------------------------+ +| PC6 | SPI_MOSI | Flash MOSI US1_TX #11 | ++-------+-------------+-------------------------------------+ +| PC7 | SPI_MISO | Flash MISO US1_RX #11 | ++-------+-------------+-------------------------------------+ +| PC8 | SPI_SCLK | Flash SCLK US1_CLK #11 | ++-------+-------------+-------------------------------------+ +| PA4 | SPI_CS | Flash Chip Select (GPIO) | ++-------+-------------+-------------------------------------+ + +System Clock +============ + +The EFR32MG12P SoC is configured to use the 38.4 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFR32MG12P SoC has four USARTs and one Low Energy UARTs (LEUART). +USART0 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +Flashing +======== + +Connect the BRD4001A board with a mounted BRD4170A radio module to your host +computer using the USB port. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: slwrb4170a + :goals: flash + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you should see the following message in the terminal: + +.. code-block:: console + + Hello World! slwrb4170a + + +.. _EFR32MG12 Website: + https://www.silabs.com/wireless/zigbee/efr32mg12-series-1-socs + +.. _EFR32MG12 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efr32mg12-datasheet.pdf + +.. _EFR32xG12 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efr32xg12-rm.pdf + +.. _BRD4170A User Guide: + https://www.silabs.com/documents/public/user-guides/ug342-brd4170a-user-guide.pdf diff --git a/boards/silabs/radio_boards/slwrb4170a/pre_dt_board.cmake b/boards/silabs/radio_boards/slwrb4170a/pre_dt_board.cmake new file mode 100644 index 00000000000..beb76b85552 --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4170a/pre_dt_board.cmake @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +# SPI is implemented via usart so node name isn't spi@... +list(APPEND EXTRA_DTC_FLAGS "-Wno-spi_bus_bridge") diff --git a/boards/silabs/radio_boards/slwrb4170a/slwrb4170a.dts b/boards/silabs/radio_boards/slwrb4170a/slwrb4170a.dts new file mode 100644 index 00000000000..94a449b2a2e --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4170a/slwrb4170a.dts @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2020 Piotr Mienkowski + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "../common/efr32-series1-common.dtsi" + +/ { + model = "Silicon Labs BRD4170A (Mighty Gecko 12 Radio Board)"; + compatible = "silabs,slwrb4170a", "silabs,efr32mg12p"; +}; + +&cpu0 { + clock-frequency = <38400000>; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 32 kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 0x00008000>; + read-only; + }; + + /* Reserve 220 kB for the application in slot 0 */ + slot0_partition: partition@8000 { + label = "image-0"; + reg = <0x00008000 0x00037000>; + }; + + /* Reserve 220 kB for the application in slot 1 */ + slot1_partition: partition@3f000 { + label = "image-1"; + reg = <0x0003f000 0x00037000>; + }; + + /* Reserve 32 kB for the scratch partition */ + scratch_partition: partition@76000 { + label = "image-scratch"; + reg = <0x00076000 0x00008000>; + }; + + /* Set 8Kb of storage at the end of the 512KB of flash */ + storage_partition: partition@7e000 { + label = "storage"; + reg = <0x0007e000 0x00002000>; + }; + + }; +}; diff --git a/boards/silabs/radio_boards/slwrb4170a/slwrb4170a.yaml b/boards/silabs/radio_boards/slwrb4170a/slwrb4170a.yaml new file mode 100644 index 00000000000..754d40f8840 --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4170a/slwrb4170a.yaml @@ -0,0 +1,21 @@ +identifier: slwrb4170a +name: EFR32MG12 2400/868-915 MHz 19 dBm Dual Band Radio Board (SLWRB4170A) +type: mcu +arch: arm +ram: 256 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb +supported: + - counter + - gpio + - nvs + - spi + - uart + - watchdog +testing: + ignore_tags: + - net + - bluetooth +vendor: silabs diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32mg12p432f1024gl125_defconfig b/boards/silabs/radio_boards/slwrb4170a/slwrb4170a_defconfig similarity index 100% rename from boards/silabs/efr32_radio/efr32_radio_efr32mg12p432f1024gl125_defconfig rename to boards/silabs/radio_boards/slwrb4170a/slwrb4170a_defconfig diff --git a/boards/silabs/radio_boards/slwrb4170a/support/openocd.cfg b/boards/silabs/radio_boards/slwrb4170a/support/openocd.cfg new file mode 100644 index 00000000000..38409eb70ad --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4170a/support/openocd.cfg @@ -0,0 +1,25 @@ +if {[info exists env(OPENOCD_INTERFACE)]} { + set INTERFACE $env(OPENOCD_INTERFACE) +} else { + # By default connect over Debug USB port using the J-Link interface + set INTERFACE "jlink" +} + +source [find interface/$INTERFACE.cfg] + +transport select swd + +set CHIPNAME efr32 + +source [find target/efm32.cfg] + +$_TARGETNAME configure -event gdb-attach { + echo "Debugger attaching: halting execution" + reset halt + gdb_breakpoint_override hard +} + +$_TARGETNAME configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} diff --git a/boards/silabs/radio_boards/slwrb4180a/Kconfig.defconfig b/boards/silabs/radio_boards/slwrb4180a/Kconfig.defconfig new file mode 100644 index 00000000000..d02170404ff --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4180a/Kconfig.defconfig @@ -0,0 +1,44 @@ +# EFR32 radio board + +# Copyright (c) 2020 Piotr Mienkowski +# Copyright (c) 2020 TriaGnoSys GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_SLWRB4180A + +config CMU_HFXO_FREQ + default 38400000 + +config CMU_LFXO_FREQ + default 32768 + +config FLASH_BASE_ADDRESS + hex + default 0x0 + +config LOG_BACKEND_SWO_FREQ_HZ + default 875000 + depends on LOG_BACKEND_SWO + +if SOC_GECKO_USE_RAIL + +config FPU + default y + +endif # SOC_GECKO_USE_RAIL + +if BT + +config FPU + default y + +config COMMON_LIBC_MALLOC_ARENA_SIZE + default 8192 + +config MAIN_STACK_SIZE + default 3072 if PM + default 2304 + +endif # BT + +endif # BOARD_SLWRB4180A diff --git a/boards/silabs/radio_boards/slwrb4180a/Kconfig.slwrb4180a b/boards/silabs/radio_boards/slwrb4180a/Kconfig.slwrb4180a new file mode 100644 index 00000000000..2e1e6c0fd3e --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4180a/Kconfig.slwrb4180a @@ -0,0 +1,8 @@ +# EFR32MG21 BRD4180A + +# Copyright (c) 2020 Piotr Mienkowski +# Copyright (c) 2020 TriaGnoSys GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SLWRB4180A + select SOC_PART_NUMBER_EFR32MG21A020F1024IM32 diff --git a/boards/silabs/radio_boards/slwrb4180a/board.cmake b/boards/silabs/radio_boards/slwrb4180a/board.cmake new file mode 100644 index 00000000000..aa7247647d8 --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4180a/board.cmake @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd) +board_runner_args(jlink "--device=EFR32MG21AxxxF1024") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/silabs/radio_boards/slwrb4180a/board.yml b/boards/silabs/radio_boards/slwrb4180a/board.yml new file mode 100644 index 00000000000..c6f825f735a --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4180a/board.yml @@ -0,0 +1,4 @@ +boards: + - name: slwrb4180a + socs: + - name: efr32mg21a020f1024im32 diff --git a/boards/silabs/efr32_radio/doc/efr32mg21-slwrb4180a.jpg b/boards/silabs/radio_boards/slwrb4180a/doc/efr32mg21-slwrb4180a.jpg similarity index 100% rename from boards/silabs/efr32_radio/doc/efr32mg21-slwrb4180a.jpg rename to boards/silabs/radio_boards/slwrb4180a/doc/efr32mg21-slwrb4180a.jpg diff --git a/boards/silabs/radio_boards/slwrb4180a/doc/index.rst b/boards/silabs/radio_boards/slwrb4180a/doc/index.rst new file mode 100644 index 00000000000..057e8ec9b00 --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4180a/doc/index.rst @@ -0,0 +1,156 @@ +.. _slwrb4180a: + +EFR32xG21 2.4 GHz 20 dBm (SLWRB4180A) +##################################### + +Overview +******** + +The EFR32MG21 Mighty Gecko Radio Board is one of the two +radio boards delivered with `EFR32-SLWSTK6006A Website`_. It contains +a Wireless System-On-Chip from the EFR32MG21 family built on an +ARM Cortex®-M33F processor with excellent low power capabilities. + +.. figure:: efr32mg21-slwrb4180a.jpg + :align: center + :alt: SLWRB4180A Mighty Gecko Radio Board + + SLWRB4180A (image courtesy of Silicon Labs) + +The BRD4180A a.k.a. SLWRB4180A radio board plugs into the Wireless Starter Kit +Mainboard BRD4001A and is supported as one of :ref:`silabs_radio_boards`. + +Hardware +******** + +- EFR32MG21A020F1024IM32 Mighty Gecko SoC +- CPU core: ARM Cortex®-M33 with FPU +- Flash memory: 1024 kB +- RAM: 96 kB +- Transmit power: up to +20 dBm +- Operation frequency: 2.4 GHz +- Crystals for LFXO (32.768 kHz) and HFXO (38.4 MHz). + +For more information about the EFR32MG21 SoC and BRD4180A board, refer to these +documents: + +- `EFR32MG21 Website`_ +- `EFR32MG21 Datasheet`_ +- `EFR32xG21 Reference Manual`_ +- `EFR32-SLWSTK6006A Website`_ +- `BRD4180A User Guide`_ + +Supported Features +================== + +The board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtcc | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c port-polling | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are currently not supported by the port. + +Connections and IOs +=================== + +In the following table, the column **Name** contains Pin names. For example, PA2 +means Pin number 2 on PORTA, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Name | Function | Usage | ++=======+=============+=====================================+ +| PB0 | GPIO | LED0 | ++-------+-------------+-------------------------------------+ +| PB1 | GPIO | LED1 | ++-------+-------------+-------------------------------------+ +| PD2 | GPIO | Push Button PB0 | ++-------+-------------+-------------------------------------+ +| PD3 | GPIO | Push Button PB1 | ++-------+-------------+-------------------------------------+ +| PD4 | GPIO | Board Controller Enable | +| | | EFM_BC_EN | ++-------+-------------+-------------------------------------+ +| PA5 | USART1_TX | UART Console EFM_BC_TX US1_TX | ++-------+-------------+-------------------------------------+ +| PA6 | USART1_RX | UART Console EFM_BC_RX US1_RX | ++-------+-------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/radio_boards/slwrb4180a/slwrb4180a_defconfig` + +System Clock +============ + +The EFR32MG21 SoC is configured to use the 38.4 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFR32MG21 SoC has three USARTs. +USART0 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +Flashing +======== + +Connect the BRD4001A board with a mounted BRD4180A radio module to your host +computer using the USB port. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: slwrb4180a + :goals: flash + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you should see the following message in the terminal: + +.. code-block:: console + + Hello World! slwrb4180a + + +.. _EFR32-SLWSTK6006A Website: + https://www.silabs.com/products/development-tools/wireless/efr32xg21-wireless-starter-kit + +.. _BRD4180A User Guide: + https://www.silabs.com/documents/public/user-guides/ug385-brd4180a-user-guide.pdf + +.. _EFR32MG21 Website: + https://www.silabs.com/products/wireless/mesh-networking/efr32mg21-series-2-socs + +.. _EFR32MG21 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efr32mg21-datasheet.pdf + +.. _EFR32xG21 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efr32xg21-rm.pdf diff --git a/boards/silabs/radio_boards/slwrb4180a/pre_dt_board.cmake b/boards/silabs/radio_boards/slwrb4180a/pre_dt_board.cmake new file mode 100644 index 00000000000..beb76b85552 --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4180a/pre_dt_board.cmake @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +# SPI is implemented via usart so node name isn't spi@... +list(APPEND EXTRA_DTC_FLAGS "-Wno-spi_bus_bridge") diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32-pinctrl.dtsi b/boards/silabs/radio_boards/slwrb4180a/slwrb4180a-pinctrl.dtsi similarity index 100% rename from boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32-pinctrl.dtsi rename to boards/silabs/radio_boards/slwrb4180a/slwrb4180a-pinctrl.dtsi diff --git a/boards/silabs/radio_boards/slwrb4180a/slwrb4180a.dts b/boards/silabs/radio_boards/slwrb4180a/slwrb4180a.dts new file mode 100644 index 00000000000..9d761504783 --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4180a/slwrb4180a.dts @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2020 TriaGnoSys GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include "slwrb4180a-pinctrl.dtsi" + +/ { + model = "Silicon Labs BRD4180A (Mighty Gecko 21 Radio Board)"; + compatible = "silabs,slwrb4180a", "silabs,efr32mg21"; + + chosen { + zephyr,console = &usart0; + zephyr,shell-uart = &usart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + led1 = &led1; + sw0 = &button0; + sw1 = &button1; + watchdog0 = &wdog0; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpiob 0 0>; + label = "LED 0"; + }; + led1: led_1 { + gpios = <&gpiob 1 0>; + label = "LED 1"; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + /* gpio flags need validation */ + gpios = <&gpiod 2 GPIO_ACTIVE_LOW>; + label = "User Push Button 0"; + zephyr,code = ; + }; + button1: button_1 { + /* gpio flags need validation */ + gpios = <&gpiod 3 GPIO_ACTIVE_LOW>; + label = "User Push Button 1"; + zephyr,code = ; + }; + }; + +}; + +&cpu0 { + clock-frequency = <38400000>; +}; + +&usart0 { + current-speed = <115200>; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rtcc0 { + prescaler = <1>; + status = "okay"; +}; + +&gpio { + status = "okay"; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; + + board-controller-enable { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&wdog0 { + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 48 kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 0x0000c000>; + read-only; + }; + + /* Reserve 464 kB for the application in slot 0 */ + slot0_partition: partition@c000 { + label = "image-0"; + reg = <0x0000c000 0x00074000>; + }; + + /* Reserve 464 kB for the application in slot 1 */ + slot1_partition: partition@80000 { + label = "image-1"; + reg = <0x00080000 0x00074000>; + }; + + /* Reserve 32 kB for the scratch partition */ + scratch_partition: partition@f4000 { + label = "image-scratch"; + reg = <0x000f4000 0x00008000>; + }; + + /* Set 16Kb of storage at the end of the 1024Kb of flash */ + storage_partition: partition@fc000 { + label = "storage"; + reg = <0x000fc000 0x00004000>; + }; + + }; +}; diff --git a/boards/silabs/radio_boards/slwrb4180a/slwrb4180a.yaml b/boards/silabs/radio_boards/slwrb4180a/slwrb4180a.yaml new file mode 100644 index 00000000000..ae9d5b7f2b8 --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4180a/slwrb4180a.yaml @@ -0,0 +1,21 @@ +identifier: slwrb4180a +name: EFR32xG21 2.4 GHz 20 dBm Radio Board (SLWRB4180A) +type: mcu +arch: arm +ram: 96 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - counter + - gpio + - nvs + - uart + - watchdog +testing: + ignore_tags: + - net + - bluetooth +vendor: silabs diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32_defconfig b/boards/silabs/radio_boards/slwrb4180a/slwrb4180a_defconfig similarity index 100% rename from boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32_defconfig rename to boards/silabs/radio_boards/slwrb4180a/slwrb4180a_defconfig diff --git a/boards/silabs/radio_boards/slwrb4180a/support/openocd.cfg b/boards/silabs/radio_boards/slwrb4180a/support/openocd.cfg new file mode 100644 index 00000000000..38409eb70ad --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4180a/support/openocd.cfg @@ -0,0 +1,25 @@ +if {[info exists env(OPENOCD_INTERFACE)]} { + set INTERFACE $env(OPENOCD_INTERFACE) +} else { + # By default connect over Debug USB port using the J-Link interface + set INTERFACE "jlink" +} + +source [find interface/$INTERFACE.cfg] + +transport select swd + +set CHIPNAME efr32 + +source [find target/efm32.cfg] + +$_TARGETNAME configure -event gdb-attach { + echo "Debugger attaching: halting execution" + reset halt + gdb_breakpoint_override hard +} + +$_TARGETNAME configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} diff --git a/boards/silabs/radio_boards/slwrb4250b/Kconfig.defconfig b/boards/silabs/radio_boards/slwrb4250b/Kconfig.defconfig new file mode 100644 index 00000000000..1fb66afb871 --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4250b/Kconfig.defconfig @@ -0,0 +1,44 @@ +# EFR32 radio board + +# Copyright (c) 2020 Piotr Mienkowski +# Copyright (c) 2020 TriaGnoSys GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_SLWRB4250B + +config CMU_HFXO_FREQ + default 38400000 + +config CMU_LFXO_FREQ + default 32768 + +config FLASH_BASE_ADDRESS + hex + default 0x0 + +config LOG_BACKEND_SWO_FREQ_HZ + default 875000 + depends on LOG_BACKEND_SWO + +if SOC_GECKO_USE_RAIL + +config FPU + default n + +endif # SOC_GECKO_USE_RAIL + +if BT + +config FPU + default y + +config COMMON_LIBC_MALLOC_ARENA_SIZE + default 8192 + +config MAIN_STACK_SIZE + default 3072 if PM + default 2304 + +endif # BT + +endif # BOARD_SLWRB4250B diff --git a/boards/silabs/radio_boards/slwrb4250b/Kconfig.slwrb4250b b/boards/silabs/radio_boards/slwrb4250b/Kconfig.slwrb4250b new file mode 100644 index 00000000000..bab71ba23c9 --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4250b/Kconfig.slwrb4250b @@ -0,0 +1,8 @@ +# EFR32FG1P BRD4250B + +# Copyright (c) 2020 Piotr Mienkowski +# Copyright (c) 2020 TriaGnoSys GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SLWRB4250B + select SOC_PART_NUMBER_EFR32FG1P133F256GM48 diff --git a/boards/silabs/radio_boards/slwrb4250b/board.cmake b/boards/silabs/radio_boards/slwrb4250b/board.cmake new file mode 100644 index 00000000000..a17aad7a895 --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4250b/board.cmake @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd) +board_runner_args(jlink "--device=EFR32FG1PxxxF256") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/silabs/radio_boards/slwrb4250b/board.yml b/boards/silabs/radio_boards/slwrb4250b/board.yml new file mode 100644 index 00000000000..cffd4c63dbb --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4250b/board.yml @@ -0,0 +1,4 @@ +boards: + - name: slwrb4250b + socs: + - name: efr32fg1p133f256gm48 diff --git a/boards/silabs/efr32_radio/doc/efr32fg1-slwrb4250b.jpg b/boards/silabs/radio_boards/slwrb4250b/doc/efr32fg1-slwrb4250b.jpg similarity index 100% rename from boards/silabs/efr32_radio/doc/efr32fg1-slwrb4250b.jpg rename to boards/silabs/radio_boards/slwrb4250b/doc/efr32fg1-slwrb4250b.jpg diff --git a/boards/silabs/radio_boards/slwrb4250b/doc/index.rst b/boards/silabs/radio_boards/slwrb4250b/doc/index.rst new file mode 100644 index 00000000000..7a865b5b573 --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4250b/doc/index.rst @@ -0,0 +1,169 @@ +.. _slwrb4250b: + +EFR32FG1 2400/868 MHz 13 dBm Dual Band (SLWRB4250B) +################################################### + +Overview +******** + +The EFR32FG1 Flex Gecko 2.4 GHz and 868 MHz Radio Board is delivered as part of +`SLWSTK6061B Proprietary Wireless Starter Kit`_. It contains a EFR32FG1 Wireless +SoC built on an ARM Cortex®-M4F processor with excellent low power capabilities. + +.. figure:: efr32fg1-slwrb4250b.jpg + :align: center + :alt: SLWRB4250B Flex Gecko 2.4 GHz and 868 MHz Radio Board + + SLWRB4250B (image courtesy of Silicon Labs) + +The BRD4250B a.k.a. SLWRB4250B radio board plugs into the Wireless Starter Kit +Mainboard BRD4001A and is supported as one of :ref:`silabs_radio_boards`. + +Hardware +******** + +- EFR32FG1P133F256GM48 Flex Gecko SoC +- CPU core: ARM Cortex®-M4 with FPU +- Flash memory: 256 kB +- RAM: 32 kB +- Transmit power: up to +13 dBm +- Operation frequency: 2.4 GHz, 868 MHz +- 8Mbit SPI NOR Flash +- Crystals for LFXO (32.768 kHz) and HFXO (38.4 MHz). + +For more information about the EFR32FG1 SoC and BRD4250B board, refer to these +documents: + +- `EFR32FG1 Website`_ +- `EFR32FG1 Datasheet`_ +- `EFR32xG1 Reference Manual`_ +- `SLWSTK6061B Proprietary Wireless Starter Kit`_ +- `BRD4250B User Guide`_ +- `BRD4250B Reference Manual`_ +- `EFR32FG1-BRD4250B Schematics`_ + +Supported Features +================== + +The board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtcc | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| SPI(M) | on-chip | spi port-polling | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/radio_boards/slwrb4250b/slwrb4250b_defconfig` + +Connections and IOs +=================== + +In the following table, the column **Pin** contains Pin names. For example, PA2 +means Pin number 2 on PORTA, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Pin | Function | Usage | ++=======+=============+=====================================+ +| PF4 | GPIO | LED0 | ++-------+-------------+-------------------------------------+ +| PF5 | GPIO | LED1 | ++-------+-------------+-------------------------------------+ +| PF6 | GPIO | Push Button PB0 | ++-------+-------------+-------------------------------------+ +| PF7 | GPIO | Push Button PB1 | ++-------+-------------+-------------------------------------+ +| PA5 | GPIO | Board Controller Enable VCOM_ENABLE | ++-------+-------------+-------------------------------------+ +| PA0 | USART0_TX | UART Console VCOM_TX US0_TX #0 | ++-------+-------------+-------------------------------------+ +| PA1 | USART0_RX | UART Console VCOM_RX US0_RX #0 | ++-------+-------------+-------------------------------------+ +| PC6 | SPI_MOSI | Flash MOSI US1_TX #11 | ++-------+-------------+-------------------------------------+ +| PC7 | SPI_MISO | Flash MISO US1_RX #11 | ++-------+-------------+-------------------------------------+ +| PC8 | SPI_SCLK | Flash SCLK US1_CLK #11 | ++-------+-------------+-------------------------------------+ +| PA4 | SPI_CS | Flash Chip Select (GPIO) | ++-------+-------------+-------------------------------------+ + +System Clock +============ + +The EFR32FG1P SoC is configured to use the 38.4 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFR32FG1P SoC has two USARTs and one Low Energy UARTs (LEUART). +USART0 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +Flashing +======== + +Connect the BRD4001A board with a mounted BRD4250B radio module to your host +computer using the USB port. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: slwrb4250b + :goals: flash + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you should see the following message in the terminal: + +.. code-block:: console + + Hello World! slwrb4250b + + +.. _EFR32FG1 Website: + https://www.silabs.com/wireless/proprietary/efr32fg1-series-1-sub-ghz-2-4-ghz-socs + +.. _EFR32FG1 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efr32fg1-datasheet.pdf + +.. _EFR32xG1 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efr32xg1-rm.pdf + +.. _SLWSTK6061B Proprietary Wireless Starter Kit: + https://www.silabs.com/products/development-tools/wireless/proprietary/slwstk6061b-efr32-flex-gecko-868-mhz-2-4-ghz-and-sub-ghz-starter-kit + +.. _BRD4250B User Guide: + https://www.silabs.com/documents/public/user-guides/ug182-brd4250b-user-guide.pdf + +.. _BRD4250B Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/brd4250b-rm.pdf + +.. _EFR32FG1-BRD4250B Schematics: + https://www.silabs.com/documents/public/schematic-files/BRD4250B-B02-schematic.pdf diff --git a/boards/silabs/radio_boards/slwrb4250b/pre_dt_board.cmake b/boards/silabs/radio_boards/slwrb4250b/pre_dt_board.cmake new file mode 100644 index 00000000000..beb76b85552 --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4250b/pre_dt_board.cmake @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +# SPI is implemented via usart so node name isn't spi@... +list(APPEND EXTRA_DTC_FLAGS "-Wno-spi_bus_bridge") diff --git a/boards/silabs/radio_boards/slwrb4250b/slwrb4250b.dts b/boards/silabs/radio_boards/slwrb4250b/slwrb4250b.dts new file mode 100644 index 00000000000..7ca9e7388ce --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4250b/slwrb4250b.dts @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2020 Piotr Mienkowski + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include "../common/efr32-series1-common.dtsi" + +/ { + model = "Silicon Labs BRD4250B (Flex Gecko 1 Radio Board)"; + compatible = "silabs,slwrb4250b", "silabs,efr32fg1p"; + + pwmleds { + compatible = "pwm-leds"; + status = "okay"; + pwm_led0: pwm_led0 { + pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + }; + }; + + aliases { + pwm-led0 = &pwm_led0; + }; +}; + +&cpu0 { + clock-frequency = <38400000>; +}; + +&timer0 { + status = "okay"; + + pwm0: pwm { + status = "okay"; + pin-location = ; + prescaler = <1024>; + }; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 32 kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 0x00008000>; + read-only; + }; + + /* Reserve 94 kB for the application in slot 0 */ + slot0_partition: partition@8000 { + label = "image-0"; + reg = <0x00008000 0x00017800>; + }; + + /* Reserve 94 kB for the application in slot 1 */ + slot1_partition: partition@1f800 { + label = "image-1"; + reg = <0x0001f800 0x00017800>; + }; + + /* Reserve 30 kB for the scratch partition */ + scratch_partition: partition@37000 { + label = "image-scratch"; + reg = <0x00037000 0x00007800>; + }; + + /* Set 6Kb of storage at the end of the 256Kb of flash */ + storage_partition: partition@3e800 { + label = "storage"; + reg = <0x0003e800 0x00001800>; + }; + + }; +}; + +&usart0 { + current-speed = <115200>; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/silabs/radio_boards/slwrb4250b/slwrb4250b.yaml b/boards/silabs/radio_boards/slwrb4250b/slwrb4250b.yaml new file mode 100644 index 00000000000..8f54bc21752 --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4250b/slwrb4250b.yaml @@ -0,0 +1,22 @@ +identifier: slwrb4250b +name: EFR32FG 2400/868 MHz 13 dBm Dual Band Radio Board (SLWRB4250B) +type: mcu +arch: arm +ram: 32 +flash: 256 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - counter + - gpio + - nvs + - spi + - uart + - watchdog +testing: + ignore_tags: + - net + - bluetooth +vendor: silabs diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32mg12p433f1024gm68_defconfig b/boards/silabs/radio_boards/slwrb4250b/slwrb4250b_defconfig similarity index 100% rename from boards/silabs/efr32_radio/efr32_radio_efr32mg12p433f1024gm68_defconfig rename to boards/silabs/radio_boards/slwrb4250b/slwrb4250b_defconfig diff --git a/boards/silabs/radio_boards/slwrb4250b/support/openocd.cfg b/boards/silabs/radio_boards/slwrb4250b/support/openocd.cfg new file mode 100644 index 00000000000..38409eb70ad --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4250b/support/openocd.cfg @@ -0,0 +1,25 @@ +if {[info exists env(OPENOCD_INTERFACE)]} { + set INTERFACE $env(OPENOCD_INTERFACE) +} else { + # By default connect over Debug USB port using the J-Link interface + set INTERFACE "jlink" +} + +source [find interface/$INTERFACE.cfg] + +transport select swd + +set CHIPNAME efr32 + +source [find target/efm32.cfg] + +$_TARGETNAME configure -event gdb-attach { + echo "Debugger attaching: halting execution" + reset halt + gdb_breakpoint_override hard +} + +$_TARGETNAME configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} diff --git a/boards/silabs/radio_boards/slwrb4255a/Kconfig.defconfig b/boards/silabs/radio_boards/slwrb4255a/Kconfig.defconfig new file mode 100644 index 00000000000..70528d489b4 --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4255a/Kconfig.defconfig @@ -0,0 +1,44 @@ +# EFR32 radio board + +# Copyright (c) 2020 Piotr Mienkowski +# Copyright (c) 2020 TriaGnoSys GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_SLWRB4255A + +config CMU_HFXO_FREQ + default 38400000 + +config CMU_LFXO_FREQ + default 32768 + +config FLASH_BASE_ADDRESS + hex + default 0x0 + +config LOG_BACKEND_SWO_FREQ_HZ + default 875000 + depends on LOG_BACKEND_SWO + +if SOC_GECKO_USE_RAIL + +config FPU + default n + +endif # SOC_GECKO_USE_RAIL + +if BT + +config FPU + default y + +config COMMON_LIBC_MALLOC_ARENA_SIZE + default 8192 + +config MAIN_STACK_SIZE + default 3072 if PM + default 2304 + +endif # BT + +endif # BOARD_SLWRB4255A diff --git a/boards/silabs/radio_boards/slwrb4255a/Kconfig.slwrb4255a b/boards/silabs/radio_boards/slwrb4255a/Kconfig.slwrb4255a new file mode 100644 index 00000000000..6f95623eb75 --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4255a/Kconfig.slwrb4255a @@ -0,0 +1,8 @@ +# EFR32FG13P BRD4255A board + +# Copyright (c) 2020 Piotr Mienkowski +# Copyright (c) 2020 TriaGnoSys GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SLWRB4255A + select SOC_PART_NUMBER_EFR32FG13P233F512GM48 diff --git a/boards/silabs/radio_boards/slwrb4255a/board.cmake b/boards/silabs/radio_boards/slwrb4255a/board.cmake new file mode 100644 index 00000000000..7e93e543d55 --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4255a/board.cmake @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd) +board_runner_args(jlink "--device=EFR32FG13PxxxF512") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/silabs/radio_boards/slwrb4255a/board.yml b/boards/silabs/radio_boards/slwrb4255a/board.yml new file mode 100644 index 00000000000..4b76604b170 --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4255a/board.yml @@ -0,0 +1,4 @@ +boards: + - name: slwrb4255a + socs: + - name: efr32fg13p233f512gm48 diff --git a/boards/silabs/efr32_radio/doc/efr32fg13-slwrb4255a.jpg b/boards/silabs/radio_boards/slwrb4255a/doc/efr32fg13-slwrb4255a.jpg similarity index 100% rename from boards/silabs/efr32_radio/doc/efr32fg13-slwrb4255a.jpg rename to boards/silabs/radio_boards/slwrb4255a/doc/efr32fg13-slwrb4255a.jpg diff --git a/boards/silabs/radio_boards/slwrb4255a/doc/index.rst b/boards/silabs/radio_boards/slwrb4255a/doc/index.rst new file mode 100644 index 00000000000..43dd6e65aad --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4255a/doc/index.rst @@ -0,0 +1,159 @@ +.. _slwrb4255a: + +EFR32FG13 2400/915 MHz 19 dBm Dual Band (SLWRB4255A) +#################################################### + +Overview +******** + +The EFR32FG13P Flex Gecko 2.4 GHz and 915 MHz Radio Board is delivered as a +`standalone Proprietary Wireless radio board`_. It contains a EFR32FG13P Wireless +SoC built on an ARM Cortex®-M4F processor with excellent low power capabilities. + +.. figure:: efr32fg13-slwrb4255a.jpg + :align: center + :alt: SLWRB4255A Flex Gecko 2.4 GHz and 915 MHz Radio Board + + SLWRB4255A (image courtesy of Silicon Labs) + +The BRD4255A a.k.a. SLWRB4255A radio board plugs into the Wireless Starter Kit +Mainboard BRD4001A and is supported as one of :ref:`silabs_radio_boards`. + +Hardware +******** + +- EFR32FG13P233F512GM48 Flex Gecko SoC +- CPU core: ARM Cortex®-M4 with FPU +- Flash memory: 512 kB +- RAM: 64 kB +- Transmit power: up to 19 dBm +- Operation frequency: 2.4 GHz, 915 MHz +- Crystals for LFXO (32.768 kHz) and HFXO (38.4 MHz). + +For more information about the EFR32FG13 SoC and BRD4255A board, refer to these +documents: + +- `EFR32FG13 Website`_ +- `EFR32FG13 Datasheet`_ +- `EFR32xG13 Reference Manual`_ +- `BRD4255A Reference Manual`_ + +Supported Features +================== + +The board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtcc | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| SPI(M) | on-chip | spi port-polling | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/radio_boards/slwrb4255/slwrb4255_defconfig` + +Connections and IOs +=================== + +In the following table, the column **Pin** contains Pin names. For example, PA2 +means Pin number 2 on PORTA, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Pin | Function | Usage | ++=======+=============+=====================================+ +| PF4 | GPIO | LED0 | ++-------+-------------+-------------------------------------+ +| PF5 | GPIO | LED1 | ++-------+-------------+-------------------------------------+ +| PF6 | GPIO | Push Button PB0 | ++-------+-------------+-------------------------------------+ +| PF7 | GPIO | Push Button PB1 | ++-------+-------------+-------------------------------------+ +| PA5 | GPIO | Board Controller Enable VCOM_ENABLE | ++-------+-------------+-------------------------------------+ +| PA0 | USART0_TX | UART Console VCOM_TX US0_TX #0 | ++-------+-------------+-------------------------------------+ +| PA1 | USART0_RX | UART Console VCOM_RX US0_RX #0 | ++-------+-------------+-------------------------------------+ +| PC6 | SPI_MOSI | Flash MOSI US1_TX #11 | ++-------+-------------+-------------------------------------+ +| PC7 | SPI_MISO | Flash MISO US1_RX #11 | ++-------+-------------+-------------------------------------+ +| PC8 | SPI_SCLK | Flash SCLK US1_CLK #11 | ++-------+-------------+-------------------------------------+ +| PA4 | SPI_CS | Flash Chip Select (GPIO) | ++-------+-------------+-------------------------------------+ + +System Clock +============ + +The EFR32FG13P SoC is configured to use the 38.4 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFR32FG13P SoC has three USARTs and one Low Energy UARTs (LEUART). +USART0 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +Flashing +======== + +Connect the BRD4001A board with a mounted BRD4255A radio module to your host +computer using the USB port. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: slwrb4255a + :goals: flash + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you should see the following message in the terminal: + +.. code-block:: console + + Hello World! slwrb4255a + + +.. _EFR32FG13 Website: + https://www.silabs.com/wireless/proprietary/efr32fg13-series-1-sub-ghz-2-4-ghz-socs + +.. _EFR32FG13 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efr32fg13-datasheet.pdf + +.. _EFR32xG13 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efr32xg13-rm.pdf + +.. _standalone Proprietary Wireless radio board: + https://www.silabs.com/development-tools/wireless/proprietary/slwrb4255a-efr32fg13-915-mhz-radio-board + +.. _BRD4255A Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/brd4255a-rm.pdf diff --git a/boards/silabs/radio_boards/slwrb4255a/pre_dt_board.cmake b/boards/silabs/radio_boards/slwrb4255a/pre_dt_board.cmake new file mode 100644 index 00000000000..beb76b85552 --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4255a/pre_dt_board.cmake @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +# SPI is implemented via usart so node name isn't spi@... +list(APPEND EXTRA_DTC_FLAGS "-Wno-spi_bus_bridge") diff --git a/boards/silabs/radio_boards/slwrb4255a/slwrb4255a.dts b/boards/silabs/radio_boards/slwrb4255a/slwrb4255a.dts new file mode 100644 index 00000000000..299a3c85263 --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4255a/slwrb4255a.dts @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2020 Piotr Mienkowski + * Copyright (c) 2021 Yonatan Schachter + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include "../common/efr32-series1-common.dtsi" + +/ { + model = "Silicon Labs BRD4255A (Flex Gecko Radio Board)"; + compatible = "silabs,slwrb4255a", "silabs,efr32fg13p"; +}; + +&cpu0 { + clock-frequency = <38400000>; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 32 kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 0x00008000>; + read-only; + }; + + /* Reserve 220 kB for the application in slot 0 */ + slot0_partition: partition@8000 { + label = "image-0"; + reg = <0x00008000 0x00037000>; + }; + + /* Reserve 220 kB for the application in slot 1 */ + slot1_partition: partition@3f000 { + label = "image-1"; + reg = <0x0003f000 0x00037000>; + }; + + /* Reserve 32 kB for the scratch partition */ + scratch_partition: partition@76000 { + label = "image-scratch"; + reg = <0x00076000 0x00008000>; + }; + + /* Set 8Kb of storage at the end of the 512KB of flash */ + storage_partition: partition@7e000 { + label = "storage"; + reg = <0x0007e000 0x00002000>; + }; + + }; +}; + +&usart0 { + current-speed = <115200>; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/silabs/radio_boards/slwrb4255a/slwrb4255a.yaml b/boards/silabs/radio_boards/slwrb4255a/slwrb4255a.yaml new file mode 100644 index 00000000000..e1d6718fbce --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4255a/slwrb4255a.yaml @@ -0,0 +1,22 @@ +identifier: slwrb4255a +name: EFR32FG13 2400/915 MHz 19 dBm Dual Band Radio Board (SLWRB4255A) +type: mcu +arch: arm +ram: 64 +flash: 512 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - counter + - gpio + - nvs + - spi + - uart + - watchdog +testing: + ignore_tags: + - net + - bluetooth +vendor: silabs diff --git a/boards/silabs/efr32mg_sltb004a/efr32mg_sltb004a_defconfig b/boards/silabs/radio_boards/slwrb4255a/slwrb4255a_defconfig similarity index 100% rename from boards/silabs/efr32mg_sltb004a/efr32mg_sltb004a_defconfig rename to boards/silabs/radio_boards/slwrb4255a/slwrb4255a_defconfig diff --git a/boards/silabs/radio_boards/slwrb4255a/support/openocd.cfg b/boards/silabs/radio_boards/slwrb4255a/support/openocd.cfg new file mode 100644 index 00000000000..38409eb70ad --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4255a/support/openocd.cfg @@ -0,0 +1,25 @@ +if {[info exists env(OPENOCD_INTERFACE)]} { + set INTERFACE $env(OPENOCD_INTERFACE) +} else { + # By default connect over Debug USB port using the J-Link interface + set INTERFACE "jlink" +} + +source [find interface/$INTERFACE.cfg] + +transport select swd + +set CHIPNAME efr32 + +source [find target/efm32.cfg] + +$_TARGETNAME configure -event gdb-attach { + echo "Debugger attaching: halting execution" + reset halt + gdb_breakpoint_override hard +} + +$_TARGETNAME configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} diff --git a/boards/silabs/efm32gg_slwstk6121a/CMakeLists.txt b/boards/silabs/radio_boards/slwrb4321a/CMakeLists.txt similarity index 100% rename from boards/silabs/efm32gg_slwstk6121a/CMakeLists.txt rename to boards/silabs/radio_boards/slwrb4321a/CMakeLists.txt diff --git a/boards/silabs/radio_boards/slwrb4321a/Kconfig.defconfig b/boards/silabs/radio_boards/slwrb4321a/Kconfig.defconfig new file mode 100644 index 00000000000..63ff16bbad6 --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4321a/Kconfig.defconfig @@ -0,0 +1,29 @@ +# EFM32GG SLWSTK6121A default board configuration +# Copyright (c) 2019 Interay Solutions B.V. +# Copyright (c) 2019 Oane Kingma +# Copyright (c) 2020 Thorvald Natvig +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_SLWRB4321A + +config CMU_HFXO_FREQ + default 50000000 + +config CMU_HFRCO_FREQ + default 72000000 + +config CMU_LFXO_FREQ + default 32768 + +config LOG_BACKEND_SWO_FREQ_HZ + default 875000 + depends on LOG_BACKEND_SWO + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_SLWRB4321A diff --git a/boards/silabs/radio_boards/slwrb4321a/Kconfig.slwrb4321a b/boards/silabs/radio_boards/slwrb4321a/Kconfig.slwrb4321a new file mode 100644 index 00000000000..1ce37ed6446 --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4321a/Kconfig.slwrb4321a @@ -0,0 +1,8 @@ +# EFM32GG11 SLWRB4321A board configuration +# Copyright (c) 2019 Interay Solutions B.V. +# Copyright (c) 2019 Oane Kingma +# Copyright (c) 2020 Thorvald Natvig +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SLWRB4321A + select SOC_PART_NUMBER_EFM32GG11B820F2048GM64 diff --git a/boards/silabs/efm32gg_slwstk6121a/board.c b/boards/silabs/radio_boards/slwrb4321a/board.c similarity index 100% rename from boards/silabs/efm32gg_slwstk6121a/board.c rename to boards/silabs/radio_boards/slwrb4321a/board.c diff --git a/boards/silabs/efm32gg_slwstk6121a/board.cmake b/boards/silabs/radio_boards/slwrb4321a/board.cmake similarity index 100% rename from boards/silabs/efm32gg_slwstk6121a/board.cmake rename to boards/silabs/radio_boards/slwrb4321a/board.cmake diff --git a/boards/silabs/efm32gg_slwstk6121a/board.h b/boards/silabs/radio_boards/slwrb4321a/board.h similarity index 100% rename from boards/silabs/efm32gg_slwstk6121a/board.h rename to boards/silabs/radio_boards/slwrb4321a/board.h diff --git a/boards/silabs/radio_boards/slwrb4321a/board.yml b/boards/silabs/radio_boards/slwrb4321a/board.yml new file mode 100644 index 00000000000..a86f5c2d620 --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4321a/board.yml @@ -0,0 +1,5 @@ +board: + name: slwrb4321a + vendor: silabs + socs: + - name: efm32gg11b820f2048gm64 diff --git a/boards/silabs/radio_boards/slwrb4321a/doc/index.rst b/boards/silabs/radio_boards/slwrb4321a/doc/index.rst new file mode 100644 index 00000000000..50ec07b7f79 --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4321a/doc/index.rst @@ -0,0 +1,186 @@ +.. _slwrb4321a: + +WGM160P Wi-Fi Module (SLWRB4321A) +################################# + +Overview +******** + +The WGM160P Starter Kit SLWSTK6121A comes with the BRD4321A radio board. +This radio boards contains a WGM160P module, which combines the WF200 Wi-Fi +transceiver with an EFM32GG11 microcontroller. + +.. figure:: wgm160p-starter-kit.jpg + :align: center + :alt: SLWSTK6121A + + SLWSTK6121A (image courtesy of Silicon Labs) + +Hardware +******** + +- Advanced Energy Monitoring provides real-time information about the energy + consumption of an application or prototype design. +- Ultra low power 128x128 pixel color Memory-LCD +- 2 user buttons and 2 LEDs +- Si7021 Humidity and Temperature Sensor +- On-board Segger J-Link USB and Ethernet debugger +- 10/100Base-TX ethernet PHY and RJ-45 jack (on included expansion board) +- MicroSD card slot +- USB Micro-AB connector + +For more information about the WGM160P and SLWSTK6121A board: + +- `WGM160P Website`_ +- `WGM160P Datasheet`_ +- `SLWSTK6121A Website`_ +- `SLWSTK6121A User Guide`_ +- `EFM32GG11 Datasheet`_ +- `EFM32GG11 Reference Manual`_ +- `WF200 Datasheet`_ + +Supported Features +================== + +The slwrb4321a board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtcc | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c port-polling | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/slwrb4321a/slwrb4321a_defconfig` + +Other hardware features, including the WF200 WiFi transceiver, are +currently not supported by the port. + +Connections and IOs +=================== + +The WGM160P's EFM32GG11 SoC has six GPIO controllers (PORTA to PORTF), all of which are +currently enabled for the SLWSTK6121A board. + +In the following table, the column **Name** contains pin names. For example, PE1 +means pin number 1 on PORTE, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Name | Function | Usage | ++=======+=============+=====================================+ +| PA4 | GPIO | LED0 | ++-------+-------------+-------------------------------------+ +| PA5 | GPIO | LED1 | ++-------+-------------+-------------------------------------+ +| PD6 | GPIO | Push Button PB0 | ++-------+-------------+-------------------------------------+ +| PD8 | GPIO | Push Button PB1 | ++-------+-------------+-------------------------------------+ +| PE7 | UART_TX | UART TX Console VCOM_TX US0_TX #1 | ++-------+-------------+-------------------------------------+ +| PE6 | UART_RX | UART RX Console VCOM_RX US0_RX #1 | ++-------+-------------+-------------------------------------+ +| PB11 | I2C_SDA | SENSOR_I2C_SDA I2C1_SDA #1 | ++-------+-------------+-------------------------------------+ +| PB12 | I2C_SCL | SENSOR_I2C_SCL I2C1_SCL #1 | ++-------+-------------+-------------------------------------+ + + +System Clock +============ + +The EFM32GG11 SoC is configured to use the 50 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFM32GG11 SoC has four USARTs, two UARTs and two Low Energy UARTs (LEUART). +USART0 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +.. note:: + Before using the kit the first time, you should update the J-Link firmware + from `J-Link-Downloads`_ + +Flashing +======== + +The SLWSTK6121A includes an `J-Link`_ serial and debug adaptor built into the +board. The adaptor provides: + +- A USB connection to the host computer +- A physical UART connection which is relayed over interface USB serial port. + +Flashing an application to SLWSTK6121A +-------------------------------------- + +Connect the SLWSTK6121A to your host computer using the USB port. + +Here is an example to build and flash the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: slwrb4321a + :goals: flash + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you'll see the following message on the corresponding serial port +terminal session: + +.. code-block:: console + + Hello World! slwrb4321a + +.. _WGM160P Website: + https://www.silabs.com/wireless/wi-fi/wfm160-series-1-modules + +.. _WGM160P Datasheet: + https://www.silabs.com/documents/public/data-sheets/wgm160p-datasheet.pdf + +.. _SLWSTK6121A Website: + https://www.silabs.com/development-tools/wireless/wi-fi/wgm160p-wifi-module-starter-kit + +.. _SLWSTK6121A User Guide: + https://www.silabs.com/documents/public/user-guides/ug351-brd4321a-user-guide.pdf + +.. _EFM32GG11 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efm32gg11-datasheet.pdf + +.. _EFM32GG11 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efm32gg11-rm.pdf + +.. _WF200 Datasheet: + https://www.silabs.com/documents/public/data-sheets/wf200-datasheet.pdf + +.. _J-Link: + https://www.segger.com/jlink-debug-probes.html + +.. _J-Link-Downloads: + https://www.segger.com/downloads/jlink diff --git a/boards/silabs/efm32gg_slwstk6121a/doc/wgm160p-starter-kit.jpg b/boards/silabs/radio_boards/slwrb4321a/doc/wgm160p-starter-kit.jpg similarity index 100% rename from boards/silabs/efm32gg_slwstk6121a/doc/wgm160p-starter-kit.jpg rename to boards/silabs/radio_boards/slwrb4321a/doc/wgm160p-starter-kit.jpg diff --git a/boards/silabs/efm32gg_slwstk6121a/efm32gg_slwstk6121a-pinctrl.dtsi b/boards/silabs/radio_boards/slwrb4321a/slwrb4321a-pinctrl.dtsi similarity index 100% rename from boards/silabs/efm32gg_slwstk6121a/efm32gg_slwstk6121a-pinctrl.dtsi rename to boards/silabs/radio_boards/slwrb4321a/slwrb4321a-pinctrl.dtsi diff --git a/boards/silabs/radio_boards/slwrb4321a/slwrb4321a.dts b/boards/silabs/radio_boards/slwrb4321a/slwrb4321a.dts new file mode 100644 index 00000000000..4dfff28a2dc --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4321a/slwrb4321a.dts @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2019 Interay Solutions B.V. + * Copyright (c) 2019 Oane Kingma + * Copyright (c) 2020 Thorvald Natvig + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include "slwrb4321a-pinctrl.dtsi" + +/ { + model = "Silicon Labs EFM32GG SLWSTK6121A board"; + compatible = "silabs,slwrb4321a", "silabs,efm32gg11b"; + + chosen { + zephyr,console = &usart0; + zephyr,shell-uart = &usart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + led1 = &led1; + sw0 = &button0; + sw1 = &button1; + watchdog0 = &wdog0; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpioa 4 0>; + label = "LED 0"; + }; + led1: led_1 { + gpios = <&gpioa 5 0>; + label = "LED 1"; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + /* gpio flags need validation */ + gpios = <&gpiod 6 GPIO_ACTIVE_LOW>; + label = "User Push Button 0"; + zephyr,code = ; + }; + button1: button_1 { + /* gpio flags need validation */ + gpios = <&gpiod 8 GPIO_ACTIVE_LOW>; + label = "User Push Button 1"; + zephyr,code = ; + }; + }; +}; + +/* Connected to the WSTK VCOM */ +&usart0 { + current-speed = <115200>; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* i2c unit 0 is not used on the board, but must be defined for i2c unit 1 + * to work properly. + */ +&i2c0 { + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* Connected to Si7021 sensor on WSTK */ +&i2c1 { + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rtcc0 { + prescaler = <1>; + status = "okay"; +}; + +&gpio { + location-swo = <0>; + status = "okay"; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&gpioe { + status = "okay"; +}; + +&gpiof { + status = "okay"; +}; + +ð0 { + /* PHY address = 0 */ + phy-address = <0>; + + /* PHY management pins */ + location-mdio = ; + location-phy_mdc = ; + location-phy_mdio = ; + + /* RMII interface pins */ + location-rmii = ; + location-rmii_refclk = ; + location-rmii_crs_dv = ; + location-rmii_txd0 = ; + location-rmii_txd1 = ; + location-rmii_tx_en = ; + location-rmii_rxd0 = ; + location-rmii_rxd1 = ; + location-rmii_rx_er = ; + + status = "okay"; +}; + +&flash0 { + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Set 12Kb of storage at the end of the 2048Kb of flash */ + storage_partition: partition@1fd000 { + label = "storage"; + reg = <0x001fd000 0x00003000>; + }; + }; +}; + +&wdog0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&cpu0 { + clock-frequency = <72000000>; +}; diff --git a/boards/silabs/radio_boards/slwrb4321a/slwrb4321a.yaml b/boards/silabs/radio_boards/slwrb4321a/slwrb4321a.yaml new file mode 100644 index 00000000000..7b61761886f --- /dev/null +++ b/boards/silabs/radio_boards/slwrb4321a/slwrb4321a.yaml @@ -0,0 +1,21 @@ +identifier: slwrb4321a +name: WGM160P Wi-Fi Module Radio Board (SLWRB4321A) +type: mcu +arch: arm +ram: 512 +flash: 2048 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - counter + - i2c + - gpio + - netif:eth + - nvs + - uart +testing: + ignore_tags: + - bluetooth +vendor: silabs diff --git a/boards/silabs/efm32gg_slwstk6121a/efm32gg_slwstk6121a_defconfig b/boards/silabs/radio_boards/slwrb4321a/slwrb4321a_defconfig similarity index 100% rename from boards/silabs/efm32gg_slwstk6121a/efm32gg_slwstk6121a_defconfig rename to boards/silabs/radio_boards/slwrb4321a/slwrb4321a_defconfig diff --git a/boards/silabs/efm32gg_slwstk6121a/support/openocd.cfg b/boards/silabs/radio_boards/slwrb4321a/support/openocd.cfg similarity index 100% rename from boards/silabs/efm32gg_slwstk6121a/support/openocd.cfg rename to boards/silabs/radio_boards/slwrb4321a/support/openocd.cfg diff --git a/boards/silabs/radio_boards/xg24_rb4187c/Kconfig.defconfig b/boards/silabs/radio_boards/xg24_rb4187c/Kconfig.defconfig new file mode 100644 index 00000000000..05899cfebc2 --- /dev/null +++ b/boards/silabs/radio_boards/xg24_rb4187c/Kconfig.defconfig @@ -0,0 +1,44 @@ +# EFR32 radio board + +# Copyright (c) 2020 Piotr Mienkowski +# Copyright (c) 2020 TriaGnoSys GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_XG24_RB4187C + +config CMU_HFXO_FREQ + default 39000000 + +config CMU_LFXO_FREQ + default 32768 + +config FLASH_BASE_ADDRESS + hex + default 0x08000000 + +config LOG_BACKEND_SWO_FREQ_HZ + default 875000 + depends on LOG_BACKEND_SWO + +if SOC_GECKO_USE_RAIL + +config FPU + default y + +endif # SOC_GECKO_USE_RAIL + +if BT + +config FPU + default y + +config COMMON_LIBC_MALLOC_ARENA_SIZE + default 8192 + +config MAIN_STACK_SIZE + default 3072 if PM + default 2304 + +endif # BT + +endif # BOARD_XG24_RB4187C diff --git a/boards/silabs/radio_boards/xg24_rb4187c/Kconfig.xg24_rb4187c b/boards/silabs/radio_boards/xg24_rb4187c/Kconfig.xg24_rb4187c new file mode 100644 index 00000000000..7d51709ba49 --- /dev/null +++ b/boards/silabs/radio_boards/xg24_rb4187c/Kconfig.xg24_rb4187c @@ -0,0 +1,8 @@ +# EFR32MG24 BRD4187C + +# Copyright (c) 2020 Piotr Mienkowski +# Copyright (c) 2020 TriaGnoSys GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_XG24_RB4187C + select SOC_PART_NUMBER_EFR32MG24B220F1536IM48 diff --git a/boards/silabs/radio_boards/xg24_rb4187c/board.cmake b/boards/silabs/radio_boards/xg24_rb4187c/board.cmake new file mode 100644 index 00000000000..a6187e28f0f --- /dev/null +++ b/boards/silabs/radio_boards/xg24_rb4187c/board.cmake @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd) +board_runner_args(jlink "--device=EFR32MG24BxxxF1536") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/silabs/radio_boards/xg24_rb4187c/board.yml b/boards/silabs/radio_boards/xg24_rb4187c/board.yml new file mode 100644 index 00000000000..09a4d074370 --- /dev/null +++ b/boards/silabs/radio_boards/xg24_rb4187c/board.yml @@ -0,0 +1,4 @@ +boards: + - name: xg24_rb4187c + socs: + - name: efr32mg24b220f1536im48 diff --git a/boards/silabs/efr32_radio/doc/efr32mg24-xg24-rb4187c.jpg b/boards/silabs/radio_boards/xg24_rb4187c/doc/efr32mg24-xg24-rb4187c.jpg similarity index 100% rename from boards/silabs/efr32_radio/doc/efr32mg24-xg24-rb4187c.jpg rename to boards/silabs/radio_boards/xg24_rb4187c/doc/efr32mg24-xg24-rb4187c.jpg diff --git a/boards/silabs/radio_boards/xg24_rb4187c/doc/index.rst b/boards/silabs/radio_boards/xg24_rb4187c/doc/index.rst new file mode 100644 index 00000000000..82da55861ce --- /dev/null +++ b/boards/silabs/radio_boards/xg24_rb4187c/doc/index.rst @@ -0,0 +1,157 @@ +.. _xg24_rb4187c: + +EFR32xG24 2.4 GHz 20 dBm (xG24-RB4187C) +####################################### + +Overview +******** + +The EFR32MG24 Mighty Gecko Radio Board is one of the two +radio boards delivered with `xG24-PK6010A Website`_. It contains +a Wireless System-On-Chip from the EFR32MG24 family built on an +ARM Cortex®-M33F processor with excellent low power capabilities. + +.. figure:: efr32mg24-xg24-rb4187c.jpg + :align: center + :alt: xG24-RB4187C Mighty Gecko Radio Board + + xG24-RB4187C (image courtesy of Silicon Labs) + +The BRD4187C a.k.a. xG24-RB4187C radio board plugs into the Wireless Pro Kit +Mainboard BRD4002A and is supported as one of :ref:`silabs_radio_boards`. + +Hardware +******** + +- EFR32MG24B220F1536IM48 Mighty Gecko SoC +- CPU core: ARM Cortex®-M33 with FPU +- Flash memory: 1536 kB +- RAM: 256 kB +- Transmit power: up to +20 dBm +- Operation frequency: 2.4 GHz +- Crystals for LFXO (32.768 kHz) and HFXO (39 MHz). + +For more information about the EFR32MG24 SoC and BRD4187C board, refer to these +documents: + +- `EFR32MG24 Website`_ +- `EFR32MG24 Datasheet`_ +- `EFR32xG24 Reference Manual`_ +- `xG24-PK6010A Website`_ +- `BRD4187C User Guide`_ + +Supported Features +================== + +The board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | stimer | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | semailbox | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are currently not supported by the port. + +Connections and IOs +=================== + +In the following table, the column **Name** contains Pin names. For example, PA2 +means Pin number 2 on PORTA, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Name | Function | Usage | ++=======+=============+=====================================+ +| PB2 | GPIO | LED0 | ++-------+-------------+-------------------------------------+ +| PB4 | GPIO | LED1 | ++-------+-------------+-------------------------------------+ +| PB1 | GPIO | Push Button 0 | ++-------+-------------+-------------------------------------+ +| PB3 | GPIO | Push Button 1 | ++-------+-------------+-------------------------------------+ +| PB0 | GPIO | Board Controller Enable | +| | | VCOM_ENABLE | ++-------+-------------+-------------------------------------+ +| PA8 | USART0_TX | UART Console VCOM_TX US0_TX | ++-------+-------------+-------------------------------------+ +| PA9 | USART0_RX | UART Console VCOM_RX US0_RX | ++-------+-------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c_defconfig` + +System Clock +============ + +The EFR32MG24 SoC is configured to use the 39 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFR32MG24 SoC has one USART and two EUSARTs. +USART0 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +Flashing +======== + +Connect the BRD4002A board with a mounted BRD4187C radio module to your host +computer using the USB port. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xg24_rb4187c + :goals: flash + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you should see the following message in the terminal: + +.. code-block:: console + + Hello World! xg24_rb4187c + + +.. _xG24-PK6010A Website: + https://www.silabs.com/development-tools/wireless/efr32xg24-pro-kit-20-dbm + +.. _BRD4187C User Guide: + https://www.silabs.com/documents/public/user-guides/ug526-brd4187c-user-guide.pdf + +.. _EFR32MG24 Website: + https://www.silabs.com/wireless/zigbee/efr32mg24-series-2-socs + +.. _EFR32MG24 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efr32mg24-datasheet.pdf + +.. _EFR32xG24 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/brd4187c-rm.pdf diff --git a/boards/silabs/radio_boards/xg24_rb4187c/pre_dt_board.cmake b/boards/silabs/radio_boards/xg24_rb4187c/pre_dt_board.cmake new file mode 100644 index 00000000000..beb76b85552 --- /dev/null +++ b/boards/silabs/radio_boards/xg24_rb4187c/pre_dt_board.cmake @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +# SPI is implemented via usart so node name isn't spi@... +list(APPEND EXTRA_DTC_FLAGS "-Wno-spi_bus_bridge") diff --git a/boards/silabs/radio_boards/xg24_rb4187c/support/openocd.cfg b/boards/silabs/radio_boards/xg24_rb4187c/support/openocd.cfg new file mode 100644 index 00000000000..38409eb70ad --- /dev/null +++ b/boards/silabs/radio_boards/xg24_rb4187c/support/openocd.cfg @@ -0,0 +1,25 @@ +if {[info exists env(OPENOCD_INTERFACE)]} { + set INTERFACE $env(OPENOCD_INTERFACE) +} else { + # By default connect over Debug USB port using the J-Link interface + set INTERFACE "jlink" +} + +source [find interface/$INTERFACE.cfg] + +transport select swd + +set CHIPNAME efr32 + +source [find target/efm32.cfg] + +$_TARGETNAME configure -event gdb-attach { + echo "Debugger attaching: halting execution" + reset halt + gdb_breakpoint_override hard +} + +$_TARGETNAME configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48-pinctrl.dtsi b/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c-pinctrl.dtsi similarity index 100% rename from boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48-pinctrl.dtsi rename to boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c-pinctrl.dtsi diff --git a/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c.dts b/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c.dts new file mode 100644 index 00000000000..21a487e758f --- /dev/null +++ b/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c.dts @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2023 Fr. Sauter AG + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include "xg24_rb4187c-pinctrl.dtsi" + +/ { + model = "Silicon Labs BRD4187C (Mighty Gecko 24 Radio Board)"; + compatible = "silabs,xg24_rb4187c", "silabs,efr32mg24"; + + chosen { + zephyr,console = &usart0; + zephyr,shell-uart = &usart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,bt-hci = &bt_hci_silabs; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + led1 = &led1; + sw0 = &button0; + sw1 = &button1; + watchdog0 = &wdog0; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpiob GECKO_PIN(2) GPIO_ACTIVE_HIGH>; + label = "LED 0"; + }; + led1: led_1 { + gpios = <&gpiob GECKO_PIN(4) GPIO_ACTIVE_HIGH>; + label = "LED 1"; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpiob GECKO_PIN(1) GPIO_ACTIVE_LOW>; + label = "User Push Button 0"; + zephyr,code = ; + }; + button1: button_1 { + gpios = <&gpiob GECKO_PIN(3) GPIO_ACTIVE_LOW>; + label = "User Push Button 1"; + zephyr,code = ; + }; + }; + +}; + +&cpu0 { + clock-frequency = <39000000>; +}; + +&pstate_em3 { + status = "disabled"; +}; + +&usart0 { + current-speed = <115200>; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio { + location-swo = <0>; + status = "okay"; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; + + board-controller-enable { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&wdog0 { + status = "okay"; +}; + +&burtc0 { + status = "okay"; +}; + +&stimer0 { + status = "okay"; +}; + +&se { + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 48 kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 DT_SIZE_K(48)>; + read-only; + }; + + /* Reserve 720 kB for the application in slot 0 */ + slot0_partition: partition@c000 { + label = "image-0"; + reg = <0x0000c000 0x000B4000>; + }; + + /* Reserve 720 kB for the application in slot 1 */ + slot1_partition: partition@C0000 { + label = "image-1"; + reg = <0x000C0000 0x000B4000>; + }; + + /* Reserve 32 kB for the scratch partition */ + scratch_partition: partition@174000 { + label = "image-scratch"; + reg = <0x00174000 DT_SIZE_K(32)>; + }; + + /* Set 16 kB of storage at the end of the 1536 kB of flash */ + storage_partition: partition@17c000 { + label = "storage"; + reg = <0x0017c000 DT_SIZE_K(16)>; + }; + }; +}; + +&bt_hci_silabs { + status = "okay"; +}; diff --git a/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c.yaml b/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c.yaml new file mode 100644 index 00000000000..b0be89058ea --- /dev/null +++ b/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c.yaml @@ -0,0 +1,20 @@ +identifier: xg24_rb4187c +name: EFR32xG24 2.4 GHz 20 dBm Radio Board (xG24-RB4187C) +type: mcu +arch: arm +ram: 256 +flash: 1536 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - bluetooth + - gpio + - uart + - watchdog +testing: + ignore_tags: + - pm + - hwinfo +vendor: silabs diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48_defconfig b/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c_defconfig similarity index 100% rename from boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48_defconfig rename to boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c_defconfig diff --git a/boards/silabs/efm32wg_stk3800/Kconfig.defconfig b/boards/silabs/starter_kits/efm32wg_stk3800/Kconfig.defconfig similarity index 100% rename from boards/silabs/efm32wg_stk3800/Kconfig.defconfig rename to boards/silabs/starter_kits/efm32wg_stk3800/Kconfig.defconfig diff --git a/boards/silabs/efm32wg_stk3800/Kconfig.efm32wg_stk3800 b/boards/silabs/starter_kits/efm32wg_stk3800/Kconfig.efm32wg_stk3800 similarity index 100% rename from boards/silabs/efm32wg_stk3800/Kconfig.efm32wg_stk3800 rename to boards/silabs/starter_kits/efm32wg_stk3800/Kconfig.efm32wg_stk3800 diff --git a/boards/silabs/efm32wg_stk3800/board.cmake b/boards/silabs/starter_kits/efm32wg_stk3800/board.cmake similarity index 100% rename from boards/silabs/efm32wg_stk3800/board.cmake rename to boards/silabs/starter_kits/efm32wg_stk3800/board.cmake diff --git a/boards/silabs/efm32wg_stk3800/board.yml b/boards/silabs/starter_kits/efm32wg_stk3800/board.yml similarity index 100% rename from boards/silabs/efm32wg_stk3800/board.yml rename to boards/silabs/starter_kits/efm32wg_stk3800/board.yml diff --git a/boards/silabs/efm32wg_stk3800/doc/efm32wg_stk3800.jpg b/boards/silabs/starter_kits/efm32wg_stk3800/doc/efm32wg_stk3800.jpg similarity index 100% rename from boards/silabs/efm32wg_stk3800/doc/efm32wg_stk3800.jpg rename to boards/silabs/starter_kits/efm32wg_stk3800/doc/efm32wg_stk3800.jpg diff --git a/boards/silabs/starter_kits/efm32wg_stk3800/doc/index.rst b/boards/silabs/starter_kits/efm32wg_stk3800/doc/index.rst new file mode 100644 index 00000000000..0c04b7b21de --- /dev/null +++ b/boards/silabs/starter_kits/efm32wg_stk3800/doc/index.rst @@ -0,0 +1,177 @@ +.. _efm32wg_stk3800: + +EFM32 Wonder Gecko (EFM32WG-STK3800) +#################################### + +Overview +******** + +The EFM32 Wonder Gecko Starter Kit EFM32WG-STK3800 contains a MCU from the +EFM32WG family built on ARM® Cortex®-M4F processor with excellent low +power capabilities. + +.. figure:: efm32wg_stk3800.jpg + :align: center + :alt: EFM32WG-STK3800 + + EFM32WG-STK3800 (image courtesy of Silicon Labs) + + +Hardware +******** + +- Advanced Energy Monitoring provides real-time information about the energy + consumption of an application or prototype design. +- 32MByte parallel NAND Flash +- 160 segment Energy Micro LCD +- 2 user buttons, 2 LEDs and a touch slider +- Ambient Light Sensor and Inductive-capacitive metal sensor +- On-board Segger J-Link USB debugger + +For more information about the EFM32WG SoC and EFM32WG-STK3800 board: + +- `EFM32WG Website`_ +- `EFM32WG Datasheet`_ +- `EFM32WG Reference Manual`_ +- `EFM32WG-STK3800 Website`_ +- `EFM32WG-STK3800 User Guide`_ +- `EFM32WG-STK3800 Schematics`_ + +Supported Features +================== + +The efm32wg_stk3800 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/starter_kit/efm32wg_stk3800/efm32wg_stk3800_defconfig` + +Other hardware features are currently not supported by the port. + +Connections and IOs +=================== + +The EFM32WG SoC has six gpio controllers (PORTA to PORTF), but only three are +currently enabled (PORTB, PORTE and PORTF) for the EFM32WG-STK3800 board. + +In the following table, the column Name contains Pin names. For example, PE2 +means Pin number 2 on PORTE, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Name | Function | Usage | ++=======+=============+=====================================+ +| PE2 | GPIO | LED0 | ++-------+-------------+-------------------------------------+ +| PE3 | GPIO | LED1 | ++-------+-------------+-------------------------------------+ +| PB9 | GPIO | Push Button PB0 | ++-------+-------------+-------------------------------------+ +| PB10 | GPIO | Push Button PB1 | ++-------+-------------+-------------------------------------+ +| PF7 | GPIO | Board Controller Enable | +| | | EFM_BC_EN | ++-------+-------------+-------------------------------------+ +| PE0 | UART0_TX | UART Console EFM_BC_TX U0_TX #1 | ++-------+-------------+-------------------------------------+ +| PE1 | UART0_RX | UART Console EFM_BC_RX U0_RX #1 | ++-------+-------------+-------------------------------------+ + +System Clock +============ + +The EFM32WG SoC is configured to use the 48 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFM32WG SoC has three USARTs, two UARTs and two Low Energy UARTs (LEUART). +UART0 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +.. note:: + Before using the kit the first time, you should update the J-Link firmware + from `J-Link-Downloads`_ + +Flashing +======== + +The EFM32WG-STK3800 includes an `J-Link`_ serial and debug adaptor built into the +board. The adaptor provides: + +- A USB connection to the host computer, which exposes a Mass Storage and a + USB Serial Port. +- A Serial Flash device, which implements the USB flash disk file storage. +- A physical UART connection which is relayed over interface USB Serial port. + +Flashing an application to EFM32-STK3800 +---------------------------------------- + +The sample application :zephyr:code-sample:`hello_world` is used for this example. +Build the Zephyr kernel and application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: efm32wg_stk3800 + :goals: build + +Connect the EFM32WG-STK3800 to your host computer using the USB port and you +should see a USB connection which exposes a Mass Storage (STK3800) and a +USB Serial Port. Copy the generated zephyr.bin in the STK3800 drive. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you should be able to see on the corresponding Serial Port +the following message: + +.. code-block:: console + + Hello World! efm32wg_stk3800 + + +.. _EFM32WG-STK3800 Website: + http://www.silabs.com/products/development-tools/mcu/32-bit/efm32-wonder-gecko-starter-kit + +.. _EFM32WG-STK3800 User Guide: + http://www.silabs.com/documents/public/user-guides/efm32wg-stk3800-ug.pdf + +.. _EFM32WG-STK3800 Schematics: + http://www.silabs.com/documents/public/schematic-files/BRD2400A_A00.pdf + +.. _EFM32WG Website: + http://www.silabs.com/products/mcu/32-bit/efm32-wonder-gecko + +.. _EFM32WG Datasheet: + http://www.silabs.com/documents/public/data-sheets/EFM32WG990.pdf + +.. _EFM32WG Reference Manual: + http://www.silabs.com/documents/public/reference-manuals/EFM32WG-RM.pdf + +.. _J-Link: + https://www.segger.com/jlink-debug-probes.html + +.. _J-Link-Downloads: + https://www.segger.com/downloads/jlink diff --git a/boards/silabs/efm32wg_stk3800/efm32wg_stk3800.dts b/boards/silabs/starter_kits/efm32wg_stk3800/efm32wg_stk3800.dts similarity index 100% rename from boards/silabs/efm32wg_stk3800/efm32wg_stk3800.dts rename to boards/silabs/starter_kits/efm32wg_stk3800/efm32wg_stk3800.dts diff --git a/boards/silabs/efm32wg_stk3800/efm32wg_stk3800.yaml b/boards/silabs/starter_kits/efm32wg_stk3800/efm32wg_stk3800.yaml similarity index 79% rename from boards/silabs/efm32wg_stk3800/efm32wg_stk3800.yaml rename to boards/silabs/starter_kits/efm32wg_stk3800/efm32wg_stk3800.yaml index acd28a6623d..35dbe24db1f 100644 --- a/boards/silabs/efm32wg_stk3800/efm32wg_stk3800.yaml +++ b/boards/silabs/starter_kits/efm32wg_stk3800/efm32wg_stk3800.yaml @@ -1,5 +1,5 @@ identifier: efm32wg_stk3800 -name: EFM32WG-STK3800 +name: EFM32 Wonder Gecko Starter Kit (EFM32WG-STK3800) type: mcu arch: arm ram: 32 diff --git a/boards/silabs/efm32wg_stk3800/efm32wg_stk3800_defconfig b/boards/silabs/starter_kits/efm32wg_stk3800/efm32wg_stk3800_defconfig similarity index 100% rename from boards/silabs/efm32wg_stk3800/efm32wg_stk3800_defconfig rename to boards/silabs/starter_kits/efm32wg_stk3800/efm32wg_stk3800_defconfig diff --git a/boards/silabs/starter_kits/index.rst b/boards/silabs/starter_kits/index.rst new file mode 100644 index 00000000000..06d6c58f988 --- /dev/null +++ b/boards/silabs/starter_kits/index.rst @@ -0,0 +1,10 @@ +.. _starter_kits: + +Starter Kits +############ + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/silabs/starter_kits/slstk3400a/Kconfig.defconfig b/boards/silabs/starter_kits/slstk3400a/Kconfig.defconfig new file mode 100644 index 00000000000..78d39acd21a --- /dev/null +++ b/boards/silabs/starter_kits/slstk3400a/Kconfig.defconfig @@ -0,0 +1,14 @@ +# EFM32HG SLSTK3400A board + +# Copyright (c) 2018, Marcio Montenegro +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_SLSTK3400A + +config CMU_HFXO_FREQ + default 24000000 + +config CMU_LFXO_FREQ + default 32768 + +endif # BOARD_SLSTK3400A diff --git a/boards/silabs/starter_kits/slstk3400a/Kconfig.slstk3400a b/boards/silabs/starter_kits/slstk3400a/Kconfig.slstk3400a new file mode 100644 index 00000000000..bdbf1d82750 --- /dev/null +++ b/boards/silabs/starter_kits/slstk3400a/Kconfig.slstk3400a @@ -0,0 +1,7 @@ +# EFM32HG SLSTK3400A board + +# Copyright (c) 2018, Marcio Montenegro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SLSTK3400A + select SOC_PART_NUMBER_EFM32HG322F64 diff --git a/boards/silabs/starter_kits/slstk3400a/board.yml b/boards/silabs/starter_kits/slstk3400a/board.yml new file mode 100644 index 00000000000..e6573ac89f5 --- /dev/null +++ b/boards/silabs/starter_kits/slstk3400a/board.yml @@ -0,0 +1,5 @@ +board: + name: slstk3400a + vendor: silabs + socs: + - name: efm32hg322f64 diff --git a/boards/silabs/starter_kits/slstk3400a/doc/index.rst b/boards/silabs/starter_kits/slstk3400a/doc/index.rst new file mode 100644 index 00000000000..7f3f919643b --- /dev/null +++ b/boards/silabs/starter_kits/slstk3400a/doc/index.rst @@ -0,0 +1,176 @@ +.. _slstk3400a: + +EFM32 Happy Gecko (SLSTK3400A) +############################## + +Overview +******** + +The EFM32 Happy Gecko Starter Kit SLSTK3400A contains a MCU from the +EFM32HG family built on ARM® Cortex®-M0+ processor with excellent low +power capabilities. + +.. figure:: slstk3400a.jpg + :align: center + :alt: SLSTK3400A + + SLSTK3400A (image courtesy of Silicon Labs) + +Hardware +******** + +- Advanced Energy Monitoring system for precise current tracking +- Real-time energy and power profiling +- ARM Cortex M0+ with 64 kB Flash and 8 kB RAM +- 128 X 128 pixel Memory LCD +- 2 user buttons, 2 user LEDs and 2 touch buttons +- 20 pin expansion header +- Silicon Labs Si7021 Relative Humidity/Temperature sensor +- USB device interface +- Integrated SEGGER J-Link USB debugger/emulator with debug out functionality + + +See these documents for more information + +- `EFM32HG Website`_ +- `EFM32HG Datasheet`_ +- `EFM32HG Reference Manual`_ +- `SLSTK3400A Website`_ +- `SLSTK3400A User Guide`_ +- `SLSTK3400A Schematics`_ + +Supported Features +================== + +The efm32hg_slstk3400 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| USART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/starter_kit/slstk3400a/slstk3400a_defconfig` + +Other hardware features are currently not supported by the port. + +Connections and IOs +=================== + +The EFM32HG SoC has six GPIO controllers (PORTA to PORTF), but only three are +currently enabled (PORTB, PORTE and PORTF) for the SLSTK3400A board. + +In the following table, the column Name contains Pin names. For example, PF4 +means Pin number 4 on PORTF, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Name | Function | Usage | ++=======+=============+=====================================+ +| PF4 | GPIO | LED0 | ++-------+-------------+-------------------------------------+ +| PF5 | GPIO | LED1 | ++-------+-------------+-------------------------------------+ +| PC9 | GPIO | Push Button PB0 | ++-------+-------------+-------------------------------------+ +| PC10 | GPIO | Push Button PB1 | ++-------+-------------+-------------------------------------+ +| PF7 | GPIO | Board Controller Enable | +| | | EFM_BC_EN | ++-------+-------------+-------------------------------------+ +| PF2 | USART0_TX | USART Console EFM_BC_TX U0_TX #4 | ++-------+-------------+-------------------------------------+ +| PA9 | USART0_RX | USART Console EFM_BC_RX U0_RX #4 | ++-------+-------------+-------------------------------------+ + +System Clock +============ + +The EFM32HG SoC is configured to use the 24 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFM32HG SoC has two USARTs, two UARTs and two Low Energy UARTs (LEUART). +USART1 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +.. note:: + Before using the kit the first time, you should update the J-Link firmware + from `J-Link-Downloads`_ + +Flashing +======== + +The SLSTK3400 includes an `J-Link`_ serial and debug adaptor built into the +board. The adaptor provides: + +- A USB connection to the host computer, which exposes a Mass Storage and a + USB Serial Port. +- A Serial Flash device, which implements the USB flash disk file storage. +- A physical UART connection which is relayed over interface USB Serial port. + +Flashing an application to EFM32-SLSTK3400A +------------------------------------------- + +The sample application :zephyr:code-sample:`hello_world` is used for this example. +Build the Zephyr kernel and application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: slstk3400a + :goals: build + +Connect the SLSTK3400A to your host computer using the USB port and +you should see a USB connection that exposes a mass storage device (STK3400) +and a USB Serial Port. Copy the generated ``zephyr.bin`` in the STK3400 drive. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you will see this message written to the serial port: + +.. code-block:: console + + Hello World! slstk3400a + + +.. _SLSTK3400A Website: + https://www.silabs.com/products/development-tools/mcu/32-bit/efm32-happy-gecko-starter-kit + +.. _SLSTK3400A User Guide: + https://www.silabs.com/documents/public/user-guides/ug255-stk3400-user-guide.pdf + +.. _SLSTK3400A Schematics: + https://www.silabs.com/documents/public/schematic-files/BRD2012A-B01-schematic.pdf + +.. _EFM32HG Website: + https://www.silabs.com/products/mcu/32-bit/efm32-happy-gecko + +.. _EFM32HG Datasheet: + https://www.silabs.com/documents/public/data-sheets/EFM32HG322.pdf + +.. _EFM32HG Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/EFM32HG-RM.pdf + +.. _J-Link: + https://www.segger.com/jlink-debug-probes.html + +.. _J-Link-Downloads: + https://www.segger.com/downloads/jlink diff --git a/boards/silabs/efm32hg_slstk3400a/doc/efm32hg_slstk3400a.jpg b/boards/silabs/starter_kits/slstk3400a/doc/slstk3400a.jpg similarity index 100% rename from boards/silabs/efm32hg_slstk3400a/doc/efm32hg_slstk3400a.jpg rename to boards/silabs/starter_kits/slstk3400a/doc/slstk3400a.jpg diff --git a/boards/silabs/starter_kits/slstk3400a/slstk3400a.dts b/boards/silabs/starter_kits/slstk3400a/slstk3400a.dts new file mode 100644 index 00000000000..d7baf87f753 --- /dev/null +++ b/boards/silabs/starter_kits/slstk3400a/slstk3400a.dts @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2017 Christian Taedcke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include + +/ { + model = "Silicon Labs EFM32HG SLSTK3400A board"; + compatible = "silabs,slstk3400a", "silabs,efm32hg"; + + chosen { + zephyr,console = &usart1; + zephyr,shell-uart = &usart1; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + led1 = &led1; + sw0 = &button0; + sw1 = &button1; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpiof 4 0>; + label = "LED 0"; + }; + led1: led_1 { + gpios = <&gpiof 5 0>; + label = "LED 1"; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + /* gpio flags need validation */ + gpios = <&gpioc 9 GPIO_ACTIVE_LOW>; + label = "User Push Button 0"; + zephyr,code = ; + }; + button1: button_1 { + /* gpio flags need validation */ + gpios = <&gpioc 10 GPIO_ACTIVE_LOW>; + label = "User Push Button 1"; + zephyr,code = ; + }; + }; + +}; + +&cpu0 { + clock-frequency = <24000000>; +}; + +&gpioa { + status = "okay"; + + board-controller-enable { + gpio-hog; + gpios = <9 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&gpioc { + status = "okay"; +}; + +&gpiof { + status = "okay"; +}; + +&usart1 { + current-speed = <115200>; + location-rx = ; + location-tx = ; + status = "okay"; +}; + +&flash0 { + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Set 4Kb of storage at the end of the 64Kb of flash */ + storage_partition: partition@f000 { + label = "storage"; + reg = <0x0000f000 0x00001000>; + }; + + }; +}; diff --git a/boards/silabs/starter_kits/slstk3400a/slstk3400a.yaml b/boards/silabs/starter_kits/slstk3400a/slstk3400a.yaml new file mode 100644 index 00000000000..0739c38d858 --- /dev/null +++ b/boards/silabs/starter_kits/slstk3400a/slstk3400a.yaml @@ -0,0 +1,18 @@ +identifier: slstk3400a +name: EFM32 Happy Gecko Starter Kit (SLSTK3400A) +type: mcu +arch: arm +ram: 8 +flash: 64 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - nvs +testing: + ignore_tags: + - net + - bluetooth +vendor: silabs diff --git a/boards/silabs/efm32hg_slstk3400a/efm32hg_slstk3400a_defconfig b/boards/silabs/starter_kits/slstk3400a/slstk3400a_defconfig similarity index 100% rename from boards/silabs/efm32hg_slstk3400a/efm32hg_slstk3400a_defconfig rename to boards/silabs/starter_kits/slstk3400a/slstk3400a_defconfig diff --git a/boards/silabs/starter_kits/slstk3401a/Kconfig.defconfig b/boards/silabs/starter_kits/slstk3401a/Kconfig.defconfig new file mode 100644 index 00000000000..992f7da89d4 --- /dev/null +++ b/boards/silabs/starter_kits/slstk3401a/Kconfig.defconfig @@ -0,0 +1,14 @@ +# EFM32PG SLSTK3401A board + +# Copyright (c) 2020, Rafael Dias Menezes +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_SLSTK3401A + +config CMU_HFXO_FREQ + default 40000000 + +config CMU_LFXO_FREQ + default 32768 + +endif # BOARD_SLSTK3401A diff --git a/boards/silabs/starter_kits/slstk3401a/Kconfig.slstk3401a b/boards/silabs/starter_kits/slstk3401a/Kconfig.slstk3401a new file mode 100644 index 00000000000..ef6df9553d6 --- /dev/null +++ b/boards/silabs/starter_kits/slstk3401a/Kconfig.slstk3401a @@ -0,0 +1,7 @@ +# EFM32PG SLSTK3401A board + +# Copyright (c) 2020, Rafael Dias Menezes +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SLSTK3401A + select SOC_PART_NUMBER_EFM32PG1B200F256GM48 diff --git a/boards/silabs/efm32pg_stk3401a/board.cmake b/boards/silabs/starter_kits/slstk3401a/board.cmake similarity index 100% rename from boards/silabs/efm32pg_stk3401a/board.cmake rename to boards/silabs/starter_kits/slstk3401a/board.cmake diff --git a/boards/silabs/starter_kits/slstk3401a/board.yml b/boards/silabs/starter_kits/slstk3401a/board.yml new file mode 100644 index 00000000000..98ae08c1992 --- /dev/null +++ b/boards/silabs/starter_kits/slstk3401a/board.yml @@ -0,0 +1,5 @@ +board: + name: slstk3401a + vendor: silabs + socs: + - name: efm32pg1b200f256gm48 diff --git a/boards/silabs/starter_kits/slstk3401a/doc/index.rst b/boards/silabs/starter_kits/slstk3401a/doc/index.rst new file mode 100644 index 00000000000..d1e41ade626 --- /dev/null +++ b/boards/silabs/starter_kits/slstk3401a/doc/index.rst @@ -0,0 +1,188 @@ +.. _slstk3401a: + +EFM32 Pearl Gecko (SLSTK3401A) +############################## + +Overview +******** + +The EFM32 Pearl Gecko Starter Kit SLSTK3401A contains an MCU from the +EFM32PG family built on an ARM® Cortex®-M4F processor with excellent low +power capabilities. + +.. figure:: slstk3401a.jpg + :align: center + :alt: EFM32PG-SLSTK3401A + + EFM32PG-SLSTK3401A (image courtesy of Silicon Labs) + +Hardware +******** + +- Advanced Energy Monitoring provides real-time information about the energy + consumption of an application or prototype design. +- Ultra low power 128x128 pixel Memory-LCD +- 2 user buttons, 2 LEDs and 2 capacitive buttons +- Humidity and temperature sensor +- On-board Segger J-Link USB debugger + +For more information about the EFM32PG SoC and SLSTK3401A board: + +- `EFM32PG Website`_ +- `EFM32PG1 Datasheet`_ +- `EFM32PG1 Reference Manual`_ +- `SLSTK3401A Website`_ +- `SLSTK3401A User Guide`_ + +Supported Features +================== + +The slstk3401a board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtcc | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c port-polling | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/starter_kits/slstk3401a/slstk3401a_defconfig` + +Other hardware features are currently not supported by the port. + +Connections and IOs +=================== + +The EFM32PG1 SoC has five GPIO controllers (PORTA to PORTD and PORTF) and +all are enabled for the SLSTK3401A board. + +In the following table, the column **Name** contains pin names. For example, PF4 +means pin number 4 on PORTF, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Name | Function | Usage | ++=======+=============+=====================================+ +| PF4 | GPIO | LED0 | ++-------+-------------+-------------------------------------+ +| PF5 | GPIO | LED1 | ++-------+-------------+-------------------------------------+ +| PF6 | GPIO | Push Button PB0 | ++-------+-------------+-------------------------------------+ +| PF7 | GPIO | Push Button PB1 | ++-------+-------------+-------------------------------------+ +| PA5 | GPIO | Board Controller Enable | +| | | EFM_BC_EN | ++-------+-------------+-------------------------------------+ +| PA0 | UART_TX | UART TX Console VCOM_TX US0_TX #0 | ++-------+-------------+-------------------------------------+ +| PA1 | UART_RX | UART RX Console VCOM_RX US0_RX #0 | ++-------+-------------+-------------------------------------+ +| PD10 | UART_TX | EXP12_UART_TX LEU0_TX #18 | ++-------+-------------+-------------------------------------+ +| PD11 | UART_RX | EXP14_UART_RX LEU0_RX #18 | ++-------+-------------+-------------------------------------+ +| PC10 | I2C_SDA | ENV_I2C_SDA I2C0_SDA #15 | ++-------+-------------+-------------------------------------+ +| PC11 | I2C_SCL | ENV_I2C_SCL I2C0_SCL #15 | ++-------+-------------+-------------------------------------+ + + +System Clock +============ + +The EFM32PG SoC is configured to use the 40 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFM32PG SoC has two USARTs and one Low Energy UART (LEUART). + +Programming and Debugging +************************* + +.. note:: + Before using the kit the first time, you should update the J-Link firmware + from `J-Link-Downloads`_ + +Flashing +======== + +The SLSTK3401A includes an `J-Link`_ serial and debug adaptor built into the +board. The adaptor provides: + +- A USB connection to the host computer, which exposes a mass storage device and a + USB serial port. +- A serial flash device, which implements the USB flash disk file storage. +- A physical UART connection which is relayed over interface USB serial port. + +Flashing an application to SLSTK3401A +------------------------------------- + +The sample application :zephyr:code-sample:`hello_world` is used for this example. +Build the Zephyr kernel and application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: slstk3401a + :goals: build + +Connect the SLSTK3401A to your host computer using the USB port and you +should see a USB connection which exposes a mass storage device(SLSTK3401A). +Copy the generated zephyr.bin to the SLSTK3401A drive. + +Use a USB-to-UART converter such as an FT232/CP2102 to connect to the UART on the +expansion header. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you'll see the following message on the corresponding serial port +terminal session: + +.. code-block:: console + + Hello World! slstk3401a + + +.. _SLSTK3401A Website: + https://www.silabs.com/development-tools/mcu/32-bit/efm32pg1-starter-kit + +.. _SLSTK3401A User Guide: + https://www.silabs.com/documents/public/user-guides/ug154-stk3401-user-guide.pdf + +.. _EFM32PG Website: + https://www.silabs.com/products/mcu/32-bit/efm32-pearl-gecko + +.. _EFM32PG1 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efm32pg1-datasheet.pdf + +.. _EFM32PG1 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efm32pg1-rm.pdf + +.. _J-Link: + https://www.segger.com/jlink-debug-probes.html + +.. _J-Link-Downloads: + https://www.segger.com/downloads/jlink diff --git a/boards/silabs/efm32pg_stk3401a/doc/efm32pg_stk3401a.jpg b/boards/silabs/starter_kits/slstk3401a/doc/slstk3401a.jpg similarity index 100% rename from boards/silabs/efm32pg_stk3401a/doc/efm32pg_stk3401a.jpg rename to boards/silabs/starter_kits/slstk3401a/doc/slstk3401a.jpg diff --git a/boards/silabs/starter_kits/slstk3401a/slstk3401a-common.dtsi b/boards/silabs/starter_kits/slstk3401a/slstk3401a-common.dtsi new file mode 100644 index 00000000000..f9a6ff3da04 --- /dev/null +++ b/boards/silabs/starter_kits/slstk3401a/slstk3401a-common.dtsi @@ -0,0 +1,136 @@ +/* + * Copyright (c) 2020 Rafael Dias Menezes + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "slstk3401a-pinctrl.dtsi" + +/ { + model = "Silicon Labs EFM32PG SLSTK3401A board"; + + chosen { + zephyr,console = &usart0; + zephyr,shell-uart = &usart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + led1 = &led1; + sw0 = &button0; + sw1 = &button1; + watchdog0 = &wdog0; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpiof 4 0>; + label = "LED 0"; + }; + led1: led_1 { + gpios = <&gpiof 5 0>; + label = "LED 1"; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + /* gpio flags need validation */ + gpios = <&gpiof 6 GPIO_ACTIVE_LOW>; + label = "User Push Button 0"; + zephyr,code = ; + }; + button1: button_1 { + /* gpio flags need validation */ + gpios = <&gpiof 7 GPIO_ACTIVE_LOW>; + label = "User Push Button 1"; + zephyr,code = ; + }; + }; +}; + +&cpu0 { + clock-frequency = <40000000>; +}; + +&usart0 { + current-speed = <115200>; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&leuart0 { + current-speed = <9600>; + location-rx = ; + location-tx = ; + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rtcc0 { + prescaler = <1>; + status = "okay"; +}; + +&gpio { + location-swo = <0>; + status = "okay"; +}; + +&gpioa { + status = "okay"; + + board-controller-enable { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&gpiob { + status = "okay"; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&gpiof { + status = "okay"; +}; + +&wdog0 { + status = "okay"; +}; + +&flash0 { + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Set 6Kb of storage at the end of the 256Kb of flash */ + storage_partition: partition@3e800 { + label = "storage"; + reg = <0x0003e800 0x00001800>; + }; + + }; +}; diff --git a/boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a-pinctrl.dtsi b/boards/silabs/starter_kits/slstk3401a/slstk3401a-pinctrl.dtsi similarity index 100% rename from boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a-pinctrl.dtsi rename to boards/silabs/starter_kits/slstk3401a/slstk3401a-pinctrl.dtsi diff --git a/boards/silabs/starter_kits/slstk3401a/slstk3401a.dts b/boards/silabs/starter_kits/slstk3401a/slstk3401a.dts new file mode 100644 index 00000000000..b2afe5d40cf --- /dev/null +++ b/boards/silabs/starter_kits/slstk3401a/slstk3401a.dts @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2020 Rafael Dias Menezes + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "slstk3401a-common.dtsi" + +/ { + model = "Silicon Labs EFM32PG SLSTK3401A board"; + compatible = "silabs,slstk3401a", "silabs,efm32pg1b"; +}; diff --git a/boards/silabs/starter_kits/slstk3401a/slstk3401a.yaml b/boards/silabs/starter_kits/slstk3401a/slstk3401a.yaml new file mode 100644 index 00000000000..c2eab5f1756 --- /dev/null +++ b/boards/silabs/starter_kits/slstk3401a/slstk3401a.yaml @@ -0,0 +1,20 @@ +identifier: slstk3401a +name: EFM32 Pearl Gecko Starter Kit (SLSTK3401A) +type: mcu +arch: arm +ram: 32 +flash: 256 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - i2c + - gpio + - nvs + - watchdog +testing: + ignore_tags: + - net + - bluetooth +vendor: silabs diff --git a/boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a_defconfig b/boards/silabs/starter_kits/slstk3401a/slstk3401a_defconfig similarity index 100% rename from boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a_defconfig rename to boards/silabs/starter_kits/slstk3401a/slstk3401a_defconfig diff --git a/boards/silabs/starter_kits/slstk3402a/Kconfig.defconfig b/boards/silabs/starter_kits/slstk3402a/Kconfig.defconfig new file mode 100644 index 00000000000..87181e6b602 --- /dev/null +++ b/boards/silabs/starter_kits/slstk3402a/Kconfig.defconfig @@ -0,0 +1,15 @@ +# EFM32PG12 SLSTK3402A board + +# Copyright (c) 2018, Christian Taedcke +# Copyright (c) 2019 Lemonbeat GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_SLSTK3402A + +config CMU_HFXO_FREQ + default 40000000 + +config CMU_LFXO_FREQ + default 32768 + +endif # BOARD_SLSTK3402A diff --git a/boards/silabs/starter_kits/slstk3402a/Kconfig.slstk3402a b/boards/silabs/starter_kits/slstk3402a/Kconfig.slstk3402a new file mode 100644 index 00000000000..e4d6444823b --- /dev/null +++ b/boards/silabs/starter_kits/slstk3402a/Kconfig.slstk3402a @@ -0,0 +1,9 @@ +# EFM32PG12 SLSTK3402A board + +# Copyright (c) 2018, Christian Taedcke +# Copyright (c) 2019 Lemonbeat GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SLSTK3402A + select SOC_PART_NUMBER_EFM32PG12B500F1024GL125 if BOARD_SLSTK3402A_EFM32PG12B500F1024GL125 + select SOC_PART_NUMBER_EFM32JG12B500F1024GL125 if BOARD_SLSTK3402A_EFM32JG12B500F1024GL125 diff --git a/boards/silabs/efm32pg_stk3402a/board.cmake b/boards/silabs/starter_kits/slstk3402a/board.cmake similarity index 100% rename from boards/silabs/efm32pg_stk3402a/board.cmake rename to boards/silabs/starter_kits/slstk3402a/board.cmake diff --git a/boards/silabs/starter_kits/slstk3402a/board.yml b/boards/silabs/starter_kits/slstk3402a/board.yml new file mode 100644 index 00000000000..539af134c6d --- /dev/null +++ b/boards/silabs/starter_kits/slstk3402a/board.yml @@ -0,0 +1,6 @@ +board: + name: slstk3402a + vendor: silabs + socs: + - name: efm32pg12b500f1024gl125 + - name: efm32jg12b500f1024gl125 diff --git a/boards/silabs/starter_kits/slstk3402a/doc/index.rst b/boards/silabs/starter_kits/slstk3402a/doc/index.rst new file mode 100644 index 00000000000..4e5293ee08f --- /dev/null +++ b/boards/silabs/starter_kits/slstk3402a/doc/index.rst @@ -0,0 +1,214 @@ +.. _slstk3402a: + +EFM32 Pearl Gecko 12 (SLSTK3402A) +################################# + +Overview +******** + +The EFM32 Pearl Gecko 12 Starter Kit SLSTK3402A contains an MCU from the +EFM32PG family built on an ARM® Cortex®-M4F processor with excellent low +power capabilities. + +.. figure:: slstk3402a.jpg + :align: center + :alt: SLSTK3402A + + EFM32PG12 SLSTK3402A (image courtesy of Silicon Labs) + +Hardware +******** + +- Advanced Energy Monitoring provides real-time information about the energy + consumption of an application or prototype design. +- Ultra low power 128x128 pixel Memory-LCD +- 2 user buttons, 2 LEDs and a touch slider +- Humidity, temperature, and inductive-capacitive metal sensor +- On-board Segger J-Link USB debugger + +For more information about the EFM32PG SoC and SLSTK3402A board: + +- `EFM32PG Website`_ +- `EFM32PG12 Datasheet`_ +- `EFM32PG12 Reference Manual`_ +- `SLSTK3402A Website`_ +- `SLSTK3402A User Guide`_ +- `SLSTK3402A Schematics`_ + +Supported Features +================== + +The slstk3402a board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtcc | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c port-polling | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | true random number generator | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32pg12b500f1024gl125_defconfig` + +The default configuration when building using this board to develop for the +EFM32JG12 SoC can be found in +:zephyr_file:`boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32jg12b500f1024gl125_defconfig` + +Other hardware features are currently not supported by the port. + +EFM32 Jade Gecko SoC +-------------------- + +The EFM32 Pearl Gecko Starter Kit SLSTK3402A can also be used to evaluate +the EFM32 Jade Gecko SoC (EFM32JG12). The only difference between the Pearl +Gecko and the Jade Gecko is their core. The Pearl Gecko contains an ARM® +Cortex®-M4F core, and the Jade Gecko an ARM® Cortex®-M3 core. Other features +such as memory and peripherals are the same. + +Code that is built for the Jade Gecko also runs on an equivalent Pearl Gecko. + +To build firmware for the Jade Gecko and run it on the EFM32 Pearl Gecko Starter +Kit, use the board ``slstk3402a/efm32jg12b500f1024gl125`` instead of +``slstk3402a/efm32pg12b500f1024gl125``. + +Connections and IOs +=================== + +The EFM32PG12 SoC has twelve GPIO controllers (PORTA to PORTL), but only four +are currently enabled (PORTA, PORTB, PORTD and PORTF) for the SLSTK3402A +board. + +In the following table, the column **Name** contains pin names. For example, PE2 +means pin number 2 on PORTE, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Name | Function | Usage | ++=======+=============+=====================================+ +| PF4 | GPIO | LED0 | ++-------+-------------+-------------------------------------+ +| PF5 | GPIO | LED1 | ++-------+-------------+-------------------------------------+ +| PF6 | GPIO | Push Button PB0 | ++-------+-------------+-------------------------------------+ +| PF7 | GPIO | Push Button PB1 | ++-------+-------------+-------------------------------------+ +| PA5 | GPIO | Board Controller Enable | +| | | EFM_BC_EN | ++-------+-------------+-------------------------------------+ +| PA0 | UART_TX | UART TX Console VCOM_TX US0_TX #0 | ++-------+-------------+-------------------------------------+ +| PA1 | UART_RX | UART RX Console VCOM_RX US0_RX #0 | ++-------+-------------+-------------------------------------+ +| PD10 | UART_TX | EXP12_UART_TX LEU0_TX #18 | ++-------+-------------+-------------------------------------+ +| PD11 | UART_RX | EXP14_UART_RX LEU0_RX #18 | ++-------+-------------+-------------------------------------+ +| PC10 | I2C_SDA | ENV_I2C_SDA I2C0_SDA #15 | ++-------+-------------+-------------------------------------+ +| PC11 | I2C_SCL | ENV_I2C_SCL I2C0_SCL #15 | ++-------+-------------+-------------------------------------+ + + +System Clock +============ + +The EFM32PG12 SoC is configured to use the 40 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFM32PG12 SoC has four USARTs and one Low Energy UART (LEUART). + +Programming and Debugging +************************* + +.. note:: + Before using the kit the first time, you should update the J-Link firmware + from `J-Link-Downloads`_ + +Flashing +======== + +The SLSTK3402A includes an `J-Link`_ serial and debug adaptor built into the +board. The adaptor provides: + +- A USB connection to the host computer, which exposes a mass storage device and a + USB serial port. +- A serial flash device, which implements the USB flash disk file storage. +- A physical UART connection which is relayed over interface USB serial port. + +Flashing an application to SLSTK3402A +------------------------------------- + +The sample application :zephyr:code-sample:`hello_world` is used for this example. +Build the Zephyr kernel and application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: slstk3402a/efm32pg12b500f1024gl125 + :goals: build + +Connect the SLSTK3402A to your host computer using the USB port and you +should see a USB connection which exposes a mass storage device(STK3402A). +Copy the generated zephyr.bin to the STK3402A drive. + +Use a USB-to-UART converter such as an FT232/CP2102 to connect to the UART on the +expansion header. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you'll see the following message on the corresponding serial port +terminal session: + +.. code-block:: console + + Hello World! slstk3402a + + +.. _SLSTK3402A Website: + https://www.silabs.com/products/development-tools/mcu/32-bit/efm32-pearl-gecko-pg12-starter-kit + +.. _SLSTK3402A User Guide: + https://www.silabs.com/documents/public/user-guides/ug257-stk3402-usersguide.pdf + +.. _SLSTK3402A Schematics: + https://www.silabs.com/documents/public/schematic-files/BRD2501A-A01-schematic.pdf + +.. _EFM32PG Website: + https://www.silabs.com/products/mcu/32-bit/efm32-pearl-gecko + +.. _EFM32PG12 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efm32pg12-datasheet.pdf + +.. _EFM32PG12 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efm32pg12-rm.pdf + +.. _J-Link: + https://www.segger.com/jlink-debug-probes.html + +.. _J-Link-Downloads: + https://www.segger.com/downloads/jlink diff --git a/boards/silabs/efm32pg_stk3402a/doc/efm32pg_stk3402a.jpg b/boards/silabs/starter_kits/slstk3402a/doc/slstk3402a.jpg similarity index 100% rename from boards/silabs/efm32pg_stk3402a/doc/efm32pg_stk3402a.jpg rename to boards/silabs/starter_kits/slstk3402a/doc/slstk3402a.jpg diff --git a/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a-pinctrl.dtsi b/boards/silabs/starter_kits/slstk3402a/slstk3402a-pinctrl.dtsi similarity index 100% rename from boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a-pinctrl.dtsi rename to boards/silabs/starter_kits/slstk3402a/slstk3402a-pinctrl.dtsi diff --git a/boards/silabs/starter_kits/slstk3402a/slstk3402a_common.dtsi b/boards/silabs/starter_kits/slstk3402a/slstk3402a_common.dtsi new file mode 100644 index 00000000000..db100cd289b --- /dev/null +++ b/boards/silabs/starter_kits/slstk3402a/slstk3402a_common.dtsi @@ -0,0 +1,166 @@ +/* + * Copyright (c) 2017 Christian Taedcke + * Copyright (c) 2019 Lemonbeat GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "slstk3402a-pinctrl.dtsi" +#include + +/ { + model = "Silicon Labs EFM32PG12 STK3402A board"; + + chosen { + zephyr,console = &usart0; + zephyr,shell-uart = &usart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + led1 = &led1; + pwm-led0 = &pwm_led0; + sw0 = &button0; + sw1 = &button1; + watchdog0 = &wdog0; + watchdog1 = &wdog1; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpiof 4 0>; + label = "LED 0"; + }; + led1: led_1 { + gpios = <&gpiof 5 0>; + label = "LED 1"; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + /* gpio flags need validation */ + gpios = <&gpiof 6 GPIO_ACTIVE_LOW>; + label = "User Push Button 0"; + zephyr,code = ; + }; + button1: button_1 { + /* gpio flags need validation */ + gpios = <&gpiof 7 GPIO_ACTIVE_LOW>; + label = "User Push Button 1"; + zephyr,code = ; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + status = "okay"; + pwm_led0: pwm_led0 { + pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + }; + }; +}; + +&cpu0 { + clock-frequency = <40000000>; +}; + +&usart0 { + current-speed = <115200>; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&leuart0 { + current-speed = <9600>; + location-rx = ; + location-tx = ; + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rtcc0 { + prescaler = <1>; + status = "okay"; +}; + +&timer0 { + status = "okay"; + + pwm0: pwm { + status = "okay"; + pin-location = ; + prescaler = <1024>; + }; +}; + +&gpio { + location-swo = <0>; + status = "okay"; +}; + +&gpioa { + status = "okay"; + + board-controller-enable { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&gpiob { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&gpiof { + status = "okay"; +}; + +&wdog0 { + status = "okay"; +}; + +&wdog1 { + status = "okay"; +}; + + +&flash0 { + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Set 6Kb of storage at the end of the 1024Kb of flash */ + storage_partition: partition@fe800 { + label = "storage"; + reg = <0x000fe800 0x00001800>; + }; + + }; +}; + +&trng0 { + status = "okay"; +}; + +&adc0 { + status = "okay"; +}; diff --git a/boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32jg12b500f1024gl125.dts b/boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32jg12b500f1024gl125.dts new file mode 100644 index 00000000000..184c3c51a07 --- /dev/null +++ b/boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32jg12b500f1024gl125.dts @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2019 Lemonbeat GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "slstk3402a_common.dtsi" + +/ { + model = "Silicon Labs EFM32JG12 STK3402A board "; + compatible = "silabs,slstk3402a_jg", "silabs,efm32jg12b"; + +}; diff --git a/boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32jg12b500f1024gl125.yaml b/boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32jg12b500f1024gl125.yaml new file mode 100644 index 00000000000..f6981091500 --- /dev/null +++ b/boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32jg12b500f1024gl125.yaml @@ -0,0 +1,19 @@ +identifier: slstk3402a/efm32jg12b500f1024gl125 +name: EFM32JG12 SLSTK3402A +type: mcu +arch: arm +ram: 256 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - i2c + - gpio + - nvs +testing: + ignore_tags: + - net + - bluetooth +vendor: silabs diff --git a/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32jg12b500f1024gl125_defconfig b/boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32jg12b500f1024gl125_defconfig similarity index 100% rename from boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32jg12b500f1024gl125_defconfig rename to boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32jg12b500f1024gl125_defconfig diff --git a/boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32pg12b500f1024gl125.dts b/boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32pg12b500f1024gl125.dts new file mode 100644 index 00000000000..a35289d0cbf --- /dev/null +++ b/boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32pg12b500f1024gl125.dts @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2017 Christian Taedcke + * Copyright (c) 2019 Lemonbeat GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "slstk3402a_common.dtsi" + +/ { + model = "Silicon Labs EFM32PG12 SLSTK3402A board"; + compatible = "silabs,slstk3402a", "silabs,efm32pg12b"; +}; diff --git a/boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32pg12b500f1024gl125.yaml b/boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32pg12b500f1024gl125.yaml new file mode 100644 index 00000000000..1ce7433a7aa --- /dev/null +++ b/boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32pg12b500f1024gl125.yaml @@ -0,0 +1,20 @@ +identifier: slstk3402a/efm32pg12b500f1024gl125 +name: EFM32PG12 SLSTK3402A +type: mcu +arch: arm +ram: 256 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - i2c + - gpio + - nvs + - watchdog +testing: + ignore_tags: + - net + - bluetooth +vendor: silabs diff --git a/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32pg12b500f1024gl125_defconfig b/boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32pg12b500f1024gl125_defconfig similarity index 100% rename from boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32pg12b500f1024gl125_defconfig rename to boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32pg12b500f1024gl125_defconfig diff --git a/boards/silabs/efm32gg_stk3701a/CMakeLists.txt b/boards/silabs/starter_kits/slstk3701a/CMakeLists.txt similarity index 100% rename from boards/silabs/efm32gg_stk3701a/CMakeLists.txt rename to boards/silabs/starter_kits/slstk3701a/CMakeLists.txt diff --git a/boards/silabs/starter_kits/slstk3701a/Kconfig.defconfig b/boards/silabs/starter_kits/slstk3701a/Kconfig.defconfig new file mode 100644 index 00000000000..24d55ad5a9b --- /dev/null +++ b/boards/silabs/starter_kits/slstk3701a/Kconfig.defconfig @@ -0,0 +1,28 @@ +# EFM32GG STK3701A default board configuration +# Copyright (c) 2019 Interay Solutions B.V. +# Copyright (c) 2019 Oane Kingma +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_SLSTK3701A + +config CMU_HFXO_FREQ + default 50000000 + +config CMU_HFRCO_FREQ + default 72000000 + +config CMU_LFXO_FREQ + default 32768 + +config LOG_BACKEND_SWO_FREQ_HZ + default 875000 + depends on LOG_BACKEND_SWO + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_SLSTK3701A diff --git a/boards/silabs/starter_kits/slstk3701a/Kconfig.slstk3701a b/boards/silabs/starter_kits/slstk3701a/Kconfig.slstk3701a new file mode 100644 index 00000000000..e0fd2b5412e --- /dev/null +++ b/boards/silabs/starter_kits/slstk3701a/Kconfig.slstk3701a @@ -0,0 +1,7 @@ +# EFM32GG11 SLSTK3701A board configuration +# Copyright (c) 2019 Interay Solutions B.V. +# Copyright (c) 2019 Oane Kingma +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SLSTK3701A + select SOC_PART_NUMBER_EFM32GG11B820F2048GL192 diff --git a/boards/silabs/efm32gg_stk3701a/board.c b/boards/silabs/starter_kits/slstk3701a/board.c similarity index 100% rename from boards/silabs/efm32gg_stk3701a/board.c rename to boards/silabs/starter_kits/slstk3701a/board.c diff --git a/boards/silabs/efm32gg_stk3701a/board.cmake b/boards/silabs/starter_kits/slstk3701a/board.cmake similarity index 100% rename from boards/silabs/efm32gg_stk3701a/board.cmake rename to boards/silabs/starter_kits/slstk3701a/board.cmake diff --git a/boards/silabs/efm32gg_stk3701a/board.h b/boards/silabs/starter_kits/slstk3701a/board.h similarity index 100% rename from boards/silabs/efm32gg_stk3701a/board.h rename to boards/silabs/starter_kits/slstk3701a/board.h diff --git a/boards/silabs/starter_kits/slstk3701a/board.yml b/boards/silabs/starter_kits/slstk3701a/board.yml new file mode 100644 index 00000000000..5c1db884a42 --- /dev/null +++ b/boards/silabs/starter_kits/slstk3701a/board.yml @@ -0,0 +1,5 @@ +board: + name: slstk3701a + vendor: silabs + socs: + - name: efm32gg11b820f2048gl192 diff --git a/boards/silabs/starter_kits/slstk3701a/doc/index.rst b/boards/silabs/starter_kits/slstk3701a/doc/index.rst new file mode 100644 index 00000000000..6209984049e --- /dev/null +++ b/boards/silabs/starter_kits/slstk3701a/doc/index.rst @@ -0,0 +1,200 @@ +.. _efm32gg_stk3701a: + +EFM32 Giant Gecko 11 (SLSTK3701A) +################################# + +Overview +******** + +The EFM32 Giant Gecko Starter Kit SLSTK3701A contains an MCU from the +EFM32GG Series 1 family built on an ARM® Cortex®-M4F processor with excellent +low power capabilities. + +.. figure:: slstk3701a.jpg + :align: center + :alt: EFM32GG11 SLSTK3701A + + EFM32GG11 SLSTK3701A (image courtesy of Silicon Labs) + +Hardware +******** + +- Advanced Energy Monitoring provides real-time information about the energy + consumption of an application or prototype design. +- Ultra low power 128x128 pixel color Memory-LCD +- 2 user buttons, 2 LEDs and a touch slider +- Relative humidity, magnetic Hall Effect and inductive-capacitive metal sensor +- USB interface for Host/Device/OTG +- 32 Mb Quad-SPI Flash memory +- SD card slot +- RJ-45 Ethernet jack +- 2 digital microphones +- On-board Segger J-Link USB debugger + +For more information about the EFM32GG11 SoC and SLSTK3701A board: + +- `EFM32GG Series 1 Website`_ +- `EFM32GG11 Datasheet`_ +- `EFM32GG11 Reference Manual`_ +- `SLSTK3701A Website`_ +- `SLSTK3701A User Guide`_ +- `SLSTK3701A Schematics`_ + +Supported Features +================== + +The slstk3701a board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtcc | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c port-polling | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/starter_kits/slstk3701a/slstk3701a_defconfig` + +Other hardware features are currently not supported by the port. + +Connections and IOs +=================== + +The EFM32GG11 SoC has nine GPIO controllers (PORTA to PORTI), all of which are +currently enabled for the SLSTK3701A board. + +In the following table, the column **Name** contains pin names. For example, PE1 +means pin number 1 on PORTE, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Name | Function | Usage | ++=======+=============+=====================================+ +| PH10 | GPIO | LED0 red | ++-------+-------------+-------------------------------------+ +| PH11 | GPIO | LED0 green | ++-------+-------------+-------------------------------------+ +| PH12 | GPIO | LED0 blue | ++-------+-------------+-------------------------------------+ +| PH13 | GPIO | LED1 red | ++-------+-------------+-------------------------------------+ +| PH14 | GPIO | LED1 green | ++-------+-------------+-------------------------------------+ +| PH15 | GPIO | LED1 blue | ++-------+-------------+-------------------------------------+ +| PC8 | GPIO | Push Button PB0 | ++-------+-------------+-------------------------------------+ +| PC9 | GPIO | Push Button PB1 | ++-------+-------------+-------------------------------------+ +| PE1 | GPIO | Board Controller Enable | +| | | EFM_BC_EN | ++-------+-------------+-------------------------------------+ +| PH4 | UART_TX | UART TX Console VCOM_TX US0_TX #4 | ++-------+-------------+-------------------------------------+ +| PH5 | UART_RX | UART RX Console VCOM_RX US0_RX #4 | ++-------+-------------+-------------------------------------+ +| PI4 | I2C_SDA | SENSOR_I2C_SDA I2C2_SDA #7 | ++-------+-------------+-------------------------------------+ +| PI5 | I2C_SCL | SENSOR_I2C_SCL I2C2_SCL #7 | ++-------+-------------+-------------------------------------+ + + +System Clock +============ + +The EFM32GG11 SoC is configured to use the 50 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFM32GG11 SoC has six USARTs, two UARTs and two Low Energy UARTs (LEUART). +USART4 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +.. note:: + Before using the kit the first time, you should update the J-Link firmware + from `J-Link-Downloads`_ + +Flashing +======== + +The SLSTK3701A includes an `J-Link`_ serial and debug adaptor built into the +board. The adaptor provides: + +- A USB connection to the host computer, which exposes a mass storage device and a + USB serial port. +- A serial flash device, which implements the USB flash disk file storage. +- A physical UART connection which is relayed over interface USB serial port. + +Flashing an application to SLSTK3701A +------------------------------------- + +The sample application :zephyr:code-sample:`hello_world` is used for this example. +Build the Zephyr kernel and application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: slstk3701a + :goals: build + +Connect the SLSTK3701A to your host computer using the USB port and you +should see a USB connection which exposes a mass storage device(STK3701A) and +a USB Serial Port. Copy the generated zephyr.bin to the STK3701A drive. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you'll see the following message on the corresponding serial port +terminal session: + +.. code-block:: console + + Hello World! slstk3701a + + +.. _SLSTK3701A Website: + https://www.silabs.com/products/development-tools/mcu/32-bit/efm32-giant-gecko-gg11-starter-kit + +.. _SLSTK3701A User Guide: + https://www.silabs.com/documents/public/user-guides/ug287-stk3701.pdf + +.. _SLSTK3701A Schematics: + https://www.silabs.com/documents/public/schematic-files/BRD2204A-B00-schematic.pdf + +.. _EFM32GG Series 1 Website: + https://www.silabs.com/products/mcu/32-bit/efm32-giant-gecko-s1 + +.. _EFM32GG11 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efm32gg11-datasheet.pdf + +.. _EFM32GG11 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efm32gg11-rm.pdf + +.. _J-Link: + https://www.segger.com/jlink-debug-probes.html + +.. _J-Link-Downloads: + https://www.segger.com/downloads/jlink diff --git a/boards/silabs/efm32gg_stk3701a/doc/efm32gg_stk3701a.jpg b/boards/silabs/starter_kits/slstk3701a/doc/slstk3701a.jpg similarity index 100% rename from boards/silabs/efm32gg_stk3701a/doc/efm32gg_stk3701a.jpg rename to boards/silabs/starter_kits/slstk3701a/doc/slstk3701a.jpg diff --git a/boards/silabs/efm32gg_stk3701a/efm32gg_stk3701a-pinctrl.dtsi b/boards/silabs/starter_kits/slstk3701a/slstk3701a-pinctrl.dtsi similarity index 100% rename from boards/silabs/efm32gg_stk3701a/efm32gg_stk3701a-pinctrl.dtsi rename to boards/silabs/starter_kits/slstk3701a/slstk3701a-pinctrl.dtsi diff --git a/boards/silabs/starter_kits/slstk3701a/slstk3701a.dts b/boards/silabs/starter_kits/slstk3701a/slstk3701a.dts new file mode 100644 index 00000000000..1e67f024d7f --- /dev/null +++ b/boards/silabs/starter_kits/slstk3701a/slstk3701a.dts @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2019 Interay Solutions B.V. + * Copyright (c) 2019 Oane Kingma + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include "slstk3701a-pinctrl.dtsi" + +/ { + model = "Silicon Labs EFM32GG11 SLSTK3701A board"; + compatible = "silabs,slstk3701a", "silabs,efm32gg11b"; + + chosen { + zephyr,console = &usart4; + zephyr,shell-uart = &usart4; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + led1 = &led1; + sw0 = &button0; + sw1 = &button1; + watchdog0 = &wdog0; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpioh 10 GPIO_ACTIVE_LOW>; + label = "LED 0"; + }; + led1: led_1 { + gpios = <&gpioh 13 GPIO_ACTIVE_LOW>; + label = "LED 1"; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + /* gpio flags need validation */ + gpios = <&gpioc 8 GPIO_ACTIVE_LOW>; + label = "User Push Button 0"; + zephyr,code = ; + }; + button1: button_1 { + /* gpio flags need validation */ + gpios = <&gpioc 9 GPIO_ACTIVE_LOW>; + label = "User Push Button 1"; + zephyr,code = ; + }; + }; +}; + +&usart0 { + current-speed = <115200>; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usart4 { + current-speed = <115200>; + pinctrl-0 = <&usart4_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&leuart0 { + current-speed = <9600>; + location-rx = ; + location-tx = ; + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rtcc0 { + prescaler = <1>; + status = "okay"; +}; + +&gpio { + location-swo = <0>; + status = "okay"; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&gpioe { + status = "okay"; + + board-controller-enable { + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&gpiof { + status = "okay"; +}; + +&gpiog { + status = "okay"; +}; + +&gpioh { + status = "okay"; +}; + +&gpioi { + status = "okay"; +}; + +ð0 { + /* PHY address = 0 */ + phy-address = <0>; + + /* PHY management pins */ + location-mdio = ; + location-phy_mdc = ; + location-phy_mdio = ; + + /* RMII interface pins */ + location-rmii = ; + location-rmii_refclk = ; + location-rmii_crs_dv = ; + location-rmii_txd0 = ; + location-rmii_txd1 = ; + location-rmii_tx_en = ; + location-rmii_rxd0 = ; + location-rmii_rxd1 = ; + location-rmii_rx_er = ; + + status = "okay"; +}; + +&flash0 { + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Set 12Kb of storage at the end of the 2048Kb of flash */ + storage_partition: partition@1fd000 { + label = "storage"; + reg = <0x001fd000 0x00003000>; + }; + }; +}; + +&wdog0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&cpu0 { + clock-frequency = <72000000>; +}; diff --git a/boards/silabs/starter_kits/slstk3701a/slstk3701a.yaml b/boards/silabs/starter_kits/slstk3701a/slstk3701a.yaml new file mode 100644 index 00000000000..bfad741b918 --- /dev/null +++ b/boards/silabs/starter_kits/slstk3701a/slstk3701a.yaml @@ -0,0 +1,19 @@ +identifier: slstk3701a +name: EFM32GG11 Giant Gecko Starter Kit (SLSTK3701A) +type: mcu +arch: arm +ram: 512 +flash: 2048 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - i2c + - gpio + - netif:eth + - nvs +testing: + ignore_tags: + - bluetooth +vendor: silabs diff --git a/boards/silabs/efm32gg_stk3701a/efm32gg_stk3701a_defconfig b/boards/silabs/starter_kits/slstk3701a/slstk3701a_defconfig similarity index 100% rename from boards/silabs/efm32gg_stk3701a/efm32gg_stk3701a_defconfig rename to boards/silabs/starter_kits/slstk3701a/slstk3701a_defconfig diff --git a/boards/silabs/efm32gg_stk3701a/support/openocd.cfg b/boards/silabs/starter_kits/slstk3701a/support/openocd.cfg similarity index 100% rename from boards/silabs/efm32gg_stk3701a/support/openocd.cfg rename to boards/silabs/starter_kits/slstk3701a/support/openocd.cfg diff --git a/boards/sipeed/longan_nano/doc/index.rst b/boards/sipeed/longan_nano/doc/index.rst index b62d91c3130..6150c2378cf 100644 --- a/boards/sipeed/longan_nano/doc/index.rst +++ b/boards/sipeed/longan_nano/doc/index.rst @@ -74,6 +74,11 @@ The board configuration supports the following hardware features: * - ADC - :kconfig:option:`CONFIG_ADC` - :dtcompatible:`gd,gd32-adc` + * - SPI + - :kconfig:option:`CONFIG_SPI` + - :dtcompatible:`gd,gd32-spi` + +The microSD card reader in Longan Nano board is connected to SPI1. Serial Port =========== diff --git a/boards/sipeed/longan_nano/support/openocd.cfg b/boards/sipeed/longan_nano/support/openocd.cfg index 4ebb4a0505b..c28b90767d7 100644 --- a/boards/sipeed/longan_nano/support/openocd.cfg +++ b/boards/sipeed/longan_nano/support/openocd.cfg @@ -13,7 +13,7 @@ ftdi_vid_pid 0x0403 0x6010 ftdi_layout_init 0x0008 0x001b ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020 -adapter_khz 2000 +adapter speed 2000 transport select jtag proc gd32vf103-pre-load {} { diff --git a/boards/snps/em_starterkit/doc/index.rst b/boards/snps/em_starterkit/doc/index.rst index 4390ab2e4c6..e569031e378 100644 --- a/boards/snps/em_starterkit/doc/index.rst +++ b/boards/snps/em_starterkit/doc/index.rst @@ -173,7 +173,7 @@ Building Sample Applications ============================== You can try many of the sample applications or tests, but let us discuss -the one called :ref:`hello_world`. +the one called :zephyr:code-sample:`hello_world`. It is found in :zephyr_file:`samples/hello_world`. Configuring @@ -201,7 +201,7 @@ Building You can build application in the usual way. Refer to :ref:`build_an_application` for more details. Here is an example for -:ref:`hello_world`. +:zephyr:code-sample:`hello_world`. .. zephyr-app-commands:: :board: em_starterkit diff --git a/boards/snps/em_starterkit/em_starterkit_emsk_em7d_2_3.overlay b/boards/snps/em_starterkit/em_starterkit_emsk_em7d_2_3.overlay index bb7e6a3ee9b..590d0aefb8a 100644 --- a/boards/snps/em_starterkit/em_starterkit_emsk_em7d_2_3.overlay +++ b/boards/snps/em_starterkit/em_starterkit_emsk_em7d_2_3.overlay @@ -19,7 +19,6 @@ uart-0 = &uart0; uart-1 = &uart1; uart-2 = &uart2; - spi-flash0 = &w25q128bv; }; chosen { diff --git a/boards/snps/em_starterkit/em_starterkit_r23.dtsi b/boards/snps/em_starterkit/em_starterkit_r23.dtsi index 3de7425d975..ef93abcfd46 100644 --- a/boards/snps/em_starterkit/em_starterkit_r23.dtsi +++ b/boards/snps/em_starterkit/em_starterkit_r23.dtsi @@ -5,10 +5,6 @@ */ / { - aliases { - spi-flash0 = &w25q128bv; - }; - soc { i2c@f0004000 { interrupts = <25 1>; diff --git a/boards/snps/emsdp/doc/index.rst b/boards/snps/emsdp/doc/index.rst index fa4606d98f8..bad8a48e4bb 100644 --- a/boards/snps/emsdp/doc/index.rst +++ b/boards/snps/emsdp/doc/index.rst @@ -161,7 +161,7 @@ Building Sample Applications ============================== You can try many of the sample applications or tests, but let us discuss -the one called :ref:`hello_world`. +the one called :zephyr:code-sample:`hello_world`. It is found in :zephyr_file:`samples/hello_world`. Configuring @@ -184,7 +184,7 @@ Building You can build an application in the usual way. Refer to :ref:`build_an_application` for more details. Here is an example for -:ref:`hello_world` for the em4. +:zephyr:code-sample:`hello_world` for the em4. .. zephyr-app-commands:: :board: emsdp/emsdp_em4 diff --git a/boards/snps/emsdp/emsdp_emsdp_em11d.dts b/boards/snps/emsdp/emsdp_emsdp_em11d.dts index 6a24a9ec5bd..d3a9a10d0e7 100644 --- a/boards/snps/emsdp/emsdp_emsdp_em11d.dts +++ b/boards/snps/emsdp/emsdp_emsdp_em11d.dts @@ -17,7 +17,6 @@ aliases { uart-0 = &uart0; - spi-flash0 = &s25fl256s; }; chosen { diff --git a/boards/snps/emsdp/emsdp_emsdp_em4.dts b/boards/snps/emsdp/emsdp_emsdp_em4.dts index 0d0306065c0..04414f10c6e 100644 --- a/boards/snps/emsdp/emsdp_emsdp_em4.dts +++ b/boards/snps/emsdp/emsdp_emsdp_em4.dts @@ -15,7 +15,6 @@ aliases { uart-0 = &uart0; - spi-flash0 = &s25fl256s; }; chosen { diff --git a/boards/snps/emsdp/emsdp_emsdp_em5d.dts b/boards/snps/emsdp/emsdp_emsdp_em5d.dts index 66a544e95ef..57ba196e1dd 100644 --- a/boards/snps/emsdp/emsdp_emsdp_em5d.dts +++ b/boards/snps/emsdp/emsdp_emsdp_em5d.dts @@ -15,7 +15,6 @@ aliases { uart-0 = &uart0; - spi-flash0 = &s25fl256s; }; chosen { diff --git a/boards/snps/emsdp/emsdp_emsdp_em6.dts b/boards/snps/emsdp/emsdp_emsdp_em6.dts index 0d0306065c0..04414f10c6e 100644 --- a/boards/snps/emsdp/emsdp_emsdp_em6.dts +++ b/boards/snps/emsdp/emsdp_emsdp_em6.dts @@ -15,7 +15,6 @@ aliases { uart-0 = &uart0; - spi-flash0 = &s25fl256s; }; chosen { diff --git a/boards/snps/emsdp/emsdp_emsdp_em7d.dts b/boards/snps/emsdp/emsdp_emsdp_em7d.dts index 66a544e95ef..57ba196e1dd 100644 --- a/boards/snps/emsdp/emsdp_emsdp_em7d.dts +++ b/boards/snps/emsdp/emsdp_emsdp_em7d.dts @@ -15,7 +15,6 @@ aliases { uart-0 = &uart0; - spi-flash0 = &s25fl256s; }; chosen { diff --git a/boards/snps/emsdp/emsdp_emsdp_em7d_esp.dts b/boards/snps/emsdp/emsdp_emsdp_em7d_esp.dts index 89fc30499b7..1880de517b9 100644 --- a/boards/snps/emsdp/emsdp_emsdp_em7d_esp.dts +++ b/boards/snps/emsdp/emsdp_emsdp_em7d_esp.dts @@ -15,7 +15,6 @@ aliases { uart-0 = &uart0; - spi-flash0 = &s25fl256s; }; chosen { diff --git a/boards/snps/emsdp/emsdp_emsdp_em9d.dts b/boards/snps/emsdp/emsdp_emsdp_em9d.dts index c28956b9f60..c87bfe3e7f6 100644 --- a/boards/snps/emsdp/emsdp_emsdp_em9d.dts +++ b/boards/snps/emsdp/emsdp_emsdp_em9d.dts @@ -16,7 +16,6 @@ aliases { uart-0 = &uart0; - spi-flash0 = &s25fl256s; }; chosen { diff --git a/boards/snps/hsdk/doc/index.rst b/boards/snps/hsdk/doc/index.rst index 5d5fb1aa521..a7165a27658 100644 --- a/boards/snps/hsdk/doc/index.rst +++ b/boards/snps/hsdk/doc/index.rst @@ -388,7 +388,7 @@ Building Sample Applications ============================== You can try many of the :ref:`sample applications and demos -`. We'll use :ref:`hello_world`, found in +`. We'll use :zephyr:code-sample:`hello_world`, found in :zephyr_file:`samples/hello_world` as an example. Configuring @@ -410,7 +410,7 @@ Building You can build an application in the usual way. Refer to :ref:`build_an_application` for more details. Here is an example for -:ref:`hello_world`. +:zephyr:code-sample:`hello_world`. .. zephyr-app-commands:: :board: hsdk diff --git a/boards/snps/hsdk4xd/doc/index.rst b/boards/snps/hsdk4xd/doc/index.rst index b373f22cee3..a5cfd534c00 100644 --- a/boards/snps/hsdk4xd/doc/index.rst +++ b/boards/snps/hsdk4xd/doc/index.rst @@ -385,7 +385,7 @@ Building Sample Applications ============================== You can try many of the :ref:`sample applications and demos -`. We'll use :ref:`hello_world`, found in +`. We'll use :zephyr:code-sample:`hello_world`, found in :zephyr_file:`samples/hello_world` as an example. Configuring @@ -407,7 +407,7 @@ Building You can build an application in the usual way. Refer to :ref:`build_an_application` for more details. Here is an example for -:ref:`hello_world`. +:zephyr:code-sample:`hello_world`. .. zephyr-app-commands:: :board: hsdk4xd diff --git a/boards/snps/iotdk/doc/index.rst b/boards/snps/iotdk/doc/index.rst index e3d99ce2423..5482bed17d9 100644 --- a/boards/snps/iotdk/doc/index.rst +++ b/boards/snps/iotdk/doc/index.rst @@ -68,7 +68,7 @@ Building Sample Applications ============================== You can try many of the sample applications or tests, but let us discuss -the one called :ref:`hello_world`. +the one called :zephyr:code-sample:`hello_world`. It is found in :zephyr_file:`samples/hello_world`. Configuring @@ -90,7 +90,7 @@ Building You can build an application in the usual way. Refer to :ref:`build_an_application` for more details. Here is an example for -:ref:`hello_world`. +:zephyr:code-sample:`hello_world`. .. zephyr-app-commands:: :board: iotdk @@ -191,7 +191,7 @@ References .. _embARC website: https://www.embarc.org -.. _Designware ARC IoT Development Kit website: `_ +.. _Designware ARC IoT Development Kit website: https://www.synopsys.com/dw/ipdir.php?ds=arc_iot_development_kit .. _Digilent Pmod Modules: http://store.digilentinc.com/pmod-modules diff --git a/boards/snps/nsim/CMakeLists.txt b/boards/snps/nsim/arc_classic/CMakeLists.txt similarity index 100% rename from boards/snps/nsim/CMakeLists.txt rename to boards/snps/nsim/arc_classic/CMakeLists.txt diff --git a/boards/snps/nsim/Kconfig b/boards/snps/nsim/arc_classic/Kconfig similarity index 100% rename from boards/snps/nsim/Kconfig rename to boards/snps/nsim/arc_classic/Kconfig diff --git a/boards/snps/nsim/Kconfig.nsim b/boards/snps/nsim/arc_classic/Kconfig.nsim similarity index 100% rename from boards/snps/nsim/Kconfig.nsim rename to boards/snps/nsim/arc_classic/Kconfig.nsim diff --git a/boards/snps/nsim/arc_mpu_regions.c b/boards/snps/nsim/arc_classic/arc_mpu_regions.c similarity index 100% rename from boards/snps/nsim/arc_mpu_regions.c rename to boards/snps/nsim/arc_classic/arc_mpu_regions.c diff --git a/boards/snps/nsim/board.cmake b/boards/snps/nsim/arc_classic/board.cmake similarity index 100% rename from boards/snps/nsim/board.cmake rename to boards/snps/nsim/arc_classic/board.cmake diff --git a/boards/snps/nsim/board.yml b/boards/snps/nsim/arc_classic/board.yml similarity index 100% rename from boards/snps/nsim/board.yml rename to boards/snps/nsim/arc_classic/board.yml diff --git a/boards/snps/nsim/doc/index.rst b/boards/snps/nsim/arc_classic/doc/index.rst similarity index 100% rename from boards/snps/nsim/doc/index.rst rename to boards/snps/nsim/arc_classic/doc/index.rst diff --git a/boards/snps/nsim/haps_arcv3_init.c b/boards/snps/nsim/arc_classic/haps_arcv3_init.c similarity index 100% rename from boards/snps/nsim/haps_arcv3_init.c rename to boards/snps/nsim/arc_classic/haps_arcv3_init.c diff --git a/boards/snps/nsim/nsim-ccm-mem.dtsi b/boards/snps/nsim/arc_classic/nsim-ccm-mem.dtsi similarity index 100% rename from boards/snps/nsim/nsim-ccm-mem.dtsi rename to boards/snps/nsim/arc_classic/nsim-ccm-mem.dtsi diff --git a/boards/snps/nsim/nsim-flash-sram-mem.dtsi b/boards/snps/nsim/arc_classic/nsim-flash-sram-mem.dtsi similarity index 100% rename from boards/snps/nsim/nsim-flash-sram-mem.dtsi rename to boards/snps/nsim/arc_classic/nsim-flash-sram-mem.dtsi diff --git a/boards/snps/nsim/nsim-flat-mem.dtsi b/boards/snps/nsim/arc_classic/nsim-flat-mem.dtsi similarity index 100% rename from boards/snps/nsim/nsim-flat-mem.dtsi rename to boards/snps/nsim/arc_classic/nsim-flat-mem.dtsi diff --git a/boards/snps/nsim/nsim-smp.dtsi b/boards/snps/nsim/arc_classic/nsim-smp.dtsi similarity index 100% rename from boards/snps/nsim/nsim-smp.dtsi rename to boards/snps/nsim/arc_classic/nsim-smp.dtsi diff --git a/boards/snps/nsim/nsim-uart-hostlink.dtsi b/boards/snps/nsim/arc_classic/nsim-uart-hostlink.dtsi similarity index 100% rename from boards/snps/nsim/nsim-uart-hostlink.dtsi rename to boards/snps/nsim/arc_classic/nsim-uart-hostlink.dtsi diff --git a/boards/snps/nsim/nsim-uart-ns16550.dtsi b/boards/snps/nsim/arc_classic/nsim-uart-ns16550.dtsi similarity index 100% rename from boards/snps/nsim/nsim-uart-ns16550.dtsi rename to boards/snps/nsim/arc_classic/nsim-uart-ns16550.dtsi diff --git a/boards/snps/nsim/nsim.dtsi b/boards/snps/nsim/arc_classic/nsim.dtsi similarity index 100% rename from boards/snps/nsim/nsim.dtsi rename to boards/snps/nsim/arc_classic/nsim.dtsi diff --git a/boards/snps/nsim/nsim_em-sec.dtsi b/boards/snps/nsim/arc_classic/nsim_em-sec.dtsi similarity index 100% rename from boards/snps/nsim/nsim_em-sec.dtsi rename to boards/snps/nsim/arc_classic/nsim_em-sec.dtsi diff --git a/boards/snps/nsim/nsim_em.dtsi b/boards/snps/nsim/arc_classic/nsim_em.dtsi similarity index 100% rename from boards/snps/nsim/nsim_em.dtsi rename to boards/snps/nsim/arc_classic/nsim_em.dtsi diff --git a/boards/snps/nsim/nsim_nsim_em.dts b/boards/snps/nsim/arc_classic/nsim_nsim_em.dts similarity index 100% rename from boards/snps/nsim/nsim_nsim_em.dts rename to boards/snps/nsim/arc_classic/nsim_nsim_em.dts diff --git a/boards/snps/nsim/nsim_nsim_em.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_em.yaml similarity index 100% rename from boards/snps/nsim/nsim_nsim_em.yaml rename to boards/snps/nsim/arc_classic/nsim_nsim_em.yaml diff --git a/boards/snps/nsim/nsim_nsim_em11d.dts b/boards/snps/nsim/arc_classic/nsim_nsim_em11d.dts similarity index 100% rename from boards/snps/nsim/nsim_nsim_em11d.dts rename to boards/snps/nsim/arc_classic/nsim_nsim_em11d.dts diff --git a/boards/snps/nsim/nsim_nsim_em11d.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_em11d.yaml similarity index 100% rename from boards/snps/nsim/nsim_nsim_em11d.yaml rename to boards/snps/nsim/arc_classic/nsim_nsim_em11d.yaml diff --git a/boards/snps/nsim/nsim_nsim_em11d_defconfig b/boards/snps/nsim/arc_classic/nsim_nsim_em11d_defconfig similarity index 95% rename from boards/snps/nsim/nsim_nsim_em11d_defconfig rename to boards/snps/nsim/arc_classic/nsim_nsim_em11d_defconfig index 1cdf8a0b67e..2146e4d8b06 100644 --- a/boards/snps/nsim/nsim_nsim_em11d_defconfig +++ b/boards/snps/nsim/arc_classic/nsim_nsim_em11d_defconfig @@ -9,3 +9,4 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS=y +CONFIG_XIP=n diff --git a/boards/snps/nsim/nsim_nsim_em7d_v22.dts b/boards/snps/nsim/arc_classic/nsim_nsim_em7d_v22.dts similarity index 100% rename from boards/snps/nsim/nsim_nsim_em7d_v22.dts rename to boards/snps/nsim/arc_classic/nsim_nsim_em7d_v22.dts diff --git a/boards/snps/nsim/nsim_nsim_em7d_v22.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_em7d_v22.yaml similarity index 100% rename from boards/snps/nsim/nsim_nsim_em7d_v22.yaml rename to boards/snps/nsim/arc_classic/nsim_nsim_em7d_v22.yaml diff --git a/boards/snps/nsim/nsim_nsim_em7d_v22_defconfig b/boards/snps/nsim/arc_classic/nsim_nsim_em7d_v22_defconfig similarity index 95% rename from boards/snps/nsim/nsim_nsim_em7d_v22_defconfig rename to boards/snps/nsim/arc_classic/nsim_nsim_em7d_v22_defconfig index 1cdf8a0b67e..2146e4d8b06 100644 --- a/boards/snps/nsim/nsim_nsim_em7d_v22_defconfig +++ b/boards/snps/nsim/arc_classic/nsim_nsim_em7d_v22_defconfig @@ -9,3 +9,4 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS=y +CONFIG_XIP=n diff --git a/boards/snps/nsim/nsim_nsim_em_defconfig b/boards/snps/nsim/arc_classic/nsim_nsim_em_defconfig similarity index 95% rename from boards/snps/nsim/nsim_nsim_em_defconfig rename to boards/snps/nsim/arc_classic/nsim_nsim_em_defconfig index 1cdf8a0b67e..2146e4d8b06 100644 --- a/boards/snps/nsim/nsim_nsim_em_defconfig +++ b/boards/snps/nsim/arc_classic/nsim_nsim_em_defconfig @@ -9,3 +9,4 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS=y +CONFIG_XIP=n diff --git a/boards/snps/nsim/nsim_nsim_hs.dts b/boards/snps/nsim/arc_classic/nsim_nsim_hs.dts similarity index 100% rename from boards/snps/nsim/nsim_nsim_hs.dts rename to boards/snps/nsim/arc_classic/nsim_nsim_hs.dts diff --git a/boards/snps/nsim/nsim_nsim_hs.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_hs.yaml similarity index 100% rename from boards/snps/nsim/nsim_nsim_hs.yaml rename to boards/snps/nsim/arc_classic/nsim_nsim_hs.yaml diff --git a/boards/snps/nsim/nsim_nsim_hs5x.dts b/boards/snps/nsim/arc_classic/nsim_nsim_hs5x.dts similarity index 100% rename from boards/snps/nsim/nsim_nsim_hs5x.dts rename to boards/snps/nsim/arc_classic/nsim_nsim_hs5x.dts diff --git a/boards/snps/nsim/nsim_nsim_hs5x.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_hs5x.yaml similarity index 100% rename from boards/snps/nsim/nsim_nsim_hs5x.yaml rename to boards/snps/nsim/arc_classic/nsim_nsim_hs5x.yaml diff --git a/boards/snps/nsim/nsim_nsim_hs5x_defconfig b/boards/snps/nsim/arc_classic/nsim_nsim_hs5x_defconfig similarity index 94% rename from boards/snps/nsim/nsim_nsim_hs5x_defconfig rename to boards/snps/nsim/arc_classic/nsim_nsim_hs5x_defconfig index 5a48971e06d..717569e757c 100644 --- a/boards/snps/nsim/nsim_nsim_hs5x_defconfig +++ b/boards/snps/nsim/arc_classic/nsim_nsim_hs5x_defconfig @@ -8,3 +8,4 @@ CONFIG_ARCV2_TIMER=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y +CONFIG_XIP=n diff --git a/boards/snps/nsim/nsim_nsim_hs5x_smp.dts b/boards/snps/nsim/arc_classic/nsim_nsim_hs5x_smp.dts similarity index 100% rename from boards/snps/nsim/nsim_nsim_hs5x_smp.dts rename to boards/snps/nsim/arc_classic/nsim_nsim_hs5x_smp.dts diff --git a/boards/snps/nsim/nsim_nsim_hs5x_smp.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_hs5x_smp.yaml similarity index 100% rename from boards/snps/nsim/nsim_nsim_hs5x_smp.yaml rename to boards/snps/nsim/arc_classic/nsim_nsim_hs5x_smp.yaml diff --git a/boards/snps/nsim/nsim_nsim_hs5x_smp_12cores.dts b/boards/snps/nsim/arc_classic/nsim_nsim_hs5x_smp_12cores.dts similarity index 100% rename from boards/snps/nsim/nsim_nsim_hs5x_smp_12cores.dts rename to boards/snps/nsim/arc_classic/nsim_nsim_hs5x_smp_12cores.dts diff --git a/boards/snps/nsim/nsim_nsim_hs5x_smp_12cores.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_hs5x_smp_12cores.yaml similarity index 100% rename from boards/snps/nsim/nsim_nsim_hs5x_smp_12cores.yaml rename to boards/snps/nsim/arc_classic/nsim_nsim_hs5x_smp_12cores.yaml diff --git a/boards/snps/nsim/nsim_nsim_hs5x_smp_12cores_defconfig b/boards/snps/nsim/arc_classic/nsim_nsim_hs5x_smp_12cores_defconfig similarity index 100% rename from boards/snps/nsim/nsim_nsim_hs5x_smp_12cores_defconfig rename to boards/snps/nsim/arc_classic/nsim_nsim_hs5x_smp_12cores_defconfig diff --git a/boards/snps/nsim/nsim_nsim_hs5x_smp_defconfig b/boards/snps/nsim/arc_classic/nsim_nsim_hs5x_smp_defconfig similarity index 95% rename from boards/snps/nsim/nsim_nsim_hs5x_smp_defconfig rename to boards/snps/nsim/arc_classic/nsim_nsim_hs5x_smp_defconfig index c55df123e9f..0b02b73960a 100644 --- a/boards/snps/nsim/nsim_nsim_hs5x_smp_defconfig +++ b/boards/snps/nsim/arc_classic/nsim_nsim_hs5x_smp_defconfig @@ -11,3 +11,4 @@ CONFIG_SERIAL=y CONFIG_SMP=y CONFIG_MP_MAX_NUM_CPUS=2 CONFIG_TICKET_SPINLOCKS=y +CONFIG_XIP=n diff --git a/boards/snps/nsim/nsim_nsim_hs6x.dts b/boards/snps/nsim/arc_classic/nsim_nsim_hs6x.dts similarity index 100% rename from boards/snps/nsim/nsim_nsim_hs6x.dts rename to boards/snps/nsim/arc_classic/nsim_nsim_hs6x.dts diff --git a/boards/snps/nsim/nsim_nsim_hs6x.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_hs6x.yaml similarity index 100% rename from boards/snps/nsim/nsim_nsim_hs6x.yaml rename to boards/snps/nsim/arc_classic/nsim_nsim_hs6x.yaml diff --git a/boards/snps/nsim/nsim_nsim_hs6x_defconfig b/boards/snps/nsim/arc_classic/nsim_nsim_hs6x_defconfig similarity index 94% rename from boards/snps/nsim/nsim_nsim_hs6x_defconfig rename to boards/snps/nsim/arc_classic/nsim_nsim_hs6x_defconfig index 5a48971e06d..717569e757c 100644 --- a/boards/snps/nsim/nsim_nsim_hs6x_defconfig +++ b/boards/snps/nsim/arc_classic/nsim_nsim_hs6x_defconfig @@ -8,3 +8,4 @@ CONFIG_ARCV2_TIMER=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y +CONFIG_XIP=n diff --git a/boards/snps/nsim/nsim_nsim_hs6x_smp.dts b/boards/snps/nsim/arc_classic/nsim_nsim_hs6x_smp.dts similarity index 100% rename from boards/snps/nsim/nsim_nsim_hs6x_smp.dts rename to boards/snps/nsim/arc_classic/nsim_nsim_hs6x_smp.dts diff --git a/boards/snps/nsim/nsim_nsim_hs6x_smp.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_hs6x_smp.yaml similarity index 100% rename from boards/snps/nsim/nsim_nsim_hs6x_smp.yaml rename to boards/snps/nsim/arc_classic/nsim_nsim_hs6x_smp.yaml diff --git a/boards/snps/nsim/nsim_nsim_hs6x_smp_12cores.dts b/boards/snps/nsim/arc_classic/nsim_nsim_hs6x_smp_12cores.dts similarity index 100% rename from boards/snps/nsim/nsim_nsim_hs6x_smp_12cores.dts rename to boards/snps/nsim/arc_classic/nsim_nsim_hs6x_smp_12cores.dts diff --git a/boards/snps/nsim/nsim_nsim_hs6x_smp_12cores.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_hs6x_smp_12cores.yaml similarity index 100% rename from boards/snps/nsim/nsim_nsim_hs6x_smp_12cores.yaml rename to boards/snps/nsim/arc_classic/nsim_nsim_hs6x_smp_12cores.yaml diff --git a/boards/snps/nsim/nsim_nsim_hs6x_smp_12cores_defconfig b/boards/snps/nsim/arc_classic/nsim_nsim_hs6x_smp_12cores_defconfig similarity index 100% rename from boards/snps/nsim/nsim_nsim_hs6x_smp_12cores_defconfig rename to boards/snps/nsim/arc_classic/nsim_nsim_hs6x_smp_12cores_defconfig diff --git a/boards/snps/nsim/nsim_nsim_hs6x_smp_defconfig b/boards/snps/nsim/arc_classic/nsim_nsim_hs6x_smp_defconfig similarity index 95% rename from boards/snps/nsim/nsim_nsim_hs6x_smp_defconfig rename to boards/snps/nsim/arc_classic/nsim_nsim_hs6x_smp_defconfig index c55df123e9f..0b02b73960a 100644 --- a/boards/snps/nsim/nsim_nsim_hs6x_smp_defconfig +++ b/boards/snps/nsim/arc_classic/nsim_nsim_hs6x_smp_defconfig @@ -11,3 +11,4 @@ CONFIG_SERIAL=y CONFIG_SMP=y CONFIG_MP_MAX_NUM_CPUS=2 CONFIG_TICKET_SPINLOCKS=y +CONFIG_XIP=n diff --git a/boards/snps/nsim/nsim_nsim_hs_defconfig b/boards/snps/nsim/arc_classic/nsim_nsim_hs_defconfig similarity index 94% rename from boards/snps/nsim/nsim_nsim_hs_defconfig rename to boards/snps/nsim/arc_classic/nsim_nsim_hs_defconfig index 123983e3241..d22ebd5ea25 100644 --- a/boards/snps/nsim/nsim_nsim_hs_defconfig +++ b/boards/snps/nsim/arc_classic/nsim_nsim_hs_defconfig @@ -8,3 +8,4 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_ARC_MPU_ENABLE=y +CONFIG_XIP=n diff --git a/boards/snps/nsim/nsim_nsim_hs_flash_xip.dts b/boards/snps/nsim/arc_classic/nsim_nsim_hs_flash_xip.dts similarity index 100% rename from boards/snps/nsim/nsim_nsim_hs_flash_xip.dts rename to boards/snps/nsim/arc_classic/nsim_nsim_hs_flash_xip.dts diff --git a/boards/snps/nsim/nsim_nsim_hs_flash_xip.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_hs_flash_xip.yaml similarity index 100% rename from boards/snps/nsim/nsim_nsim_hs_flash_xip.yaml rename to boards/snps/nsim/arc_classic/nsim_nsim_hs_flash_xip.yaml diff --git a/boards/snps/nsim/nsim_nsim_hs_flash_xip_defconfig b/boards/snps/nsim/arc_classic/nsim_nsim_hs_flash_xip_defconfig similarity index 100% rename from boards/snps/nsim/nsim_nsim_hs_flash_xip_defconfig rename to boards/snps/nsim/arc_classic/nsim_nsim_hs_flash_xip_defconfig diff --git a/boards/snps/nsim/nsim_nsim_hs_hostlink.dts b/boards/snps/nsim/arc_classic/nsim_nsim_hs_hostlink.dts similarity index 100% rename from boards/snps/nsim/nsim_nsim_hs_hostlink.dts rename to boards/snps/nsim/arc_classic/nsim_nsim_hs_hostlink.dts diff --git a/boards/snps/nsim/nsim_nsim_hs_hostlink.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_hs_hostlink.yaml similarity index 100% rename from boards/snps/nsim/nsim_nsim_hs_hostlink.yaml rename to boards/snps/nsim/arc_classic/nsim_nsim_hs_hostlink.yaml diff --git a/boards/snps/nsim/nsim_nsim_hs_hostlink_defconfig b/boards/snps/nsim/arc_classic/nsim_nsim_hs_hostlink_defconfig similarity index 94% rename from boards/snps/nsim/nsim_nsim_hs_hostlink_defconfig rename to boards/snps/nsim/arc_classic/nsim_nsim_hs_hostlink_defconfig index 123983e3241..d22ebd5ea25 100644 --- a/boards/snps/nsim/nsim_nsim_hs_hostlink_defconfig +++ b/boards/snps/nsim/arc_classic/nsim_nsim_hs_hostlink_defconfig @@ -8,3 +8,4 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_ARC_MPU_ENABLE=y +CONFIG_XIP=n diff --git a/boards/snps/nsim/nsim_nsim_hs_mpuv6.dts b/boards/snps/nsim/arc_classic/nsim_nsim_hs_mpuv6.dts similarity index 100% rename from boards/snps/nsim/nsim_nsim_hs_mpuv6.dts rename to boards/snps/nsim/arc_classic/nsim_nsim_hs_mpuv6.dts diff --git a/boards/snps/nsim/nsim_nsim_hs_mpuv6.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_hs_mpuv6.yaml similarity index 100% rename from boards/snps/nsim/nsim_nsim_hs_mpuv6.yaml rename to boards/snps/nsim/arc_classic/nsim_nsim_hs_mpuv6.yaml diff --git a/boards/snps/nsim/nsim_nsim_hs_mpuv6_defconfig b/boards/snps/nsim/arc_classic/nsim_nsim_hs_mpuv6_defconfig similarity index 100% rename from boards/snps/nsim/nsim_nsim_hs_mpuv6_defconfig rename to boards/snps/nsim/arc_classic/nsim_nsim_hs_mpuv6_defconfig diff --git a/boards/snps/nsim/nsim_nsim_hs_smp.dts b/boards/snps/nsim/arc_classic/nsim_nsim_hs_smp.dts similarity index 100% rename from boards/snps/nsim/nsim_nsim_hs_smp.dts rename to boards/snps/nsim/arc_classic/nsim_nsim_hs_smp.dts diff --git a/boards/snps/nsim/nsim_nsim_hs_smp.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_hs_smp.yaml similarity index 100% rename from boards/snps/nsim/nsim_nsim_hs_smp.yaml rename to boards/snps/nsim/arc_classic/nsim_nsim_hs_smp.yaml diff --git a/boards/snps/nsim/nsim_nsim_hs_smp_defconfig b/boards/snps/nsim/arc_classic/nsim_nsim_hs_smp_defconfig similarity index 95% rename from boards/snps/nsim/nsim_nsim_hs_smp_defconfig rename to boards/snps/nsim/arc_classic/nsim_nsim_hs_smp_defconfig index 351a2b9660b..60b058efa91 100644 --- a/boards/snps/nsim/nsim_nsim_hs_smp_defconfig +++ b/boards/snps/nsim/arc_classic/nsim_nsim_hs_smp_defconfig @@ -11,3 +11,4 @@ CONFIG_ARC_MPU_ENABLE=n CONFIG_SMP=y CONFIG_MP_MAX_NUM_CPUS=2 CONFIG_TICKET_SPINLOCKS=y +CONFIG_XIP=n diff --git a/boards/snps/nsim/nsim_nsim_hs_sram.dts b/boards/snps/nsim/arc_classic/nsim_nsim_hs_sram.dts similarity index 100% rename from boards/snps/nsim/nsim_nsim_hs_sram.dts rename to boards/snps/nsim/arc_classic/nsim_nsim_hs_sram.dts diff --git a/boards/snps/nsim/nsim_nsim_hs_sram.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_hs_sram.yaml similarity index 100% rename from boards/snps/nsim/nsim_nsim_hs_sram.yaml rename to boards/snps/nsim/arc_classic/nsim_nsim_hs_sram.yaml diff --git a/boards/snps/nsim/nsim_nsim_hs_sram_defconfig b/boards/snps/nsim/arc_classic/nsim_nsim_hs_sram_defconfig similarity index 95% rename from boards/snps/nsim/nsim_nsim_hs_sram_defconfig rename to boards/snps/nsim/arc_classic/nsim_nsim_hs_sram_defconfig index 1ee8bc1dad0..0d0380c8e64 100644 --- a/boards/snps/nsim/nsim_nsim_hs_sram_defconfig +++ b/boards/snps/nsim/arc_classic/nsim_nsim_hs_sram_defconfig @@ -9,3 +9,4 @@ CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_ARC_MPU_ENABLE=y CONFIG_HARVARD=n +CONFIG_XIP=n diff --git a/boards/snps/nsim/nsim_nsim_sem.dts b/boards/snps/nsim/arc_classic/nsim_nsim_sem.dts similarity index 100% rename from boards/snps/nsim/nsim_nsim_sem.dts rename to boards/snps/nsim/arc_classic/nsim_nsim_sem.dts diff --git a/boards/snps/nsim/nsim_nsim_sem.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_sem.yaml similarity index 100% rename from boards/snps/nsim/nsim_nsim_sem.yaml rename to boards/snps/nsim/arc_classic/nsim_nsim_sem.yaml diff --git a/boards/snps/nsim/nsim_nsim_sem_defconfig b/boards/snps/nsim/arc_classic/nsim_nsim_sem_defconfig similarity index 95% rename from boards/snps/nsim/nsim_nsim_sem_defconfig rename to boards/snps/nsim/arc_classic/nsim_nsim_sem_defconfig index deb2c9c0571..fb80da70390 100644 --- a/boards/snps/nsim/nsim_nsim_sem_defconfig +++ b/boards/snps/nsim/arc_classic/nsim_nsim_sem_defconfig @@ -9,3 +9,4 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_TRUSTED_EXECUTION_SECURE=y +CONFIG_XIP=n diff --git a/boards/snps/nsim/nsim_nsim_sem_mpu_stack_guard.dts b/boards/snps/nsim/arc_classic/nsim_nsim_sem_mpu_stack_guard.dts similarity index 100% rename from boards/snps/nsim/nsim_nsim_sem_mpu_stack_guard.dts rename to boards/snps/nsim/arc_classic/nsim_nsim_sem_mpu_stack_guard.dts diff --git a/boards/snps/nsim/nsim_nsim_sem_mpu_stack_guard.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_sem_mpu_stack_guard.yaml similarity index 100% rename from boards/snps/nsim/nsim_nsim_sem_mpu_stack_guard.yaml rename to boards/snps/nsim/arc_classic/nsim_nsim_sem_mpu_stack_guard.yaml diff --git a/boards/snps/nsim/nsim_nsim_sem_mpu_stack_guard_defconfig b/boards/snps/nsim/arc_classic/nsim_nsim_sem_mpu_stack_guard_defconfig similarity index 95% rename from boards/snps/nsim/nsim_nsim_sem_mpu_stack_guard_defconfig rename to boards/snps/nsim/arc_classic/nsim_nsim_sem_mpu_stack_guard_defconfig index 1162d5f132b..ce7181282ea 100644 --- a/boards/snps/nsim/nsim_nsim_sem_mpu_stack_guard_defconfig +++ b/boards/snps/nsim/arc_classic/nsim_nsim_sem_mpu_stack_guard_defconfig @@ -10,3 +10,4 @@ CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_TRUSTED_EXECUTION_SECURE=y CONFIG_ARC_HAS_STACK_CHECKING=n +CONFIG_XIP=n diff --git a/boards/snps/nsim/nsim_nsim_vpx5.dts b/boards/snps/nsim/arc_classic/nsim_nsim_vpx5.dts similarity index 100% rename from boards/snps/nsim/nsim_nsim_vpx5.dts rename to boards/snps/nsim/arc_classic/nsim_nsim_vpx5.dts diff --git a/boards/snps/nsim/nsim_nsim_vpx5.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_vpx5.yaml similarity index 100% rename from boards/snps/nsim/nsim_nsim_vpx5.yaml rename to boards/snps/nsim/arc_classic/nsim_nsim_vpx5.yaml diff --git a/boards/snps/nsim/nsim_nsim_vpx5_defconfig b/boards/snps/nsim/arc_classic/nsim_nsim_vpx5_defconfig similarity index 100% rename from boards/snps/nsim/nsim_nsim_vpx5_defconfig rename to boards/snps/nsim/arc_classic/nsim_nsim_vpx5_defconfig diff --git a/boards/snps/nsim/support/mdb_em.args b/boards/snps/nsim/arc_classic/support/mdb_em.args similarity index 100% rename from boards/snps/nsim/support/mdb_em.args rename to boards/snps/nsim/arc_classic/support/mdb_em.args diff --git a/boards/snps/nsim/support/mdb_em11d.args b/boards/snps/nsim/arc_classic/support/mdb_em11d.args similarity index 100% rename from boards/snps/nsim/support/mdb_em11d.args rename to boards/snps/nsim/arc_classic/support/mdb_em11d.args diff --git a/boards/snps/nsim/support/mdb_em7d_v22.args b/boards/snps/nsim/arc_classic/support/mdb_em7d_v22.args similarity index 100% rename from boards/snps/nsim/support/mdb_em7d_v22.args rename to boards/snps/nsim/arc_classic/support/mdb_em7d_v22.args diff --git a/boards/snps/nsim/support/mdb_hs.args b/boards/snps/nsim/arc_classic/support/mdb_hs.args similarity index 100% rename from boards/snps/nsim/support/mdb_hs.args rename to boards/snps/nsim/arc_classic/support/mdb_hs.args diff --git a/boards/snps/nsim/support/mdb_hs5x.args b/boards/snps/nsim/arc_classic/support/mdb_hs5x.args similarity index 100% rename from boards/snps/nsim/support/mdb_hs5x.args rename to boards/snps/nsim/arc_classic/support/mdb_hs5x.args diff --git a/boards/snps/nsim/support/mdb_hs5x_smp.args b/boards/snps/nsim/arc_classic/support/mdb_hs5x_smp.args similarity index 100% rename from boards/snps/nsim/support/mdb_hs5x_smp.args rename to boards/snps/nsim/arc_classic/support/mdb_hs5x_smp.args diff --git a/boards/snps/nsim/support/mdb_hs5x_smp_12cores.args b/boards/snps/nsim/arc_classic/support/mdb_hs5x_smp_12cores.args similarity index 100% rename from boards/snps/nsim/support/mdb_hs5x_smp_12cores.args rename to boards/snps/nsim/arc_classic/support/mdb_hs5x_smp_12cores.args diff --git a/boards/snps/nsim/support/mdb_hs6x.args b/boards/snps/nsim/arc_classic/support/mdb_hs6x.args similarity index 100% rename from boards/snps/nsim/support/mdb_hs6x.args rename to boards/snps/nsim/arc_classic/support/mdb_hs6x.args diff --git a/boards/snps/nsim/support/mdb_hs6x_smp.args b/boards/snps/nsim/arc_classic/support/mdb_hs6x_smp.args similarity index 100% rename from boards/snps/nsim/support/mdb_hs6x_smp.args rename to boards/snps/nsim/arc_classic/support/mdb_hs6x_smp.args diff --git a/boards/snps/nsim/support/mdb_hs6x_smp_12cores.args b/boards/snps/nsim/arc_classic/support/mdb_hs6x_smp_12cores.args similarity index 100% rename from boards/snps/nsim/support/mdb_hs6x_smp_12cores.args rename to boards/snps/nsim/arc_classic/support/mdb_hs6x_smp_12cores.args diff --git a/boards/snps/nsim/support/mdb_hs_flash_xip.args b/boards/snps/nsim/arc_classic/support/mdb_hs_flash_xip.args similarity index 100% rename from boards/snps/nsim/support/mdb_hs_flash_xip.args rename to boards/snps/nsim/arc_classic/support/mdb_hs_flash_xip.args diff --git a/boards/snps/nsim/support/mdb_hs_hostlink.args b/boards/snps/nsim/arc_classic/support/mdb_hs_hostlink.args similarity index 100% rename from boards/snps/nsim/support/mdb_hs_hostlink.args rename to boards/snps/nsim/arc_classic/support/mdb_hs_hostlink.args diff --git a/boards/snps/nsim/support/mdb_hs_mpuv6.args b/boards/snps/nsim/arc_classic/support/mdb_hs_mpuv6.args similarity index 100% rename from boards/snps/nsim/support/mdb_hs_mpuv6.args rename to boards/snps/nsim/arc_classic/support/mdb_hs_mpuv6.args diff --git a/boards/snps/nsim/support/mdb_hs_smp.args b/boards/snps/nsim/arc_classic/support/mdb_hs_smp.args similarity index 100% rename from boards/snps/nsim/support/mdb_hs_smp.args rename to boards/snps/nsim/arc_classic/support/mdb_hs_smp.args diff --git a/boards/snps/nsim/support/mdb_hs_sram.args b/boards/snps/nsim/arc_classic/support/mdb_hs_sram.args similarity index 100% rename from boards/snps/nsim/support/mdb_hs_sram.args rename to boards/snps/nsim/arc_classic/support/mdb_hs_sram.args diff --git a/boards/snps/nsim/support/mdb_sem.args b/boards/snps/nsim/arc_classic/support/mdb_sem.args similarity index 100% rename from boards/snps/nsim/support/mdb_sem.args rename to boards/snps/nsim/arc_classic/support/mdb_sem.args diff --git a/boards/snps/nsim/support/mdb_sem_mpu_stack_guard.args b/boards/snps/nsim/arc_classic/support/mdb_sem_mpu_stack_guard.args similarity index 100% rename from boards/snps/nsim/support/mdb_sem_mpu_stack_guard.args rename to boards/snps/nsim/arc_classic/support/mdb_sem_mpu_stack_guard.args diff --git a/boards/snps/nsim/support/mdb_vpx5.args b/boards/snps/nsim/arc_classic/support/mdb_vpx5.args similarity index 100% rename from boards/snps/nsim/support/mdb_vpx5.args rename to boards/snps/nsim/arc_classic/support/mdb_vpx5.args diff --git a/boards/snps/nsim/support/nsim_em.props b/boards/snps/nsim/arc_classic/support/nsim_em.props similarity index 100% rename from boards/snps/nsim/support/nsim_em.props rename to boards/snps/nsim/arc_classic/support/nsim_em.props diff --git a/boards/snps/nsim/support/nsim_em11d.props b/boards/snps/nsim/arc_classic/support/nsim_em11d.props similarity index 100% rename from boards/snps/nsim/support/nsim_em11d.props rename to boards/snps/nsim/arc_classic/support/nsim_em11d.props diff --git a/boards/snps/nsim/support/nsim_em7d_v22.props b/boards/snps/nsim/arc_classic/support/nsim_em7d_v22.props similarity index 100% rename from boards/snps/nsim/support/nsim_em7d_v22.props rename to boards/snps/nsim/arc_classic/support/nsim_em7d_v22.props diff --git a/boards/snps/nsim/support/nsim_hs.props b/boards/snps/nsim/arc_classic/support/nsim_hs.props similarity index 100% rename from boards/snps/nsim/support/nsim_hs.props rename to boards/snps/nsim/arc_classic/support/nsim_hs.props diff --git a/boards/snps/nsim/support/nsim_hs5x.props b/boards/snps/nsim/arc_classic/support/nsim_hs5x.props similarity index 100% rename from boards/snps/nsim/support/nsim_hs5x.props rename to boards/snps/nsim/arc_classic/support/nsim_hs5x.props diff --git a/boards/snps/nsim/support/nsim_hs6x.props b/boards/snps/nsim/arc_classic/support/nsim_hs6x.props similarity index 100% rename from boards/snps/nsim/support/nsim_hs6x.props rename to boards/snps/nsim/arc_classic/support/nsim_hs6x.props diff --git a/boards/snps/nsim/support/nsim_hs_flash_xip.props b/boards/snps/nsim/arc_classic/support/nsim_hs_flash_xip.props similarity index 100% rename from boards/snps/nsim/support/nsim_hs_flash_xip.props rename to boards/snps/nsim/arc_classic/support/nsim_hs_flash_xip.props diff --git a/boards/snps/nsim/support/nsim_hs_hostlink.props b/boards/snps/nsim/arc_classic/support/nsim_hs_hostlink.props similarity index 100% rename from boards/snps/nsim/support/nsim_hs_hostlink.props rename to boards/snps/nsim/arc_classic/support/nsim_hs_hostlink.props diff --git a/boards/snps/nsim/support/nsim_hs_mpuv6.props b/boards/snps/nsim/arc_classic/support/nsim_hs_mpuv6.props similarity index 100% rename from boards/snps/nsim/support/nsim_hs_mpuv6.props rename to boards/snps/nsim/arc_classic/support/nsim_hs_mpuv6.props diff --git a/boards/snps/nsim/support/nsim_hs_sram.props b/boards/snps/nsim/arc_classic/support/nsim_hs_sram.props similarity index 100% rename from boards/snps/nsim/support/nsim_hs_sram.props rename to boards/snps/nsim/arc_classic/support/nsim_hs_sram.props diff --git a/boards/snps/nsim/support/nsim_sem.props b/boards/snps/nsim/arc_classic/support/nsim_sem.props similarity index 100% rename from boards/snps/nsim/support/nsim_sem.props rename to boards/snps/nsim/arc_classic/support/nsim_sem.props diff --git a/boards/snps/nsim/support/nsim_sem_mpu_stack_guard.props b/boards/snps/nsim/arc_classic/support/nsim_sem_mpu_stack_guard.props similarity index 100% rename from boards/snps/nsim/support/nsim_sem_mpu_stack_guard.props rename to boards/snps/nsim/arc_classic/support/nsim_sem_mpu_stack_guard.props diff --git a/boards/snps/nsim/support/nsim_vpx5.props b/boards/snps/nsim/arc_classic/support/nsim_vpx5.props similarity index 100% rename from boards/snps/nsim/support/nsim_vpx5.props rename to boards/snps/nsim/arc_classic/support/nsim_vpx5.props diff --git a/boards/snps/nsim/arc_v/Kconfig.defconfig b/boards/snps/nsim/arc_v/Kconfig.defconfig new file mode 100644 index 00000000000..469d5e2a92b --- /dev/null +++ b/boards/snps/nsim/arc_v/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Synopsys, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NSIM_ARC_V_RMX100 + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 5000000 + +endif # BOARD_NSIM_ARC_V_RMX100 diff --git a/boards/snps/nsim/arc_v/Kconfig.nsim_arc_v b/boards/snps/nsim/arc_v/Kconfig.nsim_arc_v new file mode 100644 index 00000000000..600a7e7499d --- /dev/null +++ b/boards/snps/nsim/arc_v/Kconfig.nsim_arc_v @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Synopsys, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NSIM_ARC_V + select SOC_RMX100 if BOARD_NSIM_ARC_V_RMX100 diff --git a/boards/snps/nsim/arc_v/board.cmake b/boards/snps/nsim/arc_v/board.cmake new file mode 100644 index 00000000000..2c0230917d1 --- /dev/null +++ b/boards/snps/nsim/arc_v/board.cmake @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: Apache-2.0 + +set(SUPPORTED_EMU_PLATFORMS nsim) + +string(SUBSTRING "${BOARD_QUALIFIERS}" 1 -1 NSIM_BASE_FILENAME) +string(REPLACE "/" "_" NSIM_BASE_FILENAME "${NSIM_BASE_FILENAME}") + +board_set_flasher_ifnset(arc-nsim) +board_set_debugger_ifnset(arc-nsim) + +set(NSIM_PROPS "${NSIM_BASE_FILENAME}.props") +board_runner_args(arc-nsim "--props=${NSIM_PROPS}") + +board_finalize_runner_args(arc-nsim) +include(${ZEPHYR_BASE}/boards/common/mdb-nsim.board.cmake) +include(${ZEPHYR_BASE}/boards/common/mdb-hw.board.cmake) diff --git a/boards/snps/nsim/arc_v/board.yml b/boards/snps/nsim/arc_v/board.yml new file mode 100644 index 00000000000..a91eaffd90a --- /dev/null +++ b/boards/snps/nsim/arc_v/board.yml @@ -0,0 +1,5 @@ +board: + name: nsim_arc_v + vendor: snps + socs: + - name: rmx100 diff --git a/boards/snps/nsim/arc_v/doc/index.rst b/boards/snps/nsim/arc_v/doc/index.rst new file mode 100644 index 00000000000..22a0ecc23e9 --- /dev/null +++ b/boards/snps/nsim/arc_v/doc/index.rst @@ -0,0 +1,199 @@ +.. _nsim_arc_v: + +DesignWare RISC-V nSIM and HAPS FPGA boards +########################################### + +Overview +******** + +This platform can be used to run Zephyr RTOS on the widest possible range of Synopsys RISC-V processors in +simulation with `Designware ARC nSIM`_ or run same images on FPGA prototyping platform `HAPS`_. The +platform includes the following features: + +* RISC-V processor core, which implements riscv32 ISA +* Virtual serial console (a standard ``ns16550`` UART model) + +Supported board targets for that platform are listed below: + +* ``nsim_arc_v/rmx100`` - Synopsys RISC-V RMX100 core + +.. _board_nsim_arc_v_prop_files: + +It is recommended to look at precise description of a particular board target in ``.props`` +files in :zephyr_file:`boards/snps/nsim_arc_v/support/` directory to understand +which options are configured and so will be used on invocation of the simulator. + +.. warning:: + All nSIM targets are used for demo and testing purposes. They are not meant to + represent any real system and so might be renamed, removed or modified at any point. + +Programming and Debugging +************************* + +Required Hardware and Software +============================== + +To run single-core Zephyr RTOS applications in simulation on this board, +either `DesignWare ARC nSIM`_ or `DesignWare ARC Free nSIM`_ is required. + +Building & Running Sample Applications +====================================== + +Most board targets support building with both GNU and ARC MWDT toolchains, however +there might be exceptions from that, especially for newly added targets. You can check supported +toolchains for the board targets in the corresponding ``.yaml`` file. + +I.e. for the ``nsim_arc_v/rmx100`` board we can check :zephyr_file:`boards/snps/nsim_arc_v/nsim_arc_v_rmx100.yaml` + +The supported toolchains are listed in ``toolchain:`` array in ``.yaml`` file, where we can find: + +* **zephyr** - implies RISC-V GNU toolchain from Zephyr SDK. You can find more information about + Zephyr SDK :ref:`here `. +* **cross-compile** - implies RISC-V GNU cross toolchain, which is not a part of Zephyr SDK. Note that + some (especially new) board targets may declare ``cross-compile`` toolchain support without + ``zephyr`` toolchain support because corresponding target CPU support hasn't been added to Zephyr + SDK yet. You can find more information about its usage here: :ref:`here `. +* **arcmwdt** - implies proprietary ARC MWDT toolchain. You can find more information about its + usage here: :ref:`here `. + +.. note:: + Note that even if both GNU and MWDT toolchain support is declared for the target some tests or + samples can be only built with either GNU or MWDT toolchain due to some features limited to a + particular toolchain. + +Use this configuration to run basic Zephyr applications and kernel tests in +nSIM, for example, with the :zephyr:code-sample:`synchronization` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: nsim_arc_v/rmx100 + :goals: flash + +This will build an image with the synchronization sample app, boot it using +nSIM, and display the following console output: + +.. code-block:: console + + *** Booting Zephyr OS build zephyr-v3.2.0-3948-gd351a024dc87 *** + thread_a: Hello World from cpu 0 on nsim_arc_v! + thread_b: Hello World from cpu 0 on nsim_arc_v! + thread_a: Hello World from cpu 0 on nsim_arc_v! + thread_b: Hello World from cpu 0 on nsim_arc_v! + thread_a: Hello World from cpu 0 on nsim_arc_v! + +.. note:: + To exit the simulator, use :kbd:`Ctrl+]`, then :kbd:`Ctrl+c` + +.. _board_nsim_arc_v_verbose_build: + +.. tip:: + You can get more details about the building process by running build in verbose mode. It can be + done by passing ``-v`` flag to the west: ``west -v build -b nsim_hs samples/synchronization`` + +Debugging +========= + +.. _board_nsim_arc_v_debugging_gdb: + +Debugging with GDB +------------------ + +.. note:: + Debugging on nSIM via GDB is only supported on single-core targets (which use standalone + nSIM). + +.. note:: + The normal ``west debug`` command won't work for debugging applications using nsim boards + because both the nSIM simulator and the debugger use the same console for + input / output. + In case of GDB debugger it's possible to use a separate terminal windows for GDB and nSIM to + avoid intermixing their output. + +After building your application, open two terminal windows. In terminal one, use nSIM to start a GDB +server and wait for a remote connection with following command: + +.. code-block:: console + + west debugserver --runner arc-nsim + +In terminal two, connect to the GDB server using RISC-V GDB. You can find it in Zephyr SDK: + +* you should use :file:`riscv64-zephyr-elf-gdb` + +This command loads the symbol table from the elf binary file, for example the +:file:`build/zephyr/zephyr.elf` file: + +.. code-block:: console + + riscv64-zephyr-elf-gdb -ex 'target remote localhost:3333' -ex load build/zephyr/zephyr.elf + +Now the debug environment has been set up, and it's possible to debug the application with gdb +commands. + +Modifying the configuration +*************************** + +If modification of existing nsim configuration is required or even there's a need in creation of a +new one it's required to maintain alignment between + +* Zephyr OS configuration +* nSIM configuration +* GNU & MWDT toolchain compiler options + +.. note:: + The ``.tcf`` configuration files are not supported by Zephyr directly. There are multiple + reasons for that. ``.tcf`` perfectly suits building of bare-metal single-thread application - + in that case all the compiler options from ``.tcf`` are passed to the compiler, so all the HW + features are used by the application and optimal code is being generated. + The situation is completely different when multi-thread feature-rich operation system is + considered. Of course it is still possible to build all the code with all the + options from ``.tcf`` - but that may be far from optimal solution. For example, such approach + require so save & restore full register context for all tasks (and sometimes even for + interrupts). And for DSP-enabled or for FPU-enabled systems that leads to dozens of extra + registers save and restore even if the most of the user and kernel tasks don't actually use + DSP or FPU. Instead we prefer to fine-tune the HW features usage which (with all its pros) + require us to maintain them separately from ``.tcf`` configuration. + + +Zephyr OS configuration +======================= + +Zephyr OS configuration is defined via Kconfig and Device tree. These are non RISC-V-specific +mechanisms which are described in :ref:`board porting guide `. + +It is advised to look for ``_defconfig``, ``.dts`` and +``.yaml`` as an entry point for board target. + +nSIM configuration +================== + +nSIM configuration is defined in :ref:`props files `. +Generally they are identical to the values from corresponding ``.tcf`` configuration with few +exceptions: + +* The UART model is added +* CLINT model is added + +GNU & MWDT toolchain compiler options +===================================== + +The hardware-specific compiler options are set in corresponding SoC cmake file. For ``nsim_arc_v`` board +it is :zephyr_file:`soc/snps/nsim/arc_v/CMakeLists.txt`. + +For the GNU toolchain the basic configuration is set via ``-march`` which is defined in generic code +and based on the selected CPU model via Kconfig. It still can be forcefully set to required value +on SoC level. + +.. note:: + The non hardware-specific compiler options like optimizations, library selections, C / C++ + language options are still set in Zephyr generic code. It could be observed by + :ref:`running build in verbose mode `. + +References +********** + +.. _Designware ARC nSIM: https://www.synopsys.com/dw/ipdir.php?ds=sim_nsim +.. _DesignWare ARC Free nSIM: https://www.synopsys.com/cgi-bin/dwarcnsim/req1.cgi +.. _HAPS: https://www.synopsys.com/verification/prototyping/haps.html +.. _ARC MWDT: https://www.synopsys.com/dw/ipdir.php?ds=sw_metaware diff --git a/boards/snps/nsim/arc_v/nsim_arc_v_rmx100.dts b/boards/snps/nsim/arc_v/nsim_arc_v_rmx100.dts new file mode 100644 index 00000000000..351b88c2679 --- /dev/null +++ b/boards/snps/nsim/arc_v/nsim_arc_v_rmx100.dts @@ -0,0 +1,24 @@ +/dts-v1/; + +#include "rmx100.dtsi" + +/ { + model = "Synopsys RMX100"; + compatible = "snps,rmx100"; + + aliases { + uart-0 = &uart0; + }; + + chosen { + zephyr,sram = &ddr0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; +}; diff --git a/boards/snps/nsim/arc_v/nsim_arc_v_rmx100.yaml b/boards/snps/nsim/arc_v/nsim_arc_v_rmx100.yaml new file mode 100644 index 00000000000..3639ab453f8 --- /dev/null +++ b/boards/snps/nsim/arc_v/nsim_arc_v_rmx100.yaml @@ -0,0 +1,15 @@ +identifier: nsim_arc_v/rmx100 +name: Synopsys rmx100 +simulation: nsim +simulation_exec: nsimdrv +type: sim +arch: riscv +toolchain: + - zephyr + - cross-compile + - arcmwdt +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/snps/nsim/arc_v/nsim_arc_v_rmx100_defconfig b/boards/snps/nsim/arc_v/nsim_arc_v_rmx100_defconfig new file mode 100644 index 00000000000..17283e7b664 --- /dev/null +++ b/boards/snps/nsim/arc_v/nsim_arc_v_rmx100_defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Synopsys, Inc. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_XIP=n +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_INCLUDE_RESET_VECTOR=y +CONFIG_LOG=y diff --git a/boards/snps/nsim/arc_v/rmx100.dtsi b/boards/snps/nsim/arc_v/rmx100.dtsi new file mode 100644 index 00000000000..89586284c61 --- /dev/null +++ b/boards/snps/nsim/arc_v/rmx100.dtsi @@ -0,0 +1,8 @@ +#include "rmx1xx.dtsi" + +/ { + ddr0: memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; +}; diff --git a/boards/snps/nsim/arc_v/rmx1xx.dtsi b/boards/snps/nsim/arc_v/rmx1xx.dtsi new file mode 100644 index 00000000000..9480922e217 --- /dev/null +++ b/boards/snps/nsim/arc_v/rmx1xx.dtsi @@ -0,0 +1,55 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + timebase-frequency = <5000000>; + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "snps,av5rmx", "riscv"; + device_type = "cpu"; + reg = <0>; + clock-frequency = <5000000>; + riscv,isa = "rv32imac_zicsr_zifencei"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; + + soc { + compatible = "simple-bus"; + ranges; + interrupt-parent = <&clint>; + #address-cells = <1>; + #size-cells = <1>; + + clint: clint@2000000 { + compatible = "sifive,clint0"; + reg = <0x2000000 0x1000>; + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7>; + interrupt-names = "soft0", "timer0"; + }; + + uart0: serial@10000000{ + compatible = "ns16550", "snps,dw-apb-uart"; + reg = <0x10000000 0x400>; + reg-shift = <2>; + + /* AIA interrupt controller is not currently implemented, + * so connect UART interrupt to 17th line as a stub to + * make build system and test framework happy. + */ + interrupt-parent = <&cpu0_intc>; + interrupts = <17>; + clock-frequency = <50000000>; + status = "disabled"; + }; + }; +}; diff --git a/boards/snps/nsim/arc_v/support/rmx100.props b/boards/snps/nsim/arc_v/support/rmx100.props new file mode 100644 index 00000000000..a56659903c0 --- /dev/null +++ b/boards/snps/nsim/arc_v/support/rmx100.props @@ -0,0 +1,9 @@ + nsim_isa_family=rv32 + nsim_isa_ext=-all.i.zicsr.zifencei.zihintpause.a.m.zba.zbb.zbs.zca.zcb.zcmp.zcmt.zicbom + nsim_isa_big_endian=0 + nsim_mem-dev=clint,base=0x2000000,size=4096 + nsim_mem-dev=uart0,kind=16550,base=0x10000000,irq=24 + nsim_mem-dev=plic,base=0xc000000,size=0x04000000,interrupts=128,priorities=16 + mpu_version=64 + mpu_regions=16 + mpu_granule=0 diff --git a/boards/sparkfun/micromod/Kconfig.defconfig b/boards/sparkfun/micromod/Kconfig.defconfig new file mode 100644 index 00000000000..50f6c3f582a --- /dev/null +++ b/boards/sparkfun/micromod/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Sparkfun micromod board configuration + +# Copyright (c) 2024 Jerónimo Agulló +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MICROMOD_NRF52840 + +config BT_CTLR + default BT + +endif # BOARD_MICROMOD_NRF52840 diff --git a/boards/sparkfun/micromod/Kconfig.micromod b/boards/sparkfun/micromod/Kconfig.micromod new file mode 100644 index 00000000000..ea40f13ad1a --- /dev/null +++ b/boards/sparkfun/micromod/Kconfig.micromod @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Jerónimo Agulló +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MICROMOD + select SOC_NRF52840_QIAA if BOARD_MICROMOD_NRF52840 diff --git a/boards/sparkfun/micromod/board.cmake b/boards/sparkfun/micromod/board.cmake new file mode 100644 index 00000000000..55900ba5975 --- /dev/null +++ b/boards/sparkfun/micromod/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000") +board_runner_args(pyocd "--target=nrf52840" "--frequency=4000000") + +include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd-nrf5.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/sparkfun/micromod/board.yml b/boards/sparkfun/micromod/board.yml new file mode 100644 index 00000000000..851ac345bc5 --- /dev/null +++ b/boards/sparkfun/micromod/board.yml @@ -0,0 +1,5 @@ +board: + name: micromod + vendor: sparkfun + socs: + - name: nrf52840 diff --git a/boards/sparkfun/micromod/doc/img/sparkfun_micromod.webp b/boards/sparkfun/micromod/doc/img/sparkfun_micromod.webp new file mode 100644 index 00000000000..423c7a3d0f6 Binary files /dev/null and b/boards/sparkfun/micromod/doc/img/sparkfun_micromod.webp differ diff --git a/boards/sparkfun/micromod/doc/index.rst b/boards/sparkfun/micromod/doc/index.rst new file mode 100644 index 00000000000..507ef52e426 --- /dev/null +++ b/boards/sparkfun/micromod/doc/index.rst @@ -0,0 +1,205 @@ +.. _boardname_linkname: + +SparkFun MicroMod board Processor +################################# + +Overview +******** + +MicroMod is a solderless, modular interface ecosystem that uses the M.2 standard +to mix and match your choice of processor with specific Function Boards or +stand-alone Carrier Boards. A MicroMod processor board is approximately 22x22 mm, +and can insert into any MicroMod carrier board. More information can be found in +the `Micromod specification website`_. + +All Micromod board targets support the following hardware features: + +- USB host mode compliant to 2.0 specification +- GPIO +- 2 UART +- 2 I2C +- 2 SPI +- 2 ADC +- 2 PWM +- Watchdog Timer (WDT) + +.. figure:: img/sparkfun_micromod.webp + :align: center + :alt: Sparkfun Micromod board + + Sparkfun Micromod board (Credit: https://www.sparkfun.com) + +Zephyr currently supports the following SoCs: + +- ``micromod/nrf52840`` + +SparkFun MicroMod nRF52840 board Processor +########################################## + +Overview +******** + +The ``micromod/nrf52840`` board target features the nRF52840 SoC +from Nordic Semiconductor, the SparkFun MicroMod nRF52840 Processor offers +a powerful combination of ARM Cortex-M4 CPU and 2.4 GHz Bluetooth transceiver +in the MicroMod form-factor. More information can be found in +the `Micromod nRF52840 guide`_. + +Hardware +******** + +The ``micromod/nrf52840`` board target supports the following +hardware features: + +- ARM Cortex-M4 CPU with floating point unit (FPU) + + - 1MB internal Flash + - 256kB internal RAM + +- Integrated 2.4GHz radio with support for Bluetooth Low Energy (BLE) and ieee802154 +- USB 2.0 full speed (12 Mbps) controller +- QSPI with 128Mb flash memory +- ARM TrustZone Cryptocell 310 security subsystem +- USB host mode compliant to 2.0 specification +- GPIO +- 2 UART +- 2 I2C +- 2 SPI +- 2 ADC +- 2 PWM +- Watchdog Timer (WDT) + +Supported Features +================== + +The Zephyr ``micromod/nrf52840`` board target supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | system clock | ++-----------+------------+-------------------------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb | ++-----------+------------+-------------------------------------+ +| QSPI | on-chip | nordic,nrf-qspi | ++-----------+------------+-------------------------------------+ + + +Connections and IOs +=================== + +LED +--- + +* Led0 (blue) = P0.13 + +Micromod header +--------------- + +* micromod_1_uart = uart0 +* micromod_2_uart = uart1 +* micromod_0_i2c = i2c0 +* micromod_1_i2c = i2c1 +* micromod_0_spi = spi2 +* micromod_header compatible with ``sparkfun,micromod-gpio`` + +Programming and Debugging +************************* + +Applications for the ``micromod/nrf52840`` board target can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +The flashing tool will depend on the carrier used along with the board. +In the case of `Sparkfun asset tracking carrier`_, it is possible to use +the SWD interface along with a J-Link. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board nRF52840 DK +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: micromod/nrf52840 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + +In case of using a Nordic Segger Jlink, it is possible to configure the app to use Segger Real +Time Transfer (RTT) for debugging. In this case, build your app with the +:ref:`RTT snippet `. + +Testing the on-board LED +************************ + +There is a sample that allow you to test the LED on the board is working properly +with Zephyr: + +* :zephyr:code-sample:`blinky` + +You can build and flash the example to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/sparkfun/micromod/micromod_nrf52840.dts`. + +Testing the 128Mb qspi memory flash +*********************************** + +The ``micromod/nrf52840`` board target has a built-in NOR flash memory connected +to the qspi interface. It can be tested with the samples/drivers/jesd216 app. + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/jesd216 + :board: micromod/nrf52840 + :goals: build flash + +References +********** + +.. target-notes:: + +.. _Micromod specification website: https://www.sparkfun.com/micromod +.. _Sparkfun asset tracking carrier: https://www.sparkfun.com/products/17272 +.. _Micromod nRF52840 guide: https://learn.sparkfun.com/tutorials/micromod-nrf52840-processor-hookup-guide +.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html +.. _nRF52840 Product Specification: http://infocenter.nordicsemi.com/pdf/nRF52840_PS_v1.0.pdf diff --git a/boards/sparkfun/micromod/micromod_nrf52840-pinctrl.dtsi b/boards/sparkfun/micromod/micromod_nrf52840-pinctrl.dtsi new file mode 100644 index 00000000000..4cba8a1d098 --- /dev/null +++ b/boards/sparkfun/micromod/micromod_nrf52840-pinctrl.dtsi @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2024 Jerónimo Agulló + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + uart0_default: uart0_default { + group1 { + psels = , + , + , + ; + }; + }; + + uart0_sleep: uart0_sleep { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; + + uart1_default: uart1_default { + group1 { + psels = , + ; + }; + }; + + uart1_sleep: uart1_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + i2c0_default: i2c0_default { + group1 { + psels = , + ; + }; + }; + + i2c0_sleep: i2c0_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + i2c1_default: i2c1_default { + group1 { + psels = , + ; + }; + }; + + i2c1_sleep: i2c1_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + spi0_default: spi0_default { + group1 { + psels = , + , + ; + }; + }; + + spi0_sleep: spi0_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; + + qspi_default: qspi_default { + group1 { + psels = , + , + , + , + , + ; + nordic,drive-mode = ; + }; + }; + + qspi_sleep: qspi_sleep { + group1 { + psels = , + , + , + , + ; + low-power-enable; + }; + group2 { + psels = ; + low-power-enable; + bias-pull-up; + }; + }; +}; diff --git a/boards/sparkfun/micromod/micromod_nrf52840.dts b/boards/sparkfun/micromod/micromod_nrf52840.dts new file mode 100644 index 00000000000..a8327647165 --- /dev/null +++ b/boards/sparkfun/micromod/micromod_nrf52840.dts @@ -0,0 +1,208 @@ +/* + * Copyright (c) 2024 Jerónimo Agulló + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "micromod_nrf52840-pinctrl.dtsi" +#include + +/ { + model = "Sparkfun Micrmod nRF52840 board"; + compatible = "sparkfun,micromod-nrf52840"; + + chosen { + zephyr,console = &uart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,ieee802154 = &ieee802154; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + watchdog0 = &wdt0; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpio0 13 0>; + label = "Blue LED"; + }; + }; + + micromod_header: connector { + compatible = "sparkfun,micromod-gpio"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 4 0>, /* A0 */ + <1 0 &gpio0 5 0>, /* A1 */ + <2 0 &gpio0 27 0>, /* D0 */ + <3 0 &gpio1 8 0>, /* D1/CAM_TRIG */ + <4 0 &gpio0 15 0>, /* I2C_INT# */ + <5 0 &gpio0 29 0>, /* G0/BUS0 */ + <6 0 &gpio0 3 0>, /* G1/BUS1 */ + <7 0 &gpio1 13 0>, /* G2/BUS2 */ + <8 0 &gpio1 12 0>, /* G3/BUS3 */ + <9 0 &gpio1 11 0>, /* G4/BUS4 */ + <10 0 &gpio0 17 0>, /* G5/BUS5 */ + <11 0 &gpio1 6 0>, /* G6/BUS6 */ + <12 0 &gpio1 4 0>, /* G7/BUS7 */ + <13 0 &gpio1 14 0>, /* G8 */ + <14 0 &gpio0 9 0>, /* G9/ADC_D-/CAM_HSYNC */ + <15 0 &gpio0 10 0>, /* G10/ADC_D+/CAM_VSYNC */ + //<16 NO CONNECTED /* G11/SWO */ + <17 0 &gpio0 20 0>; /* SPI_CS */ + }; +}; + +®0 { + status = "okay"; +}; + +®1 { + regulator-initial-mode = ; +}; + +&adc { + status = "okay"; +}; + +&gpiote { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&uicr { + nfct-pins-as-gpios; + gpio-as-nreset; +}; + +&uart0 { + compatible = "nordic,nrf-uarte"; + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart1 { + compatible = "nordic,nrf-uarte"; + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart1_default>; + pinctrl-1 = <&uart1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&i2c0 { + compatible = "nordic,nrf-twi"; + status = "okay"; + pinctrl-0 = <&i2c0_default>; + pinctrl-1 = <&i2c0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&i2c1 { + compatible = "nordic,nrf-twi"; + status = "okay"; + pinctrl-0 = <&i2c1_default>; + pinctrl-1 = <&i2c1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&spi2 { + compatible = "nordic,nrf-spi"; + status = "okay"; + cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&spi0_default>; + pinctrl-1 = <&spi0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&qspi { + status = "okay"; + pinctrl-0 = <&qspi_default>; + pinctrl-1 = <&qspi_sleep>; + pinctrl-names = "default", "sleep"; + w25q128jv: w25q128jv@0 { + status="okay"; + compatible = "nordic,qspi-nor"; + reg = <0>; + writeoc = "pp4io"; + readoc = "read4io"; + sck-frequency = ; + jedec-id = [ef 70 18]; + size = ; + has-dpd; + t-enter-dpd = <3000>; + t-exit-dpd = <3000>; + }; +}; + +&ieee802154 { + status = "okay"; +}; + +&flash0 { + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + }; + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00076000>; + }; + + slot1_partition: partition@86000 { + label = "image-1"; + reg = <0x00086000 0x00074000>; + }; + + /* + * The flash starting at 0x000f8000 and ending at + * 0x000fffff is reserved for use by the application. + */ + + /* + * Storage partition will be used by FCB/LittleFS/NVS + * if enabled. + */ + + storage_partition: partition@fA000 { + label = "storage"; + reg = <0x000fA000 0x00006000>; + }; + }; +}; + +zephyr_udc0: &usbd { + compatible = "nordic,nrf-usbd"; + status = "okay"; +}; + +// Sparkfun Micromod compatible pins +micromod_1_uart: &uart0 {}; +micromod_2_uart: &uart1 {}; +micromod_0_i2c: &i2c0 {}; +micromod_1_i2c: &i2c1 {}; +micromod_0_spi: &spi2 {}; diff --git a/boards/sparkfun/micromod/micromod_nrf52840.yaml b/boards/sparkfun/micromod/micromod_nrf52840.yaml new file mode 100644 index 00000000000..3afd6269313 --- /dev/null +++ b/boards/sparkfun/micromod/micromod_nrf52840.yaml @@ -0,0 +1,26 @@ +identifier: micromod/nrf52840 +name: Sparkfun Micromod nRF52840 board +type: mcu +arch: arm +ram: 256 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - ble + - gpio + - spi + - qspi + - i2c + - pwm + - adc + - usb_device + - usb_cdc + - watchdog + - micromod_gpio + - micromod_uart + - micromod_i2c + - micromod_spi +vendor: Sparkfun diff --git a/boards/sparkfun/micromod/micromod_nrf52840_defconfig b/boards/sparkfun/micromod/micromod_nrf52840_defconfig new file mode 100644 index 00000000000..f8f1759f51c --- /dev/null +++ b/boards/sparkfun/micromod/micromod_nrf52840_defconfig @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable RTT +CONFIG_USE_SEGGER_RTT=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable console +CONFIG_CONSOLE=y + +# Enable UART +CONFIG_SERIAL=y diff --git a/boards/sparkfun/micromod/pre_dt_board.cmake b/boards/sparkfun/micromod/pre_dt_board.cmake new file mode 100644 index 00000000000..3369c21d3af --- /dev/null +++ b/boards/sparkfun/micromod/pre_dt_board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2022 Nordic Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: +# - power@40000000 & clock@40000000 & bprot@40000000 +# - acl@4001e000 & flash-controller@4001e000 +list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/sparkfun/pro_micro_rp2040/doc/index.rst b/boards/sparkfun/pro_micro_rp2040/doc/index.rst index cc8188aa3f1..f538a04b1ce 100644 --- a/boards/sparkfun/pro_micro_rp2040/doc/index.rst +++ b/boards/sparkfun/pro_micro_rp2040/doc/index.rst @@ -119,8 +119,8 @@ The Pro Micro board does make the SWD pins available on pads on the underside of the board. You can solder to these pins, and use a JTag debugger. You can also flash the SparkFun ProMicro RP2040 with a UF2 file. By default, building an app for this board will generate a -`build/zephyr/zephyr.uf2` file. If the Pro Micro RP2040 is powered on with -the `BOOTSEL` button pressed, it will appear on the host as a mass storage +:file:`build/zephyr/zephyr.uf2` file. If the Pro Micro RP2040 is powered on with +the ``BOOTSEL`` button pressed, it will appear on the host as a mass storage device. The UF2 file should be copied to the device, which will flash the Pro Micro RP2040. diff --git a/boards/sparkfun/thing_plus/doc/index.rst b/boards/sparkfun/thing_plus/doc/index.rst index a6c7aee9742..802c77ffb1a 100644 --- a/boards/sparkfun/thing_plus/doc/index.rst +++ b/boards/sparkfun/thing_plus/doc/index.rst @@ -92,7 +92,7 @@ In most cases you'll want to use the ``ns`` target with any of the Zephyr or Nordic based examples. Some of the examples do not use secure mode, so they do not required the ``ns`` suffix. -A great example of this is the `hello_world` below. +A great example of this is the :zephyr:code-sample:`hello_world` below. Flashing ======== @@ -103,7 +103,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_common.dtsi b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_common.dtsi index 2658ee5eaa4..6408d91af0e 100644 --- a/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_common.dtsi +++ b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_common.dtsi @@ -172,57 +172,6 @@ }; }; -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x10000>; - }; - slot0_partition: partition@10000 { - label = "image-0"; - }; - slot0_ns_partition: partition@50000 { - label = "image-0-nonsecure"; - }; - slot1_partition: partition@80000 { - label = "image-1"; - }; - slot1_ns_partition: partition@c0000 { - label = "image-1-nonsecure"; - }; - /* 0xf0000 to 0xf7fff reserved for TF-M partitions */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; - -/ { - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_s: image_s@20000000 { - /* Secure image memory */ - }; - - sram0_bsd: image_bsd@20010000 { - /* BSD (shared) memory */ - }; - - sram0_ns: image_ns@20020000 { - /* Non-Secure image memory */ - }; - }; -}; - / { vbatt { compatible = "voltage-divider"; @@ -233,5 +182,5 @@ }; }; -/* Include partition configuration file */ -#include "sparkfun_thing_plus_nrf9160_partition_conf.dtsi" +/* Include default memory partition configuration file */ +#include diff --git a/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_ns.dts b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_ns.dts index 6ad23ab3830..27ad9058980 100644 --- a/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_ns.dts +++ b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_ns.dts @@ -12,7 +12,7 @@ / { chosen { zephyr,flash = &flash0; - zephyr,sram = &sram0_ns; + zephyr,sram = &sram0_ns_app; zephyr,code-partition = &slot0_ns_partition; }; diff --git a/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_partition_conf.dtsi b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_partition_conf.dtsi deleted file mode 100644 index 64591fbf900..00000000000 --- a/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_partition_conf.dtsi +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2018-2020 Nordic Semiconductor ASA - * Copyright (c) 2020 Circuit Dojo LLC - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* - * Default Flash planning for sparkfun_thing_plus_nrf9160. - * - * Zephyr build for nRF9160 with ARM TrustZone-M support, - * implies building Secure and Non-Secure Zephyr images. - * - * Secure image will be placed, by default, in flash0 - * (or in slot0, if MCUboot is present). - * Secure image will use sram0 for system memory. - * - * Non-Secure image will be placed in slot0_ns, and use - * sram0_ns for system memory. - * - * Note that the Secure image only requires knowledge of - * the beginning of the Non-Secure image (not its size). - */ - -&slot0_partition { - reg = <0x00010000 0x40000>; -}; - -&slot0_ns_partition { - reg = <0x00050000 0x30000>; -}; - -&slot1_partition { - reg = <0x00080000 0x40000>; -}; - -&slot1_ns_partition { - reg = <0x000c0000 0x30000>; -}; - -/* Default SRAM planning when building for nRF9160 with - * ARM TrustZone-M support - * - Lowest 64 kB SRAM allocated to Secure image (sram0_s). - * - 64 kB SRAM reserved for and used by the BSD socket - * library (sram0_bsd). - * - Upper 128 kB allocated to Non-Secure image (sram0_ns). - */ - -&sram0_s { - reg = <0x20000000 DT_SIZE_K(64)>; -}; - -&sram0_bsd { - reg = <0x20010000 DT_SIZE_K(64)>; -}; - -&sram0_ns { - reg = <0x20020000 DT_SIZE_K(128)>; -}; diff --git a/boards/sparkfun/thing_plus_matter_mgm240p/CMakeLists.txt b/boards/sparkfun/thing_plus_matter_mgm240p/CMakeLists.txt new file mode 100644 index 00000000000..ca93e65ac91 --- /dev/null +++ b/boards/sparkfun/thing_plus_matter_mgm240p/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2021 Sateesh Kotapati +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_UART_GECKO) + zephyr_library() + zephyr_library_sources(board.c) +endif() diff --git a/boards/sparkfun/thing_plus_matter_mgm240p/Kconfig b/boards/sparkfun/thing_plus_matter_mgm240p/Kconfig new file mode 100644 index 00000000000..826ce000afd --- /dev/null +++ b/boards/sparkfun/thing_plus_matter_mgm240p/Kconfig @@ -0,0 +1,9 @@ +# SPARKFUN THING PLUS MGM240P board + +# Copyright (c) 2024 Daikin Comfort Technologies North America, Inc. +# Copyright (c) 2022, Silicon Labs +# SPDX-License-Identifier: Apache-2.0 + +module = BOARD_SPARKFUN_THING_PLUS_MATTER_MGM240P +module-str = Board Control +source "subsys/logging/Kconfig.template.log_config" diff --git a/boards/sparkfun/thing_plus_matter_mgm240p/Kconfig.defconfig b/boards/sparkfun/thing_plus_matter_mgm240p/Kconfig.defconfig new file mode 100644 index 00000000000..9c21ba54457 --- /dev/null +++ b/boards/sparkfun/thing_plus_matter_mgm240p/Kconfig.defconfig @@ -0,0 +1,45 @@ +# SPARKFUN THING PLUS MGM240P board + +# Copyright (c) 2024 Daikin Comfort Technologies North America, Inc. +# Copyright (c) 2021, Sateesh Kotapati +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_SPARKFUN_THING_PLUS_MATTER_MGM240P + +config CMU_HFXO_FREQ + default 40000000 + +config CMU_LFXO_FREQ + default 32768 + +config FLASH_BASE_ADDRESS + hex + default 0x08000000 + +if SOC_GECKO_USE_RAIL + +config FPU + default y + +endif # SOC_GECKO_USE_RAIL + +if BT + +config FPU + default y + +config COMMON_LIBC_MALLOC_ARENA_SIZE + default 8192 + +config MAIN_STACK_SIZE + default 2304 + +if SHELL + +config SHELL_STACK_SIZE + default 4096 + +endif # SHELL + +endif # BT +endif # BOARD_SPARKFUN_THING_PLUS_MGM240P diff --git a/boards/sparkfun/thing_plus_matter_mgm240p/Kconfig.sparkfun_thing_plus_matter_mgm240p b/boards/sparkfun/thing_plus_matter_mgm240p/Kconfig.sparkfun_thing_plus_matter_mgm240p new file mode 100644 index 00000000000..1bc9fb791d6 --- /dev/null +++ b/boards/sparkfun/thing_plus_matter_mgm240p/Kconfig.sparkfun_thing_plus_matter_mgm240p @@ -0,0 +1,7 @@ +# EFR32XG24 MGM240P board + +# Copyright (c) 2024 Daikin Comfort Technologies North America, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SPARKFUN_THING_PLUS_MATTER_MGM240P + select SOC_PART_NUMBER_EFR32MG24B020F1536IM40 diff --git a/boards/sparkfun/thing_plus_matter_mgm240p/board.c b/boards/sparkfun/thing_plus_matter_mgm240p/board.c new file mode 100644 index 00000000000..6578e872700 --- /dev/null +++ b/boards/sparkfun/thing_plus_matter_mgm240p/board.c @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2024 Daikin Comfort Technologies North America, Inc. + * Copyright (c) 2021 Sateesh Kotapati + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +#ifdef CONFIG_SOC_GECKO_DEV_INIT +#include "em_cmu.h" +#endif + +LOG_MODULE_REGISTER(sparkfun_thing_plus_mgm240p, +CONFIG_BOARD_SPARKFUN_THING_PLUS_MATTER_MGM240P_LOG_LEVEL); + +static int sparkfun_thing_plus_mgm240p_init_clocks(void); + +static int sparkfun_thing_plus_mgm240p_init(void) +{ + int ret; + +#ifdef CONFIG_SOC_GECKO_DEV_INIT + sparkfun_thing_plus_mgm240p_init_clocks(); +#endif + static struct gpio_dt_spec wake_up_gpio_dev = + GPIO_DT_SPEC_GET(DT_NODELABEL(wake_up_trigger), gpios); + + + if (!gpio_is_ready_dt(&wake_up_gpio_dev)) { + LOG_ERR("Wake-up GPIO device was not found!\n"); + return -ENODEV; + } + ret = gpio_pin_configure_dt(&wake_up_gpio_dev, GPIO_OUTPUT_ACTIVE); + if (ret < 0) { + return ret; + } + + return 0; +} + +#ifdef CONFIG_SOC_GECKO_DEV_INIT +static int sparkfun_thing_plus_mgm240p_init_clocks(void) +{ + CMU_ClockSelectSet(cmuClock_SYSCLK, cmuSelect_HFRCODPLL); +#if defined(_CMU_EM01GRPACLKCTRL_MASK) + CMU_ClockSelectSet(cmuClock_EM01GRPACLK, cmuSelect_HFRCODPLL); +#endif +#if defined(_CMU_EM01GRPBCLKCTRL_MASK) + CMU_ClockSelectSet(cmuClock_EM01GRPBCLK, cmuSelect_HFRCODPLL); +#endif + CMU_ClockSelectSet(cmuClock_EM23GRPACLK, cmuSelect_LFRCO); + CMU_ClockSelectSet(cmuClock_EM4GRPACLK, cmuSelect_LFRCO); +#if defined(RTCC_PRESENT) + CMU_ClockSelectSet(cmuClock_RTCC, cmuSelect_LFRCO); +#endif +#if defined(SYSRTC_PRESENT) + CMU_ClockSelectSet(cmuClock_SYSRTC, cmuSelect_LFRCO); +#endif + CMU_ClockSelectSet(cmuClock_WDOG0, cmuSelect_LFRCO); +#if WDOG_COUNT > 1 + CMU_ClockSelectSet(cmuClock_WDOG1, cmuSelect_LFRCO); +#endif + + return 0; +} +#endif + +/* needs to be done after GPIO driver init */ +SYS_INIT(sparkfun_thing_plus_mgm240p_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); diff --git a/boards/sparkfun/thing_plus_matter_mgm240p/board.cmake b/boards/sparkfun/thing_plus_matter_mgm240p/board.cmake new file mode 100644 index 00000000000..17cf81d6dae --- /dev/null +++ b/boards/sparkfun/thing_plus_matter_mgm240p/board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Daikin Comfort Technologies North America, Inc. + +# SPDX-License-Identifier: Apache-2.0 +# + +board_runner_args(jlink "--device=EFR32MG24BxxxF1536") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/sparkfun/thing_plus_matter_mgm240p/board.yml b/boards/sparkfun/thing_plus_matter_mgm240p/board.yml new file mode 100644 index 00000000000..69ecc88a5b8 --- /dev/null +++ b/boards/sparkfun/thing_plus_matter_mgm240p/board.yml @@ -0,0 +1,5 @@ +board: + name: sparkfun_thing_plus_matter_mgm240p + vendor: sparkfun + socs: + - name: efr32mg24b020f1536im40 diff --git a/boards/sparkfun/thing_plus_matter_mgm240p/doc/img/MGM240P_Thing_Plus.jpg b/boards/sparkfun/thing_plus_matter_mgm240p/doc/img/MGM240P_Thing_Plus.jpg new file mode 100644 index 00000000000..8d05b65efa8 Binary files /dev/null and b/boards/sparkfun/thing_plus_matter_mgm240p/doc/img/MGM240P_Thing_Plus.jpg differ diff --git a/boards/sparkfun/thing_plus_matter_mgm240p/doc/index.rst b/boards/sparkfun/thing_plus_matter_mgm240p/doc/index.rst new file mode 100644 index 00000000000..cdaed771bd8 --- /dev/null +++ b/boards/sparkfun/thing_plus_matter_mgm240p/doc/index.rst @@ -0,0 +1,168 @@ +.. _sparkfun_thing_plus_mgm240p: + +SPARKFUN THING PLUS MATTER +########################### + +Overview +******** + +The MGM240P Mighty Sparkfun Think Plus Matter contains +a Wireless System-On-Chip from the EFR32MG24 family built on an +ARM Cortex®-M33F processor with excellent low power capabilities. + +.. figure:: ./img/MGM240P_Thing_Plus.jpg + :height: 260px + :align: center + :alt: MGM240P Sparkfun Think Plus Matter + + xG24-MGM240P (image courtesy of Sparkfun) + +Hardware +******** + +- Based on the Series 2 EFR32MG24 SoC +- CPU core: 32-bit ARM® Cortex®-M33 core at 39 MHz +- Flash memory: 1536 kB +- RAM: 256 kB +- Supports Multiple 802.15.4 Wireless Protocols (Zigbee and OpenThread) +- Bluetooth Low Energy 5.3 +- Crystals for LFXO (32 kHz) and HFXO (39 MHz). + +For more information about the EFR32MG24 SoC and BRD2601B board, refer to these +documents: + +- `EFR32MG24 Website`_ +- `EFR32MG24 Datasheet`_ +- `EFR32xG24 Reference Manual`_ +- `MGM240P Datasheet`_ +- `MGM240P Schematics`_ + +Supported Features +================== + +The board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| COUNTER | on-chip | stimer | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | semailbox | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| I2C(M/S) | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| RADIO | on-chip | bluetooth | ++-----------+------------+-------------------------------------+ + +Other hardware features are currently not supported by the port. + +Connections and IOs +=================== + +In the following table, the column **Name** contains Pin names. For example, PA2 +means Pin number 2 on PORTA, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Name | Function | Usage | ++=======+=============+=====================================+ +| PA8 | GPIO | LED0 | ++-------+-------------+-------------------------------------+ +| PA5 | USART0_TX | UART Console EFM_BC_TX US0_TX | ++-------+-------------+-------------------------------------+ +| PA6 | USART0_RX | UART Console EFM_BC_RX US0_RX | ++-------+-------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/sparkfun_thing_plus_mgm240p/sparkfun_thing_plus_mgm240p_defconfig` + +System Clock +============ + +The EFR32MG24 SoC is configured to use the 39 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFR32MG24 SoC has one USART and two EUSARTs. +USART0 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +.. note:: + Before using the kit the first time, you should update the J-Link firmware + from `J-Link-Downloads`_ + +Flashing +======== + +The sample application :zephyr:code-sample:`hello_world` is used for this example. +Build the Zephyr kernel and application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sparkfun_thing_plus_mgm240p + :goals: build + +Connect the sparkfun_thing_plus_mgm240p to your host computer using the USB port and you +should see a USB connection. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you'll see the following message on the corresponding serial port +terminal session: + +.. code-block:: console + + Hello World! _sparkfun_thing_plus_mgm240p + +Bluetooth +========= + +To use the BLE function, run the command below to retrieve necessary binary +blobs from the SiLabs HAL repository. + +.. code-block:: console + + west blobs fetch silabs + +Then build the Zephyr kernel and a Bluetooth sample with the following +command. The :zephyr:code-sample:`bluetooth_observer` sample application is used in +this example. + +.. zephyr-app-commands:: + :zephyr-app: samples/bluetooth/observer + :board: sparkfun_thing_plus_mgm240p + :goals: build + +.. _EFR32MG24 Website: + https://www.silabs.com/wireless/zigbee/efr32mg24-series-2-socs# + +.. _EFR32MG24 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efr32mg24-datasheet.pdf + +.. _EFR32xG24 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efr32xg24-rm.pdf + +.. _MGM240P Datasheet: + https://cdn.sparkfun.com/assets/1/4/5/e/5/MGM240P-Datasheet.pdf + +.. _MGM240P Schematics: + https://cdn.sparkfun.com/assets/0/f/8/4/9/Thing_Plus_MGM240P.pdf + +.. _J-Link-Downloads: + https://www.segger.com/downloads/jlink diff --git a/boards/sparkfun/thing_plus_matter_mgm240p/dts/bindings/silabs,gecko-wake-up-trigger.yaml b/boards/sparkfun/thing_plus_matter_mgm240p/dts/bindings/silabs,gecko-wake-up-trigger.yaml new file mode 100644 index 00000000000..ba8892f2ce0 --- /dev/null +++ b/boards/sparkfun/thing_plus_matter_mgm240p/dts/bindings/silabs,gecko-wake-up-trigger.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2022, Antmicro +# SPDX-License-Identifier: Apache-2.0 + +description: GPIO Wake Up Trigger for EFR32MG24 + +compatible: "silabs,gecko-wake-up-trigger" + +include: base.yaml + +properties: + gpios: + type: phandle-array + required: true + description: | + GPIO used as wake up trigger from EM4 sleep diff --git a/boards/sparkfun/thing_plus_matter_mgm240p/pre_dt_board.cmake b/boards/sparkfun/thing_plus_matter_mgm240p/pre_dt_board.cmake new file mode 100644 index 00000000000..beb76b85552 --- /dev/null +++ b/boards/sparkfun/thing_plus_matter_mgm240p/pre_dt_board.cmake @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +# SPI is implemented via usart so node name isn't spi@... +list(APPEND EXTRA_DTC_FLAGS "-Wno-spi_bus_bridge") diff --git a/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p-pinctrl.dtsi b/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p-pinctrl.dtsi new file mode 100644 index 00000000000..4e6cb746f80 --- /dev/null +++ b/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p-pinctrl.dtsi @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2022 Silicon Labs + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +&pinctrl { + /* configuration for uart0 device, default state */ + usart0_default: usart0_default { + group1 { + /* configure PA.6 as UART_RX and PA.5 as UART_TX */ + psels = , + , + ; + }; + }; + + i2c0_default: i2c0_default { + group1 { + psels = , + , + , + ; + }; + }; + +}; diff --git a/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p.dts b/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p.dts new file mode 100644 index 00000000000..e0352730d30 --- /dev/null +++ b/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p.dts @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2024 Daikin Comfort Technologies North America, Inc. + * Copyright (c) 2020 TriaGnoSys GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "sparkfun_thing_plus_matter_mgm240p-pinctrl.dtsi" +#include + +/ { + model = "Sparkfun MGM240P (Sparkfun Thing Plus Matter)"; + compatible = "sparkfun,sparkfun_thing_plus_mgm240p", "silabs,efr32mg24"; + + chosen { + zephyr,console = &usart0; + zephyr,shell-uart = &usart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,bt-hci = &bt_hci_silabs; + }; + + aliases { + led0 = &blue_led; + watchdog0 = &wdog0; + }; + + leds { + compatible = "gpio-leds"; + blue_led: led_1 { + gpios = <&gpioa GECKO_PIN(8) GPIO_ACTIVE_LOW>; + }; + + }; + + wake_up_trigger: gpio-wake-up { + compatible = "silabs,gecko-wake-up-trigger"; + gpios = <&gpioa GECKO_PIN(5) GPIO_ACTIVE_LOW>; + }; + +}; + +&cpu0 { + clock-frequency = <78000000>; +}; + +&usart0 { + current-speed = <115200>; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; +&i2c0 { + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + status = "okay"; + +}; + +&gpio { + status = "okay"; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&wdog0 { + status = "okay"; +}; + +&se { + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 48 kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 0x0000c000>; + read-only; + }; + + /* Reserve 464 kB for the application in slot 0 */ + slot0_partition: partition@c000 { + label = "storage"; + reg = <0x0000c000 0x00074000>; + }; + + /* Reserve 464 kB for the application in slot 1 */ + slot1_partition: partition@80000 { + label = "image-0"; + reg = <0x00080000 0x00074000>; + }; + + /* Reserve 32 kB for the scratch partition */ + scratch_partition: partition@f4000 { + label = "image-1"; + reg = <0x000f4000 0x00008000>; + }; + + /* Set 528Kb of storage at the end of the 1024Kb of flash */ + storage_partition: partition@fc000 { + label = "image-scratch"; + reg = <0x000fc000 0x00084000>; + }; + }; +}; + +&adc0 { + status = "okay"; +}; + +&stimer0 { + status = "okay"; +}; + +&bt_hci_silabs { + status = "okay"; +}; diff --git a/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p.yaml b/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p.yaml new file mode 100644 index 00000000000..87bea1b9315 --- /dev/null +++ b/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p.yaml @@ -0,0 +1,23 @@ +identifier: sparkfun_thing_plus_matter_mgm240p +name: MGM240P +type: mcu +arch: arm +ram: 256 +flash: 1536 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - counter + - gpio + - uart + - spi + - watchdog +testing: + ignore_tags: + - net + - bluetooth + - pm + - hwinfo +vendor: sparkfun diff --git a/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p_defconfig b/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p_defconfig new file mode 100644 index 00000000000..6ab4ff4cdaa --- /dev/null +++ b/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Daikin Comfort Technologies North America, Inc. +# Copyright (c) 2022 Silicon Labs +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_CORTEX_M_SYSTICK=y +CONFIG_GPIO=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=76800000 +CONFIG_CMU_HFCLK_HFXO=y +CONFIG_SOC_GECKO_EMU_DCDC=y +CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y +CONFIG_CMU_HFCLK_LFXO=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_PINCTRL=y +CONFIG_REGULATOR=y diff --git a/boards/st/b_g474e_dpow1/b_g474e_dpow1.yaml b/boards/st/b_g474e_dpow1/b_g474e_dpow1.yaml index 04dc5fb08d6..b27446b1beb 100644 --- a/boards/st/b_g474e_dpow1/b_g474e_dpow1.yaml +++ b/boards/st/b_g474e_dpow1/b_g474e_dpow1.yaml @@ -14,4 +14,5 @@ supported: - watchdog - tcpc - usb + - usbd vendor: st diff --git a/boards/st/b_g474e_dpow1/b_g474e_dpow1_defconfig b/boards/st/b_g474e_dpow1/b_g474e_dpow1_defconfig index 3da57c5589e..8419446a952 100644 --- a/boards/st/b_g474e_dpow1/b_g474e_dpow1_defconfig +++ b/boards/st/b_g474e_dpow1/b_g474e_dpow1_defconfig @@ -13,12 +13,6 @@ CONFIG_UART_CONSOLE=y # GPIO Controller CONFIG_GPIO=y -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/st/b_g474e_dpow1/board.cmake b/boards/st/b_g474e_dpow1/board.cmake index b315703cd96..b77e3f43c2f 100644 --- a/boards/st/b_g474e_dpow1/board.cmake +++ b/boards/st/b_g474e_dpow1/board.cmake @@ -1,6 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +# keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) - diff --git a/boards/st/b_g474e_dpow1/doc/index.rst b/boards/st/b_g474e_dpow1/doc/index.rst index afaa8d94f81..7e1f584b522 100644 --- a/boards/st/b_g474e_dpow1/doc/index.rst +++ b/boards/st/b_g474e_dpow1/doc/index.rst @@ -42,6 +42,7 @@ More information about the board can be found at the `B-G474E-DPOW1 website`_. More information about STM32G474RE can be found here: + - `G474RE on www.st.com`_ - `STM32G4 reference manual`_ @@ -104,6 +105,8 @@ For more details please refer to `B-G474E-DPOW1 Discovery board User Manual`_. Programming and Debugging ************************* +The B-G474E-DPOW1 Discovery board includes an ST-LINK/V3E embedded debug tool interface. + Applications for the ``b_g474e_dpow1`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -111,7 +114,8 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -The B-G474E-DPOW1 Discovery board includes an ST-LINK/V3E embedded debug tool interface. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. .. code-block:: console @@ -133,7 +137,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -157,3 +161,6 @@ References .. _G474RE on www.st.com: https://www.st.com/en/microcontrollers-microprocessors/stm32g474re.html + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/b_l072z_lrwan1/b_l072z_lrwan1.yaml b/boards/st/b_l072z_lrwan1/b_l072z_lrwan1.yaml index 895fab02c5a..eef460836cb 100644 --- a/boards/st/b_l072z_lrwan1/b_l072z_lrwan1.yaml +++ b/boards/st/b_l072z_lrwan1/b_l072z_lrwan1.yaml @@ -20,4 +20,5 @@ supported: - eeprom - nvs - lora + - usbd vendor: st diff --git a/boards/st/b_l072z_lrwan1/b_l072z_lrwan1_defconfig b/boards/st/b_l072z_lrwan1/b_l072z_lrwan1_defconfig index 8accdc5b47c..f23dd0a9d83 100644 --- a/boards/st/b_l072z_lrwan1/b_l072z_lrwan1_defconfig +++ b/boards/st/b_l072z_lrwan1/b_l072z_lrwan1_defconfig @@ -3,9 +3,6 @@ # Enable MPU CONFIG_ARM_MPU=y -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - # Serial Drivers CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y @@ -15,6 +12,3 @@ CONFIG_UART_CONSOLE=y # GPIO Controller CONFIG_GPIO=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/b_l072z_lrwan1/board.cmake b/boards/st/b_l072z_lrwan1/board.cmake index ef270a0abc8..d08734fa6c1 100644 --- a/boards/st/b_l072z_lrwan1/board.cmake +++ b/boards/st/b_l072z_lrwan1/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32L072CZ" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/b_l072z_lrwan1/doc/index.rst b/boards/st/b_l072z_lrwan1/doc/index.rst index 5ea80847871..527461c24a4 100644 --- a/boards/st/b_l072z_lrwan1/doc/index.rst +++ b/boards/st/b_l072z_lrwan1/doc/index.rst @@ -191,6 +191,8 @@ the USB data lines to the MCU, short solder bridges SB15 and SB16. Programming and Debugging ************************* +B-L072Z-LRWAN1 Discovery board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``b_l072z_lrwan1`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -198,15 +200,21 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -B-L072Z-LRWAN1 Discovery board includes an ST-LINK/V2-1 embedded debug -tool interface. This interface is supported by the openocd version included -in the Zephyr SDK since v0.9.2. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to B-L072Z-LRWAN1 Discovery board --------------------------------------------------------- -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Connect the B-L072Z-LRWAN1 Discovery board to a STLinkV2 to your host computer using the USB port, then run a serial host program to connect with your board. For example: @@ -232,7 +240,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -248,3 +256,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32L0x2 reference manual: https://www.st.com/resource/en/reference_manual/DM00108281.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a.dts b/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a.dts index 13cd97c67be..d41c75c44bf 100644 --- a/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a.dts +++ b/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a.dts @@ -51,7 +51,6 @@ sw0 = &user_button; watchdog0 = &iwdg; accel0 = &lsm6dsl; - spi-flash0 = &mx25r6435f; }; }; diff --git a/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a_defconfig b/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a_defconfig index 9e3dfce576e..0f4ce3ee7b4 100644 --- a/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a_defconfig +++ b/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a_defconfig @@ -6,12 +6,6 @@ CONFIG_SERIAL=y # enable GPIO CONFIG_GPIO=y -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - # console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/b_l4s5i_iot01a/board.cmake b/boards/st/b_l4s5i_iot01a/board.cmake index d3088e3404d..9985ccb50b0 100644 --- a/boards/st/b_l4s5i_iot01a/board.cmake +++ b/boards/st/b_l4s5i_iot01a/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32L4S5VI" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/b_l4s5i_iot01a/doc/index.rst b/boards/st/b_l4s5i_iot01a/doc/index.rst index 17455c772dd..fb1620c672d 100644 --- a/boards/st/b_l4s5i_iot01a/doc/index.rst +++ b/boards/st/b_l4s5i_iot01a/doc/index.rst @@ -177,11 +177,21 @@ Default settings are 115200 8N1. Programming and Debugging ************************* +B_L4S5I_IOT01A Discovery kit includes an ST-LINK/V2-1 embedded debug tool interface. + Flashing ======== -B_L4S5I_IOT01A Discovery kit includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to B_L4S5I_IOT01A Discovery kit ------------------------------------------------------- @@ -195,7 +205,7 @@ board. For example: $ minicom -D /dev/ttyACM0 Then, build and flash in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -212,7 +222,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -231,3 +241,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32L4S5 reference manual: https://www.st.com/resource/en/reference_manual/dm00310109.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/b_u585i_iot02a/b_u585i_iot02a-common.dtsi b/boards/st/b_u585i_iot02a/b_u585i_iot02a-common.dtsi index 97fe4e0be57..c8d5ca4b790 100644 --- a/boards/st/b_u585i_iot02a/b_u585i_iot02a-common.dtsi +++ b/boards/st/b_u585i_iot02a/b_u585i_iot02a-common.dtsi @@ -35,7 +35,6 @@ aliases { watchdog0 = &iwdg; - spi-flash0 = &mx25lm51245; die-temp0 = &die_temp; volt-sensor0 = &vref1; volt-sensor1 = &vbat4; @@ -143,13 +142,13 @@ stm32_lp_tick_source: &lptim1 { status = "okay"; partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - partition@0 { - reg = <0x00000000 DT_SIZE_M(64)>; - }; + partition@0 { + reg = <0x00000000 DT_SIZE_M(64)>; + }; }; }; }; diff --git a/boards/st/b_u585i_iot02a/b_u585i_iot02a.dts b/boards/st/b_u585i_iot02a/b_u585i_iot02a.dts index e8c81ca083a..0ac55be54ce 100644 --- a/boards/st/b_u585i_iot02a/b_u585i_iot02a.dts +++ b/boards/st/b_u585i_iot02a/b_u585i_iot02a.dts @@ -6,6 +6,8 @@ /dts-v1/; #include "b_u585i_iot02a-common.dtsi" +#include +#include / { model = "STMicroelectronics B-U585I-IOT02A discovery kit"; @@ -24,6 +26,15 @@ led0 = &green_led_1; led1 = &red_led_1; sw0 = &user_button; + die-temp0 = &die_temp; + }; + + octo_nor: memory@70000000 { + compatible = "zephyr,memory-region"; + reg = <0x70000000 DT_SIZE_M(64)>; + zephyr,memory-region = "EXTMEM"; + /* The ATTR_MPU_EXTMEM attribut causing a MPU FAULT */ + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>; }; }; @@ -77,3 +88,12 @@ status = "okay"; }; }; + +&die_temp { + status = "okay"; +}; + +&adc1 { + st,adc-prescaler = <4>; + status = "okay"; +}; diff --git a/boards/st/b_u585i_iot02a/b_u585i_iot02a.yaml b/boards/st/b_u585i_iot02a/b_u585i_iot02a.yaml index ef3e9b0a210..48f1064731c 100644 --- a/boards/st/b_u585i_iot02a/b_u585i_iot02a.yaml +++ b/boards/st/b_u585i_iot02a/b_u585i_iot02a.yaml @@ -24,4 +24,5 @@ supported: - counter - i2c - rtc + - usbd vendor: st diff --git a/boards/st/b_u585i_iot02a/b_u585i_iot02a_defconfig b/boards/st/b_u585i_iot02a/b_u585i_iot02a_defconfig index 9e3dfce576e..0f4ce3ee7b4 100644 --- a/boards/st/b_u585i_iot02a/b_u585i_iot02a_defconfig +++ b/boards/st/b_u585i_iot02a/b_u585i_iot02a_defconfig @@ -6,12 +6,6 @@ CONFIG_SERIAL=y # enable GPIO CONFIG_GPIO=y -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - # console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/b_u585i_iot02a/b_u585i_iot02a_stm32u585xx_ns_defconfig b/boards/st/b_u585i_iot02a/b_u585i_iot02a_stm32u585xx_ns_defconfig index 2141cc748f8..fdb90af54d2 100644 --- a/boards/st/b_u585i_iot02a/b_u585i_iot02a_stm32u585xx_ns_defconfig +++ b/boards/st/b_u585i_iot02a/b_u585i_iot02a_stm32u585xx_ns_defconfig @@ -6,16 +6,12 @@ CONFIG_SERIAL=y # enable GPIO CONFIG_GPIO=y -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - # console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y -# enable pin controller -CONFIG_PINCTRL=y - CONFIG_ARM_TRUSTZONE_M=y CONFIG_RUNTIME_NMI=y CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +CONFIG_TFM_MCUBOOT_SIGNATURE_TYPE="RSA-3072" diff --git a/boards/st/b_u585i_iot02a/board.cmake b/boards/st/b_u585i_iot02a/board.cmake index 73320d749c6..84bf22d1162 100644 --- a/boards/st/b_u585i_iot02a/board.cmake +++ b/boards/st/b_u585i_iot02a/board.cmake @@ -12,8 +12,13 @@ if(CONFIG_BUILD_WITH_TFM) endif() endif() -board_runner_args(stm32cubeprogrammer "--erase" "--port=swd" "--reset-mode=hw") +# keep first +if(CONFIG_STM32_MEMMAP) board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +board_runner_args(stm32cubeprogrammer "--extload=MX25LM51245G_STM32U585I-IOT02A.stldr") +else() +board_runner_args(stm32cubeprogrammer "--erase" "--port=swd" "--reset-mode=hw") +endif() board_runner_args(openocd "--tcl-port=6666") board_runner_args(openocd --cmd-pre-init "gdb_report_data_abort enable") @@ -21,6 +26,7 @@ board_runner_args(openocd "--no-halt") board_runner_args(jlink "--device=STM32U585AI" "--reset-after-load") +# keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) # FIXME: openocd runner requires use of STMicro openocd fork. # Check board documentation for more details. diff --git a/boards/st/b_u585i_iot02a/doc/index.rst b/boards/st/b_u585i_iot02a/doc/index.rst index 0631b5b1ada..2400f75e3d1 100644 --- a/boards/st/b_u585i_iot02a/doc/index.rst +++ b/boards/st/b_u585i_iot02a/doc/index.rst @@ -220,7 +220,7 @@ The BOARD options are summarized below: +-------------------------------+-------------------------------------------+ Here are the instructions to build Zephyr with a non-secure configuration, -using `tfm_ipc_` sample: +using :zephyr:code-sample:`tfm_ipc` sample: .. code-block:: bash @@ -236,7 +236,7 @@ option bit TZEN will be set). $ west flash Please note that, after having run a TFM sample on the board, you will need to -run `./build/tfm/api_ns/regression.sh` once more to clean up the board from secure +run ``./build/tfm/api_ns/regression.sh`` once more to clean up the board from secure options and get back the platform back to a "normal" state and be able to run usual, non-TFM, binaries. Also note that, even then, TZEN will remain set, and you will need to use @@ -297,12 +297,16 @@ This probe allows to flash the board using various tools. Flashing ======== -Board is configured to be flashed using west STM32CubeProgrammer runner. -Installation of `STM32CubeProgrammer`_ is then required to flash the board. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. -Alternatively, openocd (provided in Zephyr SDK), JLink and pyocd can also be -used to flash and debug the board if west is told to use it as runner, -using ``-r openocd``. +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Connect the B_U585I_IOT02A Discovery kit to your host computer using the USB port, then run a serial host program to connect with your Discovery @@ -313,7 +317,7 @@ board. For example: $ minicom -D /dev/ttyACM0 Then, build and flash in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -329,7 +333,7 @@ You should see the following message on the console: Debugging ========= -Default flasher for this board is openocd. It could be used in the usual way. +Default flasher for this board is OpenOCD. It could be used in the usual way. Here is an example for the :zephyr:code-sample:`blinky` application. .. zephyr-app-commands:: diff --git a/boards/st/disco_l475_iot1/arduino_r3_connector.dtsi b/boards/st/disco_l475_iot1/arduino_r3_connector.dtsi index 05228c5ccb8..b48af67e2a1 100644 --- a/boards/st/disco_l475_iot1/arduino_r3_connector.dtsi +++ b/boards/st/disco_l475_iot1/arduino_r3_connector.dtsi @@ -35,6 +35,6 @@ }; }; -arduino_i2c: &i2c1 {}; +arduino_i2c: &i2c3 {}; arduino_spi: &spi1 {}; arduino_serial: &uart4 {}; diff --git a/boards/st/disco_l475_iot1/board.cmake b/boards/st/disco_l475_iot1/board.cmake index 7e6faf6c383..6eae838ebe3 100644 --- a/boards/st/disco_l475_iot1/board.cmake +++ b/boards/st/disco_l475_iot1/board.cmake @@ -1,8 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32L475VG" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) diff --git a/boards/st/disco_l475_iot1/disco_l475_iot1.dts b/boards/st/disco_l475_iot1/disco_l475_iot1.dts index 9b044533925..fbea236337d 100644 --- a/boards/st/disco_l475_iot1/disco_l475_iot1.dts +++ b/boards/st/disco_l475_iot1/disco_l475_iot1.dts @@ -50,6 +50,10 @@ compatible = "pwm-leds"; status = "disabled"; + /* + * green_pwm_1 is connected to CN1 pin 2 not LD1, since LD1 + * shares a pin with the Arduino SPI SCL line. + */ green_pwm_1: green_led_1 { pwms = <&pwm2 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>; label = "green LD1"; @@ -63,15 +67,15 @@ aliases { led0 = &green_led_2; led1 = &green_led_1; - pwm-led0 = &green_pwm_1; - pwm-led1 = &green_pwm_2; + pwm-led0 = &green_pwm_2; + pwm-led1 = &green_pwm_1; sw0 = &user_button; eswifi0 = &wifi0; watchdog0 = &iwdg; - spi-flash0 = &mx25r6435f; accel0 = &lsm6dsl; volt-sensor0 = &vref; volt-sensor1 = &vbat; + die-temp0 = &die_temp; }; }; @@ -247,7 +251,7 @@ pwm2: pwm { status = "okay"; - pinctrl-0 = <&tim2_ch1_pa15>; + pinctrl-0 = <&tim2_ch1_pa15>; /* CN1 pin 2 (ARD.D9-PWM) */ pinctrl-names = "default"; }; }; @@ -258,7 +262,7 @@ pwm15: pwm { status = "okay"; - pinctrl-0 = <&tim15_ch1_pb14>; /* CN1 D10 */ + pinctrl-0 = <&tim15_ch1_pb14>; /* LED2 */ pinctrl-names = "default"; }; }; diff --git a/boards/st/disco_l475_iot1/disco_l475_iot1.yaml b/boards/st/disco_l475_iot1/disco_l475_iot1.yaml index 6600d0724a8..83d7b66b0cb 100644 --- a/boards/st/disco_l475_iot1/disco_l475_iot1.yaml +++ b/boards/st/disco_l475_iot1/disco_l475_iot1.yaml @@ -26,6 +26,7 @@ supported: - qspi - dma - rtc + - usbd ram: 96 flash: 1024 vendor: st diff --git a/boards/st/disco_l475_iot1/disco_l475_iot1_defconfig b/boards/st/disco_l475_iot1/disco_l475_iot1_defconfig index 2ff706148f2..bdc37d30a6e 100644 --- a/boards/st/disco_l475_iot1/disco_l475_iot1_defconfig +++ b/boards/st/disco_l475_iot1/disco_l475_iot1_defconfig @@ -7,9 +7,6 @@ CONFIG_UART_INTERRUPT_DRIVEN=y # enable GPIO CONFIG_GPIO=y -# enable clock -CONFIG_CLOCK_CONTROL=y - # console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y @@ -19,6 +16,3 @@ CONFIG_ARM_MPU=y # Enable HW stack protection CONFIG_HW_STACK_PROTECTION=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/disco_l475_iot1/doc/index.rst b/boards/st/disco_l475_iot1/doc/index.rst index 63ccdd9582e..197881078a3 100644 --- a/boards/st/disco_l475_iot1/doc/index.rst +++ b/boards/st/disco_l475_iot1/doc/index.rst @@ -147,6 +147,8 @@ Connections and IOs Disco L475 IoT Board has 8 GPIO controllers. These controllers are responsible for pin muxing, input/output, pull-up, etc. +Note that LED LD1 and SPI1 SCK use the same GPIO pin and cannot be used simultaneously. + Available pins: --------------- @@ -163,8 +165,10 @@ Default Zephyr Peripheral Mapping: - SPI1 NSS/SCK/MISO/MOSI : PA2/PA5/PA6/PA7 (Arduino SPI) - SPI3 SCK/MISO/MOSI : PC10/PC11/PC12 (BT SPI bus) - PWM_2_CH1 : PA15 +- PWM_15_CH1 : PB14 (LD2) - USER_PB : PC13 -- LD2 : PA5 +- LD1 : PA5 (same as SPI1 SCK) +- LD2 : PB14 - ADC12_IN5 : PA0 - ADC123_IN3 : PC2 - ADC123_IN4 : PC3 @@ -189,6 +193,8 @@ Default settings are 115200 8N1. Programming and Debugging ************************* +Disco L475 IoT board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``disco_l475_iot1`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -196,14 +202,21 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Disco L475 IoT board includes an ST-LINK/V2-1 embedded debug tool -interface. This interface is supported by the openocd version -included in the Zephyr SDK since v0.9.2. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to Disco L475 IoT ----------------------------------------- -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Connect the Disco L475 IoT to your host computer using the USB port, then run a serial host program to connect with your Nucleo board. For example: @@ -229,7 +242,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -248,3 +261,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32L475 reference manual: https://www.st.com/resource/en/reference_manual/dm00083560.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_c031c6/board.cmake b/boards/st/nucleo_c031c6/board.cmake index d1a6cbfe6f2..b77e3f43c2f 100644 --- a/boards/st/nucleo_c031c6/board.cmake +++ b/boards/st/nucleo_c031c6/board.cmake @@ -1,5 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +# keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) diff --git a/boards/st/nucleo_c031c6/doc/index.rst b/boards/st/nucleo_c031c6/doc/index.rst index 8f44ab9d307..997b60e47e6 100644 --- a/boards/st/nucleo_c031c6/doc/index.rst +++ b/boards/st/nucleo_c031c6/doc/index.rst @@ -117,6 +117,8 @@ For more details please refer to `STM32 Nucleo-64 board User Manual`_. Programming and Debugging ************************* +Nucleo C031C6 board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``nucleo_c031c6`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -124,7 +126,8 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo C031C6 board includes an ST-LINK/V2-1 embedded debug tool interface. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. Flashing an application to Nucleo C031C6 ---------------------------------------- @@ -151,3 +154,6 @@ References .. _STM32 Nucleo-64 board User Manual: https://www.st.com/resource/en/user_manual/um2953-stm32c0-nucleo64-board-mb1717-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_c031c6/nucleo_c031c6_defconfig b/boards/st/nucleo_c031c6/nucleo_c031c6_defconfig index 1a570d28d13..d680df64400 100644 --- a/boards/st/nucleo_c031c6/nucleo_c031c6_defconfig +++ b/boards/st/nucleo_c031c6/nucleo_c031c6_defconfig @@ -10,9 +10,3 @@ CONFIG_UART_CONSOLE=y # GPIO Controller CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_f030r8/board.cmake b/boards/st/nucleo_f030r8/board.cmake index 594f36fd860..cd75a64d087 100644 --- a/boards/st/nucleo_f030r8/board.cmake +++ b/boards/st/nucleo_f030r8/board.cmake @@ -1,6 +1,12 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F030R8" "--speed=4000") +board_runner_args(probe-rs "--chip=STM32F030R8Tx") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/probe-rs.board.cmake) diff --git a/boards/st/nucleo_f030r8/doc/index.rst b/boards/st/nucleo_f030r8/doc/index.rst index a7479859d09..376faaa2d57 100644 --- a/boards/st/nucleo_f030r8/doc/index.rst +++ b/boards/st/nucleo_f030r8/doc/index.rst @@ -134,6 +134,8 @@ For more details please refer to `STM32 Nucleo-64 board User Manual`_. Programming and Debugging ************************* +Nucleo F030R8 board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``nucleo_f030r8`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -143,8 +145,17 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo F030R8 board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD, JLink, prob-rs can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink + $ west flash --runner prob-rs Flashing an application to Nucleo F030R8 ---------------------------------------- @@ -215,3 +226,6 @@ References .. _STM32 Nucleo-64 board User Manual: https://www.st.com/resource/en/user_manual/dm00105823.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_f030r8/nucleo_f030r8_defconfig b/boards/st/nucleo_f030r8/nucleo_f030r8_defconfig index 18ac599df25..bc6f05a7777 100644 --- a/boards/st/nucleo_f030r8/nucleo_f030r8_defconfig +++ b/boards/st/nucleo_f030r8/nucleo_f030r8_defconfig @@ -16,9 +16,3 @@ CONFIG_UART_CONSOLE=y # GPIO Controller CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_f031k6/board.cmake b/boards/st/nucleo_f031k6/board.cmake index bd51554e8c6..da308d3659a 100644 --- a/boards/st/nucleo_f031k6/board.cmake +++ b/boards/st/nucleo_f031k6/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F031K6" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f031k6/doc/index.rst b/boards/st/nucleo_f031k6/doc/index.rst index 99ae997ce26..ba1a44d8bc4 100644 --- a/boards/st/nucleo_f031k6/doc/index.rst +++ b/boards/st/nucleo_f031k6/doc/index.rst @@ -103,6 +103,8 @@ For more details please refer to `STM32 Nucleo-32 board User Manual`_. Programming and Debugging ************************* +Nucleo F031K6 board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``nucleo_f031k6`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -110,8 +112,16 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo F031K6 board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to Nucleo F030R8 ---------------------------------------- @@ -153,3 +163,6 @@ References .. _STM32 Nucleo-32 board User Manual: https://www.st.com/resource/en/user_manual/dm00231744-stm32-nucleo32-boards-mb1180-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_f031k6/nucleo_f031k6_defconfig b/boards/st/nucleo_f031k6/nucleo_f031k6_defconfig index 62817c1ba47..fdc64d65e1a 100644 --- a/boards/st/nucleo_f031k6/nucleo_f031k6_defconfig +++ b/boards/st/nucleo_f031k6/nucleo_f031k6_defconfig @@ -1,6 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 - # Kernel Options due to Low Memory (4k) CONFIG_MAIN_STACK_SIZE=512 CONFIG_IDLE_STACK_SIZE=150 @@ -18,9 +17,3 @@ CONFIG_UART_CONSOLE=y # GPIO Controller CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_f042k6/board.cmake b/boards/st/nucleo_f042k6/board.cmake index 807467728e0..3b4c81fc151 100644 --- a/boards/st/nucleo_f042k6/board.cmake +++ b/boards/st/nucleo_f042k6/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F042K6" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f042k6/doc/index.rst b/boards/st/nucleo_f042k6/doc/index.rst index a1d90c8c4f3..7d0ec6e2a2b 100644 --- a/boards/st/nucleo_f042k6/doc/index.rst +++ b/boards/st/nucleo_f042k6/doc/index.rst @@ -103,6 +103,8 @@ For more details please refer to `STM32 Nucleo-32 board User Manual`_. Programming and Debugging ************************* +Nucleo F042K6 board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``nucleo_f042k6`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -110,8 +112,16 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo F042K6 board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to Nucleo F042K6 ---------------------------------------- @@ -153,3 +163,6 @@ References .. _STM32 Nucleo-32 board User Manual: https://www.st.com/resource/en/user_manual/dm00231744-stm32-nucleo32-boards-mb1180-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_f042k6/nucleo_f042k6.dts b/boards/st/nucleo_f042k6/nucleo_f042k6.dts index ac1659dfc39..74d700c9c1d 100644 --- a/boards/st/nucleo_f042k6/nucleo_f042k6.dts +++ b/boards/st/nucleo_f042k6/nucleo_f042k6.dts @@ -117,3 +117,9 @@ &vbat { status = "okay"; }; + +zephyr_udc0: &usb { + pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/st/nucleo_f042k6/nucleo_f042k6.yaml b/boards/st/nucleo_f042k6/nucleo_f042k6.yaml index 76a2888138b..a86f5dddaeb 100644 --- a/boards/st/nucleo_f042k6/nucleo_f042k6.yaml +++ b/boards/st/nucleo_f042k6/nucleo_f042k6.yaml @@ -13,6 +13,7 @@ supported: - spi - gpio - adc + - usbd testing: ignore_tags: - net diff --git a/boards/st/nucleo_f042k6/nucleo_f042k6_defconfig b/boards/st/nucleo_f042k6/nucleo_f042k6_defconfig index 06e8a32bb1f..e3d8f7bb3d2 100644 --- a/boards/st/nucleo_f042k6/nucleo_f042k6_defconfig +++ b/boards/st/nucleo_f042k6/nucleo_f042k6_defconfig @@ -9,9 +9,3 @@ CONFIG_UART_CONSOLE=y # GPIO Controller CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_f070rb/board.cmake b/boards/st/nucleo_f070rb/board.cmake index 1237980142c..720e4e00ab5 100644 --- a/boards/st/nucleo_f070rb/board.cmake +++ b/boards/st/nucleo_f070rb/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F070RB" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f070rb/doc/index.rst b/boards/st/nucleo_f070rb/doc/index.rst index e8d9f40a77b..acecfb20979 100644 --- a/boards/st/nucleo_f070rb/doc/index.rst +++ b/boards/st/nucleo_f070rb/doc/index.rst @@ -133,6 +133,8 @@ For more details please refer to `STM32 Nucleo-64 board User Manual`_. Programming and Debugging ************************* +Nucleo F070RB board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``nucleo_f070rb`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -140,8 +142,16 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo F070RB board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to Nucleo F070RB ---------------------------------------- @@ -159,7 +169,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -180,3 +190,6 @@ References .. _STM32 Nucleo-64 board User Manual: https://www.st.com/resource/en/user_manual/dm00105823.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_f070rb/nucleo_f070rb_defconfig b/boards/st/nucleo_f070rb/nucleo_f070rb_defconfig index bee511a2809..e3d8f7bb3d2 100644 --- a/boards/st/nucleo_f070rb/nucleo_f070rb_defconfig +++ b/boards/st/nucleo_f070rb/nucleo_f070rb_defconfig @@ -9,9 +9,3 @@ CONFIG_UART_CONSOLE=y # GPIO Controller CONFIG_GPIO=y - -# Enable clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_f091rc/board.cmake b/boards/st/nucleo_f091rc/board.cmake index 690716f6c5f..f465bc737b1 100644 --- a/boards/st/nucleo_f091rc/board.cmake +++ b/boards/st/nucleo_f091rc/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F091RC" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f091rc/doc/index.rst b/boards/st/nucleo_f091rc/doc/index.rst index a83b00bd82a..2cce144c1fb 100644 --- a/boards/st/nucleo_f091rc/doc/index.rst +++ b/boards/st/nucleo_f091rc/doc/index.rst @@ -150,6 +150,8 @@ For more details please refer to `STM32 Nucleo-64 board User Manual`_. Programming and Debugging ************************* +Nucleo F091RC board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``nucleo_f091rc`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -157,8 +159,16 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo F091RC board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to Nucleo F091RC ---------------------------------------- @@ -176,7 +186,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -197,3 +207,6 @@ References .. _STM32 Nucleo-64 board User Manual: https://www.st.com/resource/en/user_manual/dm00105823.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_f091rc/nucleo_f091rc_defconfig b/boards/st/nucleo_f091rc/nucleo_f091rc_defconfig index 06e8a32bb1f..e3d8f7bb3d2 100644 --- a/boards/st/nucleo_f091rc/nucleo_f091rc_defconfig +++ b/boards/st/nucleo_f091rc/nucleo_f091rc_defconfig @@ -9,9 +9,3 @@ CONFIG_UART_CONSOLE=y # GPIO Controller CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_f103rb/board.cmake b/boards/st/nucleo_f103rb/board.cmake index 51a6e9ef3bd..724e7b7141f 100644 --- a/boards/st/nucleo_f103rb/board.cmake +++ b/boards/st/nucleo_f103rb/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F103RB" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f103rb/doc/index.rst b/boards/st/nucleo_f103rb/doc/index.rst index e2313c5e932..8a9baaea537 100644 --- a/boards/st/nucleo_f103rb/doc/index.rst +++ b/boards/st/nucleo_f103rb/doc/index.rst @@ -136,6 +136,8 @@ For more details please refer to `STM32 Nucleo-64 board User Manual`_. Programming and Debugging ************************* +Nucleo F103RB board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``nucleo_f103rb`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -143,8 +145,16 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo F103RB board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to Nucleo F103RB ---------------------------------------- @@ -186,3 +196,6 @@ References .. _STM32 Nucleo-64 board User Manual: https://www.st.com/resource/en/user_manual/dm00105823.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_f103rb/nucleo_f103rb.dts b/boards/st/nucleo_f103rb/nucleo_f103rb.dts index 1f225b41312..53b9089e554 100644 --- a/boards/st/nucleo_f103rb/nucleo_f103rb.dts +++ b/boards/st/nucleo_f103rb/nucleo_f103rb.dts @@ -69,6 +69,7 @@ ahb-prescaler = <1>; apb1-prescaler = <2>; apb2-prescaler = <1>; + adc-prescaler = <2>; }; &usart1 { diff --git a/boards/st/nucleo_f103rb/nucleo_f103rb_defconfig b/boards/st/nucleo_f103rb/nucleo_f103rb_defconfig index d4828716f02..5568aa36c02 100644 --- a/boards/st/nucleo_f103rb/nucleo_f103rb_defconfig +++ b/boards/st/nucleo_f103rb/nucleo_f103rb_defconfig @@ -8,9 +8,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# enable clock -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_f207zg/board.cmake b/boards/st/nucleo_f207zg/board.cmake index cf18155b5f3..8c62e3ccbbf 100644 --- a/boards/st/nucleo_f207zg/board.cmake +++ b/boards/st/nucleo_f207zg/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F207ZG" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f207zg/doc/index.rst b/boards/st/nucleo_f207zg/doc/index.rst index 032cf2ab859..17d51354dde 100644 --- a/boards/st/nucleo_f207zg/doc/index.rst +++ b/boards/st/nucleo_f207zg/doc/index.rst @@ -192,7 +192,20 @@ Programming and Debugging ************************* Nucleo F207ZG board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. + +Flashing +======== + +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink .. _Nucleo F207ZG website: @@ -206,3 +219,6 @@ This interface is supported by the openocd version included in Zephyr SDK. .. _STM32F207 reference manual: https://www.st.com/resource/en/reference_manual/cd00225773.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_f207zg/nucleo_f207zg.yaml b/boards/st/nucleo_f207zg/nucleo_f207zg.yaml index aeb13880f84..681cc571c0e 100644 --- a/boards/st/nucleo_f207zg/nucleo_f207zg.yaml +++ b/boards/st/nucleo_f207zg/nucleo_f207zg.yaml @@ -25,4 +25,5 @@ supported: - rng - dma - rtc + - usbd vendor: st diff --git a/boards/st/nucleo_f207zg/nucleo_f207zg_defconfig b/boards/st/nucleo_f207zg/nucleo_f207zg_defconfig index 2f2243e0a3b..737e0da2814 100644 --- a/boards/st/nucleo_f207zg/nucleo_f207zg_defconfig +++ b/boards/st/nucleo_f207zg/nucleo_f207zg_defconfig @@ -14,9 +14,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_f302r8/board.cmake b/boards/st/nucleo_f302r8/board.cmake index 7a5cef9c37e..4a80e30f04f 100644 --- a/boards/st/nucleo_f302r8/board.cmake +++ b/boards/st/nucleo_f302r8/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F302R8" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f302r8/doc/index.rst b/boards/st/nucleo_f302r8/doc/index.rst index 88afebe40cb..8cb3f9e8a13 100644 --- a/boards/st/nucleo_f302r8/doc/index.rst +++ b/boards/st/nucleo_f302r8/doc/index.rst @@ -43,7 +43,7 @@ The Nucleo F302R8 provides the following hardware components: - ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU - 72 MHz max CPU frequency - VDD from 2.0 V to 3.6 V -- 64 MB Flash +- 64 KB Flash - 16 KB SRAM - RTC - Advanced-control Timer @@ -149,7 +149,20 @@ Programming and Debugging ************************* The Nucleo F302R8 board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. + +Flashing +======== + +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink .. _Nucleo F302R8 website: @@ -166,3 +179,6 @@ This interface is supported by the openocd version included in Zephyr SDK. .. _STM32F302R8 datasheet: https://www.st.com/resource/en/datasheet/stm32f302r8.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_f302r8/nucleo_f302r8_defconfig b/boards/st/nucleo_f302r8/nucleo_f302r8_defconfig index ed6630de61e..111e2eb113b 100644 --- a/boards/st/nucleo_f302r8/nucleo_f302r8_defconfig +++ b/boards/st/nucleo_f302r8/nucleo_f302r8_defconfig @@ -8,9 +8,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_f303k8/board.cmake b/boards/st/nucleo_f303k8/board.cmake index 98c430bd2af..179e15cfcab 100644 --- a/boards/st/nucleo_f303k8/board.cmake +++ b/boards/st/nucleo_f303k8/board.cmake @@ -1,11 +1,13 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F303K8" "--speed=4000") board_runner_args(pyocd "--target=stm32f303k8tx") board_runner_args(pyocd "--flash-opt=-O reset_type=hw") board_runner_args(pyocd "--flash-opt=-O connect_mode=under-reset") -board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +# keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/st/nucleo_f303k8/doc/index.rst b/boards/st/nucleo_f303k8/doc/index.rst index 1f8ff4a3250..e659d453a80 100644 --- a/boards/st/nucleo_f303k8/doc/index.rst +++ b/boards/st/nucleo_f303k8/doc/index.rst @@ -40,7 +40,7 @@ The Nucleo F303K8 provides the following hardware components: - ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU - 72 MHz max CPU frequency - VDD from 2.0 V to 3.6 V -- 64 MB Flash +- 64 KB Flash - 12 KB SRAM - RTC - Advanced-control Timer @@ -118,7 +118,7 @@ The Nucleo F303K8 board features an Arduino Zero V3 connector. Board is configur - UART_2 TX/RX : PA2/PA15 (ST-Link Virtual Port Com) - I2C1 SCL/SDA : PB7/PB6 -- SPI1 CS/SCK/MISO/MOSI : PA_4/PA_5/PB_4/PA_7 +- SPI1 CS/SCK/MISO/MOSI : PA_4/PA_5/PA_6/PA_7 - LD2 : PB3 System Clock @@ -140,7 +140,21 @@ Programming and Debugging ************************* The Nucleo F303K8 board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. + +Flashing +======== + +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD, JLink, or pyOCD can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink + $ west flash --runner pyocd .. _Nucleo F303K8 website: @@ -157,3 +171,6 @@ This interface is supported by the openocd version included in Zephyr SDK. .. _STM32F303K8 datasheet: https://www.st.com/resource/en/datasheet/stm32f303k8.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_f303k8/nucleo_f303k8.dts b/boards/st/nucleo_f303k8/nucleo_f303k8.dts index 1090ae23ab2..efdf58a848f 100644 --- a/boards/st/nucleo_f303k8/nucleo_f303k8.dts +++ b/boards/st/nucleo_f303k8/nucleo_f303k8.dts @@ -63,6 +63,7 @@ ahb-prescaler = <1>; apb1-prescaler = <2>; apb2-prescaler = <1>; + adc12-prescaler = <0>; }; &timers2 { diff --git a/boards/st/nucleo_f303k8/nucleo_f303k8_defconfig b/boards/st/nucleo_f303k8/nucleo_f303k8_defconfig index ed6630de61e..111e2eb113b 100644 --- a/boards/st/nucleo_f303k8/nucleo_f303k8_defconfig +++ b/boards/st/nucleo_f303k8/nucleo_f303k8_defconfig @@ -8,9 +8,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_f303re/board.cmake b/boards/st/nucleo_f303re/board.cmake index 95fc7d4239a..a080f9119e1 100644 --- a/boards/st/nucleo_f303re/board.cmake +++ b/boards/st/nucleo_f303re/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F303RE" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f303re/doc/index.rst b/boards/st/nucleo_f303re/doc/index.rst index 967079f1ff3..dc7d7e2d0a6 100644 --- a/boards/st/nucleo_f303re/doc/index.rst +++ b/boards/st/nucleo_f303re/doc/index.rst @@ -43,7 +43,7 @@ The Nucleo F303RE provides the following hardware components: - ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU - 72 MHz max CPU frequency - VDD from 2.0 V to 3.6 V -- 512 MB Flash +- 512 KB Flash - 64 + 16 KB SRAM - RTC - Advanced-control Timer @@ -143,7 +143,20 @@ Programming and Debugging ************************* The Nucleo F303RE board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. + +Flashing +======== + +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink .. _Nucleo F303RE website: @@ -160,3 +173,6 @@ This interface is supported by the openocd version included in Zephyr SDK. .. _STM32F303RE datasheet: https://www.st.com/resource/en/datasheet/stm32f303re.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_f303re/nucleo_f303re.dts b/boards/st/nucleo_f303re/nucleo_f303re.dts index af1bea6d92a..efa840c140a 100644 --- a/boards/st/nucleo_f303re/nucleo_f303re.dts +++ b/boards/st/nucleo_f303re/nucleo_f303re.dts @@ -69,6 +69,8 @@ ahb-prescaler = <1>; apb1-prescaler = <2>; apb2-prescaler = <1>; + adc12-prescaler = <0>; + adc34-prescaler = <0>; }; &usart2 { diff --git a/boards/st/nucleo_f303re/nucleo_f303re_defconfig b/boards/st/nucleo_f303re/nucleo_f303re_defconfig index 2f2243e0a3b..737e0da2814 100644 --- a/boards/st/nucleo_f303re/nucleo_f303re_defconfig +++ b/boards/st/nucleo_f303re/nucleo_f303re_defconfig @@ -14,9 +14,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_f334r8/board.cmake b/boards/st/nucleo_f334r8/board.cmake index 516a7ddfb13..e98f17692ec 100644 --- a/boards/st/nucleo_f334r8/board.cmake +++ b/boards/st/nucleo_f334r8/board.cmake @@ -1,11 +1,13 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F334R8" "--speed=4000") board_runner_args(pyocd "--target=stm32f334r8tx") board_runner_args(pyocd "--flash-opt=-O reset_type=hw") board_runner_args(pyocd "--flash-opt=-O connect_mode=under-reset") -board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +# keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/st/nucleo_f334r8/doc/index.rst b/boards/st/nucleo_f334r8/doc/index.rst index 10e31269624..0115b2bda9c 100644 --- a/boards/st/nucleo_f334r8/doc/index.rst +++ b/boards/st/nucleo_f334r8/doc/index.rst @@ -128,6 +128,8 @@ For more details please refer to `STM32 Nucleo-64 board User Manual`_. Programming and Debugging ************************* +Nucleo F334R8 board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``nucleo_f334r8`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -135,8 +137,17 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo F334R8 board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD, JLink, or pyOCD can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink + $ west flash --runner pyocd Flashing an application to Nucleo F334R8 ---------------------------------------- @@ -177,3 +188,6 @@ References .. _STM32 Nucleo-64 board User Manual: https://www.st.com/resource/en/user_manual/dm00105823.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_f334r8/nucleo_f334r8_defconfig b/boards/st/nucleo_f334r8/nucleo_f334r8_defconfig index d20d3802415..c60dfffbc3b 100644 --- a/boards/st/nucleo_f334r8/nucleo_f334r8_defconfig +++ b/boards/st/nucleo_f334r8/nucleo_f334r8_defconfig @@ -10,9 +10,3 @@ CONFIG_UART_CONSOLE=y # GPIO Controller CONFIG_GPIO=y - -# Enable clock -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_f401re/board.cmake b/boards/st/nucleo_f401re/board.cmake index 2345a9299f9..65321107f3a 100644 --- a/boards/st/nucleo_f401re/board.cmake +++ b/boards/st/nucleo_f401re/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F401RE" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f401re/doc/index.rst b/boards/st/nucleo_f401re/doc/index.rst index 4b848eb1017..123992ac18b 100644 --- a/boards/st/nucleo_f401re/doc/index.rst +++ b/boards/st/nucleo_f401re/doc/index.rst @@ -148,6 +148,8 @@ Nucleo F401RE board has up to 3 I2Cs. The default I2C mapping for Zephyr is: Programming and Debugging ************************* +Nucleo F401RE board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``nucleo_f401re`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -155,8 +157,16 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo F401RE board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to Nucleo F401RE ---------------------------------------- @@ -169,7 +179,7 @@ then run a serial host program to connect with your Nucleo board: $ minicom -D /dev/ttyACM0 Now build and flash an application. Here is an example for -:ref:`hello_world`. +:zephyr:code-sample:`hello_world`. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -187,7 +197,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -206,3 +216,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32F401 reference manual: https://www.st.com/resource/en/reference_manual/dm00096844.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_f401re/nucleo_f401re_defconfig b/boards/st/nucleo_f401re/nucleo_f401re_defconfig index 750f99bdff3..51eadcb4809 100644 --- a/boards/st/nucleo_f401re/nucleo_f401re_defconfig +++ b/boards/st/nucleo_f401re/nucleo_f401re_defconfig @@ -14,9 +14,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# clock configuration -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_f410rb/board.cmake b/boards/st/nucleo_f410rb/board.cmake index 2cc7742cc2d..5eb1ca02345 100644 --- a/boards/st/nucleo_f410rb/board.cmake +++ b/boards/st/nucleo_f410rb/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F410RB" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f410rb/doc/index.rst b/boards/st/nucleo_f410rb/doc/index.rst index 58579bce21c..af87b501923 100644 --- a/boards/st/nucleo_f410rb/doc/index.rst +++ b/boards/st/nucleo_f410rb/doc/index.rst @@ -153,6 +153,8 @@ Default settings are 115200 8N1. Programming and Debugging ************************* +Nucleo F410RB board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``nucleo_f410rb`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -160,13 +162,21 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo F410RB board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to Nucleo F410RB ---------------------------------------- -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board. @@ -191,7 +201,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -210,3 +220,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32F410 reference manual: https://www.st.com/resource/en/reference_manual/dm00180366.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_f410rb/nucleo_f410rb_defconfig b/boards/st/nucleo_f410rb/nucleo_f410rb_defconfig index c729b83e3d0..51eadcb4809 100644 --- a/boards/st/nucleo_f410rb/nucleo_f410rb_defconfig +++ b/boards/st/nucleo_f410rb/nucleo_f410rb_defconfig @@ -14,9 +14,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_f411re/board.cmake b/boards/st/nucleo_f411re/board.cmake index 5cd8f3b7096..2015a3f497a 100644 --- a/boards/st/nucleo_f411re/board.cmake +++ b/boards/st/nucleo_f411re/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F411RE" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f411re/doc/index.rst b/boards/st/nucleo_f411re/doc/index.rst index 77ca25184c6..e4c10085d9b 100644 --- a/boards/st/nucleo_f411re/doc/index.rst +++ b/boards/st/nucleo_f411re/doc/index.rst @@ -141,6 +141,8 @@ Default settings are 115200 8N1. Programming and Debugging ************************* +Nucleo F411RE board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``nucleo_f411re`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -148,13 +150,21 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo F411RE board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to Nucleo F411RE ---------------------------------------- -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board. @@ -179,7 +189,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -198,3 +208,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32F411 reference manual: https://www.st.com/resource/en/reference_manual/dm00119316.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_f411re/nucleo_f411re_defconfig b/boards/st/nucleo_f411re/nucleo_f411re_defconfig index 750f99bdff3..51eadcb4809 100644 --- a/boards/st/nucleo_f411re/nucleo_f411re_defconfig +++ b/boards/st/nucleo_f411re/nucleo_f411re_defconfig @@ -14,9 +14,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# clock configuration -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_f412zg/board.cmake b/boards/st/nucleo_f412zg/board.cmake index 8b2cd0fca43..be8b35e82c8 100644 --- a/boards/st/nucleo_f412zg/board.cmake +++ b/boards/st/nucleo_f412zg/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F412ZG" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f412zg/doc/index.rst b/boards/st/nucleo_f412zg/doc/index.rst index 40039aed089..f3f1cf0db75 100644 --- a/boards/st/nucleo_f412zg/doc/index.rst +++ b/boards/st/nucleo_f412zg/doc/index.rst @@ -156,7 +156,20 @@ Programming and Debugging ************************* Nucleo F412ZG board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. + +Flashing +======== + +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink .. _Nucleo F412ZG website: @@ -170,3 +183,6 @@ This interface is supported by the openocd version included in Zephyr SDK. .. _STM32F412 reference manual: https://www.st.com/resource/en/reference_manual/dm00180369.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_f412zg/nucleo_f412zg_defconfig b/boards/st/nucleo_f412zg/nucleo_f412zg_defconfig index c729b83e3d0..51eadcb4809 100644 --- a/boards/st/nucleo_f412zg/nucleo_f412zg_defconfig +++ b/boards/st/nucleo_f412zg/nucleo_f412zg_defconfig @@ -14,9 +14,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_f413zh/board.cmake b/boards/st/nucleo_f413zh/board.cmake index 0fbe4518143..800b779a42d 100644 --- a/boards/st/nucleo_f413zh/board.cmake +++ b/boards/st/nucleo_f413zh/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F413ZH" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f413zh/doc/index.rst b/boards/st/nucleo_f413zh/doc/index.rst index c6452fb4456..1240923df82 100644 --- a/boards/st/nucleo_f413zh/doc/index.rst +++ b/boards/st/nucleo_f413zh/doc/index.rst @@ -158,7 +158,20 @@ Programming and Debugging ************************* Nucleo F413ZH board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. + +Flashing +======== + +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink .. _Nucleo F413ZH website: @@ -172,3 +185,6 @@ This interface is supported by the openocd version included in Zephyr SDK. .. _STM32F413/423 reference manual: https://www.st.com/resource/en/reference_manual/dm00305666.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_f413zh/nucleo_f413zh_defconfig b/boards/st/nucleo_f413zh/nucleo_f413zh_defconfig index c729b83e3d0..51eadcb4809 100644 --- a/boards/st/nucleo_f413zh/nucleo_f413zh_defconfig +++ b/boards/st/nucleo_f413zh/nucleo_f413zh_defconfig @@ -14,9 +14,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_f429zi/board.cmake b/boards/st/nucleo_f429zi/board.cmake index 7e8103a64b0..49ab35806ca 100644 --- a/boards/st/nucleo_f429zi/board.cmake +++ b/boards/st/nucleo_f429zi/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F429ZI" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f429zi/doc/index.rst b/boards/st/nucleo_f429zi/doc/index.rst index c15e524238b..924c30de42b 100644 --- a/boards/st/nucleo_f429zi/doc/index.rst +++ b/boards/st/nucleo_f429zi/doc/index.rst @@ -181,7 +181,20 @@ Programming and Debugging ************************* The Nucleo F429ZI board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. + +Flashing +======== + +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flash partitions for MCUBoot bootloader *************************************** @@ -217,3 +230,6 @@ A specific application can adjust each partition size based on its needs. .. _MCUBoot: https://github.com/JuulLabs-OSS/mcuboot/blob/master/README.md + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_f429zi/nucleo_f429zi.yaml b/boards/st/nucleo_f429zi/nucleo_f429zi.yaml index f8c167bc5ef..8674acc45c8 100644 --- a/boards/st/nucleo_f429zi/nucleo_f429zi.yaml +++ b/boards/st/nucleo_f429zi/nucleo_f429zi.yaml @@ -25,4 +25,5 @@ supported: - dma - nvs - rtc + - usbd vendor: st diff --git a/boards/st/nucleo_f429zi/nucleo_f429zi_defconfig b/boards/st/nucleo_f429zi/nucleo_f429zi_defconfig index 750f99bdff3..51eadcb4809 100644 --- a/boards/st/nucleo_f429zi/nucleo_f429zi_defconfig +++ b/boards/st/nucleo_f429zi/nucleo_f429zi_defconfig @@ -14,9 +14,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# clock configuration -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_f446re/board.cmake b/boards/st/nucleo_f446re/board.cmake index bc1e4722363..b7d889530e8 100644 --- a/boards/st/nucleo_f446re/board.cmake +++ b/boards/st/nucleo_f446re/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F446RE" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f446re/doc/index.rst b/boards/st/nucleo_f446re/doc/index.rst index 28fe7699e60..e111880ef32 100644 --- a/boards/st/nucleo_f446re/doc/index.rst +++ b/boards/st/nucleo_f446re/doc/index.rst @@ -164,6 +164,8 @@ used with `RS485 CAN Shield`_. Programming and Debugging ************************* +Nucleo F446RE board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``nucleo_f446re`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -171,13 +173,21 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo F446RE board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to Nucleo F446RE ---------------------------------------- -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board. @@ -202,7 +212,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -224,3 +234,6 @@ You can debug an application in the usual way. Here is an example for the .. _RS485 CAN Shield: https://www.waveshare.com/wiki/RS485_CAN_Shield + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_f446re/nucleo_f446re_defconfig b/boards/st/nucleo_f446re/nucleo_f446re_defconfig index c729b83e3d0..51eadcb4809 100644 --- a/boards/st/nucleo_f446re/nucleo_f446re_defconfig +++ b/boards/st/nucleo_f446re/nucleo_f446re_defconfig @@ -14,9 +14,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_f446ze/board.cmake b/boards/st/nucleo_f446ze/board.cmake index 715b84061aa..33af015beeb 100644 --- a/boards/st/nucleo_f446ze/board.cmake +++ b/boards/st/nucleo_f446ze/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F446ZE" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f446ze/doc/index.rst b/boards/st/nucleo_f446ze/doc/index.rst index d99167db159..0029f016ccf 100644 --- a/boards/st/nucleo_f446ze/doc/index.rst +++ b/boards/st/nucleo_f446ze/doc/index.rst @@ -189,6 +189,8 @@ The TX/RX wires are connected with pins 25/27 of CN9 connector. Programming and Debugging ************************* +Nucleo F446ZE board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``nucleo_f446ze`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -196,13 +198,21 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo F446ZE board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to Nucleo F446ZE ---------------------------------------- -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board. @@ -227,7 +237,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -246,3 +256,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32F446 reference manual: https://www.st.com/resource/en/reference_manual/dm00135183.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_f446ze/nucleo_f446ze_defconfig b/boards/st/nucleo_f446ze/nucleo_f446ze_defconfig index c729b83e3d0..51eadcb4809 100644 --- a/boards/st/nucleo_f446ze/nucleo_f446ze_defconfig +++ b/boards/st/nucleo_f446ze/nucleo_f446ze_defconfig @@ -14,9 +14,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_f722ze/board.cmake b/boards/st/nucleo_f722ze/board.cmake index 6335e34584a..fc8e64fe0b5 100644 --- a/boards/st/nucleo_f722ze/board.cmake +++ b/boards/st/nucleo_f722ze/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F722ZE" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f722ze/doc/index.rst b/boards/st/nucleo_f722ze/doc/index.rst index 83b54130405..fde339622a8 100644 --- a/boards/st/nucleo_f722ze/doc/index.rst +++ b/boards/st/nucleo_f722ze/doc/index.rst @@ -182,15 +182,26 @@ Programming and Debugging ************************* The ``nucleo_f722ze`` can be flashed and debugged in the typical manner. -The Nucleo F722ZE board includes an ST-LINK V2-1 debugger, which can be used -with the OpenOCD version provided with the Zephyr SDK. Refer to -:ref:`build_an_application` and :ref:`application_run` for detailed +The Nucleo F722ZE board includes an ST-LINK V2-1 debugger. + +Refer to :ref:`build_an_application` and :ref:`application_run` for detailed instructions. Flashing ======== -Build the :ref:`hello_world` application and flash it using the on-board +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink + +Build the :zephyr:code-sample:`hello_world` application and flash it using the on-board ST-LINK interface: .. zephyr-app-commands:: @@ -207,14 +218,6 @@ Debugging :maybe-skip-config: :goals: debug -J-Link OB Firmware ------------------- - -Like many other STM32 evaluation boards, the Nucleo F722ZE's on-board ST-LINK -debug interface may be flashed with `SEGGER J-Link OB firmware`_. This -firmware turns the ST-LINK into a J-Link probe. If the on-board debugger has -been re-flashed with J-Link OB firmware, simply append ``--runner jlink`` to -all flashing/debugging commands. References ********** @@ -243,3 +246,6 @@ More information about Nucleo F722ZE: .. _STM32 Nucleo-144 User Manual (UM1974): https://www.st.com/resource/en/user_manual/um1974-stm32-nucleo144-boards-mb1137-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_f722ze/nucleo_f722ze_defconfig b/boards/st/nucleo_f722ze/nucleo_f722ze_defconfig index 86e44f22e55..6f3d02241a3 100644 --- a/boards/st/nucleo_f722ze/nucleo_f722ze_defconfig +++ b/boards/st/nucleo_f722ze/nucleo_f722ze_defconfig @@ -15,9 +15,3 @@ CONFIG_UART_CONSOLE=y # Enable GPIO CONFIG_GPIO=y - -# Enable clocks -CONFIG_CLOCK_CONTROL=y - -# Enable pinctrl -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_f746zg/board.cmake b/boards/st/nucleo_f746zg/board.cmake index 718b783f69d..d1b2798ccdd 100644 --- a/boards/st/nucleo_f746zg/board.cmake +++ b/boards/st/nucleo_f746zg/board.cmake @@ -1,8 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F746ZG" "--speed=4000") +# keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f746zg/doc/index.rst b/boards/st/nucleo_f746zg/doc/index.rst index f0641545170..59566cf34c7 100644 --- a/boards/st/nucleo_f746zg/doc/index.rst +++ b/boards/st/nucleo_f746zg/doc/index.rst @@ -179,6 +179,8 @@ do it by removing ``SB156`` jumper on the back side of the board. Programming and Debugging ************************* +Nucleo F746ZG board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``nucleo_f746zg`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -186,23 +188,21 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo F746ZG board includes an ST-LINK/V2-1 embedded debug tool interface. - -Flashing an application to Nucleo F746ZG ----------------------------------------- - The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, -so its installation is required to be able to flash the board. +so its :ref:`installation ` is required. -Alternatively, openocd (provided in Zephyr SDK) or JLink can also be used to -flash the board using the ``--runner`` (or ``-r``) option: +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: .. code-block:: console $ west flash --runner openocd $ west flash --runner jlink -Here is an example for the :ref:`hello_world` application. +Flashing an application to Nucleo F746ZG +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board. @@ -227,7 +227,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_f746zg/nucleo_f746zg_defconfig b/boards/st/nucleo_f746zg/nucleo_f746zg_defconfig index 261e47c2d53..2ccb0d375b5 100644 --- a/boards/st/nucleo_f746zg/nucleo_f746zg_defconfig +++ b/boards/st/nucleo_f746zg/nucleo_f746zg_defconfig @@ -15,9 +15,3 @@ CONFIG_UART_CONSOLE=y # Enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_f756zg/board.cmake b/boards/st/nucleo_f756zg/board.cmake index 78ef5cce6a5..d6a50cef168 100644 --- a/boards/st/nucleo_f756zg/board.cmake +++ b/boards/st/nucleo_f756zg/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F756ZG" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f756zg/doc/index.rst b/boards/st/nucleo_f756zg/doc/index.rst index fd8b5f259c3..6d512dcca37 100644 --- a/boards/st/nucleo_f756zg/doc/index.rst +++ b/boards/st/nucleo_f756zg/doc/index.rst @@ -160,6 +160,8 @@ assigned to UART3. Default settings are 115200 8N1. Programming and Debugging ************************* +Nucleo F756ZG board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``nucleo_f756zg`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -167,12 +169,21 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo F756ZG board includes an ST-LINK/V2-1 embedded debug tool interface. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to Nucleo F756ZG ---------------------------------------- -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board. @@ -197,7 +208,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -216,3 +227,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32F756 reference manual: https://www.st.com/resource/en/reference_manual/dm00124865.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_f756zg/nucleo_f756zg.yaml b/boards/st/nucleo_f756zg/nucleo_f756zg.yaml index ddcf34064ad..4b12d824b3b 100644 --- a/boards/st/nucleo_f756zg/nucleo_f756zg.yaml +++ b/boards/st/nucleo_f756zg/nucleo_f756zg.yaml @@ -19,4 +19,5 @@ supported: - i2c - pwm - spi + - usbd vendor: st diff --git a/boards/st/nucleo_f756zg/nucleo_f756zg_defconfig b/boards/st/nucleo_f756zg/nucleo_f756zg_defconfig index 261e47c2d53..2ccb0d375b5 100644 --- a/boards/st/nucleo_f756zg/nucleo_f756zg_defconfig +++ b/boards/st/nucleo_f756zg/nucleo_f756zg_defconfig @@ -15,9 +15,3 @@ CONFIG_UART_CONSOLE=y # Enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_f767zi/board.cmake b/boards/st/nucleo_f767zi/board.cmake index 796c2a4f35a..3df233b4a75 100644 --- a/boards/st/nucleo_f767zi/board.cmake +++ b/boards/st/nucleo_f767zi/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F767ZI" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_f767zi/doc/index.rst b/boards/st/nucleo_f767zi/doc/index.rst index 5dec0099d90..e0b50050151 100644 --- a/boards/st/nucleo_f767zi/doc/index.rst +++ b/boards/st/nucleo_f767zi/doc/index.rst @@ -180,6 +180,8 @@ assigned to UART3. Default settings are 115200 8N1. Programming and Debugging ************************* +Nucleo F767ZI board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``nucleo_f767zi`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -187,12 +189,21 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo F767ZI board includes an ST-LINK/V2-1 embedded debug tool interface. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to Nucleo F767ZI ---------------------------------------- -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board. @@ -217,7 +228,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -236,3 +247,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32F767 reference manual: https://www.st.com/resource/en/reference_manual/DM00224583.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_f767zi/nucleo_f767zi_defconfig b/boards/st/nucleo_f767zi/nucleo_f767zi_defconfig index 261e47c2d53..2ccb0d375b5 100644 --- a/boards/st/nucleo_f767zi/nucleo_f767zi_defconfig +++ b/boards/st/nucleo_f767zi/nucleo_f767zi_defconfig @@ -15,9 +15,3 @@ CONFIG_UART_CONSOLE=y # Enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_g031k8/board.cmake b/boards/st/nucleo_g031k8/board.cmake index 8b8ec50a6b6..332fe061efd 100644 --- a/boards/st/nucleo_g031k8/board.cmake +++ b/boards/st/nucleo_g031k8/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32G031K8" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_g031k8/doc/index.rst b/boards/st/nucleo_g031k8/doc/index.rst index e140ac74040..c3776071ee2 100644 --- a/boards/st/nucleo_g031k8/doc/index.rst +++ b/boards/st/nucleo_g031k8/doc/index.rst @@ -110,6 +110,8 @@ For more details please refer to `STM32 Nucleo-32 board User Manual`_. Programming and Debugging ************************* +Nucleo G031K8 board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``nucleo_g031k8`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -117,8 +119,16 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo G031K8 board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to Nucleo G031K8 ---------------------------------------- @@ -136,7 +146,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -166,3 +176,6 @@ References .. _STM32 Nucleo-32 board User Manual: https://www.st.com/resource/en/user_manual/um2591-stm32g0-nucleo32-board-mb1455-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_g031k8/nucleo_g031k8_defconfig b/boards/st/nucleo_g031k8/nucleo_g031k8_defconfig index 06484e88bea..e91ac02cdda 100644 --- a/boards/st/nucleo_g031k8/nucleo_g031k8_defconfig +++ b/boards/st/nucleo_g031k8/nucleo_g031k8_defconfig @@ -14,9 +14,3 @@ CONFIG_UART_CONSOLE=y # GPIO Controller CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_g070rb/board.cmake b/boards/st/nucleo_g070rb/board.cmake index 3e31c30f8a8..e8ff9cd0ccb 100644 --- a/boards/st/nucleo_g070rb/board.cmake +++ b/boards/st/nucleo_g070rb/board.cmake @@ -1,11 +1,14 @@ # SPDX-License-Identifier: Apache-2.0 + +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(pyocd "--target=stm32g070rbtx") board_runner_args(pyocd "--flash-opt=-O reset_type=hw") board_runner_args(pyocd "--flash-opt=-O connect_mode=under-reset") board_runner_args(jlink "--device=STM32G070RB" "--speed=4000") -board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) diff --git a/boards/st/nucleo_g070rb/doc/index.rst b/boards/st/nucleo_g070rb/doc/index.rst index b18525ee0eb..87b8cef25af 100644 --- a/boards/st/nucleo_g070rb/doc/index.rst +++ b/boards/st/nucleo_g070rb/doc/index.rst @@ -143,6 +143,8 @@ For more details please refer to `STM32 Nucleo-64 board User Manual`_. Programming and Debugging ************************* +Nucleo G070RB board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``nucleo_g070rb`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -150,7 +152,17 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo G070RB board includes an ST-LINK/V2-1 embedded debug tool interface. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD, JLink, or pyOCD can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink + $ west flash --runner pyocd Flashing an application to Nucleo G070RB ---------------------------------------- @@ -168,7 +180,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -189,3 +201,6 @@ References .. _G070RB on www.st.com: https://www.st.com/en/microcontrollers/stm32g070rb.html + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_g070rb/nucleo_g070rb_defconfig b/boards/st/nucleo_g070rb/nucleo_g070rb_defconfig index 0055481a2e8..d1f404dc8ff 100644 --- a/boards/st/nucleo_g070rb/nucleo_g070rb_defconfig +++ b/boards/st/nucleo_g070rb/nucleo_g070rb_defconfig @@ -10,9 +10,3 @@ CONFIG_UART_CONSOLE=y # GPIO Controller CONFIG_GPIO=y - -# Enables clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_g071rb/board.cmake b/boards/st/nucleo_g071rb/board.cmake index 124a3aac9fe..14262985a8c 100644 --- a/boards/st/nucleo_g071rb/board.cmake +++ b/boards/st/nucleo_g071rb/board.cmake @@ -1,11 +1,14 @@ # SPDX-License-Identifier: Apache-2.0 + +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(pyocd "--target=stm32g071rbtx") board_runner_args(pyocd "--flash-opt=-O reset_type=hw") board_runner_args(pyocd "--flash-opt=-O connect_mode=under-reset") board_runner_args(jlink "--device=STM32G071RB" "--speed=4000") -board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) diff --git a/boards/st/nucleo_g071rb/doc/index.rst b/boards/st/nucleo_g071rb/doc/index.rst index 094666250f3..2202157b6cd 100644 --- a/boards/st/nucleo_g071rb/doc/index.rst +++ b/boards/st/nucleo_g071rb/doc/index.rst @@ -149,6 +149,8 @@ For more details please refer to `STM32 Nucleo-64 board User Manual`_. Programming and Debugging ************************* +Nucleo G071RB board includes an ST-LINK/V3 embedded debug tool interface. + Applications for the ``nucleo_g071rb`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -156,7 +158,17 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo G071RB board includes an ST-LINK/V3 embedded debug tool interface. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD, JLink, or pyOCD can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink + $ west flash --runner pyocd Flashing an application to Nucleo G071RB ---------------------------------------- @@ -174,7 +186,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -198,3 +210,6 @@ References .. _G071RB on www.st.com: https://www.st.com/en/microcontrollers/stm32g071rb.html + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_g071rb/nucleo_g071rb.dts b/boards/st/nucleo_g071rb/nucleo_g071rb.dts index ba832c389cc..9237cd779b0 100644 --- a/boards/st/nucleo_g071rb/nucleo_g071rb.dts +++ b/boards/st/nucleo_g071rb/nucleo_g071rb.dts @@ -94,6 +94,10 @@ clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>, <&rcc STM32_SRC_LSI RTC_SEL(2)>; status = "okay"; + + backup_regs { + status = "okay"; + }; }; &iwdg { diff --git a/boards/st/nucleo_g071rb/nucleo_g071rb_defconfig b/boards/st/nucleo_g071rb/nucleo_g071rb_defconfig index 0055481a2e8..d1f404dc8ff 100644 --- a/boards/st/nucleo_g071rb/nucleo_g071rb_defconfig +++ b/boards/st/nucleo_g071rb/nucleo_g071rb_defconfig @@ -10,9 +10,3 @@ CONFIG_UART_CONSOLE=y # GPIO Controller CONFIG_GPIO=y - -# Enables clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_g0b1re/board.cmake b/boards/st/nucleo_g0b1re/board.cmake index 142aeaaa3ae..40365ef6885 100644 --- a/boards/st/nucleo_g0b1re/board.cmake +++ b/boards/st/nucleo_g0b1re/board.cmake @@ -1,12 +1,14 @@ # SPDX-License-Identifier: Apache-2.0 -# keil.stm32g0xx_dfp.1.3.0.pack introduced stm32g0b series, but the target does -# not work with pyocd currently. -board_runner_args(pyocd "--target=stm32g071rbtx") + +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") + +board_runner_args(pyocd "--target=stm32g0b1retx") board_runner_args(pyocd "--flash-opt=-O reset_type=hw") board_runner_args(pyocd "--flash-opt=-O connect_mode=under-reset") board_runner_args(jlink "--device=STM32G0B1RE" "--speed=4000") -board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +# keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/st/nucleo_g0b1re/doc/index.rst b/boards/st/nucleo_g0b1re/doc/index.rst index b283d6d3d1f..3a32623a82e 100644 --- a/boards/st/nucleo_g0b1re/doc/index.rst +++ b/boards/st/nucleo_g0b1re/doc/index.rst @@ -147,6 +147,8 @@ For more details please refer to `STM32 Nucleo-64 board User Manual`_. Programming and Debugging ************************* +Nucleo G0B1RE board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``nucleo_g0b1re`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -154,21 +156,26 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo G0B1RE board includes an ST-LINK/V2-1 embedded debug tool interface. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. -This interface is not yet supported by the openocd version included in the Zephyr SDK. -But JLink, STM32CubeProgrammer and Pyocd interfaces are supported. -Pyocd support is currently limited: As the stm32g0b1 target causes issues, -the stm32g071 target is used. For STM32G0 support pyocd needs additional target -information, which can be installed by adding "pack" support with the -following pyocd command: +Alternatively, OpenOCD, JLink, or pyOCD can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink + $ west flash --runner pyocd + +For STM32G0 support pyocd needs additional target information, +which can be installed by adding "pack" support with the following pyocd command: .. code-block:: console $ pyocd pack --update $ pyocd pack --install stm32g0 - Flashing an application to Nucleo G0B1RE ---------------------------------------- @@ -185,7 +192,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -209,3 +216,6 @@ References .. _G0B1RE on www.st.com: https://www.st.com/en/microcontrollers/stm32g0b1re.html + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_g0b1re/nucleo_g0b1re.yaml b/boards/st/nucleo_g0b1re/nucleo_g0b1re.yaml index e2389efdbb7..f08da37e760 100644 --- a/boards/st/nucleo_g0b1re/nucleo_g0b1re.yaml +++ b/boards/st/nucleo_g0b1re/nucleo_g0b1re.yaml @@ -23,4 +23,5 @@ supported: - dma - usb_device - lptim + - usbd vendor: st diff --git a/boards/st/nucleo_g0b1re/nucleo_g0b1re_defconfig b/boards/st/nucleo_g0b1re/nucleo_g0b1re_defconfig index 84d7129fd51..d1f404dc8ff 100644 --- a/boards/st/nucleo_g0b1re/nucleo_g0b1re_defconfig +++ b/boards/st/nucleo_g0b1re/nucleo_g0b1re_defconfig @@ -10,9 +10,3 @@ CONFIG_UART_CONSOLE=y # GPIO Controller CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_g431rb/board.cmake b/boards/st/nucleo_g431rb/board.cmake index d23382841d3..7a680ee8d4b 100644 --- a/boards/st/nucleo_g431rb/board.cmake +++ b/boards/st/nucleo_g431rb/board.cmake @@ -1,5 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 + +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(pyocd "--target=stm32g431rbtx") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/st/nucleo_g431rb/doc/index.rst b/boards/st/nucleo_g431rb/doc/index.rst index 08d660a0c7d..62805c011cd 100644 --- a/boards/st/nucleo_g431rb/doc/index.rst +++ b/boards/st/nucleo_g431rb/doc/index.rst @@ -184,6 +184,8 @@ low power mode. Programming and Debugging ************************* +Nucleo G431RB board includes an ST-LINK/V3E embedded debug tool interface. + Applications for the ``nucleo_g431rb`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -191,27 +193,23 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo G431RB board includes an ST-LINK/V3E embedded debug tool interface. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. -This interface is not yet supported by the openocd version included in the Zephyr SDK. - -Instead, support can be enabled on pyocd by adding "pack" support with -the following pyocd command: +Alternatively, OpenOCD or pyOCD can also be used to flash the board using +the ``--runner`` (or ``-r``) option: .. code-block:: console - $ pyocd pack --update - $ pyocd pack --install stm32g431rb + $ west flash --runner openocd + $ west flash --runner pyocd -Note: -To manually enable the openocd interface, You can still update, compile and install -a 'local' openocd from the official openocd repo http://openocd.zylin.com . -Then run the following openocd command where the '/usr/local/bin/openocd'is your path -for the freshly installed openocd, given by "$ which openocd" : +pyOCD can be used after adding "pack" support with the following commands: .. code-block:: console - $ west flash --openocd /usr/local/bin/openocd + $ pyocd pack --update + $ pyocd pack --install stm32g431rb Flashing an application to Nucleo G431RB ---------------------------------------- @@ -224,7 +222,7 @@ then run a serial host program to connect with your Nucleo board. $ minicom -D /dev/ttyACM0 Now build and flash an application. Here is an example for -:ref:`hello_world`. +:zephyr:code-sample:`hello_world`. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -242,7 +240,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -261,3 +259,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32G4 reference manual: https://www.st.com/resource/en/reference_manual/dm00355726.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_g431rb/nucleo_g431rb.dts b/boards/st/nucleo_g431rb/nucleo_g431rb.dts index 8984d9d029d..894b5330aff 100644 --- a/boards/st/nucleo_g431rb/nucleo_g431rb.dts +++ b/boards/st/nucleo_g431rb/nucleo_g431rb.dts @@ -43,7 +43,7 @@ compatible = "gpio-keys"; user_button: button { label = "User"; - gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; + gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>; zephyr,code = ; }; }; diff --git a/boards/st/nucleo_g431rb/nucleo_g431rb_defconfig b/boards/st/nucleo_g431rb/nucleo_g431rb_defconfig index 5bd145ba76c..c574b2d1fcb 100644 --- a/boards/st/nucleo_g431rb/nucleo_g431rb_defconfig +++ b/boards/st/nucleo_g431rb/nucleo_g431rb_defconfig @@ -6,9 +6,6 @@ CONFIG_SERIAL=y # enable GPIO CONFIG_GPIO=y -# enable clocks -CONFIG_CLOCK_CONTROL=y - # Console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y @@ -18,6 +15,3 @@ CONFIG_ARM_MPU=y # Enable HW stack protection CONFIG_HW_STACK_PROTECTION=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_g474re/board.cmake b/boards/st/nucleo_g474re/board.cmake index b8f4ae4e6e8..3c3ffc9e7ff 100644 --- a/boards/st/nucleo_g474re/board.cmake +++ b/boards/st/nucleo_g474re/board.cmake @@ -1,8 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 -board_runner_args(pyocd "--target=stm32g474retx") +# keep first board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +board_runner_args(pyocd "--target=stm32g474retx") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) diff --git a/boards/st/nucleo_g474re/doc/index.rst b/boards/st/nucleo_g474re/doc/index.rst index d826ce37188..8ef04ed8fa1 100644 --- a/boards/st/nucleo_g474re/doc/index.rst +++ b/boards/st/nucleo_g474re/doc/index.rst @@ -198,6 +198,8 @@ low power mode. Programming and Debugging ************************* +Nucleo G474RE board includes an ST-LINK/V3E embedded debug tool interface. + Applications for the ``nucleo_g474re`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -205,7 +207,16 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo G474RE board includes an ST-LINK/V3E embedded debug tool interface. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or pyOCD can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner pyocd Flashing an application to Nucleo G474RE ---------------------------------------- @@ -218,7 +229,7 @@ then run a serial host program to connect with your Nucleo board. $ minicom -D /dev/ttyACM0 Now build and flash an application. Here is an example for -:ref:`hello_world`. +:zephyr:code-sample:`hello_world`. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -236,7 +247,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -255,3 +266,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32G4 reference manual: https://www.st.com/resource/en/reference_manual/dm00355726.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_g474re/nucleo_g474re_defconfig b/boards/st/nucleo_g474re/nucleo_g474re_defconfig index b22a31b2f20..c574b2d1fcb 100644 --- a/boards/st/nucleo_g474re/nucleo_g474re_defconfig +++ b/boards/st/nucleo_g474re/nucleo_g474re_defconfig @@ -6,9 +6,6 @@ CONFIG_SERIAL=y # enable GPIO CONFIG_GPIO=y -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - # Console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y @@ -18,6 +15,3 @@ CONFIG_ARM_MPU=y # Enable HW stack protection CONFIG_HW_STACK_PROTECTION=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_h503rb/Kconfig.nucleo_h503rb b/boards/st/nucleo_h503rb/Kconfig.nucleo_h503rb new file mode 100644 index 00000000000..7044105f7fb --- /dev/null +++ b/boards/st/nucleo_h503rb/Kconfig.nucleo_h503rb @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Arrow Electronics. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_H503RB + select SOC_STM32H503XX diff --git a/boards/st/nucleo_h503rb/arduino_r3_connector.dtsi b/boards/st/nucleo_h503rb/arduino_r3_connector.dtsi new file mode 100644 index 00000000000..6a25cd476c5 --- /dev/null +++ b/boards/st/nucleo_h503rb/arduino_r3_connector.dtsi @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2024 Arrow Electronics. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpioa 0 0>, /* A0 */ + <1 0 &gpioa 1 0>, /* A1 */ + <2 0 &gpioa 2 0>, /* A2 */ + <3 0 &gpiob 0 0>, /* A3 */ + <4 0 &gpioc 1 0>, /* A4 */ + <5 0 &gpioc 0 0>, /* A5 */ + <6 0 &gpiob 15 0>, /* D0 */ + <7 0 &gpiob 14 0>, /* D1 */ + <8 0 &gpioa 10 0>, /* D2 */ + <9 0 &gpiob 3 0>, /* D3 */ + <10 0 &gpiob 5 0>, /* D4 */ + <11 0 &gpiob 4 0>, /* D5 */ + <12 0 &gpiob 10 0>, /* D6 */ + <13 0 &gpioa 8 0>, /* D7 */ + <14 0 &gpioc 7 0>, /* D8 */ + <15 0 &gpioc 6 0>, /* D9 */ + <16 0 &gpioc 9 0>, /* D10 */ + <17 0 &gpioa 7 0>, /* D11 */ + <18 0 &gpioa 6 0>, /* D12 */ + <19 0 &gpioa 5 0>, /* D13 */ + <20 0 &gpiob 7 0>, /* D14 */ + <21 0 &gpiob 6 0>; /* D15 */ + }; +}; + +arduino_serial: &usart1 {}; +arduino_i2c: &i2c1 {}; +/* arduino_spi (SPI1) uses PA5, to which the user LED is connected */ diff --git a/boards/st/nucleo_h503rb/board.cmake b/boards/st/nucleo_h503rb/board.cmake new file mode 100644 index 00000000000..5ac7cb17f66 --- /dev/null +++ b/boards/st/nucleo_h503rb/board.cmake @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: Apache-2.0 + +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") + +board_runner_args(openocd "--tcl-port=6666") +board_runner_args(openocd --cmd-pre-init "gdb_report_data_abort enable") +board_runner_args(openocd "--no-halt") + +board_runner_args(pyocd "--target=stm32h503rbtx") + +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +# FIXME: official openocd runner not yet available. diff --git a/boards/st/nucleo_h503rb/board.yml b/boards/st/nucleo_h503rb/board.yml new file mode 100644 index 00000000000..bbf3662873b --- /dev/null +++ b/boards/st/nucleo_h503rb/board.yml @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Arrow Electronics. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: nucleo_h503rb + vendor: st + socs: + - name: stm32h503xx diff --git a/boards/st/nucleo_h503rb/doc/img/nucleo_h503rb.png b/boards/st/nucleo_h503rb/doc/img/nucleo_h503rb.png new file mode 100644 index 00000000000..31117ce0697 Binary files /dev/null and b/boards/st/nucleo_h503rb/doc/img/nucleo_h503rb.png differ diff --git a/boards/st/nucleo_h503rb/doc/index.rst b/boards/st/nucleo_h503rb/doc/index.rst new file mode 100644 index 00000000000..ed7133cb5b1 --- /dev/null +++ b/boards/st/nucleo_h503rb/doc/index.rst @@ -0,0 +1,296 @@ +.. _nucleo_h503rb_board: + +ST Nucleo H503RB +################ + +Overview +******** + +The Nucleo-H503RB board features an ARM |reg| Cortex |reg|-M33 core-based +STM32H503RBT6 microcontroller with a wide range of connectivity support and +configurations. +Here are some highlights of the Nucleo-H503RB board: + +- STM32H503RB microcontroller featuring 128 Kbytes of Flash memory and 32 Kbytes of + SRAM in LQFP64 package + +- Board connectors: + + - User USB Type-C |reg| + - MIPI10 for debugging (SWD/JTAG) + - Arduino |reg| Uno V3 connectivity (CN5, CN6, CN8, CN9) + - ST morpho extension connector (CN7, CN10) + +- Flexible board power supply: + + - ST-LINK USB VBUS + - user USB connector + - external sources + +- On-board ST-LINK/V3EC debugger/programmer: + + - mass storage + - Virtual COM port + - debug port + +- One user LED shared with ARDUINO |reg| Uno V3 +- Two push-buttons: USER and RESET +- 32.768 kHz crystal oscillator +- 24 MHz HSE crystal oscillator + +More information about the board can be found at the `NUCLEO_H503RB website`_. + +.. image:: img/nucleo_h503rb.png + :align: center + :alt: NUCLEO-H503RB + +Hardware +******** + +The STM32H503xx devices are a high-performance microcontrollers family +(STM32H5 series) based on the high-performance Arm |reg| Cortex |reg|-M33 32-bit +RISC core. They operate at a frequency of up to 250 MHz. + +- Core: Arm |reg| Cortex |reg|-M33 CPU with FPU, MPU, 375 DMIPS (Dhrystone 2.1), + and DSP instructions +- ART Accelerator + +- Memories + + - 128 Kbytes of embedded flash memory with ECC, two banks of read-while-write + - 2-Kbyte OTP (one-time programmable) + - 32-Kbyte SRAM with ECC + - 2 Kbytes of backup SRAM (available in the lowest power modes) + +- Clock management + + - Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI + - Two PLLs for system clock, USB, audio, and ADC + - External oscillators: 4 to 50 MHz HSE, 32.768 kHz LSE + +- Embedded regulator (LDO) +- Up to 49 fast I/Os (most 5 V tolerant), up to 9 I/Os with independent supply down to 1.08 V + +- Analog peripherals + + - 1x 12-bit ADC with up to 2.5 MSPS + - 1x 12-bit dual-channel DAC + - 1x ultra-low-power comparator + - 1x operational amplifier (7 MHz bandwidth) + +- 1x Digital temperature sensor + +- Up to 11 timers + - 4x 16-bit + - 1x 32-bit + - 2x 16-bit low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - 1x SysTick timer + - RTC with HW calendar, alarms and calibration + +- Up to 16x communication interfaces + + - Up to 2x I2Cs FM + interfaces (SMBus/PMBus |reg|) + - Up to 2x I3Cs shared with I2C + - Up to 3x USARTs (ISO7816 interface, LIN, IrDA, modem control) + - 1x LPUART + - Up to 3x SPIs including three muxed with full-duplex I2S + - Up to 3x additional SPI from 3x USART when configured in synchronous mode + - 1x FDCAN + - 1x USB 2.0 full-speed host and device + +- Two DMA controllers to offload the CPU + +- Security + + - HASH (SHA-1, SHA-2), HMAC + - True random generator + - 96-bit unique ID + - Active tamper + +- Development support: serial wire debug (SWD) and JTAG interfaces + +More information about STM32H533RE can be found here: + +- `STM32H503rb on www.st.com`_ +- `STM32H503 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_h503rb board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c bus | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ +| BKP SRAM | on-chip | Backup SRAM | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig and dts files: + + - :zephyr_file:`boards/st/nucleo_h503rb/nucleo_h503rb_defconfig` + - :zephyr_file:`boards/st/nucleo_h503rb/nucleo_h503rb.dts` + +Connections and IOs +=================== + +Nucleo-H503RB board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `STM32H5 Nucleo-64 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- USART1 TX/RX : PB14/PB15 (Arduino USART1) +- SPI1 SCK/MISO/MOSI/NSS: PA5/PA6/PA7/PC9 +- USART3 TX/RX : PA3/PA4 (VCP) +- USER_PB : PC13 +- User LED (green): PA5 + +System Clock +------------ + +Nucleo H533RE System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at +240 MHz, driven by an 24 MHz high-speed external clock. + +Serial Port +----------- + +Nucleo H533RE board has up to 3 U(S)ARTs. The Zephyr console output is assigned +to USART3. Default settings are 115200 8N1. + +Backup SRAM +----------- + +In order to test backup SRAM, you may want to disconnect VBAT from VDD_MCU. +You can do it by removing ``SB38`` jumper on the back side of the board. +VBAT can be provided via the left ST Morpho connector's pin 33. + +Programming and Debugging +************************* + +Nucleo-H503RB board includes an ST-LINK/V3EC embedded debug tool interface. +This probe allows to flash the board using various tools. + +Applications for the ``nucleo_h503rb`` board can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +OpenOCD Support +=============== + +For now, openocd support for stm32h5 is not available on upstream OpenOCD. +You can check `OpenOCD official Github mirror`_. +In order to use it though, you should clone from the cutomized +`STMicroelectronics OpenOCD Github`_ and compile it following usual README guidelines. +Once it is done, you can set the OPENOCD and OPENOCD_DEFAULT_PATH variables in +:zephyr_file:`boards/st/nucleo_h563zi/board.cmake` to point the build +to the paths of the OpenOCD binary and its scripts, before +including the common openocd.board.cmake file: + + .. code-block:: none + + set(OPENOCD "/src/openocd" CACHE FILEPATH "" FORCE) + set(OPENOCD_DEFAULT_PATH /tcl) + include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) + +Flashing +======== + +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpencOCD or pyOCD can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner pyocd + +For pyOCD, additional target information needs to be installed +which can be done by executing the following commands: + +.. code-block:: console + + $ pyocd pack --update + $ pyocd pack --install stm32h5 + +Flashing an application to Nucleo-H503RB +---------------------------------------- + +Connect the Nucleo-H503RB to your host computer using the USB port. +Then build and flash an application. Here is an example for the +:zephyr:code-sample:`hello_world` application. + +Run a serial host program to connect with your Nucleo board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash the application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_h503rb + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! nucleo_h503rb/stm32h503xx + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_h503rb + :goals: debug + +.. _NUCLEO_H503RB website: + https://www.st.com/en/evaluation-tools/nucleo-h503rb + +.. _STM32H5 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/um3121-stm32h5-nucleo64-board-mb1814-stmicroelectronics.pdf + +.. _STM32H503RB on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32h503rb + +.. _STM32H503 reference manual: + https://www.st.com/resource/en/reference_manual/rm0492-stm32h503-line-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html + +.. _OpenOCD official Github mirror: + https://github.com/openocd-org/openocd/ + +.. _STMicroelectronics OpenOCD Github: + https://github.com/STMicroelectronics/OpenOCD/tree/openocd-cubeide-r6 diff --git a/boards/st/nucleo_h503rb/nucleo_h503rb.dts b/boards/st/nucleo_h503rb/nucleo_h503rb.dts new file mode 100644 index 00000000000..46eb394c178 --- /dev/null +++ b/boards/st/nucleo_h503rb/nucleo_h503rb.dts @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2024 Arrow Electronics. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include "arduino_r3_connector.dtsi" +#include "st_morpho_connector.dtsi" +#include + + +/ { + model = "STMicroelectronics STM32H503RB-NUCLEO board"; + compatible = "st,stm32h503rb-nucleo"; + + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &usart3; + zephyr,shell-uart = &usart3; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + leds: leds { + compatible = "gpio-leds"; + green_led_2: led_2 { + gpios = <&gpioa 5 GPIO_ACTIVE_HIGH>; + label = "User LD2"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button: button { + label = "User"; + gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>; + zephyr,code = ; + }; + }; + + aliases { + led0 = &green_led_2; + sw0 = &user_button; + watchdog0 = &iwdg; + }; +}; + +&clk_csi { + status = "okay"; +}; + +&clk_hsi { + status = "okay"; +}; + +&clk_hsi48 { + status = "okay"; +}; + +&clk_hse { + clock-frequency = ; + status = "okay"; +}; + +&pll { + div-m = <2>; + mul-n = <40>; + div-p = <2>; + div-q = <2>; + div-r = <2>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <1>; + apb2-prescaler = <1>; + apb3-prescaler = <1>; +}; + +&usart1 { + pinctrl-0 = <&usart1_tx_pb14 &usart1_rx_pb15>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&usart3 { + pinctrl-0 = <&usart3_tx_pa4 &usart3_rx_pa3>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&iwdg { + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>; + pinctrl-names = "default"; + clock-frequency = ; + status = "okay"; +}; diff --git a/boards/st/nucleo_h503rb/nucleo_h503rb.yaml b/boards/st/nucleo_h503rb/nucleo_h503rb.yaml new file mode 100644 index 00000000000..355591f3b79 --- /dev/null +++ b/boards/st/nucleo_h503rb/nucleo_h503rb.yaml @@ -0,0 +1,17 @@ +identifier: nucleo_h503rb +name: ST Nucleo H503RB +type: mcu +arch: arm +toolchain: + - zephyr +ram: 32 +flash: 128 +supported: + - arduino_gpio + - arduino_serial + - backup_sram + - gpio + - uart + - i2c + - watchdog +vendor: st diff --git a/boards/st/nucleo_h503rb/nucleo_h503rb_defconfig b/boards/st/nucleo_h503rb/nucleo_h503rb_defconfig new file mode 100644 index 00000000000..752901da58d --- /dev/null +++ b/boards/st/nucleo_h503rb/nucleo_h503rb_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Arrow Electronics. +# SPDX-License-Identifier: Apache-2.0 + +# enable uart driver +CONFIG_SERIAL=y + +# console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# enable GPIO +CONFIG_GPIO=y diff --git a/boards/st/nucleo_h503rb/st_morpho_connector.dtsi b/boards/st/nucleo_h503rb/st_morpho_connector.dtsi new file mode 100644 index 00000000000..d1800fe0772 --- /dev/null +++ b/boards/st/nucleo_h503rb/st_morpho_connector.dtsi @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2024 Arrow Electronics. + * SPDX-License-Identifier: Apache-2.0 + */ + + #include + #include + +/ { + st_morpho_header: st-morpho-header { + compatible = "st-morpho-header"; + #gpio-cells = <2>; + gpio-map-mask = ; + gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>; + gpio-map = , + , + , + , + /* By default, PA13 and PA14 are used as SWD signals + * (SB40=ON, SB41=ON) + */ + , + , + , + , + , + , + , + /* STM32H503xx has no pin PF0 as described in manual (UM3121) */ + , + /* STM32H503xx has no pin PF1 as described in manual (UM3121) */ + , + , + , + , + , + , + + , + , + , + , + , + /* By default, connected to USB connector (SB13=ON, SB17=ON) */ + , + , + /* By default, connected to USB connector (SB13=ON, SB17=ON) */ + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; +}; diff --git a/boards/st/nucleo_h503rb/support/openocd.cfg b/boards/st/nucleo_h503rb/support/openocd.cfg new file mode 100644 index 00000000000..ad1f98828c2 --- /dev/null +++ b/boards/st/nucleo_h503rb/support/openocd.cfg @@ -0,0 +1,23 @@ +source [find interface/stlink-dap.cfg] + +source [find target/stm32h5x.cfg] + +transport select "dapdirect_swd" + +set CHIPNAME STM32H503RBTX +set BOARDNAME NUCLEO-STM32H503RB + +# Reset configuration +# use hardware reset, connect under reset +# connect_assert_srst needed if low power mode application running (WFI...) +reset_config srst_only srst_nogate connect_assert_srst +set CONNECT_UNDER_RESET 1 +set CORE_RESET 0 + +# Due to the use of connect_assert_srst, running gdb requires +# to reset halt just after openocd init. +rename init old_init +proc init {} { + old_init + reset halt +} diff --git a/boards/st/nucleo_h533re/Kconfig.nucleo_h533re b/boards/st/nucleo_h533re/Kconfig.nucleo_h533re new file mode 100644 index 00000000000..3d48952fb58 --- /dev/null +++ b/boards/st/nucleo_h533re/Kconfig.nucleo_h533re @@ -0,0 +1,5 @@ +# Copyright (c) 2024 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_H533RE + select SOC_STM32H533XX diff --git a/boards/st/nucleo_h533re/arduino_r3_connector.dtsi b/boards/st/nucleo_h533re/arduino_r3_connector.dtsi new file mode 100644 index 00000000000..15bb1aab0bf --- /dev/null +++ b/boards/st/nucleo_h533re/arduino_r3_connector.dtsi @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpioa 0 0>, /* A0 */ + <1 0 &gpioa 1 0>, /* A1 */ + <2 0 &gpiob 1 0>, /* A2 */ + <3 0 &gpiob 0 0>, /* A3 */ + <4 0 &gpioc 1 0>, /* A4 */ + <5 0 &gpioc 0 0>, /* A5 */ + <6 0 &gpiob 15 0>, /* D0 */ + <7 0 &gpiob 14 0>, /* D1 */ + <8 0 &gpioc 8 0>, /* D2 */ + <9 0 &gpiob 3 0>, /* D3 */ + <10 0 &gpiob 5 0>, /* D4 */ + <11 0 &gpiob 4 0>, /* D5 */ + <12 0 &gpiob 10 0>, /* D6 */ + <13 0 &gpioa 8 0>, /* D7 */ + <14 0 &gpioc 7 0>, /* D8 */ + <15 0 &gpioc 6 0>, /* D9 */ + <16 0 &gpioc 9 0>, /* D10 */ + <17 0 &gpioa 7 0>, /* D11 */ + <18 0 &gpioa 6 0>, /* D12 */ + <19 0 &gpioa 5 0>, /* D13 */ + <20 0 &gpiob 7 0>, /* D14 */ + <21 0 &gpiob 6 0>; /* D15 */ + }; +}; + +arduino_serial: &usart1 {}; diff --git a/boards/st/nucleo_h533re/board.cmake b/boards/st/nucleo_h533re/board.cmake new file mode 100644 index 00000000000..963b13b03b2 --- /dev/null +++ b/boards/st/nucleo_h533re/board.cmake @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: Apache-2.0 + +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") + +board_runner_args(pyocd "--target=stm32h533retx") + +board_runner_args(jlink "--device=STM32H533RE" "--reset-after-load") + +board_runner_args(openocd "--tcl-port=6666") +board_runner_args(openocd --cmd-pre-init "gdb_report_data_abort enable") +board_runner_args(openocd "--no-halt") + +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +# FIXME: official openocd runner not yet available. diff --git a/boards/st/nucleo_h533re/board.yml b/boards/st/nucleo_h533re/board.yml new file mode 100644 index 00000000000..4b633011b71 --- /dev/null +++ b/boards/st/nucleo_h533re/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_h533re + vendor: st + socs: + - name: stm32h533xx diff --git a/boards/st/nucleo_h533re/doc/img/nucleo_h533re.jpg b/boards/st/nucleo_h533re/doc/img/nucleo_h533re.jpg new file mode 100644 index 00000000000..aed4a9752f9 Binary files /dev/null and b/boards/st/nucleo_h533re/doc/img/nucleo_h533re.jpg differ diff --git a/boards/st/nucleo_h533re/doc/index.rst b/boards/st/nucleo_h533re/doc/index.rst new file mode 100644 index 00000000000..428f79b83c2 --- /dev/null +++ b/boards/st/nucleo_h533re/doc/index.rst @@ -0,0 +1,347 @@ +.. _nucleo_h533re_board: + +ST Nucleo H533RE +################ + +Overview +******** + +The Nucleo H533RE board is designed as an affordable development platform for +STMicroelectronics ARM |reg| Cortex |reg|-M33 core-based STM32H533RET6 +microcontroller with TrustZone |reg|. +Here are some highlights of the Nucleo H533RE board: + +- STM32H533RE microcontroller featuring 512 kbytes of Flash memory and 272 Kbytes of + SRAM in LQFP64 package + +- Board connectors: + + - USB Type-C |trade| Sink device FS + - ST Zio expansion connector including Arduino Uno V3 connectivity (CN5, CN6, CN8, CN9) + - ST morpho extension connector (CN7, CN10) + +- Flexible board power supply: + + - 5V_USB_STLK from ST-Link USB connector + - VIN (7 - 12V, 0.8) supplied via pin header CN6 pin 8 or CN7 pin 24 + - ESV on the ST morpho connector CN7 Pin 6 (5V, O.5A) + - VBUS_STLK from a USB charger via the ST-LINK USB connector + - VBUSC from the USB user connector (5V, 0.5A) + - 3V3_EXT supplied via a pin header CN6 pin 4 or CN7 pin 16 (3.3V, 1.3A) + +- On-board ST-LINK/V3EC debugger/programmer + + - mass storage + - Virtual COM port + - debug port + +- One user LED shared with ARDUINO |reg| Uno V3 +- Two push-buttons: USER and RESET +- 32.768 kHz crystal oscillator + +More information about the board can be found at the `NUCLEO_H533RE website`_. + +.. image:: img/nucleo_h533re.jpg + :align: center + :alt: NUCLEO H533RE + +Hardware +******** + +The STM32H533xx devices are high-performance microcontrollers from the STM32H5 +Series based on the high-performance Arm |reg| Cortex |reg|-M33 32-bit RISC core. +They operate at a frequency of up to 250 MHz. + +- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU. +- Performance benchmark: + + - 375 DMPIS/MHz (Dhrystone 2.1) + +- Security + + - Arm |reg| TrustZone |reg| with Armv8-M mainline security extension + - Up to eight configurable SAU regions + - TrustZone |reg| aware and securable peripherals + - Flexible life cycle scheme with secure debug authentication + - SESIP3 and PSA Level 3 certified assurance target + - Preconfigured immutable root of trust (ST-iROT) + - SFI (secure firmware installation) + - Root of trust thanks to unique boot entry and secure hide protection area (HDP) + - Secure data storage with hardware unique key (HUK) + - Secure firmware upgrade support with TF-M + - Two AES coprocessors including one with DPA resistance + - Public key accelerator, DPA resistant + - On-the-fly decryption of Octo-SPI external memories + - HASH hardware accelerator + - True random number generator, NIST SP800-90B compliant + - 96-bit unique ID + - Active tampers + +- Clock management: + + - 24 MHz crystal oscillator (HSE) + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 64 MHz (HSI) trimmable by software + - Internal low-power 32 kHz RC (LSI)( |plusminus| 5%) + - Internal 4 MHz oscillator (CSI), trimmable by software + - Internal 48 MHz (HSI48) with recovery system + - 3 PLLs for system clock, USB, audio, ADC + +- Power management + + - Embedded regulator (LDO) with three configurable range output to supply the digital circuitry + - Embedded SMPS step-down converter + +- RTC with HW calendar, alarms and calibration +- Up to 112 fast I/Os, most 5 V-tolerant, up to 10 I/Os with independent supply down to 1.08 V +- Up to 16 timers and 2 watchdogs + + - 8x 16-bit + - 2x 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input + - 2x 16-bit low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - 2x SysTick timer + +- Memories + + - Up to 512 Kbytes Flash, 2 banks read-while-write + - 1 Kbyte OTP (one-time programmable) + - 272 Kbytes of SRAM (80-Kbyte SRAM2 with ECC) + - 2 Kbytes of backup SRAM available in the lowest power modes + - Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, FRAM, NOR/NAND memories + - 1x OCTOSPI memory interface with on-the-fly decryption and support for serial PSRAM/NAND/NOR, Hyper RAM/Flash frame formats + - 1x SD/SDIO/MMC interfaces + +- Rich analog peripherals (independent supply) + + - 2x 12-bit ADC with up to 5 MSPS in 12-bit + - 1x 12-bit DAC with 2 channels + - 1x Digital temperature sensor + - Voltage reference buffer + +- 34x communication interfaces + + - 1x USB Type-C / USB power-delivery controller + - 1x USB 2.0 full-speed host and device (crystal-less) + - 3x I2C FM+ interfaces (SMBus/PMBus) + - 2x I3C interface + - 6x U(S)ARTS (ISO7816 interface, LIN, IrDA, modem control) + - 1x LP UART + - 4x SPIs including 3 muxed with full-duplex I2S + - 4x additional SPI from 4x USART when configured in Synchronous mode + - 2x FDCAN + - 1x SDMMC interface + - 2x 16 channel DMA controllers + - 1x 8- to 14- bit camera interface + - 1x HDMI-CEC + - 1x 16-bit parallel slave synchronous-interface + +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| + +More information about STM32H533RE can be found here: + +- `STM32H533re on www.st.com`_ +- `STM32H533 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_h533re board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | PWM | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | Real Time Clock | ++-----------+------------+-------------------------------------+ +| BKP SRAM | on-chip | Backup SRAM | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB full-speed host/device bus | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig and dts files: + +- Secure target: + + - :zephyr_file:`boards/st/nucleo_h533re/nucleo_h533re_defconfig` + - :zephyr_file:`boards/st/nucleo_h533re/nucleo_h533re.dts` + +Zephyr board options +==================== + +The STM32H533 is a SoC with Cortex-M33 architecture. Zephyr provides support +for building for Secure firmware. + +The BOARD options are summarized below: + ++----------------------+-----------------------------------------------+ +| BOARD | Description | ++======================+===============================================+ +| nucleo_h533re | For building Secure firmware | ++----------------------+-----------------------------------------------+ + +Connections and IOs +=================== + +Nucleo H533RE Board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `STM32H5 Nucleo-64 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- ADC1 channel 0 input: PA0 +- USART1 TX/RX : PB14/PB15 (Arduino USART1) +- SPI1 SCK/MISO/MOSI/NSS: PA5/PA6/PA7/PA4 +- UART2 TX/RX : PA2/PA3 (VCP) +- USER_PB : PC13 + +System Clock +------------ + +Nucleo H533RE System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at +240MHz, driven by an 24MHz high-speed external clock. + +Serial Port +----------- + +Nucleo H533RE board has up to 4 USARTs, 2 UARTs, and one LPUART. The Zephyr console output is assigned +to USART2. Default settings are 115200 8N1. + +Backup SRAM +----------- + +In order to test backup SRAM, you may want to disconnect VBAT from VDD_MCU. +You can do it by removing ``SB38`` jumper on the back side of the board. +VBAT can be provided via the left ST Morpho connector's pin 33. + +Programming and Debugging +************************* + +Nucleo H533RE board includes an ST-LINK/V3EC embedded debug tool interface. +This probe allows to flash the board using various tools. + +Applications for the ``nucleo_h533re`` board can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +OpenOCD Support +=============== + +For now, openocd support for stm32h5 is not available on upstream OpenOCD. +You can check `OpenOCD official Github mirror`_. +In order to use it though, you should clone from the cutomized +`STMicroelectronics OpenOCD Github`_ and compile it following usual README guidelines. +Once it is done, you can set the OPENOCD and OPENOCD_DEFAULT_PATH variables in +:zephyr_file:`boards/st/nucleo_h533re/board.cmake` to point the build +to the paths of the OpenOCD binary and its scripts, before +including the common openocd.board.cmake file: + + .. code-block:: none + + set(OPENOCD "/src/openocd" CACHE FILEPATH "" FORCE) + set(OPENOCD_DEFAULT_PATH /tcl) + include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) + +Flashing +======== + +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD, JLink, or pyOCD can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner pyocd + $ west flash --runner jlink + +For pyOCD, additional target information needs to be installed +which can be done by executing the following commands: + +.. code-block:: console + + $ pyocd pack --update + $ pyocd pack --install stm32h5 + +Flashing an application to Nucleo H533RE +---------------------------------------- + +Connect the Nucleo H533RE to your host computer using the USB port. +Then build and flash an application. Here is an example for the +:zephyr:code-sample:`hello_world` application. + +Run a serial host program to connect with your Nucleo board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash the application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_h533re + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! nucleo_h533re + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_h533re + :goals: debug + +.. _NUCLEO_H533RE website: + https://www.st.com/en/evaluation-tools/nucleo-h533re + +.. _STM32H5 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/um3121-stm32h5-nucleo64-board-mb1814-stmicroelectronics.pdf + +.. _STM32H533RE on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32h533re + +.. _STM32H533 reference manual: + https://www.st.com/resource/en/reference_manual/rm0481-stm32h533-stm32h563-stm32h573-and-stm32h562-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html + +.. _OpenOCD official Github mirror: + https://github.com/openocd-org/openocd/ + +.. _STMicroelectronics OpenOCD Github: + https://github.com/STMicroelectronics/OpenOCD/tree/openocd-cubeide-r6 diff --git a/boards/st/nucleo_h533re/nucleo_h533re.dts b/boards/st/nucleo_h533re/nucleo_h533re.dts new file mode 100644 index 00000000000..fdb245e4320 --- /dev/null +++ b/boards/st/nucleo_h533re/nucleo_h533re.dts @@ -0,0 +1,165 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include "arduino_r3_connector.dtsi" +#include "st_morpho_connector.dtsi" +#include + +/ { + model = "STMicroelectronics STM32H533RE-NUCLEO board"; + compatible = "st,stm32h533re-nucleo"; + + chosen { + zephyr,console = &usart2; + zephyr,shell-uart = &usart2; + zephyr,sram = &sram1; + zephyr,flash = &flash0; + }; + + leds: leds { + compatible = "gpio-leds"; + green_led_2: led_42 { + gpios = <&gpioa 5 GPIO_ACTIVE_LOW>; + label = "User LD2"; + }; + }; + + + pwmleds { + compatible = "pwm-leds"; + + green_pwm_led: green_pwm_led { + pwms = <&pwm3 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button: button { + label = "User"; + gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>; + zephyr,code = ; + }; + }; + + aliases { + led0 = &green_led_2; + pwm-led0 = &green_pwm_led; + sw0 = &user_button; + watchdog0 = &iwdg; + die-temp0 = &die_temp; + volt-sensor0 = &vref; + volt-sensor1 = &vbat; + }; +}; + +&clk_csi { + status = "okay"; +}; + +&clk_hsi { + status = "okay"; +}; + +&clk_hse { + clock-frequency = ; + status = "okay"; +}; + +&pll { + div-m = <2>; + mul-n = <40>; + div-p = <2>; + div-q = <2>; + div-r = <2>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <1>; + apb2-prescaler = <1>; + apb3-prescaler = <1>; +}; + +&usart1 { + pinctrl-0 = <&usart1_tx_pb14 &usart1_rx_pb15>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&usart2 { + pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&iwdg { + status = "okay"; +}; + +&timers3 { + st,prescaler = <1000>; + status = "okay"; + + pwm3: pwm { + pinctrl-0 = <&tim3_ch3_pb0>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&adc1 { + pinctrl-0 = <&adc1_inp0_pa0>; /* Arduino A0 */ + pinctrl-names = "default"; + st,adc-clock-source = ; + st,adc-prescaler = <8>; + status = "okay"; +}; + +&die_temp { + status = "okay"; +}; + +&vref { + status = "okay"; +}; + +&vbat { + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&clk_lse { + status = "okay"; +}; + +&rtc { + clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00200000>, + <&rcc STM32_SRC_LSE RTC_SEL(1)>; + status = "okay"; +}; + +&clk_hsi48 { + status = "okay"; +}; + +zephyr_udc0: &usb { + pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/st/nucleo_h533re/nucleo_h533re.yaml b/boards/st/nucleo_h533re/nucleo_h533re.yaml new file mode 100644 index 00000000000..6f675df5922 --- /dev/null +++ b/boards/st/nucleo_h533re/nucleo_h533re.yaml @@ -0,0 +1,21 @@ +# Copyright (c) 2024 +# SPDX-License-Identifier: Apache-2.0 + +identifier: nucleo_h533re +name: ST Nucleo H533RE +type: mcu +arch: arm +toolchain: + - zephyr +ram: 272 +flash: 512 +supported: + - gpio + - watchdog + - pwm + - rtc + - adc + - usb_device + - usb + - backup_sram +vendor: st diff --git a/boards/st/nucleo_h533re/nucleo_h533re_defconfig b/boards/st/nucleo_h533re/nucleo_h533re_defconfig new file mode 100644 index 00000000000..7da4b13427e --- /dev/null +++ b/boards/st/nucleo_h533re/nucleo_h533re_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +# enable uart driver +CONFIG_SERIAL=y + +# console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# enable GPIO +CONFIG_GPIO=y diff --git a/boards/st/nucleo_h533re/st_morpho_connector.dtsi b/boards/st/nucleo_h533re/st_morpho_connector.dtsi new file mode 100644 index 00000000000..ce3d7c84017 --- /dev/null +++ b/boards/st/nucleo_h533re/st_morpho_connector.dtsi @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + st_morpho_header: st-morpho-header { + compatible = "st-morpho-header"; + #gpio-cells = <2>; + gpio-map-mask = ; + gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>; + gpio-map = , + , + , + , + , /* SB40=ON, SB41=ON */ + , /* SB40=ON, SB41=ON */ + , + , + , + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , /* SB13=ON, SB17=ON */ + , + , /* SB13=ON, SB17=ON */ + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; +}; diff --git a/boards/st/nucleo_h533re/support/openocd.cfg b/boards/st/nucleo_h533re/support/openocd.cfg new file mode 100644 index 00000000000..58bdb604dcc --- /dev/null +++ b/boards/st/nucleo_h533re/support/openocd.cfg @@ -0,0 +1,23 @@ +source [find interface/stlink-dap.cfg] + +source [find target/stm32h5x.cfg] + +transport select "dapdirect_swd" + +set CHIPNAME STM32H533RETX +set BOARDNAME NUCLEO-STM32H533RE + +# Reset configuration +# use hardware reset, connect under reset +# connect_assert_srst needed if low power mode application running (WFI...) +reset_config srst_only srst_nogate connect_assert_srst +set CONNECT_UNDER_RESET 1 +set CORE_RESET 0 + +# Due to the use of connect_assert_srst, running gdb requires +# to reset halt just after openocd init. +rename init old_init +proc init {} { + old_init + reset halt +} diff --git a/boards/st/nucleo_h563zi/board.cmake b/boards/st/nucleo_h563zi/board.cmake index 8899e82de74..be01446199a 100644 --- a/boards/st/nucleo_h563zi/board.cmake +++ b/boards/st/nucleo_h563zi/board.cmake @@ -1,11 +1,19 @@ # SPDX-License-Identifier: Apache-2.0 -board_runner_args(stm32cubeprogrammer "--erase" "--port=swd" "--reset-mode=hw") +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(pyocd "--target=stm32h563zitx") board_runner_args(jlink "--device=STM32H563ZI" "--reset-after-load") +board_runner_args(openocd "--tcl-port=6666") +board_runner_args(openocd --cmd-pre-init "gdb_report_data_abort enable") +board_runner_args(openocd "--no-halt") + +# keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +#include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +# FIXME: official openocd runner not yet available. diff --git a/boards/st/nucleo_h563zi/doc/index.rst b/boards/st/nucleo_h563zi/doc/index.rst index e707e81fefa..8bbb099147e 100644 --- a/boards/st/nucleo_h563zi/doc/index.rst +++ b/boards/st/nucleo_h563zi/doc/index.rst @@ -150,6 +150,10 @@ The Zephyr nucleo_h563zi board configuration supports the following hardware fea +===========+============+=====================================+ | ADC | on-chip | ADC Controller | +-----------+------------+-------------------------------------+ +| BKP SRAM | on-chip | Backup SRAM | ++-----------+------------+-------------------------------------+ +| CAN/CANFD | on-chip | CAN | ++-----------+------------+-------------------------------------+ | CLOCK | on-chip | reset and clock control | +-----------+------------+-------------------------------------+ | DAC | on-chip | DAC Controller | @@ -216,6 +220,7 @@ Default Zephyr Peripheral Mapping: - ADC1 channel 3 input: PA6 - ADC1 channel 15 input: PA3 - DAC1 channel 2 output: PA5 +- CAN/CANFD TX/RX: PD1/PD0 - LD1 (green): PB0 - LD2 (yellow): PF4 - LD3 (red): PG4 @@ -237,27 +242,58 @@ Serial Port Nucleo H563ZI board has up to 12 U(S)ARTs. The Zephyr console output is assigned to USART3. Default settings are 115200 8N1. +Backup SRAM +----------- + +In order to test backup SRAM, you may want to disconnect VBAT from VDD_MCU. +You can do it by removing ``SB55`` jumper on the back side of the board. +VBAT can be provided via the left ST Morpho connector's pin 33. + Programming and Debugging ************************* +Nucleo H563ZI board includes an ST-LINK/V3EC embedded debug tool interface. +This probe allows to flash the board using various tools. + Applications for the ``nucleo_h563zi`` board can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). +OpenOCD Support +=============== + +For now, openocd support for stm32h5 is not available on upstream OpenOCD. +You can check `OpenOCD official Github mirror`_. +In order to use it though, you should clone from the cutomized +`STMicroelectronics OpenOCD Github`_ and compile it following usual README guidelines. +Once it is done, you can set the OPENOCD and OPENOCD_DEFAULT_PATH variables in +:zephyr_file:`boards/st/nucleo_h563zi/board.cmake` to point the build +to the paths of the OpenOCD binary and its scripts, before +including the common openocd.board.cmake file: + + .. code-block:: none + + set(OPENOCD "/src/openocd" CACHE FILEPATH "" FORCE) + set(OPENOCD_DEFAULT_PATH /tcl) + include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) + + Flashing ======== -Nucleo H563ZI board includes an ST-LINK/V3EC embedded debug tool interface. -This probe allows to flash the board using various tools. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. -Board is configured to be flashed using west STM32CubeProgrammer runner. -Installation of `STM32CubeProgrammer`_ is then required to flash the board. +Alternatively, OpenOCD, JLink, or pyOCD can also be used to flash the board using +the ``--runner`` (or ``-r``) option: -Alternatively, pyocd or jlink via an external probe can also be used to flash -and debug the board if west is told to use it as runner, which can be done by -passing either or ``-r pyocd``, or ``-r jlink``. +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner pyocd + $ west flash --runner jlink -For pyocd additional target information needs to be installed. +For pyOCD, additional target information needs to be installed. This can be done by executing the following commands. .. code-block:: console @@ -267,11 +303,11 @@ This can be done by executing the following commands. Flashing an application to Nucleo H563ZI ------------------------------------------- +---------------------------------------- Connect the Nucleo H563ZI to your host computer using the USB port. Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board: @@ -317,3 +353,9 @@ You can debug an application in the usual way. Here is an example for the .. _STM32CubeProgrammer: https://www.st.com/en/development-tools/stm32cubeprog.html + +.. _OpenOCD official Github mirror: + https://github.com/openocd-org/openocd/ + +.. _STMicroelectronics OpenOCD Github: + https://github.com/STMicroelectronics/OpenOCD/tree/openocd-cubeide-r6 diff --git a/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi b/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi index 4d375016208..030bab86a0c 100644 --- a/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi +++ b/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi @@ -66,7 +66,7 @@ div-m = <2>; mul-n = <120>; div-p = <2>; - div-q = <2>; + div-q = <3>; div-r = <2>; clocks = <&clk_hse>; status = "okay"; @@ -152,6 +152,15 @@ status = "okay"; }; +&fdcan1 { + pinctrl-0 = <&fdcan1_rx_pd0 &fdcan1_tx_pd1>; + pinctrl-names = "default"; + clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>, + <&rcc STM32_SRC_PLL1_Q FDCAN_SEL(1)>; + clk-divider = <2>; + status = "okay"; +}; + &flash0 { partitions { compatible = "fixed-partitions"; diff --git a/boards/st/nucleo_h563zi/nucleo_h563zi.dts b/boards/st/nucleo_h563zi/nucleo_h563zi.dts index 915a0ddee60..8acb70d0e6c 100644 --- a/boards/st/nucleo_h563zi/nucleo_h563zi.dts +++ b/boards/st/nucleo_h563zi/nucleo_h563zi.dts @@ -22,6 +22,7 @@ zephyr,sram = &sram1; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; + zephyr,canbus = &fdcan1; }; aliases { diff --git a/boards/st/nucleo_h563zi/nucleo_h563zi.yaml b/boards/st/nucleo_h563zi/nucleo_h563zi.yaml index 0130798df9d..a02dc2591a8 100644 --- a/boards/st/nucleo_h563zi/nucleo_h563zi.yaml +++ b/boards/st/nucleo_h563zi/nucleo_h563zi.yaml @@ -11,12 +11,15 @@ supported: - gpio - arduino_serial - arduino_spi + - backup_sram + - can - gpio - uart - entropy - adc - dac - pwm + - netif:eth - counter - spi - usb_device diff --git a/boards/st/nucleo_h563zi/nucleo_h563zi_defconfig b/boards/st/nucleo_h563zi/nucleo_h563zi_defconfig index d751abf075b..13e27a68657 100644 --- a/boards/st/nucleo_h563zi/nucleo_h563zi_defconfig +++ b/boards/st/nucleo_h563zi/nucleo_h563zi_defconfig @@ -7,9 +7,6 @@ CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y -# Enable clock -CONFIG_CLOCK_CONTROL=y - # Enable MPU CONFIG_ARM_MPU=y @@ -18,5 +15,3 @@ CONFIG_HW_STACK_PROTECTION=y # enable GPIO CONFIG_GPIO=y -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_h563zi/support/openocd.cfg b/boards/st/nucleo_h563zi/support/openocd.cfg new file mode 100644 index 00000000000..33aca4cc0c6 --- /dev/null +++ b/boards/st/nucleo_h563zi/support/openocd.cfg @@ -0,0 +1,23 @@ +source [find interface/stlink-dap.cfg] + +source [find target/stm32h5x.cfg] + +transport select "dapdirect_swd" + +set CHIPNAME STM32H563ZITX +set BOARDNAME NUCLEO-STM32H563ZI + +# Reset configuration +# use hardware reset, connect under reset +# connect_assert_srst needed if low power mode application running (WFI...) +reset_config srst_only srst_nogate connect_assert_srst +set CONNECT_UNDER_RESET 1 +set CORE_RESET 0 + +# Due to the use of connect_assert_srst, running gdb requires +# to reset halt just after openocd init. +rename init old_init +proc init {} { + old_init + reset halt +} diff --git a/boards/st/nucleo_h723zg/board.cmake b/boards/st/nucleo_h723zg/board.cmake index 745c70d780c..b9e6be6fda5 100644 --- a/boards/st/nucleo_h723zg/board.cmake +++ b/boards/st/nucleo_h723zg/board.cmake @@ -1,9 +1,11 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32H723ZG" "--speed=4000") board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) -board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) diff --git a/boards/st/nucleo_h723zg/doc/index.rst b/boards/st/nucleo_h723zg/doc/index.rst index 93574531dae..5e97327386d 100644 --- a/boards/st/nucleo_h723zg/doc/index.rst +++ b/boards/st/nucleo_h723zg/doc/index.rst @@ -117,6 +117,8 @@ features: +-------------+------------+-------------------------------------+ | RTC | on-chip | rtc | +-------------+------------+-------------------------------------+ +| FDCAN1 | on-chip | CAN-FD Controller | ++-------------+------------+-------------------------------------+ Other hardware features are not yet supported on this Zephyr port. @@ -138,6 +140,7 @@ and a ST morpho connector. Board is configured as follows: - LD3 : PB14 - I2C : PB8, PB9 - SPI1 NSS/SCK/MISO/MOSI : PD14PA5/PA6/PB5 (Arduino SPI) +- FDCAN1 RX/TX : PD0, PD1 System Clock ------------ @@ -158,31 +161,43 @@ Backup SRAM In order to test backup SRAM you may want to disconnect VBAT from VDD. You can do it by removing ``SB52`` jumper on the back side of the board. -Programming and Debugging -************************* +FDCAN +===== -Currently the ``nucleo_h723zg`` board supports stm32cubeprogrammer (default), OpenOCD and J-Link debuggers. +The Nucleo H723ZG board does not have any onboard CAN transceiver. In order to +use the FDCAN bus on this board, an external CAN bus transceiver must be +connected to pins PD0 (RX) and PD1 (TX). -.. note:: +Programming and Debugging +************************* - Official OpenOCD support for this board was added on October '20. - Make sure your openocd version is older than that. - Following links may be helpful: `OpenOCD installing Debug Version`_ - and `OpenOCD installing with ST-LINK V3 support`_ +Nucleo H723ZG board includes an ST-LINK/V3 embedded debug tool interface. .. note:: - Check if your ST-LINK V3 has newest FW version. It can be done with `STM32CubeIDE`_ + Check if your ST-LINK V3 has newest FW version. It can be done with `STM32CubeProgrammer`_ Flashing ======== -Nucleo H723ZG board includes an ST-LINK/V3 embedded debug tool interface. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink + +Flashing an application to Nucleo H723ZG +---------------------------------------- First, connect the NUCLEO-H723ZG to your host computer using the USB port to prepare it for flashing. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your NUCLEO-H723ZG board. @@ -220,7 +235,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -248,3 +263,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32CubeIDE: https://www.st.com/en/development-tools/stm32cubeide.html + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_h723zg/nucleo_h723zg.dts b/boards/st/nucleo_h723zg/nucleo_h723zg.dts index 8fdd4be9442..0626679941c 100644 --- a/boards/st/nucleo_h723zg/nucleo_h723zg.dts +++ b/boards/st/nucleo_h723zg/nucleo_h723zg.dts @@ -24,6 +24,7 @@ zephyr,dtcm = &dtcm; zephyr,sram = &sram0; zephyr,flash = &flash0; + zephyr,canbus = &fdcan1; }; leds: leds { @@ -97,6 +98,16 @@ status = "okay"; }; +&pll2 { + div-m = <1>; + mul-n = <10>; + div-p = <1>; + div-q = <1>; + div-r = <1>; + clocks = <&clk_hse>; + status = "okay"; +}; + &rcc { clocks = <&pll>; clock-frequency = ; @@ -190,3 +201,11 @@ zephyr_udc0: &usbotg_hs { &rng { status = "okay"; }; + +&fdcan1 { + pinctrl-0 = <&fdcan1_rx_pd0 &fdcan1_tx_pd1>; + pinctrl-names = "default"; + clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>, + <&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>; + status = "okay"; +}; diff --git a/boards/st/nucleo_h723zg/nucleo_h723zg.yaml b/boards/st/nucleo_h723zg/nucleo_h723zg.yaml index 698fb32a091..66161b5b9ff 100644 --- a/boards/st/nucleo_h723zg/nucleo_h723zg.yaml +++ b/boards/st/nucleo_h723zg/nucleo_h723zg.yaml @@ -22,4 +22,5 @@ supported: - backup_sram - usb_device - rtc + - can vendor: st diff --git a/boards/st/nucleo_h723zg/nucleo_h723zg_defconfig b/boards/st/nucleo_h723zg/nucleo_h723zg_defconfig index 96a37909f6b..2ccb0d375b5 100644 --- a/boards/st/nucleo_h723zg/nucleo_h723zg_defconfig +++ b/boards/st/nucleo_h723zg/nucleo_h723zg_defconfig @@ -15,9 +15,3 @@ CONFIG_UART_CONSOLE=y # Enable GPIO CONFIG_GPIO=y - -# Enable Clock -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_h743zi/board.cmake b/boards/st/nucleo_h743zi/board.cmake index 1f87d06951f..004ae3551ce 100644 --- a/boards/st/nucleo_h743zi/board.cmake +++ b/boards/st/nucleo_h743zi/board.cmake @@ -1,10 +1,14 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(openocd --cmd-post-verify "reset halt") board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) board_runner_args(jlink "--device=STM32H743ZI" "--speed=4000") -board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +board_runner_args(pyocd "--target=stm32h743zitx") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/st/nucleo_h743zi/doc/index.rst b/boards/st/nucleo_h743zi/doc/index.rst index 66e75e574bb..2a790927bfc 100644 --- a/boards/st/nucleo_h743zi/doc/index.rst +++ b/boards/st/nucleo_h743zi/doc/index.rst @@ -184,25 +184,31 @@ Requires an external CAN or CANFD transceiver. Programming and Debugging ************************* +Nucleo H743ZI board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``nucleo_h743zi`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). -.. note:: - - If using OpenOCD you will need a recent development version as the last - official release does not support H7 series yet. You can also choose the - ``stm32cubeprogrammer`` runner. - Flashing ======== -Nucleo H743ZI board includes an ST-LINK/V2-1 embedded debug tool interface. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD, JLink or pyOCD can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink + $ west flash --runner pyocd Flashing an application to Nucleo H743ZI ---------------------------------------- -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board. @@ -227,7 +233,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -246,3 +252,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32H743 reference manual: https://www.st.com/resource/en/reference_manual/dm00314099.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_h743zi/nucleo_h743zi.dts b/boards/st/nucleo_h743zi/nucleo_h743zi.dts index f410d6f956e..cc7122b5935 100644 --- a/boards/st/nucleo_h743zi/nucleo_h743zi.dts +++ b/boards/st/nucleo_h743zi/nucleo_h743zi.dts @@ -80,10 +80,20 @@ }; &pll { - div-m = <1>; - mul-n = <24>; + div-m = <2>; + mul-n = <240>; div-p = <2>; - div-q = <4>; + div-q = <2>; + div-r = <2>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&pll2 { + div-m = <4>; + mul-n = <120>; + div-p = <2>; + div-q = <3>; /* gives 80MHz to the FDCAN */ div-r = <2>; clocks = <&clk_hse>; status = "okay"; @@ -91,13 +101,13 @@ &rcc { clocks = <&pll>; - clock-frequency = ; + clock-frequency = ; d1cpre = <1>; - hpre = <1>; - d1ppre = <1>; - d2ppre1 = <1>; - d2ppre2 = <1>; - d3ppre = <1>; + hpre = <2>; + d1ppre = <2>; + d2ppre1 = <2>; + d2ppre2 = <2>; + d3ppre = <2>; }; &usart3 { @@ -171,7 +181,7 @@ zephyr_udc0: &usbotg_fs { pinctrl-0 = <&fdcan1_rx_pd0 &fdcan1_tx_pd1>; pinctrl-names = "default"; clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>, - <&rcc STM32_SRC_PLL1_Q FDCAN_SEL(1)>; + <&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>; status = "okay"; }; diff --git a/boards/st/nucleo_h743zi/nucleo_h743zi.yaml b/boards/st/nucleo_h743zi/nucleo_h743zi.yaml index b283964820a..8a315b337f5 100644 --- a/boards/st/nucleo_h743zi/nucleo_h743zi.yaml +++ b/boards/st/nucleo_h743zi/nucleo_h743zi.yaml @@ -26,4 +26,5 @@ supported: - dac - dma - rtc + - usbd vendor: st diff --git a/boards/st/nucleo_h743zi/nucleo_h743zi_defconfig b/boards/st/nucleo_h743zi/nucleo_h743zi_defconfig index 8dcaab60f61..2ccb0d375b5 100644 --- a/boards/st/nucleo_h743zi/nucleo_h743zi_defconfig +++ b/boards/st/nucleo_h743zi/nucleo_h743zi_defconfig @@ -15,9 +15,3 @@ CONFIG_UART_CONSOLE=y # Enable GPIO CONFIG_GPIO=y - -# Enable clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_h745zi_q/board.cmake b/boards/st/nucleo_h745zi_q/board.cmake index 677c748de35..716e0812e71 100644 --- a/boards/st/nucleo_h745zi_q/board.cmake +++ b/boards/st/nucleo_h745zi_q/board.cmake @@ -1,6 +1,8 @@ # SPDX-License-Identifier: Apache-2.0 # Copyright (c) 2020 Alexander Kozhinov +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32H745ZI" "--speed=4000") if(CONFIG_BOARD_NUCLEO_H745ZI_Q_STM32H745XX_M7) board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) @@ -8,5 +10,7 @@ elseif(CONFIG_BOARD_NUCLEO_H745ZI_Q_STM32H745XX_M4) board_runner_args(openocd --target-handle=_CHIPNAME.cpu1) endif() +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_h745zi_q/doc/index.rst b/boards/st/nucleo_h745zi_q/doc/index.rst index b1593b5e484..c0e5d3db722 100644 --- a/boards/st/nucleo_h745zi_q/doc/index.rst +++ b/boards/st/nucleo_h745zi_q/doc/index.rst @@ -117,6 +117,8 @@ features: +-------------+------------+-------------------------------------+ | USB OTG FS | on-chip | USB device | +-------------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-------------+------------+-------------------------------------+ Other hardware features are not yet supported on this Zephyr port. @@ -138,6 +140,7 @@ and a ST morpho connector. Board is configured as follows: - LD2 : PB7 - LD3 : PB14 - I2C : PB8, PB9 +- SPI : PA5, PA6, PB5, PD14 System Clock ------------ @@ -170,29 +173,38 @@ two cores. This is done in 3 ways: Programming and Debugging ************************* -Applications for the ``nucleo_h745zi_q`` board should be built per core target, -using either ``nucleo_h745zi_q_m7`` or ```nucleo_h745zi_q_m4`` as the target -(see :ref:`build_an_application` and :ref:`application_run` for more details). - -.. note:: +Nucleo H745ZI-Q board includes an ST-LINK/V3 embedded debug tool interface. - If using OpenOCD you will need a recent development version as the last - official release does not support H7 series and ST-LINK V3 yet. - Following links may be helpful: `OpenOCD installing Debug Version`_ - and `OpenOCD installing with ST-LINK V3 support`_ +Applications for the ``nucleo_h745zi_q`` board should be built per core target, +using either ``nucleo_h745zi_q/stm32h745xx/m7`` or ``nucleo_h745zi_q/stm32h745xx/m4`` +as the target (see :ref:`build_an_application` and :ref:`application_run` for more details). .. note:: - Check if your ST-LINK V3 has newest FW version. It can be done with `STM32CubeIDE`_ + Check if the board's ST-LINK V3 has the newest FW version. It can be updated + using `STM32CubeProgrammer`_. Flashing ======== -Nucleo H745ZI-Q board includes an ST-LINK/V3 embedded debug tool interface. - Flashing operation will depend on the target to be flashed and the SoC option bytes configuration. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner +for both cores, so its :ref:`installation ` is required. +The target core is detected automatically. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink + +It is advised to use `STM32CubeProgrammer`_ to check and update option bytes +configuration. + By default: - CPU0 (Cortex-M7) boot address is set to 0x80000000 (OB: BOOT_CM7_ADD0) @@ -208,7 +220,7 @@ Flashing an application to STM32H745ZI M7 Core First, connect the NUCLEO-H745ZI-Q to your host computer using the USB port to prepare it for flashing. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your NUCLEO-H745ZI-Q board. @@ -226,7 +238,7 @@ Build and flash the application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: nucleo_h745zi_q_m7 + :board: nucleo_h745zi_q/stm32h745xx/m7 :goals: build flash You should see the following message on the console: @@ -246,7 +258,7 @@ Here is an example for the :zephyr:code-sample:`blinky` application on M4 core. .. zephyr-app-commands:: :zephyr-app: samples/basic/blinky - :board: nucleo_h745zi_q_m4 + :board: nucleo_h745zi_q/stm32h745xx/m4 :goals: build flash .. note:: @@ -257,18 +269,17 @@ Here is an example for the :zephyr:code-sample:`blinky` application on M4 core. Debugging ========= -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +You can debug an application on Cortex M7 side in the usual way. Here is an example +for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: nucleo_h745zi_q_m7 + :board: nucleo_h745zi_q/stm32h745xx/m7 :maybe-skip-config: :goals: debug -Debugging with west is currently not available on Cortex M4 side. -In order to debug a Zephyr application on Cortex M4 side, you can use -`STM32CubeIDE`_. +Debugging a Zephyr application on Cortex M4 side with west is currently not available. +As a workaround, you can use `STM32CubeIDE`_. .. _Nucleo H745ZI-Q website: https://www.st.com/en/evaluation-tools/nucleo-h745zi-q.html @@ -290,3 +301,6 @@ In order to debug a Zephyr application on Cortex M4 side, you can use .. _STM32CubeIDE: https://www.st.com/en/development-tools/stm32cubeide.html + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4.dts b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4.dts index d4de60053ac..de94f2d0513 100644 --- a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4.dts +++ b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4.dts @@ -35,3 +35,10 @@ &rcc { clock-frequency = ; }; + +&spi1 { + pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pb5>; + pinctrl-names = "default"; + cs-gpios = <&gpiod 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + status = "okay"; +}; diff --git a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4.yaml b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4.yaml index 19c2a5a1f1c..b17c6d7963b 100644 --- a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4.yaml +++ b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4.yaml @@ -12,6 +12,7 @@ supported: - arduino_gpio - gpio - netif:eth + - spi testing: ignore_tags: - mpu diff --git a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4_defconfig b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4_defconfig index 2eb7224edab..7d56efa651b 100644 --- a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4_defconfig +++ b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4_defconfig @@ -4,9 +4,6 @@ # Enable GPIO CONFIG_GPIO=y -# Enable clock -CONFIG_CLOCK_CONTROL=y - # By default SERIAL peripherals are assigned to m7 # Enable uart driver @@ -15,6 +12,3 @@ CONFIG_CLOCK_CONTROL=y # Console #CONFIG_CONSOLE=y #CONFIG_UART_CONSOLE=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts index d3ed100f74a..a09d693b029 100644 --- a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts +++ b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts @@ -132,6 +132,13 @@ status = "okay"; }; +&spi1 { + pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pb5>; + pinctrl-names = "default"; + cs-gpios = <&gpiod 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + status = "okay"; +}; + zephyr_udc0: &usbotg_fs { pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; pinctrl-names = "default"; diff --git a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.yaml b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.yaml index 904e740e5ed..ff551e71837 100644 --- a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.yaml +++ b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.yaml @@ -17,6 +17,6 @@ supported: - i2c - pwm - netif:eth - - usb_cdc + - spi - usb_device vendor: st diff --git a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7_defconfig b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7_defconfig index a38b7cad80e..753f46510e3 100644 --- a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7_defconfig +++ b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7_defconfig @@ -19,9 +19,3 @@ CONFIG_UART_CONSOLE=y # Enable GPIO CONFIG_GPIO=y - -# Enable Clock -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_h753zi/board.cmake b/boards/st/nucleo_h753zi/board.cmake index b206f9921db..aa65b88b81a 100644 --- a/boards/st/nucleo_h753zi/board.cmake +++ b/boards/st/nucleo_h753zi/board.cmake @@ -1,9 +1,11 @@ # SPDX-License-Identifier: Apache-2.0 -board_runner_args(jlink "--device=STM32H753ZI" "--speed=4000") +# keep first board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +board_runner_args(jlink "--device=STM32H753ZI" "--speed=4000") board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) diff --git a/boards/st/nucleo_h753zi/doc/index.rst b/boards/st/nucleo_h753zi/doc/index.rst index 536d90d6310..e9af66a3232 100644 --- a/boards/st/nucleo_h753zi/doc/index.rst +++ b/boards/st/nucleo_h753zi/doc/index.rst @@ -169,25 +169,30 @@ Requires an external CAN or CANFD transceiver. Programming and Debugging ************************* +Nucleo H753ZI board includes an ST-LINK/V3 embedded debug tool interface. + Applications for the ``nucleo_h753zi`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). -.. note:: - - If using OpenOCD you will need a recent development version as the last - official release does not support H7 series yet. You can also choose the - ``stm32cubeprogrammer`` runner. - Flashing ======== -Nucleo H753ZI board includes an ST-LINK/V2-1 embedded debug tool interface. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to Nucleo H753ZI ---------------------------------------- -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board. @@ -212,7 +217,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -231,3 +236,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32H753 reference manual: https://www.st.com/resource/en/reference_manual/dm00314099.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_h753zi/nucleo_h753zi.dts b/boards/st/nucleo_h753zi/nucleo_h753zi.dts index e3b52c2b50c..d4217cfae58 100644 --- a/boards/st/nucleo_h753zi/nucleo_h753zi.dts +++ b/boards/st/nucleo_h753zi/nucleo_h753zi.dts @@ -77,10 +77,20 @@ }; &pll { - div-m = <1>; - mul-n = <24>; + div-m = <2>; + mul-n = <240>; div-p = <2>; - div-q = <4>; + div-q = <2>; + div-r = <2>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&pll2 { + div-m = <4>; + mul-n = <120>; + div-p = <2>; + div-q = <3>; /* gives 80MHz to the FDCAN */ div-r = <2>; clocks = <&clk_hse>; status = "okay"; @@ -88,13 +98,13 @@ &rcc { clocks = <&pll>; - clock-frequency = ; + clock-frequency = ; d1cpre = <1>; - hpre = <1>; - d1ppre = <1>; - d2ppre1 = <1>; - d2ppre2 = <1>; - d3ppre = <1>; + hpre = <2>; + d1ppre = <2>; + d2ppre1 = <2>; + d2ppre2 = <2>; + d3ppre = <2>; }; &usart3 { @@ -147,6 +157,8 @@ zephyr_udc0: &usbotg_fs { }; &fdcan1 { + clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>, + <&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>; pinctrl-0 = <&fdcan1_rx_pd0 &fdcan1_tx_pd1>; pinctrl-names = "default"; status = "okay"; @@ -230,7 +242,3 @@ zephyr_udc0: &usbotg_fs { }; }; - -&vbat { - status = "okay"; -}; diff --git a/boards/st/nucleo_h753zi/nucleo_h753zi_defconfig b/boards/st/nucleo_h753zi/nucleo_h753zi_defconfig index 8dcaab60f61..2ccb0d375b5 100644 --- a/boards/st/nucleo_h753zi/nucleo_h753zi_defconfig +++ b/boards/st/nucleo_h753zi/nucleo_h753zi_defconfig @@ -15,9 +15,3 @@ CONFIG_UART_CONSOLE=y # Enable GPIO CONFIG_GPIO=y - -# Enable clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_h755zi_q/Kconfig.defconfig b/boards/st/nucleo_h755zi_q/Kconfig.defconfig new file mode 100644 index 00000000000..2b0f2cac9a0 --- /dev/null +++ b/boards/st/nucleo_h755zi_q/Kconfig.defconfig @@ -0,0 +1,15 @@ +# STM32H755ZI Nucleo board configuration + +# Copyright (c) 2024 S&C Electric Company +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_H755ZI_Q + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_NUCLEO_H755ZI_Q diff --git a/boards/st/nucleo_h755zi_q/Kconfig.nucleo_h755zi_q b/boards/st/nucleo_h755zi_q/Kconfig.nucleo_h755zi_q new file mode 100644 index 00000000000..57d7263c6e1 --- /dev/null +++ b/boards/st/nucleo_h755zi_q/Kconfig.nucleo_h755zi_q @@ -0,0 +1,8 @@ +# STM32H755ZI Nucleo board configuration + +# Copyright (c) 2024 S&C Electric Company +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_H755ZI_Q + select SOC_STM32H755XX_M7 if BOARD_NUCLEO_H755ZI_Q_STM32H755XX_M7 + select SOC_STM32H755XX_M4 if BOARD_NUCLEO_H755ZI_Q_STM32H755XX_M4 diff --git a/boards/st/nucleo_h755zi_q/arduino_r3_connector.dtsi b/boards/st/nucleo_h755zi_q/arduino_r3_connector.dtsi new file mode 100644 index 00000000000..aaa4cec0583 --- /dev/null +++ b/boards/st/nucleo_h755zi_q/arduino_r3_connector.dtsi @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2024 S&C Electric Company + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpioa 3 0>, /* A0 */ + <1 0 &gpioc 0 0>, /* A1 */ + <2 0 &gpioc 3 0>, /* A2 */ + <3 0 &gpiob 1 0>, /* A3 */ + <4 0 &gpioc 2 0>, /* A4 */ + <5 0 &gpiof 11 0>, /* A5 */ + <6 0 &gpiob 7 0>, /* D0 */ + <7 0 &gpiob 6 0>, /* D1 */ + <8 0 &gpiog 14 0>, /* D2 */ + <9 0 &gpioe 13 0>, /* D3 */ + <10 0 &gpioe 14 0>, /* D4 */ + <11 0 &gpioe 11 0>, /* D5 */ + <12 0 &gpioa 8 0>, /* D6 */ + <13 0 &gpiog 12 0>, /* D7 */ + <14 0 &gpiog 9 0>, /* D8 */ + <15 0 &gpiod 15 0>, /* D9 */ + <16 0 &gpiod 14 0>, /* D10 */ + <17 0 &gpiob 5 0>, /* D11 */ + <18 0 &gpioa 6 0>, /* D12 */ + <19 0 &gpioa 5 0>, /* D13 */ + <20 0 &gpiob 9 0>, /* D14 */ + <21 0 &gpiob 8 0>; /* D15 */ + }; +}; + +arduino_i2c: &i2c1 {}; + +arduino_serial: &uart8 {}; diff --git a/boards/st/nucleo_h755zi_q/board.cmake b/boards/st/nucleo_h755zi_q/board.cmake new file mode 100644 index 00000000000..e703f23d147 --- /dev/null +++ b/boards/st/nucleo_h755zi_q/board.cmake @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: Apache-2.0 + +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +board_runner_args(jlink "--device=STM32H755ZI" "--speed=3300") +if(CONFIG_BOARD_NUCLEO_H755ZI_Q_STM32H755XX_M7) + board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) +elseif(CONFIG_BOARD_NUCLEO_H755ZI_Q_STM32H755XX_M4) + board_runner_args(openocd --target-handle=_CHIPNAME.cpu1) +endif() + +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_h755zi_q/board.yml b/boards/st/nucleo_h755zi_q/board.yml new file mode 100644 index 00000000000..ecffd3b0fd1 --- /dev/null +++ b/boards/st/nucleo_h755zi_q/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_h755zi_q + vendor: st + socs: + - name: stm32h755xx diff --git a/boards/st/nucleo_h755zi_q/doc/img/nucleo_h755zi_q.webp b/boards/st/nucleo_h755zi_q/doc/img/nucleo_h755zi_q.webp new file mode 100644 index 00000000000..4202c63585c Binary files /dev/null and b/boards/st/nucleo_h755zi_q/doc/img/nucleo_h755zi_q.webp differ diff --git a/boards/st/nucleo_h755zi_q/doc/index.rst b/boards/st/nucleo_h755zi_q/doc/index.rst new file mode 100644 index 00000000000..3d509cc90ba --- /dev/null +++ b/boards/st/nucleo_h755zi_q/doc/index.rst @@ -0,0 +1,295 @@ +.. _nucleo_h755zi_q_board: + +ST Nucleo H755ZI-Q +################### + +Overview +******** + +The NUCLEO-H755ZI-Q board, based on the MB1363 reference board, provides an affordable and +flexible way for users to try out new concepts and build prototypes on the STM32H755ZIT6 +microcontroller. + +The ST Zio connector, which extends the ARDUINO® Uno V3 connectivity, and +the ST morpho headers provide an easy means of expanding the functionality of the Nucleo +open development platform with a wide choice of specialized shields. +The NUCLEO-H755ZI-Q board does not require any separate probe as it integrates +the ST-LINK V3 debugger/programmer. + +Key Features + +- STM32H755ZIT6 microcontroller in LQFP144 package +- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support) +- USB OTG or full-speed device (depending on STM32 support) +- 3 user LEDs +- 2 user and reset push-buttons +- 32.768 kHz crystal oscillator +- Board connectors: + + - USB with Micro-AB + - Ethernet RJ45 (depending on STM32 support) + - SWDST Zio connector including Arduino* Uno V3ST + - ST morpho expansion + +- Flexible power-supply options: ST-LINK USB VBUS or external sources +- External or internal SMPS to generate Vcore logic supply +- On-board ST-LINK/V3 debugger/programmer with USB re-enumeration +- capability: mass storage, virtual COM port and debug port +- USB OTG full speed or device only + +.. image:: img/nucleo_h755zi_q.webp + :align: center + :alt: Nucleo H755ZI-Q + +More information about the board can be found at the `Nucleo H755ZI-Q website`_. + +Hardware +******** + +Nucleo H755ZI-Q provides the following hardware components: + +- STM32H755ZI in LQFP144 package +- ARM 32-bit Cortex-M7 CPU with FPU +- ARM 32-bit Cortex-M4 CPU with FPU +- Chrom-ART Accelerator +- Hardware JPEG Codec +- 480 MHz max CPU frequency +- VDD from 1.62 V to 3.6 V +- 2 MB Flash +- 1 MB SRAM +- High-resolution timer (2.1 ns) +- 32-bit timers(2) +- 16-bit timers(12) +- SPI(6) +- I2C(4) +- I2S (3) +- USART(4) +- UART(4) +- USB OTG Full Speed and High Speed(1) +- USB OTG Full Speed(1) +- CAN-FD(2) +- SAI(2) +- SPDIF_Rx(4) +- HDMI_CEC(1) +- Dual Mode Quad SPI(1) +- Camera Interface +- GPIO (up to 114) with external interrupt capability +- 16-bit ADC(3) with 36 channels / 3.6 MSPS +- 12-bit DAC with 2 channels(2) +- True Random Number Generator (RNG) +- 16-channel DMA +- LCD-TFT Controller with XGA resolution +- CRYPT and HASH peripherals + +Supported Features +================== + +The Zephyr nucleo_h755zi_q board configuration supports the following hardware +features: + ++-------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++=============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-------------+------------+-------------------------------------+ +| UART/USART | on-chip | serial port | ++-------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-------------+------------+-------------------------------------+ +| RTC | on-chip | counter | ++-------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-------------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-------------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-------------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-------------+------------+-------------------------------------+ +| USB OTG FS | on-chip | USB device | ++-------------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration per core can be found in the defconfig files: +:zephyr_file:`boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7_defconfig` and +:zephyr_file:`boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m4_defconfig` + +For mode details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The Nucleo H755ZI board features a ST Zio connector (extended Arduino Uno V3) +and a ST morpho connector. Board is configured as follows: + +- USART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) +- USER_PB : PC13 +- LD1 : PA5 +- LD2 : PE1 +- LD3 : PB14 +- I2C : PB8, PB9 + +System Clock +------------ + +Nucleo H755ZI-Q System Clock can be driven by an internal or external +oscillator, as well as the main PLL clock. By default, the System clock is +driven by the PLL clock at 480MHz, driven by an 8MHz high-speed external clock. + +Serial Port +----------- + +Nucleo H755ZI-Q board has 4 UARTs and 4 USARTs. The Zephyr console output is +assigned to USART3. Default settings are 115200 8N1. + +Resources sharing +----------------- + +The dual core nature of STM32H755 SoC requires sharing HW resources between the +two cores. This is done in 3 ways: + +- **Compilation**: Clock configuration is only accessible to M7 core. M4 core only + has access to bus clock activation and deactivation. +- **Static pre-compilation assignment**: Peripherals such as a UART are assigned in + devicetree before compilation. The user must ensure peripherals are not assigned + to both cores at the same time. +- **Run time protection**: Interrupt-controller and GPIO configurations could be + accessed by both cores at run time. Accesses are protected by a hardware semaphore + to avoid potential concurrent access issues. + +Programming and Debugging +************************* + +Nucleo H755ZI-Q board includes an ST-LINK/V3 embedded debug tool interface. + +Applications for the ``nucleo_h755zi_q`` board should be built per core target, +using either ``nucleo_h755zi_q/stm32h755xx/m7`` or ``nucleo_h755zi_q/stm32h755xx/m4`` +as the target (see :ref:`build_an_application` and :ref:`application_run` for more +details). + +.. note:: + + Check if the board's ST-LINK/V3 has the newest firmware version. It can be + updated with `STM32CubeProgrammer`_ + +Flashing +======== + +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner +for both cores, so its :ref:`installation ` is required. +The target core is detected automatically. + +It is advised to use `STM32CubeProgrammer`_ to check and update option bytes +configuration and flash ``nucleo_h755zi_q/stm32h755xx/m7`` and +``nucleo_h755zi_q/stm32h755xx/m4`` board targets. + +By default: + + - CPU0 (Cortex-M7) boot address is set to 0x08000000 (OB: BOOT_CM7_ADD0) + - CPU1 (Cortex-M4) boot address is set to 0x08100000 (OB: BOOT_CM4_ADD0) + +Also, default out of the box board configuration enables CM7 and CM4 boot when +board is powered (Option bytes BCM7 and BCM4 are checked). +In that configuration, Kconfig boot option ``STM32H7_BOOT_CM4_CM7`` should be selected. +Zephyr flash configuration has been set to meet these default settings. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink + +Flashing an application to STM32H755ZI M7 Core +---------------------------------------------- +First, connect the NUCLEO-H755ZI-Q to your host computer using +the USB port to prepare it for flashing. Then build and flash your application. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +Run a serial host program to connect with your NUCLEO-H755ZI-Q board. + +.. code-block:: console + + $ minicom -b 115200 -D /dev/ttyACM0 + +or use screen: + +.. code-block:: console + + $ screen /dev/ttyACM0 115200 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_h755zi_q/stm32h755xx/m7 + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! nucleo_h755zi_q/stm32h755xx/m7 + +.. note:: + Sometimes, flashing via OpenOCD does not work. It is necessary to erase the flash + (with STM32CubeProgrammer for example) to make it work again. + +Similarly, you can build and flash samples on the M4 target. For this, please +take care of the resource sharing (UART port used for console for instance). + +Here is an example for the :zephyr:code-sample:`blinky` application on M4 core. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_h755zi_q/stm32h755xx/m4 + :goals: build flash + +.. note:: + + Flashing both M4 and M7 and pushing RESTART button on the board leads + to LD1 and LD2 flashing simultaneously. + +Debugging +========= + +You can debug an application on the Cortex M7 core in the usual way. +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_h755zi_q/stm32h755xx/m7 + :maybe-skip-config: + :goals: debug + +Debugging a Zephyr application on Cortex M4 side with west is currently not +available. As a workaround, `STM32CubeIDE`_ can be used. + +.. _Nucleo H755ZI-Q website: + https://www.st.com/en/evaluation-tools/nucleo-h755zi-q.html + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/dm00499171-stm32h7-nucleo144-boards-mb1363-stmicroelectronics.pdf + +.. _STM32H755ZI on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32h755zi.html + +.. _STM32H755 reference manual: + https://www.st.com/resource/en/reference_manual/dm00176879-stm32h745755-and-stm32h747757-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _OpenOCD installing Debug Version: + https://github.com/zephyrproject-rtos/openocd + +.. _OpenOCD installing with ST-LINK V3 support: + https://mbd.kleier.net/integrating-st-link-v3.html + +.. _STM32CubeIDE: + https://www.st.com/en/development-tools/stm32cubeide.html + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_h755zi_q/nucleo_h755zi_q.dtsi b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q.dtsi new file mode 100644 index 00000000000..235b1f2e2aa --- /dev/null +++ b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q.dtsi @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2024 S&C Electric Company + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "arduino_r3_connector.dtsi" +#include + +/ { + leds: leds { + compatible = "gpio-leds"; + green_led: led_1 { + gpios = <&gpioa 5 GPIO_ACTIVE_HIGH>; + label = "User LD1"; + }; + yellow_led: led_2 { + gpios = <&gpioe 1 GPIO_ACTIVE_HIGH>; + label = "User LD2"; + }; + red_led: led_3 { + gpios = <&gpiob 14 GPIO_ACTIVE_HIGH>; + label = "User LD3"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button: button_0 { + gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>; + label = "User SB1"; + zephyr,code = ; + }; + }; +}; + +&rcc { + d1cpre = <1>; + hpre = <2>; + d1ppre = <2>; + d2ppre1 = <2>; + d2ppre2 = <2>; + d3ppre = <2>; +}; + +&mailbox { + status = "okay"; +}; diff --git a/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m4.dts b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m4.dts new file mode 100644 index 00000000000..71501daef00 --- /dev/null +++ b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m4.dts @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2024 S&C Electric Company + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "nucleo_h755zi_q.dtsi" + +/ { + model = "STMicroelectronics STM32H755ZI-Q-NUCLEO board"; + compatible = "st,stm32h755zi-q-nucleo"; + + /* HW resources belonging to CM4 */ + chosen { + zephyr,console = &uart8; + zephyr,shell-uart = &uart8; + zephyr,sram = &sram1; + zephyr,flash = &flash1; + }; + + aliases { + led0 = &yellow_led; + }; +}; + +&uart8 { + pinctrl-0 = <&uart8_tx_pe1 &uart8_rx_pe0>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&rcc { + clock-frequency = ; +}; diff --git a/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m4.yaml b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m4.yaml new file mode 100644 index 00000000000..b29de5b2c1b --- /dev/null +++ b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m4.yaml @@ -0,0 +1,18 @@ +identifier: nucleo_h755zi_q/stm32h755xx/m4 +name: ST Nucleo H755ZI-Q (M4) +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +ram: 288 +flash: 1024 +supported: + - arduino_gpio + - gpio + - netif:eth +testing: + ignore_tags: + - mpu + - nfc +vendor: st diff --git a/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m4_defconfig b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m4_defconfig new file mode 100644 index 00000000000..a964296bcae --- /dev/null +++ b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m4_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2024 S&C Electric Company + +# Enable GPIO +CONFIG_GPIO=y + +# By default SERIAL peripherals are assigned to m7 + +# Enable uart driver +#CONFIG_SERIAL=y + +# Console +#CONFIG_CONSOLE=y +#CONFIG_UART_CONSOLE=y diff --git a/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7.dts b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7.dts new file mode 100644 index 00000000000..d565297ebcb --- /dev/null +++ b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7.dts @@ -0,0 +1,139 @@ +/* + * Copyright (c) 2024 S&C Electric Company + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "nucleo_h755zi_q.dtsi" + +/* + * WARNING: + * Possible pin conflicts: The pins PA2 and PB13 may conflict on selection of + * ETH_STM32_HAL, since they are used in ST Zio or ST morpho connectors. To + * avoid conflicting states the jumpers JP6 and JP7 must be in ON state. + */ + +/ { + model = "STMicroelectronics STM32H755ZI-Q-NUCLEO board"; + compatible = "st,stm32h755zi-q-nucleo"; + + /* HW resources belonging to CM7 */ + chosen { + zephyr,console = &usart3; + zephyr,shell-uart = &usart3; + zephyr,dtcm = &dtcm; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + pwmleds { + compatible = "pwm-leds"; + + red_pwm_led: red_pwm_led { + pwms = <&pwm12 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "User LD3 - PWM12"; + }; + }; + + aliases { + led0 = &green_led; + pwm-led0 = &red_pwm_led; + sw0 = &user_button; + }; +}; + +&clk_lsi { + status = "okay"; +}; + +&clk_hsi48 { + status = "okay"; +}; + +&clk_hse { + hse-bypass; + clock-frequency = ; /* STLink 8MHz clock */ + status = "okay"; +}; + +&pll { + div-m = <1>; + mul-n = <120>; + div-p = <2>; + div-q = <8>; + div-r = <2>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; +}; + +&usart3 { + pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&rtc { + clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00010000>, + <&rcc STM32_SRC_LSI RTC_SEL(2)>; + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>; + pinctrl-names = "default"; + status = "okay"; + clock-frequency = ; +}; + +&timers12 { + st,prescaler = <10000>; + status = "okay"; + + pwm12: pwm { + status = "okay"; + pinctrl-0 = <&tim12_ch1_pb14>; + pinctrl-names = "default"; + }; +}; + +&mac { + status = "okay"; + pinctrl-0 = <ð_ref_clk_pa1 + ð_crs_dv_pa7 + ð_rxd0_pc4 + ð_rxd1_pc5 + ð_tx_en_pg11 + ð_txd0_pg13 + ð_txd1_pb13>; + pinctrl-names = "default"; +}; + +&mdio { + status = "okay"; + pinctrl-0 = <ð_mdio_pa2 ð_mdc_pc1>; + pinctrl-names = "default"; + + ethernet-phy@0 { + compatible = "ethernet-phy"; + reg = <0x00>; + status = "okay"; + }; +}; + +&rng { + status = "okay"; +}; + +zephyr_udc0: &usbotg_fs { + pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7.yaml b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7.yaml new file mode 100644 index 00000000000..63739dff138 --- /dev/null +++ b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7.yaml @@ -0,0 +1,20 @@ +identifier: nucleo_h755zi_q/stm32h755xx/m7 +name: ST Nucleo H755ZI-Q (M7) +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +ram: 512 +flash: 1024 +supported: + - arduino_gpio + - arduino_i2c + - uart + - gpio + - counter + - i2c + - pwm + - netif:eth + - usb_device +vendor: st diff --git a/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7_defconfig b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7_defconfig new file mode 100644 index 00000000000..49583b39167 --- /dev/null +++ b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7_defconfig @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2024 S&C Electric Company + +# Enable the internal SMPS regulator +CONFIG_POWER_SUPPLY_DIRECT_SMPS=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable UART (disable to assign to M4 core) +CONFIG_SERIAL=y + +# Console (disable to assign to M4 core) +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y diff --git a/boards/st/nucleo_h755zi_q/support/openocd.cfg b/boards/st/nucleo_h755zi_q/support/openocd.cfg new file mode 100644 index 00000000000..719125ff149 --- /dev/null +++ b/boards/st/nucleo_h755zi_q/support/openocd.cfg @@ -0,0 +1,30 @@ +# STM32H745ZI Nucleo board OpenOCD ST-LINK V3 configuration +# +# Copyright (c) 2024 S&C Electric Company +# SPDX-License-Identifier: Apache-2.0 +# + +# Borrow the nucleo_h745zi openocd configuration as no config exists for the h755 yet. +source [find board/st_nucleo_h745zi.cfg] + +# Use connect_assert_srst here to be able to program +# even when core is in sleep mode +reset_config srst_only srst_nogate connect_assert_srst + +$_CHIPNAME.cpu0 configure -event gdb-attach { + echo "Debugger attaching: halting execution" + gdb_breakpoint_override hard +} + +$_CHIPNAME.cpu0 configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} + +# Due to the use of connect_assert_srst, running gdb requires +# to reset halt just after openocd init. +rename init old_init +proc init {} { + old_init + reset halt +} diff --git a/boards/st/nucleo_h7a3zi_q/Kconfig.defconfig b/boards/st/nucleo_h7a3zi_q/Kconfig.defconfig deleted file mode 100644 index e8fd3484ea7..00000000000 --- a/boards/st/nucleo_h7a3zi_q/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# STM32H7A3ZI-Q Nucleo board configuration - -# Copyright (c) 2021 Electrolance Solutions -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_H7A3ZI_Q - -config USB_DC_HAS_HS_SUPPORT - default y - depends on USB_DC_STM32 - -endif # BOARD_NUCLEO_H7A3ZI_Q diff --git a/boards/st/nucleo_h7a3zi_q/board.cmake b/boards/st/nucleo_h7a3zi_q/board.cmake index cdd8c0a0b5f..e0cb9e0aac8 100644 --- a/boards/st/nucleo_h7a3zi_q/board.cmake +++ b/boards/st/nucleo_h7a3zi_q/board.cmake @@ -1,9 +1,11 @@ # SPDX-License-Identifier: Apache-2.0 -board_runner_args(jlink "--device=STM32H7A3ZI" "--speed=4000") +# keep first board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +board_runner_args(jlink "--device=STM32H7A3ZI" "--speed=4000") board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) diff --git a/boards/st/nucleo_h7a3zi_q/doc/index.rst b/boards/st/nucleo_h7a3zi_q/doc/index.rst index 484c7e82196..0de0ef109eb 100644 --- a/boards/st/nucleo_h7a3zi_q/doc/index.rst +++ b/boards/st/nucleo_h7a3zi_q/doc/index.rst @@ -148,6 +148,8 @@ assigned to USART3. Default settings are 115200 8N1. Programming and Debugging ************************* +Nucleo H7A3ZI-Q board includes an ST-LINK/V3E embedded debug tool interface. + Applications for the ``nucleo_h7a3zi_q`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -155,12 +157,21 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo H7A3ZI-Q board includes an ST-LINK/V3E embedded debug tool interface. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to Nucleo H7A3ZI-Q ------------------------------------------ -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board. @@ -185,7 +196,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -204,3 +215,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32H7A3ZI-Q reference manual: https://www.st.com/resource/en/reference_manual/rm0455-stm32h7a37b3-and-stm32h7b0-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_h7a3zi_q/nucleo_h7a3zi_q_defconfig b/boards/st/nucleo_h7a3zi_q/nucleo_h7a3zi_q_defconfig index 5490e9f1fc7..aa1632adccc 100644 --- a/boards/st/nucleo_h7a3zi_q/nucleo_h7a3zi_q_defconfig +++ b/boards/st/nucleo_h7a3zi_q/nucleo_h7a3zi_q_defconfig @@ -14,14 +14,8 @@ CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y -# Enable Pinctrl -CONFIG_PINCTRL=y - # Enable GPIO CONFIG_GPIO=y -# Enable clocks -CONFIG_CLOCK_CONTROL=y - # Enable SMPS CONFIG_POWER_SUPPLY_DIRECT_SMPS=y diff --git a/boards/st/nucleo_l011k4/board.cmake b/boards/st/nucleo_l011k4/board.cmake index 7c88105a59a..ed2af84d31e 100644 --- a/boards/st/nucleo_l011k4/board.cmake +++ b/boards/st/nucleo_l011k4/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32L011K4" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_l011k4/doc/index.rst b/boards/st/nucleo_l011k4/doc/index.rst index 7344ed734ad..b1d9396f7ed 100644 --- a/boards/st/nucleo_l011k4/doc/index.rst +++ b/boards/st/nucleo_l011k4/doc/index.rst @@ -118,6 +118,8 @@ For more details please refer to `STM32 Nucleo-32 board User Manual`_. Programming and Debugging ************************* +Nucleo L011K4 board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``nucleo_l011k4`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -125,8 +127,16 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo L011K4 board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to Nucleo L011K4 ---------------------------------------- @@ -144,7 +154,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -165,3 +175,6 @@ References .. _STM32 Nucleo-32 board User Manual: https://www.st.com/resource/en/user_manual/dm00231744-stm32-nucleo32-boards-mb1180-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_l011k4/nucleo_l011k4_defconfig b/boards/st/nucleo_l011k4/nucleo_l011k4_defconfig index 255389258c4..026b05cc7f8 100644 --- a/boards/st/nucleo_l011k4/nucleo_l011k4_defconfig +++ b/boards/st/nucleo_l011k4/nucleo_l011k4_defconfig @@ -14,9 +14,3 @@ CONFIG_UART_CONSOLE=y # GPIO Controller CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_l031k6/board.cmake b/boards/st/nucleo_l031k6/board.cmake index 7451e6df477..90c28655ceb 100644 --- a/boards/st/nucleo_l031k6/board.cmake +++ b/boards/st/nucleo_l031k6/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32L031K6" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_l031k6/doc/index.rst b/boards/st/nucleo_l031k6/doc/index.rst index 543d0cc01f8..0845a046fc0 100644 --- a/boards/st/nucleo_l031k6/doc/index.rst +++ b/boards/st/nucleo_l031k6/doc/index.rst @@ -111,6 +111,8 @@ For more details please refer to `STM32 Nucleo-32 board User Manual`_. Programming and Debugging ************************* +Nucleo L031K6 board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``nucleo_l031k6`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -118,8 +120,16 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo L031K6 board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to Nucleo L031K6 ---------------------------------------- @@ -137,7 +147,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -158,3 +168,6 @@ References .. _STM32 Nucleo-32 board User Manual: https://www.st.com/resource/en/user_manual/dm00231744-stm32-nucleo32-boards-mb1180-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_l031k6/nucleo_l031k6_defconfig b/boards/st/nucleo_l031k6/nucleo_l031k6_defconfig index 06484e88bea..e91ac02cdda 100644 --- a/boards/st/nucleo_l031k6/nucleo_l031k6_defconfig +++ b/boards/st/nucleo_l031k6/nucleo_l031k6_defconfig @@ -14,9 +14,3 @@ CONFIG_UART_CONSOLE=y # GPIO Controller CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_l053r8/board.cmake b/boards/st/nucleo_l053r8/board.cmake index 8f7ea297484..f6b83f83876 100644 --- a/boards/st/nucleo_l053r8/board.cmake +++ b/boards/st/nucleo_l053r8/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32L053R8" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_l053r8/doc/index.rst b/boards/st/nucleo_l053r8/doc/index.rst index e8fdac96751..4fd63f57f43 100644 --- a/boards/st/nucleo_l053r8/doc/index.rst +++ b/boards/st/nucleo_l053r8/doc/index.rst @@ -127,6 +127,8 @@ For more details please refer to `STM32 Nucleo-64 board User Manual`_. Programming and Debugging ************************* +Nucleo L053R8 board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``nucleo_l053r8`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -134,8 +136,16 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo L053R8 board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to Nucleo L053R8 ---------------------------------------- @@ -153,7 +163,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -174,3 +184,6 @@ References .. _STM32 Nucleo-64 board User Manual: https://www.st.com/resource/en/user_manual/dm00105823.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_l053r8/nucleo_l053r8_defconfig b/boards/st/nucleo_l053r8/nucleo_l053r8_defconfig index 7742224e030..634c2f45edf 100644 --- a/boards/st/nucleo_l053r8/nucleo_l053r8_defconfig +++ b/boards/st/nucleo_l053r8/nucleo_l053r8_defconfig @@ -17,9 +17,3 @@ CONFIG_UART_CONSOLE=y # GPIO Controller CONFIG_GPIO=y - -# Clock controller -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_l073rz/board.cmake b/boards/st/nucleo_l073rz/board.cmake index 5e307c7a541..bd12f7d933b 100644 --- a/boards/st/nucleo_l073rz/board.cmake +++ b/boards/st/nucleo_l073rz/board.cmake @@ -1,9 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 -board_runner_args(jlink "--device=STM32L073RZ" "--speed=4000") +# keep first board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +board_runner_args(jlink "--device=STM32L073RZ" "--speed=4000") - -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +# keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_l073rz/doc/index.rst b/boards/st/nucleo_l073rz/doc/index.rst index 991a3710d08..6ea4076a98a 100644 --- a/boards/st/nucleo_l073rz/doc/index.rst +++ b/boards/st/nucleo_l073rz/doc/index.rst @@ -143,6 +143,8 @@ For more details please refer to `STM32 Nucleo-64 board User Manual`_. Programming and Debugging ************************* +Nucleo L073RZ board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``nucleo_l073rz`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -150,8 +152,16 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo L073RZ board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to Nucleo L073RZ ---------------------------------------- @@ -169,7 +179,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -190,3 +200,6 @@ References .. _STM32 Nucleo-64 board User Manual: https://www.st.com/resource/en/user_manual/dm00105823.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_l073rz/nucleo_l073rz_defconfig b/boards/st/nucleo_l073rz/nucleo_l073rz_defconfig index f877d5b620a..f23dd0a9d83 100644 --- a/boards/st/nucleo_l073rz/nucleo_l073rz_defconfig +++ b/boards/st/nucleo_l073rz/nucleo_l073rz_defconfig @@ -12,9 +12,3 @@ CONFIG_UART_CONSOLE=y # GPIO Controller CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_l152re/board.cmake b/boards/st/nucleo_l152re/board.cmake index cbeaea2e456..716846e4923 100644 --- a/boards/st/nucleo_l152re/board.cmake +++ b/boards/st/nucleo_l152re/board.cmake @@ -1,3 +1,8 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") + +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/st/nucleo_l152re/doc/index.rst b/boards/st/nucleo_l152re/doc/index.rst index e0e92e5c168..c4d18190a23 100644 --- a/boards/st/nucleo_l152re/doc/index.rst +++ b/boards/st/nucleo_l152re/doc/index.rst @@ -137,6 +137,8 @@ For more details please refer to `STM32 Nucleo-64 board User Manual`_. Programming and Debugging ************************* +Nucleo L152RE board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``nucleo_l152re`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -144,8 +146,15 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo L152RE board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, openocd can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd Flashing an application to Nucleo L152RE ---------------------------------------- @@ -163,7 +172,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -187,3 +196,6 @@ References .. _STM32 Nucleo-64 board User Manual: https://www.st.com/resource/en/user_manual/dm00105823.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_l152re/nucleo_l152re_defconfig b/boards/st/nucleo_l152re/nucleo_l152re_defconfig index 02fb0a26c54..7496e1464eb 100644 --- a/boards/st/nucleo_l152re/nucleo_l152re_defconfig +++ b/boards/st/nucleo_l152re/nucleo_l152re_defconfig @@ -14,9 +14,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_l412rb_p/board.cmake b/boards/st/nucleo_l412rb_p/board.cmake index 5b1319aadc4..0ee007da3c5 100644 --- a/boards/st/nucleo_l412rb_p/board.cmake +++ b/boards/st/nucleo_l412rb_p/board.cmake @@ -1,7 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32L412RB" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) - diff --git a/boards/st/nucleo_l412rb_p/doc/index.rst b/boards/st/nucleo_l412rb_p/doc/index.rst index b423f06c174..11a12390782 100644 --- a/boards/st/nucleo_l412rb_p/doc/index.rst +++ b/boards/st/nucleo_l412rb_p/doc/index.rst @@ -208,6 +208,8 @@ Default settings are 115200 8N1. Programming and Debugging ************************* +Nucleo L412RB-P board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``nucleo_l412rb_p`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -215,9 +217,16 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo L412RB-P board includes an ST-LINK/V2-1 embedded debug tool -interface. This interface is supported by the openocd version -included in the Zephyr SDK since v0.9.2. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to Nucleo L412RB-P ------------------------------------------ @@ -230,7 +239,7 @@ then run a serial host program to connect with your Nucleo board. $ minicom -D /dev/ttyACM0 Now build and flash an application. Here is an example for -:ref:`hello_world`. +:zephyr:code-sample:`hello_world`. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -248,7 +257,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -267,3 +276,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32L412 reference manual: https://www.st.com/resource/en/reference_manual/dm00151940-stm32l41xxx42xxx43xxx44xxx45xxx46xxx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_l412rb_p/nucleo_l412rb_p_defconfig b/boards/st/nucleo_l412rb_p/nucleo_l412rb_p_defconfig index 349e958591e..32e9f21e000 100644 --- a/boards/st/nucleo_l412rb_p/nucleo_l412rb_p_defconfig +++ b/boards/st/nucleo_l412rb_p/nucleo_l412rb_p_defconfig @@ -15,9 +15,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_l432kc/board.cmake b/boards/st/nucleo_l432kc/board.cmake index f87a4b505b0..20c7aec7e06 100644 --- a/boards/st/nucleo_l432kc/board.cmake +++ b/boards/st/nucleo_l432kc/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32L432KC" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_l432kc/doc/index.rst b/boards/st/nucleo_l432kc/doc/index.rst index ddbfaec6a80..f312380a07c 100644 --- a/boards/st/nucleo_l432kc/doc/index.rst +++ b/boards/st/nucleo_l432kc/doc/index.rst @@ -168,6 +168,8 @@ Default settings are 115200 8N1. Programming and Debugging ************************* +Nucleo L432KC board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``nucleo_l432kc`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -175,9 +177,16 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo L432KC board includes an ST-LINK/V2-1 embedded debug tool -interface. This interface is supported by the openocd version -included in the Zephyr SDK since v0.9.2. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to Nucleo L432KC ---------------------------------------- @@ -190,7 +199,7 @@ then run a serial host program to connect with your Nucleo board. $ minicom -D /dev/ttyACM0 Now build and flash an application. Here is an example for -:ref:`hello_world`. +:zephyr:code-sample:`hello_world`. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -208,7 +217,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -227,3 +236,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32L432 reference manual: https://www.st.com/resource/en/reference_manual/dm00151940.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_l432kc/nucleo_l432kc_defconfig b/boards/st/nucleo_l432kc/nucleo_l432kc_defconfig index 82ee7285d52..3fe5e4f9882 100644 --- a/boards/st/nucleo_l432kc/nucleo_l432kc_defconfig +++ b/boards/st/nucleo_l432kc/nucleo_l432kc_defconfig @@ -12,12 +12,6 @@ CONFIG_SERIAL=y # enable GPIO CONFIG_GPIO=y -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - # console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_l433rc_p/board.cmake b/boards/st/nucleo_l433rc_p/board.cmake index d9f0635b48b..cabd763429f 100644 --- a/boards/st/nucleo_l433rc_p/board.cmake +++ b/boards/st/nucleo_l433rc_p/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32L433RC" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_l433rc_p/doc/index.rst b/boards/st/nucleo_l433rc_p/doc/index.rst index 8981c68b236..75b3a8fe20e 100644 --- a/boards/st/nucleo_l433rc_p/doc/index.rst +++ b/boards/st/nucleo_l433rc_p/doc/index.rst @@ -173,6 +173,8 @@ to LPUART1. Default settings are 115200 8N1. Programming and Debugging ************************* +Nucleo L433RC-P board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``nucleo_l433rc_p`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -180,9 +182,16 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo L433RC-P board includes an ST-LINK/V2-1 embedded debug tool -interface. This interface is supported by the openocd version -included in the Zephyr SDK since v0.9.2. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to Nucleo L433RC-P ------------------------------------------ @@ -195,7 +204,7 @@ then run a serial host program to connect with your Nucleo board. $ picocom /dev/ttyACM0 -b 115200 Now build and flash an application. Here is an example for -:ref:`hello_world`. +:zephyr:code-sample:`hello_world`. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -213,7 +222,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -232,3 +241,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32L432 reference manual: https://www.st.com/resource/en/reference_manual/dm00151940.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_l433rc_p/nucleo_l433rc_p_defconfig b/boards/st/nucleo_l433rc_p/nucleo_l433rc_p_defconfig index 82ee7285d52..3fe5e4f9882 100644 --- a/boards/st/nucleo_l433rc_p/nucleo_l433rc_p_defconfig +++ b/boards/st/nucleo_l433rc_p/nucleo_l433rc_p_defconfig @@ -12,12 +12,6 @@ CONFIG_SERIAL=y # enable GPIO CONFIG_GPIO=y -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - # console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_l452re/board.cmake b/boards/st/nucleo_l452re/board.cmake index 066106d4a19..61fc4681587 100644 --- a/boards/st/nucleo_l452re/board.cmake +++ b/boards/st/nucleo_l452re/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32L452RE" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_l452re/doc/index.rst b/boards/st/nucleo_l452re/doc/index.rst index 57839f931c5..9587b9e6c02 100644 --- a/boards/st/nucleo_l452re/doc/index.rst +++ b/boards/st/nucleo_l452re/doc/index.rst @@ -192,6 +192,8 @@ Default settings are 115200 8N1. Programming and Debugging ************************* +Nucleo L452RE board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``nucleo_l452re`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -199,9 +201,16 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo L452RE board includes an ST-LINK/V2-1 embedded debug tool -interface. This interface is supported by the openocd version -included in the Zephyr SDK since v0.9.2. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to Nucleo L452RE ---------------------------------------- @@ -214,7 +223,7 @@ then run a serial host program to connect with your Nucleo board. $ minicom -D /dev/ttyACM0 Now build and flash an application. Here is an example for -:ref:`hello_world`. +:zephyr:code-sample:`hello_world`. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -239,7 +248,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -264,3 +273,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32L452 reference manual: https://www.st.com/resource/en/reference_manual/dm00151940.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_l452re/nucleo_l452re_defconfig b/boards/st/nucleo_l452re/nucleo_l452re_defconfig index 94950b2862f..06ac5af2627 100644 --- a/boards/st/nucleo_l452re/nucleo_l452re_defconfig +++ b/boards/st/nucleo_l452re/nucleo_l452re_defconfig @@ -12,12 +12,6 @@ CONFIG_HW_STACK_PROTECTION=y # enable GPIO CONFIG_GPIO=y -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - # console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_l452re/nucleo_l452re_stm32l452xx_p_defconfig b/boards/st/nucleo_l452re/nucleo_l452re_stm32l452xx_p_defconfig index 94950b2862f..06ac5af2627 100644 --- a/boards/st/nucleo_l452re/nucleo_l452re_stm32l452xx_p_defconfig +++ b/boards/st/nucleo_l452re/nucleo_l452re_stm32l452xx_p_defconfig @@ -12,12 +12,6 @@ CONFIG_HW_STACK_PROTECTION=y # enable GPIO CONFIG_GPIO=y -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - # console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_l476rg/board.cmake b/boards/st/nucleo_l476rg/board.cmake index 7739c00b5e7..8dd9a438478 100644 --- a/boards/st/nucleo_l476rg/board.cmake +++ b/boards/st/nucleo_l476rg/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32L476RG" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_l476rg/doc/index.rst b/boards/st/nucleo_l476rg/doc/index.rst index a45b18b339e..ac566003430 100644 --- a/boards/st/nucleo_l476rg/doc/index.rst +++ b/boards/st/nucleo_l476rg/doc/index.rst @@ -181,6 +181,8 @@ Default settings are 115200 8N1. Programming and Debugging ************************* +Nucleo L476RG board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``nucleo_l476rg`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -188,16 +190,23 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo L476RG board includes an ST-LINK/V2-1 embedded debug tool -interface. This interface is supported by the openocd version -included in the Zephyr SDK since v0.9.2. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to Nucleo L476RG ---------------------------------------- Connect the Nucleo L476RG to your host computer using the USB port. Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board: @@ -222,7 +231,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -241,3 +250,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32L476 reference manual: https://www.st.com/resource/en/reference_manual/DM00083560.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_l476rg/nucleo_l476rg_defconfig b/boards/st/nucleo_l476rg/nucleo_l476rg_defconfig index 76e7e50d1fa..72ba65e4faf 100644 --- a/boards/st/nucleo_l476rg/nucleo_l476rg_defconfig +++ b/boards/st/nucleo_l476rg/nucleo_l476rg_defconfig @@ -6,9 +6,6 @@ CONFIG_SERIAL=y # enable GPIO CONFIG_GPIO=y -# enable clocks -CONFIG_CLOCK_CONTROL=y - # console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y @@ -18,6 +15,3 @@ CONFIG_ARM_MPU=y # Enable HW stack protection CONFIG_HW_STACK_PROTECTION=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_l496zg/board.cmake b/boards/st/nucleo_l496zg/board.cmake index bbb63238a8d..eab553680b0 100644 --- a/boards/st/nucleo_l496zg/board.cmake +++ b/boards/st/nucleo_l496zg/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32L496ZG" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_l496zg/doc/index.rst b/boards/st/nucleo_l496zg/doc/index.rst index da208a4c8d9..4abdc105c6a 100644 --- a/boards/st/nucleo_l496zg/doc/index.rst +++ b/boards/st/nucleo_l496zg/doc/index.rst @@ -127,6 +127,8 @@ The Zephyr nucleo_l496zg board configuration supports the following hardware fea +-----------+------------+-------------------------------------+ | RTC | on-chip | rtc | +-----------+------------+-------------------------------------+ +| OTG FS | on-chip | USB OTG Full-speed | ++-----------+------------+-------------------------------------+ | WATCHDOG | on-chip | System Window Watchdog | +-----------+------------+-------------------------------------+ @@ -182,6 +184,8 @@ Default settings are 115200 8N1. Programming and Debugging ************************* +Nucleo L496ZG board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``nucleo_l496zg`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -189,16 +193,23 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo L496ZG board includes an ST-LINK/V2-1 embedded debug tool -interface. This interface is supported by the openocd version -included in the Zephyr SDK since v0.9.5. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to Nucleo L496ZG ---------------------------------------- Connect the Nucleo L496ZG to your host computer using the USB port. Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board: @@ -223,7 +234,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -242,3 +253,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32L496 reference manual: https://www.st.com/resource/en/reference_manual/dm00083560.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_l496zg/nucleo_l496zg.dts b/boards/st/nucleo_l496zg/nucleo_l496zg.dts index 54a9015d0f2..2589fef3342 100644 --- a/boards/st/nucleo_l496zg/nucleo_l496zg.dts +++ b/boards/st/nucleo_l496zg/nucleo_l496zg.dts @@ -72,6 +72,10 @@ status = "okay"; }; +&clk_hsi48 { + status = "okay"; +}; + &pll { div-m = <1>; mul-n = <20>; @@ -111,6 +115,12 @@ status = "okay"; }; +zephyr_udc0: &usbotg_fs { + pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; + pinctrl-names = "default"; + status = "okay"; +}; + &timers1 { st,prescaler = <10000>; status = "okay"; diff --git a/boards/st/nucleo_l496zg/nucleo_l496zg.yaml b/boards/st/nucleo_l496zg/nucleo_l496zg.yaml index 39734163f3d..d1b92282d38 100644 --- a/boards/st/nucleo_l496zg/nucleo_l496zg.yaml +++ b/boards/st/nucleo_l496zg/nucleo_l496zg.yaml @@ -16,6 +16,9 @@ supported: - spi - pwm - counter + - usb + - usb_device + - usbd - watchdog testing: ignore_tags: diff --git a/boards/st/nucleo_l496zg/nucleo_l496zg_defconfig b/boards/st/nucleo_l496zg/nucleo_l496zg_defconfig index 5ef11a3cb3f..72ba65e4faf 100644 --- a/boards/st/nucleo_l496zg/nucleo_l496zg_defconfig +++ b/boards/st/nucleo_l496zg/nucleo_l496zg_defconfig @@ -6,9 +6,6 @@ CONFIG_SERIAL=y # enable GPIO CONFIG_GPIO=y -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - # console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y @@ -18,6 +15,3 @@ CONFIG_ARM_MPU=y # Enable HW stack protection CONFIG_HW_STACK_PROTECTION=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_l4a6zg/board.cmake b/boards/st/nucleo_l4a6zg/board.cmake index c268c57adae..293f2736a07 100644 --- a/boards/st/nucleo_l4a6zg/board.cmake +++ b/boards/st/nucleo_l4a6zg/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32L4A6ZG" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_l4a6zg/doc/index.rst b/boards/st/nucleo_l4a6zg/doc/index.rst index 30cac697dde..267d5f619b8 100644 --- a/boards/st/nucleo_l4a6zg/doc/index.rst +++ b/boards/st/nucleo_l4a6zg/doc/index.rst @@ -181,6 +181,8 @@ Default settings are 115200 8N1. Programming and Debugging ************************* +Nucleo L4A6ZG board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``nucleo_l4a6zg`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -188,16 +190,23 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo L4A6ZG board includes an ST-LINK/V2-1 embedded debug tool -interface. This interface is supported by the OpenOCD version -included in the Zephyr SDK since v0.9.5. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to Nucleo L4A6ZG ---------------------------------------- Connect the Nucleo L4A6ZG to your host computer using the ST-LINK USB port. Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board: @@ -222,7 +231,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -241,3 +250,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32L4A6 reference manual: https://www.st.com/resource/en/reference_manual/dm00083560.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_l4a6zg/nucleo_l4a6zg_defconfig b/boards/st/nucleo_l4a6zg/nucleo_l4a6zg_defconfig index 5ef11a3cb3f..72ba65e4faf 100644 --- a/boards/st/nucleo_l4a6zg/nucleo_l4a6zg_defconfig +++ b/boards/st/nucleo_l4a6zg/nucleo_l4a6zg_defconfig @@ -6,9 +6,6 @@ CONFIG_SERIAL=y # enable GPIO CONFIG_GPIO=y -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - # console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y @@ -18,6 +15,3 @@ CONFIG_ARM_MPU=y # Enable HW stack protection CONFIG_HW_STACK_PROTECTION=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_l4r5zi/board.cmake b/boards/st/nucleo_l4r5zi/board.cmake index 0def9a56111..2d7ce04b87e 100644 --- a/boards/st/nucleo_l4r5zi/board.cmake +++ b/boards/st/nucleo_l4r5zi/board.cmake @@ -1,8 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32L4R5ZI" "--speed=4000") +# keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_l4r5zi/doc/index.rst b/boards/st/nucleo_l4r5zi/doc/index.rst index 5fd6156e1ba..1a1302aa3e2 100644 --- a/boards/st/nucleo_l4r5zi/doc/index.rst +++ b/boards/st/nucleo_l4r5zi/doc/index.rst @@ -223,21 +223,27 @@ Programming and Debugging The NUCLEO-L4R5ZI board includes a ST-LINK/V2 embedded debug tool interface. +Flashing +======== + The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, -so its installation is required to be able to flash the board. +so its :ref:`installation ` is required. -Alternatively, openocd (provided in Zephyr SDK) or JLink can also be used to -flash the board using the ``--runner`` (or ``-r``) option: +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: .. code-block:: console $ west flash --runner openocd $ west flash --runner jlink +Flashing an application to Nucleo L4R4ZI +---------------------------------------- + Connect the Nucleo L4R5ZI to your host computer using the USB port. Then build and flash an application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board: diff --git a/boards/st/nucleo_l4r5zi/nucleo_l4r5zi_defconfig b/boards/st/nucleo_l4r5zi/nucleo_l4r5zi_defconfig index 4ba8077edd6..165b1944f31 100644 --- a/boards/st/nucleo_l4r5zi/nucleo_l4r5zi_defconfig +++ b/boards/st/nucleo_l4r5zi/nucleo_l4r5zi_defconfig @@ -6,9 +6,6 @@ CONFIG_SERIAL=y # Enable GPIO CONFIG_GPIO=y -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - # Console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y @@ -18,6 +15,3 @@ CONFIG_ARM_MPU=y # Enable HW stack protection CONFIG_HW_STACK_PROTECTION=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_l552ze_q/board.cmake b/boards/st/nucleo_l552ze_q/board.cmake index 7ec6ceb8ab9..4308af48306 100644 --- a/boards/st/nucleo_l552ze_q/board.cmake +++ b/boards/st/nucleo_l552ze_q/board.cmake @@ -1,4 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 + if(CONFIG_BUILD_WITH_TFM) set(FLASH_BASE_ADDRESS_S 0x0C000000) @@ -12,10 +13,15 @@ if(CONFIG_BUILD_WITH_TFM) endif() endif() +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") + set_ifndef(BOARD_DEBUG_RUNNER pyocd) set_ifndef(BOARD_FLASH_RUNNER pyocd) board_runner_args(pyocd "--target=stm32l552zetxq") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/st/nucleo_l552ze_q/doc/nucleol552ze_q.rst b/boards/st/nucleo_l552ze_q/doc/nucleol552ze_q.rst index f084852c7ad..0d5aa6e0fd8 100644 --- a/boards/st/nucleo_l552ze_q/doc/nucleol552ze_q.rst +++ b/boards/st/nucleo_l552ze_q/doc/nucleol552ze_q.rst @@ -197,9 +197,9 @@ The BOARD options are summarized below: +--------------------------------+-------------------------------------------+ Here are the instructions to build Zephyr with a non-secure configuration, -using `tfm_ipc_` sample: +using :zephyr:code-sample:`tfm_ipc` sample: - .. code-block:: bash + .. code-block:: console $ west build -b nucleo_l552ze_q/stm32l552xx/ns samples/tfm_integration/tfm_ipc/ @@ -213,7 +213,7 @@ option bit TZEN will be set). $ west flash Please note that, after having run a TFM sample on the board, you will need to -run `./build/tfm/api_ns/regression.sh` once more to clean up the board from secure +run ``./build/tfm/api_ns/regression.sh`` once more to clean up the board from secure options and get back the platform back to a "normal" state and be able to run usual, non-TFM, binaries. Also note that, even then, TZEN will remain set, and you will need to use @@ -282,6 +282,8 @@ UART2. Default settings are 115200 8N1. Programming and Debugging ************************* +Nucleo L552ZE Q board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``nucleo_l552ze_q`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -289,24 +291,31 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo L552ZE Q board includes an ST-LINK/V2-1 embedded debug tool -interface. Support can be enabled on pyocd by adding "pack" support with the -following pyocd command: +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or pyOCD can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner pyocd + +Support can be enabled for pyOCD by adding "pack" support with the +following pyOCD commands: .. code-block:: console $ pyocd pack --update $ pyocd pack --install stm32l552ze -Alternatively, this interface is supported by the openocd version -included in the Zephyr SDK since v0.13.1. - Flashing an application to Nucleo L552ZE Q ------------------------------------------ Connect the Nucleo L552ZE Q to your host computer using the USB port. Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board: @@ -331,7 +340,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_l552ze_q/nucleo_l552ze_q_defconfig b/boards/st/nucleo_l552ze_q/nucleo_l552ze_q_defconfig index 08e07645470..8655ea99d42 100644 --- a/boards/st/nucleo_l552ze_q/nucleo_l552ze_q_defconfig +++ b/boards/st/nucleo_l552ze_q/nucleo_l552ze_q_defconfig @@ -6,9 +6,6 @@ CONFIG_SERIAL=y # enable GPIO CONFIG_GPIO=y -# Enable clock -CONFIG_CLOCK_CONTROL=y - # console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y @@ -18,6 +15,3 @@ CONFIG_ARM_MPU=y # Enable HW stack protection CONFIG_HW_STACK_PROTECTION=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_l552ze_q/nucleo_l552ze_q_stm32l552xx_ns_defconfig b/boards/st/nucleo_l552ze_q/nucleo_l552ze_q_stm32l552xx_ns_defconfig index 540ddddfc4e..cad42d57d8c 100644 --- a/boards/st/nucleo_l552ze_q/nucleo_l552ze_q_stm32l552xx_ns_defconfig +++ b/boards/st/nucleo_l552ze_q/nucleo_l552ze_q_stm32l552xx_ns_defconfig @@ -6,9 +6,6 @@ CONFIG_SERIAL=y # enable GPIO CONFIG_GPIO=y -# Enable clock -CONFIG_CLOCK_CONTROL=y - # console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y @@ -19,6 +16,3 @@ CONFIG_ARM_MPU=y CONFIG_ARM_TRUSTZONE_M=y CONFIG_RUNTIME_NMI=y CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_u031r8/Kconfig.nucleo_u031r8 b/boards/st/nucleo_u031r8/Kconfig.nucleo_u031r8 new file mode 100644 index 00000000000..799a9d6d9d4 --- /dev/null +++ b/boards/st/nucleo_u031r8/Kconfig.nucleo_u031r8 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_U031R8 + select SOC_STM32U031XX diff --git a/boards/st/nucleo_u031r8/arduino_r3_connector.dtsi b/boards/st/nucleo_u031r8/arduino_r3_connector.dtsi new file mode 100644 index 00000000000..9dbbb45ec52 --- /dev/null +++ b/boards/st/nucleo_u031r8/arduino_r3_connector.dtsi @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpioa 0 0>, /* A0 */ + <1 0 &gpioa 1 0>, /* A1 */ + <2 0 &gpioa 4 0>, /* A2 */ + <3 0 &gpiob 0 0>, /* A3 */ + <4 0 &gpioc 1 0>, /* A4 */ + <5 0 &gpioc 0 0>, /* A5 */ + <6 0 &gpioa 3 0>, /* D0 */ + <7 0 &gpioa 2 0>, /* D1 */ + <8 0 &gpioa 10 0>, /* D2 */ + <9 0 &gpiob 3 0>, /* D3 */ + <10 0 &gpiob 5 0>, /* D4 */ + <11 0 &gpiob 4 0>, /* D5 */ + <12 0 &gpiob 10 0>, /* D6 */ + <13 0 &gpioa 8 0>, /* D7 */ + <14 0 &gpioa 9 0>, /* D8 */ + <15 0 &gpioc 7 0>, /* D9 */ + <16 0 &gpiob 6 0>, /* D10 */ + <17 0 &gpioa 7 0>, /* D11 */ + <18 0 &gpioa 6 0>, /* D12 */ + <19 0 &gpioa 5 0>, /* D13 */ + <20 0 &gpiob 9 0>, /* D14 */ + <21 0 &gpiob 8 0>; /* D15 */ + }; +}; + +arduino_serial: &usart1 {}; diff --git a/boards/st/nucleo_u031r8/board.cmake b/boards/st/nucleo_u031r8/board.cmake new file mode 100644 index 00000000000..7028d124f20 --- /dev/null +++ b/boards/st/nucleo_u031r8/board.cmake @@ -0,0 +1,9 @@ +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") + +board_runner_args(pyocd "--target=stm32u031r8tx") + +board_runner_args(jlink "--device=STM32U031R8" "--reset-after-load") + +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_u031r8/board.yml b/boards/st/nucleo_u031r8/board.yml new file mode 100644 index 00000000000..afbb6b5b6b6 --- /dev/null +++ b/boards/st/nucleo_u031r8/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_u031r8 + vendor: st + socs: + - name: stm32u031xx diff --git a/boards/st/nucleo_u031r8/doc/img/nucleo_u031r8.jpg b/boards/st/nucleo_u031r8/doc/img/nucleo_u031r8.jpg new file mode 100644 index 00000000000..f57de5f8efd Binary files /dev/null and b/boards/st/nucleo_u031r8/doc/img/nucleo_u031r8.jpg differ diff --git a/boards/st/nucleo_u031r8/doc/index.rst b/boards/st/nucleo_u031r8/doc/index.rst new file mode 100644 index 00000000000..490012ddc81 --- /dev/null +++ b/boards/st/nucleo_u031r8/doc/index.rst @@ -0,0 +1,266 @@ +.. _nucleo_u031r8_board: + +ST Nucleo U031R8 +################ + +Overview +******** + +The Nucleo U031R8 board, featuring an ARM Cortex-M0+ based STM32U031R8 MCU, +provides an affordable and flexible way for users to try out new concepts and +build prototypes by choosing from the various combinations of performance and +power consumption features. Here are some highlights of the Nucleo U031R8 +board: + + +- STM32U031R8 microcontroller in LQFP48 package +- Two types of extension resources: + + - Arduino Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32U0 I/Os + +- On-board STLINK-V2EC debugger/programmer with USB re-enumeration + capability: mass storage, Virtual COM port, and debug port +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + +- User LED shared with ARDUINO |reg| Uno V3 +- Two push-buttons: USER and RESET +- USB Type-C |reg| connector for the ST-LINK + +Hardware +******** + +The STM32U031x4/6/8 devices are an ultra-low-power microcontrollers family (STM32U0 +Series) based on the high-performance Arm |reg| Cortex |reg|-M0+ 32-bit RISC core. +They operate at a frequency of up to 56 MHz. + +- Includes ST state-of-the-art patented technology +- Ultra-low-power with FlexPowerControl: + + - 1.71 V to 3.6 V power supply + - -40 °C to +85/125 °C temperature range + - 130 nA VBAT mode: supply for RTC, 9 x 32-bit backup registers + - 16 nA Shutdown mode (4 wake-up pins) + - 30 nA Standby mode (6 wake-up pins) without RTC + - 160 nA Standby mode with RTC + - 630 nA Stop 2 mode with RTC + - 515 nA Stop 2 mode without RTC + - 4 µA wake-up from Stop mode + - 52 µA/MHz Run mode + - Brownout reset + +- Core: + + - 32-bit Arm |reg| Cortex |reg|-M0+ CPU, frequency up to 56 MHz + +- ART Accelerator: + + - 1-Kbyte instruction cache allowing 0-wait-state execution from flash memory + +- Benchmarks: + + - 1.13 DMIPS/MHz (Drystone 2.1) + - 134 CoreMark |reg| (2.4 CoreMark/MHz at 56 MHz) + - 430 ULPMark™-CP + - 167 ULPMark™-PP + - 20.3 ULPMark™-CM + +- Memories: + + - 64-Kbyte single bank flash memory, proprietary code readout protection + - 12-Kbyte SRAM with hardware parity check + +- General-purpose input/outputs: + + - Up to 53 fast I/Os, most of them 5 V‑tolerant + +- Clock management: + + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC (±1%) + - Internal low-power 32 kHz RC (±5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, + auto-trimmed by LSE (better than ±0.25 % accuracy) + - PLL for system clock, ADC + +- Security: + + - Customer code protection + - Robust read out protection (RDP): 3 protection level states + and password-based regression (128-bit PSWD) + - Hardware protection feature (HDP) + - Secure boot + - True random number generation, candidate for NIST SP 800-90B certification + - Candidate for Arm |reg| PSA level 1 and SESIP level 3 certifications + - 5 passive anti-tamper pins + - 96-bit unique ID + +- Up to 9 timers, RTC, and 2 watchdogs : + + - 1x 16-bit advanced motor-control, 1x 32-bit and 3x 16-bit general purpose, + 2x 16-bit basic, 2x low-power 16-bit timers (available in Stop mode), + 2x watchdogs, SysTick timer + - RTC with hardware calendar, alarms and calibration + +- Up to 16 communication peripherals: + + - 6x USARTs/LPUARTs (SPI, ISO 7816, LIN, IrDA, modem) + - 3x I2C interfaces supporting Fast-mode and Fast-mode Plus (up to 1 Mbit/s) + - 2x SPIs, plus 4x USARTs in SPI mode + - IRTIM (Infrared interface) + +- Rich analog peripherals (independent supply): + + - 1x 12-bit ADC (0.4 µs conversion time), up to 16-bit with hardware oversampling + - 1x 12-bit DAC output channel, low-power sample and hold + - 1x general-purpose operational amplifier with built-in PGA (variable gain up to 16) + - 1x ultra-low-power comparator + +- ECOPACK2 compliant packages + +More information about STM32U031R8 can be found here: + +- `STM32U031R8 on www.st.com`_ +- `STM32U031R8 reference manual`_ + +Supported Features +================== + +The Zephyr _nucleo_u031r8_ board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_u031r8/nucleo_u031r8_defconfig` + + +Connections and IOs +=================== + +Nucleo U031R8 Board has 10 GPIO controllers. These controllers are responsible +for pin muxing, input/output, pull-up, etc. + +For more details please refer to `STM32U031 User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- DAC1_OUT1 : PA4 +- LD1 : PA5 +- UART_1_TX : PA9 +- UART_1_RX : PA10 +- UART_2_TX : PA2 +- UART_2_RX : PA3 +- USER_PB : PC13 + +System Clock +------------ + +Nucleo U031R8 System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at +48MHz, driven by 4MHz medium speed internal oscillator. + +Serial Port +----------- + +Nucleo U031R8 board has 4 U(S)ARTs. The Zephyr console output is assigned to +USART2. Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Nucleo U031R8 board includes an ST-LINK/V3 embedded debug tool interface. +This probe allows to flash the board using various tools. + +Flashing +======== + +Board is configured to be flashed using west STM32CubeProgrammer runner. +Installation of `STM32CubeProgrammer`_ is then required to flash the board. + +Alternatively, pyocd or jlink via an external probe can also be used to flash +and debug the board if west is told to use it as runner, which can be done by +passing either or ``-r pyocd``, or ``-r jlink``. + +For pyocd additional target information needs to be installed. +This can be done by executing the following commands. + +.. code-block:: console + + $ pyocd pack --update + $ pyocd pack --install stm32u0 + + +Flashing an application to Nucleo U031R8 +------------------------------------------ + +Connect the Nucleo U031R8 to your host computer using the USB port. +Then build and flash an application. Here is an example for the +:zephyr:code-sample:`hello_world` application. + +Run a serial host program to connect with your Nucleo board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash the application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_u031r8 + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! nucleo_u031r8 + +Debugging +========= + +Default flasher for this board is openocd. It could be used in the usual way. +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_u031r8 + :goals: debug + +Note: Check the ``build/tfm`` directory to ensure that the commands required by these scripts +(``readlink``, etc.) are available on your system. Please also check ``STM32_Programmer_CLI`` +(which is used for initialization) is available in the PATH. + +.. _NUCLEO_U031R8 website: + https://www.st.com/en/evaluation-tools/nucleo-u031r8.html + +.. _STM32U031 User Manual: + https://www.st.com/resource/en/user_manual/um3261-stm32u0-series-safety-manual-stmicroelectronics.pdf + +.. _STM32U031R8 on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32u031r8 + +.. _STM32U031R8 reference manual: + https://www.st.com/resource/en/reference_manual/rm0503-stm32u0-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_u031r8/nucleo_u031r8.dts b/boards/st/nucleo_u031r8/nucleo_u031r8.dts new file mode 100644 index 00000000000..e6875786e03 --- /dev/null +++ b/boards/st/nucleo_u031r8/nucleo_u031r8.dts @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include "arduino_r3_connector.dtsi" +#include + +/ { + model = "STMicroelectronics STM32U83RC-NUCLEO board"; + compatible = "st,stm32u031r8-nucleo"; + + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &usart2; + zephyr,shell-uart = &usart2; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + leds: leds { + compatible = "gpio-leds"; + green_led_1: led_1 { + gpios = <&gpioa 5 GPIO_ACTIVE_HIGH>; + label = "User LD4"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button: button { + label = "User"; + gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>; + zephyr,code = ; + }; + }; + + aliases { + led0 = &green_led_1; + sw0 = &user_button; + }; +}; + +&usart1 { + pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&usart2 { + pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&clk_hsi { + status = "okay"; +}; + +&pll { + div-m = <1>; + mul-n = <6>; + div-p = <2>; + div-q = <2>; + div-r = <2>; + clocks = <&clk_hsi>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <1>; +}; + +&dac1 { + status = "okay"; + pinctrl-0 = <&dac1_out1_pa4>; + pinctrl-names = "default"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>; + pinctrl-names = "default"; + status = "okay"; + clock-frequency = ; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_scl_pa7 &i2c2_sda_pa6>; + pinctrl-names = "default"; + status = "okay"; + clock-frequency = ; +}; diff --git a/boards/st/nucleo_u031r8/nucleo_u031r8.yaml b/boards/st/nucleo_u031r8/nucleo_u031r8.yaml new file mode 100644 index 00000000000..7995c39a1c6 --- /dev/null +++ b/boards/st/nucleo_u031r8/nucleo_u031r8.yaml @@ -0,0 +1,14 @@ +identifier: nucleo_u031r8 +name: ST Nucleo U031R8 +type: mcu +arch: arm +toolchain: + - zephyr +supported: + - arduino_gpio + - dac + - gpio + - i2c + - usart +ram: 12 +flash: 64 diff --git a/boards/st/nucleo_u031r8/nucleo_u031r8_defconfig b/boards/st/nucleo_u031r8/nucleo_u031r8_defconfig new file mode 100644 index 00000000000..87c94473c7d --- /dev/null +++ b/boards/st/nucleo_u031r8/nucleo_u031r8_defconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y diff --git a/boards/st/nucleo_u083rc/Kconfig.nucleo_u083rc b/boards/st/nucleo_u083rc/Kconfig.nucleo_u083rc new file mode 100644 index 00000000000..fee320c2916 --- /dev/null +++ b/boards/st/nucleo_u083rc/Kconfig.nucleo_u083rc @@ -0,0 +1,5 @@ +# Copyright (c) 2024 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_U083RC + select SOC_STM32U083XX diff --git a/boards/st/nucleo_u083rc/arduino_r3_connector.dtsi b/boards/st/nucleo_u083rc/arduino_r3_connector.dtsi new file mode 100644 index 00000000000..cb596a6c00a --- /dev/null +++ b/boards/st/nucleo_u083rc/arduino_r3_connector.dtsi @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpioa 0 0>, /* A0 */ + <1 0 &gpioa 1 0>, /* A1 */ + <2 0 &gpioa 4 0>, /* A2 */ + <3 0 &gpiob 0 0>, /* A3 */ + <4 0 &gpioc 1 0>, /* A4 */ + <5 0 &gpioc 0 0>, /* A5 */ + <6 0 &gpioa 3 0>, /* D0 */ + <7 0 &gpioa 2 0>, /* D1 */ + <8 0 &gpioa 10 0>, /* D2 */ + <9 0 &gpiob 3 0>, /* D3 */ + <10 0 &gpiob 5 0>, /* D4 */ + <11 0 &gpiob 4 0>, /* D5 */ + <12 0 &gpiob 10 0>, /* D6 */ + <13 0 &gpioa 8 0>, /* D7 */ + <14 0 &gpioa 9 0>, /* D8 */ + <15 0 &gpioc 7 0>, /* D9 */ + <16 0 &gpiob 6 0>, /* D10 */ + <17 0 &gpioa 7 0>, /* D11 */ + <18 0 &gpioa 6 0>, /* D12 */ + <19 0 &gpioa 5 0>, /* D13 */ + <20 0 &gpiob 9 0>, /* D14 */ + <21 0 &gpiob 8 0>; /* D15 */ + }; +}; + +arduino_serial: &usart2 {}; diff --git a/boards/st/nucleo_u083rc/board.cmake b/boards/st/nucleo_u083rc/board.cmake new file mode 100644 index 00000000000..d969b9dff1a --- /dev/null +++ b/boards/st/nucleo_u083rc/board.cmake @@ -0,0 +1,9 @@ +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") + +board_runner_args(pyocd "--target=stm32u083rctx") + +board_runner_args(jlink "--device=STM32U083RC" "--reset-after-load") + +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_u083rc/board.yml b/boards/st/nucleo_u083rc/board.yml new file mode 100644 index 00000000000..65d9734b288 --- /dev/null +++ b/boards/st/nucleo_u083rc/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_u083rc + vendor: st + socs: + - name: stm32u083xx diff --git a/boards/st/nucleo_u083rc/doc/img/nucleo_u083rc.jpg b/boards/st/nucleo_u083rc/doc/img/nucleo_u083rc.jpg new file mode 100644 index 00000000000..ecb54648626 Binary files /dev/null and b/boards/st/nucleo_u083rc/doc/img/nucleo_u083rc.jpg differ diff --git a/boards/st/nucleo_u083rc/doc/index.rst b/boards/st/nucleo_u083rc/doc/index.rst new file mode 100644 index 00000000000..e8e7f43e092 --- /dev/null +++ b/boards/st/nucleo_u083rc/doc/index.rst @@ -0,0 +1,281 @@ +.. _nucleo_u083rc_board: + +ST Nucleo U083RC +################ + +Overview +******** + +The Nucleo U083RC board, featuring an ARM Cortex-M0+ based STM32U083RC MCU, +provides an affordable and flexible way for users to try out new concepts and +build prototypes by choosing from the various combinations of performance and +power consumption features. Here are some highlights of the Nucleo U083RC +board: + + +- STM32U083RC microcontroller in LQFP64 package +- Two types of extension resources: + + - Arduino Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32U0 I/Os + +- On-board STLINK-V2EC debugger/programmer with USB re-enumeration + capability: mass storage, Virtual COM port, and debug port +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + +- User LED shared with ARDUINO |reg| Uno V3 +- Two push-buttons: USER and RESET +- USB Type-C |reg| connector for the ST-LINK + +Hardware +******** + +The STM32U083xC devices are an ultra-low-power microcontrollers family (STM32U0 +Series) based on the high-performance Arm |reg| Cortex |reg|-M0+ 32-bit RISC core. +They operate at a frequency of up to 56 MHz. + +- Includes ST state-of-the-art patented technology +- Ultra-low-power with FlexPowerControl: + + - 1.71 V to 3.6 V power supply + - -40 °C to +85/125 °C temperature range + - 130 nA VBAT mode: supply for RTC, 9 x 32-bit backup registers + - 16 nA Shutdown mode (6 wake-up pins) + - 30 nA Standby mode (6 wake-up pins) without RTC + - 160 nA Standby mode with RTC + - 825 nA Stop 2 mode with RTC + - 695 nA Stop 2 mode without RTC + - 4 µA wake-up from Stop mode + - 52 µA/MHz Run mode + - Brownout reset + +- Core: + + - 32-bit Arm |reg| Cortex |reg|-M0+ CPU, frequency up to 56 MHz + +- ART Accelerator: + + - 1-Kbyte instruction cache allowing 0-wait-state execution from flash memory + +- Benchmarks: + + - 1.13 DMIPS/MHz (Drystone 2.1) + - 134 CoreMark |reg| (2.4 CoreMark/MHz at 56 MHz) + - 407 ULPMark™-CP + - 143 ULPMark™-PP + - 19.7 ULPMark™-CM + +- Memories: + + - 256-Kbyte single bank flash memory, proprietary code readout protection + - 40-Kbyte SRAM with hardware parity check + +- General-purpose input/outputs: + + - Up to 69 fast I/Os, most of them 5 V‑tolerant + +- Clock management: + + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC (±1%) + - Internal low-power 32 kHz RC (±5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, + auto-trimmed by LSE (better than ±0.25 % accuracy) + - Internal 48 MHz with clock recovery + - PLL for system clock, USB, ADC + +- Security: + + - Customer code protection + - Robust read out protection (RDP): 3 protection level states + and password-based regression (128-bit PSWD) + - Hardware protection feature (HDP) + - Secure boot + - AES: 128/256-bit key encryption hardware accelerator + - True random number generation, candidate for NIST SP 800-90B certification + - Candidate for Arm |reg| PSA level 1 and SESIP level 3 certifications + - 5 passive anti-tamper pins + - 96-bit unique ID + +- Up to 10 timers, 2 watchdogs and RTC: + + - 1x 16-bit advanced motor-control, 1x 32-bit and 3x 16-bit general purpose, + 2x 16-bit basic, 3x low-power 16-bit timers (available in Stop mode), + 2x watchdogs, SysTick timer + - RTC with hardware calendar, alarms and calibration + +- Up to 20 communication peripherals: + + - 1 USB 2.0 full-speed crystal-less solution with LPM and BCD + - 7 USARTs/LPUARTs (SPI, ISO 7816, LIN, IrDA, modem) + - 4 I2C interfaces supporting Fast-mode and Fast-mode Plus (up to 1 Mbit/s) + - 3 SPIs, plus 4x USARTs in SPI mode + - IRTIM (Infrared interface) + +- Rich analog peripherals (independent supply): + + - 1x 12-bit ADC (0.4 µs conversion time), up to 16-bit with hardware oversampling + - 1x 12-bit DAC output channel, low-power sample and hold + - 1x general-purpose operational amplifier with built-in PGA (variable gain up to 16) + - 2x ultra-low-power comparators + +- ECOPACK2 compliant packages + +More information about STM32U083RC can be found here: + +- `STM32U083RC on www.st.com`_ +- `STM32U083 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_u083rc board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_u083rc/nucleo_u083rc_defconfig` + + +Connections and IOs +=================== + +Nucleo U083RC Board has 10 GPIO controllers. These controllers are responsible +for pin muxing, input/output, pull-up, etc. + +For more details please refer to `STM32U083 User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- DAC1_OUT1 : PA4 +- I2C1_SCL : PB8 +- I2C1_SDA : PB9 +- LPUART_1_TX : PG7 +- LPUART_1_RX : PG8 +- SPI1_NSS : PA4 +- SPI1_SCK : PA5 +- SPI1_MISO : PA6 +- SPI1_MOSI : PA7 +- UART_2_TX : PA2 +- UART_2_RX : PA3 +- USER_PB : PC13 + +System Clock +------------ + +Nucleo U083RC System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at +48MHz, driven by 4MHz medium speed internal oscillator. + +Serial Port +----------- + +Nucleo U083RC board has 7 U(S)ARTs. The Zephyr console output is assigned to +USART2. Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Nucleo U083RC board includes an ST-LINK/V3 embedded debug tool interface. +This probe allows to flash the board using various tools. + +Flashing +======== + +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, JLink or pyOCD can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner jlink + $ west flash --runner pyocd + +For pyOCD, additional target information needs to be installed. +This can be done by executing the following commands. + +.. code-block:: console + + $ pyocd pack --update + $ pyocd pack --install stm32u0 + + +Flashing an application to Nucleo U083RC +------------------------------------------ + +Connect the Nucleo U083RC to your host computer using the USB port. +Then build and flash an application. Here is an example for the +:zephyr:code-sample:`hello_world` application. + +Run a serial host program to connect with your Nucleo board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash the application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_u083rc + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! nucleo_u083rc/stm32u083xx + +Debugging +========= + +Default flasher for this board is openocd. It could be used in the usual way. +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_u083rc + :goals: debug + +Note: Check the ``build/tfm`` directory to ensure that the commands required by these scripts +(``readlink``, etc.) are available on your system. Please also check ``STM32_Programmer_CLI`` +(which is used for initialization) is available in the PATH. + +.. _NUCLEO_U083RC website: + https://www.st.com/en/evaluation-tools/nucleo-u083rc.html + +.. _STM32U083 User Manual: + https://www.st.com/resource/en/user_manual/um3261-stm32u0-series-safety-manual-stmicroelectronics.pdf + +.. _STM32U083RC on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32u083rc + +.. _STM32U083 reference manual: + https://www.st.com/resource/en/reference_manual/rm0503-stm32u0-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_u083rc/nucleo_u083rc.dts b/boards/st/nucleo_u083rc/nucleo_u083rc.dts new file mode 100644 index 00000000000..5d3bfe02f85 --- /dev/null +++ b/boards/st/nucleo_u083rc/nucleo_u083rc.dts @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include "arduino_r3_connector.dtsi" +#include + +/ { + model = "STMicroelectronics STM32U83RC-NUCLEO board"; + compatible = "st,stm32u083rc-nucleo"; + + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &usart2; + zephyr,shell-uart = &usart2; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + leds: leds { + compatible = "gpio-leds"; + green_led_1: led_4 { + gpios = <&gpioa 5 GPIO_ACTIVE_HIGH>; + label = "User LD4"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button: button { + label = "User"; + gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>; + zephyr,code = ; + }; + }; + + aliases { + led0 = &green_led_1; + sw0 = &user_button; + }; +}; + +&usart1 { + pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&usart2 { + pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&clk_hsi { + status = "okay"; +}; + +&pll { + div-m = <1>; + mul-n = <6>; + div-p = <2>; + div-q = <2>; + div-r = <2>; + clocks = <&clk_hsi>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <1>; +}; + +&dac1 { + status = "okay"; + pinctrl-0 = <&dac1_out1_pa4>; + pinctrl-names = "default"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>; + pinctrl-names = "default"; + status = "okay"; + clock-frequency = ; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_scl_pa7 &i2c2_sda_pa6>; + pinctrl-names = "default"; + status = "okay"; + clock-frequency = ; +}; diff --git a/boards/st/nucleo_u083rc/nucleo_u083rc.yaml b/boards/st/nucleo_u083rc/nucleo_u083rc.yaml new file mode 100644 index 00000000000..1dc624d55c1 --- /dev/null +++ b/boards/st/nucleo_u083rc/nucleo_u083rc.yaml @@ -0,0 +1,16 @@ +identifier: nucleo_u083rc +name: ST Nucleo U083RC +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - arduino_gpio + - dac + - gpio + - i2c + - usart +ram: 40 +flash: 256 diff --git a/boards/st/nucleo_u083rc/nucleo_u083rc_defconfig b/boards/st/nucleo_u083rc/nucleo_u083rc_defconfig new file mode 100644 index 00000000000..ce451a733e4 --- /dev/null +++ b/boards/st/nucleo_u083rc/nucleo_u083rc_defconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y diff --git a/boards/st/nucleo_u083rc/st_morpho_connector.dtsi b/boards/st/nucleo_u083rc/st_morpho_connector.dtsi new file mode 100644 index 00000000000..698937c5da1 --- /dev/null +++ b/boards/st/nucleo_u083rc/st_morpho_connector.dtsi @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + st_morpho_header: st-morpho-header { + compatible = "st-morpho-header"; + #gpio-cells = <2>; + gpio-map-mask = ; + gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>; + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; +}; diff --git a/boards/st/nucleo_u575zi_q/board.cmake b/boards/st/nucleo_u575zi_q/board.cmake index a37e241d2ce..17127a40101 100644 --- a/boards/st/nucleo_u575zi_q/board.cmake +++ b/boards/st/nucleo_u575zi_q/board.cmake @@ -1,4 +1,4 @@ -board_runner_args(stm32cubeprogrammer "--erase" "--port=swd" "--reset-mode=hw") +# keep first board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(openocd "--tcl-port=6666") @@ -9,6 +9,7 @@ board_runner_args(pyocd "--target=stm32u575zitx") board_runner_args(jlink "--device=STM32U575ZI" "--reset-after-load") +# keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/st/nucleo_u575zi_q/doc/index.rst b/boards/st/nucleo_u575zi_q/doc/index.rst index d69bbe3f28d..080bd074c4f 100644 --- a/boards/st/nucleo_u575zi_q/doc/index.rst +++ b/boards/st/nucleo_u575zi_q/doc/index.rst @@ -247,14 +247,19 @@ This probe allows to flash the board using various tools. Flashing ======== -Board is configured to be flashed using west STM32CubeProgrammer runner. -Installation of `STM32CubeProgrammer`_ is then required to flash the board. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. -Alternatively, openocd (provided in Zephyr SDK), JLink and pyocd can also be -used to flash and debug the board if west is told to use it as runner, -which can be done by passing either ``-r openocd``, ``-r jlink`` or ``-r pyocd``. +Alternatively, OpenOCD, JLink, or pyOCD can also be used to flash the board using +the ``--runner`` (or ``-r``) option: -For pyocd additional target information needs to be installed. +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink + $ west flash --runner pyocd + +For pyOCD, additional target information needs to be installed. This can be done by executing the following commands. .. code-block:: console @@ -268,7 +273,7 @@ Flashing an application to Nucleo U575ZI Q Connect the Nucleo U575ZI Q to your host computer using the USB port. Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board: diff --git a/boards/st/nucleo_u575zi_q/nucleo_u575zi_q-common.dtsi b/boards/st/nucleo_u575zi_q/nucleo_u575zi_q-common.dtsi index bd8dc8453e0..0d66260badd 100644 --- a/boards/st/nucleo_u575zi_q/nucleo_u575zi_q-common.dtsi +++ b/boards/st/nucleo_u575zi_q/nucleo_u575zi_q-common.dtsi @@ -199,3 +199,13 @@ zephyr_udc0: &usbotg_fs { &vbat4 { status = "okay"; }; + +&clk_lsi { + status = "okay"; +}; + +stm32_lp_tick_source: &lptim1 { + clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000800>, + <&rcc STM32_SRC_LSI LPTIM1_SEL(1)>; + status = "okay"; +}; diff --git a/boards/st/nucleo_u575zi_q/nucleo_u575zi_q.dts b/boards/st/nucleo_u575zi_q/nucleo_u575zi_q.dts index 8197b69868e..9fc2e2d2a86 100644 --- a/boards/st/nucleo_u575zi_q/nucleo_u575zi_q.dts +++ b/boards/st/nucleo_u575zi_q/nucleo_u575zi_q.dts @@ -30,6 +30,7 @@ watchdog0 = &iwdg; volt-sensor0 = &vref1; volt-sensor1 = &vbat4; + die-temp0 = &die_temp; }; }; @@ -43,3 +44,7 @@ &gpdma1 { status = "okay"; }; + +&die_temp { + status = "okay"; +}; diff --git a/boards/st/nucleo_u575zi_q/nucleo_u575zi_q_defconfig b/boards/st/nucleo_u575zi_q/nucleo_u575zi_q_defconfig index 08e07645470..8655ea99d42 100644 --- a/boards/st/nucleo_u575zi_q/nucleo_u575zi_q_defconfig +++ b/boards/st/nucleo_u575zi_q/nucleo_u575zi_q_defconfig @@ -6,9 +6,6 @@ CONFIG_SERIAL=y # enable GPIO CONFIG_GPIO=y -# Enable clock -CONFIG_CLOCK_CONTROL=y - # console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y @@ -18,6 +15,3 @@ CONFIG_ARM_MPU=y # Enable HW stack protection CONFIG_HW_STACK_PROTECTION=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_u5a5zj_q/board.cmake b/boards/st/nucleo_u5a5zj_q/board.cmake index 55861552c8e..eeef658184f 100644 --- a/boards/st/nucleo_u5a5zj_q/board.cmake +++ b/boards/st/nucleo_u5a5zj_q/board.cmake @@ -1,3 +1,4 @@ +# keep first board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(openocd "--tcl-port=6666") @@ -8,6 +9,7 @@ board_runner_args(pyocd "--target=stm32u5a5zjtx") board_runner_args(jlink "--device=STM32U5A5ZJ" "--reset-after-load") +# keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/st/nucleo_u5a5zj_q/doc/index.rst b/boards/st/nucleo_u5a5zj_q/doc/index.rst index 9245300e816..d3f90a178d4 100644 --- a/boards/st/nucleo_u5a5zj_q/doc/index.rst +++ b/boards/st/nucleo_u5a5zj_q/doc/index.rst @@ -279,14 +279,19 @@ This probe allows to flash the board using various tools. Flashing ======== -Board is configured to be flashed using west STM32CubeProgrammer runner. -Installation of `STM32CubeProgrammer`_ is then required to flash the board. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. -Alternatively, openocd (provided in Zephyr SDK), JLink and pyocd can also be -used to flash and debug the board if west is told to use it as runner, -which can be done by passing either ``-r openocd``, ``-r jlink`` or ``-r pyocd``. +Alternatively, OpenOCD, JLink, or pyOCD can also be used to flash the board using +the ``--runner`` (or ``-r``) option: -For pyocd additional target information needs to be installed. +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink + $ west flash --runner pyocd + +For pyOCD, additional target information needs to be installed. This can be done by executing the following commands. .. code-block:: console @@ -300,7 +305,7 @@ Flashing an application to Nucleo U5A5ZJ Q Connect the Nucleo U5A5ZJ Q to your host computer using the USB port. Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board: diff --git a/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.dts b/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.dts index c9296ccab97..a9907afe614 100644 --- a/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.dts +++ b/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.dts @@ -58,7 +58,7 @@ }; storage_partition: partition@3e2000 { label = "storage"; - reg = <0x003f0000 DT_SIZE_K(120)>; + reg = <0x003e2000 DT_SIZE_K(120)>; }; }; diff --git a/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q_defconfig b/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q_defconfig index 08e07645470..8655ea99d42 100644 --- a/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q_defconfig +++ b/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q_defconfig @@ -6,9 +6,6 @@ CONFIG_SERIAL=y # enable GPIO CONFIG_GPIO=y -# Enable clock -CONFIG_CLOCK_CONTROL=y - # console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y @@ -18,6 +15,3 @@ CONFIG_ARM_MPU=y # Enable HW stack protection CONFIG_HW_STACK_PROTECTION=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_wb05kz/Kconfig.nucleo_wb05kz b/boards/st/nucleo_wb05kz/Kconfig.nucleo_wb05kz new file mode 100644 index 00000000000..e1646cb0bdb --- /dev/null +++ b/boards/st/nucleo_wb05kz/Kconfig.nucleo_wb05kz @@ -0,0 +1,5 @@ +# Copyright (c) 2024 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_WB05KZ + select SOC_STM32WB05XX diff --git a/boards/st/nucleo_wb05kz/arduino_r3_connector.dtsi b/boards/st/nucleo_wb05kz/arduino_r3_connector.dtsi new file mode 100644 index 00000000000..75fb046f29f --- /dev/null +++ b/boards/st/nucleo_wb05kz/arduino_r3_connector.dtsi @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + + /* Most pins are not connected to the Arduino + * connector in default hardware configuration. + * Only the connected pins are provided here. + */ + gpio-map = <14 0 &gpiob 15 0>, /* D8 */ + <16 0 &gpioa 9 0>, /* D10 */ + <17 0 &gpioa 11 0>, /* D11 */ + <18 0 &gpioa 8 0>, /* D12 */ + <19 0 &gpiob 3 0>, /* D13 */ + <20 0 &gpiob 7 0>, /* D14 */ + <21 0 &gpiob 6 0>; /* D15 */ + }; +}; + +arduino_serial: &usart1 {}; diff --git a/boards/st/nucleo_wb05kz/board.cmake b/boards/st/nucleo_wb05kz/board.cmake new file mode 100644 index 00000000000..15bdb8e444d --- /dev/null +++ b/boards/st/nucleo_wb05kz/board.cmake @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=sw") + +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/st/nucleo_wb05kz/board.yml b/boards/st/nucleo_wb05kz/board.yml new file mode 100644 index 00000000000..645506c7953 --- /dev/null +++ b/boards/st/nucleo_wb05kz/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_wb05kz + vendor: st + socs: + - name: stm32wb05 diff --git a/boards/st/nucleo_wb05kz/doc/img/nucleo_wb05kz.webp b/boards/st/nucleo_wb05kz/doc/img/nucleo_wb05kz.webp new file mode 100644 index 00000000000..694f64a3632 Binary files /dev/null and b/boards/st/nucleo_wb05kz/doc/img/nucleo_wb05kz.webp differ diff --git a/boards/st/nucleo_wb05kz/doc/index.rst b/boards/st/nucleo_wb05kz/doc/index.rst new file mode 100644 index 00000000000..7d242549ffe --- /dev/null +++ b/boards/st/nucleo_wb05kz/doc/index.rst @@ -0,0 +1,152 @@ +.. _nucleo_wb05kz_board: + +ST Nucleo WB05KZ +################ + +Overview +******** + +The Nucleo WB05KZ board is a Bluetooth |reg| Low Energy wireless and ultra-low-power +board featuring an ARM Cortex |reg|-M0+ based STM32WB05KZV MCU, embedding a +powerful and ultra-low-power radio compliant with the Bluetooth® Low Energy +SIG specification v5.4. + +.. image:: img/nucleo_wb05kz.webp + :align: center + :alt: Nucleo WB05KZ + +More information about the board can be found on the `Nucleo WB05KZ webpage`_. + +Hardware +******** + +Nucleo WB05KZ provides the following hardware components: + +- STM32WB05KZV in VFQFPN32 package +- ARM |reg| 32-bit Cortex |reg|-M0+ CPU +- 64 MHz maximal CPU frequebct +- 192 KB Flash +- 24 KB SRAM + +More information about STM32WB05KZV can be found here: + +- `WB05KZ on www.st.com`_ +- `STM32WB05 reference manual`_ + + +Supported Features +================== + +The Zephyr ``nucleo_wb05kz`` board target supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | internal flash memory | ++-----------+------------+-------------------------------------+ + + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_wb09ke/nucleo_wb09ke_defconfig` + + +Connections and IOs +=================== + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- USART1 TX/RX : PA1/PB0 (ST-Link Virtual COM Port) +- BUTTON (B1) : PA0 +- BUTTON (B2) : PB5 +- BUTTON (B3) : PB14 +- LED (LD1/BLUE) : PB1 +- LED (LD2/GREEN) : PB4 +- LED (LD3/RED) : PB2 + +For more details, please refer to the `Nucleo WB05KZ board User Manual`_. + +Programming and Debugging +************************* + +Nucleo WB05KZ board includes an ST-LINK-V3EC embedded debug tool interface. + +Applications for the ``nucleo_w05kz`` board target can be built and flashed +in the usual way (see :ref:`build_an_application` and :ref:`application_run` +for more details). + +Flashing +======== + +The board is configured to be flashed using the west `STM32CubeProgrammer`_ runner, +so :ref:`it must be installed ` beforehand. + +Alternatively, OpenOCD can also be used to flash the board using the +``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + +Flashing an application to Nucleo WB05KZ +---------------------------------------- + +Connect the Nucleo WB05KZ to your host computer using the USB port, +then run a serial host program to connect with your Nucleo board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Now build and flash an application. Here is an example for +:zephyr:code-sample:`hello_world`. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_wb05kz + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! nucleo_wb05kz/stm32wb05 + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_wb05kz + :maybe-skip-config: + :goals: debug + +.. _`Nucleo WB05KZ webpage`: + https://www.st.com/en/evaluation-tools/nucleo-wb05kz.html + +.. _`WB05KZ on www.st.com`: + https://www.st.com/en/microcontrollers-microprocessors/stm32wb05kz.html + +.. _`STM32WB05 reference manual`: + https://www.st.com/resource/en/reference_manual/rm0529-stm32wb05xz-ultralow-power-wireless-32bit-mcu-armbased-cortexm0-with-bluetooth-low-energy-and-24-ghz-radio-solution-stmicroelectronics.pdf + +.. _`Nucleo WB05KZ board User Manual`: + https://www.st.com/resource/en/user_manual/um3343-stm32wb05-nucleo64-board-mb1801-and-mb2032-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_wb05kz/nucleo_wb05kz.dts b/boards/st/nucleo_wb05kz/nucleo_wb05kz.dts new file mode 100644 index 00000000000..f61f32e06d0 --- /dev/null +++ b/boards/st/nucleo_wb05kz/nucleo_wb05kz.dts @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include + +#include "arduino_r3_connector.dtsi" + +/ { + model = "STMicroelectronics STM32WB05KZ-NUCLEO board"; + compatible = "st,stm32wb05kz-nucleo"; + + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &usart1; + zephyr,shell-uart = &usart1; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + leds: leds { + compatible ="gpio-leds"; + blue_led_1: led_0 { + gpios = <&gpiob 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + green_led_1: led_1 { + gpios = <&gpiob 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + red_led_1: led_2 { + gpios = <&gpiob 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button_1: button_0 { + label = "SW1"; + gpios = <&gpioa 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + zephyr,code = ; + }; + user_button_2: button_1 { + label = "SW2"; + gpios = <&gpiob 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + zephyr,code = ; + }; + user_button_3: button_2 { + label = "SW3"; + gpios = <&gpiob 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + zephyr,code = ; + }; + }; + + aliases { + led0 = &blue_led_1; + led1 = &green_led_1; + led2 = &red_led_1; + sw0 = &user_button_1; + sw1 = &user_button_2; + sw2 = &user_button_3; + }; +}; + +&pwrc { + smps-mode = "RUN"; + smps-bom = <3>; +}; + +&clk_lse { + status = "okay"; +}; + +&clk_hse { + status = "okay"; +}; + +&clk_hsi { + status = "okay"; +}; + +&pll { + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + clksys-prescaler = <1>; + slow-clock = <&clk_lse>; +}; + +&usart1 { + pinctrl-0 = <&usart1_tx_pa1 &usart1_rx_pb0>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; diff --git a/boards/st/nucleo_wb05kz/nucleo_wb05kz.yaml b/boards/st/nucleo_wb05kz/nucleo_wb05kz.yaml new file mode 100644 index 00000000000..ce75ada4a46 --- /dev/null +++ b/boards/st/nucleo_wb05kz/nucleo_wb05kz.yaml @@ -0,0 +1,14 @@ +identifier: nucleo_wb05kz +name: ST Nucleo WB05KZ +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 24 +flash: 192 +supported: + - gpio + - arduino_gpio +vendor: st diff --git a/boards/st/nucleo_wb05kz/nucleo_wb05kz_defconfig b/boards/st/nucleo_wb05kz/nucleo_wb05kz_defconfig new file mode 100644 index 00000000000..0a45ef65e11 --- /dev/null +++ b/boards/st/nucleo_wb05kz/nucleo_wb05kz_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/st/nucleo_wb05kz/support/openocd.cfg b/boards/st/nucleo_wb05kz/support/openocd.cfg new file mode 100644 index 00000000000..6d294443fcf --- /dev/null +++ b/boards/st/nucleo_wb05kz/support/openocd.cfg @@ -0,0 +1,5 @@ +source [find interface/stlink-dap.cfg] + +transport select "dapdirect_swd" + +source [find target/stm32wb0x.cfg] diff --git a/boards/st/nucleo_wb09ke/Kconfig.nucleo_wb09ke b/boards/st/nucleo_wb09ke/Kconfig.nucleo_wb09ke new file mode 100644 index 00000000000..9dbfd544b27 --- /dev/null +++ b/boards/st/nucleo_wb09ke/Kconfig.nucleo_wb09ke @@ -0,0 +1,5 @@ +# Copyright (c) 2024 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_WB09KE + select SOC_STM32WB09XX diff --git a/boards/st/nucleo_wb09ke/arduino_r3_connector.dtsi b/boards/st/nucleo_wb09ke/arduino_r3_connector.dtsi new file mode 100644 index 00000000000..75fb046f29f --- /dev/null +++ b/boards/st/nucleo_wb09ke/arduino_r3_connector.dtsi @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + + /* Most pins are not connected to the Arduino + * connector in default hardware configuration. + * Only the connected pins are provided here. + */ + gpio-map = <14 0 &gpiob 15 0>, /* D8 */ + <16 0 &gpioa 9 0>, /* D10 */ + <17 0 &gpioa 11 0>, /* D11 */ + <18 0 &gpioa 8 0>, /* D12 */ + <19 0 &gpiob 3 0>, /* D13 */ + <20 0 &gpiob 7 0>, /* D14 */ + <21 0 &gpiob 6 0>; /* D15 */ + }; +}; + +arduino_serial: &usart1 {}; diff --git a/boards/st/nucleo_wb09ke/board.cmake b/boards/st/nucleo_wb09ke/board.cmake new file mode 100644 index 00000000000..15bdb8e444d --- /dev/null +++ b/boards/st/nucleo_wb09ke/board.cmake @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=sw") + +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/st/nucleo_wb09ke/board.yml b/boards/st/nucleo_wb09ke/board.yml new file mode 100644 index 00000000000..2bff9e912b5 --- /dev/null +++ b/boards/st/nucleo_wb09ke/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_wb09ke + vendor: st + socs: + - name: stm32wb09 diff --git a/boards/st/nucleo_wb09ke/doc/img/nucleo_wb09ke.webp b/boards/st/nucleo_wb09ke/doc/img/nucleo_wb09ke.webp new file mode 100644 index 00000000000..f940b29713a Binary files /dev/null and b/boards/st/nucleo_wb09ke/doc/img/nucleo_wb09ke.webp differ diff --git a/boards/st/nucleo_wb09ke/doc/index.rst b/boards/st/nucleo_wb09ke/doc/index.rst new file mode 100644 index 00000000000..9e4ce9eb728 --- /dev/null +++ b/boards/st/nucleo_wb09ke/doc/index.rst @@ -0,0 +1,152 @@ +.. _nucleo_wb09ke_board: + +ST Nucleo WB09KE +################ + +Overview +******** + +The Nucleo WB09KE board is a Bluetooth |reg| Low Energy wireless and ultra-low-power +board featuring an ARM Cortex |reg|-M0+ based STM32WB09KEV MCU, embedding a +powerful and ultra-low-power radio compliant with the Bluetooth® Low Energy +SIG specification v5.4. + +.. image:: img/nucleo_wb09ke.webp + :align: center + :alt: Nucleo WB09KE + +More information about the board can be found on the `Nucleo WB09KE webpage`_. + +Hardware +******** + +Nucleo WB09KE provides the following hardware components: + +- STM32WB09KEV in VFQFPN32 package +- ARM |reg| 32-bit Cortex |reg|-M0+ CPU +- 64 MHz maximal CPU frequebct +- 512 KB Flash +- 64 KB SRAM + +More information about STM32WB09KEV can be found here: + +- `WB09KE on www.st.com`_ +- `STM32WB09 reference manual`_ + + +Supported Features +================== + +The Zephyr ``nucleo_wb09ke`` board target supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | internal flash memory | ++-----------+------------+-------------------------------------+ + + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_wb09ke/nucleo_wb09ke_defconfig` + + +Connections and IOs +=================== + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- USART1 TX/RX : PA1/PB0 (ST-Link Virtual COM Port) +- BUTTON (B1) : PA0 +- BUTTON (B2) : PB5 +- BUTTON (B3) : PB14 +- LED (LD1/BLUE) : PB1 +- LED (LD2/GREEN) : PB4 +- LED (LD3/RED) : PB2 + +For more details, please refer to the `Nucleo WB09KE board User Manual`_. + +Programming and Debugging +************************* + +Nucleo WB09KE board includes an ST-LINK-V3EC embedded debug tool interface. + +Applications for the ``nucleo_w09ke`` board target can be built and flashed +in the usual way (see :ref:`build_an_application` and :ref:`application_run` +for more details). + +Flashing +======== + +The board is configured to be flashed using the west `STM32CubeProgrammer`_ runner, +so :ref:`it must be installed ` beforehand. + +Alternatively, OpenOCD can also be used to flash the board using the +``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + +Flashing an application to Nucleo WB09KE +---------------------------------------- + +Connect the Nucleo WB09KE to your host computer using the USB port, +then run a serial host program to connect with your Nucleo board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Now build and flash an application. Here is an example for +:zephyr:code-sample:`hello_world`. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_wb09ke + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! nucleo_wb09ke/stm32wb09 + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_wb09ke + :maybe-skip-config: + :goals: debug + +.. _`Nucleo WB09KE webpage`: + https://www.st.com/en/evaluation-tools/nucleo-wb09ke.html + +.. _`WB09KE on www.st.com`: + https://www.st.com/en/microcontrollers-microprocessors/stm32wb09ke.html + +.. _`STM32WB09 reference manual`: + https://www.st.com/resource/en/reference_manual/rm0505-stm32wb09xe-ultralow-power-wireless-32bit-mcu-armbased-cortexm0-with-bluetooth-low-energy-and-24-ghz-radio-solution-stmicroelectronics.pdf + +.. _`Nucleo WB09KE board User Manual`: + https://www.st.com/resource/en/user_manual/um3345-stm32wb09-nucleo64-board-mb1801-and-mb2032-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_wb09ke/nucleo_wb09ke.dts b/boards/st/nucleo_wb09ke/nucleo_wb09ke.dts new file mode 100644 index 00000000000..733e6c0f717 --- /dev/null +++ b/boards/st/nucleo_wb09ke/nucleo_wb09ke.dts @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include + +#include "arduino_r3_connector.dtsi" + +/ { + model = "STMicroelectronics STM32WB09KE-NUCLEO board"; + compatible = "st,stm32wb09ke-nucleo"; + + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &usart1; + zephyr,shell-uart = &usart1; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + leds: leds { + compatible ="gpio-leds"; + blue_led_1: led_0 { + gpios = <&gpiob 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + green_led_1: led_1 { + gpios = <&gpiob 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + red_led_1: led_2 { + gpios = <&gpiob 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button_1: button_0 { + label = "SW1"; + gpios = <&gpioa 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + zephyr,code = ; + }; + user_button_2: button_1 { + label = "SW2"; + gpios = <&gpiob 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + zephyr,code = ; + }; + user_button_3: button_2 { + label = "SW3"; + gpios = <&gpiob 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + zephyr,code = ; + }; + }; + + aliases { + led0 = &blue_led_1; + led1 = &green_led_1; + led2 = &red_led_1; + sw0 = &user_button_1; + sw1 = &user_button_2; + sw2 = &user_button_3; + }; +}; + +&pwrc { + smps-mode = "RUN"; + smps-bom = <3>; +}; + +&clk_lse { + status = "okay"; +}; + +&clk_hse { + status = "okay"; +}; + +&clk_hsi { + status = "okay"; +}; + +&pll { + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + clksys-prescaler = <1>; + slow-clock = <&clk_lse>; +}; + +&usart1 { + pinctrl-0 = <&usart1_tx_pa1 &usart1_rx_pb0>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; diff --git a/boards/st/nucleo_wb09ke/nucleo_wb09ke.yaml b/boards/st/nucleo_wb09ke/nucleo_wb09ke.yaml new file mode 100644 index 00000000000..908b24ea6da --- /dev/null +++ b/boards/st/nucleo_wb09ke/nucleo_wb09ke.yaml @@ -0,0 +1,14 @@ +identifier: nucleo_wb09ke +name: ST Nucleo WB09KE +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 64 +flash: 512 +supported: + - gpio + - arduino_gpio +vendor: st diff --git a/boards/st/nucleo_wb09ke/nucleo_wb09ke_defconfig b/boards/st/nucleo_wb09ke/nucleo_wb09ke_defconfig new file mode 100644 index 00000000000..0a45ef65e11 --- /dev/null +++ b/boards/st/nucleo_wb09ke/nucleo_wb09ke_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/st/nucleo_wb09ke/support/openocd.cfg b/boards/st/nucleo_wb09ke/support/openocd.cfg new file mode 100644 index 00000000000..6d294443fcf --- /dev/null +++ b/boards/st/nucleo_wb09ke/support/openocd.cfg @@ -0,0 +1,5 @@ +source [find interface/stlink-dap.cfg] + +transport select "dapdirect_swd" + +source [find target/stm32wb0x.cfg] diff --git a/boards/st/nucleo_wb55rg/board.cmake b/boards/st/nucleo_wb55rg/board.cmake index 75762ef577e..13002e7ade4 100644 --- a/boards/st/nucleo_wb55rg/board.cmake +++ b/boards/st/nucleo_wb55rg/board.cmake @@ -1,7 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 -board_runner_args(pyocd "--target=stm32wb55rgvx") + +# keep first board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +board_runner_args(pyocd "--target=stm32wb55rgvx") +# keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/st/nucleo_wb55rg/doc/nucleo_wb55rg.rst b/boards/st/nucleo_wb55rg/doc/nucleo_wb55rg.rst index 6be25936050..fb1b76e76ca 100644 --- a/boards/st/nucleo_wb55rg/doc/nucleo_wb55rg.rst +++ b/boards/st/nucleo_wb55rg/doc/nucleo_wb55rg.rst @@ -241,18 +241,27 @@ Default settings are 115200 8N1. Programming and Debugging ************************* +Nucleo WB55RG board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``nucleo_wb55rg`` board configuration can be built the usual way (see :ref:`build_an_application`). Flashing ======== -Nucleo WB55RG board includes an ST-LINK/V2-1 embedded debug tool -interface. This interface is supported by the openocd version included in the -Zephyr SDK since v0.11.0. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or pyOCD can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner pyocd -If you prefer, you can use pyocd, but it requires to enable "pack" support with -the following pyocd command: +If you prefer, you can use pyOCD, but it requires to enable "pack" support with +the following pyOCD command: .. code-block:: console @@ -265,7 +274,7 @@ Flashing an application to Nucleo WB55RG Connect the Nucleo WB55RG to your host computer using the USB port. Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board: @@ -309,3 +318,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32WB5RG reference manual: https://www.st.com/resource/en/reference_manual/dm00318631.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_wb55rg/nucleo_wb55rg.dts b/boards/st/nucleo_wb55rg/nucleo_wb55rg.dts index 4eb19294f0f..f1a0d055aa8 100644 --- a/boards/st/nucleo_wb55rg/nucleo_wb55rg.dts +++ b/boards/st/nucleo_wb55rg/nucleo_wb55rg.dts @@ -179,7 +179,7 @@ }; &adc1 { - pinctrl-0 = <&adc1_in3_pc2>; + pinctrl-0 = <&adc1_in3_pc2 &adc1_in5_pa0>; pinctrl-names = "default"; st,adc-clock-source = ; st,adc-prescaler = <4>; diff --git a/boards/st/nucleo_wb55rg/nucleo_wb55rg.yaml b/boards/st/nucleo_wb55rg/nucleo_wb55rg.yaml index a2b42575b1b..c99ca8712b4 100644 --- a/boards/st/nucleo_wb55rg/nucleo_wb55rg.yaml +++ b/boards/st/nucleo_wb55rg/nucleo_wb55rg.yaml @@ -23,4 +23,5 @@ supported: - usb_device - nvs - rtc + - usbd vendor: st diff --git a/boards/st/nucleo_wb55rg/nucleo_wb55rg_defconfig b/boards/st/nucleo_wb55rg/nucleo_wb55rg_defconfig index 75373aa997c..8b09bb0775d 100644 --- a/boards/st/nucleo_wb55rg/nucleo_wb55rg_defconfig +++ b/boards/st/nucleo_wb55rg/nucleo_wb55rg_defconfig @@ -4,9 +4,6 @@ CONFIG_SERIAL=y # enable GPIO CONFIG_GPIO=y -# enable clocks -CONFIG_CLOCK_CONTROL=y - # console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y @@ -16,6 +13,3 @@ CONFIG_ARM_MPU=y # Enable HW stack protection CONFIG_HW_STACK_PROTECTION=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_wba52cg/board.cmake b/boards/st/nucleo_wba52cg/board.cmake index 4ad8bc417ea..9c612e9d0b0 100644 --- a/boards/st/nucleo_wba52cg/board.cmake +++ b/boards/st/nucleo_wba52cg/board.cmake @@ -1,4 +1,6 @@ +# keep first board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +# keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/st/nucleo_wba52cg/doc/nucleo_wba52cg.rst b/boards/st/nucleo_wba52cg/doc/nucleo_wba52cg.rst index 16439ab6dd0..7c3257aa6fa 100644 --- a/boards/st/nucleo_wba52cg/doc/nucleo_wba52cg.rst +++ b/boards/st/nucleo_wba52cg/doc/nucleo_wba52cg.rst @@ -228,8 +228,15 @@ It could be used for flash and debug using either OpenOCD or STM32Cube ecosystem Flashing ======== -STM32CubeProgrammer is configured as flashing tool by default. -If available, OpenOCD could be used. Same process applies with both tools. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd Flashing an application to Nucleo WBA52CG ----------------------------------------- @@ -262,7 +269,9 @@ Debugging using STM32CubeIDE ---------------------------- You can debug an application using a STM32WBA compatible version of STM32CubeIDE. + For that: + - Create an empty STM32WBA project by going to File > New > STM32 project - Select your MCU, click Next, and select an Empty project. - Right click on your project name, select Debug as > Debug configurations @@ -285,3 +294,6 @@ For that: .. _OpenOCD official Github mirror: https://github.com/openocd-org/openocd/commit/870769b0ba9f4dae6ada9d8b1a40d75bd83aaa06 + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_wba52cg/nucleo_wba52cg_defconfig b/boards/st/nucleo_wba52cg/nucleo_wba52cg_defconfig index 08e07645470..8655ea99d42 100644 --- a/boards/st/nucleo_wba52cg/nucleo_wba52cg_defconfig +++ b/boards/st/nucleo_wba52cg/nucleo_wba52cg_defconfig @@ -6,9 +6,6 @@ CONFIG_SERIAL=y # enable GPIO CONFIG_GPIO=y -# Enable clock -CONFIG_CLOCK_CONTROL=y - # console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y @@ -18,6 +15,3 @@ CONFIG_ARM_MPU=y # Enable HW stack protection CONFIG_HW_STACK_PROTECTION=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_wba55cg/board.cmake b/boards/st/nucleo_wba55cg/board.cmake index 4ad8bc417ea..9c612e9d0b0 100644 --- a/boards/st/nucleo_wba55cg/board.cmake +++ b/boards/st/nucleo_wba55cg/board.cmake @@ -1,4 +1,6 @@ +# keep first board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +# keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/st/nucleo_wba55cg/doc/nucleo_wba55cg.rst b/boards/st/nucleo_wba55cg/doc/nucleo_wba55cg.rst index 70b08b6b056..c1ec0751854 100644 --- a/boards/st/nucleo_wba55cg/doc/nucleo_wba55cg.rst +++ b/boards/st/nucleo_wba55cg/doc/nucleo_wba55cg.rst @@ -196,7 +196,7 @@ To fetch Binary Blobs: .. code-block:: console - west blobs fetch stm32 + west blobs fetch hal_stm32 Connections and IOs =================== @@ -241,8 +241,15 @@ It could be used for flash and debug using either OpenOCD or STM32Cube ecosystem Flashing ======== -STM32CubeProgrammer is configured as flashing tool by default. -If available, OpenOCD could be used. Same process applies with both tools. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, openocd can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd Flashing an application to Nucleo WBA55CG ----------------------------------------- @@ -275,7 +282,9 @@ Debugging using STM32CubeIDE ---------------------------- You can debug an application using a STM32WBA compatible version of STM32CubeIDE. + For that: + - Create an empty STM32WBA project by going to File > New > STM32 project - Select your MCU, click Next, and select an Empty project. - Right click on your project name, select Debug as > Debug configurations @@ -289,3 +298,6 @@ For that: .. _OpenOCD official Github mirror: https://github.com/openocd-org/openocd/commit/870769b0ba9f4dae6ada9d8b1a40d75bd83aaa06 + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_wba55cg/nucleo_wba55cg.dts b/boards/st/nucleo_wba55cg/nucleo_wba55cg.dts index f3ba9c494e2..d6e1c1f7a5d 100644 --- a/boards/st/nucleo_wba55cg/nucleo_wba55cg.dts +++ b/boards/st/nucleo_wba55cg/nucleo_wba55cg.dts @@ -71,6 +71,7 @@ sw2 = &user_button_3; mcuboot-led0 = &blue_led_1; mcuboot-button0 = &user_button_1; + die-temp0 = &die_temp; }; }; @@ -144,13 +145,17 @@ }; &adc4 { - pinctrl-0 = <&adc4_in8_pa1>; + pinctrl-0 = <&adc4_in8_pa1 &adc4_in9_pa0>; pinctrl-names = "default"; st,adc-clock-source = ; st,adc-prescaler = <4>; status = "okay"; }; +&die_temp { + status = "okay"; +}; + stm32_lp_tick_source: &lptim1 { clocks = <&rcc STM32_CLOCK_BUS_APB7 0x00000800>, <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>; @@ -173,19 +178,15 @@ stm32_lp_tick_source: &lptim1 { }; slot0_partition: partition@10000 { label = "image-0"; - reg = <0x00010000 DT_SIZE_K(448)>; + reg = <0x00010000 DT_SIZE_K(456)>; }; - slot1_partition: partition@80000 { + slot1_partition: partition@82000 { label = "image-1"; - reg = <0x00080000 DT_SIZE_K(448)>; - }; - scratch_partition: partition@f0000 { - label = "image-scratch"; - reg = <0x000f0000 DT_SIZE_K(16)>; + reg = <0x00082000 DT_SIZE_K(448)>; }; - storage_partition: partition@f4000 { + storage_partition: partition@f2000 { label = "storage"; - reg = <0x000f4000 DT_SIZE_K(48)>; + reg = <0x000f2000 DT_SIZE_K(56)>; }; }; }; diff --git a/boards/st/nucleo_wba55cg/nucleo_wba55cg_defconfig b/boards/st/nucleo_wba55cg/nucleo_wba55cg_defconfig index 98bb440f4ab..0b1968e03d3 100644 --- a/boards/st/nucleo_wba55cg/nucleo_wba55cg_defconfig +++ b/boards/st/nucleo_wba55cg/nucleo_wba55cg_defconfig @@ -7,9 +7,6 @@ CONFIG_SERIAL=y # enable GPIO CONFIG_GPIO=y -# Enable clock -CONFIG_CLOCK_CONTROL=y - # console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y @@ -20,8 +17,5 @@ CONFIG_ARM_MPU=y # Enable HW stack protection CONFIG_HW_STACK_PROTECTION=y -# enable pin controller -CONFIG_PINCTRL=y - # Enable the internal SMPS regulator CONFIG_POWER_SUPPLY_DIRECT_SMPS=y diff --git a/boards/st/nucleo_wl55jc/board.cmake b/boards/st/nucleo_wl55jc/board.cmake index d1ca609778e..716846e4923 100644 --- a/boards/st/nucleo_wl55jc/board.cmake +++ b/boards/st/nucleo_wl55jc/board.cmake @@ -1,5 +1,8 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") + +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) \ No newline at end of file diff --git a/boards/st/nucleo_wl55jc/doc/nucleo_wl55jc.rst b/boards/st/nucleo_wl55jc/doc/nucleo_wl55jc.rst index 50f7c63d9e0..98ce41d5877 100644 --- a/boards/st/nucleo_wl55jc/doc/nucleo_wl55jc.rst +++ b/boards/st/nucleo_wl55jc/doc/nucleo_wl55jc.rst @@ -258,16 +258,23 @@ Default settings are 115200 8N1. Programming and Debugging ************************* +Nucleo WL55JC board includes an STLINK-V3 embedded debug tool interface. + Applications for the ``nucleo_wl55jc`` board configuration can be built the usual way (see :ref:`build_an_application`). Flashing ======== -Nucleo WL55JC board includes an STLINK-V3 embedded debug tool -interface. This interface is supported by the openocd version included in the -Zephyr SDK since v0.11.0. -You can also choose the ``stm32cubeprogrammer`` runner. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd Flashing an application to Nucleo WL55JC @@ -275,7 +282,7 @@ Flashing an application to Nucleo WL55JC Connect the Nucleo WL55JC to your host computer using the USB port. Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board: @@ -328,3 +335,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32WL55JC reference manual: https://www.st.com/resource/en/reference_manual/dm00451556-stm32wl5x-advanced-armbased-32bit-mcus-with-subghz-radio-solution-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_wl55jc/nucleo_wl55jc.dts b/boards/st/nucleo_wl55jc/nucleo_wl55jc.dts index 6e37b1c1485..98fcc7057ae 100644 --- a/boards/st/nucleo_wl55jc/nucleo_wl55jc.dts +++ b/boards/st/nucleo_wl55jc/nucleo_wl55jc.dts @@ -147,7 +147,7 @@ stm32_lp_tick_source: &lptim1 { &adc1 { - pinctrl-0 = <&adc_in5_pb1>; + pinctrl-0 = <&adc_in5_pb1 &adc_in0_pb13>; pinctrl-names = "default"; st,adc-clock-source = ; st,adc-prescaler = <4>; diff --git a/boards/st/nucleo_wl55jc/nucleo_wl55jc_defconfig b/boards/st/nucleo_wl55jc/nucleo_wl55jc_defconfig index 0d6dc9f80d3..8b09bb0775d 100644 --- a/boards/st/nucleo_wl55jc/nucleo_wl55jc_defconfig +++ b/boards/st/nucleo_wl55jc/nucleo_wl55jc_defconfig @@ -4,9 +4,6 @@ CONFIG_SERIAL=y # enable GPIO CONFIG_GPIO=y -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - # console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y @@ -16,6 +13,3 @@ CONFIG_ARM_MPU=y # Enable HW stack protection CONFIG_HW_STACK_PROTECTION=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/sensortile_box/doc/index.rst b/boards/st/sensortile_box/doc/index.rst index db9ba488dc1..d582d3f2ee1 100644 --- a/boards/st/sensortile_box/doc/index.rst +++ b/boards/st/sensortile_box/doc/index.rst @@ -185,7 +185,7 @@ You should see following confirmation on your Linux host: usb 2-2: SerialNumber: 204A325D574D You can build and flash the provided sample application -(:ref:`sensortile_box sensors`) that reads sensors data and outputs +(:zephyr:code-sample:`sensortile_box_sensors`) that reads sensors data and outputs values on the console. References diff --git a/boards/st/sensortile_box/sensortile_box.dts b/boards/st/sensortile_box/sensortile_box.dts index 70a0b4f9007..9e7acee2e5a 100644 --- a/boards/st/sensortile_box/sensortile_box.dts +++ b/boards/st/sensortile_box/sensortile_box.dts @@ -191,7 +191,6 @@ lis2mdl: lis2mdl@0 { compatible = "st,lis2mdl"; spi-max-frequency = <1000000>; - spi-full-duplex; reg = <0>; }; }; diff --git a/boards/st/sensortile_box/sensortile_box_defconfig b/boards/st/sensortile_box/sensortile_box_defconfig index 4ba8077edd6..165b1944f31 100644 --- a/boards/st/sensortile_box/sensortile_box_defconfig +++ b/boards/st/sensortile_box/sensortile_box_defconfig @@ -6,9 +6,6 @@ CONFIG_SERIAL=y # Enable GPIO CONFIG_GPIO=y -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - # Console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y @@ -18,6 +15,3 @@ CONFIG_ARM_MPU=y # Enable HW stack protection CONFIG_HW_STACK_PROTECTION=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/sensortile_box_pro/CMakeLists.txt b/boards/st/sensortile_box_pro/CMakeLists.txt deleted file mode 100644 index f2a184ea87f..00000000000 --- a/boards/st/sensortile_box_pro/CMakeLists.txt +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library_sources(board.c) diff --git a/boards/st/sensortile_box_pro/Kconfig b/boards/st/sensortile_box_pro/Kconfig new file mode 100644 index 00000000000..d8dc05c44f6 --- /dev/null +++ b/boards/st/sensortile_box_pro/Kconfig @@ -0,0 +1,12 @@ +# SENSORTILE_BOX_PRO board configuration + +# Copyright (c) 2024 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_SENSORTILE_BOX_PRO + +config BOARD_SERIAL_BACKEND_CDC_ACM + bool "Use USB CDC as serial console backend" + default y + +endif # BOARD_SENSORTILE_BOX_PRO diff --git a/boards/st/sensortile_box_pro/Kconfig.defconfig b/boards/st/sensortile_box_pro/Kconfig.defconfig index caa346b0075..fb701bd4265 100644 --- a/boards/st/sensortile_box_pro/Kconfig.defconfig +++ b/boards/st/sensortile_box_pro/Kconfig.defconfig @@ -26,6 +26,36 @@ config SPI_STM32_INTERRUPT default y depends on SPI +if BOARD_SERIAL_BACKEND_CDC_ACM + +config USB_DEVICE_STACK + default y + +config USB_CDC_ACM + default SERIAL + +config USB_DEVICE_INITIALIZE_AT_BOOT + default y if CONSOLE + +config SHELL_BACKEND_SERIAL_CHECK_DTR + default SHELL + depends on UART_LINE_CTRL + +config UART_LINE_CTRL + default SHELL + +config USB_DEVICE_REMOTE_WAKEUP + default n + +config USB_DEVICE_VID + default 0x0483 + +config USB_DEVICE_PID + default 0x5740 + +config USB_DEVICE_PRODUCT + default "Zephyr CDC SensorTile.box PRO" + if LOG # Logger cannot use itself to log @@ -35,4 +65,11 @@ endchoice endif # LOG +endif # BOARD_SERIAL_BACKEND_CDC_ACM + +DT_CHOSEN_ZEPHYR_CONSOLE := zephyr,console + +config UART_CONSOLE + default y if $(dt_chosen_enabled,$(DT_CHOSEN_ZEPHYR_CONSOLE)) && CONSOLE + endif # BOARD_SENSORTILE_BOX_PRO diff --git a/boards/st/sensortile_box_pro/board.c b/boards/st/sensortile_box_pro/board.c deleted file mode 100644 index c19d0abe3da..00000000000 --- a/boards/st/sensortile_box_pro/board.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2023 STMicroelectronics - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_CONSOLE) && defined(CONFIG_UART_CONSOLE) -#if DT_NODE_HAS_COMPAT(DT_CHOSEN(zephyr_console), zephyr_cdc_acm_uart) -/* - * Enable console on USB CDC_ACM - */ -static int sensortile_box_pro_usb_console_init(void) -{ - const struct device *const dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_console)); - - if (!device_is_ready(dev)) { - return -ENODEV; - } - return usb_enable(NULL); -} - -/* needs to be done at Application */ -SYS_INIT(sensortile_box_pro_usb_console_init, APPLICATION, - CONFIG_KERNEL_INIT_PRIORITY_DEVICE); -#endif /* DT_NODE_HAS_COMPAT(DT_CHOSEN(zephyr_console), zephyr_cdc_acm_uart) */ -#endif /* defined(CONFIG_CONSOLE) && defined (CONFIG_UART_CONSOLE) */ diff --git a/boards/st/sensortile_box_pro/doc/index.rst b/boards/st/sensortile_box_pro/doc/index.rst index e98ddace1bb..eaad9150d70 100644 --- a/boards/st/sensortile_box_pro/doc/index.rst +++ b/boards/st/sensortile_box_pro/doc/index.rst @@ -163,8 +163,6 @@ Motion and environmental sensors (`lps22df datasheet`_) - **LIS2DU12** 3-axis accelerometer (`lis2du12 datasheet`_) - - **HTS221** Humidity sensor - (`hts221 datasheet`_) - **STTS22H** Digital temperature sensor (`stts22hh datasheet`_) - **MP23db01HP** Microphone / audio sensor @@ -219,61 +217,44 @@ Console There are two possible options for Zephyr console output: -- through UART4 which is available on SWD connector (JP2). In this case a JTAG adapter - can be used to connect SensorTile.box PRO and have both SWD and console lines available. - - To enable console and shell over UART - - - switch the console lines from cdc_acm to uart4 - (:file:`boards/st/sensortile_box_pro/sensortile_box_pro.dts`) - - - comment out the USB configuration macros - (:file:`boards/st/sensortile_box_pro/sensortile_box_pro_defconfig`) +- through USB as USB CDC/ACM class. This is the default case present in the board dts file + and is enabled by :kconfig:option:`CONFIG_BOARD_SERIAL_BACKEND_CDC_ACM`. .. code-block:: dts :caption: boards/st/sensortile_box_pro/sensortile_box_pro.dts / { chosen { - zephyr,console = &uart4; - zephyr,shell-uart = &uart4; - //zephyr,console = &cdc_acm_uart0; - //zephyr,shell-uart = &cdc_acm_uart0; + zephyr,console = &cdc_acm_uart0; }; }; -.. code-block:: Kconfig - :caption: boards/st/sensortile_box_pro/sensortile_box_pro_defconfig + &zephyr_udc0 { + cdc_acm_uart0: cdc_acm_uart0 { + compatible = "zephyr,cdc-acm-uart"; + }; + }; - # Comment out following USB config lines when - # switching console to UART - #CONFIG_USB_DEVICE_STACK=y - #CONFIG_USB_DEVICE_VID=0x0483 - #CONFIG_USB_DEVICE_PID=0x1235 - #CONFIG_USB_DEVICE_PRODUCT="Zephyr CDC SensorTile.box PRO" - #CONFIG_USB_CDC_ACM_LOG_LEVEL_OFF=y - #CONFIG_USB_DEVICE_INITIALIZE_AT_BOOT=n +- through UART4 which is available on SWD connector (JP2). In this case a JTAG adapter + can be used to connect SensorTile.box PRO and have both SWD and console lines available. -- through USB as USB CDC/ACM class. This is the default case present in the board dts file. + To enable console and shell over UART: + + - in your prj.conf, override the board's default configuration by setting :code:`CONFIG_BOARD_SERIAL_BACKEND_CDC_ACM=n` + + - add an overlay file named ``.overlay``: .. code-block:: dts - :caption: boards/st/sensortile_box_pro/sensortile_box_pro.dts / { chosen { - zephyr,console = &cdc_acm_uart0; - }; - }; - - &zephyr_udc0 { - cdc_acm_uart0: cdc_acm_uart0 { - compatible = "zephyr,cdc-acm-uart"; + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; }; }; - Console default settings are 115200 8N1. Programming and Debugging @@ -341,7 +322,7 @@ You should see following confirmation on your Linux host: usb 2-2: SerialNumber: 204A325D574D You can build and flash the provided sample application -(:ref:`sensortile_box_pro_sample_sensors`) that reads sensors data and outputs +(:zephyr:code-sample:`sensortile_box_pro_sensors`) that reads sensors data and outputs values on the console. References @@ -370,9 +351,6 @@ References .. _lis2du12 datasheet: https://www.st.com/en/mems-and-sensors/lis2du12.html -.. _hts221 datasheet: - https://www.st.com/en/mems-and-sensors/hts221.html - .. _stts22hh datasheet: https://www.st.com/en/mems-and-sensors/stts22h.html diff --git a/boards/st/sensortile_box_pro/sensortile_box_pro.dts b/boards/st/sensortile_box_pro/sensortile_box_pro.dts index 06185c32d40..7014fd86a7e 100644 --- a/boards/st/sensortile_box_pro/sensortile_box_pro.dts +++ b/boards/st/sensortile_box_pro/sensortile_box_pro.dts @@ -14,15 +14,6 @@ compatible = "st,sensortile-box-pro"; chosen { - /* - * By default, Zephyr console and shell are assigned to - * USB CDC/ACM. To enable console and shell over UART, - * uncomment following lines and set the correct config - * in sensortile_box_pro_defconfig. - * - * zephyr,console = &uart4; - * zephyr,shell-uart = &uart4; - */ zephyr,console = &cdc_acm_uart0; zephyr,shell-uart = &cdc_acm_uart0; zephyr,bt-c2h-uart = &cdc_acm_uart0; @@ -237,13 +228,6 @@ stm32_lp_tick_source: &lptim1 { status = "okay"; clock-frequency = ; - hts221@5f { - compatible = "st,hts221"; - reg = <0x5f>; - drdy-gpios = <&gpioe 11 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - lps22df@5d { compatible = "st,lps22df"; reg = <0x5d>; diff --git a/boards/st/sensortile_box_pro/sensortile_box_pro_defconfig b/boards/st/sensortile_box_pro/sensortile_box_pro_defconfig index a47f372d784..7481455c07a 100644 --- a/boards/st/sensortile_box_pro/sensortile_box_pro_defconfig +++ b/boards/st/sensortile_box_pro/sensortile_box_pro_defconfig @@ -9,23 +9,6 @@ CONFIG_HW_STACK_PROTECTION=y # enable GPIO CONFIG_GPIO=y -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# config USB and USB console +# Enable console CONFIG_SERIAL=y CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_LINE_CTRL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Comment out following USB config lines when -# switching console to UART -CONFIG_USB_DEVICE_STACK=y -CONFIG_USB_DEVICE_VID=0x0483 -CONFIG_USB_DEVICE_PID=0x1235 -CONFIG_USB_DEVICE_PRODUCT="Zephyr CDC SensorTile.box PRO" -CONFIG_USB_DEVICE_INITIALIZE_AT_BOOT=n - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/st25dv_mb1283_disco/docs/index.rst b/boards/st/st25dv_mb1283_disco/docs/index.rst index 03acec44fc5..1fef60ebf63 100644 --- a/boards/st/st25dv_mb1283_disco/docs/index.rst +++ b/boards/st/st25dv_mb1283_disco/docs/index.rst @@ -101,7 +101,7 @@ Flashing an application to ST25DV Discovery First, connect the ST25DV Discovery kit to your host computer using the USB port to prepare it for flashing. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -124,7 +124,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/st25dv_mb1283_disco/st25dv_mb1283_disco_defconfig b/boards/st/st25dv_mb1283_disco/st25dv_mb1283_disco_defconfig index e8b83db5fbb..28c590286cc 100644 --- a/boards/st/st25dv_mb1283_disco/st25dv_mb1283_disco_defconfig +++ b/boards/st/st25dv_mb1283_disco/st25dv_mb1283_disco_defconfig @@ -13,9 +13,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/st25dv_mb1283_disco/support/openocd.cfg b/boards/st/st25dv_mb1283_disco/support/openocd.cfg index 72b4cd7492a..5d6a3772c5c 100644 --- a/boards/st/st25dv_mb1283_disco/support/openocd.cfg +++ b/boards/st/st25dv_mb1283_disco/support/openocd.cfg @@ -4,7 +4,7 @@ transport select hla_swd source [find target/stm32f4x.cfg] -adapter_khz 1000 +adapter speed 1000 reset_config srst_only diff --git a/boards/st/steval_fcu001v1/doc/index.rst b/boards/st/steval_fcu001v1/doc/index.rst index a76f99c6e01..f10c0300957 100644 --- a/boards/st/steval_fcu001v1/doc/index.rst +++ b/boards/st/steval_fcu001v1/doc/index.rst @@ -123,7 +123,7 @@ program to connect with your steval_fcu001v1 via the FT232 board: $ minicom -D /dev/ttyUSB0 -Now build and flash an application. Here is an example for :ref:`hello_world` +Now build and flash an application. Here is an example for :zephyr:code-sample:`hello_world` .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -140,7 +140,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/steval_fcu001v1/steval_fcu001v1_defconfig b/boards/st/steval_fcu001v1/steval_fcu001v1_defconfig index e4d07bf3184..7574265d497 100644 --- a/boards/st/steval_fcu001v1/steval_fcu001v1_defconfig +++ b/boards/st/steval_fcu001v1/steval_fcu001v1_defconfig @@ -11,9 +11,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/steval_stwinbx1/CMakeLists.txt b/boards/st/steval_stwinbx1/CMakeLists.txt deleted file mode 100644 index f2a184ea87f..00000000000 --- a/boards/st/steval_stwinbx1/CMakeLists.txt +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library_sources(board.c) diff --git a/boards/st/steval_stwinbx1/Kconfig b/boards/st/steval_stwinbx1/Kconfig new file mode 100644 index 00000000000..520aea81d16 --- /dev/null +++ b/boards/st/steval_stwinbx1/Kconfig @@ -0,0 +1,12 @@ +# STEVAL_STWINBX1 Development kit board configuration + +# Copyright (c) 2024 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_STEVAL_STWINBX1 + +config BOARD_SERIAL_BACKEND_CDC_ACM + bool "Use USB CDC as serial console backend" + default y + +endif # BOARD_STEVAL_STWINBX1 diff --git a/boards/st/steval_stwinbx1/Kconfig.defconfig b/boards/st/steval_stwinbx1/Kconfig.defconfig index 594ebede5a7..657170dd303 100644 --- a/boards/st/steval_stwinbx1/Kconfig.defconfig +++ b/boards/st/steval_stwinbx1/Kconfig.defconfig @@ -26,6 +26,36 @@ config SPI_STM32_INTERRUPT default y depends on SPI +if BOARD_SERIAL_BACKEND_CDC_ACM + +config USB_DEVICE_STACK + default y + +config USB_CDC_ACM + default SERIAL + +config USB_DEVICE_INITIALIZE_AT_BOOT + default y if CONSOLE + +config SHELL_BACKEND_SERIAL_CHECK_DTR + default SHELL + depends on UART_LINE_CTRL + +config UART_LINE_CTRL + default SHELL + +config USB_DEVICE_REMOTE_WAKEUP + default n + +config USB_DEVICE_VID + default 0x0483 + +config USB_DEVICE_PID + default 0x5740 + +config USB_DEVICE_PRODUCT + default "Zephyr CDC STEval-STWinbx1" + if LOG # Logger cannot use itself to log @@ -35,4 +65,11 @@ endchoice endif # LOG +endif # BOARD_SERIAL_BACKEND_CDC_ACM + +DT_CHOSEN_ZEPHYR_CONSOLE := zephyr,console + +config UART_CONSOLE + default y if $(dt_chosen_enabled,$(DT_CHOSEN_ZEPHYR_CONSOLE)) && CONSOLE + endif # BOARD_STEVAL_STWINBX1 diff --git a/boards/st/steval_stwinbx1/board.c b/boards/st/steval_stwinbx1/board.c deleted file mode 100644 index 1d98da4aba0..00000000000 --- a/boards/st/steval_stwinbx1/board.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2024 STMicroelectronics - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_CONSOLE) && defined(CONFIG_UART_CONSOLE) -#if DT_NODE_HAS_COMPAT(DT_CHOSEN(zephyr_console), zephyr_cdc_acm_uart) -/* - * Enable console on USB CDC_ACM - */ -static int steval_stwinbx1_usb_console_init(void) -{ - const struct device *const dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_console)); - - if (!device_is_ready(dev)) { - return -ENODEV; - } - return (usb_enable(NULL)); -} - -/* needs to be done at Application */ -SYS_INIT(steval_stwinbx1_usb_console_init, APPLICATION, - CONFIG_KERNEL_INIT_PRIORITY_DEVICE); -#endif /* DT_NODE_HAS_COMPAT(DT_CHOSEN(zephyr_console), zephyr_cdc_acm_uart) */ -#endif /* defined(CONFIG_CONSOLE) && defined (CONFIG_UART_CONSOLE) */ diff --git a/boards/st/steval_stwinbx1/board.cmake b/boards/st/steval_stwinbx1/board.cmake index 7b41b6115ca..1335413cee7 100644 --- a/boards/st/steval_stwinbx1/board.cmake +++ b/boards/st/steval_stwinbx1/board.cmake @@ -13,6 +13,7 @@ board_runner_args(openocd "--tcl-port=6666") board_runner_args(openocd --cmd-pre-init "gdb_report_data_abort enable") board_runner_args(openocd "--no-halt") +# keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/st/steval_stwinbx1/doc/index.rst b/boards/st/steval_stwinbx1/doc/index.rst index 367de5d4373..cd0e2469484 100644 --- a/boards/st/steval_stwinbx1/doc/index.rst +++ b/boards/st/steval_stwinbx1/doc/index.rst @@ -236,59 +236,44 @@ Console There are two possible options for Zephyr console output: -- through USART2 which is available on SWD connector (CN4). In this case a JTAG adapter - can be used to connect STEVAL-STWINBX1 and have both SWD and console lines available. - - To enable console and shell over UART - - - switch the console lines from cdc_acm to uart4 - (:file:`boards/st/steval_stwinbx1/steval_stwinbx1.dts`) - - comment out the USB configuration macros - (:file:`boards/st/steval_stwinbx1/steval_stwinbx1_defconfig`) +- through USB as USB CDC/ACM class. This is the default case present in the board dts file + and is enabled by :kconfig:option:`CONFIG_BOARD_SERIAL_BACKEND_CDC_ACM`. .. code-block:: dts :caption: boards/st/steval_stwinbx1/steval_stwinbx1.dts / { chosen { - zephyr,console = &usart2; - zephyr,shell-uart = &usart2; - //zephyr,console = &cdc_acm_uart0; - //zephyr,shell-uart = &cdc_acm_uart0; + zephyr,console = &cdc_acm_uart0; }; }; -.. code-block:: Kconfig - :caption: boards/st/steval_stwinbx1/steval_stwinbx1_defconfig + &zephyr_udc0 { + cdc_acm_uart0: cdc_acm_uart0 { + compatible = "zephyr,cdc-acm-uart"; + }; + }; + +- through USART2 which is available on SWD connector (CN4). In this case a JTAG adapter + can be used to connect STEVAL-STWINBX1 and have both SWD and console lines available. + + To enable console and shell over UART: - # Comment out following USB config lines when - # switching console to UART - #CONFIG_USB_DEVICE_STACK=y - #CONFIG_USB_DEVICE_VID=0x0483 - #CONFIG_USB_DEVICE_PID=0x5740 - #CONFIG_USB_DEVICE_PRODUCT="Zephyr CDC STEval-STWinbx1" - #CONFIG_USB_DEVICE_INITIALIZE_AT_BOOT=n + - in your prj.conf, override the board's default configuration by setting :code:`CONFIG_BOARD_SERIAL_BACKEND_CDC_ACM=n` -- through USB as USB CDC/ACM class. This is the default case present in the board dts file. + - add an overlay file named ``.overlay``: .. code-block:: dts - :caption: boards/st/steval_stwinbx1/steval_stwinbx1.dts / { chosen { - zephyr,console = &cdc_acm_uart0; - }; - }; - - &zephyr_udc0 { - cdc_acm_uart0: cdc_acm_uart0 { - compatible = "zephyr,cdc-acm-uart"; + zephyr,console = &usart2; + zephyr,shell-uart = &usart2; }; }; - Console default settings are 115200 8N1. Programming and Debugging @@ -376,10 +361,9 @@ You should see the following confirmation on your Linux host: usb 3-1: Manufacturer: STMicroelectronics usb 3-1: SerialNumber: 207136863530 -.. You can build and flash the provided sample application -.. (:ref:`sensortile_box_pro_sample_sensors`) that reads sensors data and outputs -.. values on the console. - +You can build and flash the provided sample application +(:zephyr:code-sample:`stwinbx1_sensors`) that reads sensors data and outputs +values on the console. .. _STEVAL-STWINBX1 Development kit website: https://www.st.com/en/evaluation-tools/steval-stwinbx1.html diff --git a/boards/st/steval_stwinbx1/steval_stwinbx1.dts b/boards/st/steval_stwinbx1/steval_stwinbx1.dts index 4debd8cc5c1..040452e91b0 100644 --- a/boards/st/steval_stwinbx1/steval_stwinbx1.dts +++ b/boards/st/steval_stwinbx1/steval_stwinbx1.dts @@ -14,18 +14,6 @@ compatible = "st,steval_stwinbx1"; chosen { - /* - * By default, Zephyr console and shell are assigned to - * USB CDC/ACM. To enable console and shell over UART, - * uncomment the 2 following lines and set the correct - * config in steval_stwinbx1_defconfig. - */ - /* zephyr,console = &usart2; */ - /* zephyr,shell-uart = &usart2; */ - /* - * To enable console and shell over UART, - * comment the 2 following lines - */ zephyr,console = &cdc_acm_uart0; zephyr,shell-uart = &cdc_acm_uart0; @@ -161,6 +149,39 @@ stm32_lp_tick_source: &lptim1 { status = "okay"; }; +&spi2 { + pinctrl-0 = <&spi2_sck_pi1 &spi2_miso_pd3 &spi2_mosi_pi3>; + pinctrl-names = "default"; + status = "okay"; + + cs-gpios = <&gpioh 6 GPIO_ACTIVE_LOW>, + <&gpioh 15 GPIO_ACTIVE_LOW>, + <&gpioi 7 GPIO_ACTIVE_LOW>; + iis2dlpc: iis2dlpc@0 { + compatible = "st,iis2dlpc"; + spi-max-frequency = ; + reg = <0>; + drdy-gpios = <&gpiof 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; + drdy-int = <1>; + }; + + ism330dhcx: ism330dhcx@1 { + compatible = "st,ism330dhcx"; + spi-max-frequency = ; + reg = <1>; + drdy-gpios = <&gpiob 8 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; + int-pin = <1>; + }; + + iis2iclx: iis2iclx@2 { + compatible = "st,iis2iclx"; + spi-max-frequency = ; + reg = <2>; + drdy-gpios = <&gpiof 11 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; + int-pin = <2>; + }; +}; + &spi3 { pinctrl-0 = <&spi3_sck_pg9 &spi3_miso_pb4 &spi3_mosi_pb5>; pinctrl-names = "default"; @@ -190,6 +211,13 @@ stm32_lp_tick_source: &lptim1 { int-gpios = <&gpiof 5 GPIO_ACTIVE_HIGH>; status = "okay"; }; + + iis2mdc@1e { + compatible = "st,iis2mdc"; + reg = <0x1e>; + drdy-gpios = <&gpiof 9 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; }; &timers5 { diff --git a/boards/st/steval_stwinbx1/steval_stwinbx1_defconfig b/boards/st/steval_stwinbx1/steval_stwinbx1_defconfig index c432b5184df..52156512243 100644 --- a/boards/st/steval_stwinbx1/steval_stwinbx1_defconfig +++ b/boards/st/steval_stwinbx1/steval_stwinbx1_defconfig @@ -10,23 +10,6 @@ CONFIG_HW_STACK_PROTECTION=y CONFIG_GPIO=y CONFIG_GPIO_HOGS=y -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# config USB and USB console +# Enable console CONFIG_SERIAL=y CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_LINE_CTRL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Comment out following USB config lines when -# switching console to UART -CONFIG_USB_DEVICE_STACK=y -CONFIG_USB_DEVICE_VID=0x0483 -CONFIG_USB_DEVICE_PID=0x5740 -CONFIG_USB_DEVICE_PRODUCT="Zephyr CDC STEval-STWinbx1" -CONFIG_USB_DEVICE_INITIALIZE_AT_BOOT=n - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm3210c_eval/doc/index.rst b/boards/st/stm3210c_eval/doc/index.rst index 383a0e2f5fb..117e378b659 100644 --- a/boards/st/stm3210c_eval/doc/index.rst +++ b/boards/st/stm3210c_eval/doc/index.rst @@ -145,7 +145,7 @@ example, on Linux: $ minicom -D /dev/ttyACM0 You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm3210c_eval/stm3210c_eval_defconfig b/boards/st/stm3210c_eval/stm3210c_eval_defconfig index 5af8b611205..3b901615252 100644 --- a/boards/st/stm3210c_eval/stm3210c_eval_defconfig +++ b/boards/st/stm3210c_eval/stm3210c_eval_defconfig @@ -12,6 +12,3 @@ CONFIG_GPIO=y # RCC Controller CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32373c_eval/board.cmake b/boards/st/stm32373c_eval/board.cmake index 8bcf43ee8c7..c4303e2c481 100644 --- a/boards/st/stm32373c_eval/board.cmake +++ b/boards/st/stm32373c_eval/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F373VC" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32373c_eval/stm32373c_eval_defconfig b/boards/st/stm32373c_eval/stm32373c_eval_defconfig index 579a5c3fc4e..ce451a733e4 100644 --- a/boards/st/stm32373c_eval/stm32373c_eval_defconfig +++ b/boards/st/stm32373c_eval/stm32373c_eval_defconfig @@ -16,9 +16,3 @@ CONFIG_UART_CONSOLE=y # GPIO Controller CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32c0116_dk/board.cmake b/boards/st/stm32c0116_dk/board.cmake index 92d0dbb2924..f1142b2c248 100644 --- a/boards/st/stm32c0116_dk/board.cmake +++ b/boards/st/stm32c0116_dk/board.cmake @@ -1,8 +1,10 @@ # Copyright (c) 2024 Kickmaker # SPDX-License-Identifier: Apache-2.0 -board_runner_args(jlink "--device=STM32C011F6" "--speed=4000") +# keep first board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +board_runner_args(jlink "--device=STM32C011F6" "--speed=4000") -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +# keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32c0116_dk/doc/index.rst b/boards/st/stm32c0116_dk/doc/index.rst index a59086c2930..52e3c24ef20 100644 --- a/boards/st/stm32c0116_dk/doc/index.rst +++ b/boards/st/stm32c0116_dk/doc/index.rst @@ -106,6 +106,8 @@ The STM32C0116 Discovery board is configured as follows: Programming and Debugging ************************* +STM32C0116-DK Discovery kit includes an ST-LINK/V2 embedded debug tool interface. + Applications for the ``stm32c0116_dk`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -113,7 +115,15 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -STM32C0116-DK Discovery kit includes an ST-LINK/V2 embedded debug tool interface. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner jlink Flashing an application to STM32C0116-DK ------------------------------------------- @@ -121,7 +131,7 @@ Flashing an application to STM32C0116-DK First, connect the STM32C0116 Discovery kit to your host computer using the USB port to prepare it for flashing. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -152,3 +162,6 @@ You should see the following message on the console: .. _STM32C0x1 reference manual: https://www.st.com/resource/en/reference_manual/rm0490-stm32c0x1-advanced-armbased-64bit-mcus-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/stm32c0116_dk/stm32c0116_dk.dts b/boards/st/stm32c0116_dk/stm32c0116_dk.dts index f9791268886..79b4db1fa25 100644 --- a/boards/st/stm32c0116_dk/stm32c0116_dk.dts +++ b/boards/st/stm32c0116_dk/stm32c0116_dk.dts @@ -53,7 +53,7 @@ select_key { press-thresholds-mv = <0>; - zephyr,code = ; + zephyr,code = ; }; left_key { diff --git a/boards/st/stm32c0116_dk/stm32c0116_dk_defconfig b/boards/st/stm32c0116_dk/stm32c0116_dk_defconfig index 247a0d666a5..2ba52a9856f 100644 --- a/boards/st/stm32c0116_dk/stm32c0116_dk_defconfig +++ b/boards/st/stm32c0116_dk/stm32c0116_dk_defconfig @@ -11,9 +11,3 @@ CONFIG_UART_CONSOLE=y # GPIO Controller CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32f072_eval/board.cmake b/boards/st/stm32f072_eval/board.cmake index 18a9499d595..f49b17d83bb 100644 --- a/boards/st/stm32f072_eval/board.cmake +++ b/boards/st/stm32f072_eval/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F072VB" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32f072_eval/doc/index.rst b/boards/st/stm32f072_eval/doc/index.rst index 998670d4cf2..b1bb7b0b5ac 100644 --- a/boards/st/stm32f072_eval/doc/index.rst +++ b/boards/st/stm32f072_eval/doc/index.rst @@ -142,6 +142,8 @@ Default settings are 115200 8N1. Programming and Debugging ************************* +STM32F072-EVAL Discovery kit includes an ST-LINK/V2 embedded debug tool interface. + Applications for the ``stm32f072_eval`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -149,8 +151,16 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -STM32F072-EVAL Discovery kit includes an ST-LINK/V2 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to STM32F072-EVAL ------------------------------------------- @@ -182,3 +192,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32F072 reference manual: https://www.st.com/resource/en/reference_manual/dm00031936.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/stm32f072_eval/stm32f072_eval_defconfig b/boards/st/stm32f072_eval/stm32f072_eval_defconfig index 06e8a32bb1f..e3d8f7bb3d2 100644 --- a/boards/st/stm32f072_eval/stm32f072_eval_defconfig +++ b/boards/st/stm32f072_eval/stm32f072_eval_defconfig @@ -9,9 +9,3 @@ CONFIG_UART_CONSOLE=y # GPIO Controller CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32f072b_disco/board.cmake b/boards/st/stm32f072b_disco/board.cmake index b255d56ff7d..136bd345f6a 100644 --- a/boards/st/stm32f072b_disco/board.cmake +++ b/boards/st/stm32f072b_disco/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F072RB" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32f072b_disco/doc/index.rst b/boards/st/stm32f072b_disco/doc/index.rst index d09a8fc47df..6f97341d2b3 100644 --- a/boards/st/stm32f072b_disco/doc/index.rst +++ b/boards/st/stm32f072b_disco/doc/index.rst @@ -144,6 +144,8 @@ is assigned to UART 1. Default settings are 115200 8N1. Programming and Debugging ************************* +STM32F072B-DISCO board includes an ST-LINK/V2 embedded debug tool interface. + Applications for the ``stm32f072b_disco`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -151,9 +153,16 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -STM32F072B-DISCO board includes an ST-LINK/V2 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to STM32F072B-DISCO ------------------------------------------- @@ -161,7 +170,7 @@ Flashing an application to STM32F072B-DISCO First, connect the STM32F072B-DISCO Discovery kit to your host computer using the USB port to prepare it for flashing. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -189,7 +198,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -216,3 +225,6 @@ References .. _SK Pang CAN breakout board: https://www.skpang.co.uk/products/can-bus-can-fd-breakout-board-5v-supply-and-5v-logic + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/stm32f072b_disco/stm32f072b_disco_defconfig b/boards/st/stm32f072b_disco/stm32f072b_disco_defconfig index 06e8a32bb1f..e3d8f7bb3d2 100644 --- a/boards/st/stm32f072b_disco/stm32f072b_disco_defconfig +++ b/boards/st/stm32f072b_disco/stm32f072b_disco_defconfig @@ -9,9 +9,3 @@ CONFIG_UART_CONSOLE=y # GPIO Controller CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32f0_disco/board.cmake b/boards/st/stm32f0_disco/board.cmake index d0af9581843..d36f83beb8f 100644 --- a/boards/st/stm32f0_disco/board.cmake +++ b/boards/st/stm32f0_disco/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F051R8" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32f0_disco/doc/index.rst b/boards/st/stm32f0_disco/doc/index.rst index 3947600d837..64e4605566b 100644 --- a/boards/st/stm32f0_disco/doc/index.rst +++ b/boards/st/stm32f0_disco/doc/index.rst @@ -94,6 +94,8 @@ For more details please refer to `STM32F0DISCOVERY board User Manual`_. Programming and Debugging ************************* +STM32F0DISCOVERY board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``stm32f0_disco`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -101,8 +103,16 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -STM32F0DISCOVERY board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to Nucleo F030R8 ---------------------------------------- @@ -141,3 +151,6 @@ References .. _STM32F0DISCOVERY board User Manual: https://www.st.com/resource/en/user_manual/dm00050135.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/stm32f0_disco/stm32f0_disco_defconfig b/boards/st/stm32f0_disco/stm32f0_disco_defconfig index 18ac599df25..bc6f05a7777 100644 --- a/boards/st/stm32f0_disco/stm32f0_disco_defconfig +++ b/boards/st/stm32f0_disco/stm32f0_disco_defconfig @@ -16,9 +16,3 @@ CONFIG_UART_CONSOLE=y # GPIO Controller CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32f103_mini/stm32f103_mini_defconfig b/boards/st/stm32f103_mini/stm32f103_mini_defconfig deleted file mode 100644 index 9fd4400ac20..00000000000 --- a/boards/st/stm32f103_mini/stm32f103_mini_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# enable uart driver -CONFIG_SERIAL=y -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# enable GPIO -CONFIG_GPIO=y - -# enable clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32f3_disco/board.cmake b/boards/st/stm32f3_disco/board.cmake index 0c02b470bd7..553a53bf9ce 100644 --- a/boards/st/stm32f3_disco/board.cmake +++ b/boards/st/stm32f3_disco/board.cmake @@ -1,8 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 -board_runner_args(jlink "--device=STM32F303VC" "--speed=4000") +# keep first board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +board_runner_args(jlink "--device=STM32F303VC" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) diff --git a/boards/st/stm32f3_disco/doc/index.rst b/boards/st/stm32f3_disco/doc/index.rst index d4a629a4895..e557eb013c7 100644 --- a/boards/st/stm32f3_disco/doc/index.rst +++ b/boards/st/stm32f3_disco/doc/index.rst @@ -201,9 +201,6 @@ transceiver must be connected to ``PD0`` (``CAN1_RX``) and ``PD1`` Programming and Debugging ************************* -Flashing -======== - STM32F3DISCOVERY Discovery kit includes a ST-LINK/V2 or ST-LINK/V2-B embedded debug tool interface. @@ -211,13 +208,27 @@ Applications for the ``stm32f3_disco`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). +Flashing +======== + +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink + Flashing an application to STM32F3DISCOVERY ------------------------------------------- First, connect the STM32F3DISCOVERY Discovery kit to your host computer using the USB port to prepare it for flashing. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -255,7 +266,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -280,3 +291,6 @@ Again you have to use the adapted command for newer PCB revisions (E and newer): .. _STM32F303xC reference manual: https://www.st.com/resource/en/reference_manual/dm00043574.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/stm32f3_disco/stm32f3_disco_defconfig b/boards/st/stm32f3_disco/stm32f3_disco_defconfig index ed90d066c5a..d9ffe5b49a7 100644 --- a/boards/st/stm32f3_disco/stm32f3_disco_defconfig +++ b/boards/st/stm32f3_disco/stm32f3_disco_defconfig @@ -15,9 +15,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32f3_disco/stm32f3_disco_stm32f303xc_E.yaml b/boards/st/stm32f3_disco/stm32f3_disco_stm32f303xc_E.yaml index bc17f1c2d68..9a58627880c 100644 --- a/boards/st/stm32f3_disco/stm32f3_disco_stm32f303xc_E.yaml +++ b/boards/st/stm32f3_disco/stm32f3_disco_stm32f303xc_E.yaml @@ -21,4 +21,5 @@ supported: - adc - dac - rtc + - usbd vendor: st diff --git a/boards/st/stm32f411e_disco/board.cmake b/boards/st/stm32f411e_disco/board.cmake index a14479cec5f..b0408356c87 100644 --- a/boards/st/stm32f411e_disco/board.cmake +++ b/boards/st/stm32f411e_disco/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F411VE" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32f411e_disco/doc/index.rst b/boards/st/stm32f411e_disco/doc/index.rst index a2e6f02619b..acac229c810 100644 --- a/boards/st/stm32f411e_disco/doc/index.rst +++ b/boards/st/stm32f411e_disco/doc/index.rst @@ -124,6 +124,8 @@ assigned to UART2. Default settings are 115200 8N1. Programming and Debugging ************************* +STM32F411E-DISCO Discovery kit includes an ST-LINK/V2 embedded debug tool interface. + Applications for the ``stm32f411e_disco`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -131,9 +133,16 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -STM32F411E-DISCO Discovery kit includes an ST-LINK/V2 embedded debug tool -interface. This interface is supported by the openocd version included in -Zephyr SDK. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to STM32F411E-DISCO ------------------------------------------- @@ -186,3 +195,6 @@ References .. _STM32F411x reference manual: https://www.st.com/resource/en/reference_manual/dm00119316.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/stm32f411e_disco/stm32f411e_disco_defconfig b/boards/st/stm32f411e_disco/stm32f411e_disco_defconfig index 67896885dac..c9bb36d6c2d 100644 --- a/boards/st/stm32f411e_disco/stm32f411e_disco_defconfig +++ b/boards/st/stm32f411e_disco/stm32f411e_disco_defconfig @@ -14,9 +14,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32f411e_disco/stm32f411e_disco_stm32f411xe_B.overlay b/boards/st/stm32f411e_disco/stm32f411e_disco_stm32f411xe_B.overlay index 5444498949f..ea392d6ebef 100644 --- a/boards/st/stm32f411e_disco/stm32f411e_disco_stm32f411xe_B.overlay +++ b/boards/st/stm32f411e_disco/stm32f411e_disco_stm32f411xe_B.overlay @@ -12,18 +12,18 @@ }; &i2c1 { - /delete-node/ lsm303agr-magn@1e; - /delete-node/ lsm303agr-accel@19; + /delete-node/ lsm303agr-magn@1e; + /delete-node/ lsm303agr-accel@19; lsm303dlhc_magn: lsm303dlhc-magn@1e { compatible = "st,lsm303dlhc-magn"; - status = "okay"; + status = "okay"; reg = <0x1e>; }; lsm303dlhc_accel: lsm303dlhc-accel@19 { compatible = "st,lis2dh", "st,lsm303dlhc-accel"; - status = "okay"; + status = "okay"; reg = <0x19>; irq-gpios = <&gpioe 4 GPIO_ACTIVE_HIGH>, <&gpioe 5 GPIO_ACTIVE_HIGH>; diff --git a/boards/st/stm32f412g_disco/board.cmake b/boards/st/stm32f412g_disco/board.cmake index 8b2cd0fca43..be8b35e82c8 100644 --- a/boards/st/stm32f412g_disco/board.cmake +++ b/boards/st/stm32f412g_disco/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F412ZG" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32f412g_disco/doc/index.rst b/boards/st/stm32f412g_disco/doc/index.rst index 0443d00b483..ae84de7cea7 100644 --- a/boards/st/stm32f412g_disco/doc/index.rst +++ b/boards/st/stm32f412g_disco/doc/index.rst @@ -140,6 +140,8 @@ Default settings are 115200 8N1. Programming and Debugging ************************* +STM32F412G-DISCO Discovery kit includes an ST-LINK/V2 embedded debug tool interface. + Applications for the ``stm32f412g_disco`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -147,8 +149,16 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -STM32F412G-DISCO Discovery kit includes an ST-LINK/V2 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to STM32F412G-DISCO ------------------------------------------- @@ -162,7 +172,7 @@ board: $ minicom -D /dev/ttyACM0 Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -180,7 +190,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -199,3 +209,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32F412 reference manual: https://www.st.com/resource/en/reference_manual/dm00180369.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/stm32f412g_disco/stm32f412g_disco_defconfig b/boards/st/stm32f412g_disco/stm32f412g_disco_defconfig index 0efcd3c8c7e..6348ab4d847 100644 --- a/boards/st/stm32f412g_disco/stm32f412g_disco_defconfig +++ b/boards/st/stm32f412g_disco/stm32f412g_disco_defconfig @@ -14,9 +14,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO ports A, B, C, D, E CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32f429i_disc1/board.cmake b/boards/st/stm32f429i_disc1/board.cmake index 402b28d32c0..9f872edd546 100644 --- a/boards/st/stm32f429i_disc1/board.cmake +++ b/boards/st/stm32f429i_disc1/board.cmake @@ -1,8 +1,14 @@ # SPDX-License-Identifier: Apache-2.0 -board_runner_args(stm32cubeprogrammer "--erase" "--port=swd" "--reset-mode=hw") +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F429ZI" "--speed=4000") +board_runner_args(pyocd "--target=stm32f429xi") +board_runner_args(pyocd "--flash-opt=-O reset_type=hw") +board_runner_args(pyocd "--flash-opt=-O connect_mode=under-reset") -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +# keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/st/stm32f429i_disc1/doc/index.rst b/boards/st/stm32f429i_disc1/doc/index.rst index c61cfcaa739..28a79e9ac2a 100644 --- a/boards/st/stm32f429i_disc1/doc/index.rst +++ b/boards/st/stm32f429i_disc1/doc/index.rst @@ -182,7 +182,7 @@ Alternatively, you can use `STM32CubeProgrammer`_ (after installing it) using th First, connect the STM32F429I-DISC1 Discovery kit to your host computer using the USB port to prepare it for flashing. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -206,7 +206,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm32f429i_disc1/stm32f429i_disc1_defconfig b/boards/st/stm32f429i_disc1/stm32f429i_disc1_defconfig index c729b83e3d0..51eadcb4809 100644 --- a/boards/st/stm32f429i_disc1/stm32f429i_disc1_defconfig +++ b/boards/st/stm32f429i_disc1/stm32f429i_disc1_defconfig @@ -14,9 +14,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32f469i_disco/board.cmake b/boards/st/stm32f469i_disco/board.cmake index 8a8885e9a95..327c95da4fa 100644 --- a/boards/st/stm32f469i_disco/board.cmake +++ b/boards/st/stm32f469i_disco/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F469NI" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32f469i_disco/doc/index.rst b/boards/st/stm32f469i_disco/doc/index.rst index 85ebec3778f..549ffd4c67e 100644 --- a/boards/st/stm32f469i_disco/doc/index.rst +++ b/boards/st/stm32f469i_disco/doc/index.rst @@ -162,7 +162,7 @@ Flashing an application to STM32F469I-DISCO First, connect the STM32F469I-DISCO Discovery kit to your host computer using the USB port to prepare it for flashing. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -186,7 +186,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm32f469i_disco/stm32f469i_disco_defconfig b/boards/st/stm32f469i_disco/stm32f469i_disco_defconfig index c729b83e3d0..51eadcb4809 100644 --- a/boards/st/stm32f469i_disco/stm32f469i_disco_defconfig +++ b/boards/st/stm32f469i_disco/stm32f469i_disco_defconfig @@ -14,9 +14,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32f4_disco/board.cmake b/boards/st/stm32f4_disco/board.cmake index 060c7457c73..a2c5eefa38c 100644 --- a/boards/st/stm32f4_disco/board.cmake +++ b/boards/st/stm32f4_disco/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F407VG" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32f4_disco/doc/index.rst b/boards/st/stm32f4_disco/doc/index.rst index 8839759a3ab..e590250741a 100644 --- a/boards/st/stm32f4_disco/doc/index.rst +++ b/boards/st/stm32f4_disco/doc/index.rst @@ -155,6 +155,8 @@ enable console output you should use a serial cable and connect it to UART2 pins Programming and Debugging ************************* +STM32F4DISCOVERY Discovery kit includes an ST-LINK/V2 embedded debug tool interface. + Applications for the ``stm32f4_disco`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -162,8 +164,16 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -STM32F4DISCOVERY Discovery kit includes an ST-LINK/V2 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to STM32F4DISCOVERY ------------------------------------------- @@ -189,7 +199,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -211,3 +221,6 @@ You can debug an application in the usual way. Here is an example for the .. _SK Pang CAN breakout board: https://www.skpang.co.uk/products/can-bus-can-fd-breakout-board-5v-supply-and-3-3v-logic + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/stm32f4_disco/stm32f4_disco_defconfig b/boards/st/stm32f4_disco/stm32f4_disco_defconfig index c729b83e3d0..51eadcb4809 100644 --- a/boards/st/stm32f4_disco/stm32f4_disco_defconfig +++ b/boards/st/stm32f4_disco/stm32f4_disco_defconfig @@ -14,9 +14,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32f723e_disco/board.cmake b/boards/st/stm32f723e_disco/board.cmake index e5ef74a91e7..7a99727f266 100644 --- a/boards/st/stm32f723e_disco/board.cmake +++ b/boards/st/stm32f723e_disco/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F723IE" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32f723e_disco/doc/index.rst b/boards/st/stm32f723e_disco/doc/index.rst index 554c329db81..755e87d4a12 100644 --- a/boards/st/stm32f723e_disco/doc/index.rst +++ b/boards/st/stm32f723e_disco/doc/index.rst @@ -132,6 +132,8 @@ settings are 115200 8N1. Programming and Debugging ************************* +STM32F723E Discovery kit includes an ST-LINK/V2 embedded debug tool interface. + Applications for the ``stm32f723e_disco`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -139,8 +141,16 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -STM32F723E Discovery kit includes an ST-LINK/V2 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to STM32F723E-DISCO ------------------------------------------- @@ -148,7 +158,7 @@ Flashing an application to STM32F723E-DISCO First, connect the STM32F723E Discovery kit to your host computer using the USB port to prepare it for flashing. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -171,7 +181,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -190,3 +200,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32F72xxx reference manual: https://www.st.com/resource/en/reference_manual/dm00305990.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/stm32f723e_disco/stm32f723e_disco.dts b/boards/st/stm32f723e_disco/stm32f723e_disco.dts index 4c6641c7f2c..a9ca03675df 100644 --- a/boards/st/stm32f723e_disco/stm32f723e_disco.dts +++ b/boards/st/stm32f723e_disco/stm32f723e_disco.dts @@ -52,7 +52,6 @@ led1 = &red_led; led2 = &green_led; sw0 = &user_button; - spi-flash0 = &mx25r512; }; }; diff --git a/boards/st/stm32f723e_disco/stm32f723e_disco_defconfig b/boards/st/stm32f723e_disco/stm32f723e_disco_defconfig index c729b83e3d0..51eadcb4809 100644 --- a/boards/st/stm32f723e_disco/stm32f723e_disco_defconfig +++ b/boards/st/stm32f723e_disco/stm32f723e_disco_defconfig @@ -14,9 +14,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32f746g_disco/board.cmake b/boards/st/stm32f746g_disco/board.cmake index bbc3ee782d1..038a5d7e806 100644 --- a/boards/st/stm32f746g_disco/board.cmake +++ b/boards/st/stm32f746g_disco/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F746NG" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32f746g_disco/doc/index.rst b/boards/st/stm32f746g_disco/doc/index.rst index 03e71c20b90..7bd37aa2652 100644 --- a/boards/st/stm32f746g_disco/doc/index.rst +++ b/boards/st/stm32f746g_disco/doc/index.rst @@ -183,6 +183,8 @@ settings are 115200 8N1. Programming and Debugging ************************* +STM32F746G Discovery kit includes an ST-LINK/V2 embedded debug tool interface. + Applications for the ``stm32f746g_disco`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -190,8 +192,16 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -STM32F746G Discovery kit includes an ST-LINK/V2 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to STM32F746G ------------------------------------------- @@ -199,7 +209,7 @@ Flashing an application to STM32F746G First, connect the STM32F746G Discovery kit to your host computer using the USB port to prepare it for flashing. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -222,7 +232,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -241,3 +251,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32F74xxx reference manual: https://www.st.com/resource/en/reference_manual/dm00124865.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/stm32f746g_disco/stm32f746g_disco.dts b/boards/st/stm32f746g_disco/stm32f746g_disco.dts index 6250c4e8e80..2c31fef1c92 100644 --- a/boards/st/stm32f746g_disco/stm32f746g_disco.dts +++ b/boards/st/stm32f746g_disco/stm32f746g_disco.dts @@ -59,7 +59,6 @@ aliases { led0 = &green_led_1; sw0 = &user_button; - spi-flash0 = &n25q128a1; }; }; diff --git a/boards/st/stm32f746g_disco/stm32f746g_disco_defconfig b/boards/st/stm32f746g_disco/stm32f746g_disco_defconfig index c729b83e3d0..51eadcb4809 100644 --- a/boards/st/stm32f746g_disco/stm32f746g_disco_defconfig +++ b/boards/st/stm32f746g_disco/stm32f746g_disco_defconfig @@ -14,9 +14,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32f7508_dk/board.cmake b/boards/st/stm32f7508_dk/board.cmake index b81e563d0c2..83aae9337d6 100644 --- a/boards/st/stm32f7508_dk/board.cmake +++ b/boards/st/stm32f7508_dk/board.cmake @@ -1,7 +1,11 @@ # Copyright (c) 2022, Rtone. # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F750N8" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32f7508_dk/doc/index.rst b/boards/st/stm32f7508_dk/doc/index.rst index 0b3737a8761..7a3c1c96c22 100644 --- a/boards/st/stm32f7508_dk/doc/index.rst +++ b/boards/st/stm32f7508_dk/doc/index.rst @@ -178,6 +178,8 @@ settings are 115200 8N1. Programming and Debugging ************************* +STM32F7508-DK Discovery kit includes an ST-LINK/V2 embedded debug tool interface. + Applications for the ``stm32f7508_dk`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -185,8 +187,16 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -STM32F7508-DK Discovery kit includes an ST-LINK/V2 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to STM32F7508-DK ------------------------------------------- @@ -194,7 +204,7 @@ Flashing an application to STM32F7508-DK First, connect the STM32F746G Discovery kit to your host computer using the USB port to prepare it for flashing. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -217,7 +227,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -236,3 +246,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32F74xxx reference manual: https://www.st.com/resource/en/reference_manual/dm00124865.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/stm32f7508_dk/stm32f7508_dk.dts b/boards/st/stm32f7508_dk/stm32f7508_dk.dts index b98cf5aeed9..100fd6e661d 100644 --- a/boards/st/stm32f7508_dk/stm32f7508_dk.dts +++ b/boards/st/stm32f7508_dk/stm32f7508_dk.dts @@ -59,7 +59,6 @@ aliases { led0 = &green_led_1; sw0 = &user_button; - spi-flash0 = &n25q128a1; }; }; diff --git a/boards/st/stm32f7508_dk/stm32f7508_dk_defconfig b/boards/st/stm32f7508_dk/stm32f7508_dk_defconfig index 18159201a57..34fa38e544f 100644 --- a/boards/st/stm32f7508_dk/stm32f7508_dk_defconfig +++ b/boards/st/stm32f7508_dk/stm32f7508_dk_defconfig @@ -15,9 +15,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32f769i_disco/board.cmake b/boards/st/stm32f769i_disco/board.cmake index 819c5aba81b..6df48aa7403 100644 --- a/boards/st/stm32f769i_disco/board.cmake +++ b/boards/st/stm32f769i_disco/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F769NI" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32f769i_disco/doc/index.rst b/boards/st/stm32f769i_disco/doc/index.rst index 223c48a9dbe..210eb840ff0 100644 --- a/boards/st/stm32f769i_disco/doc/index.rst +++ b/boards/st/stm32f769i_disco/doc/index.rst @@ -165,6 +165,8 @@ settings are 115200 8N1. Programming and Debugging ************************* +STM32F769I Discovery kit includes an ST-LINK/V2 embedded debug tool interface. + Applications for the ``stm32f769i_disco`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -172,8 +174,16 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -STM32F769I Discovery kit includes an ST-LINK/V2 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to STM32F769I ------------------------------------------- @@ -181,7 +191,7 @@ Flashing an application to STM32F769I First, connect the STM32F769I Discovery kit to your host computer using the USB port to prepare it for flashing. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -204,7 +214,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -223,3 +233,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32F76xxx reference manual: https://www.st.com/resource/en/reference_manual/dm00224583.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/stm32f769i_disco/stm32f769i_disco.dts b/boards/st/stm32f769i_disco/stm32f769i_disco.dts index 03ff90c729b..9ad4f4ef3bc 100644 --- a/boards/st/stm32f769i_disco/stm32f769i_disco.dts +++ b/boards/st/stm32f769i_disco/stm32f769i_disco.dts @@ -77,7 +77,6 @@ led2 = &green_led_3; led3 = &red_led_4; sw0 = &user_button; - spi-flash0 = &mx25l51245g; }; quadspi_memory_avail: memory-avail@90000000 { diff --git a/boards/st/stm32f769i_disco/stm32f769i_disco_defconfig b/boards/st/stm32f769i_disco/stm32f769i_disco_defconfig index c729b83e3d0..51eadcb4809 100644 --- a/boards/st/stm32f769i_disco/stm32f769i_disco_defconfig +++ b/boards/st/stm32f769i_disco/stm32f769i_disco_defconfig @@ -14,9 +14,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32g0316_disco/board.cmake b/boards/st/stm32g0316_disco/board.cmake index 43e18743801..30495593070 100644 --- a/boards/st/stm32g0316_disco/board.cmake +++ b/boards/st/stm32g0316_disco/board.cmake @@ -1,9 +1,12 @@ # SPDX-License-Identifier: Apache-2.0 -board_runner_args(pyocd "--target=stm32g031j6mx") + +# keep first board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +board_runner_args(pyocd "--target=stm32g031j6mx") board_runner_args(jlink "--device=STM32G031J6" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) diff --git a/boards/st/stm32g0316_disco/doc/index.rst b/boards/st/stm32g0316_disco/doc/index.rst index 516a1f9623e..de6c2d91e55 100644 --- a/boards/st/stm32g0316_disco/doc/index.rst +++ b/boards/st/stm32g0316_disco/doc/index.rst @@ -81,15 +81,24 @@ Default Zephyr Peripheral Mapping: Programming and Debugging ************************* +The STM32G0316-DISCO board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``stm32g0316_disco`` board configuration can be built the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). Flashing ======== -The STM32G0316-DISCO board includes an ST-LINK/V2-1 embedded debug tool -interface. -This interface is supported by the openocd version included in the Zephyr SDK. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to the STM32G0316-DISCO ----------------------------------------------- @@ -107,7 +116,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -126,3 +135,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32G0316-DISCO website: https://www.st.com/en/evaluation-tools/stm32g0316-disco.html + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/stm32g0316_disco/stm32g0316_disco_defconfig b/boards/st/stm32g0316_disco/stm32g0316_disco_defconfig index f846f1d12a7..b9dc13649c8 100644 --- a/boards/st/stm32g0316_disco/stm32g0316_disco_defconfig +++ b/boards/st/stm32g0316_disco/stm32g0316_disco_defconfig @@ -13,9 +13,3 @@ CONFIG_UART_CONSOLE=y # GPIO Controller CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32g071b_disco/board.cmake b/boards/st/stm32g071b_disco/board.cmake index b315703cd96..b77e3f43c2f 100644 --- a/boards/st/stm32g071b_disco/board.cmake +++ b/boards/st/stm32g071b_disco/board.cmake @@ -1,6 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +# keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) - diff --git a/boards/st/stm32g071b_disco/doc/index.rst b/boards/st/stm32g071b_disco/doc/index.rst index 6047f6d298a..e64a06d1213 100644 --- a/boards/st/stm32g071b_disco/doc/index.rst +++ b/boards/st/stm32g071b_disco/doc/index.rst @@ -51,6 +51,7 @@ More information about the board can be found at the `STM32G071B-DISCO website`_ More information about STM32G071RB can be found here: + - `G071RB on www.st.com`_ - `STM32G071 reference manual`_ @@ -114,6 +115,8 @@ For more details please refer to `STM32G0 Discovery board User Manual`_. Programming and Debugging ************************* +The STM32G071B Discovery board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``stm32g071b_disco`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -121,7 +124,8 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -The STM32G071B Discovery board includes an ST-LINK/V2-1 embedded debug tool interface. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. .. code-block:: console @@ -143,7 +147,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -167,3 +171,6 @@ References .. _G071RB on www.st.com: https://www.st.com/en/microcontrollers/stm32g071rb.html + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/stm32g071b_disco/stm32g071b_disco_defconfig b/boards/st/stm32g071b_disco/stm32g071b_disco_defconfig index 2554c256697..ef1463b6aa7 100644 --- a/boards/st/stm32g071b_disco/stm32g071b_disco_defconfig +++ b/boards/st/stm32g071b_disco/stm32g071b_disco_defconfig @@ -12,9 +12,3 @@ CONFIG_UART_CONSOLE=y # GPIO Controller CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32g081b_eval/board.cmake b/boards/st/stm32g081b_eval/board.cmake index b315703cd96..b77e3f43c2f 100644 --- a/boards/st/stm32g081b_eval/board.cmake +++ b/boards/st/stm32g081b_eval/board.cmake @@ -1,6 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +# keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) - diff --git a/boards/st/stm32g081b_eval/doc/index.rst b/boards/st/stm32g081b_eval/doc/index.rst index 5363a2c230a..1f737c8daa1 100644 --- a/boards/st/stm32g081b_eval/doc/index.rst +++ b/boards/st/stm32g081b_eval/doc/index.rst @@ -92,6 +92,7 @@ More information about the board can be found at the `STM32G081B-EVAL website`_. More information about STM32G081RB can be found here: + - `G081RB on www.st.com`_ - `STM32G081 reference manual`_ @@ -152,6 +153,8 @@ For more details please refer to `STM32G0 Evaluation board User Manual`_. Programming and Debugging ************************* +The STM32G081B Evaluation board includes an ST-LINK/V2-1 embedded debug tool interface. + Applications for the ``stm32g081b_eval`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -159,7 +162,8 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -The STM32G081B Evaluation board includes an ST-LINK/V2-1 embedded debug tool interface. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. .. code-block:: console @@ -181,7 +185,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -205,3 +209,6 @@ References .. _G081RB on www.st.com: https://www.st.com/en/microcontrollers/stm32g081rb.html + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/stm32g081b_eval/stm32g081b_eval_defconfig b/boards/st/stm32g081b_eval/stm32g081b_eval_defconfig index 2554c256697..ef1463b6aa7 100644 --- a/boards/st/stm32g081b_eval/stm32g081b_eval_defconfig +++ b/boards/st/stm32g081b_eval/stm32g081b_eval_defconfig @@ -12,9 +12,3 @@ CONFIG_UART_CONSOLE=y # GPIO Controller CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32h573i_dk/board.cmake b/boards/st/stm32h573i_dk/board.cmake index 9890c769c31..f1a703cda64 100644 --- a/boards/st/stm32h573i_dk/board.cmake +++ b/boards/st/stm32h573i_dk/board.cmake @@ -1,8 +1,21 @@ # SPDX-License-Identifier: Apache-2.0 -board_runner_args(stm32cubeprogrammer "--erase" "--port=swd" "--reset-mode=hw") +# keep first +if(CONFIG_STM32_MEMMAP) +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +board_runner_args(stm32cubeprogrammer "--extload=MX25LM51245G_STM32H573I-DK-RevB-SFIx.stldr") +else() +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +endif() + board_runner_args(pyocd "--target=stm32h573iikx") +board_runner_args(openocd "--tcl-port=6666") +board_runner_args(openocd --cmd-pre-init "gdb_report_data_abort enable") +board_runner_args(openocd "--no-halt") + +# keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) -# FIXME: openocd runner not yet available. +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +# FIXME: official openocd runner not yet available. diff --git a/boards/st/stm32h573i_dk/doc/index.rst b/boards/st/stm32h573i_dk/doc/index.rst index 72fba315ace..86190a77ded 100644 --- a/boards/st/stm32h573i_dk/doc/index.rst +++ b/boards/st/stm32h573i_dk/doc/index.rst @@ -245,24 +245,60 @@ assigned to USART1. Default settings are 115200 8N1. Programming and Debugging ************************* +STM32H573I-DK Discovery board includes an ST-LINK/V3E embedded debug tool interface. + Applications for the ``stm32h573i_dk`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). +OpenOCD Support +=============== + +For now, OpenOCD support for STM32H5 is not available on upstream OpenOCD. +You can check `OpenOCD official Github mirror`_. +In order to use it though, you should clone from the cutomized +`STMicroelectronics OpenOCD Github`_ and compile it following usual README guidelines. +Once it is done, you can set the OPENOCD and OPENOCD_DEFAULT_PATH variables in +:zephyr_file:`boards/st/stm32h573i_dk/board.cmake` to point the build +to the paths of the OpenOCD binary and its scripts, before +including the common openocd.board.cmake file: + + .. code-block:: none + + set(OPENOCD "/src/openocd" CACHE FILEPATH "" FORCE) + set(OPENOCD_DEFAULT_PATH /tcl) + include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) + + Flashing ======== -STM32H573I-DK Discovery board includes an ST-LINK/V3E embedded debug tool -interface. Support is available on STM32CubeProgrammer V2.13.0. -Alternatively, this interface will be supported by a next openocd version. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or pyOCD can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner pyocd + +For pyOCD, additional target information needs to be installed +by executing the following commands: + +.. code-block:: console + + $ pyocd pack --update + $ pyocd pack --install stm32h5 Flashing an application to STM32H573I-DK Discovery -------------------------------------------------- Connect the STM32H573I-DK Discovery to your host computer using the USB port. Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board: @@ -286,8 +322,8 @@ You should see the following message on the console: Debugging ========= -Waiting for openocd support, debugging could be performed with pyocd which -requires to enable "pack" support with the following pyocd command: +Waiting for OpenOCD support, debugging could be performed with pyOCD which +requires to enable "pack" support with the following pyOCD command: .. code-block:: console @@ -295,7 +331,7 @@ requires to enable "pack" support with the following pyocd command: $ pyocd pack --install stm32h5 Once installed, you can debug an application in the usual way. Here is an -example for the :ref:`hello_world` application. +example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -317,3 +353,9 @@ example for the :ref:`hello_world` application. .. _STM32CubeProgrammer: https://www.st.com/en/development-tools/stm32cubeprog.html + +.. _OpenOCD official Github mirror: + https://github.com/openocd-org/openocd/ + +.. _STMicroelectronics OpenOCD Github: + https://github.com/STMicroelectronics/OpenOCD/tree/openocd-cubeide-r6 diff --git a/boards/st/stm32h573i_dk/stm32h573i_dk.dts b/boards/st/stm32h573i_dk/stm32h573i_dk.dts index 721cea3ab6a..c64ff945106 100644 --- a/boards/st/stm32h573i_dk/stm32h573i_dk.dts +++ b/boards/st/stm32h573i_dk/stm32h573i_dk.dts @@ -9,7 +9,8 @@ #include #include "arduino_r3_connector.dtsi" #include - +#include +#include / { model = "STMicroelectronics STM32H573I DISCOVERY KIT board"; compatible = "st,stm32h573i-dk"; @@ -56,11 +57,19 @@ led0 = &blue_led_0; sw0 = &user_button; watchdog0 = &iwdg; - spi-flash0 = &mx25lm51245; die-temp0 = &die_temp; + die-temp1 = &digi_die_temp; volt-sensor0 = &vref; volt-sensor1 = &vbat; }; + + ext_memory: memory@90000000 { + compatible = "zephyr,memory-region"; + reg = <0x90000000 DT_SIZE_M(64)>; + zephyr,memory-region = "EXTMEM"; + /* The ATTR_MPU_EXTMEM attribut causing a MPU FAULT */ + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>; + }; }; &clk_hsi48 { @@ -303,6 +312,10 @@ zephyr_udc0: &usb { status = "okay"; }; +&digi_die_temp { + status = "okay"; +}; + &vref { status = "okay"; }; diff --git a/boards/st/stm32h573i_dk/stm32h573i_dk.yaml b/boards/st/stm32h573i_dk/stm32h573i_dk.yaml index f6d5f12b173..35802081879 100644 --- a/boards/st/stm32h573i_dk/stm32h573i_dk.yaml +++ b/boards/st/stm32h573i_dk/stm32h573i_dk.yaml @@ -25,4 +25,5 @@ supported: - usb - i2c - rtc + - usbd vendor: st diff --git a/boards/st/stm32h573i_dk/stm32h573i_dk_defconfig b/boards/st/stm32h573i_dk/stm32h573i_dk_defconfig index c112d04baa0..3421a525fcd 100644 --- a/boards/st/stm32h573i_dk/stm32h573i_dk_defconfig +++ b/boards/st/stm32h573i_dk/stm32h573i_dk_defconfig @@ -15,9 +15,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32h573i_dk/support/openocd.cfg b/boards/st/stm32h573i_dk/support/openocd.cfg new file mode 100644 index 00000000000..2e5a829460c --- /dev/null +++ b/boards/st/stm32h573i_dk/support/openocd.cfg @@ -0,0 +1,23 @@ +source [find interface/stlink-dap.cfg] + +source [find target/stm32h5x.cfg] + +transport select "dapdirect_swd" + +set CHIPNAME STM32H573IIKXQ +set BOARDNAME STM32H573I-DK + +# Reset configuration +# use hardware reset, connect under reset +# connect_assert_srst needed if low power mode application running (WFI...) +reset_config srst_only srst_nogate connect_assert_srst +set CONNECT_UNDER_RESET 1 +set CORE_RESET 0 + +# Due to the use of connect_assert_srst, running gdb requires +# to reset halt just after openocd init. +rename init old_init +proc init {} { + old_init + reset halt +} diff --git a/boards/st/stm32h735g_disco/board.cmake b/boards/st/stm32h735g_disco/board.cmake index b4beb22525d..ef05a214927 100644 --- a/boards/st/stm32h735g_disco/board.cmake +++ b/boards/st/stm32h735g_disco/board.cmake @@ -1,8 +1,12 @@ # SPDX-License-Identifier: Apache-2.0 # Copyright (c) 2021 SILA Embedded Solutions GmbH +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32H735IG" "--speed=4000") board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32h735g_disco/doc/index.rst b/boards/st/stm32h735g_disco/doc/index.rst index bf7605d7766..3ec250bb4e8 100644 --- a/boards/st/stm32h735g_disco/doc/index.rst +++ b/boards/st/stm32h735g_disco/doc/index.rst @@ -69,11 +69,13 @@ The current Zephyr stm32h735g_disco board configuration supports the following h +-----------+------------+-------------------------------------+ | FDCAN2 | on-chip | CAN-FD Controller | +-----------+------------+-------------------------------------+ -| FDCAN2 | on-chip | CAN-FD Controller (disabled by | +| FDCAN3 | on-chip | CAN-FD Controller (disabled by | | | | default. Solder bridges SB29 and | | | | SB30 need to be closed for FDCAN3 | | | | to work) | +-----------+------------+-------------------------------------+ +| USB | on-chip | usb_device | ++-----------+------------+-------------------------------------+ Other hardware features are not yet supported on Zephyr porting. @@ -112,23 +114,33 @@ COM port interface. Default communication settings are 115200 8N1. Programming and Debugging ************************* +STM32H735G-DISCO board includes an ST-LINK/V3 embedded debug tool interface. + See :ref:`build_an_application` for more information about application builds. Flashing ======== -Flashing operation will depend on the target to be flashed and the SoC -option bytes configuration. -It is advised to use `STM32CubeProgrammer`_ to check and update option bytes -configuration and flash the ``stm32h735g_disco`` target. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink + +It is advised to use `STM32CubeProgrammer`_ to check and update option bytes +configuration. Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm32h735g_disco/stm32h735g_disco.dts b/boards/st/stm32h735g_disco/stm32h735g_disco.dts index 41e67e551c2..af351902869 100644 --- a/boards/st/stm32h735g_disco/stm32h735g_disco.dts +++ b/boards/st/stm32h735g_disco/stm32h735g_disco.dts @@ -206,10 +206,6 @@ }; }; -&vbat { - status = "okay"; -}; - &fdcan1 { pinctrl-0 = <&fdcan1_rx_ph14 &fdcan1_tx_ph13>; pinctrl-names = "default"; @@ -246,3 +242,9 @@ max-bitrate = <8000000>; }; }; + +zephyr_udc0: &usbotg_hs { + status = "okay"; + pinctrl-0 = <&usb_otg_hs_dm_pa11 &usb_otg_hs_dp_pa12>; + pinctrl-names = "default"; +}; diff --git a/boards/st/stm32h735g_disco/stm32h735g_disco.yaml b/boards/st/stm32h735g_disco/stm32h735g_disco.yaml index c0983f46f4f..cf0bbb425ba 100644 --- a/boards/st/stm32h735g_disco/stm32h735g_disco.yaml +++ b/boards/st/stm32h735g_disco/stm32h735g_disco.yaml @@ -9,11 +9,11 @@ toolchain: ram: 368 flash: 1024 supported: - - arduino_gpio - gpio - netif:eth - memc - adc - counter - can + - usb_device vendor: st diff --git a/boards/st/stm32h735g_disco/stm32h735g_disco_defconfig b/boards/st/stm32h735g_disco/stm32h735g_disco_defconfig index fe5e1092729..4a6dbc11f0e 100644 --- a/boards/st/stm32h735g_disco/stm32h735g_disco_defconfig +++ b/boards/st/stm32h735g_disco/stm32h735g_disco_defconfig @@ -18,9 +18,3 @@ CONFIG_UART_CONSOLE=y # Enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# Enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32h745i_disco/arduino_r3_connector.dtsi b/boards/st/stm32h745i_disco/arduino_r3_connector.dtsi index 4ad2396a162..1d24b1ecb74 100644 --- a/boards/st/stm32h745i_disco/arduino_r3_connector.dtsi +++ b/boards/st/stm32h745i_disco/arduino_r3_connector.dtsi @@ -37,6 +37,6 @@ }; -arduino_i2c: &i2c1 {}; - +arduino_i2c: &i2c4 {}; +arduino_spi: &spi2 {}; arduino_serial: &usart1 {}; diff --git a/boards/st/stm32h745i_disco/board.cmake b/boards/st/stm32h745i_disco/board.cmake index 699e51ae595..ae99e34ce51 100644 --- a/boards/st/stm32h745i_disco/board.cmake +++ b/boards/st/stm32h745i_disco/board.cmake @@ -2,14 +2,22 @@ # Copyright (c) 2020 Alexander Kozhinov # Copyright (c) 2024 Tomas Jurena +# keep first +if(CONFIG_STM32_MEMMAP) +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +board_runner_args(stm32cubeprogrammer "--extload=MT25TL01G_STM32H745I-DISCO.stldr") +else() +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +endif() + board_runner_args(jlink "--device=STM32H745XI" "--speed=4000") if(CONFIG_BOARD_STM32H745I_DISCO_STM32H745XX_M7) board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) elseif(CONFIG_BOARD_STM32H745I_DISCO_STM32H745XX_M4) board_runner_args(openocd --target-handle=_CHIPNAME.cpu1) endif() -board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +# keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32h745i_disco/doc/index.rst b/boards/st/stm32h745i_disco/doc/index.rst index 0b74a8903d0..c5b0ef79276 100644 --- a/boards/st/stm32h745i_disco/doc/index.rst +++ b/boards/st/stm32h745i_disco/doc/index.rst @@ -102,7 +102,7 @@ The current Zephyr stm32h745i_disco board configuration supports the following h Other hardware features are not yet supported on this Zephyr port. The default configuration per core can be found in the defconfig files: -:zephyr_file:`boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7_defconfig`` and +:zephyr_file:`boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7_defconfig` and :zephyr_file:`boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m4_defconfig` For more details please refer to `STM32H745-Disco UM`_. @@ -150,6 +150,8 @@ two cores. This is done in 3 ways: Programming and Debugging ************************* +STM32H745I-DISCO board includes an ST-LINK/V3 embedded debug tool interface. + Applications for the ``stm32h745i_disco`` board should be built per core target, using either ``stm32h745i_disco/stm32h745xx/m7`` or ``stm32h745i_disco/stm32h745xx/m4`` as the target (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -161,10 +163,22 @@ using either ``stm32h745i_disco/stm32h745xx/m7`` or ``stm32h745i_disco/stm32h745 Flashing ======== -STM32H745I-DISCO board includes an ST-LINK/V3 embedded debug tool interface. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. +The target core is detected automatically. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console -Flashing operation will depend on the target and the SoC -option bytes configuration. + $ west flash --runner openocd + $ west flash --runner jlink + +Flashing an application to STM32H745I-DISCO +------------------------------------------- + +Flashing operation will depend on the target and the SoC option bytes configuration. By default: @@ -176,19 +190,12 @@ board is powered (Option bytes BCM7 and BCM4 are checked). In that configuration, Kconfig boot option ``STM32H7_BOOT_CM4_CM7`` should be selected. Zephyr flash configuration has been set to meet these default settings. -Alternatively, west `STM32CubeProgrammer`_ runner can be used, after installing -it, to flash applications for both cores. The target core is detected automatically. - -.. code-block:: console - - $ west flash --runner stm32cubeprogrammer - Flashing an application to STM32H745XI M7 Core ---------------------------------------------- First, connect the STM32H745I-DISCO to your host computer using the USB port to prepare it for flashing. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your STM32H745I-DISCO board. @@ -238,7 +245,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m4_defconfig b/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m4_defconfig index 03e689742d9..e2c6b592151 100644 --- a/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m4_defconfig +++ b/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m4_defconfig @@ -5,9 +5,6 @@ # Enable GPIO CONFIG_GPIO=y -# Enable clock -CONFIG_CLOCK_CONTROL=y - # By default SERIAL peripherals are assigned to m7 # Enable uart driver @@ -16,6 +13,3 @@ CONFIG_CLOCK_CONTROL=y # Console #CONFIG_CONSOLE=y #CONFIG_UART_CONSOLE=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7.dts b/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7.dts index eb33539d879..ba2f771cfbf 100644 --- a/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7.dts +++ b/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7.dts @@ -42,10 +42,19 @@ zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; }; + ext_memory: memory@90000000 { + compatible = "zephyr,memory-region"; + reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */ + zephyr,memory-region = "EXTMEM"; + /* The ATTR_MPU_EXTMEM attribut causing a MPU FAULT */ + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>; + }; + aliases { led0 = &green_led; pwm-led0 = &green_pwm_led; sw0 = &user_button; + spi-flash0 = &mt25ql512ab1; }; }; @@ -167,7 +176,7 @@ &quadspi_bk2_io0_ph2 &quadspi_bk2_io1_ph3 >; - flash-id = <1>; + dual-flash; status = "okay"; mt25ql512ab1: qspi-nor-flash-1@90000000 { @@ -175,6 +184,7 @@ reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */ qspi-max-frequency = <72000000>; spi-bus-width = <4>; + reset-cmd; status = "okay"; partitions { diff --git a/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7_defconfig b/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7_defconfig index f3ba3ad3b2a..1ad6ad9133d 100644 --- a/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7_defconfig +++ b/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7_defconfig @@ -20,9 +20,3 @@ CONFIG_UART_CONSOLE=y # Enable GPIO CONFIG_GPIO=y - -# Enable Clock -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32h747i_disco/board.cmake b/boards/st/stm32h747i_disco/board.cmake index 93b40d3634d..6b22ac50217 100644 --- a/boards/st/stm32h747i_disco/board.cmake +++ b/boards/st/stm32h747i_disco/board.cmake @@ -1,6 +1,14 @@ # SPDX-License-Identifier: Apache-2.0 # Copyright (c) 2019 STMicroelectronics +# keep first +if(CONFIG_STM32_MEMMAP) +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +board_runner_args(stm32cubeprogrammer "--extload=MT25TL01G_STM32H747I-DISCO.stldr") +else() +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +endif() + if(CONFIG_BOARD_STM32H747I_DISCO_STM32H747XX_M7) board_runner_args(jlink "--device=STM32H747ZI_M7") board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_stm32h747i_disco_m7.cfg") @@ -10,8 +18,8 @@ elseif(CONFIG_BOARD_STM32H747I_DISCO_STM32H747XX_M4) board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_stm32h747i_disco_m4.cfg") board_runner_args(openocd --target-handle=_CHIPNAME.cpu1) endif() -board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +# keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32h747i_disco/doc/index.rst b/boards/st/stm32h747i_disco/doc/index.rst index 06b8c88e1ac..4f7a345ccc4 100644 --- a/boards/st/stm32h747i_disco/doc/index.rst +++ b/boards/st/stm32h747i_disco/doc/index.rst @@ -175,11 +175,11 @@ support in Zephyr by adding the shield ``st_b_lcd40_dsi1_mb1166`` or .. note:: The shield comes in different hardware revisions, the MB1166-A09 is utilizing a NT35510 panel controller and shall specifically - use ``st_b_lcd40_dsi1_mb1166_a09`` as SHIELD when building + use ``st_b_lcd40_dsi1_mb1166_a09`` as SHIELD when building. Prior versions are utilizing an OTM8009a controller and shall - use shield name without postfix, that is: ``st_b_lcd40_dsi1_mb1166`` + use shield name without postfix, that is: ``st_b_lcd40_dsi1_mb1166``. Shield version is printed on a sticker placed below the two bottom - mounting holes and has the format: MB1166-Axx + mounting holes and has the format: MB1166-Axx. Resources sharing ================= @@ -199,15 +199,21 @@ two cores. This is done in 3 ways: Programming and Debugging ************************* +STM32H747I-DISCO board includes an ST-LINK/V3 embedded debug tool interface. + Applications for the ``stm32h747i_disco`` board should be built per core target, -using either ``stm32h747i_disco/stm32h747xx/m7`` or ```stm32h747i_disco/stm32h747xx/m4`` as the target. +using either ``stm32h747i_disco/stm32h747xx/m7`` or ``stm32h747i_disco/stm32h747xx/m4`` +as the target. See :ref:`build_an_application` for more information about application builds. .. note:: - If using OpenOCD you will need a recent development version as the last - official release does not support H7 dualcore yet. - Also, with OpenOCD, sometimes, flashing is not working. It is necessary to + Check if the board's ST-LINK V3 has the newest FW version. It can be updated + using `STM32CubeProgrammer`_. + +.. note:: + + With OpenOCD, sometimes, flashing does not work. It is necessary to erase the flash (with STM32CubeProgrammer for example) to make it work again. Debugging with OpenOCD is currently working for this board only with Cortex M7, not Cortex M4. @@ -218,9 +224,21 @@ Flashing Flashing operation will depend on the target to be flashed and the SoC option bytes configuration. + +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner +for both cores, so its :ref:`installation ` is required. +The target core is detected automatically. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink + It is advised to use `STM32CubeProgrammer`_ to check and update option bytes -configuration and flash ``stm32h747i_disco/stm32h747xx/m7`` and -``stm32h747i_disco/stm32h747xx/m7`` targets. +configuration. By default: @@ -236,20 +254,13 @@ automatically. Zephyr flash configuration has been set to meet these default settings. -Alternatively, west `STM32CubeProgrammer`_ runner can be used, after installing -it, to flash applications for both cores. The target core is detected automatically. - -.. code-block:: console - - $ west flash --runner stm32cubeprogrammer - Flashing an application to STM32H747I M7 Core --------------------------------------------- First, connect the STM32H747I Discovery kit to your host computer using the USB port to prepare it for flashing. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -285,17 +296,16 @@ Here is an example for the :zephyr:code-sample:`blinky` application on M4 core. Debugging ========= -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +You can debug an application on Cortex M7 side in the usual way. Here is an example +for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: stm32h747i_disco/stm32h747xx/m7 :goals: debug -Debugging with west is currently not available on Cortex M4 side. -In order to debug a Zephyr application on Cortex M4 side, you can use -`STM32CubeIDE`_. +Debugging a Zephyr application on Cortex M4 side with west is currently not available. +As a workaround, you can use `STM32CubeIDE`_. .. _STM32H747I-DISCO website: https://www.st.com/en/evaluation-tools/stm32h747i-disco.html diff --git a/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m4_defconfig b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m4_defconfig index 9b540e01f63..fc25c23f302 100644 --- a/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m4_defconfig +++ b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m4_defconfig @@ -4,9 +4,6 @@ # Enable GPIO CONFIG_GPIO=y -# Clock configuration -CONFIG_CLOCK_CONTROL=y - # Enable MPU CONFIG_ARM_MPU=y @@ -19,6 +16,3 @@ CONFIG_SERIAL=y # By default CONSOLE is assigned to m7 #CONFIG_CONSOLE=y #CONFIG_UART_CONSOLE=y - -# Enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.dts b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.dts index a660f92af17..9feb49e0987 100644 --- a/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.dts +++ b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.dts @@ -31,6 +31,14 @@ zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; }; + ext_memory: memory@90000000 { + compatible = "zephyr,memory-region"; + reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */ + zephyr,memory-region = "EXTMEM"; + /* The ATTR_MPU_EXTMEM attribut causing a MPU FAULT */ + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>; + }; + leds { green_led_1:led_1 { status = "okay"; @@ -55,7 +63,6 @@ led0 = &green_led_1; led1 = &orange_led_2; sw0 = &wake_up; - spi-flash0 = &mt25ql512ab1; }; }; @@ -240,6 +247,7 @@ zephyr_udc0: &usbotg_hs { &quadspi_bk2_io0_ph2 &quadspi_bk2_io1_ph3 &quadspi_bk2_io2_pg9 &quadspi_bk2_io3_pg14>; pinctrl-names = "default"; + dual-flash; status = "okay"; mt25ql512ab1: qspi-nor-flash-1@90000000 { @@ -247,6 +255,7 @@ zephyr_udc0: &usbotg_hs { reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */ qspi-max-frequency = <72000000>; spi-bus-width = <4>; + reset-cmd; status = "okay"; partitions { diff --git a/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.yaml b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.yaml index e4b7d1b3334..d566de9a4ca 100644 --- a/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.yaml +++ b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.yaml @@ -16,6 +16,5 @@ supported: - netif:eth - qspi - memc - - usb_cdc - usb_device vendor: st diff --git a/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7_defconfig b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7_defconfig index 69659b1c01e..7339b469acc 100644 --- a/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7_defconfig +++ b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7_defconfig @@ -7,9 +7,6 @@ CONFIG_POWER_SUPPLY_DIRECT_SMPS=y # Enable GPIO CONFIG_GPIO=y -# Enable clocks -CONFIG_CLOCK_CONTROL=y - # Enable MPU CONFIG_ARM_MPU=y @@ -23,6 +20,3 @@ CONFIG_SERIAL=y # Console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y - -# Enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32h750b_dk/Kconfig.defconfig b/boards/st/stm32h750b_dk/Kconfig.defconfig new file mode 100644 index 00000000000..bcc1ec705eb --- /dev/null +++ b/boards/st/stm32h750b_dk/Kconfig.defconfig @@ -0,0 +1,17 @@ +# STM32H750B DISCOVERY board configuration + +# Copyright (c) 2024 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_STM32H750B_DK + +if DISPLAY + +# MEMC needs to be enabled in order to store +# display buffer to external SDRAM connected to FMC +config MEMC + default y + +endif # DISPLAY + +endif # BOARD_STM32H750B_DK diff --git a/boards/st/stm32h750b_dk/board.cmake b/boards/st/stm32h750b_dk/board.cmake index 6500e7b1a4a..479fe1abc2e 100644 --- a/boards/st/stm32h750b_dk/board.cmake +++ b/boards/st/stm32h750b_dk/board.cmake @@ -1,7 +1,17 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +if(CONFIG_STM32_MEMMAP) +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +board_runner_args(stm32cubeprogrammer "--extload=MT25TL01G_STM32H750B-DISCO.stldr") +else() +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw" ) +endif() + board_runner_args(jlink "--device=STM32H735IG" "--speed=4000") board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32h750b_dk/doc/index.rst b/boards/st/stm32h750b_dk/doc/index.rst index e450488ed4d..3e2cd3d009e 100644 --- a/boards/st/stm32h750b_dk/doc/index.rst +++ b/boards/st/stm32h750b_dk/doc/index.rst @@ -110,7 +110,7 @@ USB port, then run a serial host program to connect with the board. For example: $ minicom -b 115200 -D /dev/ttyACM0 You can then build and flash applications in the usual way. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -128,7 +128,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm32h750b_dk/stm32h750b_dk.dts b/boards/st/stm32h750b_dk/stm32h750b_dk.dts index bb90724dead..14a6fe1fef1 100644 --- a/boards/st/stm32h750b_dk/stm32h750b_dk.dts +++ b/boards/st/stm32h750b_dk/stm32h750b_dk.dts @@ -7,6 +7,7 @@ /dts-v1/; #include #include +#include "arduino_r3_connector.dtsi" #include / { @@ -19,6 +20,7 @@ zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,flash-controller = &mt25ql512ab1; + zephyr,display = <dc; }; sdram2: sdram@d0000000 { @@ -29,6 +31,14 @@ zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; }; + ext_memory: memory@90000000 { + compatible = "zephyr,memory-region"; + reg = <0x90000000 DT_SIZE_M(256)>; /* max addressable area */ + zephyr,memory-region = "EXTMEM"; + /* The ATTR_MPU_EXTMEM attribut causing a MPU FAULT */ + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>; + }; + leds { compatible = "gpio-leds"; red_led: led_1 { @@ -54,7 +64,7 @@ led0 = &green_led; led1 = &red_led; sw0 = &user_button; - spi-flash0 = &mt25ql512ab1; + die-temp0 = &die_temp; }; }; @@ -68,6 +78,45 @@ status = "okay"; }; +<dc { + pinctrl-0 = <<dc_r0_pi15 <dc_r1_pj0 <dc_r2_pj1 <dc_r3_ph9 + <dc_r4_pj3 <dc_r5_pj4 <dc_r6_pj5 <dc_r7_pj6 + <dc_g0_pj7 <dc_g1_pj8 <dc_g2_pj9 <dc_g3_pj10 + <dc_g4_pj11 <dc_g5_pi0 <dc_g6_pi1 <dc_g7_pk2 + <dc_b0_pj12 <dc_b1_pj13 <dc_b2_pj14 <dc_b3_pj15 + <dc_b4_pk3 <dc_b5_pk4 <dc_b6_pk5 <dc_b7_pk6 + <dc_de_pk7 <dc_clk_pi14 <dc_hsync_pi12 <dc_vsync_pi9>; + pinctrl-names = "default"; + + disp-on-gpios = <&gpiod 7 GPIO_ACTIVE_HIGH>; + + ext-sdram = <&sdram2>; + status = "okay"; + + clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>, + <&rcc STM32_SRC_PLL3_R NO_SEL>; + + width = <480>; + height = <272>; + pixel-format = ; + display-timings { + compatible = "zephyr,panel-timing"; + de-active = <1>; + pixelclk-active = <0>; + hsync-active = <0>; + vsync-active = <0>; + hsync-len = <1>; + vsync-len = <10>; + hback-porch = <43>; + vback-porch = <12>; + hfront-porch = <8>; + vfront-porch = <4>; + }; + def-back-color-red = <0xFF>; + def-back-color-green = <0xFF>; + def-back-color-blue = <0xFF>; +}; + &pll { div-m = <5>; mul-n = <192>; @@ -78,6 +127,16 @@ status = "okay"; }; +&pll3 { + div-m = <5>; + mul-n = <192>; + div-p = <2>; + div-q = <20>; + div-r = <99>; + clocks = <&clk_hse>; + status = "okay"; +}; + &rcc { clocks = <&pll>; clock-frequency = ; @@ -103,7 +162,7 @@ &quadspi_bk1_io2_pf7 &quadspi_bk1_io3_pf6 &quadspi_bk2_io0_ph2 &quadspi_bk2_io1_ph3 &quadspi_bk2_io2_pg9 &quadspi_bk2_io3_pg14>; - flash-id = <1>; + dual-flash; status = "okay"; mt25ql512ab1: qspi-nor-flash-1@90000000 { @@ -111,16 +170,17 @@ reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */ qspi-max-frequency = <72000000>; spi-bus-width = <4>; + reset-cmd; status = "okay"; partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - partition@0 { - reg = <0x0 DT_SIZE_M(64)>; - }; + partition@0 { + reg = <0x0 DT_SIZE_M(64)>; + }; }; }; @@ -151,7 +211,7 @@ status = "okay"; power-up-delay = <100>; num-auto-refresh = <8>; - mode-register = <0x220>; + mode-register = <0x230>; refresh-rate = <0x603>; bank@1 { reg = <1>; @@ -162,7 +222,7 @@ STM32_FMC_SDRAM_CAS_3 STM32_FMC_SDRAM_SDCLK_PERIOD_2 STM32_FMC_SDRAM_RBURST_ENABLE - STM32_FMC_SDRAM_RPIPE_0>; + STM32_FMC_SDRAM_RPIPE_1>; st,sdram-timing = <2 7 4 7 2 2 2>; }; }; @@ -173,3 +233,13 @@ <&rcc STM32_SRC_LSE RTC_SEL(1)>; status = "okay"; }; + +&die_temp { + status = "okay"; +}; + +&adc3 { + st,adc-clock-source = ; + st,adc-prescaler = <4>; + status = "okay"; +}; diff --git a/boards/st/stm32h750b_dk/stm32h750b_dk.yaml b/boards/st/stm32h750b_dk/stm32h750b_dk.yaml index ddca938bb51..2ef5ca14dcd 100644 --- a/boards/st/stm32h750b_dk/stm32h750b_dk.yaml +++ b/boards/st/stm32h750b_dk/stm32h750b_dk.yaml @@ -14,4 +14,5 @@ supported: - dma - flash - rtc + - memc vendor: st diff --git a/boards/st/stm32h750b_dk/stm32h750b_dk_defconfig b/boards/st/stm32h750b_dk/stm32h750b_dk_defconfig index 08add3eb2c6..88336dbe699 100644 --- a/boards/st/stm32h750b_dk/stm32h750b_dk_defconfig +++ b/boards/st/stm32h750b_dk/stm32h750b_dk_defconfig @@ -18,9 +18,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32h7b3i_dk/board.cmake b/boards/st/stm32h7b3i_dk/board.cmake index d13c9c0e976..88f340c9331 100644 --- a/boards/st/stm32h7b3i_dk/board.cmake +++ b/boards/st/stm32h7b3i_dk/board.cmake @@ -1,8 +1,18 @@ # Copyright (c) 2022 Byte-Lab d.o.o. # SPDX-License-Identifier: Apache-2.0 +# keep first +if(CONFIG_STM32_MEMMAP) +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +board_runner_args(stm32cubeprogrammer "--extload=MX25LM51245G_STM32H7B3I-DISCO.stldr") +else() +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw" ) +endif() + board_runner_args(jlink "--device=STM32H7B3LI" "--speed=4000") board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32h7b3i_dk/doc/index.rst b/boards/st/stm32h7b3i_dk/doc/index.rst index dd1c6317e78..954f4342d56 100644 --- a/boards/st/stm32h7b3i_dk/doc/index.rst +++ b/boards/st/stm32h7b3i_dk/doc/index.rst @@ -196,6 +196,8 @@ default communication settings are 115200 8N1. Programming and Debugging ************************* +STM32H7B3I Discovery kit includes an STLINK-V3E embedded debug tool interface. + Applications for the ``stm32h7b3i_dk`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -203,8 +205,16 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -STM32H7B3I Discovery kit includes an STLINK-V3E embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing may depend on the SoC option bytes configuration, which can be checked and updated using `STM32CubeProgrammer`_. @@ -215,7 +225,7 @@ Flashing an application to STM32H7B3I First, connect the STM32H7B3I Discovery kit to your host computer using the USB port to prepare it for flashing. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -238,7 +248,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts b/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts index 88685817706..95325e254b5 100644 --- a/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts +++ b/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts @@ -59,6 +59,14 @@ zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; }; + octo_nor: memory@90000000 { + compatible = "zephyr,memory-region"; + reg = <0x90000000 DT_SIZE_M(64)>; + zephyr,memory-region = "EXTMEM"; + /* The ATTR_MPU_EXTMEM attribut causing a MPU FAULT */ + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>; + }; + transceiver0: can-phy0 { compatible = "microchip,mcp2562fd", "can-transceiver-gpio"; standby-gpios = <&gpioh 8 GPIO_ACTIVE_HIGH>; @@ -70,7 +78,6 @@ led0 = &blue_led; led1 = &red_led; sw0 = &user_button; - spi-flash0 = &mx25lm51245; }; }; diff --git a/boards/st/stm32h7b3i_dk/stm32h7b3i_dk_defconfig b/boards/st/stm32h7b3i_dk/stm32h7b3i_dk_defconfig index bb3b8c0178c..8ce14cee878 100644 --- a/boards/st/stm32h7b3i_dk/stm32h7b3i_dk_defconfig +++ b/boards/st/stm32h7b3i_dk/stm32h7b3i_dk_defconfig @@ -18,11 +18,5 @@ CONFIG_UART_CONSOLE=y # Enable GPIO CONFIG_GPIO=y -# Enable clocks -CONFIG_CLOCK_CONTROL=y - -# Enable pinctrl -CONFIG_PINCTRL=y - # Enable SMPS CONFIG_POWER_SUPPLY_DIRECT_SMPS=y diff --git a/boards/st/stm32h7s78_dk/Kconfig.defconfig b/boards/st/stm32h7s78_dk/Kconfig.defconfig new file mode 100644 index 00000000000..d8a0c6ecdcd --- /dev/null +++ b/boards/st/stm32h7s78_dk/Kconfig.defconfig @@ -0,0 +1,17 @@ +# STM32H7S78 DISCOVERY KIT board configuration +# +# Copyright (c) 2024 STMicroelectronics +# +# SPDX-License-Identifier: Apache-2.0 +# + +if BOARD_STM32H7S78_DK + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_STM32H7S78_DK diff --git a/boards/st/stm32h7s78_dk/Kconfig.stm32h7s78_dk b/boards/st/stm32h7s78_dk/Kconfig.stm32h7s78_dk new file mode 100644 index 00000000000..d3c5737a289 --- /dev/null +++ b/boards/st/stm32h7s78_dk/Kconfig.stm32h7s78_dk @@ -0,0 +1,9 @@ +# STM32H7S78-DK Discovery kit board configuration +# +# Copyright (c) 2024 STMicroelectronics +# +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_STM32H7S78_DK + select SOC_STM32H7S7XX diff --git a/boards/st/stm32h7s78_dk/arduino_r3_connector.dtsi b/boards/st/stm32h7s78_dk/arduino_r3_connector.dtsi new file mode 100644 index 00000000000..c1d06e17bc1 --- /dev/null +++ b/boards/st/stm32h7s78_dk/arduino_r3_connector.dtsi @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpioc 0 0>, /* A0 */ + <1 0 &gpioc 2 0>, /* A1 */ + <2 0 &gpioc 3 0>, /* A2 */ + <3 0 &gpiof 12 0>, /* A3 */ + <4 0 &gpiof 13 0>, /* A4 */ + <5 0 &gpioc 1 0>, /* A5 */ + <6 0 &gpioe 7 0>, /* D0 */ + <7 0 &gpioe 8 0>, /* D1 */ + <8 0 &gpiof 1 0>, /* D2 */ + <9 0 &gpiod 12 0>, /* D3 */ + <10 0 &gpiof 2 0>, /* D4 */ + <11 0 &gpiod 13 0>, /* D5 */ + <12 0 &gpiod 15 0>, /* D6 */ + <13 0 &gpiof 3 0>, /* D7 */ + <14 0 &gpiof 4 0>, /* D8 */ + <15 0 &gpiof 6 0>, /* D9 */ + <16 0 &gpiof 8 0>, /* D10 */ + <17 0 &gpioe 14 0>, /* D11 */ + <18 0 &gpioe 13 0>, /* D12 */ + <19 0 &gpioe 12 0>, /* D13 */ + <20 0 &gpiob 9 0>, /* D14 */ + <21 0 &gpiob 6 0>; /* D15 */ + }; +}; + +arduino_spi: &spi4 {}; +arduino_i2c: &i2c1 {}; diff --git a/boards/st/stm32h7s78_dk/board.cmake b/boards/st/stm32h7s78_dk/board.cmake new file mode 100644 index 00000000000..79bb6fcc70b --- /dev/null +++ b/boards/st/stm32h7s78_dk/board.cmake @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) + +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +# FIXME: openocd runner not yet available. +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/st/stm32h7s78_dk/board.yml b/boards/st/stm32h7s78_dk/board.yml new file mode 100644 index 00000000000..c17be71480c --- /dev/null +++ b/boards/st/stm32h7s78_dk/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32h7s78_dk + vendor: st + socs: + - name: stm32h7s7xx diff --git a/boards/st/stm32h7s78_dk/doc/img/stm32h7s78_dk.jpg b/boards/st/stm32h7s78_dk/doc/img/stm32h7s78_dk.jpg new file mode 100644 index 00000000000..523ff89970c Binary files /dev/null and b/boards/st/stm32h7s78_dk/doc/img/stm32h7s78_dk.jpg differ diff --git a/boards/st/stm32h7s78_dk/doc/index.rst b/boards/st/stm32h7s78_dk/doc/index.rst new file mode 100644 index 00000000000..2352fde0fc9 --- /dev/null +++ b/boards/st/stm32h7s78_dk/doc/index.rst @@ -0,0 +1,306 @@ +.. _stm32h7s78_dk_board: + +ST STM32H7S78-DK Discovery +########################## + +Overview +******** + +The STM32H7S78-DK Discovery kit is designed as a complete demonstration and +development platform for STMicroelectronics Arm |reg| Cortex |reg|-M7 core-based +STM32H7S7L8H6H microcontroller with TrustZone |reg|. Here are some highlights of +the STM32H7S78-DK Discovery board: + + +- STM32H7S7L8H6H microcontroller featuring 64Kbytes of Flash memory and 620 Kbytes of SRAM in 225-pin TFBGA package +- USB Type-C |trade| Host and device with USB power-delivery controller +- SAI Audio DAC stereo with one audio jacks for input/output, +- ST MEMS digital microphone with PDM interface +- Octo-SPI interface connected to 512Mbit Octo-SPI NORFlash memory device (MX66UW1G45GXD100 from MACRONIX) +- 10/100-Mbit Ethernet, + +- Board connectors + + - STMod+ expansion connector with fan-out expansion board for Wi‑Fi |reg|, Grove and mikroBUS |trade| compatible connectors + - Pmod |trade| expansion connector + - Audio MEMS daughterboard expansion connector + - ARDUINO |reg| Uno V3 expansion connector + +- Flexible power-supply options + + - ST-LINK + - USB VBUS + - external sources + +- On-board STLINK-V3E debugger/programmer with USB re-enumeration capability: + + - mass storage + - Virtual COM port + - debug port + +- 4 user LEDs +- User and reset push-buttons + +.. image:: img/stm32h7s78_dk.jpg + :align: center + :alt: STM32H7S78-DK Discovery + +More information about the board can be found at the `STM32H7S78-DK Discovery website`_. + +Hardware +******** + +The STM32H7S7xx devices are a high-performance microcontrollers family (STM32H7 +Series) based on the high-performance Arm |reg| Cortex |reg|-M7 32-bit RISC core. +They operate at a frequency of up to 500 MHz. + +- Core: ARM |reg| 32-bit Cortex |reg| -M7 CPU with TrustZone |reg| and FPU. +- Performance benchmark: + + - 1284 DMPIS/MHz (Dhrystone 2.1) + +- Security + + - Arm |reg| TrustZone |reg| with ARMv8-M mainline security extension + - Up to 8 configurable SAU regions + - TrustZone |reg| aware and securable peripherals + - Flexible lifecycle scheme with secure debug authentication + - Preconfigured immutable root of trust (ST-iROT) + - SFI (secure firmware installation) + - Secure data storage with hardware unique key (HUK) + - Secure firmware upgrade support with TF-M + - 2x AES coprocessors including one with DPA resistance + - Public key accelerator, DPA resistant + - On-the-fly decryption of Octo-SPI external memories + - HASH hardware accelerator + - True random number generator, NIST SP800-90B compliant + - 96-bit unique ID + - Active tampers + - True Random Number Generator (RNG) NIST SP800-90B compliant + +- Clock management: + + - 24 MHz crystal oscillator (HSE) + - 32768 Hz crystal oscillator for RTC (LSE) + - Internal 64 MHz (HSI) trimmable by software + - Internal low-power 32 kHz RC (LSI)( |plusminus| 5%) + - Internal 4 MHz oscillator (CSI), trimmable by software + - Internal 48 MHz (HSI48) with recovery system + - 3 PLLs for system clock, USB, audio, ADC + +- Power management + + - Embedded regulator (LDO) with three configurable range output to supply the digital circuitry + - Embedded SMPS step-down converter + +- RTC with HW calendar, alarms and calibration +- Up to 152 fast I/Os, most 5 V-tolerant, up to 10 I/Os with independent supply down to 1.08 V +- Up to 16 timers and 2 watchdogs + + - 16x 16-bit + - 4x 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input + - 5x 16-bit low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - 1x SysTick timer + +- Memories + + - Up to 64KB Flash, 2 banks read-while-write + - 1 Kbyte OTP (one-time programmable) + - 640 KB of SRAM including 64 KB with hardware parity check and 320 Kbytes with flexible ECC + - 4 Kbytes of backup SRAM available in the lowest power modes + - Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, FRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories + - 2x OCTOSPI memory interface with on-the-fly decryption and support for serial PSRAM/NAND/NOR, Hyper RAM/Flash frame formats + - 1x HEXASPI memory interface with on-the-fly decryption and support for serial PSRAM/NAND/NOR, Hyper RAM/Flash frame formats + - 2x SD/SDIO/MMC interfaces + +- Rich analog peripherals (independent supply) + + - 2x 12-bit ADC with up to 5 MSPS in 12-bit + - 1x Digital temperature sensor + +- 35x communication interfaces + + - 1x USB Type-C / USB power-delivery controller + - 1x USB OTG full-speed with PHY + - 1x USB OTG high-speed with PHY + - 3x I2C FM+ interfaces (SMBus/PMBus) + - 1x I3C interface + - 7x U(S)ARTS (ISO7816 interface, LIN, IrDA, modem control) + - 2x LP UART + - 6x SPIs including 3 muxed with full-duplex I2S + - 2x SAI + - 2x FDCAN + - 2x SD/SDIO/MMC interface + - 2x 16 channel DMA controllers + - 1x 8- to 16- bit camera interface + - 1x HDMI-CEC + - 1x Ethernel MAC interface with DMA controller + - 1x 16-bit parallel slave synchronous-interface + - 1x SPDIF-IN interface + - 1x MDIO slave interface + +- CORDIC for trigonometric functions acceleration +- FMAC (filter mathematical accelerator) +- CRC calculation unit +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| + + +More information about STM32H7S7 can be found here: + +- `STM32H7Sx on www.st.com`_ +- `STM32H7Sx reference manual`_ + +Supported Features +================== + +The Zephyr STM32H7S78_DK board configuration supports the following +hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi bus | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig and dts files: + +- Secure target: + + - :zephyr_file:`boards/st/stm32h7s78_dk/stm32h7s78_dk_defconfig` + - :zephyr_file:`boards/st/stm32h7s78_dk/stm32h7s78_dk.dts` + +Zephyr board options +==================== + +The STM32HS7 is a SoC with Cortex-M7 architecture. Zephyr provides support +for building for Secure firmware. + +The BOARD options are summarized below: + ++----------------------+-----------------------------------------------+ +| BOARD | Description | ++======================+===============================================+ +| stm32h7s78_dk | For building Secure firmware | ++----------------------+-----------------------------------------------+ + +Connections and IOs +=================== + +STM32H7S78-DK Discovery Board has 12 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `STM32H7S78-DK Discovery board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- USART_4 TX/RX : PD1/PD0 (VCP) +- USART_7 TX/RX : PE8/PE7 (Arduino USART7) +- USER_PB : PC13 +- LD1 (green) : PO1 +- LD2 (orange) : PO5 +- LD3 (red) : PM2 +- LD4 (blue) : PM3 +- ADC1 channel 6 input : PF12 + +System Clock +------------ + +STM32H7S78-DK System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at +500MHz, driven by 24MHz external oscillator (HSE). + +Serial Port +----------- + +STM32H7S78-DK Discovery board has 2 U(S)ARTs. The Zephyr console output is +assigned to USART4. Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +STM32H7S78-DK Discovery board includes an ST-LINK/V3E embedded debug tool interface. + +Applications for the ``stm32h7s78_dk`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Flashing an application to STM32H7S78-DK Discovery +-------------------------------------------------- + +Connect the STM32H7S78-DK Discovery to your host computer using the USB port. +Then build and flash an application. Here is an example for the +:zephyr:code-sample:`hello_world` application. + +Run a serial host program to connect with your Nucleo board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash the application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32h7s78_dk + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! stm32h7s78_dk + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32h7s78_dk + :maybe-skip-config: + :goals: debug + +.. _STM32H7S78-DK Discovery website: + https://www.st.com/en/evaluation-tools/stm32h7s78-dk.html + +.. _STM32H7S78-DK Discovery board User Manual: + https://www.st.com/en/evaluation-tools/stm32h7s78-dk.html + +.. _STM32H7Sx on www.st.com: + https://www.st.com/en/evaluation-tools/stm32h7s78-dk.html + +.. _STM32H7Sx reference manual: + https://www.st.com/resource/en/reference_manual/rm0477-stm32h7rx7sx-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts b/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts new file mode 100644 index 00000000000..6cd70cbe60d --- /dev/null +++ b/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts @@ -0,0 +1,186 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include "arduino_r3_connector.dtsi" +#include + +/ { + model = "STMicroelectronics STM32H7S78 DISCOVERY KIT board"; + compatible = "st,stm32h7s78-dk"; + + chosen { + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; + zephyr,flash = &flash0; + zephyr,sram = &sram0; + }; + + leds { + compatible = "gpio-leds"; + green_led: led_1 { + gpios = <&gpioo 1 GPIO_ACTIVE_LOW>; + label = "User LD1"; + }; + orange_led: led_2 { + gpios = <&gpioo 5 GPIO_ACTIVE_LOW>; + label = "User LD2"; + }; + red_led: led_3 { + gpios = <&gpiom 2 GPIO_ACTIVE_LOW>; + label = "User LD3"; + }; + blue_led: led_4 { + gpios = <&gpiom 3 GPIO_ACTIVE_LOW>; + label = "User LD4"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button: button { + label = "User"; + gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; + + aliases { + led0 = &blue_led; + sw0 = &user_button; + watchdog0 = &iwdg; + die-temp0 = &die_temp; + volt-sensor0 = &vref; + volt-sensor1 = &vbat; + }; +}; + +&clk_hsi48 { + status = "okay"; +}; + +&clk_lse { + status = "okay"; +}; + +&clk_hse { + clock-frequency = ; + hse-bypass; /* X3 is a 24MHz oscillator on PH0 */ + status = "okay"; +}; + +&pll { + div-m = <12>; + mul-n = <250>; + div-p = <2>; + div-q = <2>; + div-r = <2>; + div-s = <2>; + div-t = <2>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + dcpre = <1>; + hpre = <1>; + ppre1 = <2>; + ppre2 = <2>; + ppre4 = <2>; + ppre5 = <2>; +}; + +&uart4 { + pinctrl-0 = <&uart4_tx_pd1 &uart4_rx_pd0>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&uart7 { + pinctrl-0 = <&uart7_tx_pe8 &uart7_rx_pe7>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&timers2 { + st,prescaler = <10000>; + status = "okay"; + + pwm2: pwm { + status = "okay"; + pinctrl-0 = <&tim2_ch4_pa3>; + pinctrl-names = "default"; + }; +}; + +&timers3 { + st,prescaler = <10000>; + status = "okay"; + + pwm3: pwm { + status = "okay"; + pinctrl-0 = <&tim3_ch2_pb5>; + pinctrl-names = "default"; + }; +}; + +&rng { + status = "okay"; +}; + +&iwdg { + status = "okay"; +}; + +&wwdg { + status = "okay"; +}; + +&adc1 { + pinctrl-0 = <&adc1_inp6_pf12>; /* Arduino A3 */ + pinctrl-names = "default"; + st,adc-clock-source = ; + st,adc-prescaler = <4>; + status = "okay"; +}; + +&adc2 { + pinctrl-0 = <&adc2_inp2_pf13>; /* Arduino A4 */ + pinctrl-names = "default"; + st,adc-clock-source = ; + st,adc-prescaler = <4>; + status = "okay"; +}; + +&spi4 { + pinctrl-0 = <&spi4_nss_pe4 &spi4_sck_pe12 + &spi4_miso_pe13 &spi4_mosi_pe14>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb9>; + pinctrl-names = "default"; +}; + +&die_temp { + status = "okay"; +}; + +&vref { + status = "okay"; +}; + +&vbat { + status = "okay"; +}; diff --git a/boards/st/stm32h7s78_dk/stm32h7s78_dk.yaml b/boards/st/stm32h7s78_dk/stm32h7s78_dk.yaml new file mode 100644 index 00000000000..e48895cbce1 --- /dev/null +++ b/boards/st/stm32h7s78_dk/stm32h7s78_dk.yaml @@ -0,0 +1,16 @@ +identifier: stm32h7s78_dk +name: ST STM32H7S78 Discovery Kit +type: mcu +arch: arm +toolchain: + - zephyr +ram: 640 +flash: 64 +supported: + - arduino_gpio + - gpio + - uart + - watchdog + - entropy + - adc +vendor: st diff --git a/boards/st/stm32h7s78_dk/stm32h7s78_dk_defconfig b/boards/st/stm32h7s78_dk/stm32h7s78_dk_defconfig new file mode 100644 index 00000000000..532d9f8e2d3 --- /dev/null +++ b/boards/st/stm32h7s78_dk/stm32h7s78_dk_defconfig @@ -0,0 +1,20 @@ +# Copyright (c) 2024 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +# Enable SMPS +CONFIG_POWER_SUPPLY_DIRECT_SMPS=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# enable uart driver +CONFIG_SERIAL=y +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# enable GPIO +CONFIG_GPIO=y diff --git a/boards/st/stm32h7s78_dk/support/openocd.cfg b/boards/st/stm32h7s78_dk/support/openocd.cfg new file mode 100644 index 00000000000..b32c9f26c2c --- /dev/null +++ b/boards/st/stm32h7s78_dk/support/openocd.cfg @@ -0,0 +1,41 @@ +source [find interface/stlink-dap.cfg] +transport select "dapdirect_swd" + +set WORKAREASIZE 0x8000 +set CHIPNAME STM32H7S7XX +set BOARDNAME STM32H7S78_DK + +# Enable debug when in low power modes +set ENABLE_LOW_POWER 1 + +# Stop Watchdog counters when halt +set STOP_WATCHDOG 1 + +# Reset configuration +# use hardware reset, connect under reset +# connect_assert_srst needed if low power mode application running (WFI...) +# reset_config srst_only srst_nogate connect_assert_srst + +#set CONNECT_UNDER_RESET 1 +#set CORE_RESET 0 + +source [find target/stm32h7rx.cfg] + + +$_CHIPNAME.cpu0 configure -event gdb-attach { + echo "Debugger attaching: halting execution" + gdb_breakpoint_override hard +} + +$_CHIPNAME.cpu0 configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} + +# Due to the use of connect_assert_srst, running gdb requires +# to reset halt just after openocd init. +rename init old_init +proc init {} { + old_init + reset halt +} diff --git a/boards/st/stm32l1_disco/board.cmake b/boards/st/stm32l1_disco/board.cmake index 6a1eecb756b..c8967fe8139 100644 --- a/boards/st/stm32l1_disco/board.cmake +++ b/boards/st/stm32l1_disco/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32L151RB" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32l1_disco/doc/index.rst b/boards/st/stm32l1_disco/doc/index.rst index 30911141f93..20d6067b966 100644 --- a/boards/st/stm32l1_disco/doc/index.rst +++ b/boards/st/stm32l1_disco/doc/index.rst @@ -138,6 +138,8 @@ For more details please refer to `STM32L1DISCOVERY board User Manual`_. Programming and Debugging ************************* +STM32L1DISCOVERY and STM32L152CDISCOVERY boards include an ST-LINK/V2 embedded debug tool interface. + Applications for the ``stm32l1_disco`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -145,9 +147,16 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -STM32L1DISCOVERY and STM32L152CDISCOVERY boards include an ST-LINK/V2 embedded -debug tool interface. This interface is supported by the openocd version -included in the Zephyr SDK. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application ----------------------- @@ -189,3 +198,6 @@ References .. _STM32L152CDISCOVERY board User Manual: https://www.st.com/resource/en/user_manual/um1079-discovery-kit-with-stm32l152rc-mcu-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/stm32l1_disco/stm32l152c_disco_defconfig b/boards/st/stm32l1_disco/stm32l152c_disco_defconfig index fd0afcb9d74..08a82bd301d 100644 --- a/boards/st/stm32l1_disco/stm32l152c_disco_defconfig +++ b/boards/st/stm32l1_disco/stm32l152c_disco_defconfig @@ -9,9 +9,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32l1_disco/stm32l1_disco_defconfig b/boards/st/stm32l1_disco/stm32l1_disco_defconfig index fd0afcb9d74..08a82bd301d 100644 --- a/boards/st/stm32l1_disco/stm32l1_disco_defconfig +++ b/boards/st/stm32l1_disco/stm32l1_disco_defconfig @@ -9,9 +9,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32l476g_disco/board.cmake b/boards/st/stm32l476g_disco/board.cmake index e0f8d547525..76b5877ddfe 100644 --- a/boards/st/stm32l476g_disco/board.cmake +++ b/boards/st/stm32l476g_disco/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32L476VG" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32l476g_disco/doc/index.rst b/boards/st/stm32l476g_disco/doc/index.rst index ef40802a709..94a6e9ce24f 100644 --- a/boards/st/stm32l476g_disco/doc/index.rst +++ b/boards/st/stm32l476g_disco/doc/index.rst @@ -162,11 +162,21 @@ Default settings are 115200 8N1. Programming and Debugging ************************* +STM32L476G Discovery board includes an ST-LINK/V2-1 embedded debug tool interface. + Flashing ======== -STM32L476G Discovery board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to STM32L476G Discovery ----------------------------------------------- @@ -180,7 +190,7 @@ board. For example: $ minicom -D /dev/ttyACM0 Then, build and flash in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -197,7 +207,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -216,3 +226,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32L476 reference manual: https://www.st.com/resource/en/reference_manual/DM00083560.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/stm32l476g_disco/stm32l476g_disco_defconfig b/boards/st/stm32l476g_disco/stm32l476g_disco_defconfig index 82ee7285d52..3fe5e4f9882 100644 --- a/boards/st/stm32l476g_disco/stm32l476g_disco_defconfig +++ b/boards/st/stm32l476g_disco/stm32l476g_disco_defconfig @@ -12,12 +12,6 @@ CONFIG_SERIAL=y # enable GPIO CONFIG_GPIO=y -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - # console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32l496g_disco/board.cmake b/boards/st/stm32l496g_disco/board.cmake index b8a1001ba60..b6f4be86151 100644 --- a/boards/st/stm32l496g_disco/board.cmake +++ b/boards/st/stm32l496g_disco/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32L496AG" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32l496g_disco/doc/index.rst b/boards/st/stm32l496g_disco/doc/index.rst index 576c07bc2cc..15461fb1a71 100644 --- a/boards/st/stm32l496g_disco/doc/index.rst +++ b/boards/st/stm32l496g_disco/doc/index.rst @@ -198,12 +198,21 @@ Default settings are 115200 8N1. Programming and Debugging ************************* +STM32L496G Discovery board includes an ST-LINK/V2-1 embedded debug tool interface. + Flashing ======== -STM32L496G Discovery board includes an ST-LINK/V2-1 embedded debug -tool interface. This interface is supported by openocd version -v0.10.0, which has been available since Zephyr SDK v0.9.2. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Applications for the ``stm32l496g_disco`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` @@ -221,7 +230,7 @@ board. For example: $ minicom -D /dev/ttyACM0 Then, build and flash in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -238,7 +247,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -257,3 +266,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32L496 reference manual: https://www.st.com/resource/en/reference_manual/DM00083560.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/stm32l496g_disco/stm32l496g_disco.dts b/boards/st/stm32l496g_disco/stm32l496g_disco.dts index e2a70f6163d..a6d1e876f4e 100644 --- a/boards/st/stm32l496g_disco/stm32l496g_disco.dts +++ b/boards/st/stm32l496g_disco/stm32l496g_disco.dts @@ -68,7 +68,6 @@ sw4 = &joy_left; volt-sensor0 = &vref; volt-sensor1 = &vbat; - spi-flash0 = &mx25r6435; }; }; diff --git a/boards/st/stm32l496g_disco/stm32l496g_disco_defconfig b/boards/st/stm32l496g_disco/stm32l496g_disco_defconfig index c7582ad0d95..dbb282919fa 100644 --- a/boards/st/stm32l496g_disco/stm32l496g_disco_defconfig +++ b/boards/st/stm32l496g_disco/stm32l496g_disco_defconfig @@ -12,12 +12,6 @@ CONFIG_SERIAL=y # enable GPIOs CONFIG_GPIO=y -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - # console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32l4r9i_disco/board.cmake b/boards/st/stm32l4r9i_disco/board.cmake index c88ae7d0783..ea87b4f9548 100644 --- a/boards/st/stm32l4r9i_disco/board.cmake +++ b/boards/st/stm32l4r9i_disco/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32L4R9AI" "--speed=4000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32l4r9i_disco/doc/index.rst b/boards/st/stm32l4r9i_disco/doc/index.rst index e2053313122..6fadc331d45 100644 --- a/boards/st/stm32l4r9i_disco/doc/index.rst +++ b/boards/st/stm32l4r9i_disco/doc/index.rst @@ -91,15 +91,25 @@ ST-LINK Virtual COM port interface. Default communication settings are 115200 8N Programming and Debugging ************************* -Flashing -======== - The STM32L4R9I Discovery board includes an ST-LINK/V2-1 debug tool. Applications for the ``stm32l4r9i_disco`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). +Flashing +======== + +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink Flashing an application to STM32L4R9I Discovery ----------------------------------------------- @@ -112,7 +122,7 @@ USB port, then run a serial host program to connect with the board. For example: $ minicom -b 115200 -D /dev/ttyACM0 You can then build and flash applications in the usual way. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -130,7 +140,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -148,3 +158,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32L4R5xx/R7xx/R9xx datasheet: https://www.st.com/resource/en/datasheet/stm32l4r5vi.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/stm32l4r9i_disco/stm32l4r9i_disco.dts b/boards/st/stm32l4r9i_disco/stm32l4r9i_disco.dts index 3d54fbc3cdf..49737c68c8f 100644 --- a/boards/st/stm32l4r9i_disco/stm32l4r9i_disco.dts +++ b/boards/st/stm32l4r9i_disco/stm32l4r9i_disco.dts @@ -44,7 +44,6 @@ die-temp0 = &die_temp; volt-sensor0 = &vref; volt-sensor1 = &vbat; - spi-flash0 = &mx25lm51245; }; }; diff --git a/boards/st/stm32l4r9i_disco/stm32l4r9i_disco_defconfig b/boards/st/stm32l4r9i_disco/stm32l4r9i_disco_defconfig index ac681be2af0..9db0a75110f 100644 --- a/boards/st/stm32l4r9i_disco/stm32l4r9i_disco_defconfig +++ b/boards/st/stm32l4r9i_disco/stm32l4r9i_disco_defconfig @@ -15,9 +15,3 @@ CONFIG_UART_CONSOLE=y # Enable GPIO CONFIG_GPIO=y - -# Enable clocks -CONFIG_CLOCK_CONTROL=y - -# Enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32l562e_dk/Kconfig.defconfig b/boards/st/stm32l562e_dk/Kconfig.defconfig index ed9a04edc17..b0dc8f3bab8 100644 --- a/boards/st/stm32l562e_dk/Kconfig.defconfig +++ b/boards/st/stm32l562e_dk/Kconfig.defconfig @@ -25,4 +25,15 @@ config BT_HCI_VS endif # BT +config MIPI_DBI_STM32_FMC_MEM_BARRIER + default n if MIPI_DBI_STM32_FMC + +if DISPLAY + +choice ST7789V_PIXEL_FORMAT + default ST7789V_BGR565 +endchoice + +endif # DISPLAY + endif # BOARD_STM32L562E_DK diff --git a/boards/st/stm32l562e_dk/board.cmake b/boards/st/stm32l562e_dk/board.cmake index 479f8dcc036..15e7afc15c0 100644 --- a/boards/st/stm32l562e_dk/board.cmake +++ b/boards/st/stm32l562e_dk/board.cmake @@ -12,10 +12,11 @@ if(CONFIG_BUILD_WITH_TFM) endif() endif() - -board_runner_args(pyocd "--target=stm32l562qeixq") +# keep first board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +board_runner_args(pyocd "--target=stm32l562qeixq") -include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +# keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/st/stm32l562e_dk/doc/index.rst b/boards/st/stm32l562e_dk/doc/index.rst index 370526ac14b..55fd91a34fa 100644 --- a/boards/st/stm32l562e_dk/doc/index.rst +++ b/boards/st/stm32l562e_dk/doc/index.rst @@ -223,7 +223,7 @@ The BOARD options are summarized below: +------------------------------+-------------------------------------------+ Here are the instructions to build Zephyr with a non-secure configuration, -using `tfm_ipc_` sample: +using :zephyr:code-sample:`tfm_ipc` sample: .. code-block:: bash @@ -239,7 +239,7 @@ option bit TZEN will be set). $ west flash Please note that, after having run a TFM sample on the board, you will need to -run `./build/tfm/api_ns/regression.sh` once more to clean up the board from secure +run ``./build/tfm/api_ns/regression.sh`` once more to clean up the board from secure options and get back the platform back to a "normal" state and be able to run usual, non-TFM, binaries. Also note that, even then, TZEN will remain set, and you will need to use @@ -284,6 +284,8 @@ assigned to USART1. Default settings are 115200 8N1. Programming and Debugging ************************* +STM32L562E-DK Discovery board includes an ST-LINK/V3E embedded debug tool interface. + Applications for the ``stm32l562e_dk`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -291,24 +293,30 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -STM32L562E-DK Discovery board includes an ST-LINK/V3E embedded debug tool -interface. Support can be enabled on pyocd by adding "pack" support with the -following pyocd command: +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + +Support can also be enabled for pyOCD by adding "pack" support with the +following pyOCD commands: .. code-block:: console $ pyocd pack --update $ pyocd pack --install stm32l562qe -Alternatively, this interface is supported by the openocd version -included in the Zephyr SDK since v0.13.1. - Flashing an application to STM32L562E-DK Discovery -------------------------------------------------- Connect the STM32L562E-DK Discovery to your host computer using the USB port. Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board: @@ -333,7 +341,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm32l562e_dk/stm32l562e_dk.dts b/boards/st/stm32l562e_dk/stm32l562e_dk.dts index 2083e93ff0d..9489e8d5429 100644 --- a/boards/st/stm32l562e_dk/stm32l562e_dk.dts +++ b/boards/st/stm32l562e_dk/stm32l562e_dk.dts @@ -20,6 +20,7 @@ zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,bt-c2h-uart = &usart1; + zephyr,display = &st7789v; }; aliases { diff --git a/boards/st/stm32l562e_dk/stm32l562e_dk.yaml b/boards/st/stm32l562e_dk/stm32l562e_dk.yaml index c2acb4cb098..cad386fb4f3 100644 --- a/boards/st/stm32l562e_dk/stm32l562e_dk.yaml +++ b/boards/st/stm32l562e_dk/stm32l562e_dk.yaml @@ -22,6 +22,7 @@ supported: - usb - usb_device - nvs + - usbd ram: 192 flash: 512 vendor: st diff --git a/boards/st/stm32l562e_dk/stm32l562e_dk_common.dtsi b/boards/st/stm32l562e_dk/stm32l562e_dk_common.dtsi index 2dd00d4ee21..f80159110e3 100644 --- a/boards/st/stm32l562e_dk/stm32l562e_dk_common.dtsi +++ b/boards/st/stm32l562e_dk/stm32l562e_dk_common.dtsi @@ -8,6 +8,8 @@ #include #include "arduino_r3_connector.dtsi" #include +#include +#include / { leds { @@ -32,7 +34,6 @@ }; aliases { - spi-flash0 = &mx25lm51245; die-temp0 = &die_temp; volt-sensor0 = &vref; volt-sensor1 = &vbat; @@ -43,6 +44,76 @@ }; }; +&fmc { + pinctrl-0 = <&fmc_a0_pf0 &fmc_nce_pd7 &fmc_nwe_pd5 &fmc_noe_pd4 + &fmc_d0_pd14 &fmc_d1_pd15 &fmc_d2_pd0 &fmc_d3_pd1 + &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9 &fmc_d7_pe10 + &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13 &fmc_d11_pe14 + &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9 &fmc_d15_pd10>; + pinctrl-names = "default"; + status = "okay"; + + sram { + compatible = "st,stm32-fmc-nor-psram"; + + #address-cells = <1>; + #size-cells = <0>; + + bank@0 { + reg = <0x0>; + st,control = ; + st,timing = <1 1 32 0 2 2 STM32_FMC_ACCESS_MODE_A>; + + fmc-mipi-dbi { + compatible = "st,stm32-fmc-mipi-dbi"; + reset-gpios = <&gpiof 14 GPIO_ACTIVE_LOW>; + power-gpios = <&gpioh 0 GPIO_ACTIVE_LOW>; + register-select-pin = <0>; + #address-cells = <1>; + #size-cells = <0>; + st7789v: lcd-panel@0 { + compatible = "sitronix,st7789v"; + reg = <0>; + mipi-mode = ; + /* A write cycle should be 68ns */ + mipi-max-frequency = <14705882>; + width = <240>; + height = <240>; + x-offset = <0>; + y-offset = <0>; + vcom = <0x1F>; + gctrl = <0x35>; + vdvs = <0x20>; + mdac = <0x00>; + gamma = <0x01>; + colmod = <0x05>; + lcm = <0x2c>; + porch-param = [0c 0c 00 33 33]; + cmd2en-param = [5a 69 02 00]; + pwctrl1-param = [a4 a1]; + pvgam-param = [D0 08 11 08 0C 15 39 33 50 36 13 14 29 2D]; + nvgam-param = [D0 08 10 08 06 06 39 44 51 0B 16 14 2F 31]; + ram-param = [00 F0]; + rgb-param = [40 02 14]; + }; + }; + }; + }; +}; + &clk_hsi48 { status = "okay"; }; @@ -176,13 +247,13 @@ stm32_lp_tick_source: &lptim1 { ]; partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - partition@0 { - reg = <0x00000000 DT_SIZE_M(64)>; - }; + partition@0 { + reg = <0x00000000 DT_SIZE_M(64)>; + }; }; }; }; diff --git a/boards/st/stm32l562e_dk/stm32l562e_dk_defconfig b/boards/st/stm32l562e_dk/stm32l562e_dk_defconfig index cf7483088e5..8655ea99d42 100644 --- a/boards/st/stm32l562e_dk/stm32l562e_dk_defconfig +++ b/boards/st/stm32l562e_dk/stm32l562e_dk_defconfig @@ -6,9 +6,6 @@ CONFIG_SERIAL=y # enable GPIO CONFIG_GPIO=y -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - # console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y @@ -18,6 +15,3 @@ CONFIG_ARM_MPU=y # Enable HW stack protection CONFIG_HW_STACK_PROTECTION=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32l562e_dk/stm32l562e_dk_stm32l562xx_ns_defconfig b/boards/st/stm32l562e_dk/stm32l562e_dk_stm32l562xx_ns_defconfig index d2035929200..cad42d57d8c 100644 --- a/boards/st/stm32l562e_dk/stm32l562e_dk_stm32l562xx_ns_defconfig +++ b/boards/st/stm32l562e_dk/stm32l562e_dk_stm32l562xx_ns_defconfig @@ -6,9 +6,6 @@ CONFIG_SERIAL=y # enable GPIO CONFIG_GPIO=y -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - # console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y @@ -19,6 +16,3 @@ CONFIG_ARM_MPU=y CONFIG_ARM_TRUSTZONE_M=y CONFIG_RUNTIME_NMI=y CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32mp157c_dk2/stm32mp157c_dk2_defconfig b/boards/st/stm32mp157c_dk2/stm32mp157c_dk2_defconfig index 056ce7eddc0..63bc58b1261 100644 --- a/boards/st/stm32mp157c_dk2/stm32mp157c_dk2_defconfig +++ b/boards/st/stm32mp157c_dk2/stm32mp157c_dk2_defconfig @@ -11,9 +11,6 @@ CONFIG_HW_STACK_PROTECTION=y CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y -# clock configuration -CONFIG_CLOCK_CONTROL=y - # console (remote proc console by default) CONFIG_CONSOLE=y CONFIG_RAM_CONSOLE=y @@ -21,6 +18,3 @@ CONFIG_RAM_CONSOLE_BUFFER_SIZE=1024 # uart console (overrides remote proc console) CONFIG_UART_CONSOLE=n - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32u083c_dk/Kconfig.stm32u083c_dk b/boards/st/stm32u083c_dk/Kconfig.stm32u083c_dk new file mode 100644 index 00000000000..1e14dd59b9b --- /dev/null +++ b/boards/st/stm32u083c_dk/Kconfig.stm32u083c_dk @@ -0,0 +1,5 @@ +# Copyright (c) 2024 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32U083C_DK + select SOC_STM32U083XX diff --git a/boards/st/stm32u083c_dk/arduino_r3_connector.dtsi b/boards/st/stm32u083c_dk/arduino_r3_connector.dtsi new file mode 100644 index 00000000000..297fd9b7f18 --- /dev/null +++ b/boards/st/stm32u083c_dk/arduino_r3_connector.dtsi @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpioa 0 0>, /* A0 */ + <1 0 &gpioa 1 0>, /* A1 */ + <2 0 &gpioa 4 0>, /* A2 */ + <3 0 &gpiob 0 0>, /* A3 */ + <4 0 &gpioc 1 0>, /* A4 */ + <5 0 &gpioc 0 0>, /* A5 */ + <6 0 &gpioa 3 0>, /* D0 */ + <7 0 &gpioa 2 0>, /* D1 */ + <8 0 &gpioc 12 0>, /* D2 */ + <9 0 &gpiob 3 0>, /* D3 */ + <10 0 &gpiob 5 0>, /* D4 */ + <11 0 &gpiob 4 0>, /* D5 */ + <12 0 &gpiob 10 0>, /* D6 */ + <13 0 &gpioa 8 0>, /* D7 */ + <14 0 &gpioa 9 0>, /* D8 */ + <15 0 &gpioc 7 0>, /* D9 */ + <16 0 &gpiob 6 0>, /* D10 */ + <17 0 &gpioa 7 0>, /* D11 */ + <18 0 &gpioa 6 0>, /* D12 */ + <19 0 &gpioa 5 0>, /* D13 */ + <20 0 &gpiob 9 0>, /* D14 */ + <21 0 &gpiob 8 0>; /* D15 */ + }; +}; + +arduino_serial: &usart2 {}; diff --git a/boards/st/stm32u083c_dk/board.cmake b/boards/st/stm32u083c_dk/board.cmake new file mode 100644 index 00000000000..a274ab952ee --- /dev/null +++ b/boards/st/stm32u083c_dk/board.cmake @@ -0,0 +1,9 @@ +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") + +board_runner_args(pyocd "--target=stm32u083mctx") + +board_runner_args(jlink "--device=STM32U083C-DK" "--reset-after-load") + +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32u083c_dk/board.yml b/boards/st/stm32u083c_dk/board.yml new file mode 100644 index 00000000000..7bcf691ac69 --- /dev/null +++ b/boards/st/stm32u083c_dk/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32u083c_dk + vendor: st + socs: + - name: stm32u083xx diff --git a/boards/st/stm32u083c_dk/doc/img/stm32u083c_dk.jpg b/boards/st/stm32u083c_dk/doc/img/stm32u083c_dk.jpg new file mode 100644 index 00000000000..7c196a75854 Binary files /dev/null and b/boards/st/stm32u083c_dk/doc/img/stm32u083c_dk.jpg differ diff --git a/boards/st/stm32u083c_dk/doc/index.rst b/boards/st/stm32u083c_dk/doc/index.rst new file mode 100644 index 00000000000..52f419f804a --- /dev/null +++ b/boards/st/stm32u083c_dk/doc/index.rst @@ -0,0 +1,294 @@ +.. _stm32u083c_dk_board: + +ST STM32U083C_DK +################ + +Overview +******** + +The STM32U083C_DK board, featuring an ARM Cortex-M0+ based STM32U083MC MCU, +provides an affordable and flexible way for users to try out new concepts and +build prototypes by choosing from the various combinations of performance and +power consumption features. Here are some highlights of the STM32U083C_DK +board: + +- Ultra-low-power STM32U083MC microcontroller based on the Arm |reg| Cortex |reg|‑M0+ core, + featuring 256 Kbytes of flash memory and 40 Kbytes of SRAM in an LQFP80 package. + +- Board connectors: + + - ST-LINK USB Type-C connector + - User USB Device with USB Type-C connector + - mikroBUS connectors + - MIPI debug in connector (Arm |reg| Cortex |reg| 10‑pin 1.27 mm‑pitch + debug connector over STDC14 footprint) + - Extension connectors for full access to all STM32 I/Os + - VBAT dedicated connector provides the capability to power the board on a battery + +- Flexible power-supply options: + + - ST-LINK USB VBUS, USB connector, or external sources + +- 4×24-segment LCD +- Three user LEDs +- Reset push-button +- User joystick +- Touchkey +- Temperature sensor + +Hardware +******** + +The STM32U083xC devices are an ultra-low-power microcontrollers family (STM32U0 +Series) based on the high-performance Arm |reg| Cortex |reg|-M0+ 32-bit RISC core. +They operate at a frequency of up to 56 MHz. + +- Includes ST state-of-the-art patented technology +- Ultra-low-power with FlexPowerControl: + + - 1.71 V to 3.6 V power supply + - -40 °C to +85/125 °C temperature range + - 130 nA VBAT mode: supply for RTC, 9 x 32-bit backup registers + - 16 nA Shutdown mode (6 wake-up pins) + - 30 nA Standby mode (6 wake-up pins) without RTC + - 160 nA Standby mode with RTC + - 825 nA Stop 2 mode with RTC + - 695 nA Stop 2 mode without RTC + - 4 µA wake-up from Stop mode + - 52 µA/MHz Run mode (LDO mode) + - Brownout reset + +- Core: + + - 32-bit Arm |reg| Cortex |reg|-M0+ CPU, frequency up to 56 MHz + +- ART Accelerator: + + - 1-Kbyte instruction cache allowing 0-wait-state execution from flash memory + +- Benchmarks: + + - 1.13 DMIPS/MHz (Drystone 2.1) + - 134 CoreMark |reg| (2.4 CoreMark/MHz at 56 MHz) + - 407 ULPMark™-CP + - 143 ULPMark™-PP + - 19.7 ULPMark™-CM + +- Memories: + + - 256-Kbyte single bank flash memory, proprietary code readout protection + - 40-Kbyte SRAM with hardware parity check + +- General-purpose input/outputs: + + - Up to 69 fast I/Os, most of them 5 V‑tolerant + +- Clock management: + + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC (±1%) + - Internal low-power 32 kHz RC (±5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, + auto-trimmed by LSE (better than ±0.25 % accuracy) + - Internal 48 MHz with clock recovery + - PLL for system clock, USB, ADC + +- Security: + + - Customer code protection + - Robust read out protection (RDP): 3 protection level states + and password-based regression (128-bit PSWD) + - Hardware protection feature (HDP) + - Secure boot + - AES: 128/256-bit key encryption hardware accelerator + - True random number generation, candidate for NIST SP 800-90B certification + - Candidate for Arm |reg| PSA level 1 and SESIP level 3 certifications + - 5 passive anti-tamper pins + - 96-bit unique ID + +- Up to 10 timers, 2 watchdogs and RTC: + + - 1x 16-bit advanced motor-control, 1x 32-bit and 3x 16-bit general purpose, + 2x 16-bit basic, 3x low-power 16-bit timers (available in Stop mode), + 2x watchdogs, SysTick timer + - RTC with hardware calendar, alarms and calibration + +- Up to 20 communication peripherals: + + - 1 USB 2.0 full-speed crystal-less solution with LPM and BCD + - 7 USARTs/LPUARTs (SPI, ISO 7816, LIN, IrDA, modem) + - 4 I2C interfaces supporting Fast-mode and Fast-mode Plus (up to 1 Mbit/s) + - 3 SPIs, plus 4x USARTs in SPI mode + - IRTIM (Infrared interface) + +- Rich analog peripherals (independent supply): + + - 1x 12-bit ADC (0.4 µs conversion time), up to 16-bit with hardware oversampling + - 1x 12-bit DAC output channel, low-power sample and hold + - 1x general-purpose operational amplifier with built-in PGA (variable gain up to 16) + - 2x ultra-low-power comparators + +- LCD driver: + - 8*48 or 4*52 segments, with step-up converter + +- General-purpose inputs/outputs: + - Up to 69 fast I/Os, most of them 5 V-tolerant + +- ECOPACK2 compliant packages + +More information about STM32U083MC can be found here: + +- `STM32U083MC on www.st.com`_ +- `STM32U083 reference manual`_ + +Supported Features +================== + +The Zephyr stm32u083c_dk board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/stm32u083c_dk/stm32u083c_dk_defconfig` + + +Connections and IOs +=================== + +STM32U083C_DK Board has 10 GPIO controllers. These controllers are responsible +for pin muxing, input/output, pull-up, etc. + +For more details please refer to `STM32U083MC User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- ADC1_IN8 : PA4 +- I2C1_SCL : PB8 +- I2C1_SDA : PB9 +- LPUART_1_TX : PG7 +- LPUART_1_RX : PG8 +- SPI1_NSS : PA4 +- SPI1_SCK : PA5 +- SPI1_MISO : PA6 +- SPI1_MOSI : PA7 +- SPI1_CS : PA15 +- UART_2_TX : PA2 +- UART_2_RX : PA3 + +System Clock +------------ + +STM32U083C_DK System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at +48MHz, driven by 4MHz medium speed internal oscillator. + +Serial Port +----------- + +STM32U083C_DK board has 7 U(S)ARTs. The Zephyr console output is assigned to +USART2. Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +STM32U083C_DK board includes an ST-LINK/V3 embedded debug tool interface. +This probe allows to flash the board using various tools. + +Flashing +======== + +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, JLink or pyOCD can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner pyocd + $ west flash --runner jlink + +For pyOCD, additional target information needs to be installed. +This can be done by executing the following commands. + +.. code-block:: console + + $ pyocd pack --update + $ pyocd pack --install stm32u0 + + +Flashing an application to STM32U083C_DK +------------------------------------------ + +Connect the STM32U083C_DK to your host computer using the USB port. +Then build and flash an application. Here is an example for the +:zephyr:code-sample:`hello_world` application. + +Run a serial host program to connect with your Nucleo board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash the application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32u083c_dk + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! stm32u083c_dk/stm32u083xx + +Debugging +========= + +Default flasher for this board is openocd. It could be used in the usual way. +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_u083rc + :goals: debug + +Note: Check the ``build/tfm`` directory to ensure that the commands required by these scripts +(``readlink``, etc.) are available on your system. Please also check ``STM32_Programmer_CLI`` +(which is used for initialization) is available in the PATH. + +.. _STM32U083_DK website: + https://www.st.com/en/evaluation-tools/stm32u083c-dk.html + +.. _STM32U083MC User Manual: + https://www.st.com/resource/en/user_manual/um3292-discovery-kit-with-STM32U083MC-MCU.pdf + +.. _STM32U083MC on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32u083mc + +.. _STM32U083 reference manual: + https://www.st.com/resource/en/reference_manual/rm0503-stm32u0-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/stm32u083c_dk/stm32u083c_dk.dts b/boards/st/stm32u083c_dk/stm32u083c_dk.dts new file mode 100644 index 00000000000..05a1485163f --- /dev/null +++ b/boards/st/stm32u083c_dk/stm32u083c_dk.dts @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include "arduino_r3_connector.dtsi" +#include + +/ { + model = "STMicroelectronics STM32U83C-DK board"; + compatible = "st,stm32u083c-dk"; + + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &usart2; + zephyr,shell-uart = &usart2; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + leds: leds { + compatible = "gpio-leds"; + green_led_1: led_3 { + gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>; + label = "User LD3"; + }; + }; + + aliases { + led0 = &green_led_1; + }; +}; + +&usart1 { + pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&usart2 { + pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&clk_hsi { + status = "okay"; +}; + +&pll { + div-m = <1>; + mul-n = <6>; + div-p = <2>; + div-q = <2>; + div-r = <2>; + clocks = <&clk_hsi>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <1>; +}; + +&dac1 { + status = "okay"; + pinctrl-0 = <&dac1_out1_pa4>; + pinctrl-names = "default"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_scl_pa9 &i2c1_sda_pa10>; + pinctrl-names = "default"; + status = "okay"; + clock-frequency = ; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_scl_pa7 &i2c2_sda_pa6>; + pinctrl-names = "default"; + status = "okay"; + clock-frequency = ; +}; diff --git a/boards/st/stm32u083c_dk/stm32u083c_dk.yaml b/boards/st/stm32u083c_dk/stm32u083c_dk.yaml new file mode 100644 index 00000000000..615f17f1c8e --- /dev/null +++ b/boards/st/stm32u083c_dk/stm32u083c_dk.yaml @@ -0,0 +1,16 @@ +identifier: stm32u083c_dk +name: ST STM32U083C-DK Discovery Kit +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - arduino_gpio + - dac + - gpio + - i2c + - usart +ram: 40 +flash: 256 diff --git a/boards/st/stm32u083c_dk/stm32u083c_dk_defconfig b/boards/st/stm32u083c_dk/stm32u083c_dk_defconfig new file mode 100644 index 00000000000..ce451a733e4 --- /dev/null +++ b/boards/st/stm32u083c_dk/stm32u083c_dk_defconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y diff --git a/boards/st/stm32u5a9j_dk/board.cmake b/boards/st/stm32u5a9j_dk/board.cmake index dadc06c643e..5bb38a1d9c6 100644 --- a/boards/st/stm32u5a9j_dk/board.cmake +++ b/boards/st/stm32u5a9j_dk/board.cmake @@ -1,11 +1,13 @@ # Copyright (c) 2023 STMicroelectronics # SPDX-License-Identifier: Apache-2.0 -board_runner_args(stm32cubeprogrammer "--erase" "--port=swd" "--reset-mode=hw") +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(openocd "--tcl-port=6666") board_runner_args(openocd --cmd-pre-init "gdb_report_data_abort enable") board_runner_args(openocd "--no-halt") +# keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/st/stm32u5a9j_dk/doc/index.rst b/boards/st/stm32u5a9j_dk/doc/index.rst index 7e3d638fa3e..571ee80f334 100644 --- a/boards/st/stm32u5a9j_dk/doc/index.rst +++ b/boards/st/stm32u5a9j_dk/doc/index.rst @@ -154,7 +154,7 @@ board. For example: $ minicom -D /dev/ttyACM0 -b 115200 Then, build and flash in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm32u5a9j_dk/stm32u5a9j_dk.dts b/boards/st/stm32u5a9j_dk/stm32u5a9j_dk.dts index 05bdfdd34eb..f8dbb7f8d18 100644 --- a/boards/st/stm32u5a9j_dk/stm32u5a9j_dk.dts +++ b/boards/st/stm32u5a9j_dk/stm32u5a9j_dk.dts @@ -247,6 +247,12 @@ uart0: &usart3 { }; }; +zephyr_udc0: &usbotg_hs { + pinctrl-0 = <&usb_otg_hs_dm_pa11 &usb_otg_hs_dp_pa12>; + pinctrl-names = "default"; + status = "okay"; +}; + &flash0 { partitions { compatible = "fixed-partitions"; diff --git a/boards/st/stm32u5a9j_dk/stm32u5a9j_dk_defconfig b/boards/st/stm32u5a9j_dk/stm32u5a9j_dk_defconfig index 93c31903765..458d687b660 100644 --- a/boards/st/stm32u5a9j_dk/stm32u5a9j_dk_defconfig +++ b/boards/st/stm32u5a9j_dk/stm32u5a9j_dk_defconfig @@ -16,9 +16,3 @@ CONFIG_UART_CONSOLE=y # Enable GPIO CONFIG_GPIO=y - -# Enable clocks -CONFIG_CLOCK_CONTROL=y - -# Enable pinctrl -CONFIG_PINCTRL=y diff --git a/boards/st/stm32vl_disco/board.cmake b/boards/st/stm32vl_disco/board.cmake index d03ace4d57d..7d5a94fd80f 100644 --- a/boards/st/stm32vl_disco/board.cmake +++ b/boards/st/stm32vl_disco/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32F100RB" "--speed=8000") +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32vl_disco/stm32vl_disco_defconfig b/boards/st/stm32vl_disco/stm32vl_disco_defconfig index 9472e788675..d9ffe5b49a7 100644 --- a/boards/st/stm32vl_disco/stm32vl_disco_defconfig +++ b/boards/st/stm32vl_disco/stm32vl_disco_defconfig @@ -15,9 +15,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# enable clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32wb5mm_dk/board.cmake b/boards/st/stm32wb5mm_dk/board.cmake index 47fc12f1308..5220869e9f0 100644 --- a/boards/st/stm32wb5mm_dk/board.cmake +++ b/boards/st/stm32wb5mm_dk/board.cmake @@ -1,7 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 -board_runner_args(pyocd "--target=stm32wb55vgyx") + +# keep first board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +board_runner_args(pyocd "--target=stm32wb55vgyx") +# keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/st/stm32wb5mm_dk/doc/stm32wb5mm_dk.rst b/boards/st/stm32wb5mm_dk/doc/stm32wb5mm_dk.rst index 51bde0110c5..9ee025f45e9 100644 --- a/boards/st/stm32wb5mm_dk/doc/stm32wb5mm_dk.rst +++ b/boards/st/stm32wb5mm_dk/doc/stm32wb5mm_dk.rst @@ -121,6 +121,8 @@ The Zephyr STM32WB5MM-DK board configuration supports the following hardware fea | UART | on-chip | serial port-polling; | | | | serial port-interrupt | +-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ Other hardware features are not yet supported on this Zephyr port. @@ -140,8 +142,8 @@ For compatibility information with the various versions of these binaries, please check `modules/hal/stm32/lib/stm32wb/hci/README`_ in the ``hal_stm32`` repo. -Note that since STM32WB Cube package V1.13.2, `"full stack"` binaries are not -compatible anymore for a use in Zephyr and only `"HCI Only"` versions should be +Note that since STM32WB Cube package V1.13.2, "full stack" binaries are not +compatible anymore for a use in Zephyr and only "HCI Only" versions should be used on the M0 side. Connections and IOs @@ -157,6 +159,7 @@ Default Zephyr Peripheral Mapping: - LPUART_1 TX/RX : PA3/PA2 - USB : PA11/PA12 - SWD : PA13/PA14 +- I2C3: SDA/SCL PB11/PB13 (Sensor I2C bus) System Clock ------------ @@ -178,19 +181,32 @@ simultaneously. The selection is done by JP4 and JP5 jumpers. To use the RGB LED, JP5 must be ON and JP4 OFF. In this configuration, GPIO_SELECT2 (PH1) is the chip select for this RGB device on SPI1. +Buttons +------- +STM32WB5MM-DK has two user buttons. The first button is mapped to PC12, +and the second to PC13. They have the aliases sw0 and sw1 respectively. Programming and Debugging ************************* +STM32WB5MM-DK has an on-board ST-Link to flash and debug the firmware on the module. + Applications for the ``stm32wb5mm_dk`` board configuration can be built the usual way (see :ref:`build_an_application`). Flashing ======== -STM32WB5MM-DK has an on-board ST-Link to flash and debug the firmware on the -module. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or pyOCD can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + $ west flash --runner openocd + $ west flash --runner pyocd Flashing ``hello_world`` application to STM32WB5MM-DK ------------------------------------------------------ @@ -232,9 +248,15 @@ You can debug an application in the usual way. Here is an example for the .. _STM32WB5MM-DK on www.st.com: https://www.st.com/en/evaluation-tools/stm32wb5mm-dk.html + .. _STM32WB5MMG datasheet: https://www.st.com/resource/en/datasheet/stm32wb5mmg.pdf + .. _modules/hal/stm32/lib/stm32wb/hci/README: https://github.com/zephyrproject-rtos/hal_stm32/blob/main/lib/stm32wb/hci/README + .. _Hello_World: https://docs.zephyrproject.org/latest/samples/hello_world/README.html + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/stm32wb5mm_dk/stm32wb5mm_dk.dts b/boards/st/stm32wb5mm_dk/stm32wb5mm_dk.dts index 6e48823ae24..e11ec3f0f20 100644 --- a/boards/st/stm32wb5mm_dk/stm32wb5mm_dk.dts +++ b/boards/st/stm32wb5mm_dk/stm32wb5mm_dk.dts @@ -9,6 +9,7 @@ #include #include #include +#include / { model = "STMicroelectronics STM32WB5MM Discovery Development Kit"; @@ -34,12 +35,29 @@ status = "disabled"; }; + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpioc 12 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 1"; + zephyr,code = ; + }; + button1: button_1 { + gpios = <&gpioc 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 2"; + zephyr,code = ; + }; + }; + aliases { watchdog0 = &iwdg; die-temp0 = &die_temp; volt-sensor0 = &vref; volt-sensor1 = &vbat; led-strip = &rgb_led_strip; + sw0 = &button0; + sw1 = &button1; + accel0 = &ism330dhcx; }; }; @@ -158,6 +176,27 @@ zephyr_udc0: &usb { }; }; +&i2c3 { + pinctrl-0 = <&i2c3_scl_pb13 &i2c3_sda_pb11>; + pinctrl-names = "default"; + status = "okay"; + clock-frequency = ; + + vl53l0x@29 { + compatible = "st,vl53l0x"; + reg = <0x29>; + xshut-gpios = <&gpioc 6 GPIO_ACTIVE_LOW>; + }; + + ism330dhcx: ism330dhcx@6b { + compatible = "st,ism330dhcx"; + reg = <0x6b>; + drdy-gpios = <&gpiod 2 GPIO_ACTIVE_HIGH>; + accel-odr= ; + gyro-odr= ; + }; +}; + &vref { status = "okay"; }; diff --git a/boards/st/stm32wb5mm_dk/stm32wb5mm_dk.yaml b/boards/st/stm32wb5mm_dk/stm32wb5mm_dk.yaml index 63c75d4473f..a90491d13aa 100644 --- a/boards/st/stm32wb5mm_dk/stm32wb5mm_dk.yaml +++ b/boards/st/stm32wb5mm_dk/stm32wb5mm_dk.yaml @@ -7,8 +7,11 @@ toolchain: - gnuarmemb - xtools ram: 256 -flash: 1024 +flash: 876 supported: - gpio - uart + - i2c + - vl53l0x + - ism330dhcx vendor: st diff --git a/boards/st/stm32wb5mm_dk/stm32wb5mm_dk_defconfig b/boards/st/stm32wb5mm_dk/stm32wb5mm_dk_defconfig index 75373aa997c..8b09bb0775d 100644 --- a/boards/st/stm32wb5mm_dk/stm32wb5mm_dk_defconfig +++ b/boards/st/stm32wb5mm_dk/stm32wb5mm_dk_defconfig @@ -4,9 +4,6 @@ CONFIG_SERIAL=y # enable GPIO CONFIG_GPIO=y -# enable clocks -CONFIG_CLOCK_CONTROL=y - # console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y @@ -16,6 +13,3 @@ CONFIG_ARM_MPU=y # Enable HW stack protection CONFIG_HW_STACK_PROTECTION=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/st/stm32wb5mmg/board.cmake b/boards/st/stm32wb5mmg/board.cmake index 47fc12f1308..5220869e9f0 100644 --- a/boards/st/stm32wb5mmg/board.cmake +++ b/boards/st/stm32wb5mmg/board.cmake @@ -1,7 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 -board_runner_args(pyocd "--target=stm32wb55vgyx") + +# keep first board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +board_runner_args(pyocd "--target=stm32wb55vgyx") +# keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/st/stm32wb5mmg/doc/stm32wb5mmg.rst b/boards/st/stm32wb5mmg/doc/stm32wb5mmg.rst index 13446524535..7b8ee9f0062 100644 --- a/boards/st/stm32wb5mmg/doc/stm32wb5mmg.rst +++ b/boards/st/stm32wb5mmg/doc/stm32wb5mmg.rst @@ -238,14 +238,23 @@ The onboard ST-Link on the ``b_u585i_iot02a`` board can be used to flash the STM32WB5MMG module. To do this you should put SW4 on OFF and SW5 on ON mode. In this case the firmware will be uploaded on the STM32WB5MMG module. +The module is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. -Flashing `hci_uart` application to STM32WB5MMG ----------------------------------------------- +Alternatively, openocd can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + +Flashing ``hci_uart`` application to STM32WB5MMG +------------------------------------------------ Connect the B-U585I-IOT02A to your host computer using the USB port. Put the SW4 (MCU SWD) in OFF mode and SW5 (SWD BLE) in ON mode. Then build and flash an application. Here is an example for the -:ref:`hci_uart ` application. +:zephyr:code-sample:`bluetooth_hci_uart` application. Run a serial host program to connect with your B-U585I-IOT02A board: @@ -287,7 +296,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hci_uart ` application. +:zephyr:code-sample:`bluetooth_hci_uart` application. .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/observer @@ -300,5 +309,9 @@ You can debug an application in the usual way. Here is an example for the .. _STM32WB5MMG datasheet: https://www.st.com/resource/en/datasheet/stm32wb5mmg.pdf + .. _modules/hal/stm32/lib/stm32wb/hci/README: https://github.com/zephyrproject-rtos/hal_stm32/blob/main/lib/stm32wb/hci/README + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/stm32wb5mmg/stm32wb5mmg_defconfig b/boards/st/stm32wb5mmg/stm32wb5mmg_defconfig index 75373aa997c..8b09bb0775d 100644 --- a/boards/st/stm32wb5mmg/stm32wb5mmg_defconfig +++ b/boards/st/stm32wb5mmg/stm32wb5mmg_defconfig @@ -4,9 +4,6 @@ CONFIG_SERIAL=y # enable GPIO CONFIG_GPIO=y -# enable clocks -CONFIG_CLOCK_CONTROL=y - # console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y @@ -16,6 +13,3 @@ CONFIG_ARM_MPU=y # Enable HW stack protection CONFIG_HW_STACK_PROTECTION=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/tdk/robokit1/doc/index.rst b/boards/tdk/robokit1/doc/index.rst index ef65431b7e5..abc90a0a611 100644 --- a/boards/tdk/robokit1/doc/index.rst +++ b/boards/tdk/robokit1/doc/index.rst @@ -153,7 +153,7 @@ Flashing #. Connect the TDK RoboKit1 board to your host computer using the USB debug port (USB1), USB2 for a serial console, and remaining micro USB for - power. Then build and flash the :ref:`hello_world` application. + power. Then build and flash the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -166,7 +166,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/tdk/robokit1/robokit1-common.dtsi b/boards/tdk/robokit1/robokit1-common.dtsi index 40fa35366a2..69c032974b8 100644 --- a/boards/tdk/robokit1/robokit1-common.dtsi +++ b/boards/tdk/robokit1/robokit1-common.dtsi @@ -89,6 +89,8 @@ }; }; +#include + &spi0 { pinctrl-0 = <&spi0_default>; pinctrl-names = "default"; @@ -103,10 +105,12 @@ reg = <0>; int-gpios = <&pioc 5 GPIO_ACTIVE_HIGH>; spi-max-frequency = <24000000>; - accel-hz = <32000>; - accel-fs = <16>; - gyro-hz = <32000>; - gyro-fs = <2000>; + accel-pwr-mode = ; + accel-odr = ; + accel-fs = ; + gyro-pwr-mode = ; + gyro-odr = ; + gyro-fs = ; }; spi_adc: adc@1 { compatible = "ti,ads7052"; diff --git a/boards/technexion/pico_pi/Kconfig.defconfig b/boards/technexion/pico_pi/Kconfig.defconfig deleted file mode 100644 index aebd510fe61..00000000000 --- a/boards/technexion/pico_pi/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Pico-Pi iMX7D M4 board - -# Copyright (c) 2019, Joris Offouga -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_PICO_PI - -if !XIP -config FLASH_SIZE - default 0 -config FLASH_BASE_ADDRESS - default 0 -endif - -endif # BOARD_PICO_PI diff --git a/boards/telink/tlsr9518adk80d/doc/index.rst b/boards/telink/tlsr9518adk80d/doc/index.rst index e80db259a77..97413403889 100644 --- a/boards/telink/tlsr9518adk80d/doc/index.rst +++ b/boards/telink/tlsr9518adk80d/doc/index.rst @@ -235,7 +235,7 @@ It is also possible to use the west flash command, but additional steps are requ Debugging ========= -This port supports UART debug and OpenOCD+GDB. The `west debug` command also supported. You may run +This port supports UART debug and OpenOCD+GDB. The ``west debug`` command also supported. You may run it in a simple way, like: .. code-block:: console diff --git a/boards/ti/cc1352p1_launchxl/CMakeLists.txt b/boards/ti/cc1352p1_launchxl/CMakeLists.txt index cdf4f19c873..1b2a7b60199 100644 --- a/boards/ti/cc1352p1_launchxl/CMakeLists.txt +++ b/boards/ti/cc1352p1_launchxl/CMakeLists.txt @@ -1,4 +1,3 @@ # SPDX-License-Identifier: Apache-2.0 -zephyr_library() -zephyr_library_sources(board_antenna.c) +add_subdirectory(${ZEPHYR_BASE}/boards/ti/common/ ${CMAKE_CURRENT_BINARY_DIR}/common) diff --git a/boards/ti/cc1352p1_launchxl/Kconfig b/boards/ti/cc1352p1_launchxl/Kconfig index 6981f6fdf8b..b75441b630f 100644 --- a/boards/ti/cc1352p1_launchxl/Kconfig +++ b/boards/ti/cc1352p1_launchxl/Kconfig @@ -1,16 +1,6 @@ # TI CC1352R LaunchXL board -# Copyright (c) 2021 Florin Stancu +# Copyright (c) 2024 Alexandre Bailon # SPDX-License-Identifier: Apache-2.0 -if BOARD_CC1352P1_LAUNCHXL - -config BOARD_ANTENNA_INIT_PRIO - int "Board antenna switch initialization priority" - default 70 - help - Set the priority for board init, must be greater than - KERNEL_INIT_PRIORITY_DEVICE but smaller than - IEEE802154_CC13XX_CC26XX_SUB_GHZ_INIT_PRIO. - -endif # BOARD_CC1352P1_LAUNCHXL +source "boards/ti/common/Kconfig" diff --git a/boards/ti/cc1352p1_launchxl/cc1352p1_launchxl-pinctrl.dtsi b/boards/ti/cc1352p1_launchxl/cc1352p1_launchxl-pinctrl.dtsi deleted file mode 100644 index 4ecc0396d26..00000000000 --- a/boards/ti/cc1352p1_launchxl/cc1352p1_launchxl-pinctrl.dtsi +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2022 Vaishnav Achath - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -&pinctrl { - /* UART0 */ - uart0_tx_default: uart0_tx_default { - pinmux = <13 IOC_PORT_MCU_UART0_TX>; - bias-disable; - }; - uart0_rx_default: uart0_rx_default { - pinmux = <12 IOC_PORT_MCU_UART0_RX>; - bias-disable; - input-enable; - }; - - /* I2C0 */ - i2c0_scl_default: i2c0_scl_default { - pinmux = <4 IOC_PORT_MCU_I2C_MSSCL>; - bias-pull-up; - drive-open-drain; - input-enable; - }; - i2c0_sda_default: i2c0_sda_default { - pinmux = <5 IOC_PORT_MCU_I2C_MSSDA>; - bias-pull-up; - drive-open-drain; - input-enable; - }; - i2c0_scl_sleep: i2c0_scl_sleep { - pinmux = <4 IOC_PORT_GPIO>; - bias-disable; - }; - i2c0_sda_sleep: i2c0_sda_sleep { - pinmux = <5 IOC_PORT_GPIO>; - bias-disable; - }; - - /* SPI0 */ - spi0_sck_default: spi0_sck_default { - pinmux = <10 IOC_PORT_MCU_SSI0_CLK>; - bias-disable; - }; - spi0_mosi_default: spi0_mosi_default { - pinmux = <9 IOC_PORT_MCU_SSI0_TX>; - bias-disable; - }; - spi0_miso_default: spi0_miso_default { - pinmux = <8 IOC_PORT_MCU_SSI0_RX>; - bias-disable; - input-enable; - }; - spi0_cs_default: spi0_cs_default { - pinmux = <11 IOC_PORT_MCU_SSI0_FSS>; - bias-disable; - }; - - /* On-board antenna pinmux states */ - board_ant_24g_off: board_ant_24g_off { - pinmux = <28 IOC_PORT_GPIO>; - bias-disable; - }; - board_ant_24g_on: board_ant_24g_on { - pinmux = <28 IOC_PORT_RFC_GPO0>; - bias-disable; - }; - board_ant_tx_pa_off: board_ant_tx_pa_off { - pinmux = <29 IOC_PORT_GPIO>; - bias-disable; - }; - board_ant_tx_pa_on: board_ant_tx_pa_on { - pinmux = <29 IOC_PORT_RFC_GPO3>; - bias-disable; - }; - board_ant_subg_off: board_ant_subg_off { - pinmux = <30 IOC_PORT_GPIO>; - bias-disable; - }; - board_ant_subg_on: board_ant_subg_on { - pinmux = <30 IOC_PORT_RFC_GPO0>; - bias-disable; - }; -}; diff --git a/boards/ti/cc1352p1_launchxl/cc1352p1_launchxl.dts b/boards/ti/cc1352p1_launchxl/cc1352p1_launchxl.dts index 9fcc6da57da..7f84f672ea2 100644 --- a/boards/ti/cc1352p1_launchxl/cc1352p1_launchxl.dts +++ b/boards/ti/cc1352p1_launchxl/cc1352p1_launchxl.dts @@ -7,163 +7,11 @@ /dts-v1/; #include -#include "../cc1352r1_launchxl/boosterpack_connector.dtsi" -#include "cc1352p1_launchxl-pinctrl.dtsi" -#include +#include "../common/launchxl.dtsi" +#include "../common/launchxl-flash.dtsi" +#include "../common/launchxl_sky13317.dtsi" / { model = "TI CC1352P1 LaunchXL"; compatible = "ti,launchxl-cc1352p1"; - - aliases { - led0 = &led0; - led1 = &led1; - sw0 = &btn0; - sw1 = &btn1; - watchdog0 = &wdt0; - mcuboot-led0 = &led1; - mcuboot-button0 = &btn1; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,ieee802154 = &ieee802154; - zephyr,code-partition = &slot0_partition; - }; - - /** - * The CC1352P LAUNCHXL has an on-board antenna switch (SKY13317-373LF) used to select the - * appropriate RF signal port based on the currently-used PHY. - * - * Truth table: - * - * Path DIO28 DIO29 DIO30 - * =========== ===== ===== ===== - * Off 0 0 0 - * Sub-1 GHz 0 0 1 // DIO30 mux to IOC_PORT_RFC_GPO0 for auto - * 2.4 GHz 1 0 0 // DIO28 mux to IOC_PORT_RFC_GPO0 for auto - * 20 dBm TX 0 1 0 // DIO29 mux to IOC_PORT_RFC_GPO3 for auto - */ - antenna_mux0: antenna_mux0 { - compatible = "skyworks,sky13317"; - status = "okay"; - gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>, <&gpio0 29 GPIO_ACTIVE_HIGH>, \ - <&gpio0 30 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&board_ant_24g_off &board_ant_tx_pa_off &board_ant_subg_off>; - pinctrl-1 = <&board_ant_24g_on &board_ant_tx_pa_off &board_ant_subg_off>; - pinctrl-2 = <&board_ant_24g_on &board_ant_tx_pa_on &board_ant_subg_off>; - pinctrl-3 = <&board_ant_24g_off &board_ant_tx_pa_off &board_ant_subg_on>; - pinctrl-4 = <&board_ant_24g_off &board_ant_tx_pa_on &board_ant_subg_on>; - pinctrl-names = "default", "ant_24g", "ant_24g_pa", "ant_subg", "ant_subg_pa"; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; - label = "Green LED"; - }; - led1: led_1 { - gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; - label = "Red LED"; - }; - }; - - keys { - compatible = "gpio-keys"; - btn0: btn_0 { - gpios = <&gpio0 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - label = "Push button 1"; - zephyr,code = ; - }; - btn1: btn_1 { - gpios = <&gpio0 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - label = "Push button 2"; - zephyr,code = ; - }; - }; -}; - -&flash0 { - partitions { - /* 40 KiB (0xa000) for MCUboot */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000a000>; - }; - - /* 136 KiB (0x22000) per slot for application */ - slot0_partition: partition@a000 { - label = "image-0"; - reg = <0x0000a000 0x00022000>; - }; - - slot1_partition: partition@2c000 { - label = "image-1"; - reg = <0x0002c000 0x00022000>; - }; - - /* 32 KiB (0x8000) for storage */ - storage_partition: partition@4e000 { - label = "storage"; - reg = <0x0004e000 0x00008000>; - }; - - /* CCFG (customer configuration area) is located in uppermost - * flash sector (0x2000/8 KiB @ 0x56000), keep it unused. - */ - }; -}; - -&cpu0 { - clock-frequency = <48000000>; -}; - -&trng { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_rx_default &uart0_tx_default>; - pinctrl-names = "default"; -}; - -&i2c0 { - status = "okay"; - pinctrl-0 = <&i2c0_scl_default &i2c0_sda_default>; - pinctrl-1 = <&i2c0_scl_sleep &i2c0_sda_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&spi0 { - status = "okay"; - pinctrl-0 = <&spi0_sck_default &spi0_mosi_default - &spi0_miso_default &spi0_cs_default>; - pinctrl-names = "default"; - cs-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; -}; - -&radio { - status = "okay"; -}; - -&ieee802154 { - status = "okay"; -}; - -&ieee802154g { - status = "disabled"; -}; - -&wdt0 { - status = "okay"; }; diff --git a/boards/ti/cc1352p1_launchxl/doc/index.rst b/boards/ti/cc1352p1_launchxl/doc/index.rst index a5f88cc19ff..b751b357307 100644 --- a/boards/ti/cc1352p1_launchxl/doc/index.rst +++ b/boards/ti/cc1352p1_launchxl/doc/index.rst @@ -168,7 +168,7 @@ Applications for the ``CC1352P LaunchPad`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. @@ -190,7 +190,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/ti/cc1352p1_launchxl/dts/bindings/skyworks,sky13317.yaml b/boards/ti/cc1352p1_launchxl/dts/bindings/skyworks,sky13317.yaml deleted file mode 100644 index b9f92fade40..00000000000 --- a/boards/ti/cc1352p1_launchxl/dts/bindings/skyworks,sky13317.yaml +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2022 Stancu Florin -# SPDX-License-Identifier: Apache-2.0 - -description: Skyworks SKY13317 pHEMT GaAs SP3T Antenna Switch - -compatible: "skyworks,sky13317" - -include: [pinctrl-device.yaml, base.yaml] - -properties: - gpios: - type: phandle-array - required: true - description: Antenna mux control pins diff --git a/boards/ti/cc1352p7_launchpad/CMakeLists.txt b/boards/ti/cc1352p7_launchpad/CMakeLists.txt new file mode 100644 index 00000000000..1b2a7b60199 --- /dev/null +++ b/boards/ti/cc1352p7_launchpad/CMakeLists.txt @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(${ZEPHYR_BASE}/boards/ti/common/ ${CMAKE_CURRENT_BINARY_DIR}/common) diff --git a/boards/ti/cc1352p7_launchpad/Kconfig b/boards/ti/cc1352p7_launchpad/Kconfig new file mode 100644 index 00000000000..3042bf1555e --- /dev/null +++ b/boards/ti/cc1352p7_launchpad/Kconfig @@ -0,0 +1,6 @@ +# TI CC1352P7 LaunchPad board + +# Copyright (c) 2024 Alexandre Bailon +# SPDX-License-Identifier: Apache-2.0 + +source "boards/ti/common/Kconfig" diff --git a/boards/ti/cc1352p7_launchpad/Kconfig.cc1352p7_lp b/boards/ti/cc1352p7_launchpad/Kconfig.cc1352p7_lp new file mode 100644 index 00000000000..4e8de72e941 --- /dev/null +++ b/boards/ti/cc1352p7_launchpad/Kconfig.cc1352p7_lp @@ -0,0 +1,7 @@ +# TI CC1352P7 LaunchPad board + +# Copyright (c) 2024 Alexandre Bailon +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CC1352P7_LP + select SOC_CC1352P7 diff --git a/boards/ti/cc1352p7_launchpad/board.cmake b/boards/ti/cc1352p7_launchpad/board.cmake new file mode 100644 index 00000000000..1c437041486 --- /dev/null +++ b/boards/ti/cc1352p7_launchpad/board.cmake @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Florin Stancu +# +# SPDX-License-Identifier: Apache-2.0 + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/ti/cc1352p7_launchpad/board.yml b/boards/ti/cc1352p7_launchpad/board.yml new file mode 100644 index 00000000000..0e97ad4ff43 --- /dev/null +++ b/boards/ti/cc1352p7_launchpad/board.yml @@ -0,0 +1,5 @@ +board: + name: cc1352p7_lp + vendor: ti + socs: + - name: cc1352p7 diff --git a/boards/ti/cc1352p7_launchpad/cc1352p7_lp.dts b/boards/ti/cc1352p7_launchpad/cc1352p7_lp.dts new file mode 100644 index 00000000000..51ad1b2ba66 --- /dev/null +++ b/boards/ti/cc1352p7_launchpad/cc1352p7_lp.dts @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2024 Alexandre Bailon + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "../common/launchxl.dtsi" +#include "../common/launchxl-flash-p7.dtsi" +#include "../common/launchxl_sky13317.dtsi" + +/ { + model = "TI CC1352P7 LaunchPad"; + compatible = "ti,lp-cc1352p7"; +}; diff --git a/boards/ti/cc1352p7_launchpad/cc1352p7_lp.yaml b/boards/ti/cc1352p7_launchpad/cc1352p7_lp.yaml new file mode 100644 index 00000000000..fe3a834ebcf --- /dev/null +++ b/boards/ti/cc1352p7_launchpad/cc1352p7_lp.yaml @@ -0,0 +1,17 @@ +identifier: cc1352p7_lp +name: TI SimpleLink CC1352P7 LaunchPad +type: mcu +arch: arm +ram: 144 +flash: 704 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - i2c + - spi + - watchdog + - hwinfo +vendor: ti diff --git a/boards/ti/cc1352p7_launchpad/cc1352p7_lp_defconfig b/boards/ti/cc1352p7_launchpad/cc1352p7_lp_defconfig new file mode 100644 index 00000000000..42ca455ed33 --- /dev/null +++ b/boards/ti/cc1352p7_launchpad/cc1352p7_lp_defconfig @@ -0,0 +1,24 @@ +# +# Copyright (c) 2021 Florin Stancu +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_BUILD_OUTPUT_HEX=y +# custom callback for the antenna switch +CONFIG_CC13X2_CC26X2_HAS_CUSTOM_RF_HWATTRS=y + +CONFIG_CC13X2_CC26X2_BOOTLOADER_ENABLE=y +CONFIG_CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE=y +CONFIG_CC13X2_CC26X2_BOOTLOADER_BACKDOOR_PIN=15 + +# Enable MPU and hardware stack protection +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_PINCTRL=y +CONFIG_GPIO=y +CONFIG_SERIAL=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/ti/cc1352p7_launchpad/doc/img/lp-cc1352p7-top.jpg b/boards/ti/cc1352p7_launchpad/doc/img/lp-cc1352p7-top.jpg new file mode 100644 index 00000000000..196b7a8e6d5 Binary files /dev/null and b/boards/ti/cc1352p7_launchpad/doc/img/lp-cc1352p7-top.jpg differ diff --git a/boards/ti/cc1352p7_launchpad/doc/index.rst b/boards/ti/cc1352p7_launchpad/doc/index.rst new file mode 100644 index 00000000000..2b7fbc12a2c --- /dev/null +++ b/boards/ti/cc1352p7_launchpad/doc/index.rst @@ -0,0 +1,248 @@ +.. _cc1352p7_lp: + +CC1352P7 LaunchPad +################## + +Overview +******** + +The Texas Instruments CC1352P7 LaunchPad |trade| (LP-CC1352P7) is a +development kit for the SimpleLink |trade| multi-Standard CC1352P7 wireless MCU. + +See the `TI CC1352P7 LaunchPad Product Page`_ for details. + +.. figure:: img/lp-cc1352p7-top.jpg + :width: 400px + :align: center + :alt: TI CC1352P7 LaunchPad + + Texas Instruments CC1352P7 LaunchPad |trade| + +Hardware +******** + +The CC1352P7 LaunchPad |trade| development kit features the CC1352P7 wireless MCU. +The board is equipped with two LEDs, two push buttons, antenna switch and +BoosterPack connectors for expansion. It also includes an integrated (XDS110) +debugger. + +The CC1352P7 wireless MCU has a 48 MHz Arm |reg| Cortex |reg|-M4F SoC and an +integrated sub-1GHz and 2.4 GHz transceiver with integrated 20dBm power amplifier +(PA) supporting multiple protocols including Bluetooth |reg| Low Energy and IEEE +|reg| 802.15.4. + +See the `TI CC1352P7 Product Page`_ for additional details. + +Supported Features +================== + +The CC1352P7 LaunchPad board configuration supports the following hardware +features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| I2C | on-chip | i2c | ++-----------+------------+----------------------+ +| SPI | on-chip | spi | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ +| HWINFO | on-chip | hwinfo | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Connections and IOs +=================== + +All I/O signals are accessible from the BoosterPack connectors. Pin function +aligns with the LaunchPad standard. + ++-------+-----------+---------------------+ +| Pin | Function | Usage | ++=======+===========+=====================+ +| DIO3 | GPIO | | ++-------+-----------+---------------------+ +| DIO4 | I2C_MSSCL | I2C SCL | ++-------+-----------+---------------------+ +| DIO5 | I2C_MSSDA | I2C SDA | ++-------+-----------+---------------------+ +| DIO6 | GPIO | Red LED | ++-------+-----------+---------------------+ +| DIO7 | GPIO | Green LED | ++-------+-----------+---------------------+ +| DIO8 | SSI0_RX | SPI MISO | ++-------+-----------+---------------------+ +| DIO9 | SSI0_TX | SPI MOSI | ++-------+-----------+---------------------+ +| DIO10 | SSI0_CLK | SPI CLK | ++-------+-----------+---------------------+ +| DIO11 | SSIO_CS | SPI CS | ++-------+-----------+---------------------+ +| DIO12 | UART0_RX | UART RXD | ++-------+-----------+---------------------+ +| DIO13 | UART0_TX | UART TXD | ++-------+-----------+---------------------+ +| DIO14 | GPIO | Button 2 | ++-------+-----------+---------------------+ +| DIO15 | GPIO | Button 1 | ++-------+-----------+---------------------+ +| DIO16 | | JTAG TDO | ++-------+-----------+---------------------+ +| DIO17 | | JTAG TDI | ++-------+-----------+---------------------+ +| DIO18 | UART0_RTS | UART RTS / JTAG SWO | ++-------+-----------+---------------------+ +| DIO19 | UART0_CTS | UART CTS | ++-------+-----------+---------------------+ +| DIO20 | GPIO | Flash CS | ++-------+-----------+---------------------+ +| DIO21 | GPIO | | ++-------+-----------+---------------------+ +| DIO22 | GPIO | | ++-------+-----------+---------------------+ +| DIO23 | AUX_IO | A0 | ++-------+-----------+---------------------+ +| DIO24 | AUX_IO | A1 | ++-------+-----------+---------------------+ +| DIO25 | AUX_IO | A2 | ++-------+-----------+---------------------+ +| DIO26 | AUX_IO | A3 | ++-------+-----------+---------------------+ +| DIO27 | AUX_IO | A4 | ++-------+-----------+---------------------+ +| DIO28 | AUX_IO | A5 | ++-------+-----------+---------------------+ +| DIO29 | AUX_IO | A6 | ++-------+-----------+---------------------+ +| DIO30 | AUX_IO | A7 | ++-------+-----------+---------------------+ + +Programming and Debugging +************************* + +Before flashing or debugging ensure the RESET, TMS, TCK, TDO, and TDI jumpers +are in place. Also place jumpers on the TXD and RXD signals for a serial +console using the XDS110 application serial port. + +Prerequisites: +============== + +#. Ensure the XDS-110 emulation firmware on the board is updated. + + Download and install the latest `XDS-110 emulation package`_. + + Follow these `xds110 firmware update directions + `_ + + Note that the emulation package install may place the xdsdfu utility + in ``/ccs_base/common/uscif/xds110/``. + +#. Install OpenOCD + + You can obtain OpenOCD by following these + :ref:`installing the latest Zephyr SDK instructions `. + + After the installation, add the directory containing the OpenOCD executable + to your environment's PATH variable. For example, use this command in Linux: + + .. code-block:: console + + export PATH=$ZEPHYR_SDK_INSTALL_DIR/sysroots/x86_64-pokysdk-linux/usr/bin/openocd:$PATH + +Flashing +======== + +Applications for the ``CC1352P7 LaunchPad`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ screen 115200 + +Replace :code:`` with the port where the XDS110 application +serial device can be found. For example, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: cc1352p7_lp + :goals: build flash + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: cc1352p7_lp + :maybe-skip-config: + :goals: debug + +Bootloader +========== + +The ROM bootloader on CC13x2x7 and CC26x2x7 devices is enabled by default. The +bootloader will start if there is no valid application image in flash or the +so-called backdoor is enabled (via option +:kconfig:option:`CONFIG_CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE`) and BTN-1 is held +down during reset. See the bootloader documentation in chapter 10 of the `TI +CC13x2x7 / CC26x2x7 Technical Reference Manual`_ for additional information. + +Power Management and UART +========================= + +System and device power management are supported on this platform, and +can be enabled via the standard Kconfig options in Zephyr, such as +:kconfig:option:`CONFIG_PM`, :kconfig:option:`CONFIG_PM_DEVICE`. + +When system power management is turned on (CONFIG_PM=y), +sleep state 2 (standby mode) is allowed, and polling is used to retrieve input +by calling uart_poll_in(), it is possible for characters to be missed if the +system enters standby mode between calls to uart_poll_in(). This is because +the UART is inactive while the system is in standby mode. The workaround is to +disable sleep state 2 while polling: + +.. code-block:: c + + pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES); + + pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES); + + +References +********** + +CC1352P7 LaunchPad Quick Start Guide: + https://www.ti.com/lit/pdf/swru573 + +.. _TI CC1352P7 LaunchPad Product Page: + https://www.ti.com/tool/LP-CC1352P7 + +.. _TI CC1352P7 Product Page: + https://www.ti.com/product/CC1352P7 + +.. _TI CC13x2x7 / CC26x2x7 Technical Reference Manual: + https://www.ti.com/lit/ug/swcu192/swcu192.pdf + +.. _XDS-110 emulation package: + http://processors.wiki.ti.com/index.php/XDS_Emulation_Software_Package#XDS_Emulation_Software_.28emupack.29_Download diff --git a/boards/ti/cc1352p7_launchpad/support/openocd.cfg b/boards/ti/cc1352p7_launchpad/support/openocd.cfg new file mode 100644 index 00000000000..8be969b1819 --- /dev/null +++ b/boards/ti/cc1352p7_launchpad/support/openocd.cfg @@ -0,0 +1 @@ +source [find board/ti_cc26x2x7_launchpad.cfg] diff --git a/boards/ti/cc1352r1_launchxl/cc1352r1_launchxl-pinctrl.dtsi b/boards/ti/cc1352r1_launchxl/cc1352r1_launchxl-pinctrl.dtsi deleted file mode 100644 index a522a57d8aa..00000000000 --- a/boards/ti/cc1352r1_launchxl/cc1352r1_launchxl-pinctrl.dtsi +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2022 Vaishnav Achath - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -&pinctrl { - /* UART0 */ - uart0_tx_default: uart0_tx_default { - pinmux = <13 IOC_PORT_MCU_UART0_TX>; - bias-disable; - }; - uart0_rx_default: uart0_rx_default { - pinmux = <12 IOC_PORT_MCU_UART0_RX>; - bias-disable; - input-enable; - }; - - /* I2C0 */ - i2c0_scl_default: i2c0_scl_default { - pinmux = <4 IOC_PORT_MCU_I2C_MSSCL>; - bias-pull-up; - drive-open-drain; - input-enable; - }; - i2c0_sda_default: i2c0_sda_default { - pinmux = <5 IOC_PORT_MCU_I2C_MSSDA>; - bias-pull-up; - drive-open-drain; - input-enable; - }; - i2c0_scl_sleep: i2c0_scl_sleep { - pinmux = <4 IOC_PORT_GPIO>; - bias-disable; - }; - i2c0_sda_sleep: i2c0_sda_sleep { - pinmux = <5 IOC_PORT_GPIO>; - bias-disable; - }; - - /* SPI0 */ - spi0_sck_default: spi0_sck_default { - pinmux = <10 IOC_PORT_MCU_SSI0_CLK>; - bias-disable; - }; - spi0_mosi_default: spi0_mosi_default { - pinmux = <9 IOC_PORT_MCU_SSI0_TX>; - bias-disable; - }; - spi0_miso_default: spi0_miso_default { - pinmux = <8 IOC_PORT_MCU_SSI0_RX>; - bias-disable; - input-enable; - }; - spi0_cs_default: spi0_cs_default { - pinmux = <11 IOC_PORT_MCU_SSI0_FSS>; - bias-disable; - }; -}; diff --git a/boards/ti/cc1352r1_launchxl/cc1352r1_launchxl.dts b/boards/ti/cc1352r1_launchxl/cc1352r1_launchxl.dts index 53e5a08a365..cf7674b4eb2 100644 --- a/boards/ti/cc1352r1_launchxl/cc1352r1_launchxl.dts +++ b/boards/ti/cc1352r1_launchxl/cc1352r1_launchxl.dts @@ -7,143 +7,14 @@ /dts-v1/; #include -#include "boosterpack_connector.dtsi" -#include "cc1352r1_launchxl-pinctrl.dtsi" -#include - -#define BTN_GPIO_FLAGS (GPIO_ACTIVE_LOW | GPIO_PULL_UP) +#include "../common/launchxl.dtsi" +#include "../common/launchxl-flash.dtsi" / { model = "TI CC1352R1 LaunchXL"; compatible = "ti,launchxl-cc1352r1"; - - aliases { - led0 = &led0; - led1 = &led1; - sw0 = &btn0; - sw1 = &btn1; - watchdog0 = &wdt0; - mcuboot-led0 = &led1; - mcuboot-button0 = &btn1; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,ieee802154 = &ieee802154; - zephyr,code-partition = &slot0_partition; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; - label = "Green LED"; - }; - led1: led_1 { - gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; - label = "Red LED"; - }; - }; - - keys { - compatible = "gpio-keys"; - btn0: btn_0 { - gpios = <&gpio0 15 BTN_GPIO_FLAGS>; - label = "Push button 1"; - zephyr,code = ; - }; - btn1: btn_1 { - gpios = <&gpio0 14 BTN_GPIO_FLAGS>; - label = "Push button 2"; - zephyr,code = ; - }; - }; -}; - -&flash0 { - partitions { - /* 40 KiB (0xa000) for MCUboot */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000a000>; - }; - - /* 136 KiB (0x22000) per slot for application */ - slot0_partition: partition@a000 { - label = "image-0"; - reg = <0x0000a000 0x00022000>; - }; - - slot1_partition: partition@2c000 { - label = "image-1"; - reg = <0x0002c000 0x00022000>; - }; - - /* 32 KiB (0x8000) for storage */ - storage_partition: partition@4e000 { - label = "storage"; - reg = <0x0004e000 0x00008000>; - }; - - /* CCFG (customer configuration area) is located in uppermost - * flash sector (0x2000/8 KiB @ 0x56000), keep it unused. - */ - }; -}; - -&cpu0 { - clock-frequency = <48000000>; -}; - -&trng { - status = "okay"; -}; - -&gpio0 { - status = "okay"; }; &adc0 { status = "okay"; }; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_rx_default &uart0_tx_default>; - pinctrl-names = "default"; -}; - -&i2c0 { - status = "okay"; - pinctrl-0 = <&i2c0_scl_default &i2c0_sda_default>; - pinctrl-1 = <&i2c0_scl_sleep &i2c0_sda_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&spi0 { - status = "okay"; - pinctrl-0 = <&spi0_sck_default &spi0_mosi_default - &spi0_miso_default &spi0_cs_default>; - pinctrl-names = "default"; - cs-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; -}; - -&radio { - status = "okay"; -}; - -&ieee802154 { - status = "okay"; -}; - -&ieee802154g { - status = "disabled"; -}; - -&wdt0 { - status = "okay"; -}; diff --git a/boards/ti/cc1352r1_launchxl/doc/index.rst b/boards/ti/cc1352r1_launchxl/doc/index.rst index 0002b1e1c6f..2e7ed0ae2ff 100644 --- a/boards/ti/cc1352r1_launchxl/doc/index.rst +++ b/boards/ti/cc1352r1_launchxl/doc/index.rst @@ -167,7 +167,7 @@ Applications for the ``CC1352R LaunchPad`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. @@ -189,7 +189,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/ti/cc1352r_sensortag/cc1352r_sensortag.dts b/boards/ti/cc1352r_sensortag/cc1352r_sensortag.dts index b79e4854f73..1e51ef27f1b 100644 --- a/boards/ti/cc1352r_sensortag/cc1352r_sensortag.dts +++ b/boards/ti/cc1352r_sensortag/cc1352r_sensortag.dts @@ -8,7 +8,7 @@ /dts-v1/; #include -#include "../cc1352r1_launchxl/boosterpack_connector.dtsi" +#include "../common/boosterpack_connector.dtsi" #include "cc1352r_sensortag-pinctrl.dtsi" #include diff --git a/boards/ti/cc1352r_sensortag/doc/index.rst b/boards/ti/cc1352r_sensortag/doc/index.rst index c270e85fd57..4120f4934df 100644 --- a/boards/ti/cc1352r_sensortag/doc/index.rst +++ b/boards/ti/cc1352r_sensortag/doc/index.rst @@ -188,7 +188,7 @@ Applications for the ``CC1352R SensorTag`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. @@ -214,7 +214,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/ti/cc1352r_sensortag/support/openocd.cfg b/boards/ti/cc1352r_sensortag/support/openocd.cfg index 16a135a531a..beec0517534 100644 --- a/boards/ti/cc1352r_sensortag/support/openocd.cfg +++ b/boards/ti/cc1352r_sensortag/support/openocd.cfg @@ -1,4 +1,4 @@ source [find board/ti_cc13x2_launchpad.cfg] # Workaround for #21372. This allows OpenOCD to flash correctly # with newer 3.x XDS firmware -adapter_khz 1500 +adapter speed 1500 diff --git a/boards/ti/cc26x2r1_launchxl/boosterpack_connector.dtsi b/boards/ti/cc26x2r1_launchxl/boosterpack_connector.dtsi deleted file mode 100644 index cf126a52146..00000000000 --- a/boards/ti/cc26x2r1_launchxl/boosterpack_connector.dtsi +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2019 Brett Witherspoon - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/ { - boosterpack_header: connector { - compatible = "ti,boosterpack-header"; - #gpio-cells = <2>; - gpio-map = <2 0 &gpio0 23 0>, - <3 0 &gpio0 2 0>, - <4 0 &gpio0 3 0>, - <5 0 &gpio0 22 0>, - <6 0 &gpio0 24 0>, - <7 0 &gpio0 10 0>, - <8 0 &gpio0 21 0>, - <9 0 &gpio0 4 0>, - <10 0 &gpio0 5 0>, - <11 0 &gpio0 15 0>, - <12 0 &gpio0 14 0>, - <13 0 &gpio0 13 0>, - <14 0 &gpio0 8 0>, - <15 0 &gpio0 9 0>, - <18 0 &gpio0 11 0>, - <19 0 &gpio0 12 0>, - <23 0 &gpio0 25 0>, - <24 0 &gpio0 26 0>, - <25 0 &gpio0 27 0>, - <26 0 &gpio0 28 0>, - <27 0 &gpio0 29 0>, - <28 0 &gpio0 30 0>, - <29 0 &gpio0 0 0>, - <30 0 &gpio0 1 0>, - <31 0 &gpio0 17 0>, - <32 0 &gpio0 16 0>, - <36 0 &gpio0 18 0>, - <37 0 &gpio0 19 0>, - <38 0 &gpio0 20 0>, - <39 0 &gpio0 6 0>, - <40 0 &gpio0 7 0>; - }; -}; - -boosterpack_i2c: &i2c0 {}; -boosterpack_spi: &spi0 {}; -boosterpack_serial: &uart0 {}; diff --git a/boards/ti/cc26x2r1_launchxl/cc26x2r1_launchxl-pinctrl.dtsi b/boards/ti/cc26x2r1_launchxl/cc26x2r1_launchxl-pinctrl.dtsi index 2376d1e98a8..02df3fee52c 100644 --- a/boards/ti/cc26x2r1_launchxl/cc26x2r1_launchxl-pinctrl.dtsi +++ b/boards/ti/cc26x2r1_launchxl/cc26x2r1_launchxl-pinctrl.dtsi @@ -17,45 +17,4 @@ bias-disable; input-enable; }; - - /* I2C0 */ - i2c0_scl_default: i2c0_scl_default { - pinmux = <4 IOC_PORT_MCU_I2C_MSSCL>; - bias-pull-up; - drive-open-drain; - input-enable; - }; - i2c0_sda_default: i2c0_sda_default { - pinmux = <5 IOC_PORT_MCU_I2C_MSSDA>; - bias-pull-up; - drive-open-drain; - input-enable; - }; - i2c0_scl_sleep: i2c0_scl_sleep { - pinmux = <4 IOC_PORT_GPIO>; - bias-disable; - }; - i2c0_sda_sleep: i2c0_sda_sleep { - pinmux = <5 IOC_PORT_GPIO>; - bias-disable; - }; - - /* SPI0 */ - spi0_sck_default: spi0_sck_default { - pinmux = <10 IOC_PORT_MCU_SSI0_CLK>; - bias-disable; - }; - spi0_mosi_default: spi0_mosi_default { - pinmux = <9 IOC_PORT_MCU_SSI0_TX>; - bias-disable; - }; - spi0_miso_default: spi0_miso_default { - pinmux = <8 IOC_PORT_MCU_SSI0_RX>; - bias-disable; - input-enable; - }; - spi0_cs_default: spi0_cs_default { - pinmux = <11 IOC_PORT_MCU_SSI0_FSS>; - bias-disable; - }; }; diff --git a/boards/ti/cc26x2r1_launchxl/cc26x2r1_launchxl.dts b/boards/ti/cc26x2r1_launchxl/cc26x2r1_launchxl.dts index 00b5c7d0507..7aa20e01b77 100644 --- a/boards/ti/cc26x2r1_launchxl/cc26x2r1_launchxl.dts +++ b/boards/ti/cc26x2r1_launchxl/cc26x2r1_launchxl.dts @@ -7,131 +7,31 @@ /dts-v1/; #include -#include "boosterpack_connector.dtsi" +#include "../common/launchxl.dtsi" +#include "../common/launchxl-flash.dtsi" #include "cc26x2r1_launchxl-pinctrl.dtsi" -#include - -#define BTN_GPIO_FLAGS (GPIO_ACTIVE_LOW | GPIO_PULL_UP) / { model = "TI CC26x2R1 LaunchXL"; compatible = "ti,launchxl-cc26x2r1"; - aliases { - led0 = &led0; - led1 = &led1; - sw0 = &btn0; - sw1 = &btn1; - watchdog0 = &wdt0; - mcuboot-led0 = &led1; - mcuboot-button0 = &btn1; - }; - chosen { - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,code-partition = &slot0_partition; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; - label = "Green LED"; - }; - led1: led_1 { - gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; - label = "Red LED"; - }; - }; - - keys { - compatible = "gpio-keys"; - btn0: btn_0 { - gpios = <&gpio0 13 BTN_GPIO_FLAGS>; - label = "Push button 1"; - zephyr,code = ; - }; - btn1: btn_1 { - gpios = <&gpio0 14 BTN_GPIO_FLAGS>; - label = "Push button 2"; - zephyr,code = ; - }; + /delete-property/ zephyr,ieee802154; }; }; -&flash0 { - partitions { - /* 40 KiB (0xa000) for MCUboot */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000a000>; - }; - - /* 136 KiB (0x22000) per slot for application */ - slot0_partition: partition@a000 { - label = "image-0"; - reg = <0x0000a000 0x00022000>; - }; - - slot1_partition: partition@2c000 { - label = "image-1"; - reg = <0x0002c000 0x00022000>; - }; - - /* 32 KiB (0x8000) for storage */ - storage_partition: partition@4e000 { - label = "storage"; - reg = <0x0004e000 0x00008000>; - }; - - /* CCFG (customer configuration area) is located in uppermost - * flash sector (0x2000/8 KiB @ 0x56000), keep it unused. - */ - }; +&radio { + status = "disabled"; }; -&cpu0 { - clock-frequency = <48000000>; +&ieee802154 { + status = "disabled"; }; -&trng { - status = "okay"; -}; - -&gpio0 { - status = "okay"; +&ieee802154g { + status = "disabled"; }; &adc0 { status = "okay"; }; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_rx_default &uart0_tx_default>; - pinctrl-names = "default"; -}; - -&i2c0 { - status = "okay"; - pinctrl-0 = <&i2c0_scl_default &i2c0_sda_default>; - pinctrl-1 = <&i2c0_scl_sleep &i2c0_sda_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&spi0 { - status = "okay"; - pinctrl-0 = <&spi0_sck_default &spi0_mosi_default - &spi0_miso_default &spi0_cs_default>; - pinctrl-names = "default"; - - cs-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; -}; - -&wdt0 { - status = "okay"; -}; diff --git a/boards/ti/cc26x2r1_launchxl/doc/index.rst b/boards/ti/cc26x2r1_launchxl/doc/index.rst index 8177df13ae3..1f6a02d92dd 100644 --- a/boards/ti/cc26x2r1_launchxl/doc/index.rst +++ b/boards/ti/cc26x2r1_launchxl/doc/index.rst @@ -173,7 +173,7 @@ Applications for the ``CC26x2R LaunchPad`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. @@ -195,7 +195,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/ti/cc3220sf_launchxl/doc/index.rst b/boards/ti/cc3220sf_launchxl/doc/index.rst index dd58c203daa..cc14840d999 100644 --- a/boards/ti/cc3220sf_launchxl/doc/index.rst +++ b/boards/ti/cc3220sf_launchxl/doc/index.rst @@ -172,7 +172,7 @@ Flashing To build and flash an application, execute the following commands for : .. zephyr-app-commands:: - :zephyr-app: + :app: :board: cc3220sf_launchxl :goals: flash @@ -199,7 +199,7 @@ To debug a previously flashed image, after resetting the board, use the 'debug' build target: .. zephyr-app-commands:: - :zephyr-app: + :app: :board: cc3220sf_launchxl :maybe-skip-config: :goals: debug diff --git a/boards/ti/cc3235sf_launchxl/doc/index.rst b/boards/ti/cc3235sf_launchxl/doc/index.rst index cf865b89028..69c5bae82f6 100644 --- a/boards/ti/cc3235sf_launchxl/doc/index.rst +++ b/boards/ti/cc3235sf_launchxl/doc/index.rst @@ -172,7 +172,7 @@ Flashing To build and flash an application, execute the following commands for : .. zephyr-app-commands:: - :zephyr-app: + :app: :board: cc3235sf_launchxl :goals: flash @@ -199,7 +199,7 @@ To debug a previously flashed image, after resetting the board, use the 'debug' build target: .. zephyr-app-commands:: - :zephyr-app: + :app: :board: cc3235sf_launchxl :maybe-skip-config: :goals: debug diff --git a/boards/ti/common/CMakeLists.txt b/boards/ti/common/CMakeLists.txt new file mode 100644 index 00000000000..1cdd655768d --- /dev/null +++ b/boards/ti/common/CMakeLists.txt @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() +zephyr_library_sources_ifdef(CONFIG_BOARD_CC1352_LP_SKY13317 board_antenna.c) diff --git a/boards/ti/common/Kconfig b/boards/ti/common/Kconfig new file mode 100644 index 00000000000..854f88bad0c --- /dev/null +++ b/boards/ti/common/Kconfig @@ -0,0 +1,24 @@ +# TI CC1352R LaunchXL board + +# Copyright (c) 2021 Florin Stancu +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CC1352_LP_SKY13317 + bool "CC1352 LP common board antenna init" + default y if DT_HAS_SKYWORKS_SKY13317_ENABLED + help + Some CC1352 boards have a SKY13317 component + to select the antenna. This enables support + for this component for the CC1352 boards using it. + +if BOARD_CC1352_LP_SKY13317 + +config BOARD_ANTENNA_INIT_PRIO + int "Board antenna switch initialization priority" + default 70 + help + Set the priority for board init, must be greater than + KERNEL_INIT_PRIORITY_DEVICE but smaller than + IEEE802154_CC13XX_CC26XX_SUB_GHZ_INIT_PRIO. + +endif # BOARD_CC1352_LP_SKY13317 diff --git a/boards/ti/cc1352p1_launchxl/board_antenna.c b/boards/ti/common/board_antenna.c similarity index 79% rename from boards/ti/cc1352p1_launchxl/board_antenna.c rename to boards/ti/common/board_antenna.c index 8bdefedd190..5081ae7f89e 100644 --- a/boards/ti/cc1352p1_launchxl/board_antenna.c +++ b/boards/ti/common/board_antenna.c @@ -30,39 +30,31 @@ #define BOARD_ANT_GPIO_PA 1 #define BOARD_ANT_GPIO_SUBG 2 -#define ANTENNA_MUX DT_NODELABEL(antenna_mux0) - static int board_antenna_init(const struct device *dev); -static void board_cc13xx_rf_callback(RF_Handle client, RF_GlobalEvent events, - void *arg); +static void board_cc13xx_rf_callback(RF_Handle client, RF_GlobalEvent events, void *arg); const RFCC26XX_HWAttrsV2 RFCC26XX_hwAttrs = { - .hwiPriority = INT_PRI_LEVEL7, - .swiPriority = 0, + .hwiPriority = INT_PRI_LEVEL7, + .swiPriority = 0, .xoscHfAlwaysNeeded = true, /* RF driver callback for custom antenna switching */ .globalCallback = board_cc13xx_rf_callback, /* Subscribe to events */ - .globalEventMask = (RF_GlobalEventRadioSetup | - RF_GlobalEventRadioPowerDown), + .globalEventMask = (RF_GlobalEventRadioSetup | RF_GlobalEventRadioPowerDown), }; PINCTRL_DT_INST_DEFINE(0); -DEVICE_DT_INST_DEFINE(0, board_antenna_init, NULL, NULL, NULL, - POST_KERNEL, CONFIG_BOARD_ANTENNA_INIT_PRIO, NULL); +DEVICE_DT_INST_DEFINE(0, board_antenna_init, NULL, NULL, NULL, POST_KERNEL, + CONFIG_BOARD_ANTENNA_INIT_PRIO, NULL); static const struct pinctrl_dev_config *ant_pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0); static const struct gpio_dt_spec ant_gpios[] = { - GPIO_DT_SPEC_GET_BY_IDX_OR(ANTENNA_MUX, gpios, BOARD_ANT_GPIO_24G, {0}), - GPIO_DT_SPEC_GET_BY_IDX_OR(ANTENNA_MUX, gpios, BOARD_ANT_GPIO_PA, {0}), - GPIO_DT_SPEC_GET_BY_IDX_OR(ANTENNA_MUX, gpios, BOARD_ANT_GPIO_SUBG, {0}), -}; - + DT_FOREACH_PROP_ELEM_SEP(DT_NODELABEL(antenna_mux0), gpios, GPIO_DT_SPEC_GET_BY_IDX, (,))}; /** * Antenna switch GPIO init routine. */ -int board_antenna_init(const struct device *dev) +static int board_antenna_init(const struct device *dev) { ARG_UNUSED(dev); int i; @@ -79,9 +71,9 @@ int board_antenna_init(const struct device *dev) /** * Custom TI RFCC26XX callback for switching the on-board antenna mux on radio setup. */ -void board_cc13xx_rf_callback(RF_Handle client, RF_GlobalEvent events, void *arg) +static void board_cc13xx_rf_callback(RF_Handle client, RF_GlobalEvent events, void *arg) { - bool sub1GHz = false; + bool sub1GHz = false; uint8_t loDivider = 0; int i; @@ -92,8 +84,8 @@ void board_cc13xx_rf_callback(RF_Handle client, RF_GlobalEvent events, void *arg if (events & RF_GlobalEventRadioSetup) { /* Decode the current PA configuration. */ - RF_TxPowerTable_PAType paType = (RF_TxPowerTable_PAType) - RF_getTxPower(client).paType; + RF_TxPowerTable_PAType paType = + (RF_TxPowerTable_PAType)RF_getTxPower(client).paType; /* Decode the generic argument as a setup command. */ RF_RadioSetup *setupCommand = (RF_RadioSetup *)arg; diff --git a/boards/ti/cc1352r1_launchxl/boosterpack_connector.dtsi b/boards/ti/common/boosterpack_connector.dtsi similarity index 100% rename from boards/ti/cc1352r1_launchxl/boosterpack_connector.dtsi rename to boards/ti/common/boosterpack_connector.dtsi diff --git a/boards/ti/common/launchxl-flash-p7.dtsi b/boards/ti/common/launchxl-flash-p7.dtsi new file mode 100644 index 00000000000..e60b9db5a80 --- /dev/null +++ b/boards/ti/common/launchxl-flash-p7.dtsi @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2024 Alexandre Bailon + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&flash0 { + partitions { + /* 40 KiB (0xa000) for MCUboot */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x0000a000>; + }; + + /* 136 KiB (0x22000) per slot for application */ + slot0_partition: partition@a000 { + label = "image-0"; + reg = <0x0000a000 0x0004e000>; + }; + + slot1_partition: partition@58000 { + label = "image-1"; + reg = <0x00058000 0x0004e000>; + }; + + /* 32 KiB (0x8000) for storage */ + storage_partition: partition@a6000 { + label = "storage"; + reg = <0x000a6000 0x00008000>; + }; + + /* CCFG (customer configuration area) is located in uppermost + * flash sector (0x2000/8 KiB @ 0xae000), keep it unused. + */ + }; +}; diff --git a/boards/ti/common/launchxl-flash.dtsi b/boards/ti/common/launchxl-flash.dtsi new file mode 100644 index 00000000000..cdd2a0fc82e --- /dev/null +++ b/boards/ti/common/launchxl-flash.dtsi @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2021 Florin Stancu + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&flash0 { + partitions { + /* 40 KiB (0xa000) for MCUboot */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x0000a000>; + }; + + /* 136 KiB (0x22000) per slot for application */ + slot0_partition: partition@a000 { + label = "image-0"; + reg = <0x0000a000 0x00022000>; + }; + + slot1_partition: partition@2c000 { + label = "image-1"; + reg = <0x0002c000 0x00022000>; + }; + + /* 32 KiB (0x8000) for storage */ + storage_partition: partition@4e000 { + label = "storage"; + reg = <0x0004e000 0x00008000>; + }; + + /* CCFG (customer configuration area) is located in uppermost + * flash sector (0x2000/8 KiB @ 0x56000), keep it unused. + */ + }; +}; diff --git a/boards/ti/common/launchxl-pinctrl.dtsi b/boards/ti/common/launchxl-pinctrl.dtsi new file mode 100644 index 00000000000..192d49e08aa --- /dev/null +++ b/boards/ti/common/launchxl-pinctrl.dtsi @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2022 Vaishnav Achath + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + /* UART0 */ + uart0_tx_default: uart0_tx_default { + pinmux = <13 IOC_PORT_MCU_UART0_TX>; + bias-disable; + }; + uart0_rx_default: uart0_rx_default { + pinmux = <12 IOC_PORT_MCU_UART0_RX>; + bias-disable; + input-enable; + }; + + /* UART1 */ + uart1_tx_default: uart1_tx_default { + pinmux = <22 IOC_PORT_MCU_UART1_TX>; + bias-disable; + }; + uart1_rx_default: uart1_rx_default { + pinmux = <24 IOC_PORT_MCU_UART1_RX>; + bias-disable; + input-enable; + }; + + /* I2C0 */ + i2c0_scl_default: i2c0_scl_default { + pinmux = <4 IOC_PORT_MCU_I2C_MSSCL>; + bias-pull-up; + drive-open-drain; + input-enable; + }; + i2c0_sda_default: i2c0_sda_default { + pinmux = <5 IOC_PORT_MCU_I2C_MSSDA>; + bias-pull-up; + drive-open-drain; + input-enable; + }; + i2c0_scl_sleep: i2c0_scl_sleep { + pinmux = <4 IOC_PORT_GPIO>; + bias-disable; + }; + i2c0_sda_sleep: i2c0_sda_sleep { + pinmux = <5 IOC_PORT_GPIO>; + bias-disable; + }; + + /* SPI0 */ + spi0_sck_default: spi0_sck_default { + pinmux = <10 IOC_PORT_MCU_SSI0_CLK>; + bias-disable; + }; + spi0_mosi_default: spi0_mosi_default { + pinmux = <9 IOC_PORT_MCU_SSI0_TX>; + bias-disable; + }; + spi0_miso_default: spi0_miso_default { + pinmux = <8 IOC_PORT_MCU_SSI0_RX>; + bias-disable; + input-enable; + }; + spi0_cs_default: spi0_cs_default { + pinmux = <11 IOC_PORT_MCU_SSI0_FSS>; + bias-disable; + }; +}; diff --git a/boards/ti/common/launchxl.dtsi b/boards/ti/common/launchxl.dtsi new file mode 100644 index 00000000000..479489f83b6 --- /dev/null +++ b/boards/ti/common/launchxl.dtsi @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2021 Florin Stancu + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "boosterpack_connector.dtsi" +#include "launchxl-pinctrl.dtsi" +#include + +#define BTN_GPIO_FLAGS (GPIO_ACTIVE_LOW | GPIO_PULL_UP) + +/ { + aliases { + led0 = &led0; + led1 = &led1; + sw0 = &btn0; + sw1 = &btn1; + watchdog0 = &wdt0; + mcuboot-led0 = &led1; + mcuboot-button0 = &btn1; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,ieee802154 = &ieee802154; + zephyr,code-partition = &slot0_partition; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; + label = "Green LED"; + }; + led1: led_1 { + gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; + label = "Red LED"; + }; + }; + + keys { + compatible = "gpio-keys"; + btn0: btn_0 { + gpios = <&gpio0 15 BTN_GPIO_FLAGS>; + label = "Push button 1"; + zephyr,code = ; + }; + btn1: btn_1 { + gpios = <&gpio0 14 BTN_GPIO_FLAGS>; + label = "Push button 2"; + zephyr,code = ; + }; + }; +}; + +&cpu0 { + clock-frequency = <48000000>; +}; + +&trng { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_rx_default &uart0_tx_default>; + pinctrl-names = "default"; +}; + +&uart1 { + status = "disabled"; + current-speed = <115200>; + pinctrl-0 = <&uart1_rx_default &uart1_tx_default>; + pinctrl-names = "default"; +}; + +&i2c0 { + status = "okay"; + pinctrl-0 = <&i2c0_scl_default &i2c0_sda_default>; + pinctrl-1 = <&i2c0_scl_sleep &i2c0_sda_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&spi0 { + status = "okay"; + pinctrl-0 = <&spi0_sck_default &spi0_mosi_default + &spi0_miso_default &spi0_cs_default>; + pinctrl-names = "default"; + cs-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; +}; + +&radio { + status = "okay"; +}; + +&ieee802154 { + status = "okay"; +}; + +&ieee802154g { + status = "disabled"; +}; + +&wdt0 { + status = "okay"; +}; diff --git a/boards/ti/common/launchxl_sky13317.dtsi b/boards/ti/common/launchxl_sky13317.dtsi new file mode 100644 index 00000000000..132dd1ed6f7 --- /dev/null +++ b/boards/ti/common/launchxl_sky13317.dtsi @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2021 Florin Stancu + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + /** + * The CC1352P LAUNCHXL has an on-board antenna switch (SKY13317-373LF) used to select the + * appropriate RF signal port based on the currently-used PHY. + * + * Truth table: + * + * Path DIO28 DIO29 DIO30 + * =========== ===== ===== ===== + * Off 0 0 0 + * Sub-1 GHz 0 0 1 // DIO30 mux to IOC_PORT_RFC_GPO0 for auto + * 2.4 GHz 1 0 0 // DIO28 mux to IOC_PORT_RFC_GPO0 for auto + * 20 dBm TX 0 1 0 // DIO29 mux to IOC_PORT_RFC_GPO3 for auto + */ + antenna_mux0: antenna_mux0 { + compatible = "skyworks,sky13317"; + status = "okay"; + gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>, <&gpio0 29 GPIO_ACTIVE_HIGH>, \ + <&gpio0 30 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&board_ant_24g_off &board_ant_tx_pa_off &board_ant_subg_off>; + pinctrl-1 = <&board_ant_24g_on &board_ant_tx_pa_off &board_ant_subg_off>; + pinctrl-2 = <&board_ant_24g_on &board_ant_tx_pa_on &board_ant_subg_off>; + pinctrl-3 = <&board_ant_24g_off &board_ant_tx_pa_off &board_ant_subg_on>; + pinctrl-4 = <&board_ant_24g_off &board_ant_tx_pa_on &board_ant_subg_on>; + pinctrl-names = "default", "ant_24g", "ant_24g_pa", "ant_subg", "ant_subg_pa"; + }; +}; + +&pinctrl { + /* On-board antenna pinmux states */ + board_ant_24g_off: board_ant_24g_off { + pinmux = <28 IOC_PORT_GPIO>; + bias-disable; + }; + board_ant_24g_on: board_ant_24g_on { + pinmux = <28 IOC_PORT_RFC_GPO0>; + bias-disable; + }; + board_ant_tx_pa_off: board_ant_tx_pa_off { + pinmux = <29 IOC_PORT_GPIO>; + bias-disable; + }; + board_ant_tx_pa_on: board_ant_tx_pa_on { + pinmux = <29 IOC_PORT_RFC_GPO3>; + bias-disable; + }; + board_ant_subg_off: board_ant_subg_off { + pinmux = <30 IOC_PORT_GPIO>; + bias-disable; + }; + board_ant_subg_on: board_ant_subg_on { + pinmux = <30 IOC_PORT_RFC_GPO0>; + bias-disable; + }; +}; diff --git a/boards/ti/common/support/openocd.cfg b/boards/ti/common/support/openocd.cfg new file mode 100644 index 00000000000..017bb64263b --- /dev/null +++ b/boards/ti/common/support/openocd.cfg @@ -0,0 +1 @@ +source [find board/ti_cc13x2_launchpad.cfg] diff --git a/boards/ti/msp_exp432p401r_launchxl/doc/index.rst b/boards/ti/msp_exp432p401r_launchxl/doc/index.rst index e24d8140a25..e59942416f9 100644 --- a/boards/ti/msp_exp432p401r_launchxl/doc/index.rst +++ b/boards/ti/msp_exp432p401r_launchxl/doc/index.rst @@ -32,8 +32,8 @@ Supported Features ================== * The on-board 32-kHz crystal allows for lower LPM3 sleep currents and a higher-precision clock source than the - default internal 32-kHz REFOCLK. Therefore, the presence of the crystal allows the full range of low- - power modes to be used. + default internal 32-kHz REFOCLK. Therefore, the presence of the crystal allows the full range of low-power + modes to be used. * The on-board 48-MHz crystal allows the device to run at its maximum operating speed for MCLK and HSMCLK. The MSP-EXP432P401R LaunchXL development board configuration supports the following hardware features: @@ -100,7 +100,7 @@ Flashing Follow the :ref:`getting_started` instructions for Zephyr application development. -For example, to build and flash the :ref:`hello_world` application for the +For example, to build and flash the :zephyr:code-sample:`hello_world` application for the MSP-EXP432P401R LaunchXL: .. zephyr-app-commands:: diff --git a/boards/ti/sk_am62/board.cmake b/boards/ti/sk_am62/board.cmake new file mode 100644 index 00000000000..d148f687c29 --- /dev/null +++ b/boards/ti/sk_am62/board.cmake @@ -0,0 +1,10 @@ +# Texas Instruments Sitara AM62x-SK-M4 EVM +# +# Copyright (c) 2024, PHYTEC Messtechnik GmbH +# +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_AM6234_M4) + board_runner_args(openocd "--no-init" "--no-halt" "--no-targets" "--gdb-client-port=3339") + include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +endif() diff --git a/boards/ti/sk_am62/doc/index.rst b/boards/ti/sk_am62/doc/index.rst index 0a93edd1367..60252c236eb 100644 --- a/boards/ti/sk_am62/doc/index.rst +++ b/boards/ti/sk_am62/doc/index.rst @@ -94,16 +94,18 @@ The board can using remoteproc, and uses the OpenAMP resource table to accomplis The testing requires the binary to be copied to the SD card to allow the A53 cores to load it while booting using remoteproc. -To test the M4F core, we build the `hello_world` sample with the following command. +To test the M4F core, we build the :zephyr:code-sample:`hello_world` sample with the following command. .. code-block:: console # From the root of the Zephyr repository west build -p -b sk_am62/am6234/m4 samples/hello_world -This builds the program and the binary is present in the `build/zephyr` directory as `zephyr.elf`. +This builds the program and the binary is present in the :file:`build/zephyr` directory as +:file:`zephyr.elf`. -We now copy this binary onto the SD card in the `/lib/firmware` directory and name it as `am62-mcu-m4f0_0-fw`. +We now copy this binary onto the SD card in the :file:`/lib/firmware` directory and name it as +:file:`am62-mcu-m4f0_0-fw`. .. code-block:: console @@ -119,6 +121,21 @@ To allow the board to boot using the SD card, set the boot pins to the SD Card b After changing the boot mode, the board should go through the boot sequence on powering up. The binary will run and print Hello world to the MCU_UART0 port. +Debugging +********* + +The board is equipped with an XDS110 JTAG debugger. To debug a binary, utilize the ``debug`` build target: + +.. zephyr-app-commands:: + :app: + :board: sk_am62/am6234/m4 + :maybe-skip-config: + :goals: debug + +.. hint:: + To utilize this feature, you'll need OpenOCD version 0.12 or higher. Due to the possibility of + older versions being available in package feeds, it's advisable to `build OpenOCD from source`_. + References ********** @@ -136,3 +153,6 @@ AM62x SK EVM TRM: .. _EVM Setup Page: https://software-dl.ti.com/mcu-plus-sdk/esd/AM62X/08_06_00_18/exports/docs/api_guide_am62x/EVM_SETUP_PAGE.html + +.. _build OpenOCD from source: + https://docs.u-boot.org/en/latest/board/ti/k3.html#building-openocd-from-source diff --git a/boards/ti/sk_am62/support/openocd.cfg b/boards/ti/sk_am62/support/openocd.cfg new file mode 100644 index 00000000000..2b09fb7345a --- /dev/null +++ b/boards/ti/sk_am62/support/openocd.cfg @@ -0,0 +1,7 @@ +# Texas Instruments Sitara AM62x-SK-M4 EVM +# +# Copyright (c) 2024, PHYTEC Messtechnik GmbH +# +# SPDX-License-Identifier: Apache-2.0 + +source [find board/ti_am625evm.cfg] diff --git a/boards/toradex/colibri_imx7d/Kconfig.defconfig b/boards/toradex/colibri_imx7d/Kconfig.defconfig deleted file mode 100644 index 4f108737fd2..00000000000 --- a/boards/toradex/colibri_imx7d/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Colibri iMX7D M4 board - -# Copyright 2017,2024 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_COLIBRI_IMX7D_MCIMX7D_M4 - -if !XIP -config FLASH_SIZE - default 0 -config FLASH_BASE_ADDRESS - default 0 -endif - - -endif # BOARD_COLIBRI_IMX7D_MCIMX7D_M4 diff --git a/boards/toradex/colibri_imx7d/doc/index.rst b/boards/toradex/colibri_imx7d/doc/index.rst index 22b356fc1c6..dd13a140b3c 100644 --- a/boards/toradex/colibri_imx7d/doc/index.rst +++ b/boards/toradex/colibri_imx7d/doc/index.rst @@ -221,6 +221,195 @@ configured in the Zephyr compilation: setenv bootm4ddr 'run m4ddr && run bootm4' run bootm4ddr +M4<->Linux IPC using RPMSG +************************** + +The IMX7D soc supports the subsys/ipc/openamp_rsc_table sample to demonstrate the +usage of rpmsg_tty as an inter processor communication. + +The board configuration is provided for the colibri_imx7d board. +The boot process of the M4 core is handled solely by the Linux kernel using the RPROC +framework. + +The sample was tested with Toradex's LTS BSP 6.6.0 Minimal Open Embedded image with +upstream Linux kernel 6.1.83. + +Required kernel modules must be loaded for RPMSG to work: + +- imx_rproc +- virtio_rpmsg_bus +- rpmsg_tty (requiring rpmsg_core) + +You need to modify your Linux device tree to add the M4 definitions: + +- Enable MU_A +- Reserve memory areas for the M4 so Linux won't touch them. +- Define the M4 remoteproc node for the drivers. + +If you have not downloaded the BSP sources, you can modify the board's device tree +from its currently loaded dtb file. + + +.. code-block:: none + + #Check the which fdtfile is loaded for your board in U-boot + printenv + #For a Colibri_imx7d on Viola Carrier on BSP 6.6.0 + fdtfile = imx7d-colibri-emmc-eval-v3.dtb + + #Copy this file to your Linux PC through SSH from /boot + #Convert the dtb into a dts + dtc -I dtb -O dts -f imx7d-colibri-emmc-eval-v3.dtb -o imx7d-colibri-emmc-eval-v3.dts + + #You need to find the following phandle numbers: + # reset-controller + # mailbox@30aa0000 + + #Note down the phandle value (0xbd) + grep -A10 "mailbox@30aa0000 {" imx7d-colibri-emmc-eval-v3.dts + # outputs your DTS's mailbox definition + # mailbox@30aa0000 { + # compatible = "fsl,imx7s-mu\0fsl,imx6sx-mu"; + # reg = <0x30aa0000 0x10000>; + # interrupts = <0x00 0x58 0x04>; + # clocks = <0x01 0x1b1>; + # #mbox-cells = <0x02>; + # status = "disabled"; + # phandle = <0xbd>; + # }; + + #Note down the phandle value (0x32) + grep -A8 "reset-controller@30390000 {" imx7d-colibri-emmc-eval-v3.dts + # outputs your DTS's reset-controller definition + # reset-controller@30390000 { + # compatible = "fsl,imx7d-src\0syscon"; + # reg = <0x30390000 0x10000>; + # interrupts = <0x00 0x59 0x04>; + # #reset-cells = <0x01>; + # phandle = <0x32>; + # }; + + #Node down the biggest phandle value + grep "phandle = <" imx7d-colibri-emmc-eval-v3.dts | sort -r | head -1 + # outputs your DTS's largest phandle definition + # phandle = <0xca>; + + #Now we can add our nodes to the .dts file: + cp imx7d-colibri-emmc-eval-v3.dts imx7d-m4.dts + nano imx7d-m4.dts + + #Modify MU_A node to enable it + mailbox@30aa0000 { + compatible = "fsl,imx7s-mu\0fsl,imx6sx-mu"; + reg = <0x30aa0000 0x10000>; + interrupts = <0x00 0x58 0x04>; + clocks = <0x01 0x1b1>; + #mbox-cells = <0x02>; + status = "okay"; + phandle = <0xbd>; + }; + + #Add these definitions under / { } just before the __symbols__ + #Disgard the comments with #--> + reserved-memory { + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges; + + vdev0buffer0@90002000 { + compatible = "shared-dma-pool"; + reg = <0x90002000 0x8000>; + no-map; + phandle = <0xcb>; #--> biggest phandle +1 + }; + + vdev0vring0@90000000 { + compatible = "shared-dma-pool"; + reg = <0x90000000 0x1000>; + no-map; + phandle = <0xcc>; #--> biggest phandle +2 + }; + + vdev0vring1@90001000 { + compatible = "shared-dma-pool"; + reg = <0x90001000 0x1000>; + no-map; + phandle = <0xcd>; #--> biggest phandle +3 + }; + + cm4tcmcode@7f8000 { + compatible = "shared-dma-pool"; + reg = <0x7f8000 0x8000>; + no-map; + phandle = <0xce>; #--> biggest phandle +4 + }; + + cm4sramcode@900000 { + compatible = "shared-dma-pool"; + reg = <0x900000 0x40000>; + no-map; + phandle = <0xcf>; #--> biggest phandle +5 + }; + + cm4reserved@8ff00000 { + compatible = "shared-dma-pool"; + reg = <0x8ff00000 0x100000>; + no-map; + phandle = <0xd0>; #--> biggest phandle +6 + }; + }; + + imx7d-cm4 { + compatible = "fsl,imx7d-cm4"; + mbox-names = "tx\0rx\0rxdb"; + mboxes = <0xbd 0x00 0x00 0xbd 0x01 0x00 0xbd 0x03 0x00>; #--> MU_A phandle (0xbd) + memory-region = <0xcb 0xcc 0xcd 0xce 0xcf 0xd0>; #--> All the previously defined phandles + syscon = <0x32>; #--> phandle for the reset-controller + clocks = <0x01 0x42>; + }; + + #Recompile the dts into a dtb + dtc -I dts -O dtb -f imx7d-m4.dts -o imx7d-m4.dtb + + #Copy the new dtb to /boot on the Colibri IMX7 board + #Start in U-boot and update the device-tree + setenv fdtfile imx7d-m4.dtb + saveenv + boot + +When the OS has finished booting with your new device tree you can enable +the drivers and start the M4 core. + +.. code-block:: console + + #Copy zephyr_openamp_rsc_table.elf to /lib/firmware on your board + $ modprobe imx_rproc + $ modprobe virtio_rpmsg_bus + $ modprobe rpmsg_tty + + #Request RPROC to load the M4 image + $ echo stop > /sys/class/remoteproc/remoteproc0/state + $ echo zephyr_openamp_rsc_table.elf > /sys/class/remoteproc/remoteproc0/firmware + $ echo start > /sys/class/remoteproc/remoteproc0/state + + #dmesg will detail the boot process: + $ dmesg + [ 497.120499] remoteproc remoteproc0: stopped remote processor imx-rproc + [ 497.138938] remoteproc remoteproc0: powering up imx-rproc + [ 497.168735] remoteproc remoteproc0: Booting fw image zephyr_openamp_rsc_table.elf, size 1267076 + [ 497.184826] rproc-virtio rproc-virtio.1.auto: assigned reserved memory node vdev0buffer0@90002000 + [ 497.221395] virtio_rpmsg_bus virtio0: rpmsg host is online + [ 497.233806] virtio_rpmsg_bus virtio0: creating channel rpmsg-tty addr 0x400 + [ 497.236666] rproc-virtio rproc-virtio.1.auto: registered virtio0 (type 7) + [ 497.259822] remoteproc remoteproc0: remote processor imx-rproc is now up + [ 497.293913] virtio_rpmsg_bus virtio0: creating channel rpmsg-client-sample addr 0x401 + [ 497.308388] rpmsg_client_sample virtio0.rpmsg-client-sample.-1.1025: new channel: 0x401 -> 0x401! + [ 497.337969] virtio_rpmsg_bus virtio0: creating channel rpmsg-tty addr 0x402 + + $ ls /dev | grep ttyRPMSG + ttyRPMSG0 -> used for zephyr shell interface + ttyRPMSG1 -> used for sample interface + Debugging ========= diff --git a/boards/toradex/verdin_imx8mp/Kconfig.defconfig b/boards/toradex/verdin_imx8mp/Kconfig.defconfig deleted file mode 100644 index 76903f1d2e1..00000000000 --- a/boards/toradex/verdin_imx8mp/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# VERDIN_IMX8MP board defconfig - -# Copyright (c) 2023 Toradex -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_VERDIN_IMX8MP - -if !XIP -config FLASH_SIZE - default 0 -config FLASH_BASE_ADDRESS - default 0 -endif - -endif # BOARD_VERDIN_IMX8MP diff --git a/boards/toradex/verdin_imx8mp/doc/index.rst b/boards/toradex/verdin_imx8mp/doc/index.rst index de7751ff0e6..e59101fa212 100644 --- a/boards/toradex/verdin_imx8mp/doc/index.rst +++ b/boards/toradex/verdin_imx8mp/doc/index.rst @@ -251,7 +251,7 @@ Toradex Verdin iMX8M Plus SoM can be debugged by connecting an external JLink JT X56 debug connector and to the PC, or simply connecting a USB-C to X66 on the Verdin Development Board. Then, the application can be debugged using the usual way. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/u-blox/ubx_bmd300eval/Kconfig b/boards/u-blox/ubx_bmd300eval/Kconfig deleted file mode 100644 index 361d81b0fed..00000000000 --- a/boards/u-blox/ubx_bmd300eval/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# BMD-300-EVAL, BMD-301-EVAL, and BMD-350-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_UBX_BMD300EVAL diff --git a/boards/u-blox/ubx_bmd300eval/doc/index.rst b/boards/u-blox/ubx_bmd300eval/doc/index.rst index d1aea13208f..d7043adf19e 100644 --- a/boards/u-blox/ubx_bmd300eval/doc/index.rst +++ b/boards/u-blox/ubx_bmd300eval/doc/index.rst @@ -348,7 +348,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/u-blox/ubx_bmd300eval/ubx_bmd300eval_nrf52832.dts b/boards/u-blox/ubx_bmd300eval/ubx_bmd300eval_nrf52832.dts index 9594b760488..bb3bb56cfdf 100644 --- a/boards/u-blox/ubx_bmd300eval/ubx_bmd300eval_nrf52832.dts +++ b/boards/u-blox/ubx_bmd300eval/ubx_bmd300eval_nrf52832.dts @@ -133,6 +133,10 @@ }; }; +® { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; diff --git a/boards/u-blox/ubx_bmd330eval/Kconfig b/boards/u-blox/ubx_bmd330eval/Kconfig index af68ffe247b..fbc749c300a 100644 --- a/boards/u-blox/ubx_bmd330eval/Kconfig +++ b/boards/u-blox/ubx_bmd330eval/Kconfig @@ -3,12 +3,6 @@ # Copyright (c) 2021 u-blox AG # SPDX-License-Identifier: Apache-2.0 -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_UBX_BMD330EVAL - # BT_CTLR depends on BT. When BT is enabled we should default to also # enabling the controller. config BT_CTLR diff --git a/boards/u-blox/ubx_bmd330eval/doc/index.rst b/boards/u-blox/ubx_bmd330eval/doc/index.rst index 3f065cfc6d2..63c1755edfd 100644 --- a/boards/u-blox/ubx_bmd330eval/doc/index.rst +++ b/boards/u-blox/ubx_bmd330eval/doc/index.rst @@ -339,7 +339,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/u-blox/ubx_bmd330eval/ubx_bmd330eval_nrf52810.dts b/boards/u-blox/ubx_bmd330eval/ubx_bmd330eval_nrf52810.dts index c65221eb38c..4c9ce71a6b2 100644 --- a/boards/u-blox/ubx_bmd330eval/ubx_bmd330eval_nrf52810.dts +++ b/boards/u-blox/ubx_bmd330eval/ubx_bmd330eval_nrf52810.dts @@ -133,6 +133,10 @@ }; }; +® { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; diff --git a/boards/u-blox/ubx_bmd340eval/Kconfig b/boards/u-blox/ubx_bmd340eval/Kconfig deleted file mode 100644 index 6cc0ace7c6e..00000000000 --- a/boards/u-blox/ubx_bmd340eval/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# BMD-340-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_UBX_BMD340EVAL diff --git a/boards/u-blox/ubx_bmd340eval/doc/index.rst b/boards/u-blox/ubx_bmd340eval/doc/index.rst index 4e1fed4e8a1..8129bf36d4d 100644 --- a/boards/u-blox/ubx_bmd340eval/doc/index.rst +++ b/boards/u-blox/ubx_bmd340eval/doc/index.rst @@ -408,7 +408,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840.dts b/boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840.dts index d06986a8afa..66ba3f4ca60 100644 --- a/boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840.dts +++ b/boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840.dts @@ -7,6 +7,7 @@ /dts-v1/; #include +#include #include "ubx_bmd340eval_nrf52840-pinctrl.dtsi" #include @@ -20,9 +21,6 @@ zephyr,uart-mcumgr = &uart0; zephyr,bt-mon-uart = &uart0; zephyr,bt-c2h-uart = &uart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; zephyr,ieee802154 = &ieee802154; }; @@ -129,10 +127,13 @@ sw2 = &button2; sw3 = &button3; watchdog0 = &wdt0; - spi-flash0 = &mx25r64; }; }; +®1 { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; @@ -262,46 +263,6 @@ arduino_spi: &spi3 { status = "okay"; }; -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000C000>; - }; - slot0_partition: partition@c000 { - label = "image-0"; - reg = <0x0000C000 0x00067000>; - }; - slot1_partition: partition@73000 { - label = "image-1"; - reg = <0x00073000 0x00067000>; - }; - scratch_partition: partition@da000 { - label = "image-scratch"; - reg = <0x000da000 0x0001e000>; - }; - - /* - * The flash starting at 0x000f8000 and ending at - * 0x000fffff is reserved for use by the application. - */ - - /* - * Storage partition will be used by FCB/LittleFS/NVS - * if enabled. - */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; - zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; diff --git a/boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840.yaml b/boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840.yaml index be6ccd190a8..eeca79d1e5e 100644 --- a/boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840.yaml +++ b/boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840.yaml @@ -20,7 +20,6 @@ supported: - pwm - spi - qspi - - usb_cdc - usb_device - watchdog - netif:openthread diff --git a/boards/u-blox/ubx_bmd345eval/doc/index.rst b/boards/u-blox/ubx_bmd345eval/doc/index.rst index 0bcb1d201da..907370fb8a0 100644 --- a/boards/u-blox/ubx_bmd345eval/doc/index.rst +++ b/boards/u-blox/ubx_bmd345eval/doc/index.rst @@ -421,7 +421,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840.dts b/boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840.dts index ef145eabe54..a4725379c27 100644 --- a/boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840.dts +++ b/boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840.dts @@ -8,6 +8,7 @@ /dts-v1/; #include +#include #include "ubx_bmd345eval_nrf52840-pinctrl.dtsi" #include @@ -21,9 +22,6 @@ zephyr,uart-mcumgr = &uart0; zephyr,bt-mon-uart = &uart0; zephyr,bt-c2h-uart = &uart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; zephyr,ieee802154 = &ieee802154; }; @@ -141,7 +139,6 @@ mcuboot-button0 = &button0; mcuboot-led0 = &led0; watchdog0 = &wdt0; - spi-flash0 = &mx25r64; }; }; @@ -277,46 +274,6 @@ arduino_spi: &spi3 { status = "okay"; }; -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000C000>; - }; - slot0_partition: partition@c000 { - label = "image-0"; - reg = <0x0000C000 0x00067000>; - }; - slot1_partition: partition@73000 { - label = "image-1"; - reg = <0x00073000 0x00067000>; - }; - scratch_partition: partition@da000 { - label = "image-scratch"; - reg = <0x000da000 0x0001e000>; - }; - - /* - * The flash starting at 0x000f8000 and ending at - * 0x000fffff is reserved for use by the application. - */ - - /* - * Storage partition will be used by FCB/LittleFS/NVS - * if enabled. - */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; - zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; diff --git a/boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840.yaml b/boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840.yaml index fa53f794f09..f79940dbbbd 100644 --- a/boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840.yaml +++ b/boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840.yaml @@ -19,7 +19,6 @@ supported: - pwm - spi - qspi - - usb_cdc - usb_device - watchdog - netif:openthread diff --git a/boards/u-blox/ubx_bmd360eval/Kconfig b/boards/u-blox/ubx_bmd360eval/Kconfig index 89f886d08e4..60b85dcb6dd 100644 --- a/boards/u-blox/ubx_bmd360eval/Kconfig +++ b/boards/u-blox/ubx_bmd360eval/Kconfig @@ -3,12 +3,6 @@ # Copyright (c) 2021 u-blox AG # SPDX-License-Identifier: Apache-2.0 -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_UBX_BMD360EVAL - # BT_CTLR depends on BT. When BT is enabled we should default to also # enabling the controller. config BT_CTLR diff --git a/boards/u-blox/ubx_bmd360eval/doc/index.rst b/boards/u-blox/ubx_bmd360eval/doc/index.rst index 556620a1764..f0fbf264f01 100644 --- a/boards/u-blox/ubx_bmd360eval/doc/index.rst +++ b/boards/u-blox/ubx_bmd360eval/doc/index.rst @@ -337,7 +337,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811.dts b/boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811.dts index 5b8679cc065..f6b6ad8d4b6 100644 --- a/boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811.dts +++ b/boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811.dts @@ -133,6 +133,10 @@ }; }; +® { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; diff --git a/boards/u-blox/ubx_bmd380eval/Kconfig b/boards/u-blox/ubx_bmd380eval/Kconfig deleted file mode 100644 index def5144ceef..00000000000 --- a/boards/u-blox/ubx_bmd380eval/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# BMD-380-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_UBX_BMD380EVAL diff --git a/boards/u-blox/ubx_bmd380eval/doc/index.rst b/boards/u-blox/ubx_bmd380eval/doc/index.rst index 1547cfc301e..e903b1ec125 100644 --- a/boards/u-blox/ubx_bmd380eval/doc/index.rst +++ b/boards/u-blox/ubx_bmd380eval/doc/index.rst @@ -407,7 +407,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/u-blox/ubx_bmd380eval/ubx_bmd380eval_nrf52840.dts b/boards/u-blox/ubx_bmd380eval/ubx_bmd380eval_nrf52840.dts index 404678ad952..08a2b1e881a 100644 --- a/boards/u-blox/ubx_bmd380eval/ubx_bmd380eval_nrf52840.dts +++ b/boards/u-blox/ubx_bmd380eval/ubx_bmd380eval_nrf52840.dts @@ -7,6 +7,7 @@ /dts-v1/; #include +#include #include "ubx_bmd380eval_nrf52840-pinctrl.dtsi" /* should be ckaa, but not available yet */ #include @@ -21,9 +22,6 @@ zephyr,uart-mcumgr = &uart0; zephyr,bt-mon-uart = &uart0; zephyr,bt-c2h-uart = &uart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; zephyr,ieee802154 = &ieee802154; }; @@ -90,10 +88,13 @@ sw2 = &button2; sw3 = &button3; watchdog0 = &wdt0; - spi-flash0 = &mx25r64; }; }; +®1 { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; @@ -197,50 +198,6 @@ status = "okay"; }; -&flash0 { - /* - * For more information, see: - * https://docs.zephyrproject.org/latest/guides/dts/\ - legacy-macros.html#legacy-flash-partitions - */ - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000C000>; - }; - slot0_partition: partition@c000 { - label = "image-0"; - reg = <0x0000C000 0x00067000>; - }; - slot1_partition: partition@73000 { - label = "image-1"; - reg = <0x00073000 0x00067000>; - }; - scratch_partition: partition@da000 { - label = "image-scratch"; - reg = <0x000da000 0x0001e000>; - }; - - /* - * The flash starting at 0x000f8000 and ending at - * 0x000fffff is reserved for use by the application. - */ - - /* - * Storage partition will be used by FCB/LittleFS/NVS - * if enabled. - */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; - zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; diff --git a/boards/u-blox/ubx_bmd380eval/ubx_bmd380eval_nrf52840.yaml b/boards/u-blox/ubx_bmd380eval/ubx_bmd380eval_nrf52840.yaml index 15bb236585d..a794a4cac05 100644 --- a/boards/u-blox/ubx_bmd380eval/ubx_bmd380eval_nrf52840.yaml +++ b/boards/u-blox/ubx_bmd380eval/ubx_bmd380eval_nrf52840.yaml @@ -17,7 +17,6 @@ supported: - pwm - spi - qspi - - usb_cdc - usb_device - watchdog - netif:openthread diff --git a/boards/u-blox/ubx_evkannab1/Kconfig b/boards/u-blox/ubx_evkannab1/Kconfig deleted file mode 100644 index cba82a1d0b2..00000000000 --- a/boards/u-blox/ubx_evkannab1/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# u-blox EVK-ANNA-B1 board configuration -# -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_UBX_EVKANNAB1 diff --git a/boards/u-blox/ubx_evkannab1/doc/index.rst b/boards/u-blox/ubx_evkannab1/doc/index.rst index f464ab5265b..79606e292ae 100644 --- a/boards/u-blox/ubx_evkannab1/doc/index.rst +++ b/boards/u-blox/ubx_evkannab1/doc/index.rst @@ -116,7 +116,7 @@ Flashing Build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Open a terminal program to the USB Serial Port installed when connecting the board and listen for output. diff --git a/boards/u-blox/ubx_evkannab1/ubx_evkannab1_nrf52832.dts b/boards/u-blox/ubx_evkannab1/ubx_evkannab1_nrf52832.dts index 2c0f051d25f..890f02370ff 100644 --- a/boards/u-blox/ubx_evkannab1/ubx_evkannab1_nrf52832.dts +++ b/boards/u-blox/ubx_evkannab1/ubx_evkannab1_nrf52832.dts @@ -129,6 +129,10 @@ }; }; +® { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; diff --git a/boards/u-blox/ubx_evkninab1/Kconfig b/boards/u-blox/ubx_evkninab1/Kconfig deleted file mode 100644 index 280d583f721..00000000000 --- a/boards/u-blox/ubx_evkninab1/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# u-blox EVK NINA-B1 board configuration -# -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_UBX_EVKNINAB1 diff --git a/boards/u-blox/ubx_evkninab1/doc/index.rst b/boards/u-blox/ubx_evkninab1/doc/index.rst index 9073c223585..33dcecb2f00 100644 --- a/boards/u-blox/ubx_evkninab1/doc/index.rst +++ b/boards/u-blox/ubx_evkninab1/doc/index.rst @@ -124,7 +124,7 @@ Flashing Build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Open a terminal program to the USB Serial Port installed when connecting the board and listen for output. diff --git a/boards/u-blox/ubx_evkninab1/ubx_evkninab1_nrf52832.dts b/boards/u-blox/ubx_evkninab1/ubx_evkninab1_nrf52832.dts index 849c96c5e6f..69d59be9851 100644 --- a/boards/u-blox/ubx_evkninab1/ubx_evkninab1_nrf52832.dts +++ b/boards/u-blox/ubx_evkninab1/ubx_evkninab1_nrf52832.dts @@ -129,6 +129,10 @@ }; }; +® { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; diff --git a/boards/u-blox/ubx_evkninab3/Kconfig b/boards/u-blox/ubx_evkninab3/Kconfig deleted file mode 100644 index acf0948c5d5..00000000000 --- a/boards/u-blox/ubx_evkninab3/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# EVK-NINA-B3 board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_UBX_EVKNINAB3 diff --git a/boards/u-blox/ubx_evkninab3/doc/index.rst b/boards/u-blox/ubx_evkninab3/doc/index.rst index fb8b0159b34..d19f49ca704 100644 --- a/boards/u-blox/ubx_evkninab3/doc/index.rst +++ b/boards/u-blox/ubx_evkninab3/doc/index.rst @@ -223,7 +223,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840.dts b/boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840.dts index 5e15c5cc232..fe024944946 100644 --- a/boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840.dts +++ b/boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include "ubx_evkninab3_nrf52840-pinctrl.dtsi" #include @@ -19,9 +20,6 @@ zephyr,uart-mcumgr = &uart0; zephyr,bt-mon-uart = &uart0; zephyr,bt-c2h-uart = &uart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; zephyr,ieee802154 = &ieee802154; }; @@ -125,6 +123,10 @@ }; }; +®1 { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; @@ -190,46 +192,6 @@ arduino_i2c: &i2c0 { status = "okay"; }; -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000C000>; - }; - slot0_partition: partition@c000 { - label = "image-0"; - reg = <0x0000C000 0x00067000>; - }; - slot1_partition: partition@73000 { - label = "image-1"; - reg = <0x00073000 0x00067000>; - }; - scratch_partition: partition@da000 { - label = "image-scratch"; - reg = <0x000da000 0x0001e000>; - }; - - /* - * The flash starting at 0x000f8000 and ending at - * 0x000fffff is reserved for use by the application. - */ - - /* - * Storage partition will be used by FCB/LittleFS/NVS - * if enabled. - */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; - zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; diff --git a/boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840.yaml b/boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840.yaml index 90d292bc049..6e01ef035e8 100644 --- a/boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840.yaml +++ b/boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840.yaml @@ -18,7 +18,6 @@ supported: - i2c - pwm - spi - - usb_cdc - usb_device - watchdog - netif:openthread diff --git a/boards/u-blox/ubx_evkninab4/Kconfig b/boards/u-blox/ubx_evkninab4/Kconfig deleted file mode 100644 index b9ef2c7aea6..00000000000 --- a/boards/u-blox/ubx_evkninab4/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# NINA-B4 EVK board configuration -# -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_UBX_EVKNINAB4 diff --git a/boards/u-blox/ubx_evkninab4/doc/index.rst b/boards/u-blox/ubx_evkninab4/doc/index.rst index 5ad6289b590..ebb3ee05918 100644 --- a/boards/u-blox/ubx_evkninab4/doc/index.rst +++ b/boards/u-blox/ubx_evkninab4/doc/index.rst @@ -119,7 +119,7 @@ Flashing Build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details) -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Open a terminal program to the USB Serial Port installed when connecting the board and listen for output. diff --git a/boards/u-blox/ubx_evkninab4/ubx_evkninab4_nrf52833.dts b/boards/u-blox/ubx_evkninab4/ubx_evkninab4_nrf52833.dts index 521f9f6aa9e..e753c2d05ba 100644 --- a/boards/u-blox/ubx_evkninab4/ubx_evkninab4_nrf52833.dts +++ b/boards/u-blox/ubx_evkninab4/ubx_evkninab4_nrf52833.dts @@ -130,6 +130,10 @@ }; }; +®1 { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; diff --git a/boards/up-bridge-the-gap/up_squared/CMakeLists.txt b/boards/up-bridge-the-gap/up_squared/CMakeLists.txt index ddfd93807ff..98e4e9b2a82 100644 --- a/boards/up-bridge-the-gap/up_squared/CMakeLists.txt +++ b/boards/up-bridge-the-gap/up_squared/CMakeLists.txt @@ -9,7 +9,7 @@ set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py -c ${CMAKE_C_COMPILER} -o ${CMAKE_OBJCOPY} - -i ${ZEPHYR_BASE}/include + -i ${ZEPHYR_BASE}/include ${PROJECT_BINARY_DIR}/include/generated -f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf $<$:--verbose> WORKING_DIRECTORY ${PROJECT_BINARY_DIR} diff --git a/boards/up-bridge-the-gap/up_squared/Kconfig.defconfig b/boards/up-bridge-the-gap/up_squared/Kconfig.defconfig index 78d041976f1..9c721cfcc32 100644 --- a/boards/up-bridge-the-gap/up_squared/Kconfig.defconfig +++ b/boards/up-bridge-the-gap/up_squared/Kconfig.defconfig @@ -18,6 +18,8 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC if APIC_TIMER config APIC_TIMER_IRQ default 24 +endif +if APIC_TIMER_TSC config APIC_TIMER_TSC_M default 3 config APIC_TIMER_TSC_N diff --git a/boards/up-bridge-the-gap/up_squared_pro_7000/CMakeLists.txt b/boards/up-bridge-the-gap/up_squared_pro_7000/CMakeLists.txt index 36ddcdf9d13..6a250ca315c 100644 --- a/boards/up-bridge-the-gap/up_squared_pro_7000/CMakeLists.txt +++ b/boards/up-bridge-the-gap/up_squared_pro_7000/CMakeLists.txt @@ -6,7 +6,7 @@ set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py -c ${CMAKE_C_COMPILER} -o ${CMAKE_OBJCOPY} - -i ${ZEPHYR_BASE}/include + -i ${ZEPHYR_BASE}/include ${PROJECT_BINARY_DIR}/include/generated -f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf $<$:--verbose> WORKING_DIRECTORY ${PROJECT_BINARY_DIR} diff --git a/boards/up-bridge-the-gap/up_squared_pro_7000/Kconfig.defconfig b/boards/up-bridge-the-gap/up_squared_pro_7000/Kconfig.defconfig index 84744a7ea3a..e7c98f9eddf 100644 --- a/boards/up-bridge-the-gap/up_squared_pro_7000/Kconfig.defconfig +++ b/boards/up-bridge-the-gap/up_squared_pro_7000/Kconfig.defconfig @@ -19,6 +19,8 @@ if APIC_TIMER config APIC_TIMER_IRQ default 24 +endif +if APIC_TIMER_TSC config APIC_TIMER_TSC_M default 3 config APIC_TIMER_TSC_N diff --git a/boards/vcc-gnd/yd_esp32/doc/index.rst b/boards/vcc-gnd/yd_esp32/doc/index.rst index 433c1ac0c30..20201b3a347 100644 --- a/boards/vcc-gnd/yd_esp32/doc/index.rst +++ b/boards/vcc-gnd/yd_esp32/doc/index.rst @@ -6,7 +6,7 @@ YD-ESP32 Overview ******** -The YD-ESP32 development board is one of VCC-GND® Studio’s official boards. +The YD-ESP32 development board is one of VCC-GND® Studio's official boards. This board is based on the ESP32-WROOM-32E module, with the ESP32 as the core. .. figure:: img/yd_esp32.png @@ -23,7 +23,7 @@ with integrated Wi-Fi & dual-mode Bluetooth. The ESP32 series employs a Tensilica Xtensa LX6 microprocessor in both dual-core and single-core variations. ESP32 is created and developed by Espressif Systems, a Shanghai-based Chinese company, and is manufactured by TSMC using their 40nm -process. [1]_ +process. The features include the following: @@ -53,6 +53,9 @@ The features include the following: - Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) - 5uA deep sleep current +For more information, check the datasheet at `ESP32 Datasheet`_ or the technical reference +manual at `ESP32 Technical Reference Manual`_. + Supported Features ================== @@ -61,7 +64,6 @@ Current Zephyr's YD-ESP32 board supports the following features: +------------+------------+-------------------------------------+ | Interface | Controller | Driver/Component | +============+============+=====================================+ -+------------+------------+-------------------------------------+ | UART | on-chip | serial port | +------------+------------+-------------------------------------+ | GPIO | on-chip | gpio | @@ -131,7 +133,7 @@ MCUboot bootloader ================== User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. +must be built (and flashed) at least once. There are two options to be used when building an application: @@ -142,9 +144,10 @@ There are two options to be used when building an application: User can select the MCUboot bootloader by adding the following line to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y Sysbuild ======== @@ -156,7 +159,7 @@ To build the sample application using sysbuild use the command: .. zephyr-app-commands:: :tool: west - :app: samples/hello_world + :zephyr-app: samples/hello_world :board: yd_esp32 :goals: build :west-args: --sysbuild @@ -192,7 +195,7 @@ Manual build ============ During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. +For that reason, images can be built one at a time using traditional build. The instructions following are relevant for both manual build and sysbuild. The only difference is the structure of the build directory. @@ -210,7 +213,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``yd_esp32`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -239,7 +242,7 @@ The board contains an addressable RGB LED (`XL-5050RGBC-WS2812B`_), driven by GP Here is an example of how to test it using the :zephyr:code-sample:`led-strip` application. .. zephyr-app-commands:: - :zephyr-app: samples/drivers/led_strip + :zephyr-app: samples/drivers/led/led_strip :board: yd_esp32/esp32/procpu :goals: flash @@ -249,8 +252,7 @@ Here is an example of how to test it using the :zephyr:code-sample:`led-strip` a Debugging ********* -ESP32 support on OpenOCD is available upstream as of version 0.12.0. -Download and install OpenOCD from `OpenOCD`_. +ESP32 support on OpenOCD is available at `OpenOCD ESP32`_. On the YD-ESP32 board, the JTAG pins are not run to a standard connector (e.g. ARM 20-pin) and need to be manually connected @@ -274,17 +276,16 @@ to the external programmer (e.g. a Flyswatter2): | IO15 | TDO | +------------+-----------+ -Further documentation can be obtained from the SoC vendor in `JTAG debugging -for ESP32`_. +Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32`_. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: yd_esp32/esp32/procpu :goals: build flash -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -302,12 +303,11 @@ GDB stub is enabled on ESP32. This does not work as the code is on flash which cannot be randomly accessed for modification. -.. _`JTAG debugging for ESP32`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/jtag-debugging/index.html -.. _`OpenOCD`: https://github.com/openocd-org/openocd - References ********** -.. [1] https://en.wikipedia.org/wiki/ESP32 -.. _ESP32 Technical Reference Manual: https://espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf -.. _Hardware Reference: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/hw-reference/index.html +.. _`ESP32-DevKitC-WROVER`: https://docs.espressif.com/projects/esp-idf/en/stable/esp32/hw-reference/esp32/get-started-devkitc.html# +.. _`ESP32 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf +.. _`ESP32 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf +.. _`JTAG debugging for ESP32`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/jtag-debugging/index.html +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/vcc-gnd/yd_esp32/yd_esp32_appcpu.dts b/boards/vcc-gnd/yd_esp32/yd_esp32_appcpu.dts index 6bed6d38402..8501714220d 100644 --- a/boards/vcc-gnd/yd_esp32/yd_esp32_appcpu.dts +++ b/boards/vcc-gnd/yd_esp32/yd_esp32_appcpu.dts @@ -18,14 +18,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &ipm0 { status = "okay"; }; diff --git a/boards/vcc-gnd/yd_esp32/yd_esp32_procpu.dts b/boards/vcc-gnd/yd_esp32/yd_esp32_procpu.dts index 8560ba7a4f9..a409ed6e909 100644 --- a/boards/vcc-gnd/yd_esp32/yd_esp32_procpu.dts +++ b/boards/vcc-gnd/yd_esp32/yd_esp32_procpu.dts @@ -48,15 +48,6 @@ }; }; -&cpu0 { - clock-frequency = ; - cpu-power-states = <&light_sleep &deep_sleep>; -}; - -&cpu1 { - clock-frequency = ; -}; - &uart0 { status = "okay"; current-speed = <115200>; diff --git a/boards/vcc-gnd/yd_stm32h750vb/Kconfig.defconfig b/boards/vcc-gnd/yd_stm32h750vb/Kconfig.defconfig new file mode 100644 index 00000000000..8e5ecbe7ff2 --- /dev/null +++ b/boards/vcc-gnd/yd_stm32h750vb/Kconfig.defconfig @@ -0,0 +1,11 @@ +# YD-STM32H750VB board configuration + +# Copyright(c) 2024 John Sanpe +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_YD_STM32H750VB + +config DISK_DRIVER_SDMMC + default y if DISK_DRIVERS + +endif # BOARD_YD_STM32H750VB diff --git a/boards/vcc-gnd/yd_stm32h750vb/Kconfig.yd_stm32h750vb b/boards/vcc-gnd/yd_stm32h750vb/Kconfig.yd_stm32h750vb new file mode 100644 index 00000000000..14b5ebe4648 --- /dev/null +++ b/boards/vcc-gnd/yd_stm32h750vb/Kconfig.yd_stm32h750vb @@ -0,0 +1,7 @@ +# YD-STM32H750VB board configuration + +# Copyright(c) 2024 John Sanpe +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_YD_STM32H750VB + select SOC_STM32H750XX diff --git a/boards/vcc-gnd/yd_stm32h750vb/board.cmake b/boards/vcc-gnd/yd_stm32h750vb/board.cmake new file mode 100644 index 00000000000..2cf1e034d59 --- /dev/null +++ b/boards/vcc-gnd/yd_stm32h750vb/board.cmake @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(dfu-util "--pid=0483:df11" "--alt=0" "--dfuse") +board_runner_args(jlink "--device=STM32H735IG" "--speed=4000") +board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") + +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/vcc-gnd/yd_stm32h750vb/board.yml b/boards/vcc-gnd/yd_stm32h750vb/board.yml new file mode 100644 index 00000000000..f26fffaa901 --- /dev/null +++ b/boards/vcc-gnd/yd_stm32h750vb/board.yml @@ -0,0 +1,5 @@ +board: + name: yd_stm32h750vb + vendor: vcc-gnd + socs: + - name: stm32h750xx diff --git a/boards/vcc-gnd/yd_stm32h750vb/doc/img/yd_stm32h750vb.png b/boards/vcc-gnd/yd_stm32h750vb/doc/img/yd_stm32h750vb.png new file mode 100644 index 00000000000..814f26a1099 Binary files /dev/null and b/boards/vcc-gnd/yd_stm32h750vb/doc/img/yd_stm32h750vb.png differ diff --git a/boards/vcc-gnd/yd_stm32h750vb/doc/index.rst b/boards/vcc-gnd/yd_stm32h750vb/doc/index.rst new file mode 100644 index 00000000000..2b5e1794bd2 --- /dev/null +++ b/boards/vcc-gnd/yd_stm32h750vb/doc/index.rst @@ -0,0 +1,133 @@ +.. _yd_stm32h750vb: + +YD-STM32H750VB +############## + +Overview +******** + +The YD-STM32H750VB development board is a complete demonstration and development +platform for Arm |reg| Cortex |reg|-M7 core-based STM32H750VBT6 microcontroller, with +128Kbytes of Flash memory and 1 Mbytes of SRAM. + +.. image:: img/yd_stm32h750vb.png + :align: center + :alt: YD-STM32H750VB + +More information about STM32H750 can be found here: + +- `STM32H750 on www.st.com`_ +- `STM32H750xx reference manual`_ +- `STM32H750xx datasheet`_ + +Supported Features +================== + +The current Zephyr YD-STM32H750VB board supports the following features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/vcc-gnd/yd_stm32h750vb/yd_stm32h750vb_defconfig` + +Pin Mapping +=========== + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1_TX : PA9 +- UART_1_RX : PA10 +- LED_1 : PA13 (SWDIO) +- LED_2 : PA14 (SWCLK) +- LED_3 : PA15 +- LED_4 : PB4 +- KEY : PB3 + +System Clock +============ + +The STM32H750VB System Clock can be driven by an internal or external oscillator, +as well as by the main PLL clock. By default, the System clock +is driven by the PLL clock at 480MHz. PLL clock is feed by a 25MHz high speed external clock. + +Flashing +======== + +There are 2 main entry points for flashing STM32H750VB SoCs, one using the ROM +bootloader, and another by using the SWD debug port (which requires additional +hardware such as ST-Link). Flashing using the ROM bootloader requires a special activation +pattern, which can be triggered by using the BOOT0 button. + +Installing dfu-util +------------------- + +It is recommended to use at least v0.8 of `dfu-util`_. The package available in +debian/ubuntu can be quite old, so you might have to build dfu-util from source. + +There is also a Windows version which works, but you may have to install the +right USB drivers with a tool like `Zadig`_. + +Flashing an application to YD-STM32H750VB +----------------------------------------- + +Connect a USB-C cable and the board should power ON. Force the board into DFU mode +by keeping the BOOT0 switch pressed while pressing and releasing the RST switch. + +The dfu-util runner is supported on this board and so a sample can be built and +tested easily. + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: yd_stm32h750vb + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: yd_stm32h750vb + :goals: debug + +References +********** + +.. target-notes:: + +.. _Zadig: + https://zadig.akeo.ie/ + +.. _dfu-util: + http://dfu-util.sourceforge.net/build.html + +.. _STM32H750 on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32h750-value-line.html + +.. _STM32H750xx reference manual: + https://www.st.com/resource/en/reference_manual/rm0433-stm32h742-stm32h743753-and-stm32h750-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32H750xx datasheet: + https://www.st.com/resource/en/datasheet/stm32h750vb.pdf diff --git a/boards/vcc-gnd/yd_stm32h750vb/support/openocd.cfg b/boards/vcc-gnd/yd_stm32h750vb/support/openocd.cfg new file mode 100644 index 00000000000..f7674378361 --- /dev/null +++ b/boards/vcc-gnd/yd_stm32h750vb/support/openocd.cfg @@ -0,0 +1,30 @@ +source [find interface/stlink-dap.cfg] +transport select dapdirect_swd + +set WORKAREASIZE 0x2000 +set CHIPNAME STM23H750VB +set BOARDNAME YD_STM23H750VB + +source [find target/stm32h7x.cfg] + +# Use connect_assert_srst here to be able to program +# even when core is in sleep mode +reset_config srst_only srst_nogate connect_assert_srst + +$_CHIPNAME.cpu0 configure -event gdb-attach { + echo "Debugger attaching: halting execution" + gdb_breakpoint_override hard +} + +$_CHIPNAME.cpu0 configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} + +# Due to the use of connect_assert_srst, running gdb requires +# to reset halt just after openocd init. +rename init old_init +proc init {} { + old_init + reset halt +} diff --git a/boards/vcc-gnd/yd_stm32h750vb/yd_stm32h750vb.dts b/boards/vcc-gnd/yd_stm32h750vb/yd_stm32h750vb.dts new file mode 100644 index 00000000000..926f1f56454 --- /dev/null +++ b/boards/vcc-gnd/yd_stm32h750vb/yd_stm32h750vb.dts @@ -0,0 +1,134 @@ +/* + * Copyright(c) 2024 John Sanpe + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include + +/ { + model = "VCC-GND Studio STM32H750VB"; + compatible = "st,stm32h750vb"; + + aliases { + led0 = &yellow_led; + led1 = &blue_led; + sw0 = &user_button; + spi-flash0 = &w25q128jv; + }; + + chosen { + zephyr,console = &usart1; + zephyr,shell-uart = &usart1; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,flash-controller = &w25q128jv; + }; + + leds { + compatible = "gpio-leds"; + red_led: led_1 { + gpios = <&gpioa 13 GPIO_ACTIVE_HIGH>; + label = "LED1"; + status = "disabled"; + }; + green_led: led_2 { + gpios = <&gpioa 14 GPIO_ACTIVE_HIGH>; + label = "LED2"; + status = "disabled"; + }; + yellow_led: led_3 { + gpios = <&gpioa 15 GPIO_ACTIVE_HIGH>; + label = "LED3"; + }; + blue_led: led_4 { + gpios = <&gpiob 4 GPIO_ACTIVE_HIGH>; + label = "LED4"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button: button { + gpios = <&gpiob 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + zephyr,code = ; + label = "USR"; + }; + }; +}; + +&clk_hse { + clock-frequency = ; + status = "okay"; +}; + +&clk_lse { + status = "okay"; +}; + +&pll { + div-m = <5>; + mul-n = <192>; + div-p = <2>; + div-q = <4>; + div-r = <4>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + d1cpre = <1>; + hpre = <2>; + d1ppre = <2>; + d2ppre1 = <2>; + d2ppre2 = <2>; + d3ppre = <2>; +}; + +&usart1 { + pinctrl-names = "default"; + pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; + current-speed = <115200>; + status = "okay"; +}; + +&sdmmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9 + &sdmmc1_d2_pc10 &sdmmc1_d3_pc11 + &sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>; + cd-gpios = <&gpioa 8 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&quadspi { + pinctrl-names = "default"; + pinctrl-0 = <&quadspi_clk_pb2 &quadspi_bk1_ncs_pb10 + &quadspi_bk1_io0_pd11 &quadspi_bk1_io1_pd12 + &quadspi_bk1_io2_pe2 &quadspi_bk1_io3_pd13>; + status = "okay"; + + w25q128jv: qspi-nor-flash@90000000 { + compatible = "st,stm32-qspi-nor"; + reg = <0x90000000 DT_SIZE_M(16)>; + qspi-max-frequency = <80000000>; + spi-bus-width = <4>; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@0 { + label = "storage"; + reg = <0x0 DT_SIZE_M(16)>; + }; + }; + }; +}; diff --git a/boards/vcc-gnd/yd_stm32h750vb/yd_stm32h750vb.yaml b/boards/vcc-gnd/yd_stm32h750vb/yd_stm32h750vb.yaml new file mode 100644 index 00000000000..0ce537a1bd4 --- /dev/null +++ b/boards/vcc-gnd/yd_stm32h750vb/yd_stm32h750vb.yaml @@ -0,0 +1,15 @@ +identifier: yd_stm32h750vb +name: YD-STM32H750VB +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 1024 +flash: 128 +supported: + - gpio + - uart + - qspi +vendor: vcc-gnd diff --git a/boards/vcc-gnd/yd_stm32h750vb/yd_stm32h750vb_defconfig b/boards/vcc-gnd/yd_stm32h750vb/yd_stm32h750vb_defconfig new file mode 100644 index 00000000000..40e6adc0583 --- /dev/null +++ b/boards/vcc-gnd/yd_stm32h750vb/yd_stm32h750vb_defconfig @@ -0,0 +1,26 @@ +# Copyright(c) 2024 John Sanpe +# SPDX-License-Identifier: Apache-2.0 + +# Enable the internal SMPS regulator +CONFIG_POWER_SUPPLY_LDO=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_SERIAL=y + +# console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# enable GPIO +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/vngiotlab/nrf51_vbluno51/doc/index.rst b/boards/vngiotlab/nrf51_vbluno51/doc/index.rst index e4f6b58a68a..b56bcdd093d 100644 --- a/boards/vngiotlab/nrf51_vbluno51/doc/index.rst +++ b/boards/vngiotlab/nrf51_vbluno51/doc/index.rst @@ -135,11 +135,11 @@ Testing the VBLUno51 with Zephyr: buttons, LEDs, UART, BLE Here are some sample applications that you can use to test different components on the VBLUno51 board: - * :ref:`hello_world` + * :zephyr:code-sample:`hello_world` * :zephyr:code-sample:`blinky` * :zephyr:code-sample:`button` - * :ref:`bluetooth-beacon-sample` - * :ref:`peripheral_hr` + * :zephyr:code-sample:`bluetooth_beacon` + * :zephyr:code-sample:`ble_peripheral_hr` References ********** diff --git a/boards/vngiotlab/nrf52_vbluno52/doc/index.rst b/boards/vngiotlab/nrf52_vbluno52/doc/index.rst index 5342fdf81c4..68a7c1b97c6 100644 --- a/boards/vngiotlab/nrf52_vbluno52/doc/index.rst +++ b/boards/vngiotlab/nrf52_vbluno52/doc/index.rst @@ -87,7 +87,7 @@ See the :ref:`getting_started` for general information on setting up your development environment. You can build and flash applications in the usual way. Here is an -example for the :ref:`hello_world` application. +example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -100,8 +100,8 @@ Testing the VBLUno52 with Zephyr: buttons, LEDs, UART, BLE Here are some sample applications that you can use to test different components on the VBLUno52 board: -* :ref:`hello_world` +* :zephyr:code-sample:`hello_world` * :zephyr:code-sample:`blinky` * :zephyr:code-sample:`button` -* :ref:`bluetooth-beacon-sample` -* :ref:`peripheral_hr` +* :zephyr:code-sample:`bluetooth_beacon` +* :zephyr:code-sample:`ble_peripheral_hr` diff --git a/boards/waveshare/esp32s3_touch_lcd_1_28/doc/index.rst b/boards/waveshare/esp32s3_touch_lcd_1_28/doc/index.rst index 3395bcff2ee..2d56d559b96 100644 --- a/boards/waveshare/esp32s3_touch_lcd_1_28/doc/index.rst +++ b/boards/waveshare/esp32s3_touch_lcd_1_28/doc/index.rst @@ -54,7 +54,8 @@ ESP32-S3 allows 2 different applications to be executed in ESP32-S3 SoC. Due to architecture, each core can be enabled to execute customized tasks in stand-alone mode and/or exchanging data over OpenAMP framework. See :ref:`ipc_samples` folder as code reference. -For more information, check the datasheet at `ESP32-S3 Datasheet`_. +For more information, check the datasheet at `ESP32-S3 Datasheet`_ or the technical reference +manual at `ESP32-S3 Technical Reference Manual`_. Supported Features ================== @@ -108,16 +109,19 @@ below to retrieve those files. Building & Flashing ******************* -ESP-IDF bootloader -================== +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. + Simple boot does not provide any security features nor OTA updates. References ********** .. _ESP32-S3-Touch-LCD-1.28 Waveshare Wiki: https://www.waveshare.com/wiki/ESP32-S3-Touch-LCD-1.28 .. _ESP32-S3 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-s3-mini-1_mini-1u_datasheet_en.pdf -.. _ESP32 Technical Reference Manual: https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf +.. _ESP32-S3 Technical Reference Manual: https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf diff --git a/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_appcpu.dts b/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_appcpu.dts index 50301f22c20..9b345338aa4 100644 --- a/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_appcpu.dts +++ b/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_appcpu.dts @@ -15,14 +15,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &flash0 { status = "okay"; reg = <0x0 DT_SIZE_M(16)>; diff --git a/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_procpu.dts b/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_procpu.dts index e4c974f7c19..cb4bd891f61 100644 --- a/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_procpu.dts +++ b/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_procpu.dts @@ -56,14 +56,28 @@ pwms = <&ledc0 0 PWM_HZ(250) PWM_POLARITY_NORMAL>; }; }; -}; - -&cpu0 { - clock-frequency = ; -}; -&cpu1 { - clock-frequency = ; + /* MIPI DBI */ + mipi_dbi { + compatible = "zephyr,mipi-dbi-spi"; + spi-dev = <&spi2>; + dc-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + write-only; + #address-cells = <1>; + #size-cells = <0>; + + gc9a01: gc9a01@0 { + status = "okay"; + compatible = "galaxycore,gc9x01x"; + reg = <0>; + mipi-max-frequency = <100000000>; + pixel-format = ; + display-inversion; + width = <240>; + height = <240>; + }; + }; }; &flash0 { @@ -154,19 +168,6 @@ pinctrl-0 = <&spim2_default>; pinctrl-names = "default"; cs-gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; - - gc9a01: gc9a01@0 { - status = "okay"; - compatible = "galaxycore,gc9x01x"; - reg = <0>; - spi-max-frequency = <100000000>; - cmd-data-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; - pixel-format = ; - display-inversion; - width = <240>; - height = <240>; - }; }; &trng0 { diff --git a/boards/waveshare/nrf51_ble400/doc/index.rst b/boards/waveshare/nrf51_ble400/doc/index.rst index 3bfe06aa204..3d34f2f27f0 100644 --- a/boards/waveshare/nrf51_ble400/doc/index.rst +++ b/boards/waveshare/nrf51_ble400/doc/index.rst @@ -168,7 +168,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/waveshare/open103z/doc/index.rst b/boards/waveshare/open103z/doc/index.rst index 2cd9c7a6ac0..773b60f202f 100644 --- a/boards/waveshare/open103z/doc/index.rst +++ b/boards/waveshare/open103z/doc/index.rst @@ -55,7 +55,7 @@ Flashing ======== Build and flash applications as usual. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -66,7 +66,7 @@ Debugging ========= Debug applications as usual. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/waveshare/open103z/waveshare_open103z_defconfig b/boards/waveshare/open103z/waveshare_open103z_defconfig index 9fd4400ac20..5568aa36c02 100644 --- a/boards/waveshare/open103z/waveshare_open103z_defconfig +++ b/boards/waveshare/open103z/waveshare_open103z_defconfig @@ -8,9 +8,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -# enable clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/we/ophelia1ev/Kconfig b/boards/we/ophelia1ev/Kconfig deleted file mode 100644 index 2b36398f590..00000000000 --- a/boards/we/ophelia1ev/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Ophelia-I EV nRF52805 board configuration - -# Copyright (c) 2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_WE_OPHELIA1EV diff --git a/boards/we/ophelia1ev/doc/index.rst b/boards/we/ophelia1ev/doc/index.rst index d64c32579a5..908b0ce6889 100644 --- a/boards/we/ophelia1ev/doc/index.rst +++ b/boards/we/ophelia1ev/doc/index.rst @@ -82,7 +82,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/we/ophelia1ev/we_ophelia1ev_nrf52805.dts b/boards/we/ophelia1ev/we_ophelia1ev_nrf52805.dts index 4d7c3d8cc0b..5300281439b 100644 --- a/boards/we/ophelia1ev/we_ophelia1ev_nrf52805.dts +++ b/boards/we/ophelia1ev/we_ophelia1ev_nrf52805.dts @@ -57,6 +57,10 @@ }; }; +® { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; diff --git a/boards/we/proteus2ev/Kconfig b/boards/we/proteus2ev/Kconfig deleted file mode 100644 index f0729af5c1f..00000000000 --- a/boards/we/proteus2ev/Kconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Proteus-II-EV board configuration - -# Copyright (c) 2016 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_WE_PROTEUS2EV_NRF52832 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_WE_PROTEUS2EV_NRF52832 - -endif # BOARD_WE_PROTEUS2EV_NRF52832 diff --git a/boards/we/proteus2ev/doc/index.rst b/boards/we/proteus2ev/doc/index.rst index 5492b4159fe..19a7df8fbac 100644 --- a/boards/we/proteus2ev/doc/index.rst +++ b/boards/we/proteus2ev/doc/index.rst @@ -112,7 +112,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/we/proteus2ev/we_proteus2ev_nrf52832.dts b/boards/we/proteus2ev/we_proteus2ev_nrf52832.dts index ef7eede1f75..b0d4a38e448 100644 --- a/boards/we/proteus2ev/we_proteus2ev_nrf52832.dts +++ b/boards/we/proteus2ev/we_proteus2ev_nrf52832.dts @@ -52,6 +52,10 @@ }; }; +® { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; diff --git a/boards/we/proteus3ev/Kconfig b/boards/we/proteus3ev/Kconfig deleted file mode 100644 index 06a2c989d8a..00000000000 --- a/boards/we/proteus3ev/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -# Proteus-III-EV board configuration - -# Copyright (c) 2016 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_WE_PROTEUS3EV - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF52X_HV - default y - -endif # BOARD_WE_PROTEUS3EV diff --git a/boards/we/proteus3ev/doc/index.rst b/boards/we/proteus3ev/doc/index.rst index dd6c5f47d6c..87180a801b4 100644 --- a/boards/we/proteus3ev/doc/index.rst +++ b/boards/we/proteus3ev/doc/index.rst @@ -114,7 +114,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/we/proteus3ev/we_proteus3ev_nrf52840.dts b/boards/we/proteus3ev/we_proteus3ev_nrf52840.dts index 62cecf7066e..63c4e5b9756 100644 --- a/boards/we/proteus3ev/we_proteus3ev_nrf52840.dts +++ b/boards/we/proteus3ev/we_proteus3ev_nrf52840.dts @@ -3,6 +3,7 @@ /dts-v1/; #include +#include #include "we_proteus3ev_nrf52840-pinctrl.dtsi" #include @@ -16,9 +17,6 @@ zephyr,uart-mcumgr = &uart0; zephyr,bt-mon-uart = &uart0; zephyr,bt-c2h-uart = &uart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; }; leds { @@ -53,6 +51,14 @@ }; }; +®0 { + status = "okay"; +}; + +®1 { + regulator-initial-mode = ; +}; + &adc { status = "okay"; }; @@ -99,42 +105,3 @@ pinctrl-1 = <&spi0_sleep>; pinctrl-names = "default", "sleep"; }; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000C000>; - }; - slot0_partition: partition@c000 { - label = "image-0"; - reg = <0x0000C000 0x00067000>; - }; - slot1_partition: partition@73000 { - label = "image-1"; - reg = <0x00073000 0x00067000>; - }; - scratch_partition: partition@da000 { - label = "image-scratch"; - reg = <0x000da000 0x0001e000>; - }; - - /* - * The flash starting at 0x000f8000 and ending at - * 0x000fffff is reserved for use by the application. - */ - - /* - * Storage partition will be used by FCB/LittleFS/NVS - * if enabled. - */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; diff --git a/boards/weact/blackpill_f401cc/blackpill_f401cc_defconfig b/boards/weact/blackpill_f401cc/blackpill_f401cc_defconfig index 180ea77ffc9..cea713f4da6 100644 --- a/boards/weact/blackpill_f401cc/blackpill_f401cc_defconfig +++ b/boards/weact/blackpill_f401cc/blackpill_f401cc_defconfig @@ -15,9 +15,3 @@ CONFIG_UART_CONSOLE=y # Enable GPIO CONFIG_GPIO=y - -# Clock configuration -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/weact/blackpill_f401ce/blackpill_f401ce_defconfig b/boards/weact/blackpill_f401ce/blackpill_f401ce_defconfig index 8f08a2bfe96..eea1cfeeb30 100644 --- a/boards/weact/blackpill_f401ce/blackpill_f401ce_defconfig +++ b/boards/weact/blackpill_f401ce/blackpill_f401ce_defconfig @@ -14,9 +14,3 @@ CONFIG_UART_CONSOLE=y # Enable GPIO CONFIG_GPIO=y - -# Clock configuration -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/weact/blackpill_f411ce/blackpill_f411ce_defconfig b/boards/weact/blackpill_f411ce/blackpill_f411ce_defconfig index 8f08a2bfe96..eea1cfeeb30 100644 --- a/boards/weact/blackpill_f411ce/blackpill_f411ce_defconfig +++ b/boards/weact/blackpill_f411ce/blackpill_f411ce_defconfig @@ -14,9 +14,3 @@ CONFIG_UART_CONSOLE=y # Enable GPIO CONFIG_GPIO=y - -# Clock configuration -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/weact/mini_stm32h743/doc/index.rst b/boards/weact/mini_stm32h743/doc/index.rst index 4a96538ac1b..9b63292ad57 100644 --- a/boards/weact/mini_stm32h743/doc/index.rst +++ b/boards/weact/mini_stm32h743/doc/index.rst @@ -168,7 +168,7 @@ the device using the west tool or the STM32CubeProgrammer. Flashing an application to MiniSTM32H743 ---------------------------------------- -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, put the board in bootloader mode as described above. Then build and flash the application in the usual way. Just add ``CONFIG_BOOT_DELAY=5000`` to the diff --git a/boards/weact/mini_stm32h743/mini_stm32h743.dts b/boards/weact/mini_stm32h743/mini_stm32h743.dts index 9aa6dcffc1b..9968b82d7d7 100644 --- a/boards/weact/mini_stm32h743/mini_stm32h743.dts +++ b/boards/weact/mini_stm32h743/mini_stm32h743.dts @@ -8,6 +8,7 @@ #include #include #include +#include / { model = "WeAct Studio MiniSTM32H743 Core Board"; @@ -18,7 +19,7 @@ zephyr,shell-uart = &usb_cdc_acm_uart; zephyr,sram = &sram0; zephyr,flash = &flash0; - zephyr,display = &st7735r_tft; + zephyr,display = &st7735r_160x80; }; leds { @@ -38,10 +39,47 @@ }; }; + mipi_dbi_st7735r_160x80 { + compatible = "zephyr,mipi-dbi-spi"; + spi-dev = <&spi4>; + dc-gpios = <&gpioe 13 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + st7735r_160x80: st7735r@0 { + compatible = "sitronix,st7735r"; + mipi-max-frequency = <20000000>; + mipi-mode = ; + reg = <0>; + width = <160>; + height = <80>; + inversion-on; + rgb-is-inverted; + x-offset = <1>; + y-offset = <26>; + pwctr1 = [A2 02 84]; + pwctr2 = [C5]; + pwctr3 = [0A 00]; + pwctr4 = [8A 2A]; + pwctr5 = [8A EE]; + invctr = <7>; + frmctr1 = [01 2C 2D]; + frmctr2 = [01 2C 2D]; + frmctr3 = [01 2C 2D 01 2C 2D]; + vmctr1 = <14>; + gamctrp1 = [02 1C 07 12 37 32 29 2D 29 25 2B 39 00 01 03 10]; + gamctrn1 = [03 1D 07 06 2E 2C 29 2D 2E 2E 37 3F 00 00 02 10]; + colmod = <5>; + /* Set D3 (RGB) bit to 1. LV_COLOR_16_SWAP is enabled by default */ + madctl = <120>; /* Set to <184> to rotate the image 180 degrees. */ + caset = [00 01 00 a0]; + raset = [00 1a 00 69]; + }; + }; + aliases { led0 = &user_led; sw0 = &user_button; - spi-flash0 = &w25q64_spi; watchdog0 = &iwdg; sdhc0 = &sdmmc1; }; @@ -154,42 +192,21 @@ zephyr_udc0: &usbotg_fs { }; }; +&gpioe { + status = "okay"; + + lcd_led { + gpio-hog; + gpios = <10 GPIO_ACTIVE_LOW>; + output-high; + }; +}; + &spi4 { pinctrl-0 = <&spi4_sck_pe12 &spi4_mosi_pe14>; cs-gpios = <&gpioe 11 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; status = "okay"; - - st7735r_tft: st7735r@0 { - compatible = "sitronix,st7735r"; - spi-max-frequency = <20000000>; - reg = <0>; - cmd-data-gpios = <&gpioe 13 GPIO_ACTIVE_LOW>; - reset-gpios = <&gpioe 10 GPIO_ACTIVE_HIGH>; - width = <160>; - height = <80>; - inversion-on; - rgb-is-inverted; - x-offset = <1>; - y-offset = <26>; - pwctr1 = [A2 02 84]; - pwctr2 = [C5]; - pwctr3 = [0A 00]; - pwctr4 = [8A 2A]; - pwctr5 = [8A EE]; - invctr = <7>; - frmctr1 = [01 2C 2D]; - frmctr2 = [01 2C 2D]; - frmctr3 = [01 2C 2D 01 2C 2D]; - vmctr1 = <14>; - gamctrp1 = [02 1C 07 12 37 32 29 2D 29 25 2B 39 00 01 03 10]; - gamctrn1 = [03 1D 07 06 2E 2C 29 2D 2E 2E 37 3F 00 00 02 10]; - colmod = <5>; - /* Set D3 (RGB) bit to 1. LV_COLOR_16_SWAP is enabled by default in Kconfig */ - madctl = <120>; /* Set to <184> to rotate the image 180 degrees. */ - caset = [00 01 00 a0]; - raset = [00 1a 00 69]; - }; }; &rng { diff --git a/boards/weact/mini_stm32h743/mini_stm32h743_defconfig b/boards/weact/mini_stm32h743/mini_stm32h743_defconfig index 39e63d879a2..809e85276c9 100644 --- a/boards/weact/mini_stm32h743/mini_stm32h743_defconfig +++ b/boards/weact/mini_stm32h743/mini_stm32h743_defconfig @@ -16,12 +16,6 @@ CONFIG_CONSOLE=y # Enable GPIO CONFIG_GPIO=y -# Enable clocks -CONFIG_CLOCK_CONTROL=y - -# Enable pin controller -CONFIG_PINCTRL=y - # Logger cannot use itself to log CONFIG_USB_CDC_ACM_LOG_LEVEL_OFF=y diff --git a/boards/weact/stm32f405_core/Kconfig.weact_stm32f405_core b/boards/weact/stm32f405_core/Kconfig.weact_stm32f405_core new file mode 100644 index 00000000000..3dc11bba2c4 --- /dev/null +++ b/boards/weact/stm32f405_core/Kconfig.weact_stm32f405_core @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Pavlo Yadvychuk +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_WEACT_STM32F405_CORE + select SOC_STM32F405XX diff --git a/boards/weact/stm32f405_core/board.cmake b/boards/weact/stm32f405_core/board.cmake new file mode 100644 index 00000000000..e4af5f534df --- /dev/null +++ b/boards/weact/stm32f405_core/board.cmake @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(dfu-util "--pid=0483:df11" "--alt=0" "--dfuse") +board_runner_args(jlink "--device=STM32F405RG" "--speed=4000") + +include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/weact/stm32f405_core/board.yml b/boards/weact/stm32f405_core/board.yml new file mode 100644 index 00000000000..8f85783cde9 --- /dev/null +++ b/boards/weact/stm32f405_core/board.yml @@ -0,0 +1,5 @@ +board: + name: weact_stm32f405_core + vendor: weact + socs: + - name: stm32f405xx diff --git a/boards/weact/stm32f405_core/doc/img/stm32f405_core.jpg b/boards/weact/stm32f405_core/doc/img/stm32f405_core.jpg new file mode 100644 index 00000000000..4c8e470f08e Binary files /dev/null and b/boards/weact/stm32f405_core/doc/img/stm32f405_core.jpg differ diff --git a/boards/weact/stm32f405_core/doc/index.rst b/boards/weact/stm32f405_core/doc/index.rst new file mode 100644 index 00000000000..e08ec5cb787 --- /dev/null +++ b/boards/weact/stm32f405_core/doc/index.rst @@ -0,0 +1,183 @@ +.. _weact_stm32f405_core: + +WeAct Studio STM32F405 Core Board V1.0 +###################################### + +Overview +******** + +The WeAct STM32F405 Core Board is an extremely low cost and bare-bones +development board featuring the STM32F405RG, see `STM32F405RG website`_. +This is the 64-pin variant of the STM32F405x series, +see `STM32F405x reference manual`_. More info about the board available +on `WeAct Github`_. + +.. image:: img/stm32f405_core.jpg + :align: center + :alt: STM32F405 Core Board v1.0 + +Hardware +******** + +The STM32F405RG based Core V1.0 Board provides the following +hardware components: + +- STM32F405RG in QFPN64 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, Adaptive real-time + accelerator (ART Accelerator) allowing 0-wait state execution from Flash memory +- 168 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 1 MB Flash +- 192+4 Kbytes of SRAM including 64-Kbyte of CCM (core coupled memory) +- GPIO with external interrupt capability +- 3x12-bit, 2.4 MSPS ADC up to 24 channels and 7.2 MSPS in triple interleaved mode +- 2x12-bit D/A converters +- 16-stream DMA controller +- Up to 17 Timers (twelve 16-bit, two 32-bit, two watchdog timers and a SysTick timer) +- USART/UART (4) +- I2C (3) +- SPI/I2S (3) +- CAN (2) +- SDIO +- USB 2.0 full-speed device/host/OTG controller with on-chip PHY +- USB 2.0 high-speed/full-speed device/host/OTG controller with on-chip full-speed PHY and ULPI +- 10/100 Ethernet MAC +- CRC calculation unit +- 96-bit unique ID +- RTC with hardware calendar +- 8- to 14-bit parallel camera interface +- LCD parallel interface, 8080/6800 modes + + +Supported Features +================== + +The Zephyr weact_stm32f405_core board configuration supports the following +hardware features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++------------+------------+-------------------------------------+ +| SYSTICK | on-chip | system clock | ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| FLASH | on-chip | flash | ++------------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++------------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++------------+------------+-------------------------------------+ +| USB OTG FS | on-chip | USB device | ++------------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/weact/stm32f405_core/weact_stm32f405_core_defconfig` + +Pin Mapping +=========== + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 +- UART_2 TX/RX : PA2/PA3 +- I2C1 SCL/SDA : PB6/PB7 +- SPI1 SCK/MISO/MOSI : PA5/PA6/PA7 +- CAN1 TX/RX : Pb9/PB8 +- SDMMC1 D0..D4/CLK/CMD : PC8/PC9/PC10/PC11/PC12/PD2 +- USER_PB : PC13 +- USER_LED : PB2 + +Clock Sources +------------- + +The board has two external oscillators. The frequency of the slow clock (LSE) is +32.768 kHz. The frequency of the main clock (HSE) is 8 MHz. + +The default configuration sources the system clock from the PLL, which is +derived from HSE, and is set at 168MHz, which is the maximum possible frequency +to achieve a stable USB clock (48MHz). + +Programming and Debugging +************************* + +There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM +bootloader, and another by using the SWD debug port (which requires additional +hardware). Flashing using the ROM bootloader requires a special activation +pattern, which can be triggered by using the BOOT0 pin. + +Flashing +======== + +Installing dfu-util +------------------- + +It is recommended to use at least v0.8 of `dfu-util`_. The package available in +debian/ubuntu can be quite old, so you might have to build dfu-util from source. + +There is also a Windows version which works, but you may have to install the +right USB drivers with a tool like `Zadig`_. + +Flashing an Application +----------------------- + +Connect a USB-C cable and the board should power ON. Force the board into DFU mode +by keeping the BOOT0 switch pressed while pressing and releasing the NRST switch. + +The dfu-util runner is supported on this board and so a sample can be built and +tested easily. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: weact_stm32f405_core + :goals: build flash + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/button + :board: weact_stm32f405_core + :goals: build flash + +.. zephyr-app-commands:: + :zephyr-app: samples/subsys/fs/fs_sample + :board: weact_stm32f405_core + :goals: build flash + + +Debugging +========= + +The board can be debugged by installing the included 100 mil (0.1 inch) header, +and attaching an SWD debugger to the 3V3 (3.3V), GND, SCK, and DIO +pins on that header. + +References +********** + +.. target-notes:: + +.. _board release notes: + https://github.com/WeActStudio/WeActStudio.STM32F4_64Pin_CoreBoard/blob/master/README.md + +.. _Zadig: + https://zadig.akeo.ie/ + +.. _WeAct Github: + https://github.com/WeActStudio/WeActStudio.STM32F4_64Pin_CoreBoard + +.. _dfu-util: + http://dfu-util.sourceforge.net/build.html + +.. _STM32F405RG website: + https://www.st.com/en/microcontrollers-microprocessors/stm32f405rg.html + +.. _STM32F405x reference manual: + https://www.st.com/resource/en/reference_manual/rm0090-stm32f405415-stm32f407417-stm32f427437-and-stm32f429439-advanced-armbased-32bit-mcus-stmicroelectronics.pdf diff --git a/boards/weact/stm32f405_core/support/openocd.cfg b/boards/weact/stm32f405_core/support/openocd.cfg new file mode 100644 index 00000000000..451853a38bd --- /dev/null +++ b/boards/weact/stm32f405_core/support/openocd.cfg @@ -0,0 +1,18 @@ +source [find interface/stlink.cfg] + +transport select hla_swd + +source [find target/stm32f4x.cfg] + +reset_config srst_only + +$_TARGETNAME configure -event gdb-attach { + echo "Debugger attaching: halting execution" + reset halt + gdb_breakpoint_override hard +} + +$_TARGETNAME configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} diff --git a/boards/weact/stm32f405_core/weact_stm32f405_core.dts b/boards/weact/stm32f405_core/weact_stm32f405_core.dts new file mode 100644 index 00000000000..ba9090bf354 --- /dev/null +++ b/boards/weact/stm32f405_core/weact_stm32f405_core.dts @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2024 Pavlo Yadvychuk + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include + +/ { + model = "WeAct Studio STM32F405 Core Board"; + compatible = "weact,stm32f405-core", "st,stm32f405"; + + chosen { + zephyr,console = &usart1; + zephyr,shell-uart = &usart1; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,ccm = &ccm0; + }; + + leds { + compatible = "gpio-leds"; + led: led { + gpios = <&gpiob 2 GPIO_ACTIVE_HIGH>; + label = "User LED"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button: button { + label = "User"; + gpios = <&gpioc 13 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; + zephyr,code = ; + }; + }; + + aliases { + led0 = &led; + sw0 = &user_button; + watchdog0 = &iwdg; + sdhc0 = &sdmmc1; + }; +}; + +&clk_lsi { + status = "okay"; +}; + +&clk_hse { + clock-frequency = ; + status = "okay"; +}; + +&pll { + div-m = <8>; + mul-n = <336>; + div-p = <2>; + div-q = <7>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <4>; + apb2-prescaler = <2>; +}; + +&usart1 { + pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&usart2 { + pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>; + pinctrl-names = "default"; + status = "okay"; + clock-frequency = ; +}; + +&spi1 { + pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>; + pinctrl-names = "default"; + status = "okay"; +}; + +&can1 { + pinctrl-0 = <&can1_rx_pb8 &can1_tx_pb9>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdmmc1 { + status = "okay"; + pinctrl-0 = <&sdio_d0_pc8 &sdio_d1_pc9 + &sdio_d2_pc10 &sdio_d3_pc11 + &sdio_ck_pc12 &sdio_cmd_pd2>; + pinctrl-names = "default"; + cd-gpios = <&gpioa 8 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; +}; + +&rtc { + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>, + <&rcc STM32_SRC_LSI RTC_SEL(2)>; + status = "okay"; +}; + +zephyr_udc0: &usbotg_fs { + pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; + pinctrl-names = "default"; + status = "okay"; +}; + +&iwdg { + status = "okay"; +}; + +&backup_sram { + status = "okay"; +}; diff --git a/boards/weact/stm32f405_core/weact_stm32f405_core.yaml b/boards/weact/stm32f405_core/weact_stm32f405_core.yaml new file mode 100644 index 00000000000..880770c6913 --- /dev/null +++ b/boards/weact/stm32f405_core/weact_stm32f405_core.yaml @@ -0,0 +1,21 @@ +identifier: weact_stm32f405_core +name: WeAct Studio STM32F405 Core Board +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 128 +flash: 1024 +supported: + - counter + - spi + - i2c + - uart + - usb + - can + - gpio + - watchdog + - backup_sram +vendor: weact diff --git a/boards/weact/stm32f405_core/weact_stm32f405_core_defconfig b/boards/weact/stm32f405_core/weact_stm32f405_core_defconfig new file mode 100644 index 00000000000..51eadcb4809 --- /dev/null +++ b/boards/weact/stm32f405_core/weact_stm32f405_core_defconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_SERIAL=y + +# console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# enable GPIO +CONFIG_GPIO=y diff --git a/boards/weact/stm32g431_core/doc/index.rst b/boards/weact/stm32g431_core/doc/index.rst index 7ebfbd02b29..bf6f80009d5 100644 --- a/boards/weact/stm32g431_core/doc/index.rst +++ b/boards/weact/stm32g431_core/doc/index.rst @@ -81,7 +81,7 @@ Hardware Configuration +---------------+---------+-----------------------------------------------+ | SB6/SB7 | Open | Connect PB4/PB6 (UCPD1_CCx) to USB-C CCx pins | +---------------+---------+-----------------------------------------------+ -| SB3/SB5 | Open | Connect PA9/PA10 (UCPD1_DBCCx) to to PB6/PB4 | +| SB3/SB5 | Open | Connect PA9/PA10 (UCPD1_DBCCx) to PB6/PB4 | +---------------+---------+-----------------------------------------------+ | SB4 | Open | Connect PB2 to VBUS voltage divider | +---------------+---------+-----------------------------------------------+ diff --git a/boards/weact/stm32g431_core/weact_stm32g431_core_defconfig b/boards/weact/stm32g431_core/weact_stm32g431_core_defconfig index 19919b198ca..8c6c0164a54 100644 --- a/boards/weact/stm32g431_core/weact_stm32g431_core_defconfig +++ b/boards/weact/stm32g431_core/weact_stm32g431_core_defconfig @@ -5,7 +5,6 @@ # CONFIG_CLOCK_CONTROL=y -CONFIG_PINCTRL=y CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/wemos/esp32s2_lolin_mini/doc/index.rst b/boards/wemos/esp32s2_lolin_mini/doc/index.rst index 70682657f8a..d09dec2b5f9 100644 --- a/boards/wemos/esp32s2_lolin_mini/doc/index.rst +++ b/boards/wemos/esp32s2_lolin_mini/doc/index.rst @@ -66,7 +66,7 @@ The usual ``flash`` target will work with the ``esp32s2_lolin_mini`` board configuration after putting the board into bootloader mode by holding the '0' button then pressing 'RST' and releasing the 'RST' button. -Here is an example for the :ref:`hello_world` +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: diff --git a/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini.dts b/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini.dts index 53a598ad0de..14d6fd4b1d8 100644 --- a/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini.dts +++ b/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini.dts @@ -46,11 +46,6 @@ }; }; -&cpu0 { - clock-frequency = ; - cpu-power-states = <&deep_sleep &light_sleep>; -}; - &uart0 { status = "okay"; current-speed = <115200>; diff --git a/boards/witte/index.rst b/boards/witte/index.rst new file mode 100644 index 00000000000..c7c0d910782 --- /dev/null +++ b/boards/witte/index.rst @@ -0,0 +1,10 @@ +.. _boards-witte: + +Witte +##### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/witte/linum/Kconfig.defconfig b/boards/witte/linum/Kconfig.defconfig new file mode 100644 index 00000000000..af3bbba6dd4 --- /dev/null +++ b/boards/witte/linum/Kconfig.defconfig @@ -0,0 +1,15 @@ +# STM32H753ZI Linum board configuration + +# Copyright (c) 2024 Felipe Neves +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_LINUM + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_LINUM diff --git a/boards/witte/linum/Kconfig.linum b/boards/witte/linum/Kconfig.linum new file mode 100644 index 00000000000..447e3e71469 --- /dev/null +++ b/boards/witte/linum/Kconfig.linum @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Felipe Neves +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LINUM + select SOC_STM32H753XX diff --git a/boards/witte/linum/board.cmake b/boards/witte/linum/board.cmake new file mode 100644 index 00000000000..8b78b0963a6 --- /dev/null +++ b/boards/witte/linum/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=STM32H753BI" "--speed=4000") +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) diff --git a/boards/witte/linum/board.yml b/boards/witte/linum/board.yml new file mode 100644 index 00000000000..e9ae2c0307d --- /dev/null +++ b/boards/witte/linum/board.yml @@ -0,0 +1,5 @@ +board: + name: linum + vendor: witte + socs: + - name: stm32h753xx diff --git a/boards/witte/linum/doc/img/linum-stm32h753bi-top.jpg b/boards/witte/linum/doc/img/linum-stm32h753bi-top.jpg new file mode 100644 index 00000000000..df465c76513 Binary files /dev/null and b/boards/witte/linum/doc/img/linum-stm32h753bi-top.jpg differ diff --git a/boards/witte/linum/doc/index.rst b/boards/witte/linum/doc/index.rst new file mode 100644 index 00000000000..537807a7979 --- /dev/null +++ b/boards/witte/linum/doc/index.rst @@ -0,0 +1,408 @@ +.. _linum: + +Witte Technology Linum Board +############################ + +Overview +******** +Linum is a development board released by Witte Tenology in 2023, and it was developed around the +STM32H753BI microcontroller. The board has 2 expansion connectors used by the LCD display with +touchscreen and another for access to other peripherals of microcontroller. Also it brings plenty +of communications interfaces like UART with RS232 and RS485 capabillities, CAN bus compatible to +FD standard, and networking over Ethernet. + +.. image:: img/linum-stm32h753bi-top.jpg + :align: center + :alt: Linum development board + +Hardware +******** + +The board features: + - 8 to 52V power supply + - SWD Pins for use as STLink (Pin header) and TC2030-IDC 6-Pin Tag-Connect Plug-of-Nails™ Connector + - Crystal for HS 25MHz + - Crystal for RTC 32.768KHz + - 1 UART serial for debug + - 1 Led RGB + - 1 Buzzer without internal oscillator + - 1 Mono audio up to 3W + - 1 Ethernet 10/100 + - 1 MicroSD connector supporting 1 or 4-bit bus + - 1 USB 2.0 Host/Device + - 1 EEPROM memory with 512K bits + - 1 External SRAM memory with 8MB + - 1 NOR memory with 16MB + - 2 On-board RS232 Transceiver with RTS/CTS + - 2 On-board RS485 Transceiver + - 2 On-board CAN-FD Transceiver + +Expansion connector 1 features: + - 1 Display RBG 888 + - 1 Capacitive Touchscreen sensor + +Expansion connector 2 features. + - 1 SPI + - 1 I2C + - 1 One Wire + - 2 DACs + - 6 PWM Channels + - 10 ADCs + +More information about the board, can be found at the `Witte Linum website`_. + +Supported Features +================== + +The Zephyr Linum board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | counter | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb_device | ++-----------+------------+-------------------------------------+ +| CAN/CANFD | on-chip | canbus | ++-----------+------------+-------------------------------------+ +| LTDC | on-chip | LCD Interface | ++-----------+------------+-------------------------------------+ +| FMC | on-chip | memc (SDRAM) | ++-----------+------------+-------------------------------------+ +| SDMMC | on-chip | disk access | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/witte/linum/linum_defconfig` + + +Default Zephyr Peripheral Mapping: +---------------------------------- + + +BOARD-LEDs +---------- + +The LINUM-STM32H753BI has 3 software controllable LEDs. + + ======= ===== + LED RGB PINS + ======= ===== + LED_R PG2 + LED_G PG3 + LED_B PB2 + ======= ===== + +UART/USART +---------- + +The LINUM-STM32H753BI used the USART1 for serial console. + +USART1 +------ + + ====== ===== + USART1 PINS + ====== ===== + TX PB14 + RX PB15 + ====== ===== + +The LINUM-STM32H753BI board has two on-board RS-232 transceiver connected to USART2 and USART3. + + ====== ===== + USART2 PINS + ====== ===== + TXD PD5 + RXD PD6 + CTS PD3 + RTS PD4 + ====== ===== + + ====== ===== + USART3 PINS + ====== ===== + TXD PB10 + RXD PB11 + CTS PD11 + RTS PD12 + ====== ===== + +The LINUM-STM32H753BI board has two on-board RS-485 transceiver connected to USART4 and USART6. + + ====== ===== + UART4 PINS + ====== ===== + TXD PB9 + RXD PB8 + DE PA15 + ====== ===== + + ====== ===== + USART6 PINS + ====== ===== + TXD PC6 + RXD PC7 + DE PG12 + ====== ===== + +SDMMC +----- + +The LINUM-STM32H753BI has one SDCard slot connected as below: + + ========== ===== + SDMMC1 PINS + ========== ===== + SDMMC_D0 PC8 + SDMMC_D1 PC9 + SDMMC_D2 PC10 + SDMMC_D3 PC11 + SDMMC_DK PC12 + ========== ===== + + =============== ===== + GPIO PINS + =============== ===== + SDCARD_DETECTED PG7 + SDCARD_PWR_EN PD7 + =============== ===== + +ETHERNET +-------- + +The LINUM-STM32H753BI has a ethernet connection using the transceiver KSZ8081RNACA. + + ============ ===== + ETH PINS + ============ ===== + ETH_REF_CLK PA1 + ETH_MDIO PA2 + ETH_CRS_DV PA7 + ETH_MDC PC1 + ETH_RXD0 PC4 + ETH_RXD1 PC5 + ETH_TX_EN PG11 + ETH_TXD0 PG13 + ETH_TXD1 PG14 + ETH_CLK PA8 + ETH_RESET PI4 + ============ ===== + +CAN-FD +------ + +The LINUM-STM32H753BI board has two on-board CAN-FD transceiver connected to FDCAN1 and FDCAN2. + + ====== ===== + FDCAN1 PINS + ====== ===== + TXD PH13 + RXD PH14 + STD PI2 + ====== ===== + + ====== ===== + FDCAN2 PINS + ====== ===== + TXD PB13 + RXD PB12 + STD PE3 + ====== ===== + +USB +--- + +The LINUM-STM32H753BI has one usb port. + + ========= ===== + USB PINS + ========= ===== + USB_VBUS PA9 + USB_N PA11 + USB_P PA12 + USB_EN PI12 + USB_FLT PI13 + ========= ===== + +I2C3 +---- +The LINUM-STM32H753BI connects the EEPROM memory and the touchscreen sensor to I2C3. + + ====== ===== + I2C3 PINS + ====== ===== + SCL PH7 + SDA PH8 + ====== ===== + +External SDRAM +-------------- +The LINUM-STM32H753BI has a external SDRAM with 8Mbytes connected to FMC peripheral. + + =========== ===== + FMC PINS + =========== ===== + FMC_A0 PF0 + FMC_A1 PF1 + FMC_A2 PF2 + FMC_A3 PF3 + FMC_A4 PF4 + FMC_A5 PF5 + FMC_A6 PF12 + FMC_A7 PF13 + FMC_A8 PF14 + FMC_A9 PF15 + FMC_A10 PG0 + FMC_A11 PG1 + FMC_BA0 PG4 + FMC_BA1 PG5 + FMC_D0 PD14 + FMC_D1 PD15 + FMC_D2 PD0 + FMC_D3 PD1 + FMC_D4 PE7 + FMC_D5 PE8 + FMC_D6 PE9 + FMC_D7 PE10 + FMC_D8 PE11 + FMC_D9 PE12 + FMC_D10 PE13 + FMC_D11 PE14 + FMC_D12 PE15 + FMC_D13 PD8 + FMC_D14 PD9 + FMC_D15 PD10 + FMC_NBL0 PE0 + FMC_NBL1 PE1 + FMC_SDCKE0 PC3 + FMC_SDCLK PG8 + FMC_SDNCAS PG15 + FMC_SDNEO PC2 + FMC_SDNRAS PF11 + FMC_SDNWE PC0 + =========== ===== + +LCD +--- +The LINUM-STM32H753BI use the LTDC to support one LCD with RGB connection. + + ============= ===== + LTDC PINS + ============= ===== + LTDC_B0 PJ12 + LTDC_B1 PJ13 + LTDC_B2 PJ14 + LTDC_B3 PJ15 + LTDC_B4 PK3 + LTDC_B5 PK4 + LTDC_B6 PK5 + LTDC_B7 PK6 + LTDC_CLK PI14 + LTDC_DE PK7 + LTDC_G0 PJ7 + LTDC_G1 PJ8 + LTDC_G2 PJ9 + LTDC_G3 PJ10 + LTDC_G4 PJ11 + LTDC_G5 PK0 + LTDC_G6 PK1 + LTDC_G7 PK2 + LTDC_HSYNC PI10 + LTDC_R0 PI15 + LTDC_R1 PJ0 + LTDC_R2 PJ1 + LTDC_R3 PJ2 + LTDC_R4 PJ3 + LTDC_R5 PJ4 + LTDC_R6 PJ5 + LTDC_R7 PJ6 + LTDC_VSYNC PI9 + PWM_BACKLIGHT PH6 + ============= ===== + +System Clock +------------ + +Linum H753ZI System Clock could be driven by an internal or external +oscillator, as well as the main PLL clock. By default, the System clock is +driven by the PLL clock at 480MHz, driven by an 25MHz high-speed external clock. + + +Programming and Debugging +************************* + +Applications for the ``linum`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. note:: + + For debugging or programming Linum you will need to use an external debug + debug or flash tool and connect it to the SWD Connnector. JLink or ST-Link + probes are examples of out of the box compatible tools. + +Flashing +======== + +Flashing an application to the Linum board +------------------------------------------- + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +Run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ minicom -b 115200 -D /dev/ttyACM0 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: linum + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! linum + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: linum + :maybe-skip-config: + :goals: debug + +.. _Witte Linum website: + https://wittetech.com/ diff --git a/boards/witte/linum/linum.dts b/boards/witte/linum/linum.dts new file mode 100644 index 00000000000..d4846f3e1c7 --- /dev/null +++ b/boards/witte/linum/linum.dts @@ -0,0 +1,392 @@ +/* + * Copyright (c) 2024 Felipe Neves + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include + +/ { + model = "Witte Technology STM32H753ZI Linum board"; + compatible = "witte,linum"; + + chosen { + zephyr,console = &usart1; + zephyr,shell-uart = &usart1; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,dtcm = &dtcm; + zephyr,code-partition = &slot0_partition; + zephyr,canbus = &fdcan1; + }; + + sdram1: sdram@c0000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + device_type = "memory"; + reg = <0xc0000000 DT_SIZE_M(8)>; + zephyr,memory-region = "SDRAM1"; + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + }; + + leds: leds { + compatible = "gpio-leds"; + green_led: led_0 { + gpios = <&gpiog 2 GPIO_ACTIVE_LOW>; + label = "User LD1"; + }; + red_led: led_1 { + gpios = <&gpiob 2 GPIO_ACTIVE_LOW>; + label = "User LD2"; + }; + blue_led: led_2 { + gpios = <&gpiog 3 GPIO_ACTIVE_LOW>; + label = "User LD3"; + }; + + }; + + aliases { + led0 = &green_led; + led1 = &blue_led; + }; +}; + +&gpiod { + status = "okay"; + + /* power the SD card */ + mcu-sel-gpios { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&gpioi { + status = "okay"; + /* power the ETH PHY , and FDCAN1 XVCR*/ + mcu-sel-gpios { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>, + <4 GPIO_ACTIVE_HIGH>; + + output-high; + }; +}; + +&gpioe { + status = "okay"; + + /* power FDCAN2 XVCR*/ + mcu-sel-gpios { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>, + <4 GPIO_ACTIVE_HIGH>; + + output-high; + }; +}; + +&clk_lsi { + status = "okay"; +}; + +&clk_hsi48 { + status = "okay"; +}; + +&clk_hse { + /delete-property/ hse-bypass; + clock-frequency = ; + status = "okay"; +}; + +&pll { + div-m = <5>; + mul-n = <192>; + div-p = <2>; + div-q = <4>; + div-r = <4>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&pll2 { + div-m = <2>; + mul-n = <48>; + div-p = <8>; + div-q = <40>; + div-r = <3>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + d1cpre = <1>; + hpre = <2>; + d1ppre = <2>; + d2ppre1 = <2>; + d2ppre2 = <2>; + d3ppre = <2>; +}; + +&usart1 { + pinctrl-0 = <&usart1_tx_pb14 &usart1_rx_pb15>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&usart2 { + pinctrl-0 = <&usart2_tx_pd5 &usart2_rx_pd6>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&usart3 { + pinctrl-0 = <&usart3_tx_pb10 &usart3_rx_pb11>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&uart4 { + pinctrl-0 = <&uart4_tx_pb9 &uart4_rx_pb8>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&usart6 { + pinctrl-0 = <&usart6_tx_pc6 &usart6_rx_pc7>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +zephyr_udc0: &usbotg_fs { + pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rtc { + clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00010000>, + <&rcc STM32_SRC_LSI RTC_SEL(2)>; + status = "okay"; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_scl_ph7 &i2c3_sda_ph8>; + pinctrl-names = "default"; + status = "okay"; + clock-frequency = ; +}; + +&timers12 { + st,prescaler = <10000>; + status = "okay"; + + pwm12: pwm { + status = "okay"; + pinctrl-0 = <&tim12_ch1_pb14>; + pinctrl-names = "default"; + }; +}; + +&adc1 { + pinctrl-0 = <&adc1_inp15_pa3>; + pinctrl-names = "default"; + st,adc-clock-source = ; + st,adc-prescaler = <4>; + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&fdcan1 { + clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>, + <&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>; + pinctrl-0 = <&fdcan1_tx_ph13 &fdcan1_rx_ph14>; + pinctrl-names = "default"; + status = "okay"; +}; + +&fdcan2 { + clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>, + <&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>; + pinctrl-0 = <&fdcan2_rx_pb12 &fdcan2_tx_pb13>; + pinctrl-names = "default"; + status = "okay"; +}; + +&mac { + status = "okay"; + pinctrl-0 = <ð_rxd0_pc4 + ð_rxd1_pc5 + ð_ref_clk_pa1 + ð_crs_dv_pa7 + ð_tx_en_pg11 + ð_txd0_pg13 + ð_txd1_pg14>; + pinctrl-names = "default"; +}; + +&mdio { + status = "okay"; + pinctrl-0 = <ð_mdio_pa2 ð_mdc_pc1>; + pinctrl-names = "default"; + + ethernet-phy@0 { + compatible = "microchip,ksz8081"; + reg = <0x00>; + status = "okay"; + microchip,interface-type = "rmii-25MHz"; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pb5>; + pinctrl-names = "default"; + cs-gpios = <&gpiod 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; +}; + +&fmc { + pinctrl-0 = <&fmc_nbl0_pe0 + &fmc_nbl1_pe1 &fmc_sdclk_pg8 &fmc_sdnwe_pc0 &fmc_sdcke0_pc3_c + &fmc_sdne0_pc2_c &fmc_sdnras_pf11 &fmc_sdncas_pg15 + &fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4 + &fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14 + &fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1 + &fmc_a14_pg4 &fmc_a15_pg5 &fmc_d0_pd14 &fmc_d1_pd15 + &fmc_d2_pd0 &fmc_d3_pd1 &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9 + &fmc_d7_pe10 &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13 + &fmc_d11_pe14 &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9 + &fmc_d15_pd10>; + pinctrl-names = "default"; + status = "okay"; + + sdram { + status = "okay"; + power-up-delay = <100>; + num-auto-refresh = <8>; + mode-register = <0x220>; + refresh-rate = <0x603>; + bank@1 { + reg = <1>; + st,sdram-control = ; + st,sdram-timing = <2 7 4 7 2 2 2>; + }; + }; +}; + +<dc { + pinctrl-0 = <<dc_r0_pi15 <dc_r1_pj0 <dc_r2_pj1 <dc_r3_pj2 + <dc_r4_pj3 <dc_r5_pj4 <dc_r6_pj5 <dc_r7_pj6 + <dc_g0_pj7 <dc_g1_pj8 <dc_g2_pj9 <dc_g3_pj10 + <dc_g4_pj11 <dc_g5_pk0 <dc_g6_pk1 <dc_g7_pk2 + <dc_b0_pj12 <dc_b1_pj13 <dc_b2_pj14 <dc_b3_pj15 + <dc_b4_pk3 <dc_b5_pk4 <dc_b6_pk5 <dc_b7_pk6 + <dc_de_pk7 <dc_clk_pi14 <dc_hsync_pi10 <dc_vsync_pi9>; + pinctrl-names = "default"; + + disp-on-gpios = <&gpiod 7 GPIO_ACTIVE_HIGH>; + + ext-sdram = <&sdram1>; + status = "okay"; + + clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>, + <&rcc STM32_SRC_PLL3_R NO_SEL>; + + width = <480>; + height = <272>; + pixel-format = ; + display-timings { + compatible = "zephyr,panel-timing"; + de-active = <1>; + pixelclk-active = <0>; + hsync-active = <0>; + vsync-active = <0>; + hsync-len = <1>; + vsync-len = <10>; + hback-porch = <43>; + vback-porch = <12>; + hfront-porch = <8>; + vfront-porch = <4>; + }; + def-back-color-red = <0xFF>; + def-back-color-green = <0xFF>; + def-back-color-blue = <0xFF>; +}; + +&sdmmc1 { + pinctrl-0 = <&sdmmc1_d0_pc8 + &sdmmc1_d1_pc9 + &sdmmc1_d2_pc10 + &sdmmc1_d3_pc11 + &sdmmc1_ck_pc12 + &sdmmc1_cmd_pd2>; + pinctrl-names = "default"; + cd-gpios = <&gpiog 7 GPIO_ACTIVE_LOW>; + status = "okay"; + + disk { + status = "okay"; + }; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* 128KB for bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(128)>; + read-only; + }; + + /* storage: 128KB for settings */ + storage_partition: partition@20000 { + label = "storage"; + reg = <0x00020000 DT_SIZE_K(128)>; + }; + + /* application image slot: 256KB */ + slot0_partition: partition@40000 { + label = "image-0"; + reg = <0x00040000 DT_SIZE_K(256)>; + }; + + /* backup slot: 256KB */ + slot1_partition: partition@80000 { + label = "image-1"; + reg = <0x00080000 DT_SIZE_K(256)>; + }; + + /* swap slot: 128KB */ + scratch_partition: partition@c0000 { + label = "image-scratch"; + reg = <0x000c0000 DT_SIZE_K(128)>; + }; + + }; +}; diff --git a/boards/witte/linum/linum.yaml b/boards/witte/linum/linum.yaml new file mode 100644 index 00000000000..3242d570583 --- /dev/null +++ b/boards/witte/linum/linum.yaml @@ -0,0 +1,21 @@ +identifier: linum +name: Linum +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 512 +flash: 2048 +supported: + - uart + - gpio + - counter + - i2c + - pwm + - netif:eth + - spi + - usb_device + - can +vendor: witte diff --git a/boards/witte/linum/linum_defconfig b/boards/witte/linum/linum_defconfig new file mode 100644 index 00000000000..2ccb0d375b5 --- /dev/null +++ b/boards/witte/linum/linum_defconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable UART +CONFIG_SERIAL=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y diff --git a/boards/witte/linum/support/openocd.cfg b/boards/witte/linum/support/openocd.cfg new file mode 100644 index 00000000000..89d4f7ab594 --- /dev/null +++ b/boards/witte/linum/support/openocd.cfg @@ -0,0 +1,21 @@ +source [find board/st_nucleo_h743zi.cfg] + +reset_config srst_only srst_nogate connect_assert_srst + +$_CHIPNAME.cpu0 configure -event gdb-attach { + echo "Debugger attaching: halting execution" + gdb_breakpoint_override hard +} + +$_CHIPNAME.cpu0 configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} + +# Due to the use of connect_assert_srst, running gdb requires +# to reset halt just after openocd init. +rename init old_init +proc init {} { + old_init + reset halt +} diff --git a/boards/wiznet/w5500_evb_pico/doc/index.rst b/boards/wiznet/w5500_evb_pico/doc/index.rst index 63d63370f76..4763f5e5398 100644 --- a/boards/wiznet/w5500_evb_pico/doc/index.rst +++ b/boards/wiznet/w5500_evb_pico/doc/index.rst @@ -165,7 +165,7 @@ Create a file in /etc/udev.rules.d with any name, and write the line below. ATTRS{idVendor}=="2e8a", ATTRS{idProduct}=="000c", MODE="660", GROUP="plugdev", TAG+="uaccess" -This example is valid for the case that the user joins to `plugdev` groups. +This example is valid for the case that the user joins to ``plugdev`` groups. The Raspberry Pi Pico, and thus the W55500 Evaluation Board, has an SWD interface that can be used to program and debug the on board RP2040. This @@ -189,26 +189,26 @@ application. :goals: build flash :gen-args: -DOPENOCD=/usr/local/bin/openocd -DOPENOCD_DEFAULT_PATH=/usr/local/share/openocd/scripts -DRPI_PICO_DEBUG_ADAPTER=picoprobe -Set the environment variables **OPENOCD** to `/usr/local/bin/openocd` and -**OPENOCD_DEFAULT_PATH** to `/usr/local/share/openocd/scripts`. This should +Set the environment variables **OPENOCD** to :file:`/usr/local/bin/openocd` and +**OPENOCD_DEFAULT_PATH** to :file:`/usr/local/share/openocd/scripts`. This should work with the OpenOCD that was installed with the default configuration. This configuration also works with an environment that is set up by the `pico_setup.sh`_ script. **RPI_PICO_DEBUG_ADAPTER** specifies what debug adapter is used for debugging. -If **RPI_PICO_DEBUG_ADAPTER** was not assigned, `picoprobe` is used by default. -The other supported adapters are `raspberrypi-swd`, `jlink` and -`blackmagicprobe`. How to connect `picoprobe` and `raspberrypi-swd` is +If **RPI_PICO_DEBUG_ADAPTER** was not assigned, ``picoprobe`` is used by default. +The other supported adapters are ``raspberrypi-swd``, ``jlink`` and +``blackmagicprobe``. How to connect ``picoprobe`` and ``raspberrypi-swd`` is described in `Getting Started with Raspberry Pi Pico`_. Any other SWD debug adapter maybe also work with this configuration. The value of **RPI_PICO_DEBUG_ADAPTER** is cached, so it can be omitted from -`west flash` and `west debug` if it was previously set while running -`west build`. +``west flash`` and ``west debug`` if it was previously set while running +``west build``. **RPI_PICO_DEBUG_ADAPTER** is used in an argument to OpenOCD as -`"source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]"`. Thus, +``"source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]"``. Thus, **RPI_PICO_DEBUG_ADAPTER** needs to be assigned the file name of the debug adapter. @@ -224,7 +224,7 @@ Using UF2 If you don't have an SWD adapter, you can flash the Raspberry Pi Pico with a UF2 file. By default, building an app for this board will generate a -`build/zephyr/zephyr.uf2` file. If the Pico is powered on with the `BOOTSEL` +:file:`build/zephyr/zephyr.uf2` file. If the Pico is powered on with the ``BOOTSEL`` button pressed, it will appear on the host as a mass storage device. The UF2 file should be drag-and-dropped to the device, which will flash the Pico. @@ -256,8 +256,8 @@ Here is an example for debugging the :zephyr:code-sample:`blinky` application. :gen-args: -DOPENOCD=/usr/local/bin/openocd -DOPENOCD_DEFAULT_PATH=/usr/local/share/openocd/scripts -DRPI_PICO_DEBUG_ADAPTER=raspberrypi-swd As with flashing, you can specify the debug adapter by specifying -**RPI_PICO_DEBUG_ADAPTER** at `west build` time. No needs to specify it at -`west debug` time. +**RPI_PICO_DEBUG_ADAPTER** at ``west build`` time. No needs to specify it at +``west debug`` time. You can also debug with OpenOCD and gdb launching from command-line. Run the following command: diff --git a/boards/xen/xenvm/doc/index.rst b/boards/xen/xenvm/doc/index.rst index 88221b582e7..06e6ab38450 100644 --- a/boards/xen/xenvm/doc/index.rst +++ b/boards/xen/xenvm/doc/index.rst @@ -79,10 +79,12 @@ configuration by altering device tree and Kconfig options. This will be covered in detail in next section. Most of Xen-specific features are not supported at the moment. This includes: + * XenBus (under development) * Xen PV drivers Now only following features are supported: + * Xen Enlighten memory page * Xen event channels * Xen PV console (2 versions: regular ring buffer based for DomU and consoleio for Dom0) diff --git a/cmake/compiler/arcmwdt/compiler_flags.cmake b/cmake/compiler/arcmwdt/compiler_flags.cmake index 5d2be413dc8..6b334c1fe84 100644 --- a/cmake/compiler/arcmwdt/compiler_flags.cmake +++ b/cmake/compiler/arcmwdt/compiler_flags.cmake @@ -116,7 +116,7 @@ set_compiler_property(PROPERTY warning_error_misra_sane -Werror=vla) set_compiler_property(PROPERTY cstd -std=) if (NOT CONFIG_ARCMWDT_LIBC) - set_compiler_property(PROPERTY nostdinc -Hno_default_include -Hnoarcexlib) + set_compiler_property(PROPERTY nostdinc -Hno_default_include -Hnoarcexlib -U__STDC_LIB_EXT1__) set_compiler_property(APPEND PROPERTY nostdinc_include ${NOSTDINC}) endif() @@ -152,14 +152,8 @@ set_property(TARGET compiler-cpp PROPERTY no_rtti "-fno-rtti") # do not link in supplied run-time startup files set_compiler_property(PROPERTY freestanding -Hnocrt) -# Flag to enable debugging -if(CONFIG_THREAD_LOCAL_STORAGE) - # FIXME: Temporary workaround for ARC MWDT toolchain issue - LLDAC linker produce errors on - # debugging information (if -g option specified) of thread-local variables. - set_compiler_property(PROPERTY debug) -else() - set_compiler_property(PROPERTY debug -g) -endif() +# Flag to keep DWARF information (enable debug info) +set_compiler_property(PROPERTY debug -g) # compile common globals like normal definitions set_compiler_property(PROPERTY no_common -fno-common) @@ -180,7 +174,11 @@ set_compiler_property(PROPERTY security_fortify_compile_time) set_compiler_property(PROPERTY security_fortify_run_time) # Required C++ flags when using mwdt -set_property(TARGET compiler-cpp PROPERTY required "-Hcplus" "-Hoff=Stackcheck_alloca") +set_property(TARGET compiler-cpp PROPERTY required "-Hcplus" ) + +if(CONFIG_ARC) + set_property(TARGET compiler-cpp PROPERTY required "-Hoff=Stackcheck_alloca") +endif() # Compiler flag for turning off thread-safe initialization of local statics set_property(TARGET compiler-cpp PROPERTY no_threadsafe_statics "-fno-threadsafe-statics") diff --git a/cmake/compiler/arcmwdt/target.cmake b/cmake/compiler/arcmwdt/target.cmake index 40e313a8ed1..09ec803a29f 100644 --- a/cmake/compiler/arcmwdt/target.cmake +++ b/cmake/compiler/arcmwdt/target.cmake @@ -30,7 +30,11 @@ set(NOSTDINC ${TOOLCHAIN_HOME}/arc/inc) # common compile options, no copyright msg, little-endian, no small data, # no MWDT stack checking -list(APPEND TOOLCHAIN_C_FLAGS -Hnocopyr -HL -Hnosdata -Hoff=Stackcheck_alloca) +list(APPEND TOOLCHAIN_C_FLAGS -Hnocopyr -HL -Hnosdata) + +if(CONFIG_ARC) + list(APPEND TOOLCHAIN_C_FLAGS -Hoff=Stackcheck_alloca) +endif() # The MWDT compiler can replace some code with call to builtin functions. # We can't rely on these functions presence if we don't use MWDT libc. @@ -39,3 +43,9 @@ list(APPEND TOOLCHAIN_C_FLAGS -Hnocopyr -HL -Hnosdata -Hoff=Stackcheck_alloca) if(NOT CONFIG_ARCMWDT_LIBC) list(APPEND TOOLCHAIN_C_FLAGS -fno-builtin) endif() + +# The MWDT compiler requires different macro definitions for ARC and RISC-V +# architectures. __MW_ASM_RV_MACRO__ allows to select appropriate compilation branch. +if(CONFIG_RISCV) + list(APPEND TOOLCHAIN_C_FLAGS -D__MW_ASM_RV_MACRO__) +endif() diff --git a/cmake/compiler/clang/target.cmake b/cmake/compiler/clang/target.cmake index d258cdadcf4..30e5da399af 100644 --- a/cmake/compiler/clang/target.cmake +++ b/cmake/compiler/clang/target.cmake @@ -31,6 +31,8 @@ if(NOT "${ARCH}" STREQUAL "posix") ) include(${ZEPHYR_BASE}/cmake/compiler/clang/target_arm.cmake) + elseif("${ARCH}" STREQUAL "arm64") + include(${ZEPHYR_BASE}/cmake/compiler/clang/target_arm64.cmake) elseif("${ARCH}" STREQUAL "riscv") include(${ZEPHYR_BASE}/cmake/compiler/gcc/target_riscv.cmake) endif() @@ -81,11 +83,3 @@ if(NOT "${ARCH}" STREQUAL "posix") string(REPLACE ";" " " CMAKE_REQUIRED_FLAGS "${CMAKE_REQUIRED_FLAGS}") endif() - -# Load toolchain_cc-family macros - -macro(toolchain_cc_nostdinc) - if(NOT "${ARCH}" STREQUAL "posix") - zephyr_compile_options( -nostdinc) - endif() -endmacro() diff --git a/cmake/compiler/clang/target_arm.cmake b/cmake/compiler/clang/target_arm.cmake index 53a68cfb162..e369694132f 100644 --- a/cmake/compiler/clang/target_arm.cmake +++ b/cmake/compiler/clang/target_arm.cmake @@ -25,6 +25,10 @@ if(CONFIG_FPU) elseif(CONFIG_FP_SOFTABI) list(APPEND ARM_C_FLAGS -mfloat-abi=softfp) endif() +else() + list(APPEND ARM_C_FLAGS -mfpu=none) + # Disable usage of FPU registers + list(APPEND ARM_C_FLAGS -mfloat-abi=soft) endif() if(CONFIG_FP16) diff --git a/cmake/compiler/clang/target_arm64.cmake b/cmake/compiler/clang/target_arm64.cmake new file mode 100644 index 00000000000..44933802d0c --- /dev/null +++ b/cmake/compiler/clang/target_arm64.cmake @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: Apache-2.0 +if(DEFINED GCC_M_CPU) + list(APPEND TOOLCHAIN_C_FLAGS -mcpu=${GCC_M_CPU}) + list(APPEND TOOLCHAIN_LD_FLAGS -mcpu=${GCC_M_CPU}) +endif() + +if(DEFINED GCC_M_ARCH) + list(APPEND TOOLCHAIN_C_FLAGS -march=${GCC_M_ARCH}) + list(APPEND TOOLCHAIN_LD_FLAGS -march=${GCC_M_ARCH}) +endif() + +if(DEFINED GCC_M_TUNE) + list(APPEND TOOLCHAIN_C_FLAGS -mtune=${GCC_M_TUNE}) + list(APPEND TOOLCHAIN_LD_FLAGS -mtune=${GCC_M_TUNE}) +endif() diff --git a/cmake/compiler/compiler_flags_template.cmake b/cmake/compiler/compiler_flags_template.cmake index a18ef39d916..c72e9b70f5d 100644 --- a/cmake/compiler/compiler_flags_template.cmake +++ b/cmake/compiler/compiler_flags_template.cmake @@ -13,6 +13,8 @@ set_compiler_property(PROPERTY optimization_speed) set_compiler_property(PROPERTY optimization_size) +set_compiler_property(PROPERTY optimization_size_aggressive) + ####################################################### # This section covers flags related to warning levels # ####################################################### diff --git a/cmake/compiler/gcc/compiler_flags.cmake b/cmake/compiler/gcc/compiler_flags.cmake index be08cc18bad..e982f75aa78 100644 --- a/cmake/compiler/gcc/compiler_flags.cmake +++ b/cmake/compiler/gcc/compiler_flags.cmake @@ -20,6 +20,7 @@ else() endif() set_compiler_property(PROPERTY optimization_speed -O2) set_compiler_property(PROPERTY optimization_size -Os) +set_compiler_property(PROPERTY optimization_size_aggressive -Oz) if(CMAKE_C_COMPILER_VERSION GREATER_EQUAL "4.5.0") set_compiler_property(PROPERTY optimization_lto -flto) diff --git a/cmake/compiler/gcc/target_arm.cmake b/cmake/compiler/gcc/target_arm.cmake index 78e5fc94550..72b6cc03601 100644 --- a/cmake/compiler/gcc/target_arm.cmake +++ b/cmake/compiler/gcc/target_arm.cmake @@ -10,6 +10,11 @@ endif() list(APPEND ARM_C_FLAGS -mabi=aapcs) +if(CONFIG_BIG_ENDIAN) + list(APPEND TOOLCHAIN_C_FLAGS -mbig-endian) + list(APPEND TOOLCHAIN_LD_FLAGS -mbig-endian) +endif() + if(CONFIG_FPU) list(APPEND ARM_C_FLAGS -mfpu=${GCC_M_FPU}) diff --git a/cmake/compiler/gcc/target_arm64.cmake b/cmake/compiler/gcc/target_arm64.cmake index f5c8c25440b..2674cac50cc 100644 --- a/cmake/compiler/gcc/target_arm64.cmake +++ b/cmake/compiler/gcc/target_arm64.cmake @@ -16,3 +16,21 @@ endif() list(APPEND TOOLCHAIN_C_FLAGS -mabi=lp64) list(APPEND TOOLCHAIN_LD_FLAGS -mabi=lp64) + +set(LLEXT_REMOVE_FLAGS + -fno-pic + -fno-pie + -ffunction-sections + -fdata-sections + -g.* + -Os +) + +list(APPEND LLEXT_EDK_REMOVE_FLAGS + --sysroot=.* + -fmacro-prefix-map=.* +) + +list(APPEND LLEXT_EDK_APPEND_FLAGS + -nodefaultlibs +) diff --git a/cmake/compiler/icx/target.cmake b/cmake/compiler/icx/target.cmake index b72af1600ac..cd389497a5d 100644 --- a/cmake/compiler/icx/target.cmake +++ b/cmake/compiler/icx/target.cmake @@ -63,11 +63,6 @@ endif() set(CMAKE_REQUIRED_FLAGS -nostartfiles -nostdlib ${isystem_include_flags}) string(REPLACE ";" " " CMAKE_REQUIRED_FLAGS "${CMAKE_REQUIRED_FLAGS}") -# Load toolchain_cc-family macros -macro(toolchain_cc_nostdinc) - zephyr_compile_options( -nostdinc) -endmacro() - if(CONFIG_CPP) list(APPEND TOOLCHAIN_C_FLAGS "-no-intel-lib=libirc") endif() diff --git a/cmake/compiler/xt-clang/target.cmake b/cmake/compiler/xt-clang/target.cmake index 33b3be758da..41a72aa782e 100644 --- a/cmake/compiler/xt-clang/target.cmake +++ b/cmake/compiler/xt-clang/target.cmake @@ -1,3 +1,22 @@ # SPDX-License-Identifier: Apache-2.0 include(${ZEPHYR_BASE}/cmake/compiler/xcc/target.cmake) + +# Flags not supported by llext linker +# (regexps are supported and match whole word) +set(LLEXT_REMOVE_FLAGS + -fno-pic + -fno-pie + -ffunction-sections + -fdata-sections + -g.* + -Os + -mcpu=.* +) + +# Flags to be added to llext code compilation +set(LLEXT_APPEND_FLAGS + -fPIC + -nostdlib + -nodefaultlibs +) diff --git a/cmake/emu/armfvp.cmake b/cmake/emu/armfvp.cmake index f5f1cc62a47..70fa5dc0aa3 100644 --- a/cmake/emu/armfvp.cmake +++ b/cmake/emu/armfvp.cmake @@ -1,11 +1,9 @@ # Copyright (c) 2021-2022 Arm Limited (or its affiliates). All rights reserved. # SPDX-License-Identifier: Apache-2.0 -set(armfvp_bin_path $ENV{ARMFVP_BIN_PATH}) - find_program( ARMFVP - PATHS ${armfvp_bin_path} + PATHS ENV ARMFVP_BIN_PATH NO_DEFAULT_PATH NAMES ${ARMFVP_BIN_NAME} ) diff --git a/cmake/emu/qemu.cmake b/cmake/emu/qemu.cmake index 0fd445f3c59..cc47f48d1ff 100644 --- a/cmake/emu/qemu.cmake +++ b/cmake/emu/qemu.cmake @@ -254,9 +254,13 @@ elseif(QEMU_NET_STACK) # NET_TOOLS has been set to the net-tools repo path # net-tools/monitor_15_4 has been built beforehand - set_ifndef(NET_TOOLS ${ZEPHYR_BASE}/../net-tools) # Default if not set + set_ifndef(NET_TOOLS ${ZEPHYR_BASE}/../tools/net-tools) # Default if not set list(APPEND PRE_QEMU_COMMANDS_FOR_server + COMMAND + #Disable Ctrl-C to ensure that users won't accidentally exit + #w/o killing the monitor. + stty intr ^d COMMAND #This command is run in the background using '&'. This prevents #chaining other commands with '&&'. The command is enclosed in '{}' @@ -268,7 +272,11 @@ elseif(QEMU_NET_STACK) /tmp/ip-stack-client > /dev/null & } - # TODO: Support cleanup of the monitor_15_4 process + ) + set(POST_QEMU_COMMANDS_FOR_server + COMMAND + # Kill the monitor_15_4 sub-process + pkill -P $$$$ ) endif() endif(QEMU_PIPE_STACK) @@ -440,6 +448,7 @@ foreach(target ${qemu_targets}) ${MORE_FLAGS_FOR_${target}} ${QEMU_SMP_FLAGS} ${QEMU_KERNEL_OPTION} + ${POST_QEMU_COMMANDS_FOR_${target}} DEPENDS ${logical_target_for_zephyr_elf} WORKING_DIRECTORY ${APPLICATION_BINARY_DIR} COMMENT "${QEMU_PIPE_COMMENT}[QEMU] CPU: ${QEMU_CPU_TYPE_${ARCH}}" diff --git a/cmake/emu/renode.cmake b/cmake/emu/renode.cmake index ab26cfeaf80..fa99da0f8fd 100644 --- a/cmake/emu/renode.cmake +++ b/cmake/emu/renode.cmake @@ -22,40 +22,7 @@ add_custom_target(run_renode COMMAND ${RENODE} ${RENODE_FLAGS} - -e '$$bin=@${APPLICATION_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME}\; include @${RENODE_SCRIPT}\; ${RENODE_OVERLAY} s' - WORKING_DIRECTORY ${APPLICATION_BINARY_DIR} - DEPENDS ${logical_target_for_zephyr_elf} - USES_TERMINAL - ) - -find_program( - RENODE_TEST - renode-test - ) - -set(RENODE_TEST_FLAGS - --variable ELF:@${APPLICATION_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME} - --variable RESC:@${RENODE_SCRIPT} - --variable UART:${RENODE_UART} - --variable KEYWORDS:${ZEPHYR_BASE}/tests/robot/common.robot - --results-dir ${APPLICATION_BINARY_DIR} - ) - -add_custom_target(run_renode_test - COMMAND /bin/sh -c "\ - if [ -z $$ROBOT_FILES ] \;\ - then\ - echo ''\;\ - echo '--- Error: Robot file path is required to run Robot tests in Renode. To provide the path please set the ROBOT_FILES variable.'\;\ - echo '--- To rerun the test with west execute:'\;\ - echo '--- ROBOT_FILES=\\ west build -p -b \\ -s \\ -t run_renode_test'\;\ - echo ''\;\ - exit 1\;\ - fi\;" - COMMAND - ${RENODE_TEST} - ${RENODE_TEST_FLAGS} - ${APPLICATION_SOURCE_DIR}/$$ROBOT_FILES + -e '$$elf=@${PROJECT_BINARY_DIR}/${KERNEL_ELF_NAME}\; include @${RENODE_SCRIPT}\; ${RENODE_OVERLAY} s' WORKING_DIRECTORY ${APPLICATION_BINARY_DIR} DEPENDS ${logical_target_for_zephyr_elf} USES_TERMINAL diff --git a/cmake/emu/simics.cmake b/cmake/emu/simics.cmake new file mode 100644 index 00000000000..dee1305a1f1 --- /dev/null +++ b/cmake/emu/simics.cmake @@ -0,0 +1,30 @@ +# Copyright (c) 2023 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +find_program( + SIMICS + NAMES simics + ) + +zephyr_get(SIMICS_SCRIPT_PATH SYSBUILD GLOBAL) +if(SIMICS_SCRIPT_PATH) + set(SIMICS_SCRIPT ${SIMICS_SCRIPT_PATH}) +else() + set(SIMICS_SCRIPT ${BOARD_DIR}/support/${BOARD}.simics) +endif() + +get_property(SIMICS_ARGS GLOBAL PROPERTY "BOARD_EMU_ARGS_simics") + +add_custom_target(run_simics + COMMAND + ${SIMICS} + -no-gui + -no-win + ${SIMICS_SCRIPT} + ${SIMICS_ARGS} + -e run + WORKING_DIRECTORY ${APPLICATION_BINARY_DIR} + DEPENDS ${logical_target_for_zephyr_elf} + USES_TERMINAL + ) diff --git a/cmake/flash/CMakeLists.txt b/cmake/flash/CMakeLists.txt index 392274891f1..f948b059751 100644 --- a/cmake/flash/CMakeLists.txt +++ b/cmake/flash/CMakeLists.txt @@ -77,8 +77,7 @@ function(runners_yaml_append_config) runners_yaml_append("") endfunction() -# Save runner state in a YAML file, and put that YAML file's location -# in the cache. +# Save runner state in a YAML file. function(create_runners_yaml) set(runners ${ARGV}) @@ -97,6 +96,14 @@ function(create_runners_yaml) runners_yaml_append("\n# Default debug runner if --runner is not given.") runners_yaml_append("debug-runner: ${BOARD_DEBUG_RUNNER}") endif() + if(DEFINED BOARD_SIM_RUNNER) + runners_yaml_append("\n# Default simulation runner if --runner is not given.") + runners_yaml_append("sim-runner: ${BOARD_SIM_RUNNER}") + endif() + if(DEFINED BOARD_ROBOT_RUNNER) + runners_yaml_append("\n# Default test runner if --runner is not given.") + runners_yaml_append("robot-runner: ${BOARD_ROBOT_RUNNER}") + endif() # Sets up common runner configuration values. runners_yaml_append_config() @@ -120,11 +127,9 @@ function(create_runners_yaml) endif() endforeach() - # Write the final contents and set its location in the cache. + # Write the final contents. file(GENERATE OUTPUT "${runners_yaml}" CONTENT $) - set(ZEPHYR_RUNNERS_YAML "${runners_yaml}" CACHE INTERNAL - "a configuration file for the runners Python package") endfunction() get_property(RUNNERS GLOBAL PROPERTY ZEPHYR_RUNNERS) diff --git a/cmake/gcc-m-cpu.cmake b/cmake/gcc-m-cpu.cmake index 8b02d7bee86..8cb777c4769 100644 --- a/cmake/gcc-m-cpu.cmake +++ b/cmake/gcc-m-cpu.cmake @@ -34,6 +34,16 @@ if("${ARCH}" STREQUAL "arm") else() set(GCC_M_CPU cortex-m55+nodsp) endif() + elseif(CONFIG_CPU_CORTEX_M85) + if (CONFIG_ARMV8_1_M_MVEF) + set(GCC_M_CPU cortex-m85) + elseif(CONFIG_ARMV8_1_M_MVEI) + set(GCC_M_CPU cortex-m85+nomve.fp) + elseif(CONFIG_ARMV8_M_DSP) + set(GCC_M_CPU cortex-m85+nomve) + else() + set(GCC_M_CPU cortex-m85+nodsp) + endif() elseif(CONFIG_CPU_CORTEX_R4) if(CONFIG_FPU AND CONFIG_CPU_HAS_VFP) set(GCC_M_CPU cortex-r4f) diff --git a/cmake/gcc-m-fpu.cmake b/cmake/gcc-m-fpu.cmake index 0e231b2ae3b..a25cdf05679 100644 --- a/cmake/gcc-m-fpu.cmake +++ b/cmake/gcc-m-fpu.cmake @@ -39,6 +39,10 @@ if("${ARCH}" STREQUAL "arm") set(FPU_FOR_cortex-m55+nomve.fp auto) set(FPU_FOR_cortex-m55+nomve auto) set(FPU_FOR_cortex-m55+nodsp auto) + set(FPU_FOR_cortex-m85 auto) + set(FPU_FOR_cortex-m85+nomve.fp auto) + set(FPU_FOR_cortex-m85+nomve auto) + set(FPU_FOR_cortex-m85+nodsp auto) set(GCC_M_FPU ${FPU_FOR_${GCC_M_CPU}}) endif() diff --git a/cmake/gen_version_h.cmake b/cmake/gen_version_h.cmake index d7749aa2670..9e1170d9304 100644 --- a/cmake/gen_version_h.cmake +++ b/cmake/gen_version_h.cmake @@ -2,6 +2,11 @@ cmake_minimum_required(VERSION 3.20.0) +set(ZEPHYR_BASE $ENV{ZEPHYR_BASE} CACHE PATH "Zephyr base") +set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${ZEPHYR_BASE}/cmake/modules) + +include(git) + if(VERSION_TYPE STREQUAL KERNEL) set(BUILD_VERSION_NAME BUILD_VERSION) else() @@ -10,23 +15,7 @@ endif() if(NOT DEFINED ${BUILD_VERSION_NAME}) cmake_path(GET VERSION_FILE PARENT_PATH work_dir) - find_package(Git QUIET) - if(GIT_FOUND) - execute_process( - COMMAND ${GIT_EXECUTABLE} describe --abbrev=12 --always - WORKING_DIRECTORY ${work_dir} - OUTPUT_VARIABLE ${BUILD_VERSION_NAME} - OUTPUT_STRIP_TRAILING_WHITESPACE - ERROR_STRIP_TRAILING_WHITESPACE - ERROR_VARIABLE stderr - RESULT_VARIABLE return_code - ) - if(return_code) - message(STATUS "git describe failed: ${stderr}") - elseif(NOT "${stderr}" STREQUAL "") - message(STATUS "git describe warned: ${stderr}") - endif() - endif() + git_describe(${work_dir} ${BUILD_VERSION_NAME}) endif() include(${ZEPHYR_BASE}/cmake/modules/version.cmake) diff --git a/cmake/ide/eclipse_cdt4_generator_amendment.cmake b/cmake/ide/eclipse_cdt4_generator_amendment.cmake index 1bad729118e..36eca028335 100644 --- a/cmake/ide/eclipse_cdt4_generator_amendment.cmake +++ b/cmake/ide/eclipse_cdt4_generator_amendment.cmake @@ -9,7 +9,7 @@ # # Solution: # The amendment function generates a macro header file -# ${CMAKE_BINARY_DIR}/zephyr/include/generated/cmake_intdef.h +# ${CMAKE_BINARY_DIR}/zephyr/include/generated/zephyr/cmake_intdef.h # based on INTERFACE_COMPILE_DEFINITIONS and appends the # defines from the file to # CMAKE_EXTRA_GENERATOR_C_SYSTEM_DEFINED_MACROS. @@ -46,7 +46,7 @@ # CMAKE_EXTRA_GENERATOR_CXX_SYSTEM_DEFINED_MACROS. # #3. The amendment function appends the defines from -# ${CMAKE_BINARY_DIR}/zephyr/include/generated/autoconf.h to +# ${CMAKE_BINARY_DIR}/zephyr/include/generated/zephyr/autoconf.h to # CMAKE_EXTRA_GENERATOR_C_SYSTEM_DEFINED_MACROS. # function(eclipse_cdt4_generator_amendment _param_defs) @@ -88,7 +88,7 @@ else(${_param_defs} EQUAL 1) message(" ${_work_mode}") endif(${_param_defs} EQUAL 1) -set(OUTPUT_FILE ${CMAKE_BINARY_DIR}/zephyr/include/generated/cmake_intdef.h) +set(OUTPUT_FILE ${CMAKE_BINARY_DIR}/zephyr/include/generated/zephyr/cmake_intdef.h) file(WRITE ${OUTPUT_FILE} "/* Generated by eclipse_cd4_generator_amendment.cmake */\n") file(APPEND ${OUTPUT_FILE} "/* The header contains the defines collected from the */\n") file(APPEND ${OUTPUT_FILE} "/* INTERFACE_COMPILE_DEFINITIONS target property */\n") @@ -104,7 +104,7 @@ if (${_work_mode} STREQUAL "C and CXX includes, defines in Eclipse with project message(" -------------------------------------------------------------------------") message(" Add the following two command line parameters:") message("") - message(" -imacros ${CMAKE_BINARY_DIR}/zephyr/include/generated/cmake_intdef.h") + message(" -imacros ${CMAKE_BINARY_DIR}/zephyr/include/generated/zephyr/cmake_intdef.h") message(" -imacros ${AUTOCONF_H}") message("") message(" to 'CDT cross GCC Built-in Compiler Settings' provider command definition") @@ -125,7 +125,7 @@ if ( (${_work_mode} STREQUAL "C and CXX includes, defines in .settings - [EXPERI file(APPEND ${OUTPUT_FILE} "\t\t\t\n") file(APPEND ${OUTPUT_FILE} "\t\t\t\n") if (${_work_mode} STREQUAL "C and CXX includes, defines in .settings with project defines - [EXPERIMENTAL]") - file(APPEND ${OUTPUT_FILE} "\t\t\t\n") + file(APPEND ${OUTPUT_FILE} "\t\t\t\n") else () file(APPEND ${OUTPUT_FILE} "\t\t\t\n") endif () @@ -167,7 +167,7 @@ if ( (${_work_mode} STREQUAL "C and CXX includes, defines in .cproject without _ endif() - file(STRINGS ${CMAKE_BINARY_DIR}/zephyr/include/generated/cmake_intdef.h _int_comp_def) + file(STRINGS ${CMAKE_BINARY_DIR}/zephyr/include/generated/zephyr/cmake_intdef.h _int_comp_def) set (_resultDefines "${CMAKE_EXTRA_GENERATOR_C_SYSTEM_DEFINED_MACROS}") foreach( d ${_int_comp_def} ) string(REGEX MATCH "^#define +([A-Za-z_][A-Za-z0-9_]*) *(.*) *$" _dummy "${d}") diff --git a/cmake/kobj.cmake b/cmake/kobj.cmake index dc693509b11..22fa36ae44a 100644 --- a/cmake/kobj.cmake +++ b/cmake/kobj.cmake @@ -2,9 +2,9 @@ function(gen_kobj gen_dir_out) if (PROJECT_BINARY_DIR) - set(gen_dir ${PROJECT_BINARY_DIR}/include/generated) + set(gen_dir ${PROJECT_BINARY_DIR}/include/generated/zephyr) else () - set(gen_dir ${CMAKE_BINARY_DIR}/include/generated) + set(gen_dir ${CMAKE_BINARY_DIR}/include/generated/zephyr) endif () set(KOBJ_TYPES ${gen_dir}/kobj-types-enum.h) @@ -30,6 +30,7 @@ function(gen_kobj gen_dir_out) ) add_custom_target(${KOBJ_TYPES_H_TARGET} DEPENDS ${KOBJ_TYPES} ${KOBJ_OTYPE}) + cmake_path(GET gen_dir PARENT_PATH gen_dir) set(${gen_dir_out} ${gen_dir} PARENT_SCOPE) endfunction () diff --git a/cmake/linker/arcmwdt/linker_flags.cmake b/cmake/linker/arcmwdt/linker_flags.cmake index 4675e97e14e..63aead6e93b 100644 --- a/cmake/linker/arcmwdt/linker_flags.cmake +++ b/cmake/linker/arcmwdt/linker_flags.cmake @@ -1,4 +1,42 @@ +# Copyright (c) 2024 Nordic Semiconductor +# # SPDX-License-Identifier: Apache-2.0 +set_property(TARGET linker PROPERTY cpp_base -Hcplus) + +check_set_linker_property(TARGET linker PROPERTY baremetal + -Hlld + -Hnosdata + -Xtimer0 # to suppress the warning message + -Hnoxcheck_obj + -Hnocplus + -Hhostlib= + -Hheap=0 + -Hnoivt + -Hnocrt +) + +# There are two options: +# - We have full MWDT libc support and we link MWDT libc - this is default +# behavior and we don't need to do something for that. +# - We use minimal libc provided by Zephyr itself. In that case we must not +# link MWDT libc, but we still need to link libmw +if(CONFIG_MINIMAL_LIBC) + check_set_linker_property(TARGET linker APPEND PROPERTY baremetal + -Hnolib + -Hldopt=-lmw + ) +endif() + +check_set_linker_property(TARGET linker PROPERTY orphan_warning + ${LINKERFLAGPREFIX},--orphan-handling=warn +) + +check_set_linker_property(TARGET linker PROPERTY orphan_error + ${LINKERFLAGPREFIX},--orphan-handling=error +) + # Extra warnings options for twister run set_property(TARGET linker PROPERTY warnings_as_errors -Wl,--fatal-warnings) + +check_set_linker_property(TARGET linker PROPERTY sort_alignment -Wl,--sort-section=alignment) diff --git a/cmake/linker/arcmwdt/target.cmake b/cmake/linker/arcmwdt/target.cmake index f2247ba4540..4eaf824b7c0 100644 --- a/cmake/linker/arcmwdt/target.cmake +++ b/cmake/linker/arcmwdt/target.cmake @@ -4,7 +4,7 @@ set_property(TARGET linker PROPERTY devices_start_symbol "_device_list_start") find_program(CMAKE_LINKER ${CROSS_COMPILE}lldac PATHS ${TOOLCHAIN_HOME} NO_DEFAULT_PATH) # the prefix to transfer linker options from compiler -set_ifndef(LINKERFLAGPREFIX -Wl,) +set_ifndef(LINKERFLAGPREFIX -Wl) # Run $LINKER_SCRIPT file through the C preprocessor, producing ${linker_script_gen} # NOTE: ${linker_script_gen} will be produced at build-time; not at configure-time @@ -30,7 +30,6 @@ macro(configure_linker_script linker_script_gen linker_pass_define) endif() zephyr_get_include_directories_for_lang(C current_includes) - get_property(current_defines GLOBAL PROPERTY PROPERTY_LINKER_SCRIPT_DEFINES) # the command to generate linker file from template add_custom_command( @@ -48,9 +47,9 @@ macro(configure_linker_script linker_script_gen linker_pass_define) -MD -MF ${linker_script_gen}.dep -MT ${linker_script_gen} -D_LINKER -D_ASMLANGUAGE + -D__MWDT_LINKER_CMD__ -imacros ${AUTOCONF_H} ${current_includes} - ${current_defines} ${template_script_defines} ${LINKER_SCRIPT} -E @@ -64,7 +63,7 @@ endmacro() # Force symbols to be entered in the output file as undefined symbols function(toolchain_ld_force_undefined_symbols) foreach(symbol ${ARGN}) - zephyr_link_libraries(${LINKERFLAGPREFIX}-u${symbol}) + zephyr_link_libraries(${LINKERFLAGPREFIX},-u${symbol}) endforeach() endfunction() @@ -91,14 +90,14 @@ function(toolchain_ld_link_elf) target_link_libraries( ${TOOLCHAIN_LD_LINK_ELF_TARGET_ELF} ${TOOLCHAIN_LD_LINK_ELF_LIBRARIES_PRE_SCRIPT} - ${LINKERFLAGPREFIX}-T${TOOLCHAIN_LD_LINK_ELF_LINKER_SCRIPT} + ${LINKERFLAGPREFIX},-T${TOOLCHAIN_LD_LINK_ELF_LINKER_SCRIPT} ${TOOLCHAIN_LD_LINK_ELF_LIBRARIES_POST_SCRIPT} - ${LINKERFLAGPREFIX}--gc-sections - ${LINKERFLAGPREFIX}--entry=__start - ${LINKERFLAGPREFIX}--Map=${TOOLCHAIN_LD_LINK_ELF_OUTPUT_MAP} - ${LINKERFLAGPREFIX}--whole-archive + ${LINKERFLAGPREFIX},--gc-sections + ${LINKERFLAGPREFIX},--entry=__start + ${LINKERFLAGPREFIX},--Map=${TOOLCHAIN_LD_LINK_ELF_OUTPUT_MAP} + ${LINKERFLAGPREFIX},--whole-archive ${WHOLE_ARCHIVE_LIBS} - ${LINKERFLAGPREFIX}--no-whole-archive + ${LINKERFLAGPREFIX},--no-whole-archive ${NO_WHOLE_ARCHIVE_LIBS} $ ${LIB_INCLUDE_DIR} @@ -111,65 +110,10 @@ endfunction(toolchain_ld_link_elf) # linker options of temporary linkage for code generation macro(toolchain_ld_baremetal) - zephyr_ld_options( - -Hlld - -Hnosdata - -Xtimer0 # to suppress the warning message - -Hnoxcheck_obj - -Hnocplus - -Hhostlib= - -Hheap=0 - -Hnoivt - -Hnocrt - ) - - # There are two options: - # - We have full MWDT libc support and we link MWDT libc - this is default - # behavior and we don't need to do something for that. - # - We use minimal libc provided by Zephyr itself. In that case we must not - # link MWDT libc, but we still need to link libmw - if(CONFIG_MINIMAL_LIBC) - zephyr_ld_options( - -Hnolib - -Hldopt=-lmw - ) - endif() - - # Funny thing is if this is set to =error, some architectures will - # skip this flag even though the compiler flag check passes - # (e.g. ARC and Xtensa). So warning should be the default for now. - # - # Skip this for native application as Zephyr only provides - # additions to the host toolchain linker script. The relocation - # sections (.rel*) requires us to override those provided - # by host toolchain. As we can't account for all possible - # combination of compiler and linker on all machines used - # for development, it is better to turn this off. - # - # CONFIG_LINKER_ORPHAN_SECTION_PLACE is to place the orphan sections - # without any warnings or errors, which is the default behavior. - # So there is no need to explicitly set a linker flag. - if(CONFIG_LINKER_ORPHAN_SECTION_WARN) - message(WARNING "MWDT toolchain does not support - CONFIG_LINKER_ORPHAN_SECTION_WARN") - elseif(CONFIG_LINKER_ORPHAN_SECTION_ERROR) - zephyr_ld_options( - ${LINKERFLAGPREFIX}--orphan-handling=error) - endif() endmacro() # base linker options macro(toolchain_ld_base) - if(NOT PROPERTY_LINKER_SCRIPT_DEFINES) - set_property(GLOBAL PROPERTY PROPERTY_LINKER_SCRIPT_DEFINES -D__MWDT_LINKER_CMD__) - endif() - - # Sort the common symbols and each input section by alignment - # in descending order to minimize padding between these symbols. - zephyr_ld_option_ifdef( - CONFIG_LINKER_SORT_BY_ALIGNMENT - ${LINKERFLAGPREFIX}--sort-section=alignment - ) endmacro() # generate linker script snippets from configure files @@ -193,9 +137,6 @@ endmacro() # link C++ libraries macro(toolchain_ld_cpp) - zephyr_link_libraries( - -Hcplus - ) endmacro() # use linker for relocation diff --git a/cmake/linker/armlink/target.cmake b/cmake/linker/armlink/target.cmake index e8511aea244..9aa32ad0e6f 100644 --- a/cmake/linker/armlink/target.cmake +++ b/cmake/linker/armlink/target.cmake @@ -6,18 +6,12 @@ find_program(CMAKE_LINKER ${CROSS_COMPILE}armlink PATHS ${TOOLCHAIN_HOME} NO_DEF add_custom_target(armlink) -macro(toolchain_ld_base) -endmacro() - function(toolchain_ld_force_undefined_symbols) foreach(symbol ${ARGN}) zephyr_link_libraries(--undefined=${symbol}) endforeach() endfunction() -macro(toolchain_ld_baremetal) -endmacro() - macro(configure_linker_script linker_script_gen linker_pass_define) set(STEERING_FILE) set(STEERING_C) @@ -114,6 +108,5 @@ function(toolchain_ld_link_elf) ) endfunction(toolchain_ld_link_elf) -include(${ZEPHYR_BASE}/cmake/linker/ld/target_cpp.cmake) include(${ZEPHYR_BASE}/cmake/linker/ld/target_relocation.cmake) include(${ZEPHYR_BASE}/cmake/linker/ld/target_configure.cmake) diff --git a/cmake/linker/ld/clang/linker_flags.cmake b/cmake/linker/ld/clang/linker_flags.cmake index cc53fab40c0..3155f386a7c 100644 --- a/cmake/linker/ld/clang/linker_flags.cmake +++ b/cmake/linker/ld/clang/linker_flags.cmake @@ -6,4 +6,10 @@ elseif(CONFIG_COVERAGE_NATIVE_SOURCE) endif() # Extra warnings options for twister run -set_property(TARGET linker PROPERTY ld_extra_warning_options -Wl,--fatal-warnings) +set_property(TARGET linker PROPERTY ld_extra_warning_options ${LINKERFLAGPREFIX},--fatal-warnings) + +# GNU ld and LLVM lld complains when used with llvm/clang: +# error: section: init_array is not contiguous with other relro sections +# +# So do not create RELRO program header. +set_property(TARGET linker APPEND PROPERTY cpp_base ${LINKERFLAGPREFIX},-z,norelro) diff --git a/cmake/linker/ld/linker_flags.cmake b/cmake/linker/ld/linker_flags.cmake index 5660b410760..49bba260d3a 100644 --- a/cmake/linker/ld/linker_flags.cmake +++ b/cmake/linker/ld/linker_flags.cmake @@ -1,3 +1,31 @@ +# Copyright (c) 2024 Nordic Semiconductor +# +# SPDX-License-Identifier: Apache-2.0 + +check_set_linker_property(TARGET linker PROPERTY base + ${LINKERFLAGPREFIX},--gc-sections + ${LINKERFLAGPREFIX},--build-id=none +) + +if(NOT CONFIG_MINIMAL_LIBCPP AND NOT CONFIG_NATIVE_LIBRARY AND NOT CONFIG_EXTERNAL_MODULE_LIBCPP) + set_property(TARGET linker PROPERTY cpp_base -lstdc++) +endif() + +check_set_linker_property(TARGET linker PROPERTY baremetal + -nostdlib + -static + ${LINKERFLAGPREFIX},-X + ${LINKERFLAGPREFIX},-N +) + +check_set_linker_property(TARGET linker PROPERTY orphan_warning + ${LINKERFLAGPREFIX},--orphan-handling=warn +) + +check_set_linker_property(TARGET linker PROPERTY orphan_error + ${LINKERFLAGPREFIX},--orphan-handling=error +) + check_set_linker_property(TARGET linker PROPERTY memusage "${LINKERFLAGPREFIX},--print-memory-usage") # -no-pie is not supported until binutils 2.37. @@ -14,6 +42,13 @@ set_property(TARGET linker PROPERTY partial_linking "-r") set_property(TARGET linker PROPERTY lto_arguments -flto -fno-ipa-sra -ffunction-sections -fdata-sections) +check_set_linker_property(TARGET linker PROPERTY no_relax ${LINKERFLAGPREFIX},--no-relax) + +check_set_linker_property(TARGET linker PROPERTY sort_alignment + ${LINKERFLAGPREFIX},--sort-common=descending + ${LINKERFLAGPREFIX},--sort-section=alignment +) + # Some linker flags might not be purely ld specific, but a combination of # linker and compiler, such as: # --coverage for clang diff --git a/cmake/linker/ld/target.cmake b/cmake/linker/ld/target.cmake index 2d60e8ea63d..d45f35de238 100644 --- a/cmake/linker/ld/target.cmake +++ b/cmake/linker/ld/target.cmake @@ -56,7 +56,6 @@ macro(configure_linker_script linker_script_gen linker_pass_define) endif() zephyr_get_include_directories_for_lang(C current_includes) - get_property(current_defines GLOBAL PROPERTY PROPERTY_LINKER_SCRIPT_DEFINES) if(DEFINED SOC_LINKER_SCRIPT) cmake_path(GET SOC_LINKER_SCRIPT PARENT_PATH soc_linker_script_includes) set(soc_linker_script_includes -I${soc_linker_script_includes}) @@ -76,11 +75,12 @@ macro(configure_linker_script linker_script_gen linker_pass_define) -MD -MF ${linker_script_gen}.dep -MT ${linker_script_gen} -D_LINKER -D_ASMLANGUAGE + -D__GCC_LINKER_CMD__ -imacros ${AUTOCONF_H} ${current_includes} ${soc_linker_script_includes} - ${current_defines} ${template_script_defines} + -DUSE_PARTITION_MANAGER=$,$,$> -E ${LINKER_SCRIPT} -P # Prevent generation of debug `#line' directives. -o ${linker_script_gen} @@ -147,8 +147,5 @@ function(toolchain_ld_link_elf) endfunction(toolchain_ld_link_elf) # Load toolchain_ld-family macros -include(${ZEPHYR_BASE}/cmake/linker/${LINKER}/target_base.cmake) -include(${ZEPHYR_BASE}/cmake/linker/${LINKER}/target_baremetal.cmake) -include(${ZEPHYR_BASE}/cmake/linker/${LINKER}/target_cpp.cmake) include(${ZEPHYR_BASE}/cmake/linker/${LINKER}/target_relocation.cmake) include(${ZEPHYR_BASE}/cmake/linker/${LINKER}/target_configure.cmake) diff --git a/cmake/linker/ld/target_baremetal.cmake b/cmake/linker/ld/target_baremetal.cmake deleted file mode 100644 index 76965ed81b2..00000000000 --- a/cmake/linker/ld/target_baremetal.cmake +++ /dev/null @@ -1,39 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# See root CMakeLists.txt for description and expectations of these macros - -macro(toolchain_ld_baremetal) - - # LINKERFLAGPREFIX comes from linker/ld/target.cmake - zephyr_ld_options( - -nostdlib - -static - ${LINKERFLAGPREFIX},-X - ${LINKERFLAGPREFIX},-N - ) - - # Funny thing is if this is set to =error, some architectures will - # skip this flag even though the compiler flag check passes - # (e.g. ARC and Xtensa). So warning should be the default for now. - # - # Skip this for native application as Zephyr only provides - # additions to the host toolchain linker script. The relocation - # sections (.rel*) requires us to override those provided - # by host toolchain. As we can't account for all possible - # combination of compiler and linker on all machines used - # for development, it is better to turn this off. - # - # CONFIG_LINKER_ORPHAN_SECTION_PLACE is to place the orphan sections - # without any warnings or errors, which is the default behavior. - # So there is no need to explicitly set a linker flag. - if(CONFIG_LINKER_ORPHAN_SECTION_WARN) - zephyr_ld_options( - ${LINKERFLAGPREFIX},--orphan-handling=warn - ) - elseif(CONFIG_LINKER_ORPHAN_SECTION_ERROR) - zephyr_ld_options( - ${LINKERFLAGPREFIX},--orphan-handling=error - ) - endif() - -endmacro() diff --git a/cmake/linker/ld/target_base.cmake b/cmake/linker/ld/target_base.cmake deleted file mode 100644 index b92ec877371..00000000000 --- a/cmake/linker/ld/target_base.cmake +++ /dev/null @@ -1,58 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# See root CMakeLists.txt for description and expectations of these macros - -macro(toolchain_ld_base) - - if(NOT PROPERTY_LINKER_SCRIPT_DEFINES) - set_property(GLOBAL PROPERTY PROPERTY_LINKER_SCRIPT_DEFINES -D__GCC_LINKER_CMD__) - endif() - - # TOOLCHAIN_LD_FLAGS comes from compiler/gcc/target.cmake - # LINKERFLAGPREFIX comes from linker/ld/target.cmake - zephyr_ld_options( - ${TOOLCHAIN_LD_FLAGS} - ) - - zephyr_ld_options( - ${LINKERFLAGPREFIX},--gc-sections - ${LINKERFLAGPREFIX},--build-id=none - ) - - # Sort the common symbols and each input section by alignment - # in descending order to minimize padding between these symbols. - zephyr_ld_option_ifdef( - CONFIG_LINKER_SORT_BY_ALIGNMENT - ${LINKERFLAGPREFIX},--sort-common=descending - ${LINKERFLAGPREFIX},--sort-section=alignment - ) - - if (NOT CONFIG_LINKER_USE_RELAX) - zephyr_ld_options( - ${LINKERFLAGPREFIX},--no-relax - ) - endif() - - if (CONFIG_LLVM_USE_LD) - if(CONFIG_LIBGCC_RTLIB) - set(runtime_lib "libgcc") - elseif(CONFIG_COMPILER_RT_RTLIB) - set(runtime_lib "compiler_rt") - endif() - - zephyr_link_libraries( - --config ${ZEPHYR_BASE}/cmake/toolchain/llvm/clang_${runtime_lib}.cfg - ) - endif() - - if(CONFIG_CPP AND (CMAKE_C_COMPILER_ID STREQUAL "Clang")) - # GNU ld complains when used with llvm/clang: - # error: section: init_array is not contiguous with other relro sections - # - # So do not create RELRO program header. - zephyr_link_libraries( - -Wl,-z,norelro - ) - endif() - -endmacro() diff --git a/cmake/linker/ld/target_cpp.cmake b/cmake/linker/ld/target_cpp.cmake deleted file mode 100644 index a6601347172..00000000000 --- a/cmake/linker/ld/target_cpp.cmake +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# See root CMakeLists.txt for description and expectations of these macros - -macro(toolchain_ld_cpp) - - if(NOT CONFIG_EXTERNAL_MODULE_LIBCPP) - zephyr_link_libraries( - -lstdc++ - ) - endif() - -endmacro() diff --git a/cmake/linker/linker_flags_template.cmake b/cmake/linker/linker_flags_template.cmake index 2ef080d6216..870c597be24 100644 --- a/cmake/linker/linker_flags_template.cmake +++ b/cmake/linker/linker_flags_template.cmake @@ -1,3 +1,23 @@ +# Copyright (c) 2024 Nordic Semiconductor +# +# SPDX-License-Identifier: Apache-2.0 + +# Base properties. +# Basic linker properties which should always be applied for a Zephyr build. +set_property(TARGET linker PROPERTY base) + +# Base properties when C++ support is enabled. +# Basic linker properties which should always be applied for a Zephyr build +# using C++. +set_property(TARGET linker PROPERTY cpp_base) + +# Base properties when building Zephyr for an embedded target (baremetal). +set_property(TARGET linker PROPERTY baremetal) + +# Property for controlling linker reporting / handling when placing orphaned sections. +set_property(TARGET linker PROPERTY orphan_warning) +set_property(TARGET linker PROPERTY orphan_error) + # coverage is a property holding the linker flag required for coverage support on the toolchain. # For example, on ld/gcc this would be: -lgcov # Set the property for the corresponding flags of the given toolchain. @@ -20,3 +40,12 @@ set_property(TARGET linker PROPERTY no_position_independent) # Linker flag for doing partial linking # such as, "-r" or "--relocatable" for LD and LLD. set_property(TARGET linker PROPERTY partial_linking) + +# Linker flag for section sorting by alignment +set_property(TARGET linker PROPERTY sort_alignment) + +# Linker flag for disabling relaxation of address optimization for jump calls. +set_property(TARGET linker PROPERTY no_relax) + +# Linker flag for enabling relaxation of address optimization for jump calls. +set_property(TARGET linker PROPERTY relax) diff --git a/cmake/linker/lld/linker_flags.cmake b/cmake/linker/lld/linker_flags.cmake index 8ed5f7a65b9..f6e873ad631 100644 --- a/cmake/linker/lld/linker_flags.cmake +++ b/cmake/linker/lld/linker_flags.cmake @@ -1,11 +1,25 @@ # Copyright (c) 2022 Google LLC # SPDX-License-Identifier: Apache-2.0 -# Since lld is a drop in replacement for ld, we can just use ld's flags -include(${ZEPHYR_BASE}/cmake/linker/ld/${COMPILER}/linker_flags.cmake OPTIONAL) +# Since lld is a drop in replacement for ld, we can just use ld's flags as a base +# and adjust for lld specifics afterwards. +include(${ZEPHYR_BASE}/cmake/linker/ld/linker_flags.cmake OPTIONAL) -check_set_linker_property(TARGET linker PROPERTY memusage "${LINKERFLAGPREFIX},--print-memory-usage") +if(NOT CONFIG_MINIMAL_LIBCPP AND NOT CONFIG_NATIVE_LIBRARY AND NOT CONFIG_EXTERNAL_MODULE_LIBCPP) + set_property(TARGET linker PROPERTY cpp_base -lc++ ${LINKERFLAGPREFIX},-z,norelro) +endif() + +# Force LLVM to use built-in lld linker +if(NOT CONFIG_LLVM_USE_LD) + check_set_linker_property(TARGET linker APPEND PROPERTY baremetal -fuse-ld=lld) +endif() set_property(TARGET linker PROPERTY no_position_independent "${LINKERFLAGPREFIX},--no-pie") -set_property(TARGET linker PROPERTY partial_linking "-r") +set_property(TARGET linker PROPERTY lto_arguments) + +check_set_linker_property(TARGET linker PROPERTY sort_alignment ${LINKERFLAGPREFIX},--sort-section=alignment) + +if(CONFIG_RISCV_GP) + check_set_linker_property(TARGET linker PROPERTY relax ${LINKERFLAGPREFIX},--relax-gp) +endif() diff --git a/cmake/linker/lld/target.cmake b/cmake/linker/lld/target.cmake index 5deab047100..a16529eeef7 100644 --- a/cmake/linker/lld/target.cmake +++ b/cmake/linker/lld/target.cmake @@ -30,7 +30,6 @@ macro(configure_linker_script linker_script_gen linker_pass_define) endif() zephyr_get_include_directories_for_lang(C current_includes) - get_property(current_defines GLOBAL PROPERTY PROPERTY_LINKER_SCRIPT_DEFINES) add_custom_command( OUTPUT ${linker_script_gen} @@ -45,9 +44,9 @@ macro(configure_linker_script linker_script_gen linker_pass_define) -MD -MF ${linker_script_gen}.dep -MT ${linker_script_gen} -D_LINKER -D_ASMLANGUAGE + -D__LLD_LINKER_CMD__ -imacros ${AUTOCONF_H} ${current_includes} - ${current_defines} ${template_script_defines} -E ${LINKER_SCRIPT} -P # Prevent generation of debug `#line' directives. @@ -108,8 +107,5 @@ endfunction(toolchain_ld_link_elf) # Load toolchain_ld-family macros -include(${ZEPHYR_BASE}/cmake/linker/${LINKER}/target_base.cmake) -include(${ZEPHYR_BASE}/cmake/linker/${LINKER}/target_baremetal.cmake) -include(${ZEPHYR_BASE}/cmake/linker/${LINKER}/target_cpp.cmake) include(${ZEPHYR_BASE}/cmake/linker/ld/target_relocation.cmake) include(${ZEPHYR_BASE}/cmake/linker/ld/target_configure.cmake) diff --git a/cmake/linker/lld/target_baremetal.cmake b/cmake/linker/lld/target_baremetal.cmake deleted file mode 100644 index 6faf8f50cac..00000000000 --- a/cmake/linker/lld/target_baremetal.cmake +++ /dev/null @@ -1,46 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# See root CMakeLists.txt for description and expectations of these macros - -macro(toolchain_ld_baremetal) - - # LINKERFLAGPREFIX comes from linker/lld/target.cmake - zephyr_ld_options( - -nostdlib - -static - ${LINKERFLAGPREFIX},-X - ${LINKERFLAGPREFIX},-N - ) - - # Force LLVM to use built-in lld linker - if(NOT CONFIG_LLVM_USE_LD) - zephyr_ld_options( - -fuse-ld=lld - ) - endif() - - # Funny thing is if this is set to =error, some architectures will - # skip this flag even though the compiler flag check passes - # (e.g. ARC and Xtensa). So warning should be the default for now. - # - # Skip this for native application as Zephyr only provides - # additions to the host toolchain linker script. The relocation - # sections (.rel*) requires us to override those provided - # by host toolchain. As we can't account for all possible - # combination of compiler and linker on all machines used - # for development, it is better to turn this off. - # - # CONFIG_LINKER_ORPHAN_SECTION_PLACE is to place the orphan sections - # without any warnings or errors, which is the default behavior. - # So there is no need to explicitly set a linker flag. - if(CONFIG_LINKER_ORPHAN_SECTION_WARN) - zephyr_ld_options( - ${LINKERFLAGPREFIX},--orphan-handling=warn - ) - elseif(CONFIG_LINKER_ORPHAN_SECTION_ERROR) - zephyr_ld_options( - ${LINKERFLAGPREFIX},--orphan-handling=error - ) - endif() - -endmacro() diff --git a/cmake/linker/lld/target_base.cmake b/cmake/linker/lld/target_base.cmake deleted file mode 100644 index 44f43839d37..00000000000 --- a/cmake/linker/lld/target_base.cmake +++ /dev/null @@ -1,61 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# See root CMakeLists.txt for description and expectations of these macros - -macro(toolchain_ld_base) - - if(NOT PROPERTY_LINKER_SCRIPT_DEFINES) - set_property(GLOBAL PROPERTY PROPERTY_LINKER_SCRIPT_DEFINES -D__LLD_LINKER_CMD__) - endif() - - # TOOLCHAIN_LD_FLAGS comes from compiler/clang/target.cmake - # LINKERFLAGPREFIX comes from linker/lld/target.cmake - zephyr_ld_options( - ${TOOLCHAIN_LD_FLAGS} - ) - - zephyr_ld_options( - ${LINKERFLAGPREFIX},--gc-sections - ${LINKERFLAGPREFIX},--build-id=none - ) - - # Sort each input section by alignment. - zephyr_ld_option_ifdef( - CONFIG_LINKER_SORT_BY_ALIGNMENT - ${LINKERFLAGPREFIX},--sort-section=alignment - ) - - if (NOT CONFIG_LINKER_USE_RELAX) - zephyr_ld_options( - ${LINKERFLAGPREFIX},--no-relax - ) - endif() - - # Global pointer relaxation is off by default in lld. Explicitly enable it if - # linker relaxations and gp usage are both allowed. - if (CONFIG_LINKER_USE_RELAX AND CONFIG_RISCV_GP) - zephyr_ld_options( - ${LINKERFLAGPREFIX},--relax-gp - ) - endif() - - if(CONFIG_CPP) - # LLVM lld complains: - # error: section: init_array is not contiguous with other relro sections - # - # So do not create RELRO program header. - zephyr_link_libraries( - -Wl,-z,norelro - ) - endif() - - if(CONFIG_LIBGCC_RTLIB) - set(runtime_lib "libgcc") - elseif(CONFIG_COMPILER_RT_RTLIB) - set(runtime_lib "compiler_rt") - endif() - - zephyr_link_libraries( - --config ${ZEPHYR_BASE}/cmake/toolchain/llvm/clang_${runtime_lib}.cfg - ) -endmacro() diff --git a/cmake/linker/lld/target_cpp.cmake b/cmake/linker/lld/target_cpp.cmake deleted file mode 100644 index 1004c0e6865..00000000000 --- a/cmake/linker/lld/target_cpp.cmake +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# See root CMakeLists.txt for description and expectations of these macros - -macro(toolchain_ld_cpp) - - zephyr_link_libraries( - -lc++ - ) - -endmacro() diff --git a/cmake/linker/xt-ld/linker_flags.cmake b/cmake/linker/xt-ld/linker_flags.cmake new file mode 100644 index 00000000000..af464509b87 --- /dev/null +++ b/cmake/linker/xt-ld/linker_flags.cmake @@ -0,0 +1,36 @@ +# Copyright (c) 2024 Nordic Semiconductor +# +# SPDX-License-Identifier: Apache-2.0 + +check_set_linker_property(TARGET linker PROPERTY base + ${LINKERFLAGPREFIX},--gc-sections + ${LINKERFLAGPREFIX},--build-id=none +) + +if(NOT CONFIG_MINIMAL_LIBCPP AND NOT CONFIG_NATIVE_LIBRARY AND NOT CONFIG_EXTERNAL_MODULE_LIBCPP) + set_property(TARGET linker PROPERTY cpp_base -lstdc++) +endif() + +check_set_linker_property(TARGET linker PROPERTY baremetal + -nostdlib + -static + ${LINKERFLAGPREFIX},-X + ${LINKERFLAGPREFIX},-N +) + +check_set_linker_property(TARGET linker PROPERTY orphan_warning + ${LINKERFLAGPREFIX},--orphan-handling=warn +) + +check_set_linker_property(TARGET linker PROPERTY orphan_error + ${LINKERFLAGPREFIX},--orphan-handling=error +) + +set_property(TARGET linker PROPERTY partial_linking "-r") + +check_set_linker_property(TARGET linker PROPERTY no_relax ${LINKERFLAGPREFIX},--no-relax) + +check_set_linker_property(TARGET linker PROPERTY sort_alignment + ${LINKERFLAGPREFIX},--sort-common=descending + ${LINKERFLAGPREFIX},--sort-section=alignment +) diff --git a/cmake/linker/xt-ld/target.cmake b/cmake/linker/xt-ld/target.cmake index 20209107ff7..4f8e4fcfbdb 100644 --- a/cmake/linker/xt-ld/target.cmake +++ b/cmake/linker/xt-ld/target.cmake @@ -59,7 +59,6 @@ macro(configure_linker_script linker_script_gen linker_pass_define) endif() zephyr_get_include_directories_for_lang(C current_includes) - get_property(current_defines GLOBAL PROPERTY PROPERTY_LINKER_SCRIPT_DEFINES) add_custom_command( OUTPUT ${linker_script_gen} @@ -75,9 +74,9 @@ macro(configure_linker_script linker_script_gen linker_pass_define) -MD -MF ${linker_script_gen}.dep -MT ${linker_script_gen} -D_LINKER -D_ASMLANGUAGE + -D__GCC_LINKER_CMD__ -imacros ${AUTOCONF_H} ${current_includes} - ${current_defines} ${template_script_defines} -E ${LINKER_SCRIPT} -P # Prevent generation of debug `#line' directives. @@ -140,8 +139,5 @@ endfunction(toolchain_ld_link_elf) # xt-ld is Xtensa's own version of binutils' ld. # So we can reuse most of the ld configurations. -include(${ZEPHYR_BASE}/cmake/linker/${LINKER}/target_base.cmake) -include(${ZEPHYR_BASE}/cmake/linker/ld/target_baremetal.cmake) -include(${ZEPHYR_BASE}/cmake/linker/ld/target_cpp.cmake) include(${ZEPHYR_BASE}/cmake/linker/ld/target_relocation.cmake) include(${ZEPHYR_BASE}/cmake/linker/ld/target_configure.cmake) diff --git a/cmake/linker/xt-ld/target_base.cmake b/cmake/linker/xt-ld/target_base.cmake deleted file mode 100644 index c6c1566a920..00000000000 --- a/cmake/linker/xt-ld/target_base.cmake +++ /dev/null @@ -1,36 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# See root CMakeLists.txt for description and expectations of these macros - -macro(toolchain_ld_base) - - if(NOT PROPERTY_LINKER_SCRIPT_DEFINES) - set_property(GLOBAL PROPERTY PROPERTY_LINKER_SCRIPT_DEFINES -D__GCC_LINKER_CMD__) - endif() - - # TOOLCHAIN_LD_FLAGS comes from compiler/gcc/target.cmake - # LINKERFLAGPREFIX comes from linker/xt-ld/target.cmake - zephyr_ld_options( - ${TOOLCHAIN_LD_FLAGS} - ) - - zephyr_ld_options( - ${LINKERFLAGPREFIX},--gc-sections - ${LINKERFLAGPREFIX},--build-id=none - ) - - # Sort the common symbols and each input section by alignment - # in descending order to minimize padding between these symbols. - zephyr_ld_option_ifdef( - CONFIG_LINKER_SORT_BY_ALIGNMENT - ${LINKERFLAGPREFIX},--sort-common=descending - ${LINKERFLAGPREFIX},--sort-section=alignment - ) - - if (NOT CONFIG_LINKER_USE_RELAX) - zephyr_ld_options( - ${LINKERFLAGPREFIX},--no-relax - ) - endif() - -endmacro() diff --git a/cmake/linker_script/common/common-ram.cmake b/cmake/linker_script/common/common-ram.cmake index c5301cc9857..091da6ff541 100644 --- a/cmake/linker_script/common/common-ram.cmake +++ b/cmake/linker_script/common/common-ram.cmake @@ -44,6 +44,7 @@ zephyr_iterable_section(NAME k_sem GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUB zephyr_iterable_section(NAME k_queue GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) zephyr_iterable_section(NAME k_condvar GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) zephyr_iterable_section(NAME k_event GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) +zephyr_iterable_section(NAME k_fifo GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) zephyr_iterable_section(NAME net_buf_pool GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) @@ -54,12 +55,12 @@ if(CONFIG_NETWORKING) zephyr_iterable_section(NAME eth_bridge GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) endif() -if(CONFIG_SENSING) - zephyr_iterable_section(NAME sensing_sensor GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) +if(CONFIG_ARM_SCMI) + zephyr_iterable_section(NAME scmi_protocol GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) endif() -if(CONFIG_UART_MUX) - zephyr_iterable_section(NAME uart_mux GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) +if(CONFIG_SENSING) + zephyr_iterable_section(NAME sensing_sensor GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) endif() if(CONFIG_USB_DEVICE_STACK) @@ -100,8 +101,7 @@ if(CONFIG_ZTEST) endif() if(CONFIG_ZBUS) - zephyr_iterable_section(NAME zbus_observer GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) - zephyr_iterable_section(NAME zbus_channel_observation_mask GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME zbus_channel_observation_mask GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN 1) endif() if(CONFIG_UVB) diff --git a/cmake/linker_script/common/common-rom.cmake b/cmake/linker_script/common/common-rom.cmake index 125d438b58b..2fd4fcedb47 100644 --- a/cmake/linker_script/common/common-rom.cmake +++ b/cmake/linker_script/common/common-rom.cmake @@ -188,6 +188,11 @@ zephyr_iterable_section(NAME tracing_backend KVMA RAM_REGION GROUP RODATA_REGION zephyr_linker_section(NAME zephyr_dbg_info KVMA RAM_REGION GROUP RODATA_REGION NOINPUT ${XIP_ALIGN_WITH_INPUT}) zephyr_linker_section_configure(SECTION zephyr_dbg_info INPUT ".zephyr_dbg_info" KEEP) +if(CONFIG_SYMTAB) + zephyr_linker_section(NAME symtab KVMA FLASH GROUP RODATA_REGION SUBALIGN 4 NOINPUT) + zephyr_linker_section_configure(SECTION symtab INPUT ".gnu.linkonce.symtab*") +endif() + if (CONFIG_DEVICE_DEPS) zephyr_linker_section(NAME device_deps KVMA RAM_REGION GROUP RODATA_REGION NOINPUT ${XIP_ALIGN_WITH_INPUT} ENDALIGN 16) zephyr_linker_section_configure(SECTION device_deps INPUT .__device_deps_pass1* KEEP SORT NAME PASS LINKER_DEVICE_DEPS_PASS1) @@ -205,6 +210,10 @@ if (CONFIG_LOG) zephyr_iterable_section(NAME log_backend KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) endif() +if (CONFIG_MULTI_LEVEL_INTERRUPTS) + zephyr_iterable_section(NAME intc_table KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN 4) +endif() + if (CONFIG_HTTP_SERVER) zephyr_iterable_section(NAME http_service_desc KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) endif() diff --git a/cmake/llext-edk.cmake b/cmake/llext-edk.cmake index 9501133f3ab..e78498c7845 100644 --- a/cmake/llext-edk.cmake +++ b/cmake/llext-edk.cmake @@ -17,9 +17,8 @@ # - INTERFACE_INCLUDE_DIRECTORIES: List of include directories to copy headers # from. It should simply be the INTERFACE_INCLUDE_DIRECTORIES property of the # zephyr_interface target. -# - AUTOCONF_H: Name of the autoconf.h file, used to generate the imacros flag. # - llext_edk_file: Output file name for the tarball. -# - llext_cflags: Additional flags to be added to the generated flags. +# - llext_edk_cflags: Flags to be used for source compile commands. # - ZEPHYR_BASE: Path to the zephyr base directory. # - WEST_TOPDIR: Path to the west top directory. # - APPLICATION_SOURCE_DIR: Path to the application source directory. @@ -31,6 +30,11 @@ cmake_minimum_required(VERSION 3.20.0) +if (CONFIG_LLEXT_EXPORT_BUILTINS_BY_SLID) + message(FATAL_ERROR + "The LLEXT EDK is not compatible with CONFIG_LLEXT_EXPORT_BUILTINS_BY_SLID.") +endif() + set(llext_edk ${PROJECT_BINARY_DIR}/${llext_edk_name}) set(llext_edk_inc ${llext_edk}/include) @@ -89,10 +93,10 @@ string(REGEX REPLACE "[^a-zA-Z0-9]" "_" llext_edk_name_sane ${llext_edk_name}) string(TOUPPER ${llext_edk_name_sane} llext_edk_name_sane) set(install_dir_var "${llext_edk_name_sane}_INSTALL_DIR") -separate_arguments(LLEXT_CFLAGS NATIVE_COMMAND ${llext_cflags}) +separate_arguments(llext_edk_cflags NATIVE_COMMAND ${llext_edk_cflags}) set(make_relative FALSE) -foreach(flag ${llext_cflags}) +foreach(flag ${llext_edk_cflags}) if (flag STREQUAL "-imacros") set(make_relative TRUE) elseif (make_relative) @@ -112,16 +116,12 @@ foreach(flag ${llext_cflags}) list(APPEND new_cflags ${flag}) endif() endforeach() -set(LLEXT_CFLAGS ${new_cflags}) - -cmake_path(CONVERT "${INTERFACE_INCLUDE_DIRECTORIES}" TO_CMAKE_PATH_LIST include_dirs) - -set(autoconf_h_edk ${llext_edk_inc}/${AUTOCONF_H}) -cmake_path(RELATIVE_PATH AUTOCONF_H BASE_DIRECTORY ${PROJECT_BINARY_DIR} OUTPUT_VARIABLE autoconf_h_rel) +set(llext_edk_cflags ${new_cflags}) -list(APPEND base_flags_make ${llext_cflags} ${imacros_make}) -list(APPEND base_flags_cmake ${llext_cflags} ${imacros_cmake}) +list(APPEND base_flags_make ${llext_edk_cflags} ${imacros_make}) +list(APPEND base_flags_cmake ${llext_edk_cflags} ${imacros_cmake}) +separate_arguments(include_dirs NATIVE_COMMAND ${INTERFACE_INCLUDE_DIRECTORIES}) file(MAKE_DIRECTORY ${llext_edk_inc}) foreach(dir ${include_dirs}) if (NOT EXISTS ${dir}) @@ -173,7 +173,7 @@ list(JOIN imacros_gen_make " " imacros_gen_str) file(APPEND ${llext_edk}/Makefile.cflags "\n\nLLEXT_GENERATED_IMACROS_CFLAGS = ${imacros_gen_str}") # Generate flags for CMake -list(APPEND all_flags_cmake ${base_flags_cmake} ${imacros_gen_make} ${all_inc_flags_cmake}) +list(APPEND all_flags_cmake ${base_flags_cmake} ${imacros_gen_cmake} ${all_inc_flags_cmake}) file(WRITE ${llext_edk}/cmake.cflags "set(LLEXT_CFLAGS ${all_flags_cmake})") file(APPEND ${llext_edk}/cmake.cflags "\n\nset(LLEXT_ALL_INCLUDE_CFLAGS ${all_inc_flags_cmake})") diff --git a/cmake/modules/FindDeprecated.cmake b/cmake/modules/FindDeprecated.cmake index bad0ab6ffe7..df0b6a3df51 100644 --- a/cmake/modules/FindDeprecated.cmake +++ b/cmake/modules/FindDeprecated.cmake @@ -99,6 +99,54 @@ if("PYTHON_PREFER" IN_LIST Deprecated_FIND_COMPONENTS) endif() endif() +if("toolchain_ld_base" IN_LIST Deprecated_FIND_COMPONENTS) + # This code was deprecated after Zephyr v4.0.0 + list(REMOVE_ITEM Deprecated_FIND_COMPONENTS toolchain_ld_base) + + if(COMMAND toolchain_ld_base) + message(DEPRECATION + "The macro/function 'toolchain_ld_base' is deprecated. " + "Please use '${LINKER}/linker_flags.cmake' and define the appropriate " + "linker flags as properties instead. " + "See '${ZEPHYR_BASE}/cmake/linker/linker_flags_template.cmake' for " + "known linker properties." + ) + toolchain_ld_base() + endif() +endif() + +if("toolchain_ld_baremetal" IN_LIST Deprecated_FIND_COMPONENTS) + # This code was deprecated after Zephyr v4.0.0 + list(REMOVE_ITEM Deprecated_FIND_COMPONENTS toolchain_ld_baremetal) + + if(COMMAND toolchain_ld_baremetal) + message(DEPRECATION + "The macro/function 'toolchain_ld_baremetal' is deprecated. " + "Please use '${LINKER}/linker_flags.cmake' and define the appropriate " + "linker flags as properties instead. " + "See '${ZEPHYR_BASE}/cmake/linker/linker_flags_template.cmake' for " + "known linker properties." + ) + toolchain_ld_baremetal() + endif() +endif() + +if("toolchain_ld_cpp" IN_LIST Deprecated_FIND_COMPONENTS) + # This code was deprecated after Zephyr v4.0.0 + list(REMOVE_ITEM Deprecated_FIND_COMPONENTS toolchain_ld_cpp) + + if(COMMAND toolchain_ld_cpp) + message(DEPRECATION + "The macro/function 'toolchain_ld_cpp' is deprecated. " + "Please use '${LINKER}/linker_flags.cmake' and define the appropriate " + "linker flags as properties instead. " + "See '${ZEPHYR_BASE}/cmake/linker/linker_flags_template.cmake' for " + "known linker properties." + ) + toolchain_ld_cpp() + endif() +endif() + if(NOT "${Deprecated_FIND_COMPONENTS}" STREQUAL "") message(STATUS "The following deprecated component(s) could not be found: " "${Deprecated_FIND_COMPONENTS}") diff --git a/cmake/modules/FindThreads.cmake b/cmake/modules/FindThreads.cmake index 943aa9eb171..a89ae3d5e0d 100644 --- a/cmake/modules/FindThreads.cmake +++ b/cmake/modules/FindThreads.cmake @@ -26,7 +26,7 @@ include(FindPackageHandleStandardArgs) set(Threads_FOUND FALSE) -if(DEFINED CONFIG_PTHREAD) +if(DEFINED CONFIG_POSIX_THREADS) set(Threads_FOUND TRUE) set(CMAKE_THREAD_LIBS_INIT ) set(CMAKE_USE_PTHREADS_INIT 1) diff --git a/cmake/modules/FindZephyr-sdk.cmake b/cmake/modules/FindZephyr-sdk.cmake index dae75f262d8..b1c1c8cf02b 100644 --- a/cmake/modules/FindZephyr-sdk.cmake +++ b/cmake/modules/FindZephyr-sdk.cmake @@ -4,29 +4,51 @@ # FindZephyr-sdk module for supporting module search mode of Zephyr SDK. # -# Its purpose is to allow the find_package basic signature mode to lookup Zephyr -# SDK and based on user / environment settings of selected toolchain decide if -# the Zephyr SDK CMake package should be loaded. +# It is possible to control the behavior of the Zephyr-SDK package using +# COMPONENTS. +# The Zephyr-SDK package supports the components: +# - LOAD: Load a Zephyr-SDK. This is the default behavior if no COMPONENTS is specified. +# Its purpose is to allow the find_package basic signature mode to lookup Zephyr +# SDK and based on user / environment settings of selected toolchain decide if +# the Zephyr SDK CMake package should be loaded. # -# It extends the Zephyr-sdk CMake package by providing more flexibility in when -# the Zephyr SDK is loaded and loads additional host tools from the Zephyr SDK. +# It extends the Zephyr-sdk CMake package by providing more flexibility in when +# the Zephyr SDK is loaded and loads additional host tools from the Zephyr SDK. # -# The module defines the following variables: +# The module defines the following variables when used in normal search and load mode: +# 'ZEPHYR_SDK_INSTALL_DIR' +# Install location of the Zephyr SDK # -# 'ZEPHYR_SDK_INSTALL_DIR' -# Install location of the Zephyr SDK +# 'ZEPHYR_TOOLCHAIN_VARIANT' +# Zephyr toolchain variant to use if not defined already. # -# 'ZEPHYR_TOOLCHAIN_VARIANT' -# Zephyr toolchain variant to use if not defined already. +# 'Zephyr-sdk_FOUND' +# True if the Zephyr SDK was found. + +# - LIST: Will list all available Zephyr SDKs found in the system but not load +# any Sdk. This can be used to fetch available Zephyr-SDKs before doing +# an actual load. +# LIST component will define the following lists: +# - Zephyr-sdk : Version of a Zephyr-SDK +# - Zephyr-sdk_DIRS : Install dir of the Zephyr-SDK +# Each entry in Zephyr-SDK has a corresponding entry in Zephyr-SDK_DIRS. +# For example: +# index: Zephyr-sdk: Zephyr-sdk_DIRS: +# 0 0.15.0 /opt/zephyr-sdk-0.15.0 +# 1 0.16.0 /home//zephyr-sdk-0.16.0 # -# 'Zephyr-sdk_FOUND' -# True if the Zephyr SDK was found. + +include(extensions) # Set internal variables if set in environment. zephyr_get(ZEPHYR_TOOLCHAIN_VARIANT) zephyr_get(ZEPHYR_SDK_INSTALL_DIR) +if("${Zephyr-sdk_FIND_COMPONENTS}" STREQUAL "") + set(Zephyr-sdk_FIND_COMPONENTS LOAD) +endif() + # Load Zephyr SDK Toolchain. # There are three scenarios where Zephyr SDK should be looked up: # 1) Zephyr specified as toolchain (ZEPHYR_SDK_INSTALL_DIR still used if defined) @@ -38,7 +60,8 @@ if(("zephyr" STREQUAL ${ZEPHYR_TOOLCHAIN_VARIANT}) OR (Zephyr-sdk_FIND_REQUIRED)) # No toolchain was specified, so inform user that we will be searching. - if (NOT DEFINED ZEPHYR_SDK_INSTALL_DIR AND + if (NOT Zephyr-sdk_FIND_QUIETLY AND + NOT DEFINED ZEPHYR_SDK_INSTALL_DIR AND NOT DEFINED ZEPHYR_TOOLCHAIN_VARIANT) message(STATUS "ZEPHYR_TOOLCHAIN_VARIANT not set, trying to locate Zephyr SDK") endif() @@ -49,7 +72,7 @@ if(("zephyr" STREQUAL ${ZEPHYR_TOOLCHAIN_VARIANT}) OR SET(CMAKE_FIND_PACKAGE_SORT_DIRECTION DEC) SET(CMAKE_FIND_PACKAGE_SORT_ORDER NATURAL) - if(DEFINED ZEPHYR_SDK_INSTALL_DIR) + if(DEFINED ZEPHYR_SDK_INSTALL_DIR AND LOAD IN_LIST Zephyr-sdk_FIND_COMPONENTS) # The Zephyr SDK will automatically set the toolchain variant. # To support Zephyr SDK tools (DTC, and other tools) with 3rd party toolchains # then we keep track of current toolchain variant. @@ -77,36 +100,53 @@ if(("zephyr" STREQUAL ${ZEPHYR_TOOLCHAIN_VARIANT}) OR find_package(Zephyr-sdk 0.0.0 EXACT QUIET CONFIG PATHS ${zephyr_sdk_search_paths}) # Remove duplicate entries and sort naturally in descending order. - set(zephyr_sdk_found_versions ${Zephyr-sdk_CONSIDERED_VERSIONS}) - set(zephyr_sdk_found_configs ${Zephyr-sdk_CONSIDERED_CONFIGS}) + foreach(version config IN ZIP_LISTS Zephyr-sdk_CONSIDERED_VERSIONS Zephyr-sdk_CONSIDERED_CONFIGS) + if(NOT DEFINED Zephyr-sdk-${version}_DIR) + set(Zephyr-sdk-${version}_DIR ${config}) + endif() + endforeach() list(REMOVE_DUPLICATES Zephyr-sdk_CONSIDERED_VERSIONS) list(SORT Zephyr-sdk_CONSIDERED_VERSIONS COMPARE NATURAL ORDER DESCENDING) - # Loop over each found Zepher SDK version until one is found that is compatible. - foreach(zephyr_sdk_candidate ${Zephyr-sdk_CONSIDERED_VERSIONS}) - if("${zephyr_sdk_candidate}" VERSION_GREATER_EQUAL "${Zephyr-sdk_FIND_VERSION}") - # Find the path for the current version being checked and get the directory - # of the Zephyr SDK so it can be checked. - list(FIND zephyr_sdk_found_versions ${zephyr_sdk_candidate} zephyr_sdk_current_index) - list(GET zephyr_sdk_found_configs ${zephyr_sdk_current_index} zephyr_sdk_current_check_path) - get_filename_component(zephyr_sdk_current_check_path ${zephyr_sdk_current_check_path} DIRECTORY) - - # Then see if this version is compatible. - find_package(Zephyr-sdk ${Zephyr-sdk_FIND_VERSION} QUIET CONFIG PATHS ${zephyr_sdk_current_check_path} NO_DEFAULT_PATH) - - if (${Zephyr-sdk_FOUND}) - # A compatible version of the Zephyr SDK has been found which is the highest - # supported version, exit. - break() + if(LIST IN_LIST Zephyr-sdk_FIND_COMPONENTS) + set(Zephyr-sdk) + set(Zephyr-sdk_DIRS) + # Only list the Zephyr SDKs installed in the system. + foreach(version ${Zephyr-sdk_CONSIDERED_VERSIONS}) + cmake_path(GET Zephyr-sdk-${version}_DIR PARENT_PATH dir) + cmake_path(GET dir PARENT_PATH dir) + list(APPEND Zephyr-sdk ${version}) + list(APPEND Zephyr-sdk_DIRS ${dir}) + if (NOT Zephyr-sdk_FIND_QUIETLY) + message(STATUS "Zephyr-sdk, version=${version}, dir=${dir}") endif() - endif() - endforeach() + endforeach() + else() + # Loop over each found Zepher SDK version until one is found that is compatible. + foreach(zephyr_sdk_candidate ${Zephyr-sdk_CONSIDERED_VERSIONS}) + if("${zephyr_sdk_candidate}" VERSION_GREATER_EQUAL "${Zephyr-sdk_FIND_VERSION}") + # Find the path for the current version being checked and get the directory + # of the Zephyr SDK so it can be checked. + cmake_path(GET Zephyr-sdk-${zephyr_sdk_candidate}_DIR PARENT_PATH zephyr_sdk_current_check_path) + cmake_path(GET zephyr_sdk_current_check_path PARENT_PATH zephyr_sdk_current_check_path) + + # Then see if this version is compatible. + find_package(Zephyr-sdk ${Zephyr-sdk_FIND_VERSION} QUIET CONFIG PATHS ${zephyr_sdk_current_check_path} NO_DEFAULT_PATH) + + if (${Zephyr-sdk_FOUND}) + # A compatible version of the Zephyr SDK has been found which is the highest + # supported version, exit. + break() + endif() + endif() + endforeach() - if (NOT ${Zephyr-sdk_FOUND}) - # This means no compatible Zephyr SDK versions were found, set the version - # back to the minimum version so that it is displayed in the error text. - find_package(Zephyr-sdk ${Zephyr-sdk_FIND_VERSION} REQUIRED CONFIG PATHS ${zephyr_sdk_search_paths}) + if (NOT ${Zephyr-sdk_FOUND}) + # This means no compatible Zephyr SDK versions were found, set the version + # back to the minimum version so that it is displayed in the error text. + find_package(Zephyr-sdk ${Zephyr-sdk_FIND_VERSION} REQUIRED CONFIG PATHS ${zephyr_sdk_search_paths}) + endif() endif() endif() @@ -121,13 +161,17 @@ set(zephyr_sdk_found_configs) set(zephyr_sdk_current_index) set(zephyr_sdk_current_check_path) -if(DEFINED ZEPHYR_SDK_INSTALL_DIR) - # Cache the Zephyr SDK install dir. - set(ZEPHYR_SDK_INSTALL_DIR ${ZEPHYR_SDK_INSTALL_DIR} CACHE PATH "Zephyr SDK install directory") -endif() +if(LOAD IN_LIST Zephyr-sdk_FIND_COMPONENTS) + if(DEFINED ZEPHYR_SDK_INSTALL_DIR) + # Cache the Zephyr SDK install dir. + set(ZEPHYR_SDK_INSTALL_DIR ${ZEPHYR_SDK_INSTALL_DIR} CACHE PATH "Zephyr SDK install directory") + endif() -if(Zephyr-sdk_FOUND) - include(${ZEPHYR_SDK_INSTALL_DIR}/cmake/zephyr/host-tools.cmake) + if(Zephyr-sdk_FOUND) + include(${ZEPHYR_SDK_INSTALL_DIR}/cmake/zephyr/host-tools.cmake) - message(STATUS "Found host-tools: zephyr ${SDK_VERSION} (${ZEPHYR_SDK_INSTALL_DIR})") + if (NOT Zephyr-sdk_FIND_QUIETLY) + message(STATUS "Found host-tools: zephyr ${SDK_VERSION} (${ZEPHYR_SDK_INSTALL_DIR})") + endif() + endif() endif() diff --git a/cmake/modules/boards.cmake b/cmake/modules/boards.cmake index 4aa65b67cbd..d13e0a16f2d 100644 --- a/cmake/modules/boards.cmake +++ b/cmake/modules/boards.cmake @@ -136,7 +136,7 @@ foreach(root ${BOARD_ROOT}) message(WARNING "BOARD_ROOT element without a 'boards' subdirectory: ${root} Hints: - - if your board directory is '/foo/bar/boards//my_board' then add '/foo/bar' to BOARD_ROOT, not the entire board directory + - if your board directory is '/foo/bar/boards/my_board' then add '/foo/bar' to BOARD_ROOT, not the entire board directory - if in doubt, use absolute paths") endif() endforeach() diff --git a/cmake/modules/configuration_files.cmake b/cmake/modules/configuration_files.cmake index 2bd843a0d8d..84af8c5b635 100644 --- a/cmake/modules/configuration_files.cmake +++ b/cmake/modules/configuration_files.cmake @@ -30,17 +30,10 @@ include(extensions) # Merge in variables from other sources (e.g. sysbuild) zephyr_get(FILE_SUFFIX SYSBUILD GLOBAL) -zephyr_get(APPLICATION_CONFIG_DIR) -if(DEFINED APPLICATION_CONFIG_DIR) - string(CONFIGURE ${APPLICATION_CONFIG_DIR} APPLICATION_CONFIG_DIR) - if(NOT IS_ABSOLUTE ${APPLICATION_CONFIG_DIR}) - get_filename_component(APPLICATION_CONFIG_DIR ${APPLICATION_CONFIG_DIR} ABSOLUTE) - endif() -else() - # Application config dir is not set, so we default to the application - # source directory as configuration directory. - set(APPLICATION_CONFIG_DIR ${APPLICATION_SOURCE_DIR}) -endif() +zephyr_get(APPLICATION_CONFIG_DIR SYSBUILD GLOBAL) +zephyr_file(APPLICATION_ROOT APPLICATION_CONFIG_DIR) +set_ifndef(APPLICATION_CONFIG_DIR ${APPLICATION_SOURCE_DIR}) +string(CONFIGURE ${APPLICATION_CONFIG_DIR} APPLICATION_CONFIG_DIR) zephyr_get(CONF_FILE SYSBUILD LOCAL) if(NOT DEFINED CONF_FILE) @@ -63,7 +56,7 @@ else() endif() endif() -set(APPLICATION_CONFIG_DIR ${APPLICATION_CONFIG_DIR} CACHE INTERNAL "The application configuration folder" FORCE) +set(APPLICATION_CONFIG_DIR ${APPLICATION_CONFIG_DIR} CACHE PATH "The application configuration folder" FORCE) set(CONF_FILE ${CONF_FILE} CACHE STRING "If desired, you can build the application using\ the configuration settings specified in an alternate .conf file using this parameter. \ These settings will override the settings in the application’s .config file or its default .conf file.\ diff --git a/cmake/modules/dts.cmake b/cmake/modules/dts.cmake index b052af0ac90..82c5a302fbc 100644 --- a/cmake/modules/dts.cmake +++ b/cmake/modules/dts.cmake @@ -76,7 +76,7 @@ find_package(Dtc 1.4.6) # - DTC_OVERLAY_FILE: list of devicetree overlay files which will be # used to modify or extend the base devicetree. # - EXTRA_DTC_OVERLAY_FILE: list of extra devicetree overlay files. -# This variable is is similar to DTC_OVERLAY_FILE but the files in +# This variable is similar to DTC_OVERLAY_FILE but the files in # EXTRA_DTC_OVERLAY_FILE will be applied after DTC_OVERLAY_FILE and # thus files specified by EXTRA_DTC_OVERLAY_FILE have higher precedence. # - EXTRA_DTC_FLAGS: list of extra command line options to pass to @@ -293,18 +293,13 @@ ${EXTRA_GEN_DEFINES_ARGS} execute_process( COMMAND ${CMD_GEN_DEFINES} WORKING_DIRECTORY ${PROJECT_BINARY_DIR} - RESULT_VARIABLE ret + COMMAND_ERROR_IS_FATAL ANY ) -if(NOT "${ret}" STREQUAL "0") - message(STATUS "In: ${PROJECT_BINARY_DIR}, command: ${CMD_GEN_DEFINES}") - message(FATAL_ERROR "gen_defines.py failed with return code: ${ret}") -else() - zephyr_file_copy(${ZEPHYR_DTS}.new ${ZEPHYR_DTS} ONLY_IF_DIFFERENT) - zephyr_file_copy(${DEVICETREE_GENERATED_H}.new ${DEVICETREE_GENERATED_H} ONLY_IF_DIFFERENT) - file(REMOVE ${ZEPHYR_DTS}.new ${DEVICETREE_GENERATED_H}.new) - message(STATUS "Generated zephyr.dts: ${ZEPHYR_DTS}") - message(STATUS "Generated devicetree_generated.h: ${DEVICETREE_GENERATED_H}") -endif() +zephyr_file_copy(${ZEPHYR_DTS}.new ${ZEPHYR_DTS} ONLY_IF_DIFFERENT) +zephyr_file_copy(${DEVICETREE_GENERATED_H}.new ${DEVICETREE_GENERATED_H} ONLY_IF_DIFFERENT) +file(REMOVE ${ZEPHYR_DTS}.new ${DEVICETREE_GENERATED_H}.new) +message(STATUS "Generated zephyr.dts: ${ZEPHYR_DTS}") +message(STATUS "Generated devicetree_generated.h: ${DEVICETREE_GENERATED_H}") # # Run GEN_DRIVER_KCONFIG_SCRIPT. @@ -381,9 +376,14 @@ execute_process( OUTPUT_QUIET # Discard stdout WORKING_DIRECTORY ${PROJECT_BINARY_DIR} RESULT_VARIABLE ret + ERROR_VARIABLE stderr ) if(NOT "${ret}" STREQUAL "0") - message(FATAL_ERROR "command failed with return code: ${ret}") + message(FATAL_ERROR "dtc failed with return code: ${ret}") +elseif(stderr) + # dtc printed warnings on stderr but did not fail. + # Display them as CMake warnings to draw attention. + message(WARNING "dtc raised one or more warnings:\n${stderr}") endif() endif(DTC) diff --git a/cmake/modules/extensions.cmake b/cmake/modules/extensions.cmake index cd431147431..b9812d84379 100644 --- a/cmake/modules/extensions.cmake +++ b/cmake/modules/extensions.cmake @@ -113,7 +113,14 @@ endfunction() # https://cmake.org/cmake/help/latest/command/target_link_libraries.html function(zephyr_link_libraries) - target_link_libraries(zephyr_interface INTERFACE ${ARGV}) + if(ARGV0 STREQUAL "PROPERTY") + if(ARGC GREATER 2) + message(FATAL_ERROR "zephyr_link_libraries(PROPERTY ) only allows a single property.") + endif() + target_link_libraries(zephyr_interface INTERFACE $) + else() + target_link_libraries(zephyr_interface INTERFACE ${ARGV}) + endif() endfunction() function(zephyr_libc_link_libraries) @@ -505,7 +512,7 @@ function(zephyr_library_compile_options item) # library and link with it to obtain the flags. # # Linking with a dummy interface library will place flags later on - # the command line than the the flags from zephyr_interface because + # the command line than the flags from zephyr_interface because # zephyr_interface will be the first interface library that flags # are taken from. @@ -705,9 +712,10 @@ endfunction() # This section provides glue between CMake and the Python code that # manages the runners. +set(TYPES "FLASH" "DEBUG" "SIM" "ROBOT") function(_board_check_runner_type type) # private helper - if (NOT (("${type}" STREQUAL "FLASH") OR ("${type}" STREQUAL "DEBUG"))) - message(FATAL_ERROR "invalid type ${type}; should be FLASH or DEBUG") + if (NOT "${type}" IN_LIST TYPES) + message(FATAL_ERROR "invalid type ${type}; should be one of: ${TYPES}") endif() endfunction() @@ -723,8 +731,8 @@ endfunction() # # This would set the board's flash runner to "pyocd". # -# In general, "type" is FLASH or DEBUG, and "runner" is the name of a -# runner. +# In general, "type" is FLASH, DEBUG, SIM or ROBOT and "runner" is +# the name of a runner. function(board_set_runner type runner) _board_check_runner_type(${type}) if (DEFINED BOARD_${type}_RUNNER) @@ -765,6 +773,16 @@ macro(board_set_debugger_ifnset runner) board_set_runner_ifnset(DEBUG ${runner}) endmacro() +# A convenience macro for board_set_runner_ifnset(ROBOT ${runner}). +macro(board_set_robot_runner_ifnset runner) + board_set_runner_ifnset(ROBOT ${runner}) +endmacro() + +# A convenience macro for board_set_runner_ifnset(SIM ${runner}). +macro(board_set_sim_runner_ifnset runner) + board_set_runner_ifnset(SIM ${runner}) +endmacro() + # This function is intended for board.cmake files and application # CMakeLists.txt files. # @@ -842,6 +860,39 @@ function(board_set_rimage_target target) zephyr_check_cache(RIMAGE_TARGET) endfunction() +function(board_emu_args emu) + string(MAKE_C_IDENTIFIER ${emu} emu_id) + # Note the "_EXPLICIT_" here, and see below. + set_property(GLOBAL APPEND PROPERTY BOARD_EMU_ARGS_EXPLICIT_${emu_id} ${ARGN}) +endfunction() + +function(board_finalize_emu_args emu) + # If the application provided a macro to add additional emu + # arguments, handle them. + if(COMMAND app_set_emu_args) + app_set_emu_args() + endif() + + # Retrieve the list of explicitly set arguments. + string(MAKE_C_IDENTIFIER ${emu} emu_id) + get_property(explicit GLOBAL PROPERTY "BOARD_EMU_ARGS_EXPLICIT_${emu_id}") + + # Note no _EXPLICIT_ here. This property contains the final list. + set_property(GLOBAL APPEND PROPERTY BOARD_EMU_ARGS_${emu_id} + # Default arguments from the common emu file come first. + ${ARGN} + # Arguments explicitly given with board_emu_args() come + # next, so they take precedence over the common emu file. + ${explicit} + # Arguments given via the CMake cache come last of all. Users + # can provide variables in this way from the CMake command line. + ${BOARD_EMU_ARGS_${emu_id}} + ) + + # Add the finalized emu to the global property list. + set_property(GLOBAL APPEND PROPERTY ZEPHYR_EMUS ${emu}) +endfunction() + # Zephyr board revision: # # This section provides a function for revision checking. @@ -1171,6 +1222,7 @@ endfunction(zephyr_check_compiler_flag_hardcoded) # ROM_START Inside the first output section of the image. This option is # currently only available on ARM Cortex-M, ARM Cortex-R, # x86, ARC, openisa_rv32m1, and RISC-V. +# ROM_SECTIONS Inside the ROMABLE_REGION GROUP, not initialized. # RAM_SECTIONS Inside the RAMABLE_REGION GROUP, not initialized. # DATA_SECTIONS Inside the RAMABLE_REGION GROUP, initialized. # RAMFUNC_SECTION Inside the RAMFUNC RAMABLE_REGION GROUP, not initialized. @@ -1199,8 +1251,8 @@ endfunction(zephyr_check_compiler_flag_hardcoded) # _mysection_end = .; # _mysection_size = ABSOLUTE(_mysection_end - _mysection_start); # -# When placing into SECTIONS, RAM_SECTIONS or DATA_SECTIONS, the files must -# instead define their own output sections to achieve the same thing: +# When placing into SECTIONS, ROM_SECTIONS, RAM_SECTIONS or DATA_SECTIONS, the +# files must instead define their own output sections to achieve the same thing: # SECTION_PROLOGUE(.mysection,,) # { # _mysection_start = .; @@ -1220,6 +1272,7 @@ function(zephyr_linker_sources location) # the global linker.ld. set(snippet_base "${__build_dir}/include/generated") set(sections_path "${snippet_base}/snippets-sections.ld") + set(rom_sections_path "${snippet_base}/snippets-rom-sections.ld") set(ram_sections_path "${snippet_base}/snippets-ram-sections.ld") set(data_sections_path "${snippet_base}/snippets-data-sections.ld") set(rom_start_path "${snippet_base}/snippets-rom-start.ld") @@ -1239,6 +1292,7 @@ function(zephyr_linker_sources location) get_property(cleared GLOBAL PROPERTY snippet_files_cleared) if (NOT DEFINED cleared) file(WRITE ${sections_path} "") + file(WRITE ${rom_sections_path} "") file(WRITE ${ram_sections_path} "") file(WRITE ${data_sections_path} "") file(WRITE ${rom_start_path} "") @@ -1258,6 +1312,8 @@ function(zephyr_linker_sources location) # Choose destination file, based on the argument. if ("${location}" STREQUAL "SECTIONS") set(snippet_path "${sections_path}") + elseif("${location}" STREQUAL "ROM_SECTIONS") + set(snippet_path "${rom_sections_path}") elseif("${location}" STREQUAL "RAM_SECTIONS") set(snippet_path "${ram_sections_path}") elseif("${location}" STREQUAL "DATA_SECTIONS") @@ -2377,18 +2433,20 @@ function(check_set_linker_property) list(GET LINKER_PROPERTY_PROPERTY 0 property) list(REMOVE_AT LINKER_PROPERTY_PROPERTY 0) - set(option ${LINKER_PROPERTY_PROPERTY}) - string(MAKE_C_IDENTIFIER check${option} check) + foreach(option ${LINKER_PROPERTY_PROPERTY}) + string(MAKE_C_IDENTIFIER check${option} check) - set(SAVED_CMAKE_REQUIRED_FLAGS ${CMAKE_REQUIRED_FLAGS}) - set(CMAKE_REQUIRED_FLAGS "${CMAKE_REQUIRED_FLAGS} ${option}") - zephyr_check_compiler_flag(C "" ${check}) - set(CMAKE_REQUIRED_FLAGS ${SAVED_CMAKE_REQUIRED_FLAGS}) + set(SAVED_CMAKE_REQUIRED_FLAGS ${CMAKE_REQUIRED_FLAGS}) + set(CMAKE_REQUIRED_FLAGS "${CMAKE_REQUIRED_FLAGS} ${option}") + zephyr_check_compiler_flag(C "" ${check}) + set(CMAKE_REQUIRED_FLAGS ${SAVED_CMAKE_REQUIRED_FLAGS}) - if(${${check}}) - set_property(TARGET ${LINKER_PROPERTY_TARGET} ${APPEND} PROPERTY ${property} ${option}) - endif() + if(${${check}}) + set_property(TARGET ${LINKER_PROPERTY_TARGET} ${APPEND} PROPERTY ${property} ${option}) + set(APPEND "APPEND") + endif() + endforeach() endfunction() # 'set_compiler_property' is a function that sets the property for the C and @@ -3581,13 +3639,15 @@ endfunction() # # : Return variable where the node path will be stored # NODELABEL