From 64242d2e967f87f297e515e42f7e22b8a066ea47 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Henrik=20Tj=C3=A4der?= Date: Wed, 29 Sep 2021 16:06:48 +0200 Subject: [PATCH] Clippy fixes and fmt --- hal/src/thumbv7em/clock/v1.rs | 2 +- hal/src/thumbv7em/clock/v2.rs | 10 +++++++++- hal/src/thumbv7em/clock/v2/dfll.rs | 8 ++++---- hal/src/thumbv7em/clock/v2/osculp32k.rs | 1 + hal/src/thumbv7em/clock/v2/pclk.rs | 4 ++-- hal/src/thumbv7em/clock/v2/presets.rs | 10 ++++++---- hal/src/thumbv7em/clock/v2/rtc.rs | 2 +- hal/src/thumbv7em/clock/v2/xosc32k.rs | 11 +++++++---- 8 files changed, 31 insertions(+), 17 deletions(-) diff --git a/hal/src/thumbv7em/clock/v1.rs b/hal/src/thumbv7em/clock/v1.rs index 6aea1170c604..b655bdf6fd66 100644 --- a/hal/src/thumbv7em/clock/v1.rs +++ b/hal/src/thumbv7em/clock/v1.rs @@ -4,10 +4,10 @@ //! The other types in this module are used to enforce at compile time //! that the peripherals have been correctly configured. use crate::clock::v2::pclk::*; -use crate::sercom::v2::*; use crate::pac::gclk::genctrl::SRC_A::*; use crate::pac::gclk::pchctrl::GEN_A::*; use crate::pac::{self, GCLK, MCLK, NVMCTRL, OSC32KCTRL, OSCCTRL}; +use crate::sercom::v2::*; use crate::time::{Hertz, MegaHertz}; pub type ClockGenId = pac::gclk::pchctrl::GEN_A; diff --git a/hal/src/thumbv7em/clock/v2.rs b/hal/src/thumbv7em/clock/v2.rs index c5cd1ca0723a..38e87de09e9b 100644 --- a/hal/src/thumbv7em/clock/v2.rs +++ b/hal/src/thumbv7em/clock/v2.rs @@ -13,7 +13,7 @@ use crate::clock::types::Enabled; use crate::pac::{GCLK, MCLK, NVMCTRL, OSC32KCTRL, OSCCTRL}; use crate::time::Hertz; -use rtc::{Active32k, Active1k}; +use rtc::{Active1k, Active32k}; mod presets; @@ -46,6 +46,14 @@ impl PacClocks { /// This is especially useful when V2 clocking API must interact with /// legacy V1 clocking API based peripherals; E.g. access to [`MCLK`] is /// necessary in most circumstances. + /// + /// # Safety + /// + /// Stealing the PAC resources allows for full control of + /// clocking, something clocking v2 cannot observe or detect. + /// + /// Thus changing clocking "behind the back" of v2 clocking might invalidate + /// typestates representing the current configuration as seen by v2. pub unsafe fn steal(self) -> (OSCCTRL, OSC32KCTRL, GCLK, MCLK) { (self.oscctrl, self.osc32kctrl, self.gclk, self.mclk) } diff --git a/hal/src/thumbv7em/clock/v2/dfll.rs b/hal/src/thumbv7em/clock/v2/dfll.rs index ecdaf4c7714f..714c0ad761b4 100644 --- a/hal/src/thumbv7em/clock/v2/dfll.rs +++ b/hal/src/thumbv7em/clock/v2/dfll.rs @@ -79,23 +79,23 @@ impl DfllToken { #[inline] fn wait_sync_enable(&self) { - while self.dfllsync().read().enable().bit() == true {} + while self.dfllsync().read().enable().bit() {} } #[inline] fn wait_sync_dfllmul(&self) { - while self.dfllsync().read().dfllmul().bit() == true {} + while self.dfllsync().read().dfllmul().bit() {} } #[allow(dead_code)] #[inline] fn wait_sync_dfllval(&self) { - while self.dfllsync().read().dfllval().bit() == true {} + while self.dfllsync().read().dfllval().bit() {} } #[inline] fn wait_sync_dfllctrlb(&self) { - while self.dfllsync().read().dfllctrlb().bit() == true {} + while self.dfllsync().read().dfllctrlb().bit() {} } #[inline] diff --git a/hal/src/thumbv7em/clock/v2/osculp32k.rs b/hal/src/thumbv7em/clock/v2/osculp32k.rs index 2405cd99b2e5..a47dfaf2d827 100644 --- a/hal/src/thumbv7em/clock/v2/osculp32k.rs +++ b/hal/src/thumbv7em/clock/v2/osculp32k.rs @@ -75,6 +75,7 @@ impl OscUlp32kToken { self.osculp32k().modify(|_, w| w.en32k().bit(enabled)); } + #[allow(dead_code)] #[inline] fn wrtlock(&mut self) { self.osculp32k().modify(|_, w| w.wrtlock().bit(true)); diff --git a/hal/src/thumbv7em/clock/v2/pclk.rs b/hal/src/thumbv7em/clock/v2/pclk.rs index 98626fb6ec40..f8c423917a70 100644 --- a/hal/src/thumbv7em/clock/v2/pclk.rs +++ b/hal/src/thumbv7em/clock/v2/pclk.rs @@ -166,8 +166,8 @@ where /// /// It is generic over: /// - a peripheral it is bound to via concept of [`PclkType`] -/// - a clock source ([`PclkSourceMarker`]; variants are provided through [`Gen0`], -/// [`Gen1`], `GenX` types) +/// - a clock source ([`PclkSourceMarker`]; variants are provided through +/// [`Gen0`], [`Gen1`], `GenX` types) pub struct Pclk where P: PclkType, diff --git a/hal/src/thumbv7em/clock/v2/presets.rs b/hal/src/thumbv7em/clock/v2/presets.rs index 30da49f42f09..f26ccc8ed92b 100644 --- a/hal/src/thumbv7em/clock/v2/presets.rs +++ b/hal/src/thumbv7em/clock/v2/presets.rs @@ -5,8 +5,8 @@ /// - [`Dfll`][`super::dfll::Dfll`] (`48 MHz`) /// - [`Gclk5`][`super::gclk::Gclk5`] (`48 MHz / 24 -> 2 MHz`) /// - [`Pclk`][`super::pclk::Pclk`] -/// - [`Dpll0>`][`super::dpll::Dpll0`] (`2 MHz * 60 -> 120 -/// MHz`) +/// - [`Dpll0>`][`super::dpll::Dpll0`] (`2 MHz * 60 -> +/// 120 MHz`) /// - [`Gclk0`][`super::gclk::Gclk0`] (`120 MHz`) /// /// Input arguments for this macro can be retrieved by calling @@ -52,7 +52,8 @@ macro_rules! clocking_preset_gclk0_120mhz_gclk5_2mhz { /// - [`Dfll`][`super::dfll::Dfll`] (`48 MHz`) /// - [`Gclk5`][`super::gclk::Gclk5`] (`48 MHz / 24 -> 2 MHz`) /// - [`Pclk`][`super::pclk::Pclk`] -/// - [`Dpll0>`][`super::dpll::Dpll0`] (`2 MHz * 60 -> 120 MHz`) +/// - [`Dpll0>`][`super::dpll::Dpll0`] (`2 MHz * 60 -> +/// 120 MHz`) /// - [`Gclk0`][`super::gclk::Gclk0`] (`120 MHz`) /// /// with configured external 32k crystal oscillator: @@ -108,7 +109,8 @@ macro_rules! clocking_preset_gclk0_120mhz_gclk5_2mhz_gclk1_external_32khz { /// - [`Dfll`][`super::dfll::Dfll`] (`48 MHz`) /// - [`Gclk5`][`super::gclk::Gclk5`] (`48 MHz / 24 -> 2 MHz`) /// - [`Pclk`][`super::pclk::Pclk`] -/// - [`Dpll0>`][`super::dpll::Dpll0`] (`2 MHz * 60 -> 120 MHz`) +/// - [`Dpll0>`][`super::dpll::Dpll0`] (`2 MHz * 60 -> +/// 120 MHz`) /// - [`Gclk0`][`super::gclk::Gclk0`] (`120 MHz`) /// /// with internal, ultra low power 32k oscillator: diff --git a/hal/src/thumbv7em/clock/v2/rtc.rs b/hal/src/thumbv7em/clock/v2/rtc.rs index 303584f31d45..5d4e46d5a44c 100644 --- a/hal/src/thumbv7em/clock/v2/rtc.rs +++ b/hal/src/thumbv7em/clock/v2/rtc.rs @@ -4,7 +4,7 @@ //! This is a bit of a hack right now. I think it might be best if the RTC //! migrates into the `clock` module, since it's so integrated with OSC32KCTRL. -use crate::clock::types::{Increment, Decrement}; +use crate::clock::types::{Decrement, Increment}; use crate::pac::osc32kctrl::rtcctrl::RTCSEL_A; use crate::pac::OSC32KCTRL; use crate::typelevel::Sealed; diff --git a/hal/src/thumbv7em/clock/v2/xosc32k.rs b/hal/src/thumbv7em/clock/v2/xosc32k.rs index 51f4192ff9b9..3488d0ac7675 100644 --- a/hal/src/thumbv7em/clock/v2/xosc32k.rs +++ b/hal/src/thumbv7em/clock/v2/xosc32k.rs @@ -112,6 +112,7 @@ impl Xosc32kToken { self.xosc32k().modify(|_, w| w.enable().bit(true)); } + #[allow(dead_code)] #[inline] fn wrtlock(&mut self) { self.xosc32k().modify(|_, w| w.wrtlock().bit(true)); @@ -207,7 +208,8 @@ where self } - /// Controls how [`Xosc32k`] behaves when a peripheral clock request is detected + /// Controls how [`Xosc32k`] behaves when a peripheral clock request is + /// detected #[inline] pub fn set_on_demand(mut self, on_demand: bool) -> Self { self.on_demand_mode = on_demand; @@ -265,7 +267,8 @@ where X: Output32k, Y: Output1k, { - /// Deconstruct the [`Xosc32k`] into a Xosc32kToken and the associated GPIO pin + /// Deconstruct the [`Xosc32k`] into a Xosc32kToken and the associated GPIO + /// pin #[inline] pub fn free(self) -> (Xosc32kToken, XIn32) { (self.token, self.xin32) @@ -332,8 +335,8 @@ where X: Output32k, Y: Output1k, { - /// Deconstruct the [`Xosc32k`] into a Xosc32kToken and the two associated GPIO - /// pins + /// Deconstruct the [`Xosc32k`] into a Xosc32kToken and the two associated + /// GPIO pins #[inline] pub fn free(self) -> (Xosc32kToken, XIn32, XOut32) { (self.token, self.xin32, self.mode.xout32)