From 18c84a83e47925ce1ddfb03daf22a15cdf005030 Mon Sep 17 00:00:00 2001 From: Giovanni Bajo Date: Sun, 17 Dec 2023 15:27:57 +0100 Subject: [PATCH] n64: improve PIF HLE emulation by reducing latency (#1351) When doing PIF HLE emulation, we run the HLE state machine just once per frame. This is OK in general, but there can be a few situations where this can cause PIF to miss one command from CPU. For instance, a ROM might send the PIF boot termination command (0x8) and then shortly after issue a SI DMA to identify controllers. If the two happen within the same frame, our HLE emulation would miss the boot termination command. This commit updates the HLE state machine also after each write to PIF RAM. --- ares/n64/pif/io.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/ares/n64/pif/io.cpp b/ares/n64/pif/io.cpp index 44eb1ff76d..0b472a199d 100644 --- a/ares/n64/pif/io.cpp +++ b/ares/n64/pif/io.cpp @@ -23,7 +23,8 @@ auto PIF::readWord(u32 address) -> u32 { auto PIF::writeWord(u32 address, u32 data) -> void { writeInt(address, data); - return intA(Write, Size4); + intA(Write, Size4); + mainHLE(); } auto PIF::dmaRead(u32 address, u32 ramAddress) -> void { @@ -40,4 +41,5 @@ auto PIF::dmaWrite(u32 address, u32 ramAddress) -> void { writeInt(address + offset, data); } intA(Write, Size64); + mainHLE(); }