From e0b0ffb9a58773cefc2664f7f1f44ecf0bf92c7b Mon Sep 17 00:00:00 2001 From: Jan Olencki Date: Wed, 22 Jan 2025 08:56:53 +0100 Subject: [PATCH] [#68174] Improve initialization of the examples --- .../uartlite_sleep_after_1000_iters.patch | 13 ++------ .../scripts/tests/uartlite_wrong_ports.patch | 15 ++++------ .../tests/uartlite_wrong_second_port.patch | 15 ++++------ samples/apb3uart/sim_main.cpp | 30 ++++++++++++++----- samples/cpu_ibex/sim_main.cpp | 23 ++++++++++---- samples/fastvdma/sim_main.cpp | 27 ++++++++++------- samples/fpga_isp/sim_main.cpp | 22 +++++++------- samples/liteuart/sim_main.cpp | 26 ++++++++++++---- samples/ram/sim_main.cpp | 25 +++++++++++----- samples/uartlite/sim_main.cpp | 19 ++++++++---- samples/uartlite_extended/sim_main.cpp | 30 ++++++++++++++----- 11 files changed, 154 insertions(+), 91 deletions(-) diff --git a/.github/scripts/tests/uartlite_sleep_after_1000_iters.patch b/.github/scripts/tests/uartlite_sleep_after_1000_iters.patch index 7731916..615779a 100644 --- a/.github/scripts/tests/uartlite_sleep_after_1000_iters.patch +++ b/.github/scripts/tests/uartlite_sleep_after_1000_iters.patch @@ -1,22 +1,15 @@ diff --git a/src/Plugins/CoSimulationPlugin/IntegrationLibrary/src/renode_bus.cpp b/src/Plugins/CoSimulationPlugin/IntegrationLibrary/src/renode_bus.cpp -index 2e425a734..5519bbce7 100644 --- a/src/Plugins/CoSimulationPlugin/IntegrationLibrary/src/renode_bus.cpp +++ b/src/Plugins/CoSimulationPlugin/IntegrationLibrary/src/renode_bus.cpp -@@ -179,6 +179,7 @@ void RenodeAgent::handleInterrupts(void) - } - } - +@@ -198,8 +198,11 @@ +#include - void RenodeAgent::simulate(int receiverPort, int senderPort, const char* address) + void RenodeAgent::simulate() { - renodeAgent = this; -@@ -188,7 +189,9 @@ void RenodeAgent::simulate(int receiverPort, int senderPort, const char* address Protocol* result; reset(); + int iter = 0; - while(channel->getIsConnected()) { + while(communicationChannel->isConnected()) { + if(++iter > 1000) sleep(600); result = receive(); handleRequest(result); - delete result; diff --git a/.github/scripts/tests/uartlite_wrong_ports.patch b/.github/scripts/tests/uartlite_wrong_ports.patch index dfdf827..1a12534 100644 --- a/.github/scripts/tests/uartlite_wrong_ports.patch +++ b/.github/scripts/tests/uartlite_wrong_ports.patch @@ -1,13 +1,8 @@ diff --git a/samples/uartlite/sim_main.cpp b/samples/uartlite/sim_main.cpp -index f80e5b8..1e42fd3 100644 --- a/samples/uartlite/sim_main.cpp +++ b/samples/uartlite/sim_main.cpp -@@ -84,7 +84,7 @@ int main(int argc, char **argv, char **env) { - tfp->open("simx.vcd"); - #endif - RenodeAgent *uart = Init(); -- uart->simulate(atoi(argv[1]), atoi(argv[2]), address); -+ uart->simulate(atoi(argv[1]) + 5, atoi(argv[2]) + 5, address); - top->final(); - exit(0); - } +@@ -95,3 +95,3 @@ int main(int argc, char **argv, char **env) { + RenodeAgent *uart = initAgent(); +- uart->connect(atoi(argv[1]), atoi(argv[2]), address); ++ uart->connect(atoi(argv[1]) + 5, atoi(argv[2]) + 5, address); + uart->simulate(); diff --git a/.github/scripts/tests/uartlite_wrong_second_port.patch b/.github/scripts/tests/uartlite_wrong_second_port.patch index afc8933..2b053b3 100644 --- a/.github/scripts/tests/uartlite_wrong_second_port.patch +++ b/.github/scripts/tests/uartlite_wrong_second_port.patch @@ -1,13 +1,8 @@ diff --git a/samples/uartlite/sim_main.cpp b/samples/uartlite/sim_main.cpp -index f80e5b8..f07a0ff 100644 --- a/samples/uartlite/sim_main.cpp +++ b/samples/uartlite/sim_main.cpp -@@ -84,7 +84,7 @@ int main(int argc, char **argv, char **env) { - tfp->open("simx.vcd"); - #endif - RenodeAgent *uart = Init(); -- uart->simulate(atoi(argv[1]), atoi(argv[2]), address); -+ uart->simulate(atoi(argv[1]), atoi(argv[2]) + 5, address); - top->final(); - exit(0); - } +@@ -95,3 +95,3 @@ int main(int argc, char **argv, char **env) { + RenodeAgent *uart = initAgent(); +- uart->connect(atoi(argv[1]), atoi(argv[2]), address); ++ uart->connect(atoi(argv[1]), atoi(argv[2]) + 5, address); + uart->simulate(); diff --git a/samples/apb3uart/sim_main.cpp b/samples/apb3uart/sim_main.cpp index 9fa0d40..6421463 100644 --- a/samples/apb3uart/sim_main.cpp +++ b/samples/apb3uart/sim_main.cpp @@ -1,5 +1,5 @@ // -// Copyright (c) 2010-2021 Antmicro +// Copyright (c) 2010-2025 Antmicro // // This file is licensed under the MIT License. // Full license text is available in 'LICENSE' file. @@ -34,15 +34,22 @@ void eval() { uart->eval(); } -RenodeAgent *Init() { +UART *initAgent() { // These need static lifetime because we assign them to global pointers. // By having the initialization here we guarantee that any static initialization // from other compilation units (e. g. Verilator) is already done. static VerilatedContext context; static VApb3UartCtrl uart_ctrl_obj(&context); - uart_ctrl = &uart_ctrl_obj; + const int murax_rxtx_reg = 0x0; + static UART uart_obj = UART(&uart_ctrl->io_uart_txd, &uart_ctrl->io_uart_rxd, prescaler, murax_rxtx_reg, &uart_ctrl->io_interrupt); + + return &uart_obj; +} + +void initBus(RenodeAgent *agent) +{ APB3* bus = new APB3(); //================================================= @@ -66,9 +73,13 @@ RenodeAgent *Init() { //================================================= // Init peripheral //================================================= - const int murax_rxtx_reg = 0x0; - static UART uart_obj = UART(bus, &uart_ctrl->io_uart_txd, &uart_ctrl->io_uart_rxd, prescaler, murax_rxtx_reg, &uart_ctrl->io_interrupt); - uart = &uart_obj; + agent->addBus(bus); +} + +RenodeAgent *Init() { + uart = initAgent(); + uart->connectNative(); + initBus(uart); return uart; } @@ -79,7 +90,6 @@ int main(int argc, char **argv, char **env) { } const char *address = argc < 4 ? "127.0.0.1" : argv[3]; - Init(); Verilated::commandArgs(argc, argv); #if VM_TRACE Verilated::traceEverOn(true); @@ -87,7 +97,11 @@ int main(int argc, char **argv, char **env) { uart_ctrl->trace(tfp, 99); tfp->open("simx.fst"); #endif - uart->simulate(atoi(argv[1]), atoi(argv[2]), address); + + uart = initAgent(); + uart->connect(atoi(argv[1]), atoi(argv[2]), address); + initBus(uart); + uart->simulate(); uart_ctrl->final(); #if VM_TRACE diff --git a/samples/cpu_ibex/sim_main.cpp b/samples/cpu_ibex/sim_main.cpp index 597bd7a..b5b368d 100644 --- a/samples/cpu_ibex/sim_main.cpp +++ b/samples/cpu_ibex/sim_main.cpp @@ -24,26 +24,35 @@ void evaluateModel() ibex->evaluateModel(); } -RenodeAgent *Init() +CpuAgent *initAgent() { Verilated::commandArgs(0, (const char **)nullptr); + CpuAgent* agent = new CpuAgent(); + return agent; +} +void initBus(CpuAgent *agent) +{ WishboneInitiator *instructionFetchBus = new WishboneInitiator(); WishboneInitiator *loadStoreBus = new WishboneInitiator(); - agent = new CpuAgent(instructionFetchBus); - agent->addBus(loadStoreBus); - ibex = new Ibex(); ibex->setInstructionFetchBus(*instructionFetchBus); ibex->setLoadStoreBus(*loadStoreBus); + agent->addBus(instructionFetchBus); + agent->addBus(loadStoreBus); agent->addCPU(ibex); instructionFetchBus->evaluateModel = evaluateModel; loadStoreBus->evaluateModel = evaluateModel; +} +RenodeAgent *Init() { + agent = initAgent(); + agent->connectNative(); + initBus(agent); return agent; } @@ -56,8 +65,10 @@ int main(int argc, char **argv, char **env) } const char *address = argc < 4 ? "127.0.0.1" : argv[3]; - Init(); - agent->simulate(atoi(argv[1]), atoi(argv[2]), address); + agent = initAgent(); + agent->connect(atoi(argv[1]), atoi(argv[2]), address); + initBus(agent); + agent->simulate(); return 0; } diff --git a/samples/fastvdma/sim_main.cpp b/samples/fastvdma/sim_main.cpp index a1eb926..be2363f 100644 --- a/samples/fastvdma/sim_main.cpp +++ b/samples/fastvdma/sim_main.cpp @@ -1,5 +1,5 @@ // -// Copyright (c) 2010-2021 Antmicro +// Copyright (c) 2010-2025 Antmicro // // This file is licensed under the MIT License. // Full license text is available in 'LICENSE' file. @@ -19,7 +19,7 @@ #include "src/buses/axilite.h" #include "src/renode_bus.h" -RenodeAgent *fastvdma; +RenodeAgent *fastvdma = new RenodeAgent; VDMATop *top = new VDMATop; VerilatedVcdC *tfp; vluint64_t main_time = 0; @@ -34,7 +34,8 @@ void eval() { fastvdma->handleInterrupts(); } -RenodeAgent *Init() { +void initAgent(RenodeAgent *agent) +{ AxiLite* bus = new AxiLite(); AxiSlave* slaveBus = new AxiSlave(32, 32); @@ -121,13 +122,16 @@ RenodeAgent *Init() { //================================================= // Init peripheral //================================================= - fastvdma = new RenodeAgent(bus); - fastvdma->addBus(slaveBus); + agent->addBus(bus); + agent->addBus(slaveBus); - fastvdma->registerInterrupt(&top->io_irq_writerDone, 0); - fastvdma->registerInterrupt(&top->io_irq_readerDone, 0); + agent->registerInterrupt(&top->io_irq_writerDone, 0); + agent->registerInterrupt(&top->io_irq_readerDone, 0); +} - slaveBus->setAgent(fastvdma); +RenodeAgent *Init() { + fastvdma->connectNative(); + initAgent(fastvdma); return fastvdma; } @@ -145,9 +149,12 @@ int main(int argc, char **argv, char **env) { top->trace(tfp, 99); tfp->open("simx.vcd"); #endif - Init(); + + fastvdma->connect(atoi(argv[1]), atoi(argv[2]), address); + initAgent(fastvdma); + fastvdma->simulate(); fastvdma->reset(); - fastvdma->simulate(atoi(argv[1]), atoi(argv[2]), address); + top->final(); exit(0); } diff --git a/samples/fpga_isp/sim_main.cpp b/samples/fpga_isp/sim_main.cpp index 988c4b6..0d91179 100644 --- a/samples/fpga_isp/sim_main.cpp +++ b/samples/fpga_isp/sim_main.cpp @@ -1,5 +1,5 @@ // -// Copyright (c) 2010-2022 Antmicro +// Copyright (c) 2010-2025 Antmicro // // This file is licensed under the MIT License. // Full license text is available in 'LICENSE' file. @@ -25,7 +25,7 @@ #include "src/buses/axi.h" #include "src/renode_bus.h" -RenodeAgent *isp; +RenodeAgent *isp = new RenodeAgent; Vfpga_isp *top = new Vfpga_isp; vluint64_t main_time = 0; @@ -43,7 +43,7 @@ void eval() { isp->handleInterrupts(); } -RenodeAgent *Init() { +void initAgent(RenodeAgent *agent) { AxiSlave* slaveBus = new AxiSlave(32, 32); Axi* axi = new Axi(32, 32); @@ -152,11 +152,8 @@ RenodeAgent *Init() { //================================================= // Init peripheral //================================================= - isp = new RenodeAgent(axi); - isp->addBus(slaveBus); - - slaveBus->setAgent(isp); - axi->setAgent(isp); + agent->addBus(axi); + agent->addBus(slaveBus); isp->registerInterrupt(&top->irq_dmaIn, 0); isp->registerInterrupt(&top->irq_dmaOut, 1); @@ -167,7 +164,11 @@ RenodeAgent *Init() { top->trace(tfp, 99); tfp->open(DEF_TRACE_FILEPATH); #endif +} +RenodeAgent *Init() { + isp->connectNative(); + initAgent(isp); return isp; } @@ -179,9 +180,10 @@ int main(int argc, char **argv, char **env) { const char *address = argc < 4 ? "127.0.0.1" : argv[3]; Verilated::commandArgs(argc, argv); - Init(); + isp->connect(atoi(argv[1]), atoi(argv[2]), address); + initAgent(isp); isp->reset(); - isp->simulate(atoi(argv[1]), atoi(argv[2]), address); + isp->simulate(); top->final(); exit(0); } diff --git a/samples/liteuart/sim_main.cpp b/samples/liteuart/sim_main.cpp index 316d2f4..6889050 100644 --- a/samples/liteuart/sim_main.cpp +++ b/samples/liteuart/sim_main.cpp @@ -1,5 +1,5 @@ // -// Copyright (c) 2010-2021 Antmicro +// Copyright (c) 2010-2025 Antmicro // // This file is licensed under the MIT License. // Full license text is available in 'LICENSE' file. @@ -34,7 +34,13 @@ void eval() { uart->eval(); } -RenodeAgent *Init() { +UART *initAgent() { + const int litex_rxtx_reg = 0x800; + return new UART(&top->serial_tx, &top->serial_rx, prescaler, litex_rxtx_reg, &top->irq_uart0); +} + +void initBus(RenodeAgent *agent) +{ Wishbone* bus = new Wishbone(); //================================================= @@ -60,8 +66,13 @@ RenodeAgent *Init() { //================================================= // Init peripheral //================================================= - const int litex_rxtx_reg = 0x800; - uart = new UART(bus, &top->serial_tx, &top->serial_rx, prescaler, litex_rxtx_reg, &top->irq_uart0); + agent->addBus(bus); +} + +RenodeAgent *Init() { + uart = initAgent(); + uart->connectNative(); + initBus(uart); return uart; } @@ -79,8 +90,11 @@ int main(int argc, char **argv, char **env) { top->trace(tfp, 99); tfp->open("simx.fst"); #endif - Init(); - uart->simulate(atoi(argv[1]), atoi(argv[2]), address); + uart = initAgent(); + uart->connect(atoi(argv[1]), atoi(argv[2]), address); + initBus(uart); + uart->simulate(); + top->final(); exit(0); } diff --git a/samples/ram/sim_main.cpp b/samples/ram/sim_main.cpp index 9e230bb..e65610b 100644 --- a/samples/ram/sim_main.cpp +++ b/samples/ram/sim_main.cpp @@ -1,5 +1,5 @@ // -// Copyright (c) 2010-2021 Antmicro +// Copyright (c) 2010-2025 Antmicro // // This file is licensed under the MIT License. // Full license text is available in 'LICENSE' file. @@ -11,12 +11,12 @@ #include #include #if VM_TRACE -# include +#include #endif #include "src/buses/axi.h" #include "src/renode.h" -RenodeAgent *axi_ram; +RenodeAgent *axi_ram = new RenodeAgent; Vaxi_ram *top = new Vaxi_ram; VerilatedVcdC *tfp; vluint64_t main_time = 0; @@ -30,7 +30,8 @@ void eval() { top->eval(); } -RenodeAgent *Init() { +void initAgent(RenodeAgent *agent) +{ Axi* bus = new Axi(32, 32); //================================================= @@ -84,8 +85,13 @@ RenodeAgent *Init() { //================================================= // Init peripheral //================================================= - axi_ram = new RenodeAgent(bus); - bus->setAgent(axi_ram); + + agent->addBus(bus); +} + +RenodeAgent *Init() { + axi_ram->connectNative(); + initAgent(axi_ram); return axi_ram; } @@ -103,8 +109,11 @@ int main(int argc, char **argv, char **env) { top->trace(tfp, 99); tfp->open("simx.vcd"); #endif - Init(); - axi_ram->simulate(atoi(argv[1]), atoi(argv[2]), address); + + axi_ram->connect(atoi(argv[1]), atoi(argv[2]), address); + initAgent(axi_ram); + axi_ram->simulate(); + top->final(); exit(0); } diff --git a/samples/uartlite/sim_main.cpp b/samples/uartlite/sim_main.cpp index f80e5b8..78337a2 100644 --- a/samples/uartlite/sim_main.cpp +++ b/samples/uartlite/sim_main.cpp @@ -1,5 +1,5 @@ // -// Copyright (c) 2010-2021 Antmicro +// Copyright (c) 2010-2025 Antmicro // // This file is licensed under the MIT License. // Full license text is available in 'LICENSE' file. @@ -32,7 +32,8 @@ void eval() { top->eval(); } -RenodeAgent *Init() { +RenodeAgent *initAgent() { + RenodeAgent *agent = new UART(&top->txd, &top->rxd, prescaler); AxiLite* bus = new AxiLite(); //================================================= @@ -66,7 +67,14 @@ RenodeAgent *Init() { //================================================= // Init peripheral //================================================= - return new UART(bus, &top->txd, &top->rxd, prescaler); + agent->addBus(bus); + return agent; +} + +RenodeAgent *Init() { + RenodeAgent *agent = initAgent(); + agent->connectNative(); + return agent; } int main(int argc, char **argv, char **env) { @@ -83,8 +91,9 @@ int main(int argc, char **argv, char **env) { top->trace(tfp, 99); tfp->open("simx.vcd"); #endif - RenodeAgent *uart = Init(); - uart->simulate(atoi(argv[1]), atoi(argv[2]), address); + RenodeAgent *uart = initAgent(); + uart->connect(atoi(argv[1]), atoi(argv[2]), address); + uart->simulate(); top->final(); exit(0); } diff --git a/samples/uartlite_extended/sim_main.cpp b/samples/uartlite_extended/sim_main.cpp index ebfc77a..8a7d14c 100644 --- a/samples/uartlite_extended/sim_main.cpp +++ b/samples/uartlite_extended/sim_main.cpp @@ -1,5 +1,5 @@ // -// Copyright (c) 2010-2021 Antmicro +// Copyright (c) 2010-2025 Antmicro // // This file is licensed under the MIT License. // Full license text is available in 'LICENSE' file. @@ -34,7 +34,7 @@ void eval() { struct UARTWithLogger: UART { - UARTWithLogger(BaseTargetBus* bus, uint8_t* txd, uint8_t* rxd, uint32_t prescaler, uint32_t tx_reg_addr=4, uint8_t* irq=nullptr); + UARTWithLogger(uint8_t* txd, uint8_t* rxd, uint32_t prescaler, uint32_t tx_reg_addr=4, uint8_t* irq=nullptr); protected: void writeToBus(int width, uint64_t addr, uint64_t value) override; @@ -42,8 +42,8 @@ struct UARTWithLogger: UART void Txd(); }; -UARTWithLogger::UARTWithLogger(BaseTargetBus* bus, uint8_t* txd, uint8_t* rxd, uint32_t prescaler, uint32_t tx_reg_addr, uint8_t* irq) - : UART(bus, txd, rxd, prescaler, tx_reg_addr, irq) {} +UARTWithLogger::UARTWithLogger(uint8_t* txd, uint8_t* rxd, uint32_t prescaler, uint32_t tx_reg_addr, uint8_t* irq) + : UART(txd, rxd, prescaler, tx_reg_addr, irq) {} void UARTWithLogger::writeToBus(int width, uint64_t addr, uint64_t value) { UART::writeToBus(width, addr, value); @@ -62,7 +62,11 @@ void UARTWithLogger::Txd() log(LOG_LEVEL_INFO, "Transmitted to Renode on the TX line"); } -RenodeAgent *Init() { +RenodeAgent *initAgent() { + return new UARTWithLogger(&top->txd, &top->rxd, prescaler); +} + +void initBus(RenodeAgent *agent) { AxiLite* bus = new AxiLite(); //================================================= @@ -96,7 +100,14 @@ RenodeAgent *Init() { //================================================= // Init peripheral //================================================= - return new UARTWithLogger(bus, &top->txd, &top->rxd, prescaler); + agent->addBus(bus); +} + +RenodeAgent *Init() { + RenodeAgent *agent = initAgent(); + agent->connectNative(); + initBus(agent); + return agent; } int main(int argc, char **argv, char **env) { @@ -113,8 +124,11 @@ int main(int argc, char **argv, char **env) { top->trace(tfp, 99); tfp->open("simx.vcd"); #endif - RenodeAgent *uart = Init(); - uart->simulate(atoi(argv[1]), atoi(argv[2]), address); + RenodeAgent *uart = initAgent(); + uart->connect(atoi(argv[1]), atoi(argv[2]), address); + initBus(uart); + uart->simulate(); + top->final(); exit(0); }