diff --git a/samples/cpu_ibex/sim_ibex.cpp b/samples/cpu_ibex/sim_ibex.cpp
index cf8324b..69ad754 100644
--- a/samples/cpu_ibex/sim_ibex.cpp
+++ b/samples/cpu_ibex/sim_ibex.cpp
@@ -7,9 +7,9 @@ void IbexBusInterface::connect(WishboneInitiator<uint32_t, uint32_t> &wishbone)
     wishbone.wb_ack = &rvalid_i();
     wishbone.wb_rd_dat = &rdata_i();
     wishbone.wb_stb = &req_o();
-    wishbone.wb_addr = &addr_o();
     wishbone.wb_wr_dat = &wdata_o();
     wishbone.wb_we = &we_o();
+    wishbone.wb_addr = &wb_addr;
     wishbone.wb_cyc = &wb_cyc;
     wishbone.wb_sel = &wb_sel;
     wishbone.wb_rst = &wb_rst;
@@ -20,6 +20,7 @@ void IbexBusInterface::convert(uint8_t clk)
 {
     gnt_i() = req_o() & ~wb_stall;
     wb_sel = be_o();
+    wb_addr = addr_o() >> 2;
 
     if (wb_rst)
         wb_cyc = low;
diff --git a/samples/cpu_ibex/sim_ibex.h b/samples/cpu_ibex/sim_ibex.h
index e0c2d41..fb9d0d8 100644
--- a/samples/cpu_ibex/sim_ibex.h
+++ b/samples/cpu_ibex/sim_ibex.h
@@ -30,6 +30,7 @@ struct IbexBusInterface
     void connect(WishboneInitiator<uint32_t, uint32_t> &wishbone);
     void convert(uint8_t clk);
 
+    uint32_t wb_addr;
     uint8_t wb_cyc = 0, wb_sel, wb_rst = high, wb_stall = high;
 };