Calling cutout prior Component.create_port_on_component ignores Circuit port type

[svandenb-dev]

Before submitting the issue

• I have searched among the existing issues
• I am using a Python virtual environment

Description of the bug

If the cutout is executed before creating ports with specifying circuit port design comes with coaxial ports.

Steps To Reproduce

Import libraries

from ansys.aedt.core.edb import Edb
from ansys.aedt.core.generic.constants import SourceType
from ansys.aedt.core.hfss3dlayout import Hfss3dLayout
from ansys.aedt.core import generate_unique_folder_name
from ansys.aedt.core.downloads import download_file

Define output project

output_project = r"D:\Temp\demo.aedb"
temp_folder = generate_unique_folder_name()
targetfile = download_file("edb/ANSYS-HSD_V1.aedb", destination=temp_folder)

Load EDB

edbapp = Edb(edbpath=targetfile, edbversion="2024.2")

Define signal and reference nets

signal_nets = ["PCIe_Gen4_RX1_P", "PCIe_Gen4_RX1_N"]
reference_net = ["GND"]

Create ports

components = ["U1", "X1"]
for component in components:
if not edbapp.components.create_port_on_component(component=component,
net_list=signal_nets,
port_type=SourceType.CircPort,
do_pingroup=True,
reference_net=reference_net,
):
edbapp.logger.error(f"Failed to create port on component {component}")

create siwave setup

siwave_setup = edbapp.create_siwave_syz_setup(name="siwave_setup")
siwave_setup.add_frequency_sweep(frequency_sweep=[
["linear count", "0", "1kHz", 1],
["log scale", "1kHz", "0.1GHz", 10],
["linear scale", "0.1GHz", "10GHz", "10GHz"],
])

Clip layout

edbapp.cutout(signal_list=signal_nets, reference_list=reference_net, expansion_size=5e-3)

Save and close EDB

edbapp.save_as(output_project)
edbapp.close()

Open EDB in ANSYS HFSS 3D layout

hfss3d = Hfss3dLayout(projectname=output_project, version="2024.2")
hfss3d.release_desktop(close_desktop=False, close_projects=False)

Which Operating System are you using?

Windows

Which Python version are you using?

3.10

Installed packages

NA