diff --git a/docs/regmap/adi_regmap_axi_laser_driver.txt b/docs/regmap/adi_regmap_axi_laser_driver.txt index 0cfb5ef794..abf6936541 100644 --- a/docs/regmap/adi_regmap_axi_laser_driver.txt +++ b/docs/regmap/adi_regmap_axi_laser_driver.txt @@ -39,7 +39,7 @@ ID ENDREG FIELD -[31:0] ''ID'' +[31:0] ID ID RO Value of the ID configuration parameter. @@ -93,7 +93,7 @@ Configuration Registers ENDREG FIELD -[31:0] ''PULSE_PERIOD'' +[31:0] PULSE_PERIOD PWM_PERIOD RW The period of the generated signal. The resolution is the core clock's time period. @@ -110,7 +110,7 @@ Configuration Registers ENDREG FIELD -[31:0] ''PULSE_WIDTH'' +[31:0] PULSE_WIDTH PWM_WIDTH RW The pulse width of the generated signal. The resolution is the core clock's time period. diff --git a/docs/regmap/adi_regmap_data_offload.txt b/docs/regmap/adi_regmap_data_offload.txt index 65e4732762..54b63daece 100644 --- a/docs/regmap/adi_regmap_data_offload.txt +++ b/docs/regmap/adi_regmap_data_offload.txt @@ -39,7 +39,7 @@ PERIPHERAL_ID ENDREG FIELD -[31:0] ''ID'' +[31:0] ID PERIPHERAL_ID RO Value of the ID configuration parameter. @@ -84,14 +84,14 @@ SYNTHESIS_CONFIG_1 ENDREG FIELD -[2] ''HAS_BYPASS'' +[2] HAS_BYPASS HAS_BYPASS RO If set the bypass logic is implemented. ENDFIELD FIELD -[1] ''TX_OR_RXN_PATH'' +[1] TX_OR_RXN_PATH TX_OR_RXN_PATH RO If this device was configured for the TX path, this bit will be set to 1. @@ -99,7 +99,7 @@ Conversely, the bit will be 0 for the RX path. ENDFIELD FIELD -[0] ''MEM_TYPE'' +[0] MEM_TYPE MEMORY_TYPE RO This bit identifies the type of memory that was chosen during synthesis. A value of 1 @@ -115,7 +115,7 @@ SYNTHESIS_CONFIG_2 ENDREG FIELD -[31:0] 1<<''MEM_SIZE_LOG2'' +[31:0] MEM_SIZE_LSB = 1<>32 +[1:0] MEM_SIZE_MSB = (1<>32 MEM_SIZE_MSB RO 2 bits (MSB) of the storage unit size. @@ -145,7 +145,7 @@ TRANSFER_LENGTH ENDREG FIELD -[31:0] (2^''MEM_SIZE_LOG2''-1)>>6 +[31:0] TRANSFER_LENGTH = (2**MEM_SIZE_LOG2-1)>>6 TRANSFER_LENGTH RW The transfer length register can be used to override the transfer length in RX mode in increments of 64 bytes. @@ -189,7 +189,7 @@ RESET_OFFLOAD ENDREG FIELD -[0] ''AUTO_BRINGUP'' +[0] AUTO_BRINGUP RESETN RW "Software Reset": Resets all the internal address registers and state machines. @@ -204,7 +204,7 @@ CONTROL ENDREG FIELD -[1] ~''TX_OR_RXN_PATH'' +[1] ONESHOT_EN = ~TX_OR_RXN_PATH ONESHOT_EN RW Enables oneshot mode. This means that the data offload will only play a received buffer once, @@ -259,14 +259,14 @@ FSM_BDG ENDREG FIELD -[11:8] 0xXXXXXXXX +[11:8] FSM_STATE_READ RO It force the Rx side offload state machine into the required state. ENDFIELD FIELD -[4:0] 0xXXXXXXXX +[4:0] FSM_STATE_WRITE RO The current state of the offload state machine. diff --git a/docs/regmap/adi_regmap_dmac.txt b/docs/regmap/adi_regmap_dmac.txt index c9081732a8..0a2648fb16 100644 --- a/docs/regmap/adi_regmap_dmac.txt +++ b/docs/regmap/adi_regmap_dmac.txt @@ -39,7 +39,7 @@ PERIPHERAL_ID ENDREG FIELD -[31:0] ''ID'' +[31:0] ID PERIPHERAL_ID RO Value of the ID configuration parameter. @@ -84,35 +84,35 @@ INTERFACE_DESCRIPTION_1 ENDREG FIELD -[3:0] log2(''DMA_DATA_WIDTH_DEST''/8) +[3:0] BYTES_PER_BEAT_DEST_LOG2 = $clog2(DMA_DATA_WIDTH_DEST/8) BYTES_PER_BEAT_DEST_LOG2 R Width of data bus on destination interface. Log2 of interface data widths in bytes. ENDFIELD FIELD -[5:4] ''DMA_TYPE_DEST'' +[5:4] DMA_TYPE_DEST DMA_TYPE_DEST R Value of ''DMA_TYPE_DEST'' parameter.(0 - AXI MemoryMap, 1 - AXI Stream, 2 - FIFO ) ENDFIELD FIELD -[11:8] log2(''DMA_DATA_WIDTH_SRC''/8) +[11:8] BYTES_PER_BEAT_SRC_LOG2 = $clog2(DMA_DATA_WIDTH_SRC/8) BYTES_PER_BEAT_SRC_LOG2 R Width of data bus on source interface. Log2 of interface data widths in bytes. ENDFIELD FIELD -[13:12] ''DMA_TYPE_SRC'' +[13:12] DMA_TYPE_SRC DMA_TYPE_SRC R Value of ''DMA_TYPE_SRC'' parameter.(0 - AXI MemoryMap, 1 - AXI Stream, 2 - FIFO ) ENDFIELD FIELD -[19:16] ''BYTES_PER_BURST_WIDTH'' +[19:16] BYTES_PER_BURST_WIDTH BYTES_PER_BURST_WIDTH R Value of ''BYTES_PER_BURST_WIDTH'' interface parameter. Log2 of the real ''MAX_BYTES_PER_BURST''. @@ -129,21 +129,21 @@ INTERFACE_DESCRIPTION_2 ENDREG FIELD -[0] ''CACHE_COHERENT'' +[0] CACHE_COHERENT CACHE_COHERENT R Value of ''CACHE_COHERENT'' parameter.(0 - Disabled, 1 - Enabled ) ENDFIELD FIELD -[7:4] ''AXI_AXCACHE'' +[7:4] AXI_AXCACHE AXI_AXCACHE R Value of ''AXI_AXCACHE'' parameter. ENDFIELD FIELD -[10:8] ''AXI_AXPROT'' +[10:8] AXI_AXPROT AXI_AXPROT R Value of ''AXI_AXPROT'' parameter. @@ -298,7 +298,7 @@ FLAGS ENDREG FIELD -[0] ''CYCLIC'' +[0] CYCLIC CYCLIC RW Setting this field to 1 puts the DMA transfer into cyclic mode. In cyclic mode @@ -368,7 +368,7 @@ X_LENGTH ENDREG FIELD -[31:0] 2^log2(max(''DMA_DATA_WIDTH_SRC'', ''DMA_DATA_WIDTH_DEST'')/8)-1 +[31:0] X_LENGTH = 2**$clog2(`MAX(DMA_DATA_WIDTH_SRC, DMA_DATA_WIDTH_DEST)/8)-1 X_LENGTH RW Number of bytes to transfer - 1. diff --git a/docs/regmap/adi_regmap_fan_control.txt b/docs/regmap/adi_regmap_fan_control.txt index 9ad4c54610..f6467bd38a 100644 --- a/docs/regmap/adi_regmap_fan_control.txt +++ b/docs/regmap/adi_regmap_fan_control.txt @@ -39,7 +39,7 @@ PERIPHERAL_ID ENDREG FIELD -[31:0] ''ID'' +[31:0] ID PERIPHERAL_ID RO Value of the ID configuration parameter. @@ -221,7 +221,7 @@ PWM_WIDTH ENDREG FIELD -[31:0] ''PWM_PERIOD'' +[31:0] PWM_PERIOD PWM_WIDTH RW This register contains the width of the PWM output signal. By default its @@ -278,7 +278,7 @@ TEMP_DATA_SOURCE ENDREG FIELD -[31:0] ''INTERNAL_SYSMONE'' +[31:0] INTERNAL_SYSMONE TEMP_DATA_SOURCE RO This register copies the value from the INTERNAL_SYSMONE register and is used to inform @@ -342,7 +342,7 @@ TEMP_00_H ENDREG FIELD -[31:0] ''TEMP_00_H'' +[31:0] TEMP_00_H TEMP_00_H RW Temperature threshold below which PWM should be 0% @@ -357,7 +357,7 @@ TEMP_25_L ENDREG FIELD -[31:0] ''TEMP_25_L'' +[31:0] TEMP_25_L TEMP_25_L RW Temperature threshold above which PWM should be 25% @@ -372,7 +372,7 @@ TEMP_25_H ENDREG FIELD -[31:0] ''TEMP_25_H'' +[31:0] TEMP_25_H TEMP_25_H RW Temperature threshold below which PWM should be 25% @@ -387,7 +387,7 @@ TEMP_50_L ENDREG FIELD -[31:0] ''TEMP_50_L'' +[31:0] TEMP_50_L TEMP_50_L RW Temperature threshold above which PWM should be 50% @@ -402,7 +402,7 @@ TEMP_50_H ENDREG FIELD -[31:0] ''TEMP_50_H'' +[31:0] TEMP_50_H TEMP_50_H RW Temperature threshold below which PWM should be 50% @@ -417,7 +417,7 @@ TEMP_75_L ENDREG FIELD -[31:0] ''TEMP_75_L'' +[31:0] TEMP_75_L TEMP_75_L RW Temperature threshold above which PWM should be 75% @@ -432,7 +432,7 @@ TEMP_75_H ENDREG FIELD -[31:0] ''TEMP_75_H'' +[31:0] TEMP_75_H TEMP_75_H RW Temperature threshold below which PWM should be 75% @@ -447,7 +447,7 @@ TEMP_100_L ENDREG FIELD -[31:0] ''TEMP_100_L'' +[31:0] TEMP_100_L TEMP_100_L RW Temperature threshold above which PWM should be 100% @@ -462,7 +462,7 @@ TACHO_25 ENDREG FIELD -[31:0] ''TACHO_T25'' +[31:0] TACHO_T25 TACHO_25 RW Nominal tacho period at 25% PWM @@ -477,7 +477,7 @@ TACHO_50 ENDREG FIELD -[31:0] ''TACHO_T50'' +[31:0] TACHO_T50 TACHO_50 RW Nominal tacho period at 50% PWM @@ -492,7 +492,7 @@ TACHO_75 ENDREG FIELD -[31:0] ''TACHO_T75'' +[31:0] TACHO_T75 TACHO_75 RW Nominal tacho period at 75% PWM @@ -507,7 +507,7 @@ TACHO_100 ENDREG FIELD -[31:0] ''TACHO_T100'' +[31:0] TACHO_T100 TACHO_100 RW Nominal tacho period at 100% PWM @@ -522,7 +522,7 @@ TACHO_25_TOL ENDREG FIELD -[31:0] ''TACHO_T25''*''TACHO_TOL_PERCENT''/100 +[31:0] TACHO_25_TOL = TACHO_T25*TACHO_TOL_PERCENT/100 TACHO_25_TOL RW Tolerance for the 25% PWM tacho period @@ -537,7 +537,7 @@ TACHO_50_TOL ENDREG FIELD -[31:0] ''TACHO_T50''*''TACHO_TOL_PERCENT''/100 +[31:0] TACHO_50_TOL = TACHO_T50*TACHO_TOL_PERCENT/100 TACHO_50_TOL RW Tolerance for the 50% PWM tacho period @@ -552,7 +552,7 @@ TACHO_75_TOL ENDREG FIELD -[31:0] ''TACHO_T75''*''TACHO_TOL_PERCENT''/100 +[31:0] TACHO_75_TOL = TACHO_T75*TACHO_TOL_PERCENT/100 TACHO_75_TOL RW Tolerance for the 75% PWM tacho period @@ -567,7 +567,7 @@ TACHO_100_TOL ENDREG FIELD -[31:0] ''TACHO_T100''*''TACHO_TOL_PERCENT''/100 +[31:0] TACHO_100_TOL = TACHO_T100*TACHO_TOL_PERCENT/100 TACHO_100_TOL RW Tolerance for the 100% PWM tacho period diff --git a/docs/regmap/adi_regmap_hdmi.txt b/docs/regmap/adi_regmap_hdmi.txt index fa9963e0e6..5afb848574 100644 --- a/docs/regmap/adi_regmap_hdmi.txt +++ b/docs/regmap/adi_regmap_hdmi.txt @@ -8,7 +8,7 @@ ENDTITLE REG 0x0010 -RSTN +RSTN_TX HDMI Interface Control & Status ENDREG @@ -90,7 +90,7 @@ ENDFIELD REG 0x0015 -CLK_FREQ +CLK_FREQ_TX HDMI Interface Control & Status ENDREG @@ -111,7 +111,7 @@ ENDFIELD REG 0x0016 -CLK_RATIO +CLK_RATIO_TX HDMI Interface Control & Status ENDREG @@ -145,7 +145,7 @@ ENDFIELD REG 0x0018 -VDMA_STATUS +VDMA_STATUS_TX HDMI Interface Control & Status ENDREG @@ -395,7 +395,7 @@ ENDTITLE REG 0x0010 -RSTN +RSTN_RX HDMI Interface Control & Status ENDREG @@ -450,7 +450,7 @@ ENDFIELD REG 0x0015 -CLK_FREQ +CLK_FREQ_RX HDMI Interface Control & Status ENDREG @@ -471,7 +471,7 @@ ENDFIELD REG 0x0016 -CLK_RATIO +CLK_RATIO_RX HDMI Interface Control & Status ENDREG @@ -488,7 +488,7 @@ ENDFIELD REG 0x0018 -VDMA_STATUS +VDMA_STATUS_RX HDMI Interface Control & Status ENDREG diff --git a/docs/regmap/adi_regmap_i3c_controller.txt b/docs/regmap/adi_regmap_i3c_controller.txt index a8c6261d37..6746abdb29 100644 --- a/docs/regmap/adi_regmap_i3c_controller.txt +++ b/docs/regmap/adi_regmap_i3c_controller.txt @@ -39,7 +39,7 @@ DEVICE_ID ENDREG FIELD -[31:0] ''ID'' +[31:0] ID DEVICE_ID RO Value of the ID configuration parameter. @@ -183,7 +183,7 @@ CMD_FIFO_ROOM ENDREG FIELD -[31:0] 0xXXXXXXXX +[31:0] CMD_FIFO_ROOM RO Number of free entries in the CMD FIFO. @@ -213,7 +213,7 @@ SDO_FIFO_ROOM ENDREG FIELD -[31:0] 0xXXXXXXXX +[31:0] SDO_FIFO_ROOM RO Number of free entries in the SDO FIFO. @@ -265,42 +265,42 @@ See :ref:`i3c_controller instruction-format` for the structure of the command. ENDREG FIELD -[22] 0xX +[22] CMD_IS_CCC WO Indicate if it is a CCC transfer (1) or not (0). ENDFIELD FIELD -[21] 0xX +[21] CMD_BCAST_HEADER WO Include broadcast header in private transfer (1) or not (0). ENDFIELD FIELD -[20] 0xX +[20] CMD_SR WO Repeated start flag, yield a Sr (1) or P (0) at the end of the transfer. ENDFIELD FIELD -[19:8] 0xXXX +[19:8] CMD_BUFFER_LENGHT WO Unsigned 12-bits payload length, direction depends on RNW value. ENDFIELD FIELD -[7:1] 0xXX +[7:1] CMD_DA WO 7-bit device address (don’t care in broadcast mode). ENDFIELD FIELD -[0] 0xX +[0] CMD_RNW WO If should retrieve data from device (1) or not (0). @@ -318,21 +318,21 @@ Writing to it has no effect. ENDREG FIELD -[23:0] 0x?? +[23:0] CMDR_FIFO_ERROR RO If an error occurred during the transfer. ENDFIELD FIELD -[19:8] 0x?? +[19:8] CMDR_FIFO_BUFFER_LENGTH RO Unsigned 12-bits transferred payload length. ENDFIELD FIELD -[7:0] 0x?? +[7:0] CMDR_FIFO_SYNC RO Command synchronization. @@ -350,25 +350,25 @@ is discarded. Reading from this register always returns 0x00000000. ENDREG FIELD -[31:24] 0xXX +[31:24] SDO_FIFO_BYTE_3 RO ENDFIELD FIELD -[23:16] 0xXX +[23:16] SDO_FIFO_BYTE_2 RO ENDFIELD FIELD -[15:8] 0xXX +[15:8] SDO_FIFO_BYTE_1 RO ENDFIELD FIELD -[7:0] 0xXX +[7:0] SDO_FIFO_BYTE_0 RO ENDFIELD @@ -385,7 +385,7 @@ Writing to it has no effect. ENDREG FIELD -[31:0] 0xXXXXXXXX +[31:0] SDI_FIFO RO ENDFIELD @@ -402,21 +402,21 @@ Writing to it has no effect. ENDREG FIELD -[23:17] 0xXX +[23:17] IBI_FIFO_DA RO IBI Dynamic address. ENDFIELD FIELD -[15:8] 0xXX +[15:8] IBI_FIFO_MDB RO IBI MDB, if the peripheral's BCR[2] is Low, the field is ignored. ENDFIELD FIELD -[7:0] 0xXX +[7:0] IBI_FIFO_SYNC RO Synchronization number. @@ -546,7 +546,7 @@ Device address to apply DEV_CHAR[3:0]. ENDFIELD FIELD -[8] 0xX +[8] DEV_CHAR_WEN W Enable write of the fields. diff --git a/docs/regmap/adi_regmap_interpolate.txt b/docs/regmap/adi_regmap_interpolate.txt index 40a60a7659..705517a9f1 100644 --- a/docs/regmap/adi_regmap_interpolate.txt +++ b/docs/regmap/adi_regmap_interpolate.txt @@ -214,7 +214,7 @@ ENDREG FIELD [20] -Auto rearm trigger +AUTO_REARM_TRIGGER RW Rearms the trigger on the last(sample) signal of the DMA(per DAC channel) ENDFIELD diff --git a/docs/regmap/adi_regmap_jesd_rx.txt b/docs/regmap/adi_regmap_jesd_rx.txt index e1beb1d280..a3100c0613 100644 --- a/docs/regmap/adi_regmap_jesd_rx.txt +++ b/docs/regmap/adi_regmap_jesd_rx.txt @@ -160,7 +160,7 @@ Available starting from version 1.07.a; ENDFIELD FIELD -[12] ''ASYNC_CLK'' +[12] ASYNC_CLK ASYNC_CLK RO This bit is set if link clock and device clock are connected to different sources. diff --git a/docs/regmap/adi_regmap_jesd_tx.txt b/docs/regmap/adi_regmap_jesd_tx.txt index d0c3581bda..a5760fa6d5 100644 --- a/docs/regmap/adi_regmap_jesd_tx.txt +++ b/docs/regmap/adi_regmap_jesd_tx.txt @@ -143,7 +143,7 @@ Available starting from version 1.06.a; ENDFIELD FIELD -[12] ''ASYNC_CLK'' +[12] ASYNC_CLK ASYNC_CLK RO This bit is set if link clock and device clock are connected to different sources. diff --git a/docs/regmap/adi_regmap_pwm_gen.txt b/docs/regmap/adi_regmap_pwm_gen.txt index f4fee0566a..737766a8e2 100644 --- a/docs/regmap/adi_regmap_pwm_gen.txt +++ b/docs/regmap/adi_regmap_pwm_gen.txt @@ -8,13 +8,13 @@ ENDTITLE REG 0x0000 -REG_VERSION +VERSION Version and Scratch Registers ENDREG FIELD [31:0] 0x00020101 -VERSION[31:0] +VERSION RO Version number. Unique to all cores. ENDFIELD @@ -24,13 +24,13 @@ ENDFIELD REG 0x0001 -REG_ID +ID Core ID ENDREG FIELD [31:0] 0x00000000 -ID[31:0] +ID RO Instance identifier number. ENDFIELD @@ -40,13 +40,13 @@ ENDFIELD REG 0x0002 -REG_SCRATCH +SCRATCH Version and Scratch Registers ENDREG FIELD [31:0] 0x00000000 -SCRATCH[31:0] +SCRATCH RW Scratch register. ENDFIELD @@ -56,13 +56,13 @@ ENDFIELD REG 0x0003 -REG_CORE_MAGIC +CORE_MAGIC Identification number ENDREG FIELD [31:0] 0x504C5347 -CORE_MAGIC[31:0] +CORE_MAGIC RW Identification number. ENDFIELD @@ -72,7 +72,7 @@ ENDFIELD REG 0x0004 -REG_RSTN +RSTN Reset and load values ENDREG @@ -95,7 +95,7 @@ ENDFIELD REG 0x0006 -REG_CONFIG +CONFIG Features enable register ENDREG @@ -130,7 +130,7 @@ ENDFIELD REG 0x0005 -REG_NB_PULSES +NB_PULSES Number of pulses ENDREG @@ -145,48 +145,51 @@ ENDFIELD ############################################################################################ REG -0x0010 -REG_PULSE_X_PERIOD -Pulse x period +0x0010 + n +WHERE n IS FROM 0 TO 15 +PULSE_n_PERIOD +Pulse n period ENDREG FIELD [31:0] 0x0000 -PULSE_X_PERIOD[31:0] - base + 'h4 for each channel -> e.g. CH3 period - 'h4C +PULSE_PERIOD RW -Pulse x duration, defined in number of clock cycles. +Pulse duration, defined in number of clock cycles. ENDFIELD ############################################################################################ ############################################################################################ REG -0x0020 -REG_PULSE_X_WIDTH -Pulse x width +0x0020 + n +WHERE n IS FROM 0 TO 15 +PULSE_n_WIDTH +Pulse n width ENDREG FIELD [31:0] 0x0000 -PULSE_X_WIDTH[31:0] - base + 'h4 for each channel -> e.g. CH3 width - 'h8C +PULSE_WIDTH RW -Pulse x width (high time), defined in number of clock cycles. +Pulse width (high time), defined in number of clock cycles. ENDFIELD ############################################################################################ ############################################################################################ REG -0x0030 -REG_PULSE_X_OFFSET -Pulse x offset +0x0030 + n +WHERE n IS FROM 0 TO 15 +PULSE_n_OFFSET +Pulse n offset ENDREG FIELD [31:0] 0x0000 -PULSE_X_OFFSET[31:0] - base + 'h4 for each channel -> e.g. CH3 offset - 'hCC +PULSE_OFFSET RW -Pulse x offset, defined in number of clock cycles. +Pulse offset, defined in number of clock cycles. ENDFIELD ############################################################################################ diff --git a/docs/regmap/adi_regmap_spi_engine.txt b/docs/regmap/adi_regmap_spi_engine.txt index 681c37d45d..f4993ed354 100644 --- a/docs/regmap/adi_regmap_spi_engine.txt +++ b/docs/regmap/adi_regmap_spi_engine.txt @@ -39,7 +39,7 @@ PERIPHERAL_ID ENDREG FIELD -[31:0] ''ID'' +[31:0] ID PERIPHERAL_ID RO Value of the ID configuration parameter. @@ -70,7 +70,7 @@ DATA_WIDTH ENDREG FIELD -[7:4] ''NUM_OF_SDI'' +[7:4] NUM_OF_SDI NUM_OF_SDI RO Number of SDI. @@ -78,7 +78,7 @@ It is equal with the maximum supported SDI lines in bits. ENDFIELD FIELD -[3:0] ''DATA_WITH'' +[3:0] DATA_WIDTH DATA_WIDTH RO Data width of the SDI/SDO parallel interface. @@ -247,7 +247,7 @@ SYNC_ID ENDREG FIELD -[31:0] 0xXXXXXXXX +[31:0] SYNC_ID RO Last synchronization event ID received from the SPI engine control interface. @@ -277,7 +277,7 @@ CMD_FIFO_ROOM ENDREG FIELD -[31:0] log2((2^''CMD_FIFO_ADDRESS_WIDTH'')-1) +[31:0] CMD_FIFO_ROOM = $clog2((2**CMD_FIFO_ADDRESS_WIDTH)-1) CMD_FIFO_ROOM RO Number of free entries in the command FIFO. The reset value of the CMD_FIFO_ROOM register @@ -293,7 +293,7 @@ SDO_FIFO_ROOM ENDREG FIELD -[31:0] log2((2^''SDO_FIFO_ADDRESS_WIDTH'')-1) +[31:0] SDO_FIFO_ROOM = $clog2((2**SDO_FIFO_ADDRESS_WIDTH)-1) SDO_FIFO_ROOM RO Number of free entries in the serial-data-out FIFO. The reset value of the SDO_FIFO_ROOM @@ -324,7 +324,7 @@ CMD_FIFO ENDREG FIELD -[31:0] 0xXXXXXXXX +[31:0] CMD_FIFO WO Command FIFO register. Writing to this register inserts an entry into the command FIFO. @@ -341,7 +341,7 @@ SDO_FIFO ENDREG FIELD -[31:0] 0xXXXXXXXX +[31:0] SDO_FIFO WO SDO FIFO register. Writing to this register inserts an entry into the SDO FIFO. @@ -358,7 +358,7 @@ SDI_FIFO ENDREG FIELD -[31:0] 0xXXXXXXXX +[31:0] SDI_FIFO RO SDI FIFO register. Reading from this register removes the first entry from the SDI FIFO. @@ -375,7 +375,7 @@ SDI_FIFO_MSB ENDREG FIELD -[31:0] 0xXXXXXXXX +[31:0] SDI_FIFO_MSB RO Store SDI's 32 bits MSB, if exists. @@ -390,7 +390,7 @@ SDI_FIFO_PEEK ENDREG FIELD -[31:0] 0xXXXXXXXX +[31:0] SDI_FIFO_PEEK RO SDI FIFO peek register. @@ -453,7 +453,7 @@ OFFLOAD0_CDM_FIFO ENDREG FIELD -[31:0] 0xXXXXXXXX +[31:0] OFFLOAD0_CDM_FIFO WO Offload command FIFO register. Writing to this register inserts an entry into the command FIFO @@ -470,7 +470,7 @@ OFFLOAD0_SDO_FIFO ENDREG FIELD -[31:0] 0xXXXXXXXX +[31:0] OFFLOAD0_SDO_FIFO WO Offload SDO FIFO register. Writing to this register inserts an entry into the offload SDO FIFO. @@ -487,7 +487,7 @@ CFG_INFO_0 ENDREG FIELD -[31:0] ''CFG_INFO_0'' +[31:0] CFG_INFO_0 CFG_INFO_0 RO Configuration Info. @@ -501,7 +501,7 @@ CFG_INFO_1 ENDREG FIELD -[31:0] ''CFG_INFO_1'' +[31:0] CFG_INFO_1 CFG_INFO_1 RO Configuration Info. @@ -515,7 +515,7 @@ CFG_INFO_2 ENDREG FIELD -[31:0] ''CFG_INFO_2'' +[31:0] CFG_INFO_2 CFG_INFO_2 RO Configuration Info. @@ -529,7 +529,7 @@ CFG_INFO_3 ENDREG FIELD -[31:0] ''CFG_INFO_3'' +[31:0] CFG_INFO_3 CFG_INFO_4 RO Configuration Info. diff --git a/docs/regmap/adi_regmap_system_id.txt b/docs/regmap/adi_regmap_system_id.txt index ac949fda78..7ae29942dd 100644 --- a/docs/regmap/adi_regmap_system_id.txt +++ b/docs/regmap/adi_regmap_system_id.txt @@ -39,7 +39,7 @@ PERIPHERAL_ID ENDREG FIELD -[31:0] ''ID'' +[31:0] ID PERIPHERAL_ID RO Value of the ID configuration parameter. diff --git a/docs/regmap/adi_regmap_tdd_gen.txt b/docs/regmap/adi_regmap_tdd_gen.txt index f53c1e3ad9..5352ab7058 100644 --- a/docs/regmap/adi_regmap_tdd_gen.txt +++ b/docs/regmap/adi_regmap_tdd_gen.txt @@ -39,7 +39,7 @@ PERIPHERAL_ID ENDREG FIELD -[31:0] ''ID'' +[31:0] ID PERIPHERAL_ID R Value of the ID configuration parameter. @@ -84,49 +84,49 @@ INTERFACE_DESCRIPTION ENDREG FIELD -[30:24] ''SYNC_COUNT_WIDTH'' +[30:24] SYNC_COUNT_WIDTH SYNC_COUNT_WIDTH R Width of internal synchronization counter. ENDFIELD FIELD -[21:16] ''BURST_COUNT_WIDTH'' +[21:16] BURST_COUNT_WIDTH BURST_COUNT_WIDTH R Width of burst counter. ENDFIELD FIELD -[13:8] ''REGISTER_WIDTH'' +[13:8] REGISTER_WIDTH REGISTER_WIDTH R Width of internal reference counter and timing registers. ENDFIELD FIELD -[7] ''SYNC_EXTERNAL_CDC'' +[7] SYNC_EXTERNAL_CDC SYNC_EXTERNAL_CDC R Enable CDC for external synchronization pulse. ENDFIELD FIELD -[6] ''SYNC_EXTERNAL'' +[6] SYNC_EXTERNAL SYNC_EXTERNAL R Enable external synchronization support. ENDFIELD FIELD -[5] ''SYNC_INTERNAL'' +[5] SYNC_INTERNAL SYNC_INTERNAL R Enable internal synchronization support. ENDFIELD FIELD -[4:0] ''CHANNEL_COUNT''-1 +[4:0] CHANNEL_COUNT_EXTRA = CHANNEL_COUNT-1 CHANNEL_COUNT_EXTRA R Number of channels starting from CH1, excluding CH0. @@ -141,7 +141,7 @@ DEFAULT_POLARITY ENDREG FIELD -[31:0] ''DEFAULT_POLARITY'' +[31:0] DEFAULT_POLARITY DEFAULT_POLARITY R Default polarity per every channel - LSB corresponds to CH0, MSB to CH31. diff --git a/docs/regmap/adi_regmap_xcvr_intel.txt b/docs/regmap/adi_regmap_xcvr_intel.txt index af85666c77..ec957507f8 100644 --- a/docs/regmap/adi_regmap_xcvr_intel.txt +++ b/docs/regmap/adi_regmap_xcvr_intel.txt @@ -96,7 +96,7 @@ Status Reporting Register ENDREG FIELD -[31:NUM_OF_LANES] +[31:NUM_OF_LANES+1] RESERVED RO 0 diff --git a/docs/user_guide/ip_cores/creating_new_ip.rst b/docs/user_guide/ip_cores/creating_new_ip.rst index a866b906c1..7c07516e79 100644 --- a/docs/user_guide/ip_cores/creating_new_ip.rst +++ b/docs/user_guide/ip_cores/creating_new_ip.rst @@ -55,14 +55,14 @@ The register and fields are defined with the following syntax: REG - 0x00000000 +
[WHERE n IS ...] ENDREG FIELD - [31:0] 0x00000000 + [31:0] [WHERE n IS ...] @@ -100,21 +100,72 @@ For example: The ``WHERE`` line is only present if using ranged :ref:`register/fields `. Noticed that the description can be multi-line and can also include Sphinx -syntax, parsed during build +syntax, parsed during build. The file content is always 90-columns wide. -A field default value shall be a parameter, by escaping it with "double" single -quotes ``''``, e.g. +There are multiple ways to define the default value for a field. +All parameter values used for defining or calculating the default +value of a field must be a configuration parameter. +In cases where expressions are used to calculate the field values, these +must be compatible SystemVerilog, as the expressions are used in the +simulation environment as well. .. code:: FIELD - [31:0] ''ID'' + [31:0] + SCRATCH + RO + Value of the Scratch field is undefined. + In a simulation environment this value appears as X for all bits. + ENDFIELD + + FIELD + [31:0] 0x12345678 + VERSION + RO + Value of the Version is hardcoded in the IP. + ENDFIELD + + FIELD + [31:0] ID PERIPHERAL_ID RO Value of the ID configuration parameter. In case of multiple instances, each instance will have a unique ID. ENDFIELD + FIELD + [31:0] SPECIAL = (VALUE1+(VALUE2-VALUE3)*VALUE4)/VALUE5 + SPECIAL + RO + Value of the SPECIAL field is calculated using an expression. + Example of simple operations + ENDFIELD + + FIELD + [31:0] SPECIAL = (VALUE1>VALUE2)?VALUE3:VALUE4 + SPECIAL + RO + Value of the SPECIAL field is calculated using an expression. + Example of conditional calculation + ENDFIELD + + FIELD + [31:0] SPECIAL = `MAX(VALUE1,`MIN(VALUE2,VALUE3)) + SPECIAL + RO + Value of the SPECIAL field is calculated using an expression. + Example of min and max value calculation + ENDFIELD + + FIELD + [31:0] SPECIAL = $clog2(VALUE1**VALUE2) + SPECIAL + RO + Value of the SPECIAL field is calculated using an expression. + Example of log2 and exponentiation calculation + ENDFIELD + Examples: * :git-hdl:`docs/regmap/adi_regmap_spi_engine.txt` @@ -196,11 +247,20 @@ Ranged Registers and Fields ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Registers and fields can use a special ``n`` variable and the ``WHERE`` method -to define an incrementing/repeating register/field. +to define an incrementing/repeating register/field. There is an option increase +the address increment value by an additional parameter. This parameter must be +in hexadecimal format as well. The syntax is ``WHERE n IS FROM TO ``, for example, for registers: .. code:: + REG + 0x0102 + n + WHERE n IS FROM 0 TO 15 + CHAN_CNTRLn_3 + DAC Channel Control & Status (channel - 0) + ENDREG + REG 0x0102 + 0x16*n WHERE n IS FROM 0 TO 15