From 476d1d42299d4bdce1354d5721eec455bba9d5c6 Mon Sep 17 00:00:00 2001 From: Tomasz Motylewski Date: Fri, 27 Mar 2020 15:28:57 +0100 Subject: [PATCH 01/12] fix aximrd2wbsp.v parameters AW. fix S_AXI_ARREADY output wire --- rtl/aximrd2wbsp.v | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/rtl/aximrd2wbsp.v b/rtl/aximrd2wbsp.v index a8099b0..0f0bb8b 100644 --- a/rtl/aximrd2wbsp.v +++ b/rtl/aximrd2wbsp.v @@ -51,7 +51,8 @@ module aximrd2wbsp #( // This is an int between 1-16 parameter C_AXI_DATA_WIDTH = 32,// Width of the AXI R&W data parameter C_AXI_ADDR_WIDTH = 28, // AXI Address width - parameter AW = 26, // AXI Address width + localparam AXI_LSBS = $clog2(C_AXI_DATA_WIDTH)-3, + parameter AW = C_AXI_ADDR_WIDTH - AXI_LSBS, // AXI Address width parameter LGFIFO = 3, parameter [0:0] OPT_SWAP_ENDIANNESS = 0 // parameter WBMODE = "B4PIPELINE" @@ -62,7 +63,7 @@ module aximrd2wbsp #( // AXI read address channel signals input wire S_AXI_ARVALID, // Read address valid - output reg S_AXI_ARREADY, // Read address ready + output wire S_AXI_ARREADY, // Read address ready input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID, // Read ID input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR, // Read address input wire [7:0] S_AXI_ARLEN, // Read Burst Length From 7a6581624df50fbbb96c19749d661dd868480e7f Mon Sep 17 00:00:00 2001 From: Tomasz Motylewski Date: Tue, 21 Jul 2020 17:58:46 +0200 Subject: [PATCH 02/12] ported wb2axip to Xilinx Vivado Verilog (not SystemVerilog because import in block design does not work in 2019.2) replaced localparam, removed default_nettype none --- rtl/axi_addr.v | 2 +- rtl/axilrd2wbsp.v | 2 +- rtl/axilsingle.v | 6 +++--- rtl/axilwr2wbsp.v | 2 +- rtl/axim2wbsp.v | 12 ++++++------ rtl/aximrd2wbsp.v | 2 +- rtl/aximwr2wbsp.v | 2 +- rtl/sfifo.v | 2 +- rtl/skidbuffer.v | 2 +- rtl/wbarbiter.v | 2 +- 10 files changed, 17 insertions(+), 17 deletions(-) diff --git a/rtl/axi_addr.v b/rtl/axi_addr.v index 73942c2..cf4ec12 100644 --- a/rtl/axi_addr.v +++ b/rtl/axi_addr.v @@ -39,7 +39,7 @@ //////////////////////////////////////////////////////////////////////////////// // // -`default_nettype none +//`default_nettype none // // module axi_addr(i_last_addr, diff --git a/rtl/axilrd2wbsp.v b/rtl/axilrd2wbsp.v index 635b13f..be9b762 100644 --- a/rtl/axilrd2wbsp.v +++ b/rtl/axilrd2wbsp.v @@ -32,7 +32,7 @@ //////////////////////////////////////////////////////////////////////////////// // // -`default_nettype none +//`default_nettype none // module axilrd2wbsp(i_clk, i_axi_reset_n, // AXI read address channel signals diff --git a/rtl/axilsingle.v b/rtl/axilsingle.v index 13a9911..d2cab8f 100644 --- a/rtl/axilsingle.v +++ b/rtl/axilsingle.v @@ -112,11 +112,11 @@ module axilsingle #( parameter NS = 16, // parameter integer C_AXI_DATA_WIDTH = 32, - localparam integer C_AXI_ADDR_WIDTH = $clog2(NS)+$clog2(C_AXI_DATA_WIDTH)-3, + parameter integer C_AXI_ADDR_WIDTH = $clog2(NS)+$clog2(C_AXI_DATA_WIDTH)-3, // // AW, and DW, are short-hand abbreviations used locally. - localparam AW = C_AXI_ADDR_WIDTH, - localparam DW = C_AXI_DATA_WIDTH, + parameter AW = C_AXI_ADDR_WIDTH, + parameter DW = C_AXI_DATA_WIDTH, // // LGFLEN specifies the log (based two) of the number of // transactions that may need to be held outstanding internally. diff --git a/rtl/axilwr2wbsp.v b/rtl/axilwr2wbsp.v index b9cc152..55a0ae3 100644 --- a/rtl/axilwr2wbsp.v +++ b/rtl/axilwr2wbsp.v @@ -33,7 +33,7 @@ //////////////////////////////////////////////////////////////////////////////// // // -`default_nettype none +//`default_nettype none // module axilwr2wbsp(i_clk, i_axi_reset_n, // AXI write address channel signals diff --git a/rtl/axim2wbsp.v b/rtl/axim2wbsp.v index f4eda1c..1c723ec 100644 --- a/rtl/axim2wbsp.v +++ b/rtl/axim2wbsp.v @@ -39,16 +39,16 @@ //////////////////////////////////////////////////////////////////////////////// // // -`default_nettype none +//`default_nettype none // module axim2wbsp #( - parameter C_AXI_ID_WIDTH = 2, // The AXI id width used for R&W + parameter C_AXI_ID_WIDTH = 16, // The AXI id width used for R&W // This is an int between 1-16 parameter C_AXI_DATA_WIDTH = 32,// Width of the AXI R&W data - parameter C_AXI_ADDR_WIDTH = 28, // AXI Address width - localparam AXI_LSBS = $clog2(C_AXI_DATA_WIDTH)-3, - localparam DW = C_AXI_DATA_WIDTH, - localparam AW = C_AXI_ADDR_WIDTH - AXI_LSBS, + parameter C_AXI_ADDR_WIDTH = 16, // AXI Address width + parameter AXI_LSBS = $clog2(C_AXI_DATA_WIDTH)-3, + parameter DW = C_AXI_DATA_WIDTH, + parameter AW = C_AXI_ADDR_WIDTH - AXI_LSBS, parameter LGFIFO = 5, parameter [0:0] OPT_READONLY = 1'b0, parameter [0:0] OPT_WRITEONLY = 1'b0 diff --git a/rtl/aximrd2wbsp.v b/rtl/aximrd2wbsp.v index 0f0bb8b..c1436f6 100644 --- a/rtl/aximrd2wbsp.v +++ b/rtl/aximrd2wbsp.v @@ -44,7 +44,7 @@ //////////////////////////////////////////////////////////////////////////////// // // -`default_nettype none +//`default_nettype none // module aximrd2wbsp #( parameter C_AXI_ID_WIDTH = 6, // The AXI id width used for R&W diff --git a/rtl/aximwr2wbsp.v b/rtl/aximwr2wbsp.v index 08637aa..6670b5e 100644 --- a/rtl/aximwr2wbsp.v +++ b/rtl/aximwr2wbsp.v @@ -33,7 +33,7 @@ //////////////////////////////////////////////////////////////////////////////// // // -`default_nettype none +//`default_nettype none // // module aximwr2wbsp #( diff --git a/rtl/sfifo.v b/rtl/sfifo.v index 189ad29..54fa46c 100644 --- a/rtl/sfifo.v +++ b/rtl/sfifo.v @@ -22,7 +22,7 @@ //////////////////////////////////////////////////////////////////////////////// // // -`default_nettype none +//`default_nettype none // module sfifo(i_clk, i_reset, i_wr, i_data, o_full, o_fill, i_rd, o_data, o_empty); parameter BW=8; // Byte/data width diff --git a/rtl/skidbuffer.v b/rtl/skidbuffer.v index 3fdaf0d..afe155c 100644 --- a/rtl/skidbuffer.v +++ b/rtl/skidbuffer.v @@ -76,7 +76,7 @@ //////////////////////////////////////////////////////////////////////////////// // // -`default_nettype none +//`default_nettype none // module skidbuffer(i_clk, i_reset, i_valid, o_ready, i_data, diff --git a/rtl/wbarbiter.v b/rtl/wbarbiter.v index 9a834aa..5054663 100644 --- a/rtl/wbarbiter.v +++ b/rtl/wbarbiter.v @@ -54,7 +54,7 @@ //////////////////////////////////////////////////////////////////////////////// // // -`default_nettype none +//`default_nettype none // `define WBA_ALTERNATING // From ae288823da581f4778c96ce7061564dfa6631bd5 Mon Sep 17 00:00:00 2001 From: Tomasz Motylewski Date: Mon, 27 Jul 2020 18:06:17 +0200 Subject: [PATCH 03/12] fixed default_nettype in all wb2axip modules --- rtl/afifo.v | 1 + rtl/axi_addr.v | 2 +- rtl/axidma.v | 4 ++++ rtl/axidouble.v | 1 + rtl/axildouble.v | 6 +++--- rtl/axilrd2wbsp.v | 2 +- rtl/axilsingle.v | 6 +++--- rtl/axilwr2wbsp.v | 2 +- rtl/axim2wbsp.v | 6 +++++- rtl/aximrd2wbsp.v | 6 +++++- rtl/aximwr2wbsp.v | 6 +++++- rtl/axixclk.v | 4 ++++ rtl/easyaxil.v | 4 ++++ rtl/sfifo.v | 2 +- rtl/sfifothresh.v | 4 ++++ rtl/skidbuffer.v | 2 +- rtl/wbarbiter.v | 2 +- rtl/wbsafety.v | 4 ++++ 18 files changed, 49 insertions(+), 15 deletions(-) diff --git a/rtl/afifo.v b/rtl/afifo.v index afb8420..473347c 100644 --- a/rtl/afifo.v +++ b/rtl/afifo.v @@ -632,3 +632,4 @@ module afifo( end endgenerate `endif endmodule +`default_nettype wire diff --git a/rtl/axi_addr.v b/rtl/axi_addr.v index cf4ec12..73942c2 100644 --- a/rtl/axi_addr.v +++ b/rtl/axi_addr.v @@ -39,7 +39,7 @@ //////////////////////////////////////////////////////////////////////////////// // // -//`default_nettype none +`default_nettype none // // module axi_addr(i_last_addr, diff --git a/rtl/axidma.v b/rtl/axidma.v index 928b200..1b56f91 100644 --- a/rtl/axidma.v +++ b/rtl/axidma.v @@ -1869,3 +1869,7 @@ module axidma #( // None (currently) `endif endmodule +`ifndef YOSYS +`default_nettype wire +`endif + diff --git a/rtl/axidouble.v b/rtl/axidouble.v index 9fa14f3..42e7057 100644 --- a/rtl/axidouble.v +++ b/rtl/axidouble.v @@ -1198,3 +1198,4 @@ module axidouble #( end endgenerate `endif endmodule +`default_nettype wire diff --git a/rtl/axildouble.v b/rtl/axildouble.v index e5f7be2..b8fc88b 100644 --- a/rtl/axildouble.v +++ b/rtl/axildouble.v @@ -735,6 +735,6 @@ module axildouble #( cover((cvr_writes > 4) && (cvr_reads > 4)); `endif endmodule -// `ifndef YOSYS -// `default_nettype wire -// `endif +`ifndef YOSYS +`default_nettype wire +`endif diff --git a/rtl/axilrd2wbsp.v b/rtl/axilrd2wbsp.v index be9b762..635b13f 100644 --- a/rtl/axilrd2wbsp.v +++ b/rtl/axilrd2wbsp.v @@ -32,7 +32,7 @@ //////////////////////////////////////////////////////////////////////////////// // // -//`default_nettype none +`default_nettype none // module axilrd2wbsp(i_clk, i_axi_reset_n, // AXI read address channel signals diff --git a/rtl/axilsingle.v b/rtl/axilsingle.v index d2cab8f..645d037 100644 --- a/rtl/axilsingle.v +++ b/rtl/axilsingle.v @@ -714,6 +714,6 @@ module axilsingle #( cover((cvr_writes > 4) && (cvr_reads > 4)); `endif endmodule -// `ifndef YOSYS -// `default_nettype wire -// `endif +`ifndef YOSYS +`default_nettype wire +`endif diff --git a/rtl/axilwr2wbsp.v b/rtl/axilwr2wbsp.v index 55a0ae3..b9cc152 100644 --- a/rtl/axilwr2wbsp.v +++ b/rtl/axilwr2wbsp.v @@ -33,7 +33,7 @@ //////////////////////////////////////////////////////////////////////////////// // // -//`default_nettype none +`default_nettype none // module axilwr2wbsp(i_clk, i_axi_reset_n, // AXI write address channel signals diff --git a/rtl/axim2wbsp.v b/rtl/axim2wbsp.v index 1c723ec..fb8cbab 100644 --- a/rtl/axim2wbsp.v +++ b/rtl/axim2wbsp.v @@ -39,7 +39,7 @@ //////////////////////////////////////////////////////////////////////////////// // // -//`default_nettype none +`default_nettype none // module axim2wbsp #( parameter C_AXI_ID_WIDTH = 16, // The AXI id width used for R&W @@ -281,3 +281,7 @@ module axim2wbsp #( `ifdef FORMAL `endif endmodule +`ifndef YOSYS +`default_nettype wire +`endif + diff --git a/rtl/aximrd2wbsp.v b/rtl/aximrd2wbsp.v index c1436f6..6e6f5b7 100644 --- a/rtl/aximrd2wbsp.v +++ b/rtl/aximrd2wbsp.v @@ -44,7 +44,7 @@ //////////////////////////////////////////////////////////////////////////////// // // -//`default_nettype none +`default_nettype none // module aximrd2wbsp #( parameter C_AXI_ID_WIDTH = 6, // The AXI id width used for R&W @@ -602,3 +602,7 @@ module aximrd2wbsp #( `endif endmodule +`ifndef YOSYS +`default_nettype wire +`endif + diff --git a/rtl/aximwr2wbsp.v b/rtl/aximwr2wbsp.v index 6670b5e..1af778c 100644 --- a/rtl/aximwr2wbsp.v +++ b/rtl/aximwr2wbsp.v @@ -33,7 +33,7 @@ //////////////////////////////////////////////////////////////////////////////// // // -//`default_nettype none +`default_nettype none // // module aximwr2wbsp #( @@ -569,3 +569,7 @@ module aximwr2wbsp #( cover(cvr_wrid_bursts == 4); `endif endmodule +`ifndef YOSYS +`default_nettype wire +`endif + diff --git a/rtl/axixclk.v b/rtl/axixclk.v index d362974..57ea252 100644 --- a/rtl/axixclk.v +++ b/rtl/axixclk.v @@ -307,3 +307,7 @@ module axixclk #( end endgenerate endmodule +`ifndef YOSYS +`default_nettype wire +`endif + diff --git a/rtl/easyaxil.v b/rtl/easyaxil.v index 9a46d2b..63188fe 100644 --- a/rtl/easyaxil.v +++ b/rtl/easyaxil.v @@ -440,3 +440,7 @@ module easyaxil #( // }}} `endif endmodule +`ifndef YOSYS +`default_nettype wire +`endif + diff --git a/rtl/sfifo.v b/rtl/sfifo.v index 54fa46c..189ad29 100644 --- a/rtl/sfifo.v +++ b/rtl/sfifo.v @@ -22,7 +22,7 @@ //////////////////////////////////////////////////////////////////////////////// // // -//`default_nettype none +`default_nettype none // module sfifo(i_clk, i_reset, i_wr, i_data, o_full, o_fill, i_rd, o_data, o_empty); parameter BW=8; // Byte/data width diff --git a/rtl/sfifothresh.v b/rtl/sfifothresh.v index 7a010cf..33b754f 100644 --- a/rtl/sfifothresh.v +++ b/rtl/sfifothresh.v @@ -95,3 +95,7 @@ module sfifothresh(i_clk, i_reset, assert(o_int == (o_fill >= $past(i_threshold))); `endif endmodule +`ifndef YOSYS +`default_nettype wire +`endif + diff --git a/rtl/skidbuffer.v b/rtl/skidbuffer.v index afe155c..3fdaf0d 100644 --- a/rtl/skidbuffer.v +++ b/rtl/skidbuffer.v @@ -76,7 +76,7 @@ //////////////////////////////////////////////////////////////////////////////// // // -//`default_nettype none +`default_nettype none // module skidbuffer(i_clk, i_reset, i_valid, o_ready, i_data, diff --git a/rtl/wbarbiter.v b/rtl/wbarbiter.v index 5054663..9a834aa 100644 --- a/rtl/wbarbiter.v +++ b/rtl/wbarbiter.v @@ -54,7 +54,7 @@ //////////////////////////////////////////////////////////////////////////////// // // -//`default_nettype none +`default_nettype none // `define WBA_ALTERNATING // diff --git a/rtl/wbsafety.v b/rtl/wbsafety.v index 3699a89..1a91e6d 100644 --- a/rtl/wbsafety.v +++ b/rtl/wbsafety.v @@ -523,3 +523,7 @@ module wbsafety(i_clk, i_reset, `endif endmodule +`ifndef YOSYS +`default_nettype wire +`endif + From 64f874159fdd1c169900dfcbd0d5802a3b10d926 Mon Sep 17 00:00:00 2001 From: Tomasz Motylewski Date: Tue, 28 Jul 2020 15:51:05 +0200 Subject: [PATCH 04/12] added X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM CYC" to module axim2wbsp --- rtl/axim2wbsp.v | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/rtl/axim2wbsp.v b/rtl/axim2wbsp.v index fb8cbab..c2bd27e 100644 --- a/rtl/axim2wbsp.v +++ b/rtl/axim2wbsp.v @@ -106,16 +106,16 @@ module axim2wbsp #( // We'll share the clock and the reset output wire o_reset, - output wire o_wb_cyc, - output wire o_wb_stb, - output wire o_wb_we, - output wire [(AW-1):0] o_wb_addr, - output wire [(C_AXI_DATA_WIDTH-1):0] o_wb_data, - output wire [(C_AXI_DATA_WIDTH/8-1):0] o_wb_sel, - input wire i_wb_stall, - input wire i_wb_ack, - input wire [(C_AXI_DATA_WIDTH-1):0] i_wb_data, - input wire i_wb_err + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM CYC" *) output wire o_wb_cyc, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM STB" *) output wire o_wb_stb, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM WE" *) output wire o_wb_we, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM ADR" *) output wire [(AW-1):0] o_wb_addr, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM DAT_MOSI" *) output wire [(C_AXI_DATA_WIDTH-1):0] o_wb_data, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM SEL" *) output wire [(C_AXI_DATA_WIDTH/8-1):0] o_wb_sel, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM STALL" *)input wire i_wb_stall, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM ACK" *) input wire i_wb_ack, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM DAT_MISO" *) input wire [(C_AXI_DATA_WIDTH-1):0] i_wb_data, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM ERR" *)input wire i_wb_err ); // // From ed01204dc42c188f130bfbb427d83d2b0731f315 Mon Sep 17 00:00:00 2001 From: Tomasz Motylewski Date: Sat, 1 Aug 2020 15:48:49 +0200 Subject: [PATCH 05/12] added X_INTERFACE_INFOattributes for automatic AXI bus detection in Vivado --- rtl/wbm2axilite.v | 21 +++++----- rtl/wbm2axisp.v | 98 ++++++++++++++++++++++++----------------------- 2 files changed, 61 insertions(+), 58 deletions(-) diff --git a/rtl/wbm2axilite.v b/rtl/wbm2axilite.v index 4909943..406ee5b 100644 --- a/rtl/wbm2axilite.v +++ b/rtl/wbm2axilite.v @@ -45,16 +45,17 @@ module wbm2axilite #( input wire i_reset, // // We'll share the clock and the reset - input wire i_wb_cyc, - input wire i_wb_stb, - input wire i_wb_we, - input wire [(AW-1):0] i_wb_addr, - input wire [(DW-1):0] i_wb_data, - input wire [(DW/8-1):0] i_wb_sel, - output wire o_wb_stall, - output reg o_wb_ack, - output reg [(DW-1):0] o_wb_data, - output reg o_wb_err, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS CYC" *) input wire i_wb_cyc, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS STB" *) input wire i_wb_stb, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS WE" *) input wire i_wb_we, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ADR" *) input wire [(AW-1):0] i_wb_addr, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS DAT_MOSI" *) input wire [(DW-1):0] i_wb_data, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS SEL" *) input wire [(DW/8-1):0] i_wb_sel, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS STALL" *) output reg o_wb_stall, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ACK" *) output reg o_wb_ack, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS DAT_MISO" *) output reg [(DW-1):0] o_wb_data, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ERR" *) output reg o_wb_err, + // // AXI write address channel signals output reg o_axi_awvalid, diff --git a/rtl/wbm2axisp.v b/rtl/wbm2axisp.v index b0a2511..9fbe574 100644 --- a/rtl/wbm2axisp.v +++ b/rtl/wbm2axisp.v @@ -60,67 +60,69 @@ module wbm2axisp #( parameter [C_AXI_ID_WIDTH-1:0] AXI_WRITE_ID = 1'b0, parameter LGFIFO = 6 ) ( - input wire i_clk, // System clock + (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_ACLK, ASSOCIATED_BUSIF M_AXI" *) + // , ASSOCIATED_RESET S_AXI_ARESETN, FREQ_HZ 80000000, PHASE 0.000" *) + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_ACLK CLK" *) input wire i_clk, // System clock input wire i_reset,// Reset signal,drives AXI rst // AXI write address channel signals - output reg o_axi_awvalid, // Write address valid - input wire i_axi_awready, // Slave is ready to accept - output wire [C_AXI_ID_WIDTH-1:0] o_axi_awid, // Write ID - output reg [C_AXI_ADDR_WIDTH-1:0] o_axi_awaddr, // Write address - output wire [7:0] o_axi_awlen, // Write Burst Length - output wire [2:0] o_axi_awsize, // Write Burst size - output wire [1:0] o_axi_awburst, // Write Burst type - output wire [0:0] o_axi_awlock, // Write lock type - output wire [3:0] o_axi_awcache, // Write Cache type - output wire [2:0] o_axi_awprot, // Write Protection type - output wire [3:0] o_axi_awqos, // Write Quality of Svc + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output reg o_axi_awvalid, // Write address valid + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) input wire i_axi_awready, // Slave is ready to accept + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *) output wire [C_AXI_ID_WIDTH-1:0] o_axi_awid, // Write ID + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output reg [C_AXI_ADDR_WIDTH-1:0] o_axi_awaddr, // Write address + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *) output wire [7:0] o_axi_awlen, // Write Burst Length + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *) output wire [2:0] o_axi_awsize, // Write Burst size + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *) output wire [1:0] o_axi_awburst, // Write Burst type + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *) output wire [0:0] o_axi_awlock, // Write lock type + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *) output wire [3:0] o_axi_awcache, // Write Cache type + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output wire [2:0] o_axi_awprot, // Write Protection type + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *) output wire [3:0] o_axi_awqos, // Write Quality of Svc // AXI write data channel signals - output reg o_axi_wvalid, // Write valid - input wire i_axi_wready, // Write data ready - output reg [C_AXI_DATA_WIDTH-1:0] o_axi_wdata, // Write data - output reg [C_AXI_DATA_WIDTH/8-1:0] o_axi_wstrb, // Write strobes - output wire o_axi_wlast, // Last write transaction + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) output reg o_axi_wvalid, // Write valid + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) input wire i_axi_wready, // Write data ready + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) output reg [C_AXI_DATA_WIDTH-1:0] o_axi_wdata, // Write data + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) output reg [C_AXI_DATA_WIDTH/8-1:0] o_axi_wstrb, // Write strobes + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *) output wire o_axi_wlast, // Last write transaction // AXI write response channel signals - input wire i_axi_bvalid, // Write reponse valid - output wire o_axi_bready, // Response ready - input wire [C_AXI_ID_WIDTH-1:0] i_axi_bid, // Response ID - input wire [1:0] i_axi_bresp, // Write response + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input wire i_axi_bvalid, // Write reponse valid + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output wire o_axi_bready, // Response ready + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *) input wire [C_AXI_ID_WIDTH-1:0] i_axi_bid, // Response ID + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) input wire [1:0] i_axi_bresp, // Write response // AXI read address channel signals - output reg o_axi_arvalid, // Read address valid - input wire i_axi_arready, // Read address ready - output wire [C_AXI_ID_WIDTH-1:0] o_axi_arid, // Read ID - output reg [C_AXI_ADDR_WIDTH-1:0] o_axi_araddr, // Read address - output wire [7:0] o_axi_arlen, // Read Burst Length - output wire [2:0] o_axi_arsize, // Read Burst size - output wire [1:0] o_axi_arburst, // Read Burst type - output wire [0:0] o_axi_arlock, // Read lock type - output wire [3:0] o_axi_arcache, // Read Cache type - output wire [2:0] o_axi_arprot, // Read Protection type - output wire [3:0] o_axi_arqos, // Read Protection type + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output reg o_axi_arvalid, // Read address valid + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input wire i_axi_arready, // Read address ready + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *) output wire [C_AXI_ID_WIDTH-1:0] o_axi_arid, // Read ID + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output reg [C_AXI_ADDR_WIDTH-1:0] o_axi_araddr, // Read address + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *) output wire [7:0] o_axi_arlen, // Read Burst Length + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *) output wire [2:0] o_axi_arsize, // Read Burst size + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *) output wire [1:0] o_axi_arburst, // Read Burst type + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *) output wire [0:0] o_axi_arlock, // Read lock type + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *) output wire [3:0] o_axi_arcache, // Read Cache type + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output wire [2:0] o_axi_arprot, // Read Protection type + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *) output wire [3:0] o_axi_arqos, // Read Protection type // AXI read data channel signals - input wire i_axi_rvalid, // Read reponse valid - output wire o_axi_rready, // Read Response ready - input wire [C_AXI_ID_WIDTH-1:0] i_axi_rid, // Response ID - input wire [C_AXI_DATA_WIDTH-1:0] i_axi_rdata, // Read data - input wire [1:0] i_axi_rresp, // Read response - input wire i_axi_rlast, // Read last + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input wire i_axi_rvalid, // Read reponse valid + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) output wire o_axi_rready, // Read Response ready + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *) input wire [C_AXI_ID_WIDTH-1:0] i_axi_rid, // Response ID + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input wire [C_AXI_DATA_WIDTH-1:0] i_axi_rdata, // Read data + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input wire [1:0] i_axi_rresp, // Read response + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *) input wire i_axi_rlast, // Read last // We'll share the clock and the reset - input wire i_wb_cyc, - input wire i_wb_stb, - input wire i_wb_we, - input wire [(AW-1):0] i_wb_addr, - input wire [(DW-1):0] i_wb_data, - input wire [(DW/8-1):0] i_wb_sel, - output reg o_wb_stall, - output reg o_wb_ack, - output reg [(DW-1):0] o_wb_data, - output reg o_wb_err + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS CYC" *) input wire i_wb_cyc, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS STB" *) input wire i_wb_stb, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS WE" *) input wire i_wb_we, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ADR" *) input wire [(AW-1):0] i_wb_addr, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS DAT_MOSI" *) input wire [(DW-1):0] i_wb_data, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS SEL" *) input wire [(DW/8-1):0] i_wb_sel, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS STALL" *) output reg o_wb_stall, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ACK" *) output reg o_wb_ack, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS DAT_MISO" *) output reg [(DW-1):0] o_wb_data, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ERR" *) output reg o_wb_err ); //***************************************************************************** From 750887ff6dcd570b6b823530b82f40512e6f60cd Mon Sep 17 00:00:00 2001 From: Tomasz Motylewski Date: Thu, 6 Aug 2020 09:18:06 +0200 Subject: [PATCH 06/12] added ifndef YOSYS default_wiretype to 2 files --- rtl/afifo.v | 3 +++ rtl/axidouble.v | 3 +++ 2 files changed, 6 insertions(+) diff --git a/rtl/afifo.v b/rtl/afifo.v index 473347c..2734c8d 100644 --- a/rtl/afifo.v +++ b/rtl/afifo.v @@ -632,4 +632,7 @@ module afifo( end endgenerate `endif endmodule +`ifndef YOSYS `default_nettype wire +`endif + diff --git a/rtl/axidouble.v b/rtl/axidouble.v index 42e7057..b7ebb4c 100644 --- a/rtl/axidouble.v +++ b/rtl/axidouble.v @@ -1198,4 +1198,7 @@ module axidouble #( end endgenerate `endif endmodule +`ifndef YOSYS `default_nettype wire +`endif + From 3d1bc5d8e72f3be2a769ba52de5b19cc17aa7fc8 Mon Sep 17 00:00:00 2001 From: Tomasz Motylewski Date: Fri, 7 Aug 2020 12:30:32 +0200 Subject: [PATCH 07/12] propagated AXI_LSBS to submodules because I need to override it --- rtl/axim2wbsp.v | 2 ++ rtl/aximrd2wbsp.v | 2 +- rtl/aximwr2wbsp.v | 2 +- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/rtl/axim2wbsp.v b/rtl/axim2wbsp.v index c2bd27e..2760ca6 100644 --- a/rtl/axim2wbsp.v +++ b/rtl/axim2wbsp.v @@ -138,6 +138,7 @@ module axim2wbsp #( .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH), .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH), .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH), + .AXI_LSBS(AXI_LSBS), .LGFIFO(LGFIFO)) axi_write_decoder( .S_AXI_ACLK(S_AXI_ACLK), .S_AXI_ARESETN(S_AXI_ARESETN), @@ -194,6 +195,7 @@ module axim2wbsp #( .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH), .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH), .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH), + .AXI_LSBS(AXI_LSBS), .LGFIFO(LGFIFO)) axi_read_decoder( .S_AXI_ACLK(S_AXI_ACLK), .S_AXI_ARESETN(S_AXI_ARESETN), diff --git a/rtl/aximrd2wbsp.v b/rtl/aximrd2wbsp.v index 6e6f5b7..fde27fe 100644 --- a/rtl/aximrd2wbsp.v +++ b/rtl/aximrd2wbsp.v @@ -51,7 +51,7 @@ module aximrd2wbsp #( // This is an int between 1-16 parameter C_AXI_DATA_WIDTH = 32,// Width of the AXI R&W data parameter C_AXI_ADDR_WIDTH = 28, // AXI Address width - localparam AXI_LSBS = $clog2(C_AXI_DATA_WIDTH)-3, + parameter AXI_LSBS = $clog2(C_AXI_DATA_WIDTH)-3, parameter AW = C_AXI_ADDR_WIDTH - AXI_LSBS, // AXI Address width parameter LGFIFO = 3, parameter [0:0] OPT_SWAP_ENDIANNESS = 0 diff --git a/rtl/aximwr2wbsp.v b/rtl/aximwr2wbsp.v index 1af778c..2d7afa6 100644 --- a/rtl/aximwr2wbsp.v +++ b/rtl/aximwr2wbsp.v @@ -42,7 +42,7 @@ module aximwr2wbsp #( parameter C_AXI_DATA_WIDTH = 32,// Width of the AXI R&W data parameter C_AXI_ADDR_WIDTH = 28, // AXI Address width parameter [0:0] OPT_SWAP_ENDIANNESS = 1'b1, // Lil to Big Endian swap - localparam AXI_LSBS = $clog2(C_AXI_DATA_WIDTH)-3, + parameter AXI_LSBS = $clog2(C_AXI_DATA_WIDTH)-3, localparam AW = C_AXI_ADDR_WIDTH-AXI_LSBS, localparam DW = C_AXI_DATA_WIDTH, From 75db1f242595af5c351d09139040fa0f5912a263 Mon Sep 17 00:00:00 2001 From: Tomasz Motylewski Date: Fri, 7 Aug 2020 12:38:21 +0200 Subject: [PATCH 08/12] Added IP-XACT definitions of Wishbone3 and Wishbone4 bus. Added X_INTERFACE_INFO wishbone4 to wbp2classic to use the module in Xilinx Vivado block design --- interfaces/wishbone.xml | 17 ++ interfaces/wishbone4.xml | 18 ++ interfaces/wishbone4_rtl.xml | 311 +++++++++++++++++++++++++++++++++++ interfaces/wishbone_rtl.xml | 223 +++++++++++++++++++++++++ rtl/wbp2classic.v | 63 +++---- 5 files changed, 602 insertions(+), 30 deletions(-) create mode 100644 interfaces/wishbone.xml create mode 100644 interfaces/wishbone4.xml create mode 100644 interfaces/wishbone4_rtl.xml create mode 100644 interfaces/wishbone_rtl.xml diff --git a/interfaces/wishbone.xml b/interfaces/wishbone.xml new file mode 100644 index 0000000..fcee99f --- /dev/null +++ b/interfaces/wishbone.xml @@ -0,0 +1,17 @@ + + + opencores.org + bus + wishbone + 3.0 + false + false + 1 + 1 + wishbone from opencores.org b3.pdf + + + wishbone + + + diff --git a/interfaces/wishbone4.xml b/interfaces/wishbone4.xml new file mode 100644 index 0000000..0ac6319 --- /dev/null +++ b/interfaces/wishbone4.xml @@ -0,0 +1,18 @@ + + + opencores.org + bus + wishbone4 + 4.0 + false + false + + 1 + 1 + https://opencores.org/howto/wishbone 2010-06-22 Rev.B4 specs. + + + wishbone4 + + + diff --git a/interfaces/wishbone4_rtl.xml b/interfaces/wishbone4_rtl.xml new file mode 100644 index 0000000..1e840e0 --- /dev/null +++ b/interfaces/wishbone4_rtl.xml @@ -0,0 +1,311 @@ + + + opencores.org + bus + wishbone4_rtl + 4.0 + + + + CYC + cycle in progress + + + true + + + required + 1 + + + required + 1 + in + + 0 + + + + addr + + + + + STB + data transfer strobe RD or WR + + + required + 1 + + + required + 1 + in + + 0 + + + + WE + WriteEnable + + + 1 + + + 1 + in + + 0 + + + + wr + + + + + SEL + select sub-words e.g. bytes for writing + + + + in + + 65535 + + + + wr + + + + + ACK + ACK master input + + + required + 1 + in + + + required + + 0 + + + + ADR + Address bus + + + true + + + required + + + in + + 0 + + + + addr + + + + + DAT_MISO + DAT_I master O slave + + + true + + + in + + 0 + + + + rd + + + + + DAT_MOSI + DAT_O master I slave + + + in + + + 0 + + + + wr + + + + + LOCK + uninterruptible access + + + 1 + + + 1 + in + + 0 + + + + ERR + slave terminates access with error + + + 1 + in + + + 1 + + 0 + + + + RTY + slave not ready, access terminated + + + 1 + in + + + 1 + + 0 + + + + TGD_MISO + information that is associated with the data input array [DAT_I()], and is qualified by signal [STB_I] + + + in + + 0 + + + + TGD_MOSI + info about data output array [DAT_O()], and is qualified by signal [STB_O] + + + true + + + in + + 0 + + + + TGA + address lines [ADR_O()] info + + + true + + + in + + 0 + + + + addr + + + + + TGC + bus cycles, qualified by [CYC_O] + + + in + + 0 + + + + STALL + slave signals that it can not accept more transfer + + + 1 + in + + + 1 + + 0 + + + + CTI + Cycle Type Identifier + + + true + + + 3 + + + 3 + in + + 0 + + + + addr + + + + + BTE + Burst Type Extension + + + true + + + 2 + + + 2 + in + + 0 + + + + addr + + + + + + + wishbone4 + + + diff --git a/interfaces/wishbone_rtl.xml b/interfaces/wishbone_rtl.xml new file mode 100644 index 0000000..038c0b9 --- /dev/null +++ b/interfaces/wishbone_rtl.xml @@ -0,0 +1,223 @@ + + + opencores.org + bus + wishbone_rtl + 3.0 + + + + CYC + cycle in progress + + + true + + + required + 1 + + + required + 1 + in + + 0 + + + + STB + data transfer strobe RD or WR + + + required + 1 + + + required + 1 + in + + 0 + + + + WE + WriteEnable + + + 1 + + + 1 + in + + 0 + + + + SEL + select sub-words e.g. bytes for writing + + + + in + + 65535 + + + + ACK + ACK master input + + + required + 1 + in + + + required + + 0 + + + + ADR + Address bus + + + true + + + required + + + in + + 0 + + + + addr + + + + + DAT_MISO + DAT_I master O slave + + + true + + + in + + 0 + + + + DAT_MOSI + DAT_O master I slave + + + in + + + 0 + + + + LOCK + uninterruptible access + + + 1 + + + 1 + in + + 0 + + + + ERR + slave terminates access with error + + + 1 + in + + + 1 + + 0 + + + + RTY + slave not ready, access terminated + + + 1 + in + + + 1 + + 0 + + + + TGD_MISO + information that is associated with the data input array [DAT_I()], and is qualified by signal [STB_I] + + + in + + 0 + + + + TGD_MOSI + info about data output array [DAT_O()], and is qualified by signal [STB_O] + + + true + + + in + + 0 + + + + TGA + address lines [ADR_O()] info + + + true + + + in + + 0 + + + + TGC + bus cycles, qualified by [CYC_O] + + + in + + 0 + + + + + + wishbone + + + diff --git a/rtl/wbp2classic.v b/rtl/wbp2classic.v index 0e465f1..d98eef6 100644 --- a/rtl/wbp2classic.v +++ b/rtl/wbp2classic.v @@ -34,38 +34,41 @@ // `default_nettype none // -module wbp2classic(i_clk, i_reset, - i_mcyc, i_mstb, i_mwe, i_maddr, i_mdata, i_msel, - o_mstall, o_mack, o_mdata, o_merr, - o_scyc, o_sstb, o_swe, o_saddr, o_sdata, o_ssel, - i_sack, i_sdata, i_serr, - o_scti, o_sbte); - parameter AW = 12, - DW = 32; - // - input wire i_clk, i_reset; +module wbp2classic #( + parameter AW = 12, + DW = 32 + ) ( + input wire i_clk, i_reset, + // + // Incoming WB pipelined port WB4 slave interface + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS CYC" *) input wire i_mcyc, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS STB" *) input wire i_mstb, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS WE" *) input wire i_mwe, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ADR" *) input wire [(AW-1):0] i_maddr, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS DAT_MOSI" *) input wire [(DW-1):0] i_mdata, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS SEL" *) input wire [(DW/8-1):0] i_msel, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS STALL" *) output reg o_mstall, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ACK" *) output reg o_mack, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS DAT_MISO" *) output reg [(DW-1):0] o_mdata, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ERR" *) output reg o_merr, + + // We'll share the clock and the reset + // - // Incoming WB pipelined port - input wire i_mcyc, i_mstb, i_mwe; - input wire [AW-1:0] i_maddr; - input wire [DW-1:0] i_mdata; - input wire [DW/8-1:0] i_msel; - output reg o_mstall, o_mack; - output reg [DW-1:0] o_mdata; - output reg o_merr; - // - // Outgoing WB classic port - output reg o_scyc, o_sstb, o_swe; - output reg [AW-1:0] o_saddr; - output reg [DW-1:0] o_sdata; - output reg [DW/8-1:0] o_ssel; - input wire i_sack; - input wire [DW-1:0] i_sdata; - input wire i_serr; + // Outgoing WB classic port master ( for convinience labelled as WB4, later use separate interface definition for WB3 classic) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM CYC" *) output reg o_scyc, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM STB" *) output reg o_sstb, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM WE" *) output reg o_swe, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM ADR" *) output reg [(AW-1):0] o_saddr, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM DAT_MOSI" *) output reg [(DW-1):0] o_sdata, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM SEL" *) output reg [(DW/8-1):0] o_ssel, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM ACK" *) input wire i_sack, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM DAT_MISO" *) input wire [(DW-1):0] i_sdata, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM ERR" *) input wire i_serr, // Extra wires, not necessarily necessary for WB/B3 - output reg [2:0] o_scti; - output reg [1:0] o_sbte; - + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM CTI" *) output reg [2:0] o_scti, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM BTE" *) output reg [1:0] o_sbte +); // // returned = whether we've received our return value or not. reg returned; From 57414d318e2b441587bae85768357980a533e611 Mon Sep 17 00:00:00 2001 From: Tomasz Motylewski Date: Tue, 11 Aug 2020 09:59:42 +0200 Subject: [PATCH 09/12] prepared for upstream merge, cleaned up module interfaces --- rtl/axilsingle.v | 6 +++--- rtl/axim2wbsp.v | 29 +++++++++++++++++------------ rtl/aximrd2wbsp.v | 2 +- rtl/aximwr2wbsp.v | 2 +- rtl/wbm2axilite.v | 2 +- rtl/wbm2axisp.v | 9 +++++++-- rtl/wbp2classic.v | 22 +++++++++++----------- 7 files changed, 41 insertions(+), 31 deletions(-) diff --git a/rtl/axilsingle.v b/rtl/axilsingle.v index 645d037..d42b39b 100644 --- a/rtl/axilsingle.v +++ b/rtl/axilsingle.v @@ -112,11 +112,11 @@ module axilsingle #( parameter NS = 16, // parameter integer C_AXI_DATA_WIDTH = 32, - parameter integer C_AXI_ADDR_WIDTH = $clog2(NS)+$clog2(C_AXI_DATA_WIDTH)-3, + localparam integer C_AXI_ADDR_WIDTH = $clog2(NS)+$clog2(C_AXI_DATA_WIDTH)-3, // // AW, and DW, are short-hand abbreviations used locally. - parameter AW = C_AXI_ADDR_WIDTH, - parameter DW = C_AXI_DATA_WIDTH, + localparam AW = C_AXI_ADDR_WIDTH, + localparam DW = C_AXI_DATA_WIDTH, // // LGFLEN specifies the log (based two) of the number of // transactions that may need to be held outstanding internally. diff --git a/rtl/axim2wbsp.v b/rtl/axim2wbsp.v index 2760ca6..2efa9dd 100644 --- a/rtl/axim2wbsp.v +++ b/rtl/axim2wbsp.v @@ -42,20 +42,21 @@ `default_nettype none // module axim2wbsp #( - parameter C_AXI_ID_WIDTH = 16, // The AXI id width used for R&W + parameter C_AXI_ID_WIDTH = 2, // The AXI id width used for R&W // This is an int between 1-16 parameter C_AXI_DATA_WIDTH = 32,// Width of the AXI R&W data - parameter C_AXI_ADDR_WIDTH = 16, // AXI Address width - parameter AXI_LSBS = $clog2(C_AXI_DATA_WIDTH)-3, - parameter DW = C_AXI_DATA_WIDTH, - parameter AW = C_AXI_ADDR_WIDTH - AXI_LSBS, + parameter C_AXI_ADDR_WIDTH = 28, // AXI Address width + parameter AXI_LSBS = $clog2(C_AXI_DATA_WIDTH)-3, // leave it calculated, unless AXI narrow transfers need to be supported + parameter DW = C_AXI_DATA_WIDTH, // leave it calculated + parameter AW = C_AXI_ADDR_WIDTH - AXI_LSBS, // leave it calculated parameter LGFIFO = 5, + parameter [0:0] OPT_SWAP_ENDIANNESS = 1'b0, parameter [0:0] OPT_READONLY = 1'b0, parameter [0:0] OPT_WRITEONLY = 1'b0 ) ( - // + // names are matching AXI spec, therefore X_INTERFACE_INFO not needed input wire S_AXI_ACLK, // System clock - input wire S_AXI_ARESETN, + input wire S_AXI_ARESETN, // reset, active low // AXI write address channel signals input wire S_AXI_AWVALID, // Write address valid @@ -104,18 +105,20 @@ module axim2wbsp #( output wire S_AXI_RLAST, // Read last output wire [1:0] S_AXI_RRESP, // Read response - // We'll share the clock and the reset - output wire o_reset, + // Wishbone4 pipelined master. We'll share the clock and output the active-high reset + (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME o_reset, POLARITY ACTIVE_HIGH" *) + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 o_reset RST" *) output wire o_reset, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM CYC" *) output wire o_wb_cyc, (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM STB" *) output wire o_wb_stb, (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM WE" *) output wire o_wb_we, (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM ADR" *) output wire [(AW-1):0] o_wb_addr, (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM DAT_MOSI" *) output wire [(C_AXI_DATA_WIDTH-1):0] o_wb_data, (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM SEL" *) output wire [(C_AXI_DATA_WIDTH/8-1):0] o_wb_sel, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM STALL" *)input wire i_wb_stall, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM STALL" *) input wire i_wb_stall, (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM ACK" *) input wire i_wb_ack, (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM DAT_MISO" *) input wire [(C_AXI_DATA_WIDTH-1):0] i_wb_data, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM ERR" *)input wire i_wb_err + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM ERR" *) input wire i_wb_err ); // // @@ -138,6 +141,7 @@ module axim2wbsp #( .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH), .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH), .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH), + .OPT_SWAP_ENDIANNESS(OPT_SWAP_ENDIANNESS), .AXI_LSBS(AXI_LSBS), .LGFIFO(LGFIFO)) axi_write_decoder( @@ -196,7 +200,8 @@ module axim2wbsp #( .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH), .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH), .AXI_LSBS(AXI_LSBS), - .LGFIFO(LGFIFO)) + .LGFIFO(LGFIFO), + .OPT_SWAP_ENDIANNESS(OPT_SWAP_ENDIANNESS)) axi_read_decoder( .S_AXI_ACLK(S_AXI_ACLK), .S_AXI_ARESETN(S_AXI_ARESETN), // diff --git a/rtl/aximrd2wbsp.v b/rtl/aximrd2wbsp.v index fde27fe..f2be9b2 100644 --- a/rtl/aximrd2wbsp.v +++ b/rtl/aximrd2wbsp.v @@ -51,7 +51,7 @@ module aximrd2wbsp #( // This is an int between 1-16 parameter C_AXI_DATA_WIDTH = 32,// Width of the AXI R&W data parameter C_AXI_ADDR_WIDTH = 28, // AXI Address width - parameter AXI_LSBS = $clog2(C_AXI_DATA_WIDTH)-3, + parameter AXI_LSBS = $clog2(C_AXI_DATA_WIDTH)-3, // change it only to support narrow transfers parameter AW = C_AXI_ADDR_WIDTH - AXI_LSBS, // AXI Address width parameter LGFIFO = 3, parameter [0:0] OPT_SWAP_ENDIANNESS = 0 diff --git a/rtl/aximwr2wbsp.v b/rtl/aximwr2wbsp.v index 027f22d..2f672eb 100644 --- a/rtl/aximwr2wbsp.v +++ b/rtl/aximwr2wbsp.v @@ -43,7 +43,7 @@ module aximwr2wbsp #( parameter C_AXI_ADDR_WIDTH = 28, // AXI Address width parameter [0:0] OPT_SWAP_ENDIANNESS = 1'b0, // Lil to Big Endian swap - parameter AXI_LSBS = $clog2(C_AXI_DATA_WIDTH)-3, + parameter AXI_LSBS = $clog2(C_AXI_DATA_WIDTH)-3, // change it only to support narrow transfers localparam AW = C_AXI_ADDR_WIDTH-AXI_LSBS, localparam DW = C_AXI_DATA_WIDTH, diff --git a/rtl/wbm2axilite.v b/rtl/wbm2axilite.v index 52fd433..489a7c8 100644 --- a/rtl/wbm2axilite.v +++ b/rtl/wbm2axilite.v @@ -51,7 +51,7 @@ module wbm2axilite #( (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ADR" *) input wire [(AW-1):0] i_wb_addr, (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS DAT_MOSI" *) input wire [(DW-1):0] i_wb_data, (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS SEL" *) input wire [(DW/8-1):0] i_wb_sel, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS STALL" *) output reg o_wb_stall, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS STALL" *) output wire o_wb_stall, (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ACK" *) output reg o_wb_ack, (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS DAT_MISO" *) output reg [(DW-1):0] o_wb_data, (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ERR" *) output reg o_wb_err, diff --git a/rtl/wbm2axisp.v b/rtl/wbm2axisp.v index b0bef3f..a10dbaa 100644 --- a/rtl/wbm2axisp.v +++ b/rtl/wbm2axisp.v @@ -67,9 +67,10 @@ module wbm2axisp #( ) ( // {{{ (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_ACLK, ASSOCIATED_BUSIF M_AXI" *) - // , ASSOCIATED_RESET S_AXI_ARESETN, FREQ_HZ 80000000, PHASE 0.000" *) (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_ACLK CLK" *) input wire i_clk, // System clock - input wire i_reset,// Reset signal,drives AXI rst + + (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_HIGH" *) + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 i_reset RST" *) input wire i_reset,// Reset signal active high, inverted drives AXI rst // AXI write address channel signals (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output reg o_axi_awvalid, // Write address valid @@ -1147,3 +1148,7 @@ module wbm2axisp #( `endif // FORMAL // }}} endmodule +`ifndef YOSYS +`default_nettype wire +`endif + diff --git a/rtl/wbp2classic.v b/rtl/wbp2classic.v index d98eef6..8bfba66 100644 --- a/rtl/wbp2classic.v +++ b/rtl/wbp2classic.v @@ -56,18 +56,18 @@ module wbp2classic #( // // Outgoing WB classic port master ( for convinience labelled as WB4, later use separate interface definition for WB3 classic) - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM CYC" *) output reg o_scyc, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM STB" *) output reg o_sstb, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM WE" *) output reg o_swe, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM ADR" *) output reg [(AW-1):0] o_saddr, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM DAT_MOSI" *) output reg [(DW-1):0] o_sdata, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM SEL" *) output reg [(DW/8-1):0] o_ssel, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM ACK" *) input wire i_sack, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM DAT_MISO" *) input wire [(DW-1):0] i_sdata, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM ERR" *) input wire i_serr, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM CYC" *) output reg o_scyc, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM STB" *) output reg o_sstb, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM WE" *) output reg o_swe, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM ADR" *) output reg [(AW-1):0] o_saddr, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM DAT_MOSI" *) output reg [(DW-1):0] o_sdata, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM SEL" *) output reg [(DW/8-1):0] o_ssel, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM ACK" *) input wire i_sack, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM DAT_MISO" *) input wire [(DW-1):0] i_sdata, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM ERR" *) input wire i_serr, // Extra wires, not necessarily necessary for WB/B3 - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM CTI" *) output reg [2:0] o_scti, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM BTE" *) output reg [1:0] o_sbte + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM CTI" *) output reg [2:0] o_scti, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM BTE" *) output reg [1:0] o_sbte ); // // returned = whether we've received our return value or not. From bdc512567936194deb5486bd07a34981a673110e Mon Sep 17 00:00:00 2001 From: Tomasz Motylewski Date: Thu, 13 Aug 2020 14:00:32 +0200 Subject: [PATCH 10/12] split lines with X_INTERFACE_INFO as requested for upstream merge --- rtl/axim2wbsp.v | 33 +++++++---- rtl/wbm2axilite.v | 55 +++++++++++++---- rtl/wbm2axisp.v | 147 ++++++++++++++++++++++++++++++---------------- rtl/wbp2classic.v | 73 +++++++++++++++-------- 4 files changed, 214 insertions(+), 94 deletions(-) diff --git a/rtl/axim2wbsp.v b/rtl/axim2wbsp.v index 2efa9dd..022eba9 100644 --- a/rtl/axim2wbsp.v +++ b/rtl/axim2wbsp.v @@ -107,18 +107,29 @@ module axim2wbsp #( // Wishbone4 pipelined master. We'll share the clock and output the active-high reset (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME o_reset, POLARITY ACTIVE_HIGH" *) - (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 o_reset RST" *) output wire o_reset, + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 o_reset RST" *) + output wire o_reset, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM CYC" *) output wire o_wb_cyc, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM STB" *) output wire o_wb_stb, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM WE" *) output wire o_wb_we, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM ADR" *) output wire [(AW-1):0] o_wb_addr, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM DAT_MOSI" *) output wire [(C_AXI_DATA_WIDTH-1):0] o_wb_data, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM SEL" *) output wire [(C_AXI_DATA_WIDTH/8-1):0] o_wb_sel, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM STALL" *) input wire i_wb_stall, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM ACK" *) input wire i_wb_ack, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM DAT_MISO" *) input wire [(C_AXI_DATA_WIDTH-1):0] i_wb_data, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM ERR" *) input wire i_wb_err + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM CYC" *) + output wire o_wb_cyc, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM STB" *) + output wire o_wb_stb, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM WE" *) + output wire o_wb_we, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM ADR" *) + output wire [(AW-1):0] o_wb_addr, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM DAT_MOSI" *) + output wire [(C_AXI_DATA_WIDTH-1):0] o_wb_data, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM SEL" *) + output wire [(C_AXI_DATA_WIDTH/8-1):0] o_wb_sel, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM STALL" *) + input wire i_wb_stall, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM ACK" *) + input wire i_wb_ack, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM DAT_MISO" *) + input wire [(C_AXI_DATA_WIDTH-1):0] i_wb_data, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM ERR" *) + input wire i_wb_err ); // // diff --git a/rtl/wbm2axilite.v b/rtl/wbm2axilite.v index 489a7c8..0fd02b8 100644 --- a/rtl/wbm2axilite.v +++ b/rtl/wbm2axilite.v @@ -41,49 +41,82 @@ module wbm2axilite #( localparam DW = C_AXI_DATA_WIDTH,// Wishbone data width localparam AW = C_AXI_ADDR_WIDTH-2// WB addr width (log wordsize) ) ( + (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME i_clk, ASSOCIATED_BUSIF WBS:M_AXI" *) + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 i_clk CLK" *) input wire i_clk, + (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_HIGH" *) + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 i_reset RST" *) input wire i_reset, // // We'll share the clock and the reset - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS CYC" *) input wire i_wb_cyc, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS STB" *) input wire i_wb_stb, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS WE" *) input wire i_wb_we, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ADR" *) input wire [(AW-1):0] i_wb_addr, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS DAT_MOSI" *) input wire [(DW-1):0] i_wb_data, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS SEL" *) input wire [(DW/8-1):0] i_wb_sel, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS STALL" *) output wire o_wb_stall, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ACK" *) output reg o_wb_ack, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS DAT_MISO" *) output reg [(DW-1):0] o_wb_data, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ERR" *) output reg o_wb_err, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS CYC" *) + input wire i_wb_cyc, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS STB" *) + input wire i_wb_stb, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS WE" *) + input wire i_wb_we, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ADR" *) + input wire [(AW-1):0] i_wb_addr, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS DAT_MOSI" *) + input wire [(DW-1):0] i_wb_data, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS SEL" *) + input wire [(DW/8-1):0] i_wb_sel, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS STALL" *) + output wire o_wb_stall, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ACK" *) + output reg o_wb_ack, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS DAT_MISO" *) + output reg [(DW-1):0] o_wb_data, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ERR" *) + output reg o_wb_err, // // AXI write address channel signals + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output reg o_axi_awvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) input wire i_axi_awready, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output reg [C_AXI_ADDR_WIDTH-1:0] o_axi_awaddr, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output wire [2:0] o_axi_awprot, // // AXI write data channel signals + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) output reg o_axi_wvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) input wire i_axi_wready, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) output reg [C_AXI_DATA_WIDTH-1:0] o_axi_wdata, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) output reg [C_AXI_DATA_WIDTH/8-1:0] o_axi_wstrb, // // AXI write response channel signals + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input wire i_axi_bvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output wire o_axi_bready, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) input wire [1:0] i_axi_bresp, // // AXI read address channel signals + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output reg o_axi_arvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input wire i_axi_arready, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output reg [C_AXI_ADDR_WIDTH-1:0] o_axi_araddr, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output wire [2:0] o_axi_arprot, // - // AXI read data channel signals + // AXI read data channel signals + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input wire i_axi_rvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) output wire o_axi_rready, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input wire [C_AXI_DATA_WIDTH-1:0] i_axi_rdata, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input wire [1:0] i_axi_rresp ); diff --git a/rtl/wbm2axisp.v b/rtl/wbm2axisp.v index a10dbaa..baccb00 100644 --- a/rtl/wbm2axisp.v +++ b/rtl/wbm2axisp.v @@ -67,69 +67,118 @@ module wbm2axisp #( ) ( // {{{ (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_ACLK, ASSOCIATED_BUSIF M_AXI" *) - (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_ACLK CLK" *) input wire i_clk, // System clock + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_ACLK CLK" *) + input wire i_clk, // System clock (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_HIGH" *) - (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 i_reset RST" *) input wire i_reset,// Reset signal active high, inverted drives AXI rst + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 i_reset RST" *) + input wire i_reset,// Reset signal active high, inverted drives AXI rst // AXI write address channel signals - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output reg o_axi_awvalid, // Write address valid - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) input wire i_axi_awready, // Slave is ready to accept - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *) output wire [C_AXI_ID_WIDTH-1:0] o_axi_awid, // Write ID - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output reg [C_AXI_ADDR_WIDTH-1:0] o_axi_awaddr, // Write address - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *) output wire [7:0] o_axi_awlen, // Write Burst Length - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *) output wire [2:0] o_axi_awsize, // Write Burst size - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *) output wire [1:0] o_axi_awburst, // Write Burst type - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *) output wire [0:0] o_axi_awlock, // Write lock type - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *) output wire [3:0] o_axi_awcache, // Write Cache type - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output wire [2:0] o_axi_awprot, // Write Protection type - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *) output wire [3:0] o_axi_awqos, // Write Quality of Svc + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) + output reg o_axi_awvalid, // Write address valid + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) + input wire i_axi_awready, // Slave is ready to accept + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *) + output wire [C_AXI_ID_WIDTH-1:0] o_axi_awid, // Write ID + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) + output reg [C_AXI_ADDR_WIDTH-1:0] o_axi_awaddr, // Write address + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *) + output wire [7:0] o_axi_awlen, // Write Burst Length + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *) + output wire [2:0] o_axi_awsize, // Write Burst size + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *) + output wire [1:0] o_axi_awburst, // Write Burst type + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *) + output wire [0:0] o_axi_awlock, // Write lock type + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *) + output wire [3:0] o_axi_awcache, // Write Cache type + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) + output wire [2:0] o_axi_awprot, // Write Protection type + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *) + output wire [3:0] o_axi_awqos, // Write Quality of Svc // AXI write data channel signals - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) output reg o_axi_wvalid, // Write valid - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) input wire i_axi_wready, // Write data ready - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) output reg [C_AXI_DATA_WIDTH-1:0] o_axi_wdata, // Write data - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) output reg [C_AXI_DATA_WIDTH/8-1:0] o_axi_wstrb, // Write strobes - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *) output wire o_axi_wlast, // Last write transaction + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) + output reg o_axi_wvalid, // Write valid + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) + input wire i_axi_wready, // Write data ready + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) + output reg [C_AXI_DATA_WIDTH-1:0] o_axi_wdata, // Write data + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) + output reg [C_AXI_DATA_WIDTH/8-1:0] o_axi_wstrb, // Write strobes + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *) + output wire o_axi_wlast, // Last write transaction // AXI write response channel signals - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input wire i_axi_bvalid, // Write reponse valid - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output wire o_axi_bready, // Response ready - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *) input wire [C_AXI_ID_WIDTH-1:0] i_axi_bid, // Response ID - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) input wire [1:0] i_axi_bresp, // Write response + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) + input wire i_axi_bvalid, // Write reponse valid + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) + output wire o_axi_bready, // Response ready + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *) + input wire [C_AXI_ID_WIDTH-1:0] i_axi_bid, // Response ID + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) + input wire [1:0] i_axi_bresp, // Write response // AXI read address channel signals - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output reg o_axi_arvalid, // Read address valid - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input wire i_axi_arready, // Read address ready - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *) output wire [C_AXI_ID_WIDTH-1:0] o_axi_arid, // Read ID - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output reg [C_AXI_ADDR_WIDTH-1:0] o_axi_araddr, // Read address - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *) output wire [7:0] o_axi_arlen, // Read Burst Length - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *) output wire [2:0] o_axi_arsize, // Read Burst size - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *) output wire [1:0] o_axi_arburst, // Read Burst type - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *) output wire [0:0] o_axi_arlock, // Read lock type - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *) output wire [3:0] o_axi_arcache, // Read Cache type - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output wire [2:0] o_axi_arprot, // Read Protection type - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *) output wire [3:0] o_axi_arqos, // Read Protection type + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) + output reg o_axi_arvalid, // Read address valid + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) + input wire i_axi_arready, // Read address ready + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *) + output wire [C_AXI_ID_WIDTH-1:0] o_axi_arid, // Read ID + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) + output reg [C_AXI_ADDR_WIDTH-1:0] o_axi_araddr, // Read address + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *) + output wire [7:0] o_axi_arlen, // Read Burst Length + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *) + output wire [2:0] o_axi_arsize, // Read Burst size + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *) + output wire [1:0] o_axi_arburst, // Read Burst type + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *) + output wire [0:0] o_axi_arlock, // Read lock type + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *) + output wire [3:0] o_axi_arcache, // Read Cache type + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) + output wire [2:0] o_axi_arprot, // Read Protection type + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *) + output wire [3:0] o_axi_arqos, // Read Protection type // AXI read data channel signals - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input wire i_axi_rvalid, // Read reponse valid - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) output wire o_axi_rready, // Read Response ready - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *) input wire [C_AXI_ID_WIDTH-1:0] i_axi_rid, // Response ID - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input wire [C_AXI_DATA_WIDTH-1:0] i_axi_rdata, // Read data - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input wire [1:0] i_axi_rresp, // Read response - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *) input wire i_axi_rlast, // Read last + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) + input wire i_axi_rvalid, // Read reponse valid + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) + output wire o_axi_rready, // Read Response ready + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *) + input wire [C_AXI_ID_WIDTH-1:0] i_axi_rid, // Response ID + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) + input wire [C_AXI_DATA_WIDTH-1:0] i_axi_rdata, // Read data + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) + input wire [1:0] i_axi_rresp, // Read response + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *) + input wire i_axi_rlast, // Read last // We'll share the clock and the reset - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS CYC" *) input wire i_wb_cyc, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS STB" *) input wire i_wb_stb, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS WE" *) input wire i_wb_we, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ADR" *) input wire [(AW-1):0] i_wb_addr, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS DAT_MOSI" *) input wire [(DW-1):0] i_wb_data, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS SEL" *) input wire [(DW/8-1):0] i_wb_sel, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS STALL" *) output reg o_wb_stall, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ACK" *) output reg o_wb_ack, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS DAT_MISO" *) output reg [(DW-1):0] o_wb_data, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ERR" *) output reg o_wb_err + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS CYC" *) + input wire i_wb_cyc, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS STB" *) + input wire i_wb_stb, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS WE" *) + input wire i_wb_we, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ADR" *) + input wire [(AW-1):0] i_wb_addr, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS DAT_MOSI" *) + input wire [(DW-1):0] i_wb_data, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS SEL" *) + input wire [(DW/8-1):0] i_wb_sel, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS STALL" *) + output reg o_wb_stall, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ACK" *) + output reg o_wb_ack, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS DAT_MISO" *) + output reg [(DW-1):0] o_wb_data, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ERR" *) + output reg o_wb_err // }}} ); //////////////////////////////////////////////////////////////////////// diff --git a/rtl/wbp2classic.v b/rtl/wbp2classic.v index 8bfba66..f7a31b7 100644 --- a/rtl/wbp2classic.v +++ b/rtl/wbp2classic.v @@ -38,36 +38,63 @@ module wbp2classic #( parameter AW = 12, DW = 32 ) ( - input wire i_clk, i_reset, - // + + (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME i_clk, ASSOCIATED_BUSIF WBS:WBCM" *) + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 i_clk CLK" *) + input wire i_clk, + (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_HIGH" *) + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 i_reset RST" *) + input wire i_reset, + // // Incoming WB pipelined port WB4 slave interface - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS CYC" *) input wire i_mcyc, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS STB" *) input wire i_mstb, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS WE" *) input wire i_mwe, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ADR" *) input wire [(AW-1):0] i_maddr, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS DAT_MOSI" *) input wire [(DW-1):0] i_mdata, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS SEL" *) input wire [(DW/8-1):0] i_msel, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS STALL" *) output reg o_mstall, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ACK" *) output reg o_mack, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS DAT_MISO" *) output reg [(DW-1):0] o_mdata, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ERR" *) output reg o_merr, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS CYC" *) + input wire i_mcyc, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS STB" *) + input wire i_mstb, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS WE" *) + input wire i_mwe, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ADR" *) + input wire [(AW-1):0] i_maddr, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS DAT_MOSI" *) + input wire [(DW-1):0] i_mdata, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS SEL" *) + input wire [(DW/8-1):0] i_msel, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS STALL" *) + output reg o_mstall, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ACK" *) + output reg o_mack, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS DAT_MISO" *) + output reg [(DW-1):0] o_mdata, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ERR" *) + output reg o_merr, // We'll share the clock and the reset // // Outgoing WB classic port master ( for convinience labelled as WB4, later use separate interface definition for WB3 classic) - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM CYC" *) output reg o_scyc, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM STB" *) output reg o_sstb, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM WE" *) output reg o_swe, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM ADR" *) output reg [(AW-1):0] o_saddr, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM DAT_MOSI" *) output reg [(DW-1):0] o_sdata, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM SEL" *) output reg [(DW/8-1):0] o_ssel, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM ACK" *) input wire i_sack, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM DAT_MISO" *) input wire [(DW-1):0] i_sdata, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM ERR" *) input wire i_serr, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM CYC" *) + output reg o_scyc, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM STB" *) + output reg o_sstb, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM WE" *) + output reg o_swe, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM ADR" *) + output reg [(AW-1):0] o_saddr, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM DAT_MOSI" *) + output reg [(DW-1):0] o_sdata, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM SEL" *) + output reg [(DW/8-1):0] o_ssel, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM ACK" *) + input wire i_sack, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM DAT_MISO" *) + input wire [(DW-1):0] i_sdata, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM ERR" *) + input wire i_serr, // Extra wires, not necessarily necessary for WB/B3 - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM CTI" *) output reg [2:0] o_scti, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM BTE" *) output reg [1:0] o_sbte + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM CTI" *) + output reg [2:0] o_scti, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM BTE" *) + output reg [1:0] o_sbte ); // // returned = whether we've received our return value or not. From a770ac19f6230c32e1cd4a83365e0032ee71390c Mon Sep 17 00:00:00 2001 From: Tomasz Motylewski Date: Mon, 17 Aug 2020 22:05:47 +0200 Subject: [PATCH 11/12] changed wishbone interface name B3 and B4 --- interfaces/{wishbone.xml => wishboneB3.xml} | 2 +- .../{wishbone_rtl.xml => wishboneB3_rtl.xml} | 32 ++++++++++++- interfaces/{wishbone4.xml => wishboneB4.xml} | 8 ++-- .../{wishbone4_rtl.xml => wishboneB4_rtl.xml} | 10 ++-- rtl/axim2wbsp.v | 20 ++++---- rtl/wbm2axilite.v | 22 ++++----- rtl/wbm2axisp.v | 20 ++++---- rtl/wbp2classic.v | 47 +++++++++---------- 8 files changed, 94 insertions(+), 67 deletions(-) rename interfaces/{wishbone.xml => wishboneB3.xml} (95%) rename interfaces/{wishbone_rtl.xml => wishboneB3_rtl.xml} (88%) rename interfaces/{wishbone4.xml => wishboneB4.xml} (81%) rename interfaces/{wishbone4_rtl.xml => wishboneB4_rtl.xml} (98%) diff --git a/interfaces/wishbone.xml b/interfaces/wishboneB3.xml similarity index 95% rename from interfaces/wishbone.xml rename to interfaces/wishboneB3.xml index fcee99f..a55a62f 100644 --- a/interfaces/wishbone.xml +++ b/interfaces/wishboneB3.xml @@ -3,7 +3,7 @@ opencores.org bus wishbone - 3.0 + B3 false false 1 diff --git a/interfaces/wishbone_rtl.xml b/interfaces/wishboneB3_rtl.xml similarity index 88% rename from interfaces/wishbone_rtl.xml rename to interfaces/wishboneB3_rtl.xml index 038c0b9..fc56b5c 100644 --- a/interfaces/wishbone_rtl.xml +++ b/interfaces/wishboneB3_rtl.xml @@ -3,8 +3,8 @@ opencores.org bus wishbone_rtl - 3.0 - + B3 + CYC @@ -214,6 +214,34 @@ 0 + + CTI + CTI + + + 3 + + + 3 + in + + 0 + + + + BTE + BTE + + + 2 + + + 2 + in + + 0 + + diff --git a/interfaces/wishbone4.xml b/interfaces/wishboneB4.xml similarity index 81% rename from interfaces/wishbone4.xml rename to interfaces/wishboneB4.xml index 0ac6319..8a0ff7e 100644 --- a/interfaces/wishbone4.xml +++ b/interfaces/wishboneB4.xml @@ -2,17 +2,17 @@ opencores.org bus - wishbone4 - 4.0 + wishbone + B4 false false - + 1 1 https://opencores.org/howto/wishbone 2010-06-22 Rev.B4 specs. - wishbone4 + wishbone diff --git a/interfaces/wishbone4_rtl.xml b/interfaces/wishboneB4_rtl.xml similarity index 98% rename from interfaces/wishbone4_rtl.xml rename to interfaces/wishboneB4_rtl.xml index 1e840e0..f369b37 100644 --- a/interfaces/wishbone4_rtl.xml +++ b/interfaces/wishboneB4_rtl.xml @@ -2,11 +2,11 @@ opencores.org bus - wishbone4_rtl - 4.0 - + wishbone_rtl + B4 + - + CYC cycle in progress @@ -305,7 +305,7 @@ - wishbone4 + wishbone diff --git a/rtl/axim2wbsp.v b/rtl/axim2wbsp.v index 022eba9..245e1b6 100644 --- a/rtl/axim2wbsp.v +++ b/rtl/axim2wbsp.v @@ -110,25 +110,25 @@ module axim2wbsp #( (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 o_reset RST" *) output wire o_reset, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM CYC" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 M_WBP CYC" *) output wire o_wb_cyc, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM STB" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 M_WBP STB" *) output wire o_wb_stb, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM WE" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 M_WBP WE" *) output wire o_wb_we, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM ADR" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 M_WBP ADR" *) output wire [(AW-1):0] o_wb_addr, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM DAT_MOSI" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 M_WBP DAT_MOSI" *) output wire [(C_AXI_DATA_WIDTH-1):0] o_wb_data, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM SEL" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 M_WBP SEL" *) output wire [(C_AXI_DATA_WIDTH/8-1):0] o_wb_sel, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM STALL" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 M_WBP STALL" *) input wire i_wb_stall, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM ACK" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 M_WBP ACK" *) input wire i_wb_ack, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM DAT_MISO" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 M_WBP DAT_MISO" *) input wire [(C_AXI_DATA_WIDTH-1):0] i_wb_data, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBM ERR" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 M_WBP ERR" *) input wire i_wb_err ); // diff --git a/rtl/wbm2axilite.v b/rtl/wbm2axilite.v index 0fd02b8..d0f6689 100644 --- a/rtl/wbm2axilite.v +++ b/rtl/wbm2axilite.v @@ -41,7 +41,7 @@ module wbm2axilite #( localparam DW = C_AXI_DATA_WIDTH,// Wishbone data width localparam AW = C_AXI_ADDR_WIDTH-2// WB addr width (log wordsize) ) ( - (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME i_clk, ASSOCIATED_BUSIF WBS:M_AXI" *) + (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME i_clk, ASSOCIATED_BUSIF S_WBP:M_AXI" *) (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 i_clk CLK" *) input wire i_clk, (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_HIGH" *) @@ -49,25 +49,25 @@ module wbm2axilite #( input wire i_reset, // // We'll share the clock and the reset - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS CYC" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP CYC" *) input wire i_wb_cyc, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS STB" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP STB" *) input wire i_wb_stb, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS WE" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP WE" *) input wire i_wb_we, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ADR" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP ADR" *) input wire [(AW-1):0] i_wb_addr, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS DAT_MOSI" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP DAT_MOSI" *) input wire [(DW-1):0] i_wb_data, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS SEL" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP SEL" *) input wire [(DW/8-1):0] i_wb_sel, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS STALL" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP STALL" *) output wire o_wb_stall, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ACK" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP ACK" *) output reg o_wb_ack, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS DAT_MISO" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP DAT_MISO" *) output reg [(DW-1):0] o_wb_data, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ERR" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP ERR" *) output reg o_wb_err, // diff --git a/rtl/wbm2axisp.v b/rtl/wbm2axisp.v index baccb00..9e19dbc 100644 --- a/rtl/wbm2axisp.v +++ b/rtl/wbm2axisp.v @@ -159,25 +159,25 @@ module wbm2axisp #( input wire i_axi_rlast, // Read last // We'll share the clock and the reset - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS CYC" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP CYC" *) input wire i_wb_cyc, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS STB" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP STB" *) input wire i_wb_stb, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS WE" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP WE" *) input wire i_wb_we, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ADR" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP ADR" *) input wire [(AW-1):0] i_wb_addr, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS DAT_MOSI" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP DAT_MOSI" *) input wire [(DW-1):0] i_wb_data, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS SEL" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP SEL" *) input wire [(DW/8-1):0] i_wb_sel, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS STALL" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP STALL" *) output reg o_wb_stall, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ACK" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP ACK" *) output reg o_wb_ack, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS DAT_MISO" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP DAT_MISO" *) output reg [(DW-1):0] o_wb_data, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ERR" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP ERR" *) output reg o_wb_err // }}} ); diff --git a/rtl/wbp2classic.v b/rtl/wbp2classic.v index f7a31b7..f8752a5 100644 --- a/rtl/wbp2classic.v +++ b/rtl/wbp2classic.v @@ -39,7 +39,7 @@ module wbp2classic #( DW = 32 ) ( - (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME i_clk, ASSOCIATED_BUSIF WBS:WBCM" *) + (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME i_clk, ASSOCIATED_BUSIF S_WBP:M_WBC" *) (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 i_clk CLK" *) input wire i_clk, (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_HIGH" *) @@ -47,53 +47,52 @@ module wbp2classic #( input wire i_reset, // // Incoming WB pipelined port WB4 slave interface - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS CYC" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP CYC" *) input wire i_mcyc, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS STB" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP STB" *) input wire i_mstb, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS WE" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP WE" *) input wire i_mwe, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ADR" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP ADR" *) input wire [(AW-1):0] i_maddr, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS DAT_MOSI" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP DAT_MOSI" *) input wire [(DW-1):0] i_mdata, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS SEL" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP SEL" *) input wire [(DW/8-1):0] i_msel, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS STALL" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP STALL" *) output reg o_mstall, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ACK" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP ACK" *) output reg o_mack, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS DAT_MISO" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP DAT_MISO" *) output reg [(DW-1):0] o_mdata, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBS ERR" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP ERR" *) output reg o_merr, // We'll share the clock and the reset - // // Outgoing WB classic port master ( for convinience labelled as WB4, later use separate interface definition for WB3 classic) - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM CYC" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B3 M_WBC CYC" *) output reg o_scyc, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM STB" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B3 M_WBC STB" *) output reg o_sstb, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM WE" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B3 M_WBC WE" *) output reg o_swe, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM ADR" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B3 M_WBC ADR" *) output reg [(AW-1):0] o_saddr, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM DAT_MOSI" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B3 M_WBC DAT_MOSI" *) output reg [(DW-1):0] o_sdata, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM SEL" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B3 M_WBC SEL" *) output reg [(DW/8-1):0] o_ssel, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM ACK" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B3 M_WBC ACK" *) input wire i_sack, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM DAT_MISO" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B3 M_WBC DAT_MISO" *) input wire [(DW-1):0] i_sdata, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM ERR" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B3 M_WBC ERR" *) input wire i_serr, - // Extra wires, not necessarily necessary for WB/B3 - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM CTI" *) + // Extra wires, not necessary for WB/B3 + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B3 M_WBC CTI" *) output reg [2:0] o_scti, - (* X_INTERFACE_INFO = "opencores.org:bus:wishbone4:4.0 WBCM BTE" *) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B3 M_WBC BTE" *) output reg [1:0] o_sbte ); // From a7264fc561c0ff032fbcca8d4df494f409f3fb21 Mon Sep 17 00:00:00 2001 From: Tomasz Motylewski Date: Mon, 17 Aug 2020 22:11:36 +0200 Subject: [PATCH 12/12] STALL input is required in B4 master --- interfaces/wishboneB4_rtl.xml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/interfaces/wishboneB4_rtl.xml b/interfaces/wishboneB4_rtl.xml index f369b37..af5722b 100644 --- a/interfaces/wishboneB4_rtl.xml +++ b/interfaces/wishboneB4_rtl.xml @@ -6,7 +6,7 @@ B4 - + CYC cycle in progress @@ -249,6 +249,7 @@ slave signals that it can not accept more transfer + required 1 in