diff --git a/interfaces/wishboneB3.xml b/interfaces/wishboneB3.xml new file mode 100644 index 0000000..a55a62f --- /dev/null +++ b/interfaces/wishboneB3.xml @@ -0,0 +1,17 @@ + + + opencores.org + bus + wishbone + B3 + false + false + 1 + 1 + wishbone from opencores.org b3.pdf + + + wishbone + + + diff --git a/interfaces/wishboneB3_rtl.xml b/interfaces/wishboneB3_rtl.xml new file mode 100644 index 0000000..fc56b5c --- /dev/null +++ b/interfaces/wishboneB3_rtl.xml @@ -0,0 +1,251 @@ + + + opencores.org + bus + wishbone_rtl + B3 + + + + CYC + cycle in progress + + + true + + + required + 1 + + + required + 1 + in + + 0 + + + + STB + data transfer strobe RD or WR + + + required + 1 + + + required + 1 + in + + 0 + + + + WE + WriteEnable + + + 1 + + + 1 + in + + 0 + + + + SEL + select sub-words e.g. bytes for writing + + + + in + + 65535 + + + + ACK + ACK master input + + + required + 1 + in + + + required + + 0 + + + + ADR + Address bus + + + true + + + required + + + in + + 0 + + + + addr + + + + + DAT_MISO + DAT_I master O slave + + + true + + + in + + 0 + + + + DAT_MOSI + DAT_O master I slave + + + in + + + 0 + + + + LOCK + uninterruptible access + + + 1 + + + 1 + in + + 0 + + + + ERR + slave terminates access with error + + + 1 + in + + + 1 + + 0 + + + + RTY + slave not ready, access terminated + + + 1 + in + + + 1 + + 0 + + + + TGD_MISO + information that is associated with the data input array [DAT_I()], and is qualified by signal [STB_I] + + + in + + 0 + + + + TGD_MOSI + info about data output array [DAT_O()], and is qualified by signal [STB_O] + + + true + + + in + + 0 + + + + TGA + address lines [ADR_O()] info + + + true + + + in + + 0 + + + + TGC + bus cycles, qualified by [CYC_O] + + + in + + 0 + + + + CTI + CTI + + + 3 + + + 3 + in + + 0 + + + + BTE + BTE + + + 2 + + + 2 + in + + 0 + + + + + + wishbone + + + diff --git a/interfaces/wishboneB4.xml b/interfaces/wishboneB4.xml new file mode 100644 index 0000000..8a0ff7e --- /dev/null +++ b/interfaces/wishboneB4.xml @@ -0,0 +1,18 @@ + + + opencores.org + bus + wishbone + B4 + false + false + + 1 + 1 + https://opencores.org/howto/wishbone 2010-06-22 Rev.B4 specs. + + + wishbone + + + diff --git a/interfaces/wishboneB4_rtl.xml b/interfaces/wishboneB4_rtl.xml new file mode 100644 index 0000000..af5722b --- /dev/null +++ b/interfaces/wishboneB4_rtl.xml @@ -0,0 +1,312 @@ + + + opencores.org + bus + wishbone_rtl + B4 + + + + CYC + cycle in progress + + + true + + + required + 1 + + + required + 1 + in + + 0 + + + + addr + + + + + STB + data transfer strobe RD or WR + + + required + 1 + + + required + 1 + in + + 0 + + + + WE + WriteEnable + + + 1 + + + 1 + in + + 0 + + + + wr + + + + + SEL + select sub-words e.g. bytes for writing + + + + in + + 65535 + + + + wr + + + + + ACK + ACK master input + + + required + 1 + in + + + required + + 0 + + + + ADR + Address bus + + + true + + + required + + + in + + 0 + + + + addr + + + + + DAT_MISO + DAT_I master O slave + + + true + + + in + + 0 + + + + rd + + + + + DAT_MOSI + DAT_O master I slave + + + in + + + 0 + + + + wr + + + + + LOCK + uninterruptible access + + + 1 + + + 1 + in + + 0 + + + + ERR + slave terminates access with error + + + 1 + in + + + 1 + + 0 + + + + RTY + slave not ready, access terminated + + + 1 + in + + + 1 + + 0 + + + + TGD_MISO + information that is associated with the data input array [DAT_I()], and is qualified by signal [STB_I] + + + in + + 0 + + + + TGD_MOSI + info about data output array [DAT_O()], and is qualified by signal [STB_O] + + + true + + + in + + 0 + + + + TGA + address lines [ADR_O()] info + + + true + + + in + + 0 + + + + addr + + + + + TGC + bus cycles, qualified by [CYC_O] + + + in + + 0 + + + + STALL + slave signals that it can not accept more transfer + + + required + 1 + in + + + 1 + + 0 + + + + CTI + Cycle Type Identifier + + + true + + + 3 + + + 3 + in + + 0 + + + + addr + + + + + BTE + Burst Type Extension + + + true + + + 2 + + + 2 + in + + 0 + + + + addr + + + + + + + wishbone + + + diff --git a/rtl/afifo.v b/rtl/afifo.v index 1e333b2..a10c50b 100644 --- a/rtl/afifo.v +++ b/rtl/afifo.v @@ -649,3 +649,7 @@ module afifo( end endgenerate `endif endmodule +`ifndef YOSYS +`default_nettype wire +`endif + diff --git a/rtl/axidma.v b/rtl/axidma.v index 5b2b584..5638741 100644 --- a/rtl/axidma.v +++ b/rtl/axidma.v @@ -2740,3 +2740,7 @@ module axidma #( // None (currently) `endif endmodule +`ifndef YOSYS +`default_nettype wire +`endif + diff --git a/rtl/axidouble.v b/rtl/axidouble.v index f40fea3..05b2bb9 100644 --- a/rtl/axidouble.v +++ b/rtl/axidouble.v @@ -1198,3 +1198,7 @@ module axidouble #( end endgenerate `endif endmodule +`ifndef YOSYS +`default_nettype wire +`endif + diff --git a/rtl/axildouble.v b/rtl/axildouble.v index e5f7be2..b8fc88b 100644 --- a/rtl/axildouble.v +++ b/rtl/axildouble.v @@ -735,6 +735,6 @@ module axildouble #( cover((cvr_writes > 4) && (cvr_reads > 4)); `endif endmodule -// `ifndef YOSYS -// `default_nettype wire -// `endif +`ifndef YOSYS +`default_nettype wire +`endif diff --git a/rtl/axilsingle.v b/rtl/axilsingle.v index 13a9911..d42b39b 100644 --- a/rtl/axilsingle.v +++ b/rtl/axilsingle.v @@ -714,6 +714,6 @@ module axilsingle #( cover((cvr_writes > 4) && (cvr_reads > 4)); `endif endmodule -// `ifndef YOSYS -// `default_nettype wire -// `endif +`ifndef YOSYS +`default_nettype wire +`endif diff --git a/rtl/axim2wbsp.v b/rtl/axim2wbsp.v index f4eda1c..245e1b6 100644 --- a/rtl/axim2wbsp.v +++ b/rtl/axim2wbsp.v @@ -46,16 +46,17 @@ module axim2wbsp #( // This is an int between 1-16 parameter C_AXI_DATA_WIDTH = 32,// Width of the AXI R&W data parameter C_AXI_ADDR_WIDTH = 28, // AXI Address width - localparam AXI_LSBS = $clog2(C_AXI_DATA_WIDTH)-3, - localparam DW = C_AXI_DATA_WIDTH, - localparam AW = C_AXI_ADDR_WIDTH - AXI_LSBS, + parameter AXI_LSBS = $clog2(C_AXI_DATA_WIDTH)-3, // leave it calculated, unless AXI narrow transfers need to be supported + parameter DW = C_AXI_DATA_WIDTH, // leave it calculated + parameter AW = C_AXI_ADDR_WIDTH - AXI_LSBS, // leave it calculated parameter LGFIFO = 5, + parameter [0:0] OPT_SWAP_ENDIANNESS = 1'b0, parameter [0:0] OPT_READONLY = 1'b0, parameter [0:0] OPT_WRITEONLY = 1'b0 ) ( - // + // names are matching AXI spec, therefore X_INTERFACE_INFO not needed input wire S_AXI_ACLK, // System clock - input wire S_AXI_ARESETN, + input wire S_AXI_ARESETN, // reset, active low // AXI write address channel signals input wire S_AXI_AWVALID, // Write address valid @@ -104,17 +105,30 @@ module axim2wbsp #( output wire S_AXI_RLAST, // Read last output wire [1:0] S_AXI_RRESP, // Read response - // We'll share the clock and the reset + // Wishbone4 pipelined master. We'll share the clock and output the active-high reset + (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME o_reset, POLARITY ACTIVE_HIGH" *) + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 o_reset RST" *) output wire o_reset, + + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 M_WBP CYC" *) output wire o_wb_cyc, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 M_WBP STB" *) output wire o_wb_stb, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 M_WBP WE" *) output wire o_wb_we, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 M_WBP ADR" *) output wire [(AW-1):0] o_wb_addr, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 M_WBP DAT_MOSI" *) output wire [(C_AXI_DATA_WIDTH-1):0] o_wb_data, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 M_WBP SEL" *) output wire [(C_AXI_DATA_WIDTH/8-1):0] o_wb_sel, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 M_WBP STALL" *) input wire i_wb_stall, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 M_WBP ACK" *) input wire i_wb_ack, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 M_WBP DAT_MISO" *) input wire [(C_AXI_DATA_WIDTH-1):0] i_wb_data, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 M_WBP ERR" *) input wire i_wb_err ); // @@ -138,6 +152,8 @@ module axim2wbsp #( .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH), .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH), .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH), + .OPT_SWAP_ENDIANNESS(OPT_SWAP_ENDIANNESS), + .AXI_LSBS(AXI_LSBS), .LGFIFO(LGFIFO)) axi_write_decoder( .S_AXI_ACLK(S_AXI_ACLK), .S_AXI_ARESETN(S_AXI_ARESETN), @@ -194,7 +210,9 @@ module axim2wbsp #( .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH), .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH), .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH), - .LGFIFO(LGFIFO)) + .AXI_LSBS(AXI_LSBS), + .LGFIFO(LGFIFO), + .OPT_SWAP_ENDIANNESS(OPT_SWAP_ENDIANNESS)) axi_read_decoder( .S_AXI_ACLK(S_AXI_ACLK), .S_AXI_ARESETN(S_AXI_ARESETN), // @@ -281,3 +299,7 @@ module axim2wbsp #( `ifdef FORMAL `endif endmodule +`ifndef YOSYS +`default_nettype wire +`endif + diff --git a/rtl/aximrd2wbsp.v b/rtl/aximrd2wbsp.v index a42e80f..f2be9b2 100644 --- a/rtl/aximrd2wbsp.v +++ b/rtl/aximrd2wbsp.v @@ -51,7 +51,8 @@ module aximrd2wbsp #( // This is an int between 1-16 parameter C_AXI_DATA_WIDTH = 32,// Width of the AXI R&W data parameter C_AXI_ADDR_WIDTH = 28, // AXI Address width - parameter AW = 26, // AXI Address width + parameter AXI_LSBS = $clog2(C_AXI_DATA_WIDTH)-3, // change it only to support narrow transfers + parameter AW = C_AXI_ADDR_WIDTH - AXI_LSBS, // AXI Address width parameter LGFIFO = 3, parameter [0:0] OPT_SWAP_ENDIANNESS = 0 // parameter WBMODE = "B4PIPELINE" @@ -601,3 +602,7 @@ module aximrd2wbsp #( `endif endmodule +`ifndef YOSYS +`default_nettype wire +`endif + diff --git a/rtl/aximwr2wbsp.v b/rtl/aximwr2wbsp.v index a16d89a..2f672eb 100644 --- a/rtl/aximwr2wbsp.v +++ b/rtl/aximwr2wbsp.v @@ -41,8 +41,9 @@ module aximwr2wbsp #( // This is an int between 1-16 parameter C_AXI_DATA_WIDTH = 32,// Width of the AXI R&W data parameter C_AXI_ADDR_WIDTH = 28, // AXI Address width + parameter [0:0] OPT_SWAP_ENDIANNESS = 1'b0, // Lil to Big Endian swap - localparam AXI_LSBS = $clog2(C_AXI_DATA_WIDTH)-3, + parameter AXI_LSBS = $clog2(C_AXI_DATA_WIDTH)-3, // change it only to support narrow transfers localparam AW = C_AXI_ADDR_WIDTH-AXI_LSBS, localparam DW = C_AXI_DATA_WIDTH, @@ -571,3 +572,7 @@ module aximwr2wbsp #( cover(cvr_wrid_bursts == 4); `endif endmodule +`ifndef YOSYS +`default_nettype wire +`endif + diff --git a/rtl/axixclk.v b/rtl/axixclk.v index d362974..57ea252 100644 --- a/rtl/axixclk.v +++ b/rtl/axixclk.v @@ -307,3 +307,7 @@ module axixclk #( end endgenerate endmodule +`ifndef YOSYS +`default_nettype wire +`endif + diff --git a/rtl/easyaxil.v b/rtl/easyaxil.v index e2e6dbb..25e5028 100644 --- a/rtl/easyaxil.v +++ b/rtl/easyaxil.v @@ -439,3 +439,7 @@ module easyaxil #( // }}} `endif endmodule +`ifndef YOSYS +`default_nettype wire +`endif + diff --git a/rtl/sfifothresh.v b/rtl/sfifothresh.v index 7a010cf..33b754f 100644 --- a/rtl/sfifothresh.v +++ b/rtl/sfifothresh.v @@ -95,3 +95,7 @@ module sfifothresh(i_clk, i_reset, assert(o_int == (o_fill >= $past(i_threshold))); `endif endmodule +`ifndef YOSYS +`default_nettype wire +`endif + diff --git a/rtl/wbm2axilite.v b/rtl/wbm2axilite.v index f3d63e2..d0f6689 100644 --- a/rtl/wbm2axilite.v +++ b/rtl/wbm2axilite.v @@ -41,48 +41,82 @@ module wbm2axilite #( localparam DW = C_AXI_DATA_WIDTH,// Wishbone data width localparam AW = C_AXI_ADDR_WIDTH-2// WB addr width (log wordsize) ) ( + (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME i_clk, ASSOCIATED_BUSIF S_WBP:M_AXI" *) + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 i_clk CLK" *) input wire i_clk, + (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_HIGH" *) + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 i_reset RST" *) input wire i_reset, // // We'll share the clock and the reset - input wire i_wb_cyc, - input wire i_wb_stb, - input wire i_wb_we, - input wire [(AW-1):0] i_wb_addr, - input wire [(DW-1):0] i_wb_data, - input wire [(DW/8-1):0] i_wb_sel, - output wire o_wb_stall, - output reg o_wb_ack, - output reg [(DW-1):0] o_wb_data, - output reg o_wb_err, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP CYC" *) + input wire i_wb_cyc, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP STB" *) + input wire i_wb_stb, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP WE" *) + input wire i_wb_we, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP ADR" *) + input wire [(AW-1):0] i_wb_addr, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP DAT_MOSI" *) + input wire [(DW-1):0] i_wb_data, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP SEL" *) + input wire [(DW/8-1):0] i_wb_sel, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP STALL" *) + output wire o_wb_stall, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP ACK" *) + output reg o_wb_ack, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP DAT_MISO" *) + output reg [(DW-1):0] o_wb_data, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP ERR" *) + output reg o_wb_err, + // // AXI write address channel signals + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output reg o_axi_awvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) input wire i_axi_awready, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output reg [C_AXI_ADDR_WIDTH-1:0] o_axi_awaddr, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output wire [2:0] o_axi_awprot, // // AXI write data channel signals + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) output reg o_axi_wvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) input wire i_axi_wready, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) output reg [C_AXI_DATA_WIDTH-1:0] o_axi_wdata, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) output reg [C_AXI_DATA_WIDTH/8-1:0] o_axi_wstrb, // // AXI write response channel signals + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input wire i_axi_bvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output wire o_axi_bready, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) input wire [1:0] i_axi_bresp, // // AXI read address channel signals + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output reg o_axi_arvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input wire i_axi_arready, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output reg [C_AXI_ADDR_WIDTH-1:0] o_axi_araddr, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output wire [2:0] o_axi_arprot, // - // AXI read data channel signals + // AXI read data channel signals + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input wire i_axi_rvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) output wire o_axi_rready, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input wire [C_AXI_DATA_WIDTH-1:0] i_axi_rdata, + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input wire [1:0] i_axi_rresp ); diff --git a/rtl/wbm2axisp.v b/rtl/wbm2axisp.v index cac5652..9e19dbc 100644 --- a/rtl/wbm2axisp.v +++ b/rtl/wbm2axisp.v @@ -66,67 +66,119 @@ module wbm2axisp #( // }}} ) ( // {{{ - input wire i_clk, // System clock - input wire i_reset,// Reset signal,drives AXI rst + (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_ACLK, ASSOCIATED_BUSIF M_AXI" *) + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_ACLK CLK" *) + input wire i_clk, // System clock + + (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_HIGH" *) + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 i_reset RST" *) + input wire i_reset,// Reset signal active high, inverted drives AXI rst // AXI write address channel signals - output reg o_axi_awvalid, // Write address valid - input wire i_axi_awready, // Slave is ready to accept - output wire [C_AXI_ID_WIDTH-1:0] o_axi_awid, // Write ID - output reg [C_AXI_ADDR_WIDTH-1:0] o_axi_awaddr, // Write address - output wire [7:0] o_axi_awlen, // Write Burst Length - output wire [2:0] o_axi_awsize, // Write Burst size - output wire [1:0] o_axi_awburst, // Write Burst type - output wire [0:0] o_axi_awlock, // Write lock type - output wire [3:0] o_axi_awcache, // Write Cache type - output wire [2:0] o_axi_awprot, // Write Protection type - output wire [3:0] o_axi_awqos, // Write Quality of Svc + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) + output reg o_axi_awvalid, // Write address valid + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) + input wire i_axi_awready, // Slave is ready to accept + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *) + output wire [C_AXI_ID_WIDTH-1:0] o_axi_awid, // Write ID + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) + output reg [C_AXI_ADDR_WIDTH-1:0] o_axi_awaddr, // Write address + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *) + output wire [7:0] o_axi_awlen, // Write Burst Length + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *) + output wire [2:0] o_axi_awsize, // Write Burst size + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *) + output wire [1:0] o_axi_awburst, // Write Burst type + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *) + output wire [0:0] o_axi_awlock, // Write lock type + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *) + output wire [3:0] o_axi_awcache, // Write Cache type + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) + output wire [2:0] o_axi_awprot, // Write Protection type + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *) + output wire [3:0] o_axi_awqos, // Write Quality of Svc // AXI write data channel signals - output reg o_axi_wvalid, // Write valid - input wire i_axi_wready, // Write data ready - output reg [C_AXI_DATA_WIDTH-1:0] o_axi_wdata, // Write data - output reg [C_AXI_DATA_WIDTH/8-1:0] o_axi_wstrb, // Write strobes - output wire o_axi_wlast, // Last write transaction + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) + output reg o_axi_wvalid, // Write valid + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) + input wire i_axi_wready, // Write data ready + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) + output reg [C_AXI_DATA_WIDTH-1:0] o_axi_wdata, // Write data + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) + output reg [C_AXI_DATA_WIDTH/8-1:0] o_axi_wstrb, // Write strobes + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *) + output wire o_axi_wlast, // Last write transaction // AXI write response channel signals - input wire i_axi_bvalid, // Write reponse valid - output wire o_axi_bready, // Response ready + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) + input wire i_axi_bvalid, // Write reponse valid + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) + output wire o_axi_bready, // Response ready + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *) input wire [C_AXI_ID_WIDTH-1:0] i_axi_bid, // Response ID - input wire [1:0] i_axi_bresp, // Write response + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) + input wire [1:0] i_axi_bresp, // Write response // AXI read address channel signals - output reg o_axi_arvalid, // Read address valid - input wire i_axi_arready, // Read address ready - output wire [C_AXI_ID_WIDTH-1:0] o_axi_arid, // Read ID - output reg [C_AXI_ADDR_WIDTH-1:0] o_axi_araddr, // Read address - output wire [7:0] o_axi_arlen, // Read Burst Length - output wire [2:0] o_axi_arsize, // Read Burst size - output wire [1:0] o_axi_arburst, // Read Burst type - output wire [0:0] o_axi_arlock, // Read lock type - output wire [3:0] o_axi_arcache, // Read Cache type - output wire [2:0] o_axi_arprot, // Read Protection type - output wire [3:0] o_axi_arqos, // Read Protection type + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) + output reg o_axi_arvalid, // Read address valid + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) + input wire i_axi_arready, // Read address ready + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *) + output wire [C_AXI_ID_WIDTH-1:0] o_axi_arid, // Read ID + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) + output reg [C_AXI_ADDR_WIDTH-1:0] o_axi_araddr, // Read address + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *) + output wire [7:0] o_axi_arlen, // Read Burst Length + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *) + output wire [2:0] o_axi_arsize, // Read Burst size + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *) + output wire [1:0] o_axi_arburst, // Read Burst type + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *) + output wire [0:0] o_axi_arlock, // Read lock type + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *) + output wire [3:0] o_axi_arcache, // Read Cache type + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) + output wire [2:0] o_axi_arprot, // Read Protection type + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *) + output wire [3:0] o_axi_arqos, // Read Protection type // AXI read data channel signals - input wire i_axi_rvalid, // Read reponse valid - output wire o_axi_rready, // Read Response ready + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) + input wire i_axi_rvalid, // Read reponse valid + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) + output wire o_axi_rready, // Read Response ready + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *) input wire [C_AXI_ID_WIDTH-1:0] i_axi_rid, // Response ID + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input wire [C_AXI_DATA_WIDTH-1:0] i_axi_rdata, // Read data - input wire [1:0] i_axi_rresp, // Read response - input wire i_axi_rlast, // Read last + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) + input wire [1:0] i_axi_rresp, // Read response + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *) + input wire i_axi_rlast, // Read last // We'll share the clock and the reset - input wire i_wb_cyc, - input wire i_wb_stb, - input wire i_wb_we, - input wire [(AW-1):0] i_wb_addr, - input wire [(DW-1):0] i_wb_data, - input wire [(DW/8-1):0] i_wb_sel, - output reg o_wb_stall, - output reg o_wb_ack, - output reg [(DW-1):0] o_wb_data, - output reg o_wb_err + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP CYC" *) + input wire i_wb_cyc, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP STB" *) + input wire i_wb_stb, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP WE" *) + input wire i_wb_we, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP ADR" *) + input wire [(AW-1):0] i_wb_addr, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP DAT_MOSI" *) + input wire [(DW-1):0] i_wb_data, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP SEL" *) + input wire [(DW/8-1):0] i_wb_sel, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP STALL" *) + output reg o_wb_stall, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP ACK" *) + output reg o_wb_ack, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP DAT_MISO" *) + output reg [(DW-1):0] o_wb_data, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP ERR" *) + output reg o_wb_err // }}} ); //////////////////////////////////////////////////////////////////////// @@ -1145,3 +1197,7 @@ module wbm2axisp #( `endif // FORMAL // }}} endmodule +`ifndef YOSYS +`default_nettype wire +`endif + diff --git a/rtl/wbp2classic.v b/rtl/wbp2classic.v index 0e465f1..f8752a5 100644 --- a/rtl/wbp2classic.v +++ b/rtl/wbp2classic.v @@ -34,38 +34,67 @@ // `default_nettype none // -module wbp2classic(i_clk, i_reset, - i_mcyc, i_mstb, i_mwe, i_maddr, i_mdata, i_msel, - o_mstall, o_mack, o_mdata, o_merr, - o_scyc, o_sstb, o_swe, o_saddr, o_sdata, o_ssel, - i_sack, i_sdata, i_serr, - o_scti, o_sbte); - parameter AW = 12, - DW = 32; - // - input wire i_clk, i_reset; - // - // Incoming WB pipelined port - input wire i_mcyc, i_mstb, i_mwe; - input wire [AW-1:0] i_maddr; - input wire [DW-1:0] i_mdata; - input wire [DW/8-1:0] i_msel; - output reg o_mstall, o_mack; - output reg [DW-1:0] o_mdata; - output reg o_merr; - // - // Outgoing WB classic port - output reg o_scyc, o_sstb, o_swe; - output reg [AW-1:0] o_saddr; - output reg [DW-1:0] o_sdata; - output reg [DW/8-1:0] o_ssel; - input wire i_sack; - input wire [DW-1:0] i_sdata; - input wire i_serr; - // Extra wires, not necessarily necessary for WB/B3 - output reg [2:0] o_scti; - output reg [1:0] o_sbte; +module wbp2classic #( + parameter AW = 12, + DW = 32 + ) ( + (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME i_clk, ASSOCIATED_BUSIF S_WBP:M_WBC" *) + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 i_clk CLK" *) + input wire i_clk, + (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME i_reset, POLARITY ACTIVE_HIGH" *) + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 i_reset RST" *) + input wire i_reset, + // + // Incoming WB pipelined port WB4 slave interface + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP CYC" *) + input wire i_mcyc, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP STB" *) + input wire i_mstb, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP WE" *) + input wire i_mwe, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP ADR" *) + input wire [(AW-1):0] i_maddr, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP DAT_MOSI" *) + input wire [(DW-1):0] i_mdata, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP SEL" *) + input wire [(DW/8-1):0] i_msel, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP STALL" *) + output reg o_mstall, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP ACK" *) + output reg o_mack, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP DAT_MISO" *) + output reg [(DW-1):0] o_mdata, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B4 S_WBP ERR" *) + output reg o_merr, + + // We'll share the clock and the reset + + // Outgoing WB classic port master ( for convinience labelled as WB4, later use separate interface definition for WB3 classic) + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B3 M_WBC CYC" *) + output reg o_scyc, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B3 M_WBC STB" *) + output reg o_sstb, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B3 M_WBC WE" *) + output reg o_swe, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B3 M_WBC ADR" *) + output reg [(AW-1):0] o_saddr, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B3 M_WBC DAT_MOSI" *) + output reg [(DW-1):0] o_sdata, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B3 M_WBC SEL" *) + output reg [(DW/8-1):0] o_ssel, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B3 M_WBC ACK" *) + input wire i_sack, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B3 M_WBC DAT_MISO" *) + input wire [(DW-1):0] i_sdata, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B3 M_WBC ERR" *) + input wire i_serr, + // Extra wires, not necessary for WB/B3 + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B3 M_WBC CTI" *) + output reg [2:0] o_scti, + (* X_INTERFACE_INFO = "opencores.org:bus:wishbone:B3 M_WBC BTE" *) + output reg [1:0] o_sbte +); // // returned = whether we've received our return value or not. reg returned; diff --git a/rtl/wbsafety.v b/rtl/wbsafety.v index 3699a89..1a91e6d 100644 --- a/rtl/wbsafety.v +++ b/rtl/wbsafety.v @@ -523,3 +523,7 @@ module wbsafety(i_clk, i_reset, `endif endmodule +`ifndef YOSYS +`default_nettype wire +`endif +