How to get flat netlist from design checkpoint generated from vivado synthesis? #1003
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I'm trying to get the flat logical netlist from post-synthesis design checkpoint using RapidWright. And the flat netlist consists of only leaf/primitive cells and connections between them. However, the logical netlist is represented hierarchically in RapidWright based on the EDIF format. And I don't find any APIs in RapidWright that can helps me flat the hierarchical netlist directly. So I get the leaf cells and nets using public class FlatCircuitNetlist {
public static void main(String[] args) {
String dcpPath = "./benchmark/lu_20x20.dcp";
Design circuitDesign = Design.readCheckpoint(dcpPath);
EDIFNetlist logicalNetlist = circuitDesign.getNetlist();
List<EDIFHierCellInst> leafHierCellInsts = logicalNetlist.getAllLeafHierCellInstances();
Map<EDIFCellInst, EDIFHierCellInst> cell2HierCellMap = new HashMap<>();
Map<EDIFHierNet, List<EDIFHierPortInst>> hierNet2HierPortMap = logicalNetlist.getPhysicalNetPinMap();
Map<EDIFHierPortInst, EDIFHierNet> hierPort2HierNetMap = new HashMap<>();
Map<EDIFHierCellInst, List<EDIFHierPortInst>> hierCell2HierPortMap = new HashMap<>();
Map<EDIFHierPortInst, EDIFHierCellInst> hierPort2HierCellMap = new HashMap<>();
for (EDIFHierCellInst hierCellInst : leafHierCellInsts) {
cell2HierCellMap.put(hierCellInst.getInst(), hierCellInst);
}
for (Map.Entry<EDIFHierNet, List<EDIFHierPortInst>> entry : hierNet2HierPortMap.entrySet()) {
for (EDIFHierPortInst portInst : entry.getValue()) {
hierPort2HierNetMap.put(portInst, entry.getKey());
EDIFHierCellInst hierCell = cell2HierCellMap.get(portInst.getPortInst().getCellInst());
assert hierCell != null;
hierPort2HierCellMap.put(portInst, hierCell);
if (hierCell2HierPortMap.containsKey(hierCell)){
List<EDIFHierPortInst> portInsts = hierCell2HierPortMap.get(hierCell);
portInsts.add(portInst);
} else {
List<EDIFHierPortInst> portInsts = new ArrayList<>();
portInsts.add(portInst);
hierCell2HierPortMap.put(hierCell, portInsts);
}
}
}
System.out.println("Generate Flat Netlist Successfully");
}
} Can anyone help me verify if this implementation is correct and capable of extracting the complete information of the flat netlist? Specifically, I want to know if Besides, I find that this implementation doesn't work for netlists containing blockbox cells. Specifically, it seems that |
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Replies: 1 comment 3 replies
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The easiest approach is to create a new flattened netlist as a copy of the existing hierarchical one. Trying to modify an existing netlist in place to remove all the hierarchy could be done, but it is probably better to avoid that approach. I'm not sure about the code above, it is touching on some of the important APIs that are needed, but it doesn't address some of the corner cases such as VCC and GND nets and their respective sources that need to be collapsed in a flattened netlist. I've drafted up a PR that includes code that can accomplish this, see #1006 for details, it includes a test that should demonstrate how it can be used and will accommodate designs that contain black boxes. |
Beta Was this translation helpful? Give feedback.
The easiest approach is to create a new flattened netlist as a copy of the existing hierarchical one. Trying to modify an existing netlist in place to remove all the hierarchy could be done, but it is probably better to avoid that approach. I'm not sure about the code above, it is touching on some of the important APIs that are needed, but it doesn't address some of the corner cases such as VCC and GND nets and their respective sources that need to be collapsed in a flattened netlist.
I've drafted up a PR that includes code that can accomplish this, see #1006 for details, it includes a test that should demonstrate how it can be used and will accommodate designs that contain black boxes.