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I'm trying to check the area breakdown of the plugins in Vexii (like the area of IntAlu, Lsu or Branch).
Is there a way to generate plugins as separate verilog modules? Or are there any other ways to analyze their area?
The text was updated successfully, but these errors were encountered:
I would say, the only way is to run the synthesis flow between a configuration with and without a feature to get its "real" ressource usage. It may not be faisable for everything thing as there may be some coupling between a few plugins.
Using verilog module to contains logic feature get messed up a lot with hierarchy flattening.
Hi,
I'm trying to check the area breakdown of the plugins in Vexii (like the area of IntAlu, Lsu or Branch).
Is there a way to generate plugins as separate verilog modules? Or are there any other ways to analyze their area?
The text was updated successfully, but these errors were encountered: