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  • Other doc / media / talks
  • Technicalities
  • Navigating the code
    • -
  • Check list
  • About VexRiscv (not VexiiRiscv)
    • +
  • Check list
  • Framework
  • Framework
  • Framework
  • Framework
  • Framework
  • Framework
  • Framework
  • Framework
  • Framework
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  • Framework

    Scala / SpinalHDL

    -

    This combination allows to goes way beyond what regular HDL allows in terms of hardware description capabilities. -You can find some documentation about SpinalHDL here :

    +

    VexiiRiscv is implemented in Scala and use SpinalHDL to generate hardware.

    +

    Scala is a general purpose programming language (like C/C++/Java/Rust/…). Staticaly typed, with a garbage collector. +This combination allows to goes way beyond what regular HDL allows in terms of hardware elaboration time capabilities.

    +

    You can find some documentation about SpinalHDL here :

    Plugin

    -

    One main design aspect of VexiiRiscv is that all its hardware is defined inside plugins. +

    One of the main aspect of VexiiRiscv is that all its hardware is defined inside plugins. When you want to instantiate a VexiiRiscv CPU, you “only” need to provide a list of plugins as parameters. So, plugins can be seen as both parameters and hardware definition from a VexiiRiscv perspective.

    So it is quite different from the regular HDL component/module paradigm. Here are the advantagesof this approach :

    @@ -471,7 +473,10 @@

    Pipeline APIhttps://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Libraries/Pipeline/index.html

    +

    More documentation about it in :

    +

    @@ -504,7 +509,7 @@

    Pipeline API

    - Version: master git~d07b8dd 2024-09-08 + Version: master git~d7fa741 2024-09-10

    diff --git a/master/VexiiRiscv/HowToUse/index.html b/master/VexiiRiscv/HowToUse/index.html index 955513f..6d8157b 100644 --- a/master/VexiiRiscv/HowToUse/index.html +++ b/master/VexiiRiscv/HowToUse/index.html @@ -78,8 +78,8 @@
  • Other doc / media / talks
  • Technicalities
  • Navigating the code
    • -
  • Check list
  • About VexRiscv (not VexiiRiscv)
    • +
  • Check list

  • Framework
  • Framework
      @@ -252,10 +252,10 @@

      Introduction

      In a few words, VexiiRiscv :

        -

      • Is an hardware CPU project

        • -

      • Implements the RISC-V instruction set

        • +

      • Is an project which implement an hardware CPU

        • +

      • Follows the RISC-V instruction set

      • Is free / open-source

        • -

      • Should fit well on FPGA and ASIC

        • +

      • Should fit well on FPGA but also be portable to ASIC

      Other doc / media / talks

      @@ -298,23 +298,16 @@

      Technicalities

      Navigating the code

      +

      VexiiRiscv isn’t implmeneted in Verilog nor VHDL. Instead it is written in scala and use the SpinalHDL API to generate hardware. +This allows to leverage an advanced elaboration time paradigme in order to generate hardware in a very flexible manner.

      Here are a few key / typical code examples :

        -

      • The CPU toplevel src/main/scala/vexiiriscv/VexiiRiscv.scala

        • +

      • Integer ALU plugin ; src/main/scala/vexiiriscv/execute/IntAluPlugin.scala

      • A cpu configuration generator : dev/src/main/scala/vexiiriscv/Param.scala

        • +

      • The CPU toplevel src/main/scala/vexiiriscv/VexiiRiscv.scala

      • Some globally shared definitions : src/main/scala/vexiiriscv/Global.scala

        • -

      • Integer ALU plugin ; src/main/scala/vexiiriscv/execute/IntAluPlugin.scala

        • -
      -

      Also on quite important one is to use a text editor / IDE which support curly brace folding and to start with them fully folded, as the code extensively used nested structures.

      -

      -
      -

      Check list

      -

      Here is a list of important assumptions and things to know about :

      -
        -

      • trap/flush/pc request from the pipeline, once asserted one cycle can not be undone. This also mean that while a given instruction is stuck somewhere, if that instruction did raised on of those request, nothing should change the execution path. For instance, a sudden cache line refill completion should not lift the request from the LSU asking a redo (due to cache refill hazard).

        • -

      • In the execute pipeline, stage.up(RS1/RS2) is the value to be used, while stage.down(RS1/RS2) should not be used, as it implement the bypassing for the next stage

        • -

      • Fetch.ctrl(0) isn’t persistent.

      +

      Also due to the nested structure of the code base, a text editor / IDE which support curly brace folding can be very usefull.

      About VexRiscv (not VexiiRiscv)

      @@ -330,6 +323,15 @@

      About VexRiscv (not VexiiRiscv) +

      Check list

      +

      Here is a list of important design assumptions and things to know about :

      +
        +

      • trap/flush/pc request from the pipeline, once asserted one cycle can not be undone. This also mean that while a given instruction is stuck somewhere, if that instruction did raised on of those request, nothing should change the execution path. For instance, a sudden cache line refill completion should not lift the request from the LSU asking a redo (due to cache refill hazard).

        • +

      • In the execute pipeline, stage.up(RS1/RS2) is the value to be used, while stage.down(RS1/RS2) should not be used, as it implement the bypassing for the next stage

        • +

      • Fetch.ctrl(0) isn’t persistent (meaning the PC requested can change at any time)

        • +
      +