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@@ -250,6 +250,11 @@
 
   <section id="fetch">
 <h1>Fetch<a class="headerlink" href="#fetch" title="Permalink to this heading"></a></h1>
+<p>The goal of the fetch pipeline is to provide the CPU with a stream of words in which the instructions to execute are presents.
+So more precisely, the fetch pipeline doesn’t realy have the notion of instruction, but instead, just provide memory aligned chunks of memory block (ex 64 bits).
+Those chunks of memory (word) will later be handled by the “AlignerPlugin” to extract the instruction to be executed (and also handle the decompression in the case of RVC).</p>
+<p>Here is an example of fetch architecture with an instruction cache, branch predictor aswell as a prefetcher.</p>
+<img alt="../../_images/fetch_l1.png" src="../../_images/fetch_l1.png" />
 <p>A few plugins operate in the fetch stage :</p>
 <ul class="simple">
 <li><p>FetchPipelinePlugin</p></li>
@@ -283,6 +288,11 @@ <h2>FetchCachelessPlugin<a class="headerlink" href="#fetchcachelessplugin" title
 <li><p>Allow out of order memory bus responses (for maximal compatibility)</p></li>
 <li><p>Always generate aligned memory accesses</p></li>
 </ul>
+<p>Note that in order to get goo performance on FPGA, you may want to set it with the following config in order to relax timings :</p>
+<ul class="simple">
+<li><p>forkAt = 1</p></li>
+<li><p>joinAt = 2</p></li>
+</ul>
 </section>
 <section id="fetchl1plugin">
 <h2>FetchL1Plugin<a class="headerlink" href="#fetchl1plugin" title="Permalink to this heading"></a></h2>
@@ -310,7 +320,8 @@ <h2>PrefetcherNextLinePlugin<a class="headerlink" href="#prefetchernextlineplugi
 </section>
 <section id="btbplugin">
 <h2>BtbPlugin<a class="headerlink" href="#btbplugin" title="Permalink to this heading"></a></h2>
-<p>See more in the Branch prediction chapter</p>
+<p>This plugin implement most of the branch prediction logic.
+See more in the Branch prediction chapter</p>
 </section>
 <section id="gshareplugin">
 <h2>GSharePlugin<a class="headerlink" href="#gshareplugin" title="Permalink to this heading"></a></h2>
@@ -357,7 +368,7 @@ <h2>HistoryPlugin<a class="headerlink" href="#historyplugin" title="Permalink to
     <!-- source/_templates/footer.html -->
     
     <div class="doc-footer-current-version"><p>
-    Version: master git~d07b8dd 2024-09-08
+    Version: master git~d7fa741 2024-09-10
     </p></div>
     
 
diff --git a/master/VexiiRiscv/Framework/index.html b/master/VexiiRiscv/Framework/index.html
index 8288444..2f3c410 100644
--- a/master/VexiiRiscv/Framework/index.html
+++ b/master/VexiiRiscv/Framework/index.html
@@ -78,8 +78,8 @@
 <li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#other-doc-media-talks">Other doc / media / talks</a></li>
 <li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#technicalities">Technicalities</a></li>
 <li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#navigating-the-code">Navigating the code</a></li>
-<li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#check-list">Check list</a></li>
 <li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#about-vexriscv-not-vexiiriscv">About VexRiscv (not VexiiRiscv)</a></li>
+<li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#check-list">Check list</a></li>
 </ul>
 </li>
 <li class="toctree-l1 current"><a class="current reference internal" href="#">Framework</a><ul>
@@ -256,25 +256,27 @@ <h2>Dependencies<a class="headerlink" href="#dependencies" title="Permalink to t
 <ul class="simple">
 <li><p>Scala : Which will take care of the elaboration</p></li>
 <li><p>SpinalHDL : Which provide a hardware description API</p></li>
-<li><p>Plugin : Which are used to inject hardware in the CPU</p></li>
-<li><p>Fiber : Which allows to define elaboration threads in the plugins</p></li>
+<li><p>Plugin : Which are used to inject hardware in the CPU. Plugins can discover each others.</p></li>
+<li><p>Fiber : Which allows to define elaboration threads (used in the plugins)</p></li>
 <li><p>Retainer : Which allows to block the execution of the elaboration threads waiting on it</p></li>
 <li><p>Database : Which specify a shared scope for all the plugins to share elaboration time stuff</p></li>
 <li><p>spinal.lib.misc.pipeline : Which allow to pipeline things in a very dynamic manner.</p></li>
-<li><p>spinal.lib.logic : Which provide Quine McCluskey to generate logic decoders from the elaboration time specifications</p></li>
+<li><p>spinal.lib.logic : Which provide the Quine McCluskey algorithm to generate logic decoders from the elaboration time specifications</p></li>
 </ul>
 </section>
 <section id="scala-spinalhdl">
 <h2>Scala / SpinalHDL<a class="headerlink" href="#scala-spinalhdl" title="Permalink to this heading"></a></h2>
-<p>This combination allows to goes way beyond what regular HDL allows in terms of hardware description capabilities.
-You can find some documentation about SpinalHDL here :</p>
+<p>VexiiRiscv is implemented in Scala and use SpinalHDL to generate hardware.</p>
+<p>Scala is a general purpose programming language (like C/C++/Java/Rust/…). Staticaly typed, with a garbage collector.
+This combination allows to goes way beyond what regular HDL allows in terms of hardware elaboration time capabilities.</p>
+<p>You can find some documentation about SpinalHDL here :</p>
 <ul class="simple">
 <li><p><a class="reference external" href="https://spinalhdl.github.io/SpinalDoc-RTD/master/index.html">https://spinalhdl.github.io/SpinalDoc-RTD/master/index.html</a></p></li>
 </ul>
 </section>
 <section id="plugin">
 <h2>Plugin<a class="headerlink" href="#plugin" title="Permalink to this heading"></a></h2>
-<p>One main design aspect of VexiiRiscv is that all its hardware is defined inside plugins.
+<p>One of the main aspect of VexiiRiscv is that all its hardware is defined inside plugins.
 When you want to instantiate a VexiiRiscv CPU, you “only” need to provide a list of plugins as parameters.
 So, plugins can be seen as both parameters and hardware definition from a VexiiRiscv perspective.</p>
 <p>So it is quite different from the regular HDL component/module paradigm. Here are the advantagesof this approach :</p>
@@ -471,7 +473,10 @@ <h2>Pipeline API<a class="headerlink" href="#pipeline-api" title="Permalink to t
 <li><p>Allow design space exploration with less paine (retiming, moving around the architecture)</p></li>
 <li><p>Reduce boiler plate code</p></li>
 </ul>
-<p>More documentation about it in <a class="reference external" href="https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Libraries/Pipeline/index.html">https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Libraries/Pipeline/index.html</a></p>
+<p>More documentation about it in :</p>
+<ul class="simple">
+<li><p><a class="reference external" href="https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Libraries/Pipeline/index.html">https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Libraries/Pipeline/index.html</a></p></li>
+</ul>
 </section>
 </section>
 
@@ -504,7 +509,7 @@ <h2>Pipeline API<a class="headerlink" href="#pipeline-api" title="Permalink to t
     <!-- source/_templates/footer.html -->
     
     <div class="doc-footer-current-version"><p>
-    Version: master git~d07b8dd 2024-09-08
+    Version: master git~d7fa741 2024-09-10
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diff --git a/master/VexiiRiscv/HowToUse/index.html b/master/VexiiRiscv/HowToUse/index.html
index 955513f..6d8157b 100644
--- a/master/VexiiRiscv/HowToUse/index.html
+++ b/master/VexiiRiscv/HowToUse/index.html
@@ -78,8 +78,8 @@
 <li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#other-doc-media-talks">Other doc / media / talks</a></li>
 <li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#technicalities">Technicalities</a></li>
 <li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#navigating-the-code">Navigating the code</a></li>
-<li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#check-list">Check list</a></li>
 <li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#about-vexriscv-not-vexiiriscv">About VexRiscv (not VexiiRiscv)</a></li>
+<li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#check-list">Check list</a></li>
 </ul>
 </li>
 <li class="toctree-l1"><a class="reference internal" href="../Framework/index.html">Framework</a><ul>
@@ -424,7 +424,7 @@ <h2>Synthesis / Inferation<a class="headerlink" href="#synthesis-inferation" tit
     <!-- source/_templates/footer.html -->
     
     <div class="doc-footer-current-version"><p>
-    Version: master git~d07b8dd 2024-09-08
+    Version: master git~d7fa741 2024-09-10
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diff --git a/master/VexiiRiscv/Introduction/index.html b/master/VexiiRiscv/Introduction/index.html
index 3e6326e..0f3baab 100644
--- a/master/VexiiRiscv/Introduction/index.html
+++ b/master/VexiiRiscv/Introduction/index.html
@@ -78,8 +78,8 @@
 <li class="toctree-l2"><a class="reference internal" href="#other-doc-media-talks">Other doc / media / talks</a></li>
 <li class="toctree-l2"><a class="reference internal" href="#technicalities">Technicalities</a></li>
 <li class="toctree-l2"><a class="reference internal" href="#navigating-the-code">Navigating the code</a></li>
-<li class="toctree-l2"><a class="reference internal" href="#check-list">Check list</a></li>
 <li class="toctree-l2"><a class="reference internal" href="#about-vexriscv-not-vexiiriscv">About VexRiscv (not VexiiRiscv)</a></li>
+<li class="toctree-l2"><a class="reference internal" href="#check-list">Check list</a></li>
 </ul>
 </li>
 <li class="toctree-l1"><a class="reference internal" href="../Framework/index.html">Framework</a><ul>
@@ -252,10 +252,10 @@
 <h1>Introduction<a class="headerlink" href="#introduction" title="Permalink to this heading"></a></h1>
 <p>In a few words, VexiiRiscv :</p>
 <ul class="simple">
-<li><p>Is an hardware CPU project</p></li>
-<li><p>Implements the RISC-V instruction set</p></li>
+<li><p>Is an project which implement an hardware CPU</p></li>
+<li><p>Follows the RISC-V instruction set</p></li>
 <li><p>Is free / open-source</p></li>
-<li><p>Should fit well on FPGA and ASIC</p></li>
+<li><p>Should fit well on FPGA but also be portable to ASIC</p></li>
 </ul>
 <section id="other-doc-media-talks">
 <h2>Other doc / media / talks<a class="headerlink" href="#other-doc-media-talks" title="Permalink to this heading"></a></h2>
@@ -298,23 +298,16 @@ <h2>Technicalities<a class="headerlink" href="#technicalities" title="Permalink
 </section>
 <section id="navigating-the-code">
 <h2>Navigating the code<a class="headerlink" href="#navigating-the-code" title="Permalink to this heading"></a></h2>
+<p>VexiiRiscv isn’t implmeneted in Verilog nor VHDL. Instead it is written in scala and use the SpinalHDL API to generate hardware.
+This allows to leverage an advanced elaboration time paradigme in order to generate hardware in a very flexible manner.</p>
 <p>Here are a few key / typical code examples :</p>
 <ul class="simple">
-<li><p>The CPU toplevel src/main/scala/vexiiriscv/VexiiRiscv.scala</p></li>
+<li><p>Integer ALU plugin ; src/main/scala/vexiiriscv/execute/IntAluPlugin.scala</p></li>
 <li><p>A cpu configuration generator : dev/src/main/scala/vexiiriscv/Param.scala</p></li>
+<li><p>The CPU toplevel src/main/scala/vexiiriscv/VexiiRiscv.scala</p></li>
 <li><p>Some globally shared definitions : src/main/scala/vexiiriscv/Global.scala</p></li>
-<li><p>Integer ALU plugin ; src/main/scala/vexiiriscv/execute/IntAluPlugin.scala</p></li>
-</ul>
-<p>Also on quite important one is to use a text editor / IDE which support curly brace folding and to start with them fully folded, as the code extensively used nested structures.</p>
-</section>
-<section id="check-list">
-<h2>Check list<a class="headerlink" href="#check-list" title="Permalink to this heading"></a></h2>
-<p>Here is a list of important assumptions and things to know about :</p>
-<ul class="simple">
-<li><p>trap/flush/pc request from the pipeline, once asserted one cycle can not be undone. This also mean that while a given instruction is stuck somewhere, if that instruction did raised on of those request, nothing should change the execution path. For instance, a sudden cache line refill completion should not lift the request from the LSU asking a redo (due to cache refill hazard).</p></li>
-<li><p>In the execute pipeline, stage.up(RS1/RS2) is the value to be used, while stage.down(RS1/RS2) should not be used, as it implement the bypassing for the next stage</p></li>
-<li><p>Fetch.ctrl(0) isn’t persistent.</p></li>
 </ul>
+<p>Also due to the nested structure of the code base, a text editor / IDE which support curly brace folding can be very usefull.</p>
 </section>
 <section id="about-vexriscv-not-vexiiriscv">
 <h2>About VexRiscv (not VexiiRiscv)<a class="headerlink" href="#about-vexriscv-not-vexiiriscv" title="Permalink to this heading"></a></h2>
@@ -330,6 +323,15 @@ <h2>About VexRiscv (not VexiiRiscv)<a class="headerlink" href="#about-vexriscv-n
 </ul>
 <p>So, enough is enough, it was time to start fresh :D</p>
 </section>
+<section id="check-list">
+<h2>Check list<a class="headerlink" href="#check-list" title="Permalink to this heading"></a></h2>
+<p>Here is a list of important design assumptions and things to know about :</p>
+<ul class="simple">
+<li><p>trap/flush/pc request from the pipeline, once asserted one cycle can not be undone. This also mean that while a given instruction is stuck somewhere, if that instruction did raised on of those request, nothing should change the execution path. For instance, a sudden cache line refill completion should not lift the request from the LSU asking a redo (due to cache refill hazard).</p></li>
+<li><p>In the execute pipeline, stage.up(RS1/RS2) is the value to be used, while stage.down(RS1/RS2) should not be used, as it implement the bypassing for the next stage</p></li>
+<li><p>Fetch.ctrl(0) isn’t persistent (meaning the PC requested can change at any time)</p></li>
+</ul>
+</section>
 </section>
 
     <script type="text/javascript">
@@ -361,7 +363,7 @@ <h2>About VexRiscv (not VexiiRiscv)<a class="headerlink" href="#about-vexriscv-n
     <!-- source/_templates/footer.html -->
     
     <div class="doc-footer-current-version"><p>
-    Version: master git~d07b8dd 2024-09-08
+    Version: master git~d7fa741 2024-09-10
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diff --git a/master/VexiiRiscv/Performance/index.html b/master/VexiiRiscv/Performance/index.html
index 4e19110..5ea2e85 100644
--- a/master/VexiiRiscv/Performance/index.html
+++ b/master/VexiiRiscv/Performance/index.html
@@ -78,8 +78,8 @@
 <li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#other-doc-media-talks">Other doc / media / talks</a></li>
 <li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#technicalities">Technicalities</a></li>
 <li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#navigating-the-code">Navigating the code</a></li>
-<li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#check-list">Check list</a></li>
 <li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#about-vexriscv-not-vexiiriscv">About VexRiscv (not VexiiRiscv)</a></li>
+<li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#check-list">Check list</a></li>
 </ul>
 </li>
 <li class="toctree-l1"><a class="reference internal" href="../Framework/index.html">Framework</a><ul>
@@ -280,6 +280,79 @@ <h1>Performance / Area / FMax<a class="headerlink" href="#performance-area-fmax"
 </tbody>
 </table>
 <p>It is too early for area / fmax metric, there is a lot of design space exploration to do which will trade IPC against FMax / Area.</p>
+<p>Here are a few synthesis results :</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span>! Note !
+Those results are with the best speed grade of each family
+In practice, depending what board/FPGA you use, it is common for them to have worst speed grade.
+Also, concerning the area usage, those numbers are a bit inflated because :
+- The SDC constraint stress the timings =&gt; Synthesis use more logic to improve the timings
+- The inputs/outputs of the design are serialized/deserialized (ff+logic cost) to reduce the pin count
+
+rv32i_noBypass -&gt;
+- 0.78 Dhrystone/MHz 0.60 Coremark/MHz
+- Artix 7    -&gt; 210 Mhz 1182 LUT 1759 FF
+- Cyclone V  -&gt; 159 Mhz 1,015 ALMs
+- Cyclone IV -&gt; 130 Mhz 1,987 LUT 2,017 FF
+- Trion      -&gt; 94 Mhz LUT 1847   FF 1990
+- Titanium   -&gt; 320 Mhz LUT 2005   FF 2030
+
+rv32i -&gt;
+- 1.12 Dhrystone/MHz 0.87 Coremark/MHz
+- Artix 7    -&gt; 206 Mhz 1413 LUT 1761 FF
+- Cyclone V  -&gt; 138 Mhz 1,244 ALMs
+- Cyclone IV -&gt; 124 Mhz 2,188 LUT 2,019 FF
+- Trion      -&gt; 78 Mhz LUT 2252   FF 1962
+- Titanium   -&gt; 300 Mhz LUT 2347   FF 2000
+
+rv64i -&gt;
+- 1.18 Dhrystone/MHz 0.77 Coremark/MHz
+- Artix 7    -&gt; 186 Mhz 2157 LUT 2332 FF
+- Cyclone V  -&gt; 117 Mhz 1,760 ALMs
+- Cyclone IV -&gt; 113 Mhz 3,432 LUT 2,770 FF
+- Trion      -&gt; 83 Mhz LUT 3883   FF 2681
+- Titanium   -&gt; 278 Mhz LUT 3909   FF 2783
+
+rv32im -&gt;
+- 1.20 Dhrystone/MHz 2.70 Coremark/MHz
+- Artix 7    -&gt; 190 Mhz 1815 LUT 2078 FF
+- Cyclone V  -&gt; 131 Mhz 1,474 ALMs
+- Cyclone IV -&gt; 125 Mhz 2,781 LUT 2,266 FF
+- Trion      -&gt; 83 Mhz LUT 2643   FF 2209
+- Titanium   -&gt; 324 Mhz LUT 2685   FF 2279
+
+rv32im_branchPredict -&gt;
+- 1.45 Dhrystone/MHz 2.99 Coremark/MHz
+- Artix 7    -&gt; 195 Mhz 2066 LUT 2438 FF
+- Cyclone V  -&gt; 136 Mhz 1,648 ALMs
+- Cyclone IV -&gt; 117 Mhz 3,093 LUT 2,597 FF
+- Trion      -&gt; 86 Mhz LUT 2963   FF 2568
+- Titanium   -&gt; 327 Mhz LUT 3015   FF 2636
+
+rv32im_branchPredict_cached8k8k -&gt;
+- 1.45 Dhrystone/MHz 2.97 Coremark/MHz
+- Artix 7    -&gt; 210 Mhz 2721 LUT 3477 FF
+- Cyclone V  -&gt; 137 Mhz 1,953 ALMs
+- Cyclone IV -&gt; 127 Mhz 3,648 LUT 3,153 FF
+- Trion      -&gt; 93 Mhz LUT 3388   FF 3204
+- Titanium   -&gt; 314 Mhz LUT 3432   FF 3274
+
+rv32imasu_cached_branchPredict_cached8k8k_linux -&gt;
+- 1.45 Dhrystone/MHz 2.96 Coremark/MHz
+- Artix 7    -&gt; 199 Mhz 3351 LUT 3833 FF
+- Cyclone V  -&gt; 131 Mhz 2,612 ALMs
+- Cyclone IV -&gt; 109 Mhz 4,909 LUT 3,897 FF
+- Trion      -&gt; 73 Mhz LUT 4367   FF 3613
+- Titanium   -&gt; 270 Mhz LUT 4409   FF 3724
+
+rv32im_branchPredictStressed_cached8k8k_ipcMax_lateAlu -&gt;
+- 1.74 Dhrystone/MHz 3.41 Coremark/MHz
+- Artix 7    -&gt; 140 Mhz 3247 LUT 3755 FF
+- Cyclone V  -&gt; 99 Mhz 2,477 ALMs
+- Cyclone IV -&gt; 85 Mhz 4,835 LUT 3,765 FF
+- Trion      -&gt; 60 Mhz LUT 4438   FF 3832
+- Titanium   -&gt; 228 Mhz LUT 4459   FF 3963
+</pre></div>
+</div>
 <section id="tuning">
 <h2>Tuning<a class="headerlink" href="#tuning" title="Permalink to this heading"></a></h2>
 <p>VexiiRiscv can scale a lot in function of its plugins/parameters. It can scale from simple microcontroller
@@ -330,7 +403,7 @@ <h2>Tuning<a class="headerlink" href="#tuning" title="Permalink to this heading"
     <!-- source/_templates/footer.html -->
     
     <div class="doc-footer-current-version"><p>
-    Version: master git~d07b8dd 2024-09-08
+    Version: master git~d7fa741 2024-09-10
     </p></div>
     
 
diff --git a/master/VexiiRiscv/Soc/index.html b/master/VexiiRiscv/Soc/index.html
index e3b164c..81f0514 100644
--- a/master/VexiiRiscv/Soc/index.html
+++ b/master/VexiiRiscv/Soc/index.html
@@ -78,8 +78,8 @@
 <li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#other-doc-media-talks">Other doc / media / talks</a></li>
 <li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#technicalities">Technicalities</a></li>
 <li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#navigating-the-code">Navigating the code</a></li>
-<li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#check-list">Check list</a></li>
 <li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#about-vexriscv-not-vexiiriscv">About VexRiscv (not VexiiRiscv)</a></li>
+<li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#check-list">Check list</a></li>
 </ul>
 </li>
 <li class="toctree-l1"><a class="reference internal" href="../Framework/index.html">Framework</a><ul>
@@ -288,7 +288,7 @@ <h1>SoC<a class="headerlink" href="#soc" title="Permalink to this heading"></
     <!-- source/_templates/footer.html -->
     
     <div class="doc-footer-current-version"><p>
-    Version: master git~d07b8dd 2024-09-08
+    Version: master git~d7fa741 2024-09-10
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diff --git a/master/VexiiRiscv/Soc/litex.html b/master/VexiiRiscv/Soc/litex.html
index 6a1a3b1..7907af7 100644
--- a/master/VexiiRiscv/Soc/litex.html
+++ b/master/VexiiRiscv/Soc/litex.html
@@ -77,8 +77,8 @@
 <li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#other-doc-media-talks">Other doc / media / talks</a></li>
 <li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#technicalities">Technicalities</a></li>
 <li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#navigating-the-code">Navigating the code</a></li>
-<li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#check-list">Check list</a></li>
 <li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#about-vexriscv-not-vexiiriscv">About VexRiscv (not VexiiRiscv)</a></li>
+<li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#check-list">Check list</a></li>
 </ul>
 </li>
 <li class="toctree-l1"><a class="reference internal" href="../Framework/index.html">Framework</a><ul>
@@ -328,7 +328,7 @@ <h1>Litex<a class="headerlink" href="#litex" title="Permalink to this heading">
     <!-- source/_templates/footer.html -->
     
     <div class="doc-footer-current-version"><p>
-    Version: master git~d07b8dd 2024-09-08
+    Version: master git~d7fa741 2024-09-10
     </p></div>
     
 
diff --git a/master/VexiiRiscv/Soc/microsoc.html b/master/VexiiRiscv/Soc/microsoc.html
index b472f1b..9077df4 100644
--- a/master/VexiiRiscv/Soc/microsoc.html
+++ b/master/VexiiRiscv/Soc/microsoc.html
@@ -78,8 +78,8 @@
 <li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#other-doc-media-talks">Other doc / media / talks</a></li>
 <li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#technicalities">Technicalities</a></li>
 <li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#navigating-the-code">Navigating the code</a></li>
-<li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#check-list">Check list</a></li>
 <li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#about-vexriscv-not-vexiiriscv">About VexRiscv (not VexiiRiscv)</a></li>
+<li class="toctree-l2"><a class="reference internal" href="../Introduction/index.html#check-list">Check list</a></li>
 </ul>
 </li>
 <li class="toctree-l1"><a class="reference internal" href="../Framework/index.html">Framework</a><ul>
@@ -300,7 +300,7 @@ <h1>MicroSoc<a class="headerlink" href="#microsoc" title="Permalink to this head
     <!-- source/_templates/footer.html -->
     
     <div class="doc-footer-current-version"><p>
-    Version: master git~d07b8dd 2024-09-08
+    Version: master git~d7fa741 2024-09-10
     </p></div>
     
 
diff --git a/master/_images/fetch_l1.png b/master/_images/fetch_l1.png
new file mode 100644
index 0000000..28da453
Binary files /dev/null and b/master/_images/fetch_l1.png differ
diff --git a/master/_sources/VexiiRiscv/Fetch/index.rst.txt b/master/_sources/VexiiRiscv/Fetch/index.rst.txt
index 3e35ae1..42cf571 100644
--- a/master/_sources/VexiiRiscv/Fetch/index.rst.txt
+++ b/master/_sources/VexiiRiscv/Fetch/index.rst.txt
@@ -2,6 +2,16 @@
 Fetch
 =====
 
+The goal of the fetch pipeline is to provide the CPU with a stream of words in which the instructions to execute are presents.
+So more precisely, the fetch pipeline doesn't realy have the notion of instruction, but instead, just provide memory aligned chunks of memory block (ex 64 bits).
+Those chunks of memory (word) will later be handled by the "AlignerPlugin" to extract the instruction to be executed (and also handle the decompression in the case of RVC).
+
+Here is an example of fetch architecture with an instruction cache, branch predictor aswell as a prefetcher.
+
+.. image:: /asset/picture/fetch_l1.png
+
+
+
 A few plugins operate in the fetch stage :
 
 - FetchPipelinePlugin
@@ -40,6 +50,12 @@ Will :
 - Allow out of order memory bus responses (for maximal compatibility)
 - Always generate aligned memory accesses
 
+Note that in order to get goo performance on FPGA, you may want to set it with the following config in order to relax timings :
+
+- forkAt = 1
+- joinAt = 2
+
+
 
 FetchL1Plugin
 -------------
@@ -75,6 +91,7 @@ The prefetcher can be turned off by setting the CSR 0x7FF bit 0.
 BtbPlugin
 ---------
 
+This plugin implement most of the branch prediction logic. 
 See more in the Branch prediction chapter
 
 GSharePlugin
diff --git a/master/_sources/VexiiRiscv/Framework/index.rst.txt b/master/_sources/VexiiRiscv/Framework/index.rst.txt
index 280bf2f..f86db34 100644
--- a/master/_sources/VexiiRiscv/Framework/index.rst.txt
+++ b/master/_sources/VexiiRiscv/Framework/index.rst.txt
@@ -9,18 +9,22 @@ VexRiscv is based on a few tools / API
 
 - Scala : Which will take care of the elaboration
 - SpinalHDL : Which provide a hardware description API
-- Plugin : Which are used to inject hardware in the CPU
-- Fiber : Which allows to define elaboration threads in the plugins
+- Plugin : Which are used to inject hardware in the CPU. Plugins can discover each others.
+- Fiber : Which allows to define elaboration threads (used in the plugins)
 - Retainer : Which allows to block the execution of the elaboration threads waiting on it
 - Database : Which specify a shared scope for all the plugins to share elaboration time stuff
 - spinal.lib.misc.pipeline : Which allow to pipeline things in a very dynamic manner.
-- spinal.lib.logic : Which provide Quine McCluskey to generate logic decoders from the elaboration time specifications
+- spinal.lib.logic : Which provide the Quine McCluskey algorithm to generate logic decoders from the elaboration time specifications
 
 
 Scala / SpinalHDL
 -----------------
 
-This combination allows to goes way beyond what regular HDL allows in terms of hardware description capabilities.
+VexiiRiscv is implemented in Scala and use SpinalHDL to generate hardware.
+
+Scala is a general purpose programming language (like C/C++/Java/Rust/...). Staticaly typed, with a garbage collector.
+This combination allows to goes way beyond what regular HDL allows in terms of hardware elaboration time capabilities.
+
 You can find some documentation about SpinalHDL here :
 
 - https://spinalhdl.github.io/SpinalDoc-RTD/master/index.html
@@ -28,7 +32,7 @@ You can find some documentation about SpinalHDL here :
 Plugin
 ------
 
-One main design aspect of VexiiRiscv is that all its hardware is defined inside plugins.
+One of the main aspect of VexiiRiscv is that all its hardware is defined inside plugins.
 When you want to instantiate a VexiiRiscv CPU, you "only" need to provide a list of plugins as parameters.
 So, plugins can be seen as both parameters and hardware definition from a VexiiRiscv perspective.
 
@@ -242,5 +246,7 @@ In short, the design use a pipeline API in order to :
 - Allow design space exploration with less paine (retiming, moving around the architecture)
 - Reduce boiler plate code
 
-More documentation about it in https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Libraries/Pipeline/index.html
+More documentation about it in :
+
+- https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Libraries/Pipeline/index.html
 
diff --git a/master/_sources/VexiiRiscv/Introduction/index.rst.txt b/master/_sources/VexiiRiscv/Introduction/index.rst.txt
index 7292c82..866d135 100644
--- a/master/_sources/VexiiRiscv/Introduction/index.rst.txt
+++ b/master/_sources/VexiiRiscv/Introduction/index.rst.txt
@@ -3,10 +3,10 @@ Introduction
 
 In a few words, VexiiRiscv :
 
-- Is an hardware CPU project
-- Implements the RISC-V instruction set
+- Is an project which implement an hardware CPU
+- Follows the RISC-V instruction set
 - Is free / open-source
-- Should fit well on FPGA and ASIC
+- Should fit well on FPGA but also be portable to ASIC
 
 Other doc / media / talks
 -------------------------
@@ -53,23 +53,18 @@ Here is a diagram with 2 issue / early+late alu / 6 stages configuration (note t
 Navigating the code
 -------------------
 
+VexiiRiscv isn't implmeneted in Verilog nor VHDL. Instead it is written in scala and use the SpinalHDL API to generate hardware.
+This allows to leverage an advanced elaboration time paradigme in order to generate hardware in a very flexible manner.
+
 Here are a few key / typical code examples :
 
-- The CPU toplevel src/main/scala/vexiiriscv/VexiiRiscv.scala
+- Integer ALU plugin ; src/main/scala/vexiiriscv/execute/IntAluPlugin.scala
 - A cpu configuration generator : dev/src/main/scala/vexiiriscv/Param.scala
+- The CPU toplevel src/main/scala/vexiiriscv/VexiiRiscv.scala
 - Some globally shared definitions : src/main/scala/vexiiriscv/Global.scala
-- Integer ALU plugin ; src/main/scala/vexiiriscv/execute/IntAluPlugin.scala
 
-Also on quite important one is to use a text editor / IDE which support curly brace folding and to start with them fully folded, as the code extensively used nested structures.
+Also due to the nested structure of the code base, a text editor / IDE which support curly brace folding can be very usefull.
 
-Check list
-----------
-
-Here is a list of important assumptions and things to know about :
-
-- trap/flush/pc request from the pipeline, once asserted one cycle can not be undone. This also mean that while a given instruction is stuck somewhere, if that instruction did raised on of those request, nothing should change the execution path. For instance, a sudden cache line refill completion should not lift the request from the LSU asking a redo (due to cache refill hazard).
-- In the execute pipeline, stage.up(RS1/RS2) is the value to be used, while stage.down(RS1/RS2) should not be used, as it implement the bypassing for the next stage
-- Fetch.ctrl(0) isn't persistent.
 
 About VexRiscv (not VexiiRiscv)
 -------------------------------
@@ -85,3 +80,13 @@ There is few reasons why VexiiRiscv exists instead of doing incremental upgrade
 - The VexRiscv verification infrastructure based on its own golden model isn't great.
 
 So, enough is enough, it was time to start fresh :D
+
+Check list
+----------
+
+Here is a list of important design assumptions and things to know about :
+
+- trap/flush/pc request from the pipeline, once asserted one cycle can not be undone. This also mean that while a given instruction is stuck somewhere, if that instruction did raised on of those request, nothing should change the execution path. For instance, a sudden cache line refill completion should not lift the request from the LSU asking a redo (due to cache refill hazard).
+- In the execute pipeline, stage.up(RS1/RS2) is the value to be used, while stage.down(RS1/RS2) should not be used, as it implement the bypassing for the next stage
+- Fetch.ctrl(0) isn't persistent (meaning the PC requested can change at any time)
+
diff --git a/master/_sources/VexiiRiscv/Performance/index.rst.txt b/master/_sources/VexiiRiscv/Performance/index.rst.txt
index abb8a8c..af26640 100644
--- a/master/_sources/VexiiRiscv/Performance/index.rst.txt
+++ b/master/_sources/VexiiRiscv/Performance/index.rst.txt
@@ -25,6 +25,81 @@ It is too early for area / fmax metric, there is a lot of design space explorati
 
 
 
+Here are a few synthesis results : 
+
+.. code-block:: 
+
+    ! Note ! 
+    Those results are with the best speed grade of each family
+    In practice, depending what board/FPGA you use, it is common for them to have worst speed grade.
+    Also, concerning the area usage, those numbers are a bit inflated because : 
+    - The SDC constraint stress the timings => Synthesis use more logic to improve the timings
+    - The inputs/outputs of the design are serialized/deserialized (ff+logic cost) to reduce the pin count
+
+    rv32i_noBypass ->
+    - 0.78 Dhrystone/MHz 0.60 Coremark/MHz
+    - Artix 7    -> 210 Mhz 1182 LUT 1759 FF 
+    - Cyclone V  -> 159 Mhz 1,015 ALMs
+    - Cyclone IV -> 130 Mhz 1,987 LUT 2,017 FF 
+    - Trion      -> 94 Mhz LUT 1847   FF 1990
+    - Titanium   -> 320 Mhz LUT 2005   FF 2030
+
+    rv32i ->
+    - 1.12 Dhrystone/MHz 0.87 Coremark/MHz
+    - Artix 7    -> 206 Mhz 1413 LUT 1761 FF 
+    - Cyclone V  -> 138 Mhz 1,244 ALMs
+    - Cyclone IV -> 124 Mhz 2,188 LUT 2,019 FF 
+    - Trion      -> 78 Mhz LUT 2252   FF 1962
+    - Titanium   -> 300 Mhz LUT 2347   FF 2000
+
+    rv64i ->
+    - 1.18 Dhrystone/MHz 0.77 Coremark/MHz
+    - Artix 7    -> 186 Mhz 2157 LUT 2332 FF 
+    - Cyclone V  -> 117 Mhz 1,760 ALMs
+    - Cyclone IV -> 113 Mhz 3,432 LUT 2,770 FF 
+    - Trion      -> 83 Mhz LUT 3883   FF 2681
+    - Titanium   -> 278 Mhz LUT 3909   FF 2783
+
+    rv32im ->
+    - 1.20 Dhrystone/MHz 2.70 Coremark/MHz
+    - Artix 7    -> 190 Mhz 1815 LUT 2078 FF 
+    - Cyclone V  -> 131 Mhz 1,474 ALMs
+    - Cyclone IV -> 125 Mhz 2,781 LUT 2,266 FF 
+    - Trion      -> 83 Mhz LUT 2643   FF 2209
+    - Titanium   -> 324 Mhz LUT 2685   FF 2279
+
+    rv32im_branchPredict ->
+    - 1.45 Dhrystone/MHz 2.99 Coremark/MHz
+    - Artix 7    -> 195 Mhz 2066 LUT 2438 FF 
+    - Cyclone V  -> 136 Mhz 1,648 ALMs
+    - Cyclone IV -> 117 Mhz 3,093 LUT 2,597 FF 
+    - Trion      -> 86 Mhz LUT 2963   FF 2568
+    - Titanium   -> 327 Mhz LUT 3015   FF 2636
+
+    rv32im_branchPredict_cached8k8k ->
+    - 1.45 Dhrystone/MHz 2.97 Coremark/MHz
+    - Artix 7    -> 210 Mhz 2721 LUT 3477 FF 
+    - Cyclone V  -> 137 Mhz 1,953 ALMs
+    - Cyclone IV -> 127 Mhz 3,648 LUT 3,153 FF 
+    - Trion      -> 93 Mhz LUT 3388   FF 3204
+    - Titanium   -> 314 Mhz LUT 3432   FF 3274
+
+    rv32imasu_cached_branchPredict_cached8k8k_linux ->
+    - 1.45 Dhrystone/MHz 2.96 Coremark/MHz
+    - Artix 7    -> 199 Mhz 3351 LUT 3833 FF 
+    - Cyclone V  -> 131 Mhz 2,612 ALMs
+    - Cyclone IV -> 109 Mhz 4,909 LUT 3,897 FF 
+    - Trion      -> 73 Mhz LUT 4367   FF 3613
+    - Titanium   -> 270 Mhz LUT 4409   FF 3724
+
+    rv32im_branchPredictStressed_cached8k8k_ipcMax_lateAlu ->
+    - 1.74 Dhrystone/MHz 3.41 Coremark/MHz
+    - Artix 7    -> 140 Mhz 3247 LUT 3755 FF 
+    - Cyclone V  -> 99 Mhz 2,477 ALMs
+    - Cyclone IV -> 85 Mhz 4,835 LUT 3,765 FF 
+    - Trion      -> 60 Mhz LUT 4438   FF 3832
+    - Titanium   -> 228 Mhz LUT 4459   FF 3963
+
 
 Tuning
 ------
diff --git a/master/artefacts/VexiiRiscv_docs-master-SingleHTML.zip b/master/artefacts/VexiiRiscv_docs-master-SingleHTML.zip
index 0a731a6..ed2394f 100644
Binary files a/master/artefacts/VexiiRiscv_docs-master-SingleHTML.zip and b/master/artefacts/VexiiRiscv_docs-master-SingleHTML.zip differ
diff --git a/master/artefacts/VexiiRiscv_docs-master.pdf b/master/artefacts/VexiiRiscv_docs-master.pdf
index 657c7ec..7cf3381 100644
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diff --git a/master/genindex.html b/master/genindex.html
index 0693792..b967542 100644
--- a/master/genindex.html
+++ b/master/genindex.html
@@ -75,8 +75,8 @@
 <li class="toctree-l2"><a class="reference internal" href="VexiiRiscv/Introduction/index.html#other-doc-media-talks">Other doc / media / talks</a></li>
 <li class="toctree-l2"><a class="reference internal" href="VexiiRiscv/Introduction/index.html#technicalities">Technicalities</a></li>
 <li class="toctree-l2"><a class="reference internal" href="VexiiRiscv/Introduction/index.html#navigating-the-code">Navigating the code</a></li>
-<li class="toctree-l2"><a class="reference internal" href="VexiiRiscv/Introduction/index.html#check-list">Check list</a></li>
 <li class="toctree-l2"><a class="reference internal" href="VexiiRiscv/Introduction/index.html#about-vexriscv-not-vexiiriscv">About VexRiscv (not VexiiRiscv)</a></li>
+<li class="toctree-l2"><a class="reference internal" href="VexiiRiscv/Introduction/index.html#check-list">Check list</a></li>
 </ul>
 </li>
 <li class="toctree-l1"><a class="reference internal" href="VexiiRiscv/Framework/index.html">Framework</a><ul>
@@ -253,7 +253,7 @@ <h1 id="index">Index</h1>
     <!-- source/_templates/footer.html -->
     
     <div class="doc-footer-current-version"><p>
-    Version: master git~d07b8dd 2024-09-08
+    Version: master git~d7fa741 2024-09-10
     </p></div>
     
 
diff --git a/master/index.html b/master/index.html
index 63d6745..5d922d5 100644
--- a/master/index.html
+++ b/master/index.html
@@ -77,8 +77,8 @@
 <li class="toctree-l2"><a class="reference internal" href="VexiiRiscv/Introduction/index.html#other-doc-media-talks">Other doc / media / talks</a></li>
 <li class="toctree-l2"><a class="reference internal" href="VexiiRiscv/Introduction/index.html#technicalities">Technicalities</a></li>
 <li class="toctree-l2"><a class="reference internal" href="VexiiRiscv/Introduction/index.html#navigating-the-code">Navigating the code</a></li>
-<li class="toctree-l2"><a class="reference internal" href="VexiiRiscv/Introduction/index.html#check-list">Check list</a></li>
 <li class="toctree-l2"><a class="reference internal" href="VexiiRiscv/Introduction/index.html#about-vexriscv-not-vexiiriscv">About VexRiscv (not VexiiRiscv)</a></li>
+<li class="toctree-l2"><a class="reference internal" href="VexiiRiscv/Introduction/index.html#check-list">Check list</a></li>
 </ul>
 </li>
 <li class="toctree-l1"><a class="reference internal" href="VexiiRiscv/Framework/index.html">Framework</a><ul>
@@ -294,7 +294,7 @@ <h1>VexiiRiscv<a class="headerlink" href="#vexiiriscv" title="Permalink to this
     <!-- source/_templates/footer.html -->
     
     <div class="doc-footer-current-version"><p>
-    Version: master git~d07b8dd 2024-09-08
+    Version: master git~d7fa741 2024-09-10
     </p></div>
     
 
diff --git a/master/search.html b/master/search.html
index 363a856..09e7827 100644
--- a/master/search.html
+++ b/master/search.html
@@ -78,8 +78,8 @@
 <li class="toctree-l2"><a class="reference internal" href="VexiiRiscv/Introduction/index.html#other-doc-media-talks">Other doc / media / talks</a></li>
 <li class="toctree-l2"><a class="reference internal" href="VexiiRiscv/Introduction/index.html#technicalities">Technicalities</a></li>
 <li class="toctree-l2"><a class="reference internal" href="VexiiRiscv/Introduction/index.html#navigating-the-code">Navigating the code</a></li>
-<li class="toctree-l2"><a class="reference internal" href="VexiiRiscv/Introduction/index.html#check-list">Check list</a></li>
 <li class="toctree-l2"><a class="reference internal" href="VexiiRiscv/Introduction/index.html#about-vexriscv-not-vexiiriscv">About VexRiscv (not VexiiRiscv)</a></li>
+<li class="toctree-l2"><a class="reference internal" href="VexiiRiscv/Introduction/index.html#check-list">Check list</a></li>
 </ul>
 </li>
 <li class="toctree-l1"><a class="reference internal" href="VexiiRiscv/Framework/index.html">Framework</a><ul>
@@ -260,7 +260,7 @@
     <!-- source/_templates/footer.html -->
     
     <div class="doc-footer-current-version"><p>
-    Version: master git~d07b8dd 2024-09-08
+    Version: master git~d7fa741 2024-09-10
     </p></div>
     
 
diff --git a/master/searchindex.js b/master/searchindex.js
index f600954..febe8c2 100644
--- a/master/searchindex.js
+++ b/master/searchindex.js
@@ -1 +1 @@
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