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I am planning to customise the VexRiscv core and implement new plugin for processing in memory capabilities using one basic instruction lets say PIM_MEM_CPY which will copy the contents from the memory and paste it in the memory itself. Can this be done in a RISC way on this core?
Thanks
The text was updated successfully, but these errors were encountered:
I plan to have a co-processor (PIM processor) in/near the memory for memory-intensive tasks. So the main task for this custom instruction will be to establish a communication between the CPU and the PIM processor to divide the memory-intensive tasks and establish a handshake. Any suggestions / relevant resources will be useful.
Hi ,
I am planning to customise the VexRiscv core and implement new plugin for processing in memory capabilities using one basic instruction lets say PIM_MEM_CPY which will copy the contents from the memory and paste it in the memory itself. Can this be done in a RISC way on this core?
Thanks
The text was updated successfully, but these errors were encountered: