From 7fac668e38ac4d2a496605c8161b8dd33bd7185e Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 20 Sep 2024 15:40:36 +0200 Subject: [PATCH] Fix CsrPlugin FPU access --- src/main/scala/vexriscv/plugin/CsrPlugin.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 4ae6fc83..2fe4aa97 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -784,7 +784,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep buffer.ready := injectionPort.fire val fpu = withDebugFpuAccess generate new Area { val access = service(classOf[FpuPlugin]).access - access.start := buffer.valid && buffer.op === DebugDmToHartOp.REG_READ || buffer.op === DebugDmToHartOp.REG_WRITE + access.start := buffer.valid && (buffer.op === DebugDmToHartOp.REG_READ || buffer.op === DebugDmToHartOp.REG_WRITE) access.regId := buffer.address access.write := buffer.op === DebugDmToHartOp.REG_WRITE access.writeData := dataCsrw.value.take(2).asBits