From 7812bc66152c745509fd642b8e3efe940e6e843b Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Tue, 5 Mar 2024 11:45:53 +0100 Subject: [PATCH 1/2] VexRiscvSmpCluster add more debug trigger options --- .../scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala index 854828f3..78afa774 100644 --- a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala +++ b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala @@ -255,7 +255,9 @@ object VexRiscvSmpClusterGen { withInstructionCache : Boolean = true, forceMisa : Boolean = false, forceMscratch : Boolean = false, - privilegedDebug : Boolean = false, + privilegedDebug: Boolean = false, + privilegedDebugTriggers: Int = 2, + privilegedDebugTriggersLsu: Boolean = false, csrFull : Boolean = false ) = { assert(iCacheSize/iCacheWays <= 4096, "Instruction cache ways can't be bigger than 4096 bytes") @@ -264,7 +266,12 @@ object VexRiscvSmpClusterGen { val misa = Riscv.misaToInt(s"ima${if(withFloat) "f" else ""}${if(withDouble) "d" else ""}${if(rvc) "c" else ""}${if(withSupervisor) "s" else ""}") val csrConfig = if(withSupervisor){ - var c = CsrPluginConfig.openSbi(mhartid = hartId, misa = misa).copy(utimeAccess = CsrAccess.READ_ONLY, withPrivilegedDebug = privilegedDebug) + var c = CsrPluginConfig.openSbi(mhartid = hartId, misa = misa).copy( + utimeAccess = CsrAccess.READ_ONLY, + withPrivilegedDebug = privilegedDebug, + debugTriggers = privilegedDebugTriggers, + debugTriggersLsu = privilegedDebugTriggersLsu + ) if(csrFull){ c = c.copy( mcauseAccess = CsrAccess.READ_WRITE, From 2cd19c89b13a0dee4441a6f1fb71eb434946ddf6 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 12 Feb 2024 12:47:31 +0100 Subject: [PATCH 2/2] Revert unwanted push IBusDBusCachedTightlyCoupledRam --- src/main/scala/vexriscv/VexRiscvBmbGenerator.scala | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala b/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala index e42d82be..50cd15b8 100644 --- a/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala +++ b/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala @@ -120,10 +120,6 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener case _ => } - config.plugins += new IBusDBusCachedTightlyCoupledRam( - mapping = SizeMapping(0x20000000, 0x1000) - ) - val cpu = new VexRiscv(config) def doExport(value : => Any, postfix : String) = { sexport(Handle(value).setCompositeName(VexRiscvBmbGenerator.this, postfix))