From 143eb08e34c8e7660156d9a0877633c64ff9e7f2 Mon Sep 17 00:00:00 2001
From: Andreas Wallner <A.Wallner@innovative-solutions.at>
Date: Tue, 22 Aug 2023 02:13:23 +0200
Subject: [PATCH] Fix VCS blackbox simulation notes

---
 source/SpinalHDL/Simulation/install/VCS.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/source/SpinalHDL/Simulation/install/VCS.rst b/source/SpinalHDL/Simulation/install/VCS.rst
index 37310785009..615a7b33abb 100644
--- a/source/SpinalHDL/Simulation/install/VCS.rst
+++ b/source/SpinalHDL/Simulation/install/VCS.rst
@@ -126,4 +126,4 @@ Sometimes, IP vendors will provide you with some design entites in Verilog/VHDL
 The integration can done by following two ways:
 
 1. In a ``Blackbox`` definition, use ``addRTLPath(path: String)`` to assign a external Verilog/VHDL file to this blackbox.
-2. Use the method ``mergeRTLSource(fileName: String=null)`` of ``SpinalConfig``.
+2. Use the method ``mergeRTLSource(fileName: String=null)`` of ``SpinalReport``.