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-Wconversion Flag Does Not Warn on Ternary Expression #1151

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hankhsu1996 opened this issue Oct 10, 2024 · 2 comments
Open

-Wconversion Flag Does Not Warn on Ternary Expression #1151

hankhsu1996 opened this issue Oct 10, 2024 · 2 comments

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@hankhsu1996
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Describe the bug

When using a ternary expression in SystemVerilog code, slang does not issue a width mismatch warning when the -Wconversion flag is enabled. This behavior is inconsistent with direct assignments where the warning is correctly triggered.

To Reproduce

Run the following code with slang and the -Wconversion flag:

module test;
  initial begin
    static int a = 3;
    static int b = 5;
    static bit cond = 1;
    static longint result = 7;
    result = cond ? a : b;
  end
endmodule

When the assignment uses a ternary expression (result = cond ? a : b;), there is no warning, despite the width mismatch. However, when assigning directly without the ternary (result = a;), slang correctly triggers a warning.

@MikePopoloski
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Fixed in dd2addd

@hankhsu1996
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@MikePopoloski

I would like to reopen this issue because I believe it is not fully resolved. After further testing, I noticed that when one branch is correct and the other branch involves width expansion, no warning is issued. However, if the implicit conversion results in width truncation, slang does trigger a warning.

Here is an example that demonstrates the issue:

module test;
  initial begin
    static int a = 3;
    static int b = 5;
    static bit cond = 1;
    static longint result = 7;
    result = cond ? a : longint'(b);
  end
endmodule

In this case, I would expect slang to report a width expansion warning, but now it does not. Could you please take a look at this?
Thank you!

@MikePopoloski MikePopoloski reopened this Jan 8, 2025
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