From f5504896dd770b781686044958cbb14f7c93b83e Mon Sep 17 00:00:00 2001
From: root <sina@hyperdbg.org>
Date: Fri, 23 Feb 2024 16:56:59 +0900
Subject: [PATCH] add generated output

---
 generated/Blinky.sv      | 26 ++++++++++++++++++++++++++
 generated/filelist.f     |  1 +
 src/main/scala/top.scala |  8 +++++++-
 3 files changed, 34 insertions(+), 1 deletion(-)
 create mode 100644 generated/Blinky.sv
 create mode 100644 generated/filelist.f

diff --git a/generated/Blinky.sv b/generated/Blinky.sv
new file mode 100644
index 0000000..5f38007
--- /dev/null
+++ b/generated/Blinky.sv
@@ -0,0 +1,26 @@
+// Generated by CIRCT firtool-1.62.0
+module Blinky(
+  input  clock,
+         reset,
+  output io_led0
+);
+
+  reg       led;
+  reg [8:0] counterWrap_c_value;
+  always @(posedge clock) begin
+    if (reset) begin
+      led <= 1'h0;
+      counterWrap_c_value <= 9'h0;
+    end
+    else begin
+      automatic logic counterWrap = counterWrap_c_value == 9'h1F3;
+      led <= counterWrap ^ led;
+      if (counterWrap)
+        counterWrap_c_value <= 9'h0;
+      else
+        counterWrap_c_value <= counterWrap_c_value + 9'h1;
+    end
+  end // always @(posedge)
+  assign io_led0 = led;
+endmodule
+
diff --git a/generated/filelist.f b/generated/filelist.f
new file mode 100644
index 0000000..896f8ad
--- /dev/null
+++ b/generated/filelist.f
@@ -0,0 +1 @@
+Blinky.sv
diff --git a/src/main/scala/top.scala b/src/main/scala/top.scala
index 9316ab3..68391f7 100644
--- a/src/main/scala/top.scala
+++ b/src/main/scala/top.scala
@@ -22,7 +22,13 @@ object Main extends App {
   println(
     ChiselStage.emitSystemVerilog(
       new Blinky(1000),
-      firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")
+      firtoolOpts = Array(
+      "-disable-all-randomization", 
+      "-strip-debug-info",
+      "--split-verilog", // The intention for this argument (and next argument) is to separate generated files.
+      "-o",
+      "generated/",
+      )
     )
   )
 }