diff --git a/.gitignore b/.gitignore index 5468655..3d192aa 100644 --- a/.gitignore +++ b/.gitignore @@ -340,12 +340,12 @@ project/plugins/project/ hs_err_pid* # Visual Studio Code -.vscode/* -!.vscode/settings.json -!.vscode/tasks.json -!.vscode/launch.json -!.vscode/extensions.json -!.vscode/*.code-snippets +#.vscode/* +#!.vscode/settings.json +#!.vscode/tasks.json +#!.vscode/launch.json +#!.vscode/extensions.json +#!.vscode/*.code-snippets # Local History for Visual Studio Code .history/ @@ -357,4 +357,7 @@ hs_err_pid* .metals/* # Scala metals -.bloop/ \ No newline at end of file +.bloop/ + +# Temporary disable the generated verilog files +#generated/ \ No newline at end of file diff --git a/.vscode/settings.json b/.vscode/settings.json deleted file mode 100644 index 32cfc61..0000000 --- a/.vscode/settings.json +++ /dev/null @@ -1,5 +0,0 @@ -{ - "files.watcherExclude": { - "**/target": true - } -} \ No newline at end of file diff --git a/generated/Blinky.sv b/generated/Blinky.sv deleted file mode 100644 index 5f38007..0000000 --- a/generated/Blinky.sv +++ /dev/null @@ -1,26 +0,0 @@ -// Generated by CIRCT firtool-1.62.0 -module Blinky( - input clock, - reset, - output io_led0 -); - - reg led; - reg [8:0] counterWrap_c_value; - always @(posedge clock) begin - if (reset) begin - led <= 1'h0; - counterWrap_c_value <= 9'h0; - end - else begin - automatic logic counterWrap = counterWrap_c_value == 9'h1F3; - led <= counterWrap ^ led; - if (counterWrap) - counterWrap_c_value <= 9'h0; - else - counterWrap_c_value <= counterWrap_c_value + 9'h1; - end - end // always @(posedge) - assign io_led0 = led; -endmodule - diff --git a/generated/Buffer.sv b/generated/Buffer.sv deleted file mode 100644 index 893768a..0000000 --- a/generated/Buffer.sv +++ /dev/null @@ -1,33 +0,0 @@ -// Generated by CIRCT firtool-1.62.0 -module Buffer( - input clock, - reset, - output io_in_ready, - input io_in_valid, - input [7:0] io_in_bits, - input io_out_ready, - output io_out_valid, - output [7:0] io_out_bits -); - - reg stateReg; - reg [7:0] dataReg; - always @(posedge clock) begin - if (reset) begin - stateReg <= 1'h0; - dataReg <= 8'h0; - end - else begin - if (stateReg) - stateReg <= ~io_out_ready & stateReg; - else - stateReg <= io_in_valid | stateReg; - if (~stateReg & io_in_valid) - dataReg <= io_in_bits; - end - end // always @(posedge) - assign io_in_ready = ~stateReg; - assign io_out_valid = stateReg; - assign io_out_bits = dataReg; -endmodule - diff --git a/generated/BufferedTx.sv b/generated/BufferedTx.sv deleted file mode 100644 index b980704..0000000 --- a/generated/BufferedTx.sv +++ /dev/null @@ -1,33 +0,0 @@ -// Generated by CIRCT firtool-1.62.0 -module BufferedTx( - input clock, - reset, - output io_txd, - io_channel_ready, - input io_channel_valid, - input [7:0] io_channel_bits -); - - wire _buf_io_out_valid; - wire [7:0] _buf_io_out_bits; - wire _tx_io_channel_ready; - Tx tx ( - .clock (clock), - .reset (reset), - .io_txd (io_txd), - .io_channel_ready (_tx_io_channel_ready), - .io_channel_valid (_buf_io_out_valid), - .io_channel_bits (_buf_io_out_bits) - ); - Buffer buf_0 ( - .clock (clock), - .reset (reset), - .io_in_ready (io_channel_ready), - .io_in_valid (io_channel_valid), - .io_in_bits (io_channel_bits), - .io_out_ready (_tx_io_channel_ready), - .io_out_valid (_buf_io_out_valid), - .io_out_bits (_buf_io_out_bits) - ); -endmodule - diff --git a/generated/Sender.sv b/generated/Sender.sv deleted file mode 100644 index 736f9ea..0000000 --- a/generated/Sender.sv +++ /dev/null @@ -1,43 +0,0 @@ -// Generated by CIRCT firtool-1.62.0 -module Sender( - input clock, - reset, - output io_txd -); - - wire _tx_io_channel_ready; - wire [15:0][6:0] _GEN = - '{7'h48, - 7'h48, - 7'h48, - 7'h48, - 7'h21, - 7'h64, - 7'h6C, - 7'h72, - 7'h6F, - 7'h57, - 7'h20, - 7'h6F, - 7'h6C, - 7'h6C, - 7'h65, - 7'h48}; - reg [7:0] cntReg; - wire _tx_io_channel_valid_T = cntReg != 8'hC; - always @(posedge clock) begin - if (reset) - cntReg <= 8'h0; - else if (_tx_io_channel_ready & _tx_io_channel_valid_T) - cntReg <= cntReg + 8'h1; - end // always @(posedge) - BufferedTx tx ( - .clock (clock), - .reset (reset), - .io_txd (io_txd), - .io_channel_ready (_tx_io_channel_ready), - .io_channel_valid (_tx_io_channel_valid_T), - .io_channel_bits ({1'h0, _GEN[cntReg[3:0]]}) - ); -endmodule - diff --git a/generated/Tx.sv b/generated/Tx.sv deleted file mode 100644 index fe73d14..0000000 --- a/generated/Tx.sv +++ /dev/null @@ -1,39 +0,0 @@ -// Generated by CIRCT firtool-1.62.0 -module Tx( - input clock, - reset, - output io_txd, - io_channel_ready, - input io_channel_valid, - input [7:0] io_channel_bits -); - - reg [10:0] shiftReg; - reg [19:0] cntReg; - reg [3:0] bitsReg; - wire _io_channel_ready_T = cntReg == 20'h0; - always @(posedge clock) begin - if (reset) begin - shiftReg <= 11'h7FF; - cntReg <= 20'h0; - bitsReg <= 4'h0; - end - else if (_io_channel_ready_T) begin - if (|bitsReg) begin - shiftReg <= {1'h1, shiftReg[10:1]}; - bitsReg <= bitsReg - 4'h1; - end - else begin - shiftReg <= io_channel_valid ? {2'h3, io_channel_bits, 1'h0} : 11'h7FF; - if (io_channel_valid) - bitsReg <= 4'hB; - end - cntReg <= 20'h1B1; - end - else - cntReg <= cntReg - 20'h1; - end // always @(posedge) - assign io_txd = shiftReg[0]; - assign io_channel_ready = _io_channel_ready_T & ~(|bitsReg); -endmodule - diff --git a/generated/UartMain.sv b/generated/UartMain.sv deleted file mode 100644 index 412de5a..0000000 --- a/generated/UartMain.sv +++ /dev/null @@ -1,15 +0,0 @@ -// Generated by CIRCT firtool-1.62.0 -module UartMain( - input clock, - reset, - io_rxd, - output io_txd -); - - Sender s ( - .clock (clock), - .reset (reset), - .io_txd (io_txd) - ); -endmodule - diff --git a/generated/filelist.f b/generated/filelist.f deleted file mode 100644 index 896f8ad..0000000 --- a/generated/filelist.f +++ /dev/null @@ -1 +0,0 @@ -Blinky.sv