diff --git a/sim/hwdbg/DebuggerModuleTestingBRAM/Makefile b/sim/hwdbg/DebuggerModuleTestingBRAM/Makefile index 91415c1..013b26b 100644 --- a/sim/hwdbg/DebuggerModuleTestingBRAM/Makefile +++ b/sim/hwdbg/DebuggerModuleTestingBRAM/Makefile @@ -14,4 +14,4 @@ VERILOG_SOURCES += $(shell pwd)/../../../generated/InterpreterPortInformation.sv TOPLEVEL = DebuggerModuleTestingBRAM MODULE = test_DebuggerModuleTestingBRAM -include $(shell cocotb-config --makefiles)/Makefile.sim +include $(shell cocotb-config --makefiles)/Makefile.sim \ No newline at end of file diff --git a/sim/hwdbg/DebuggerModuleTestingBRAM/test.sh b/sim/hwdbg/DebuggerModuleTestingBRAM/test.sh index 9745da3..a83ca69 100755 --- a/sim/hwdbg/DebuggerModuleTestingBRAM/test.sh +++ b/sim/hwdbg/DebuggerModuleTestingBRAM/test.sh @@ -1 +1 @@ -make SIM=verilator WAVES=1 +make SIM=icarus WAVES=1 diff --git a/sim/hwdbg/DebuggerModuleTestingBRAM/test_DebuggerModuleTestingBRAM.py b/sim/hwdbg/DebuggerModuleTestingBRAM/test_DebuggerModuleTestingBRAM.py index 5a8ad9e..47f7c0b 100644 --- a/sim/hwdbg/DebuggerModuleTestingBRAM/test_DebuggerModuleTestingBRAM.py +++ b/sim/hwdbg/DebuggerModuleTestingBRAM/test_DebuggerModuleTestingBRAM.py @@ -18,7 +18,7 @@ import cocotb from cocotb.clock import Clock -from cocotb.triggers import RisingEdge +from cocotb.triggers import RisingEdge, Timer from cocotb.types import LogicArray maximum_number_of_clock_cycles = 1000 @@ -265,9 +265,9 @@ async def DebuggerModuleTestingBRAM_test(dut): # assert LogicArray(dut.io_outputPin_31.value) == LogicArray("Z") # - # Create a 10ns period clock on port clock + # Create a 1ns period clock on port clock # - clock = Clock(dut.clock, 10, units="ns") + clock = Clock(dut.clock, 1, units="ns") # # Start the clock. Start it low to avoid issues on the first RisingEdge @@ -287,7 +287,8 @@ async def DebuggerModuleTestingBRAM_test(dut): # dut.reset.value = 1 for _ in range(10): - await RisingEdge(dut.clock) + # await RisingEdge(dut.clock) + await Timer(1, units="ns") dut.reset.value = 0 dut._log.info("Enabling an interrupting chip to receive commands from BRAM") @@ -337,13 +338,13 @@ async def DebuggerModuleTestingBRAM_test(dut): # Tell the hwdbg to receive BRAM results # dut.io_plInSignal.value = 1 - await RisingEdge(dut.clock) + await Timer(1, units="ns") dut.io_plInSignal.value = 0 # # Synchronize with the clock. This will regisiter the initial `inputPinX` value # - await RisingEdge(dut.clock) + await Timer(1, units="ns") # # Wait until the debuggee sends an interrupt to debugger @@ -359,7 +360,7 @@ async def DebuggerModuleTestingBRAM_test(dut): print("Number of clock cycles spent in debuggee (PL): " + str(clock_counter)) clock_counter = clock_counter + 1 - await RisingEdge(dut.clock) + await Timer(1, units="ns") # # Apply a limitation to the number of clock cycles that @@ -381,7 +382,7 @@ async def DebuggerModuleTestingBRAM_test(dut): # # Run one more clock cycle to apply the latest BRAM modifications # - await RisingEdge(dut.clock) + await Timer(1, units="ns") # # Print contents of BRAM @@ -393,4 +394,4 @@ async def DebuggerModuleTestingBRAM_test(dut): # of more clock cycles # for _ in range(10): - await RisingEdge(dut.clock) + await Timer(1, units="ns") diff --git a/src/main/scala/hwdbg/communication/interpreter.scala b/src/main/scala/hwdbg/communication/interpreter.scala index 1973994..d6f7432 100644 --- a/src/main/scala/hwdbg/communication/interpreter.scala +++ b/src/main/scala/hwdbg/communication/interpreter.scala @@ -298,6 +298,7 @@ class DebuggerPacketInterpreter( // // Instantiate the port information module // + val ( noNewDataSenderModule, dataValidOutputModule, diff --git a/src/main/scala/hwdbg/communication/interpreter/port_information.scala b/src/main/scala/hwdbg/communication/interpreter/port_information.scala index 72103c7..5998745 100644 --- a/src/main/scala/hwdbg/communication/interpreter/port_information.scala +++ b/src/main/scala/hwdbg/communication/interpreter/port_information.scala @@ -64,20 +64,22 @@ class InterpreterPortInformation( val state = RegInit(sIdle) // - // Convert input port pins into vector + // Get number of input/output ports // - val inputPinsVec = VecInit(inputPortsConfiguration.values.toSeq.map(_.U)) + val numberOfInputPorts = inputPortsConfiguration.size + val numberOfOutputPorts = outputPortsConfiguration.size // - // Convert output port pins into vector + // Convert input port pins into vector // - val outputPinsVec = VecInit(outputPortsConfiguration.values.toSeq.map(_.U)) + // val inputPinsVec = VecInit(inputPortsConfiguration.values.toSeq.map(_.U)) + val inputPinsVec = RegInit(VecInit(Seq.fill(numberOfInputPorts)(0.U(bramDataWidth.W)))) // - // Get number of input/output ports + // Convert output port pins into vector // - val numberOfInputPorts = inputPortsConfiguration.size - val numberOfOutputPorts = outputPortsConfiguration.size + // val outputPinsVec = VecInit(outputPortsConfiguration.values.toSeq.map(_.U)) + val outputPinsVec = RegInit(VecInit(Seq.fill(numberOfOutputPorts)(0.U(bramDataWidth.W)))) // // Determine the width for numberOfSentPins based on conditions @@ -124,6 +126,16 @@ class InterpreterPortInformation( // dataValidOutput := true.B + // + // Fill the port info + // + LogInfo(debug)("Iterating over input pins:") + + inputPortsConfiguration.foreach { case (port, pins) => + LogInfo(debug)(s"Port $port has $pins pins") + inputPinsVec(port) := pins.U + } + // // Going to the next state (sending count of input ports) // @@ -144,6 +156,16 @@ class InterpreterPortInformation( // dataValidOutput := true.B + // + // Fill the port info + // + LogInfo(debug)("Iterating over output pins:") + + outputPortsConfiguration.foreach { case (port, pins) => + LogInfo(debug)(s"Port $port has $pins pins") + outputPinsVec(port) := pins.U + } + // // Next, we gonna send each ports' information () // @@ -155,11 +177,6 @@ class InterpreterPortInformation( // // Send input port items // - LogInfo(debug)("Iterating over input pins:") - - inputPortsConfiguration.foreach { case (port, pins) => - LogInfo(debug)(s"Port $port has $pins pins") - } // // Adjust data @@ -199,11 +216,6 @@ class InterpreterPortInformation( // // Send output port items // - LogInfo(debug)("Iterating over output pins:") - - outputPortsConfiguration.foreach { case (port, pins) => - LogInfo(debug)(s"Port $port has $pins pins") - } // // Adjust data