diff --git a/sim/hwdbg/communication/SendReceiveSynchronizer/test_SendReceiveSynchronizer.py b/sim/hwdbg/communication/SendReceiveSynchronizer/test_SendReceiveSynchronizer.py
index 91a099d..0273e46 100644
--- a/sim/hwdbg/communication/SendReceiveSynchronizer/test_SendReceiveSynchronizer.py
+++ b/sim/hwdbg/communication/SendReceiveSynchronizer/test_SendReceiveSynchronizer.py
@@ -119,6 +119,13 @@ async def SendReceiveSynchronizer_test(dut):
         await RisingEdge(dut.clock)
         dut.io_plInSignal.value = 0
 
+        #
+        # Activate sending logic to test whether the chip fails synchronizing signals or not
+        # 
+        dut.io_beginSendingBuffer.value = 1
+        await RisingEdge(dut.clock)
+        dut.io_beginSendingBuffer.value = 0
+
         #
         # Wait until the receive operation is done (finished)
         #
@@ -233,17 +240,23 @@ async def SendReceiveSynchronizer_test(dut):
                     else:
                         dut.io_readNextData.value = 0
 
-
             #
             # Go to the next clock cycle
             #
             await RisingEdge(dut.clock)
 
+
         if test_number % 3 != 0:
             dut.io_noNewDataReceiver.value = 1
             await RisingEdge(dut.clock)
             dut.io_noNewDataReceiver.value = 0
 
+        #
+        # Run extra waiting clocks
+        #
+        for _ in range(10):
+            await RisingEdge(dut.clock)
+
         ###############################################################
         #                                                             #
         #                       Sending Logic                         #
@@ -253,9 +266,10 @@ async def SendReceiveSynchronizer_test(dut):
         dut._log.info("Enable sending data on the chip (" + str(test_number) + ")")
 
         #
-        # Still there is data to send
+        # There is data to send
         #
         dut.io_noNewDataSender.value = 0
+        dut.io_beginSendingBuffer.value = 0
 
         #
         # Tell the sender to start sending data (This mainly operates based on
@@ -265,6 +279,13 @@ async def SendReceiveSynchronizer_test(dut):
         await RisingEdge(dut.clock)
         dut.io_beginSendingBuffer.value = 0
 
+        #
+        # Activate receiving logic to test whether the chip fails synchronizing signals or not
+        # 
+        dut.io_plInSignal.value = 1
+        await RisingEdge(dut.clock)
+        dut.io_plInSignal.value = 0
+
         #
         # No new data at this stage
         #
diff --git a/src/main/scala/hwdbg/communication/send_receive_synchronizer.scala b/src/main/scala/hwdbg/communication/send_receive_synchronizer.scala
index f7b5c70..8e0f015 100644
--- a/src/main/scala/hwdbg/communication/send_receive_synchronizer.scala
+++ b/src/main/scala/hwdbg/communication/send_receive_synchronizer.scala
@@ -188,7 +188,7 @@ class SendReceiveSynchronizer(
           //
           // Go to the sender state
           //
-          state := sReceiver
+          state := sSender
 
         }.otherwise {