diff --git a/include/drivers/irq/riscv_plic0.h b/include/drivers/irq/riscv_plic0.h
index 4eec75c583..9f7c59a969 100644
--- a/include/drivers/irq/riscv_plic0.h
+++ b/include/drivers/irq/riscv_plic0.h
@@ -4,15 +4,18 @@
  *
  * SPDX-License-Identifier: GPL-2.0-only
  *
- * SiFive U54/U74 PLIC handling (HiFive Unleashed/Unmatched, Polarfire)
+ * SiFive U54/U74 PLIC handling (HiFive Unleashed/Unmatched, Polarfire,
+ * QEMU RISC-V virt)
  */
 
 #pragma once
 
 /* This is a check that prevents using this driver blindly. Extend the list if
  * this driver is confirmed to be working on other platforms. */
-#if !defined(CONFIG_PLAT_HIFIVE) && !defined(CONFIG_PLAT_POLARFIRE)
-#error "This code supports the SiFive U54/U74 PLIC only."
+#if !defined(CONFIG_PLAT_HIFIVE) && \
+    !defined(CONFIG_PLAT_POLARFIRE) && \
+    !defined(CONFIG_PLAT_QEMU_RISCV_VIRT)
+#error "Check if this platform suppots a PLIC."
 #endif
 
 /* tell the kernel we have the set trigger feature */
diff --git a/libsel4/sel4_plat_include/qemu-riscv-virt/sel4/plat/api/constants.h b/libsel4/sel4_plat_include/qemu-riscv-virt/sel4/plat/api/constants.h
new file mode 100644
index 0000000000..dcd96cda63
--- /dev/null
+++ b/libsel4/sel4_plat_include/qemu-riscv-virt/sel4/plat/api/constants.h
@@ -0,0 +1,11 @@
+/*
+ * Copyright 2022, HENSOLDT Cyber
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+
+#pragma once
+
+#include <autoconf.h>
+
+/* nothing here */
diff --git a/src/plat/qemu-riscv-virt/config.cmake b/src/plat/qemu-riscv-virt/config.cmake
new file mode 100644
index 0000000000..7f52cec289
--- /dev/null
+++ b/src/plat/qemu-riscv-virt/config.cmake
@@ -0,0 +1,109 @@
+#
+# Copyright 2022, HENSOLDT Cyber
+# Copyright 2020, Data61, CSIRO (ABN 41 687 119 230)
+#
+# SPDX-License-Identifier: GPL-2.0-only
+#
+
+cmake_minimum_required(VERSION 3.7.2)
+
+declare_platform(qemu-riscv-virt KernelPlatformQEMURiscVVirt PLAT_QEMU_RISCV_VIRT KernelArchRiscV)
+
+if(KernelPlatformQEMURiscVVirt)
+
+    # ToDo: use setup_seL4_arch("riscv64;riscv32")
+    if("${KernelSel4Arch}" STREQUAL riscv64)
+        declare_seL4_arch(riscv64)
+    elseif("${KernelSel4Arch}" STREQUAL riscv32)
+        # This is still untested
+        declare_seL4_arch(riscv32)
+    else()
+        fallback_declare_seL4_arch_default(riscv64)
+    endif()
+
+    config_set(KernelOpenSBIPlatform OPENSBI_PLATFORM "generic")
+    config_set(KernelPlatformFirstHartID FIRST_HART_ID 0)
+
+    # Unless QEMU_DTS is set explicitly, the device tree is extract from QEMU.
+    # This keeps it nicely up to date with the newer QEMU versions and is quite
+    # convenient for the development usecase.
+    if(NOT DEFINED QEMU_DTS)
+
+        message(STATUS "Extracting device tree from QEMU")
+
+        set(QEMU_BINARY "qemu-system-${KernelSel4Arch}")
+        find_program(QEMU_BINARY ${QEMU_BINARY})
+
+        # RISC-V virtual platform works since QEMU 5.1.0
+        set(MIN_QEMU_VERSION "5.1.0")
+        execute_process(
+            COMMAND ${QEMU_BINARY} -version
+            RESULT_VARIABLE error
+            OUTPUT_VARIABLE QEMU_STDOUT_MESSAGE
+        )
+        if(error)
+            message(FATAL_ERROR "Failed to determine QEMU version (${QEMU_BINARY})")
+        endif()
+        string(
+            REGEX
+                MATCH
+                "[0-9](\\.[0-9])+"
+                QEMU_VERSION
+                "${QEMU_STDOUT_MESSAGE}"
+        )
+        if("${QEMU_VERSION}" VERSION_LESS "${MIN_QEMU_VERSION}")
+            message(
+                FATAL_ERROR
+                    "Error: need at least QEMU version ${MIN_QEMU_VERSION}, found '${QEMU_VERSION}'"
+            )
+        endif()
+
+        if(NOT DEFINED QEMU_MEMORY)
+            # Having 2 GiB of memory as default seems a good trade-off. It's
+            # sufficient for test/demo systems, but still something the host can
+            # provide without running short on resources.
+            set(QEMU_MEMORY "2048")
+        endif()
+
+        if(KernelMaxNumNodes)
+            set(QEMU_SMP_OPTION "${KernelMaxNumNodes}")
+        else()
+            set(QEMU_SMP_OPTION "1")
+        endif()
+
+        set(QEMU_DT_BASE_NAME "${CMAKE_BINARY_DIR}/qemu-riscv-virt")
+        set(QEMU_DTB "${QEMU_DT_BASE_NAME}.dtb")
+        set(QEMU_DTS "${QEMU_DT_BASE_NAME}.dts")
+
+        execute_process(
+            COMMAND
+                ${QEMU_BINARY} -machine virt,dumpdtb=${QEMU_DTB} -cpu rv${KernelWordSize} -smp
+                ${QEMU_SMP_OPTION} -m ${QEMU_MEMORY} -nographic
+            RESULT_VARIABLE error
+        )
+        if(error)
+            message(FATAL_ERROR "Failed to dump DTB using ${QEMU_BINARY})")
+        endif()
+
+        execute_process(
+            COMMAND
+                dtc -q -I dtb -O dts -o ${QEMU_DTS} ${QEMU_DTB}
+            RESULT_VARIABLE error
+        )
+        if(error)
+            message(FATAL_ERROR "Failed to convert QEMU's DTB to a DTS (${QEMU_DTB})")
+        endif()
+
+    endif()
+
+    list(APPEND KernelDTSList "${QEMU_DTS}" "${CMAKE_CURRENT_LIST_DIR}/overlay-qemu-riscv-virt.dts")
+
+    # QEMU pretends to have a CLINT/ACLINT timer with 10 MHz, but this may not
+    # hold in practical mesurements. A SiFive PLIC/CLINT with 127 interrupt
+    # sources is emulated by default.
+    declare_default_headers(
+        TIMER_FREQUENCY 10000000 PLIC_MAX_NUM_INT 128
+        INTERRUPT_CONTROLLER drivers/irq/riscv_plic0.h
+    )
+
+endif()
diff --git a/src/plat/qemu-riscv-virt/overlay-qemu-riscv-virt.dts b/src/plat/qemu-riscv-virt/overlay-qemu-riscv-virt.dts
new file mode 100644
index 0000000000..36f930b6f5
--- /dev/null
+++ b/src/plat/qemu-riscv-virt/overlay-qemu-riscv-virt.dts
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2022, HENSOLDT Cyber
+ *
+ * SPDX-License-Identifier: GPL-2.0-only
+ */
+
+/ {
+    chosen {
+        /*
+         * - elfloader and kernel use SBI console by default
+         * - QEMU emulates a SiFive PLIC and CLINT by default
+         *
+         * Nothing needed for elfloader
+         *      seL4,elfloader-devices = ... ;
+         *
+         */
+        seL4,kernel-devices =
+            &{/soc/plic@c000000};
+    };
+};