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tnt_strings.h
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tnt_strings.h
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#ifndef __TNT_STRINGS_H
#define __TNT_STRINGS_H
/* ------------------ Types ------------------ */
// VEX/pub/libvex_ir.h
const char *IRType_string[] = {
"INVALID",
"I1",
"I8",
"I16",
"I32",
"I64",
"I128", /* 128-bit scalar */
"F32", /* IEEE 754 float */
"F64", /* IEEE 754 double */
"D32", /* 32-bit Decimal floating point */
"D64", /* 64-bit Decimal floating point */
"D128", /* 128-bit Decimal floating point */
"F128", /* 128-bit floating point; implementation defined */
"V128", /* 128-bit SIMD */
"V256" /* 256-bit SIMD */
};
#define IRType_MAX ( sizeof(IRType_string)/sizeof(IRType_string[0]) )
/* ------------------ Endianness ------------------ */
const char *IREndness_string[] = {
"LE",
"BE" };
/* ------------------ Constants ------------------ */
const char *IRConst_string[] = {
"Ico_U1",
"Ico_U8",
"Ico_U16",
"Ico_U32",
"Ico_U64",
"Ico_F64",
"Ico_F64i",
"Ico_V128" };
/* --------------- Primops (arity 1",2",3 and 4) --------------- */
// First op: 0x1400, Last op: Iop_LAST
const char *IROp_string[] = {
"INVALID",
"Add8", "Add16", "Add32", "Add64",
"Sub8", "Sub16", "Sub32", "Sub64",
/* Signless mul. MullS/MullU is elsewhere. */
"Mul8", "Mul16", "Mul32", "Mul64",
"Or8", "Or16", "Or32", "Or64",
"And8", "And16", "And32", "And64",
"Xor8", "Xor16", "Xor32", "Xor64",
"Shl8", "Shl16", "Shl32", "Shl64",
"Shr8", "Shr16", "Shr32", "Shr64",
"Sar8", "Sar16", "Sar32", "Sar64",
/* Integer comparisons. */
"CmpEQ8", "CmpEQ16", "CmpEQ32", "CmpEQ64",
"CmpNE8", "CmpNE16", "CmpNE32", "CmpNE64",
/* Tags for unary ops */
"Not8", "Not16", "Not32", "Not64",
/* Exactly like CmpEQ8/16/32/64", but carrying the additional
hint that these compute the success/failure of a CAS
operation, and hence are almost certainly applied to two
copies of the same value, which in turn has implications for
Memcheck's instrumentation. */
"CasCmpEQ8", "CasCmpEQ16", "CasCmpEQ32", "CasCmpEQ64",
"CasCmpNE8", "CasCmpNE16", "CasCmpNE32", "CasCmpNE64",
/* Exactly like CmpNE8/16/32/64", but carrying the additional
hint that these needs expensive definedness tracking. */
"ExpCmpNE8", "ExpCmpNE16", "ExpCmpNE32", "ExpCmpNE64",
/* -- Ordering not important after here. -- */
/* Widening multiplies */
"MullS8", "MullS16", "MullS32", "MullS64",
"MullU8", "MullU16", "MullU32", "MullU64",
/* Wierdo integer stuff */
"Clz64", "Clz32", /* count leading zeroes */
"Ctz64", "Ctz32", /* count trailing zeros */
/* Ctz64/Ctz32/Clz64/Clz32 are UNDEFINED when given arguments of
zero. You must ensure they are never given a zero argument.
*/
/* Standard integer comparisons */
"CmpLT32S", "CmpLT64S",
"CmpLE32S", "CmpLE64S",
"CmpLT32U", "CmpLT64U",
"CmpLE32U", "CmpLE64U",
/* As a sop to Valgrind-Memcheck, the following are useful. */
"CmpNEZ8", "CmpNEZ16", "CmpNEZ32", "CmpNEZ64",
"CmpwNEZ32", "CmpwNEZ64", /* all-0s -> all-Os; other -> all-1s */
"Left8", "Left16", "Left32", "Left64", /* \x -> x | -x */
"Max32U", /* unsigned max */
/* PowerPC-style 3-way integer comparisons. Without them it is
difficult to simulate PPC efficiently.
op(x,y) | x < y = 0x8 else
| x > y = 0x4 else
| x == y = 0x2
*/
"CmpORD32U", "CmpORD64U",
"CmpORD32S", "CmpORD64S",
/* Division */
/* TODO: clarify semantics wrt rounding, negative values, whatever */
"DivU32", // :: I32",I32 -> I32 (simple div", no mod)
"DivS32", // ditto, signed
"DivU64", // :: I64",I64 -> I64 (simple div, no mod)
"DivS64", // ditto, signed
"DivU64E", // :: I64",I64 -> I64 (dividend is 64-bit arg (hi) concat with 64 0's (low))
"DivS64E", // ditto, signed
"DivU32E", // :: I32",I32 -> I32 (dividend is 32-bit arg (hi) concat with 32 0's (low))
"DivS32E", // ditto, signed
"DivModU64to32", // :: I64",I32 -> I64
// of which lo half is div and hi half is mod
"DivModS64to32", // ditto, signed
"DivModU128to64", // :: V128",I64 -> V128
// of which lo half is div and hi half is mod
"DivModS128to64", // ditto, signed
"DivModS64to64", // :: I64",I64 -> I128
// of which lo half is div and hi half is mod
/* Integer conversions. Some of these are redundant (eg
"64to8 is the same as "64to32 and then "32to8), but
having a complete set reduces the typical dynamic size of IR
and makes the instruction selectors easier to write. */
/* Widening conversions */
"8Uto16", "8Uto32", "8Uto64",
"16Uto32", "16Uto64",
"32Uto64",
"8Sto16", "8Sto32", "8Sto64",
"16Sto32", "16Sto64",
"32Sto64",
/* Narrowing conversions */
"64to8", "32to8", "64to16",
/* 8 <-> 16 bit conversions */
"16to8", // :: I16 -> I8", low half
"16HIto8", // :: I16 -> I8", high half
"8HLto16", // :: (I8",I8) -> I16
/* 16 <-> 32 bit conversions */
"32to16", // :: I32 -> I16", low half
"32HIto16", // :: I32 -> I16", high half
"16HLto32", // :: (I16",I16) -> I32
/* 32 <-> 64 bit conversions */
"64to32", // :: I64 -> I32", low half
"64HIto32", // :: I64 -> I32", high half
"32HLto64", // :: (I32",I32) -> I64
/* 64 <-> 128 bit conversions */
"128to64", // :: I128 -> I64", low half
"128HIto64", // :: I128 -> I64", high half
"64HLto128", // :: (I64",I64) -> I128
/* 1-bit stuff */
"Not1", /* :: Ity_Bit -> Ity_Bit */
"32to1", /* :: Ity_I32 -> Ity_Bit, just select bit[0] */
"64to1", /* :: Ity_I64 -> Ity_Bit, just select bit[0] */
"1Uto8", /* :: Ity_Bit -> Ity_I8", unsigned widen */
"1Uto32", /* :: Ity_Bit -> Ity_I32", unsigned widen */
"1Uto64", /* :: Ity_Bit -> Ity_I64", unsigned widen */
"1Sto8", /* :: Ity_Bit -> Ity_I8", signed widen */
"1Sto16", /* :: Ity_Bit -> Ity_I16", signed widen */
"1Sto32", /* :: Ity_Bit -> Ity_I32", signed widen */
"1Sto64", /* :: Ity_Bit -> Ity_I64", signed widen */
/* ------ Floating point. We try to be IEEE754 compliant. ------ */
/* --- Simple stuff as mandated by 754. --- */
/* Binary operations, with rounding. */
/* :: IRRoundingMode(I32) x F64 x F64 -> F64 */
"AddF64", "SubF64", "MulF64", "DivF64",
/* :: IRRoundingMode(I32) x F32 x F32 -> F32 */
"AddF32", "SubF32", "MulF32", "DivF32",
/* Variants of the above which produce a 64-bit result but which
round their result to a IEEE float range first. */
/* :: IRRoundingMode(I32) x F64 x F64 -> F64 */
"AddF64r32", "SubF64r32", "MulF64r32", "DivF64r32",
/* Unary operations, without rounding. */
/* :: F64 -> F64 */
"NegF64", "AbsF64",
/* :: F32 -> F32 */
"NegF32", "AbsF32",
/* Unary operations, with rounding. */
/* :: IRRoundingMode(I32) x F64 -> F64 */
"SqrtF64",
/* :: IRRoundingMode(I32) x F32 -> F32 */
"SqrtF32",
/* Comparison, yielding GT/LT/EQ/UN(ordered), as per the following:
0x45 Unordered
0x01 LT
0x00 GT
0x40 EQ
This just happens to be the Intel encoding. The values
are recorded in the type IRCmpF64Result.
*/
/* :: F64 x F64 -> IRCmpF64Result(I32) */
"CmpF64",
"CmpF32",
"CmpF128",
/* --- Int to/from FP conversions. --- */
/* For the most part, these take a first argument :: Ity_I32 (as
IRRoundingMode) which is an indication of the rounding mode
to use, as per the following encoding ("the standard
encoding"):
00b to nearest (the default)
01b to -infinity
10b to +infinity
11b to zero
This just happens to be the Intel encoding. For reference only,
the PPC encoding is:
00b to nearest (the default)
01b to zero
10b to +infinity
11b to -infinity
Any PPC -> IR front end will have to translate these PPC
encodings, as encoded in the guest state, to the standard
encodings, to pass to the primops.
For reference only, the ARM VFP encoding is:
00b to nearest
01b to +infinity
10b to -infinity
11b to zero
Again, this will have to be converted to the standard encoding
to pass to primops.
If one of these conversions gets an out-of-range condition,
or a NaN", as an argument, the result is host-defined. On x86
the "integer indefinite" value 0x80..00 is produced. On PPC
it is either 0x80..00 or 0x7F..FF depending on the sign of
the argument.
On ARMvfp, when converting to a signed integer result, the
overflow result is 0x80..00 for negative args and 0x7F..FF
for positive args. For unsigned integer results it is
0x00..00 and 0xFF..FF respectively.
Rounding is required whenever the destination type cannot
represent exactly all values of the source type.
*/
"F64toI16S", /* IRRoundingMode(I32) x F64 -> signed I16 */
"F64toI32S", /* IRRoundingMode(I32) x F64 -> signed I32 */
"F64toI64S", /* IRRoundingMode(I32) x F64 -> signed I64 */
"F64toI64U", /* IRRoundingMode(I32) x F64 -> unsigned I64 */
"F64toI32U", /* IRRoundingMode(I32) x F64 -> unsigned I32 */
"I32StoF64", /* signed I32 -> F64 */
"I64StoF64", /* IRRoundingMode(I32) x signed I64 -> F64 */
"I64UtoF64", /* IRRoundingMode(I32) x unsigned I64 -> F64 */
"I64UtoF32", /* IRRoundingMode(I32) x unsigned I64 -> F32 */
"I32UtoF32", /* IRRoundingMode(I32) x unsigned I32 -> F32 */
"I32UtoF64", /* unsigned I32 -> F64 */
"F32toI32S", /* IRRoundingMode(I32) x F32 -> signed I32 */
"F32toI64S", /* IRRoundingMode(I32) x F32 -> signed I64 */
"F32toI32U", /* IRRoundingMode(I32) x F32 -> unsigned I32 */
"F32toI64U", /* IRRoundingMode(I32) x F32 -> unsigned I64 */
"I32StoF32", /* IRRoundingMode(I32) x signed I32 -> F32 */
"I64StoF32", /* IRRoundingMode(I32) x signed I64 -> F32 */
/* Conversion between floating point formats */
"F32toF64", /* F32 -> F64 */
"F64toF32", /* IRRoundingMode(I32) x F64 -> F32 */
/* Reinterpretation. Take an F64 and produce an I64 with
the same bit pattern, or vice versa. */
"ReinterpF64asI64", "ReinterpI64asF64",
"ReinterpF32asI32", "ReinterpI32asF32",
/* Support for 128-bit floating point */
"F64HLtoF128",/* (high half of F128",low half of F128) -> F128 */
"F128HItoF64",/* F128 -> high half of F128 into a F64 register */
"F128LOtoF64",/* F128 -> low half of F128 into a F64 register */
/* :: IRRoundingMode(I32) x F128 x F128 -> F128 */
"AddF128", "SubF128", "MulF128", "DivF128",
/* :: F128 -> F128 */
"NegF128", "AbsF128",
/* :: IRRoundingMode(I32) x F128 -> F128 */
"SqrtF128",
"I32StoF128", /* signed I32 -> F128 */
"I64StoF128", /* signed I64 -> F128 */
"I32UtoF128", /* unsigned I32 -> F128 */
"I64UtoF128", /* unsigned I64 -> F128 */
"F32toF128", /* F32 -> F128 */
"F64toF128", /* F64 -> F128 */
"F128toI32S", /* IRRoundingMode(I32) x F128 -> signed I32 */
"F128toI64S", /* IRRoundingMode(I32) x F128 -> signed I64 */
"F128toI32U", /* IRRoundingMode(I32) x F128 -> unsigned I32 */
"F128toI64U", /* IRRoundingMode(I32) x F128 -> unsigned I64 */
"F128toF64", /* IRRoundingMode(I32) x F128 -> F64 */
"F128toF32", /* IRRoundingMode(I32) x F128 -> F32 */
/* --- guest x86/amd64 specifics, not mandated by 754. --- */
/* Binary ops, with rounding. */
/* :: IRRoundingMode(I32) x F64 x F64 -> F64 */
"AtanF64", /* FPATAN", arctan(arg1/arg2) */
"Yl2xF64", /* FYL2X, arg1 * log2(arg2) */
"Yl2xp1F64", /* FYL2XP1", arg1 * log2(arg2+1.0) */
"PRemF64", /* FPREM, non-IEEE remainder(arg1/arg2) */
"PRemC3210F64", /* C3210 flags resulting from FPREM, :: I32 */
"PRem1F64", /* FPREM1", IEEE remainder(arg1/arg2) */
"PRem1C3210F64", /* C3210 flags resulting from FPREM1", :: I32 */
"ScaleF64", /* FSCALE", arg1 * (2^RoundTowardsZero(arg2)) */
/* Note that on x86 guest, PRem1{C3210} has the same behaviour
as the IEEE mandated RemF64", except it is limited in the
range of its operand. Hence the partialness. */
/* Unary ops, with rounding. */
/* :: IRRoundingMode(I32) x F64 -> F64 */
"SinF64", /* FSIN */
"CosF64", /* FCOS */
"TanF64", /* FTAN */
"2xm1F64", /* (2^arg - 1.0) */
"RoundF64toInt", /* F64 value to nearest integral value (still
as F64) */
"RoundF32toInt", /* F32 value to nearest integral value (still
as F32) */
/* --- guest s390 specifics, not mandated by 754. --- */
/* Fused multiply-add/sub */
/* :: IRRoundingMode(I32) x F32 x F32 x F32 -> F32
(computes arg2 * arg3 +/- arg4) */
"MAddF32", "MSubF32",
/* --- guest ppc32/64 specifics, not mandated by 754. --- */
/* Ternary operations, with rounding. */
/* Fused multiply-add/sub, with 112-bit intermediate
precision for ppc.
Also used to implement fused multiply-add/sub for s390. */
/* :: IRRoundingMode(I32) x F64 x F64 x F64 -> F64
(computes arg2 * arg3 +/- arg4) */
"MAddF64", "MSubF64",
/* Variants of the above which produce a 64-bit result but which
round their result to a IEEE float range first. */
/* :: IRRoundingMode(I32) x F64 x F64 x F64 -> F64 */
"MAddF64r32", "MSubF64r32",
/* :: F64 -> F64 */
"Est5FRSqrt", /* reciprocal square root estimate, 5 good bits */
"RoundF64toF64_NEAREST", /* frin */
"RoundF64toF64_NegINF", /* frim */
"RoundF64toF64_PosINF", /* frip */
"RoundF64toF64_ZERO", /* friz */
/* :: F64 -> F32 */
"TruncF64asF32", /* do F64->F32 truncation as per 'fsts' */
/* :: IRRoundingMode(I32) x F64 -> F64 */
"RoundF64toF32", /* round F64 to nearest F32 value (still as F64) */
/* NB: pretty much the same as "F64toF32", except no change
of type. */
/* ------------------ 32-bit SIMD Integer ------------------ */
/* 32x1 saturating add/sub (ok, well, not really SIMD :) */
"QAdd32S",
"QSub32S",
/* 16x2 add/sub, also signed/unsigned saturating variants */
"Add16x2", "Sub16x2",
"QAdd16Sx2", "QAdd16Ux2",
"QSub16Sx2", "QSub16Ux2",
/* 16x2 signed/unsigned halving add/sub. For each lane, these
compute bits 16:1 of (eg) sx(argL) + sx(argR),
or zx(argL) - zx(argR) etc. */
"HAdd16Ux2", "HAdd16Sx2",
"HSub16Ux2", "HSub16Sx2",
/* 8x4 add/sub, also signed/unsigned saturating variants */
"Add8x4", "Sub8x4",
"QAdd8Sx4", "QAdd8Ux4",
"QSub8Sx4", "QSub8Ux4",
/* 8x4 signed/unsigned halving add/sub. For each lane, these
compute bits 8:1 of (eg) sx(argL) + sx(argR),
or zx(argL) - zx(argR) etc. */
"HAdd8Ux4", "HAdd8Sx4",
"HSub8Ux4", "HSub8Sx4",
/* 8x4 sum of absolute unsigned differences. */
"Sad8Ux4",
/* MISC (vector integer cmp != 0) */
"CmpNEZ16x2", "CmpNEZ8x4",
/* ------------------ 64-bit SIMD FP ------------------------ */
/* Convertion to/from int */
"I32UtoFx2", "I32StoFx2", /* I32x4 -> F32x4 */
"FtoI32Ux2_RZ", "FtoI32Sx2_RZ", /* F32x4 -> I32x4 */
/* Fixed32 format is floating-point number with fixed number of fraction
bits. The number of fraction bits is passed as a second argument of
type I8. */
"F32ToFixed32Ux2_RZ", "F32ToFixed32Sx2_RZ", /* fp -> fixed-point */
"Fixed32UToF32x2_RN", "Fixed32SToF32x2_RN", /* fixed-point -> fp */
/* Binary operations */
"Max32Fx2", "Min32Fx2",
/* Pairwise Min and Max. See integer pairwise operations for more
details. */
"PwMax32Fx2", "PwMin32Fx2",
/* Note: For the following compares, the arm front-end assumes a
nan in a lane of either argument returns zero for that lane. */
"CmpEQ32Fx2", "CmpGT32Fx2", "CmpGE32Fx2",
/* Vector Reciprocal Estimate finds an approximate reciprocal of each
element in the operand vector, and places the results in the destination
vector. */
"Recip32Fx2",
/* Vector Reciprocal Step computes (2.0 - arg1 * arg2).
Note, that if one of the arguments is zero and another one is infinity
of arbitrary sign the result of the operation is 2.0. */
"Recps32Fx2",
/* Vector Reciprocal Square Root Estimate finds an approximate reciprocal
square root of each element in the operand vector. */
"Rsqrte32Fx2",
/* Vector Reciprocal Square Root Step computes (3.0 - arg1 * arg2) / 2.0.
Note, that of one of the arguments is zero and another one is infiinty
of arbitrary sign the result of the operation is 1.5. */
"Rsqrts32Fx2",
/* Unary */
"Neg32Fx2", "Abs32Fx2",
/* ------------------ 64-bit SIMD Integer. ------------------ */
/* MISC (vector integer cmp != 0) */
"CmpNEZ8x8", "CmpNEZ16x4", "CmpNEZ32x2",
/* ADDITION (normal / unsigned sat / signed sat) */
"Add8x8", "Add16x4", "Add32x2",
"QAdd8Ux8", "QAdd16Ux4", "QAdd32Ux2", "QAdd64Ux1",
"QAdd8Sx8", "QAdd16Sx4", "QAdd32Sx2", "QAdd64Sx1",
/* PAIRWISE operations */
/* "PwFoo16x4( [a,b,c,d], [e,f,g,h] ) =
[Foo16(a,b), Foo16(c,d), Foo16(e,f), Foo16(g,h)] */
"PwAdd8x8", "PwAdd16x4", "PwAdd32x2",
"PwMax8Sx8", "PwMax16Sx4", "PwMax32Sx2",
"PwMax8Ux8", "PwMax16Ux4", "PwMax32Ux2",
"PwMin8Sx8", "PwMin16Sx4", "PwMin32Sx2",
"PwMin8Ux8", "PwMin16Ux4", "PwMin32Ux2",
/* Longening variant is unary. The resulting vector contains two times
less elements than operand, but they are two times wider.
Example:
"PAddL16Ux4( [a,b,c,d] ) = [a+b,c+d]
where a+b and c+d are unsigned 32-bit values. */
"PwAddL8Ux8", "PwAddL16Ux4", "PwAddL32Ux2",
"PwAddL8Sx8", "PwAddL16Sx4", "PwAddL32Sx2",
/* SUBTRACTION (normal / unsigned sat / signed sat) */
"Sub8x8", "Sub16x4", "Sub32x2",
"QSub8Ux8", "QSub16Ux4", "QSub32Ux2", "QSub64Ux1",
"QSub8Sx8", "QSub16Sx4", "QSub32Sx2", "QSub64Sx1",
/* ABSOLUTE VALUE */
"Abs8x8", "Abs16x4", "Abs32x2",
/* MULTIPLICATION (normal / high half of signed/unsigned / plynomial ) */
"Mul8x8", "Mul16x4", "Mul32x2",
"Mul32Fx2",
"MulHi16Ux4",
"MulHi16Sx4",
/* Plynomial multiplication treats it's arguments as coefficients of
polynoms over {0, 1}. */
"PolynomialMul8x8",
/* Vector Saturating Doubling Multiply Returning High Half and
Vector Saturating Rounding Doubling Multiply Returning High Half */
/* These IROp's multiply corresponding elements in two vectors, double
the results, and place the most significant half of the final results
in the destination vector. The results are truncated or rounded. If
any of the results overflow, they are saturated. */
"QDMulHi16Sx4", "QDMulHi32Sx2",
"QRDMulHi16Sx4", "QRDMulHi32Sx2",
/* AVERAGING: note: (arg1 + arg2 + 1) >>u 1 */
"Avg8Ux8",
"Avg16Ux4",
/* MIN/MAX */
"Max8Sx8", "Max16Sx4", "Max32Sx2",
"Max8Ux8", "Max16Ux4", "Max32Ux2",
"Min8Sx8", "Min16Sx4", "Min32Sx2",
"Min8Ux8", "Min16Ux4", "Min32Ux2",
/* COMPARISON */
"CmpEQ8x8", "CmpEQ16x4", "CmpEQ32x2",
"CmpGT8Ux8", "CmpGT16Ux4", "CmpGT32Ux2",
"CmpGT8Sx8", "CmpGT16Sx4", "CmpGT32Sx2",
/* COUNT ones / leading zeroes / leading sign bits (not including topmost
bit) */
"Cnt8x8",
"Clz8Sx8", "Clz16Sx4", "Clz32Sx2",
"Cls8Sx8", "Cls16Sx4", "Cls32Sx2",
"Clz64x2",
/* VECTOR x VECTOR SHIFT / ROTATE */
"Shl8x8", "Shl16x4", "Shl32x2",
"Shr8x8", "Shr16x4", "Shr32x2",
"Sar8x8", "Sar16x4", "Sar32x2",
"Sal8x8", "Sal16x4", "Sal32x2", "Sal64x1",
/* VECTOR x SCALAR SHIFT (shift amt :: Ity_I8) */
"ShlN8x8", "ShlN16x4", "ShlN32x2",
"ShrN8x8", "ShrN16x4", "ShrN32x2",
"SarN8x8", "SarN16x4", "SarN32x2",
/* VECTOR x VECTOR SATURATING SHIFT */
"QShl8x8", "QShl16x4", "QShl32x2", "QShl64x1",
"QSal8x8", "QSal16x4", "QSal32x2", "QSal64x1",
/* VECTOR x INTEGER SATURATING SHIFT */
"QShlN8Sx8", "QShlN16Sx4", "QShlN32Sx2", "QShlN64Sx1",
"QShlN8x8", "QShlN16x4", "QShlN32x2", "QShlN64x1",
"QSalN8x8", "QSalN16x4", "QSalN32x2", "QSalN64x1",
/* NARROWING (binary)
-- narrow 2xI64 into 1xI64", hi half from left arg */
/* For saturated narrowing, I believe there are 4 variants of
the basic arithmetic operation, depending on the signedness
of argument and result. Here are examples that exemplify
what I mean:
QNarrow16Uto8U ( UShort x ) if (x >u 255) x = 255;
return x[7:0];
QNarrow16Sto8S ( Short x ) if (x <s -128) x = -128;
if (x >s 127) x = 127;
return x[7:0];
QNarrow16Uto8S ( UShort x ) if (x >u 127) x = 127;
return x[7:0];
QNarrow16Sto8U ( Short x ) if (x <s 0) x = 0;
if (x >s 255) x = 255;
return x[7:0];
*/
"QNarrowBin16Sto8Ux8",
"QNarrowBin16Sto8Sx8", "QNarrowBin32Sto16Sx4",
"NarrowBin16to8x8", "NarrowBin32to16x4",
/* INTERLEAVING */
/* Interleave lanes from low or high halves of
operands. Most-significant result lane is from the left
arg. */
"InterleaveHI8x8", "InterleaveHI16x4", "InterleaveHI32x2",
"InterleaveLO8x8", "InterleaveLO16x4", "InterleaveLO32x2",
/* Interleave odd/even lanes of operands. Most-significant result lane
is from the left arg. Note that Interleave{Odd,Even}Lanes32x2 are
identical to Interleave{HI,LO}32x2 and so are omitted.*/
"InterleaveOddLanes8x8", "InterleaveEvenLanes8x8",
"InterleaveOddLanes16x4", "InterleaveEvenLanes16x4",
/* CONCATENATION -- build a new value by concatenating either
the even or odd lanes of both operands. Note that
Cat{Odd,Even}Lanes32x2 are identical to Interleave{HI,LO}32x2
and so are omitted. */
"CatOddLanes8x8", "CatOddLanes16x4",
"CatEvenLanes8x8", "CatEvenLanes16x4",
/* GET / SET elements of VECTOR
GET is binop (I64", I8) -> I<elem_size>
SET is triop (I64", I8", I<elem_size>) -> I64 */
/* Note: the arm back-end handles only constant second argument */
"GetElem8x8", "GetElem16x4", "GetElem32x2",
"SetElem8x8", "SetElem16x4", "SetElem32x2",
/* DUPLICATING -- copy value to all lanes */
"Dup8x8", "Dup16x4", "Dup32x2",
/* EXTRACT -- copy 8-arg3 highest bytes from arg1 to 8-arg3 lowest bytes
of result and arg3 lowest bytes of arg2 to arg3 highest bytes of
result.
It is a triop: (I64", I64", I8) -> I64 */
/* Note: the arm back-end handles only constant third argumnet. */
"Extract64",
/* REVERSE the order of elements in each Half-words, Words,
Double-words */
/* Examples:
Reverse16_8x8([a,b,c,d,e,f,g,h]) = [b,a,d,c,f,e,h,g]
Reverse32_8x8([a,b,c,d,e,f,g,h]) = [d,c,b,a,h,g,f,e]
Reverse64_8x8([a,b,c,d,e,f,g,h]) = [h,g,f,e,d,c,b,a] */
"Reverse16_8x8",
"Reverse32_8x8", "Reverse32_16x4",
"Reverse64_8x8", "Reverse64_16x4", "Reverse64_32x2",
/* PERMUTING -- copy src bytes to dst,
as indexed by control vector bytes:
for i in 0 .. 7 . result[i] = argL[ argR[i] ]
argR[i] values may only be in the range 0 .. 7, else behaviour
is undefined. */
"Perm8x8",
/* MISC CONVERSION -- get high bits of each byte lane, a la
x86/amd64 pmovmskb */
"GetMSBs8x8", /* I64 -> I8 */
/* Vector Reciprocal Estimate and Vector Reciprocal Square Root Estimate
See floating-point equiwalents for details. */
"Recip32x2", "Rsqrte32x2",
/* ------------------ Decimal Floating Point ------------------ */
/* ARITHMETIC INSTRUCTIONS 64-bit
----------------------------------
IRRoundingMode(I32) X D64 X D64 -> D64
*/
"AddD64", "SubD64", "MulD64", "DivD64",
/* ARITHMETIC INSTRUCTIONS 128-bit
----------------------------------
IRRoundingMode(I32) X D128 X D128 -> D128
*/
"AddD128", "SubD128", "MulD128", "DivD128",
/* SHIFT SIGNIFICAND INSTRUCTIONS
* The DFP significand is shifted by the number of digits specified
* by the U8 operand. Digits shifted out of the leftmost digit are
* lost. Zeros are supplied to the vacated positions on the right.
* The sign of the result is the same as the sign of the original
* operand.
*
* D64 x U8 -> D64 left shift and right shift respectively */
"ShlD64", "ShrD64",
/* D128 x U8 -> D128 left shift and right shift respectively */
"ShlD128", "ShrD128",
/* FORMAT CONVERSION INSTRUCTIONS
* D32 -> D64
*/
"D32toD64",
/* D64 -> D128 */
"D64toD128",
/* I32S -> D128 */
"I32StoD128",
/* I32U -> D128 */
"I32UtoD128",
/* I64S -> D128 */
"I64StoD128",
/* I64U -> D128 */
"I64UtoD128",
/* IRRoundingMode(I32) x D64 -> D32 */
"D64toD32",
/* IRRoundingMode(I32) x D128 -> D64 */
"D128toD64",
/* I32S -> D64 */
"I32StoD64",
/* I32U -> D64 */
"I32UtoD64",
/* IRRoundingMode(I32) x I64 -> D64 */
"I64StoD64",
/* IRRoundingMode(I32) x I64 -> D64 */
"I64UtoD64",
/* IRRoundingMode(I32) x D64 -> I32 */
"D64toI32S",
/* IRRoundingMode(I32) x D64 -> I32 */
"D64toI32U",
/* IRRoundingMode(I32) x D64 -> I64 */
"D64toI64S",
/* IRRoundingMode(I32) x D64 -> I64 */
"D64toI64U",
/* IRRoundingMode(I32) x D128 -> I32 */
"D128toI32S",
/* IRRoundingMode(I32) x D128 -> I32 */
"D128toI32U",
/* IRRoundingMode(I32) x D128 -> I64 */
"D128toI64S",
/* IRRoundingMode(I32) x D128 -> I64 */
"D128toI64U",
/* IRRoundingMode(I32) x F32 -> D32 */
"F32toD32",
/* IRRoundingMode(I32) x F32 -> D64 */
"F32toD64",
/* IRRoundingMode(I32) x F32 -> D128 */
"F32toD128",
/* IRRoundingMode(I32) x F64 -> D32 */
"F64toD32",
/* IRRoundingMode(I32) x F64 -> D64 */
"F64toD64",
/* IRRoundingMode(I32) x F64 -> D128 */
"F64toD128",
/* IRRoundingMode(I32) x F128 -> D32 */
"F128toD32",
/* IRRoundingMode(I32) x F128 -> D64 */
"F128toD64",
/* IRRoundingMode(I32) x F128 -> D128 */
"F128toD128",
/* IRRoundingMode(I32) x D32 -> F32 */
"D32toF32",
/* IRRoundingMode(I32) x D32 -> F64 */
"D32toF64",
/* IRRoundingMode(I32) x D32 -> F128 */
"D32toF128",
/* IRRoundingMode(I32) x D64 -> F32 */
"D64toF32",
/* IRRoundingMode(I32) x D64 -> F64 */
"D64toF64",
/* IRRoundingMode(I32) x D64 -> F128 */
"D64toF128",
/* IRRoundingMode(I32) x D128 -> F32 */
"D128toF32",
/* IRRoundingMode(I32) x D128 -> F64 */
"D128toF64",
/* IRRoundingMode(I32) x D128 -> F128 */
"D128toF128",
/* ROUNDING INSTRUCTIONS
* IRRoundingMode(I32) x D64 -> D64
* The D64 operand, if a finite number, it is rounded to a
* floating point integer value, i.e. no fractional part.
*/
"RoundD64toInt",
/* IRRoundingMode(I32) x D128 -> D128 */
"RoundD128toInt",
/* COMPARE INSTRUCTIONS
* D64 x D64 -> IRCmpD64Result(I32) */
"CmpD64",
/* D128 x D128 -> IRCmpD128Result(I32) */
"CmpD128",
/* COMPARE BIASED EXPONENET INSTRUCTIONS
* D64 x D64 -> IRCmpD64Result(I32) */
"CmpExpD64",
/* D128 x D128 -> IRCmpD128Result(I32) */
"CmpExpD128",
/* QUANTIZE AND ROUND INSTRUCTIONS
* The source operand is converted and rounded to the form with the
* immediate exponent specified by the rounding and exponent parameter.
*
* The second operand is converted and rounded to the form
* of the first operand's exponent and the rounded based on the specified
* rounding mode parameter.
*
* IRRoundingMode(I32) x D64 x D64-> D64 */
"QuantizeD64",
/* IRRoundingMode(I32) x D128 x D128 -> D128 */
"QuantizeD128",
/* IRRoundingMode(I32) x I8 x D64 -> D64
* The Decimal Floating point operand is rounded to the requested
* significance given by the I8 operand as specified by the rounding
* mode.
*/
"SignificanceRoundD64",
/* IRRoundingMode(I32) x I8 x D128 -> D128 */
"SignificanceRoundD128",
/* EXTRACT AND INSERT INSTRUCTIONS
* D64 -> I64
* The exponent of the D32 or D64 operand is extracted. The
* extracted exponent is converted to a 64-bit signed binary integer.
*/
"ExtractExpD64",
/* D128 -> I64 */
"ExtractExpD128",
/* D64 -> I64
* The number of significand digits of the D64 operand is extracted.
* The number is stored as a 64-bit signed binary integer.
*/
"ExtractSigD64",
/* D128 -> I64 */
"ExtractSigD128",
/* I64 x D64 -> D64
* The exponent is specified by the first I64 operand the signed
* significand is given by the second I64 value. The result is a D64
* value consisting of the specified significand and exponent whose
* sign is that of the specified significand.
*/
"InsertExpD64",
/* I64 x D128 -> D128 */
"InsertExpD128",
/* Support for 128-bit DFP type */
"D64HLtoD128", "D128HItoD64", "D128LOtoD64",
/* I64 -> I64
* Convert 50-bit densely packed BCD string to 60 bit BCD string
*/
"DPBtoBCD",
/* I64 -> I64
* Convert 60 bit BCD string to 50-bit densely packed BCD string
*/
"BCDtoDPB",
/* BCD arithmetic instructions, (V128", V128) -> V128
* The BCD format is the same as that used in the BCD<->DPB conversion
* routines, except using 124 digits (vs 60) plus the trailing 4-bit signed code.
* */
"BCDAdd", "BCDSub",
/* Conversion I64 -> D64 */
"ReinterpI64asD64",
/* Conversion D64 -> I64 */
"ReinterpD64asI64",
/* ------------------ 128-bit SIMD FP. ------------------ */
/* --- 32x4 vector FP --- */
/* binary */
"Add32Fx4", "Sub32Fx4", "Mul32Fx4", "Div32Fx4",
"Max32Fx4", "Min32Fx4",
"Add32Fx2", "Sub32Fx2",
/* Note: For the following compares, the ppc and arm front-ends assume a
nan in a lane of either argument returns zero for that lane. */
"CmpEQ32Fx4", "CmpLT32Fx4", "CmpLE32Fx4", "CmpUN32Fx4",
"CmpGT32Fx4", "CmpGE32Fx4",
/* Vector Absolute */
"Abs32Fx4",
/* Pairwise Max and Min. See integer pairwise operations for details. */
"PwMax32Fx4", "PwMin32Fx4",
/* unary */
"Sqrt32Fx4", "RSqrt32Fx4",
"Neg32Fx4",
/* Vector Reciprocal Estimate finds an approximate reciprocal of each
element in the operand vector, and places the results in the destination
vector. */
"Recip32Fx4",
/* Vector Reciprocal Step computes (2.0 - arg1 * arg2).
Note, that if one of the arguments is zero and another one is infinity
of arbitrary sign the result of the operation is 2.0. */
"Recps32Fx4",
/* Vector Reciprocal Square Root Estimate finds an approximate reciprocal
square root of each element in the operand vector. */
"Rsqrte32Fx4",
/* Vector Reciprocal Square Root Step computes (3.0 - arg1 * arg2) / 2.0.
Note, that of one of the arguments is zero and another one is infiinty
of arbitrary sign the result of the operation is 1.5. */
"Rsqrts32Fx4",
/* --- Int to/from FP conversion --- */
/* Unlike the standard fp conversions, these irops take no
rounding mode argument. Instead the irop trailers _R{M,P,N",Z}
indicate the mode: {-inf, +inf, nearest, zero} respectively. */
"I32UtoFx4", "I32StoFx4", /* I32x4 -> F32x4 */
"FtoI32Ux4_RZ", "FtoI32Sx4_RZ", /* F32x4 -> I32x4 */
"QFtoI32Ux4_RZ", "QFtoI32Sx4_RZ", /* F32x4 -> I32x4 (with saturation) */
"RoundF32x4_RM", "RoundF32x4_RP", /* round to fp integer */
"RoundF32x4_RN", "RoundF32x4_RZ", /* round to fp integer */
/* Fixed32 format is floating-point number with fixed number of fraction
bits. The number of fraction bits is passed as a second argument of
type I8. */
"F32ToFixed32Ux4_RZ", "F32ToFixed32Sx4_RZ", /* fp -> fixed-point */
"Fixed32UToF32x4_RN", "Fixed32SToF32x4_RN", /* fixed-point -> fp */
/* --- Single to/from half conversion --- */
/* FIXME: what kind of rounding in F32x4 -> F16x4 case? */
"F32toF16x4", "F16toF32x4", /* F32x4 <-> F16x4 */
/* --- 32x4 lowest-lane-only scalar FP --- */
/* In binary cases, upper 3/4 is copied from first operand. In
unary cases, upper 3/4 is copied from the operand. */
/* binary */
"Add32F0x4", "Sub32F0x4", "Mul32F0x4", "Div32F0x4",
"Max32F0x4", "Min32F0x4",
"CmpEQ32F0x4", "CmpLT32F0x4", "CmpLE32F0x4", "CmpUN32F0x4",
/* unary */
"Recip32F0x4", "Sqrt32F0x4", "RSqrt32F0x4",
/* --- 64x2 vector FP --- */
/* binary */
"Add64Fx2", "Sub64Fx2", "Mul64Fx2", "Div64Fx2",
"Max64Fx2", "Min64Fx2",
"CmpEQ64Fx2", "CmpLT64Fx2", "CmpLE64Fx2", "CmpUN64Fx2",
/* unary */
"Recip64Fx2", "Sqrt64Fx2", "RSqrt64Fx2",
/* --- 64x2 lowest-lane-only scalar FP --- */
/* In binary cases, upper half is copied from first operand. In
unary cases, upper half is copied from the operand. */
/* binary */
"Add64F0x2", "Sub64F0x2", "Mul64F0x2", "Div64F0x2",
"Max64F0x2", "Min64F0x2",
"CmpEQ64F0x2", "CmpLT64F0x2", "CmpLE64F0x2", "CmpUN64F0x2",
/* unary */
"Recip64F0x2", "Sqrt64F0x2", "RSqrt64F0x2",
/* --- pack / unpack --- */
/* 64 <-> 128 bit vector */
"V128to64", // :: V128 -> I64", low half
"V128HIto64", // :: V128 -> I64", high half
"64HLtoV128", // :: (I64",I64) -> V128
"64UtoV128",
"SetV128lo64",
/* 32 <-> 128 bit vector */
"32UtoV128",
"V128to32", // :: V128 -> I32", lowest lane
"SetV128lo32", // :: (V128",I32) -> V128
/* ------------------ 128-bit SIMD Integer. ------------------ */
/* BITWISE OPS */
"NotV128",